linux-old/drivers/sound/swarm_cs4297a.c
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   1/*******************************************************************************
   2*
   3*      "swarm_cs4297a.c" --  Cirrus Logic-Crystal CS4297a linux audio driver.
   4*
   5*      Copyright (C) 2001  Broadcom Corporation.
   6*      Copyright (C) 2000,2001  Cirrus Logic Corp.  
   7*            -- adapted from drivers by Thomas Sailer, 
   8*            -- but don't bug him; Problems should go to:
   9*            -- tom woller (twoller@crystal.cirrus.com) or
  10*               (audio@crystal.cirrus.com).
  11*            -- adapted from cs4281 PCI driver for cs4297a on
  12*               BCM1250 Synchronous Serial interface
  13*               (Kip Walker, Broadcom Corp.)
  14*      Copyright (C) 2004  Maciej W. Rozycki
  15*
  16*      This program is free software; you can redistribute it and/or modify
  17*      it under the terms of the GNU General Public License as published by
  18*      the Free Software Foundation; either version 2 of the License, or
  19*      (at your option) any later version.
  20*
  21*      This program is distributed in the hope that it will be useful,
  22*      but WITHOUT ANY WARRANTY; without even the implied warranty of
  23*      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  24*      GNU General Public License for more details.
  25*
  26*      You should have received a copy of the GNU General Public License
  27*      along with this program; if not, write to the Free Software
  28*      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  29*
  30* Module command line parameters:
  31*   none
  32*
  33*  Supported devices:
  34*  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  35*  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  36*  /dev/midi   simple MIDI UART interface, no ioctl
  37*
  38* Modification History
  39* 08/20/00 trw - silence and no stopping DAC until release
  40* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  41* 09/18/00 trw - added 16bit only record with conversion 
  42* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous 
  43*                capture/playback rates)
  44* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin  
  45*                libOSSm.so)
  46* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  47* 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  48* 11/10/00 bkz - added __devinit to cs4297a_hw_init()
  49* 11/10/00 trw - fixed SMP and capture spinlock hang.
  50* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  51* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  52* 12/08/00 trw - added PM support. 
  53* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8 
  54*                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  55* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  56* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use 
  57*                defaultorder-100 as power of 2 for the buffer size. example:
  58*                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  59*
  60*******************************************************************************/
  61
  62#include <linux/list.h>
  63#include <linux/version.h>
  64#include <linux/module.h>
  65#include <linux/string.h>
  66#include <linux/ioport.h>
  67#include <linux/sched.h>
  68#include <linux/delay.h>
  69#include <linux/sound.h>
  70#include <linux/slab.h>
  71#include <linux/soundcard.h>
  72#include <linux/ac97_codec.h>
  73#include <linux/pci.h>
  74#include <linux/bitops.h>
  75#include <linux/init.h>
  76#include <linux/poll.h>
  77#include <linux/smp_lock.h>
  78#include <linux/wrapper.h>
  79
  80#include <asm/byteorder.h>
  81#include <asm/dma.h>
  82#include <asm/hardirq.h>
  83#include <asm/io.h>
  84#include <asm/uaccess.h>
  85
  86#include <asm/sibyte/sb1250_regs.h>
  87#include <asm/sibyte/sb1250_int.h>
  88#include <asm/sibyte/sb1250_dma.h>
  89#include <asm/sibyte/sb1250_scd.h>
  90#include <asm/sibyte/sb1250_syncser.h>
  91#include <asm/sibyte/sb1250_mac.h>
  92#include <asm/sibyte/sb1250.h>
  93#include <asm/sibyte/64bit.h>
  94
  95struct cs4297a_state;
  96EXPORT_NO_SYMBOLS;
  97
  98static void stop_dac(struct cs4297a_state *s);
  99static void stop_adc(struct cs4297a_state *s);
 100static void start_dac(struct cs4297a_state *s);
 101static void start_adc(struct cs4297a_state *s);
 102#undef OSS_DOCUMENTED_MIXER_SEMANTICS
 103
 104// --------------------------------------------------------------------- 
 105
 106#define CS4297a_MAGIC           0xf00beef1
 107
 108// buffer order determines the size of the dma buffer for the driver.
 109// under Linux, a smaller buffer allows more responsiveness from many of the 
 110// applications (e.g. games).  A larger buffer allows some of the apps (esound) 
 111// to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 112// rather than 64k as some of the games work more responsively.
 113// log base 2( buff sz = 32k).
 114
 115//static unsigned long defaultorder = 3;
 116//MODULE_PARM(defaultorder, "i");
 117
 118//
 119// Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 120//
 121#define CSDEBUG 0
 122#if CSDEBUG
 123#define CSDEBUG_INTERFACE 1
 124#else
 125#undef CSDEBUG_INTERFACE
 126#endif
 127//
 128// cs_debugmask areas
 129//
 130#define CS_INIT         0x00000001      // initialization and probe functions
 131#define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 132#define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 133#define CS_FUNCTION     0x00000008      // enter/leave functions
 134#define CS_WAVE_WRITE   0x00000010      // write information for wave
 135#define CS_WAVE_READ    0x00000020      // read information for wave
 136#define CS_AC97         0x00000040      // AC97 register access
 137#define CS_DESCR        0x00000080      // descriptor management
 138#define CS_OPEN         0x00000400      // all open functions in the driver
 139#define CS_RELEASE      0x00000800      // all release functions in the driver
 140#define CS_PARMS        0x00001000      // functional and operational parameters
 141#define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 142#define CS_TMP          0x10000000      // tmp debug mask bit
 143
 144//
 145// CSDEBUG is usual mode is set to 1, then use the
 146// cs_debuglevel and cs_debugmask to turn on or off debugging.
 147// Debug level of 1 has been defined to be kernel errors and info
 148// that should be printed on any released driver.
 149//
 150#if CSDEBUG
 151#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 152#else
 153#define CS_DBGOUT(mask,level,x)
 154#endif
 155
 156#if CSDEBUG
 157static unsigned long cs_debuglevel = 4; // levels range from 1-9
 158static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/;
 159MODULE_PARM(cs_debuglevel, "i");
 160MODULE_PARM(cs_debugmask, "i");
 161#endif
 162#define CS_TRUE         1
 163#define CS_FALSE        0
 164
 165#define CS_TYPE_ADC 0
 166#define CS_TYPE_DAC 1
 167
 168#define SER_BASE    (A_SER_BASE_1 + KSEG1)
 169#define SS_CSR(t)   (SER_BASE+t)
 170#define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8))
 171#define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8))
 172
 173#define FRAME_BYTES            32
 174#define FRAME_SAMPLE_BYTES      4
 175
 176/* Should this be variable? */
 177#define SAMPLE_BUF_SIZE        (16*1024)
 178#define SAMPLE_FRAME_COUNT     (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES)
 179/* The driver can explode/shrink the frames to/from a smaller sample
 180   buffer */
 181#define DMA_BLOAT_FACTOR       1
 182#define DMA_DESCR              (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR)
 183#define DMA_BUF_SIZE           (DMA_DESCR * FRAME_BYTES)
 184
 185/* Use the maxmium count (255 == 5.1 ms between interrupts) */
 186#define DMA_INT_CNT            ((1 << S_DMA_INT_PKTCNT) - 1)
 187
 188/* Figure this out: how many TX DMAs ahead to schedule a reg access */
 189#define REG_LATENCY            150
 190
 191#define FRAME_TX_US             20
 192
 193#define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz)
 194
 195#ifdef CONFIG_SIBYTE_SB1250_DUART       
 196extern char sb1250_duart_present[];
 197#endif
 198
 199static const char invalid_magic[] =
 200    KERN_CRIT "cs4297a: invalid magic value\n";
 201
 202#define VALIDATE_STATE(s)                          \
 203({                                                 \
 204        if (!(s) || (s)->magic != CS4297a_MAGIC) { \
 205                printk(invalid_magic);             \
 206                return -ENXIO;                     \
 207        }                                          \
 208})
 209
 210struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs };
 211
 212typedef struct serdma_descr_s {
 213        u64 descr_a;
 214        u64 descr_b;
 215} serdma_descr_t;
 216
 217typedef unsigned long paddr_t;
 218
 219typedef struct serdma_s {
 220        unsigned         ringsz;
 221        serdma_descr_t  *descrtab;
 222        serdma_descr_t  *descrtab_end;
 223        paddr_t          descrtab_phys;
 224        
 225        serdma_descr_t  *descr_add;
 226        serdma_descr_t  *descr_rem;
 227        
 228        u64  *dma_buf;           // buffer for DMA contents (frames)
 229        paddr_t          dma_buf_phys;
 230        u16  *sample_buf;               // tmp buffer for sample conversions
 231        u16  *sb_swptr;
 232        u16  *sb_hwptr;
 233        u16  *sb_end;
 234
 235        dma_addr_t dmaaddr;
 236//        unsigned buforder;    // Log base 2 of 'dma_buf' size in bytes..
 237        unsigned numfrag;       // # of 'fragments' in the buffer.
 238        unsigned fragshift;     // Log base 2 of fragment size.
 239        unsigned hwptr, swptr;
 240        unsigned total_bytes;   // # bytes process since open.
 241        unsigned blocks;        // last returned blocks value GETOPTR
 242        unsigned wakeup;        // interrupt occurred on block 
 243        int count;
 244        unsigned underrun;      // underrun flag
 245        unsigned error; // over/underrun 
 246        wait_queue_head_t wait;
 247        wait_queue_head_t reg_wait;
 248        // redundant, but makes calculations easier 
 249        unsigned fragsize;      // 2**fragshift..
 250        unsigned sbufsz;        // 2**buforder.
 251        unsigned fragsamples;
 252        // OSS stuff 
 253        unsigned mapped:1;      // Buffer mapped in cs4297a_mmap()?
 254        unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 255        unsigned endcleared:1;
 256        unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 257        unsigned ossfragshift;
 258        int ossmaxfrags;
 259        unsigned subdivision;
 260} serdma_t;
 261
 262struct cs4297a_state {
 263        // magic 
 264        unsigned int magic;
 265
 266        struct list_head list;
 267
 268        // soundcore stuff 
 269        int dev_audio;
 270        int dev_mixer;
 271
 272        // hardware resources 
 273        unsigned int irq;
 274
 275        struct {
 276                unsigned int rx_ovrrn; /* FIFO */
 277                unsigned int rx_overflow; /* staging buffer */
 278                unsigned int tx_underrun;
 279                unsigned int rx_bad;
 280                unsigned int rx_good;
 281        } stats;
 282
 283        // mixer registers 
 284        struct {
 285                unsigned short vol[10];
 286                unsigned int recsrc;
 287                unsigned int modcnt;
 288                unsigned short micpreamp;
 289        } mix;
 290
 291        // wave stuff   
 292        struct properties {
 293                unsigned fmt;
 294                unsigned fmt_original;  // original requested format
 295                unsigned channels;
 296                unsigned rate;
 297        } prop_dac, prop_adc;
 298        unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 299        unsigned ena;
 300        spinlock_t lock;
 301        struct semaphore open_sem;
 302        struct semaphore open_sem_adc;
 303        struct semaphore open_sem_dac;
 304        mode_t open_mode;
 305        wait_queue_head_t open_wait;
 306        wait_queue_head_t open_wait_adc;
 307        wait_queue_head_t open_wait_dac;
 308
 309        dma_addr_t dmaaddr_sample_buf;
 310        unsigned buforder_sample_buf;   // Log base 2 of 'dma_buf' size in bytes..
 311
 312        serdma_t dma_dac, dma_adc;
 313
 314        volatile u16 read_value;
 315        volatile u16 read_reg;
 316        volatile u64 reg_request;
 317};
 318
 319#if 1
 320#define prog_codec(a,b)
 321#define dealloc_dmabuf(a,b);
 322#endif
 323
 324static int prog_dmabuf_adc(struct cs4297a_state *s)
 325{
 326        s->dma_adc.ready = 1;
 327        return 0;
 328}
 329
 330
 331static int prog_dmabuf_dac(struct cs4297a_state *s)
 332{
 333        s->dma_dac.ready = 1;
 334        return 0;
 335}
 336
 337static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
 338                          unsigned len, unsigned char c)
 339{
 340        if (bptr + len > bsize) {
 341                unsigned x = bsize - bptr;
 342                memset(((char *) buf) + bptr, c, x);
 343                bptr = 0;
 344                len -= x;
 345        }
 346        CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
 347                "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n",
 348                        (unsigned)c, (unsigned)((char *) buf) + bptr, len));
 349        memset(((char *) buf) + bptr, c, len);
 350}
 351
 352#if CSDEBUG
 353
 354// DEBUG ROUTINES
 355
 356#define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 357#define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 358#define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 359#define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 360
 361static void cs_printioctl(unsigned int x)
 362{
 363        unsigned int i;
 364        unsigned char vidx;
 365        // Index of mixtable1[] member is Device ID 
 366        // and must be <= SOUND_MIXER_NRDEVICES.
 367        // Value of array member is index into s->mix.vol[]
 368        static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 369                [SOUND_MIXER_PCM] = 1,  // voice 
 370                [SOUND_MIXER_LINE1] = 2,        // AUX
 371                [SOUND_MIXER_CD] = 3,   // CD 
 372                [SOUND_MIXER_LINE] = 4, // Line 
 373                [SOUND_MIXER_SYNTH] = 5,        // FM
 374                [SOUND_MIXER_MIC] = 6,  // Mic 
 375                [SOUND_MIXER_SPEAKER] = 7,      // Speaker 
 376                [SOUND_MIXER_RECLEV] = 8,       // Recording level 
 377                [SOUND_MIXER_VOLUME] = 9        // Master Volume 
 378        };
 379
 380        switch (x) {
 381        case SOUND_MIXER_CS_GETDBGMASK:
 382                CS_DBGOUT(CS_IOCTL, 4,
 383                          printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 384                break;
 385        case SOUND_MIXER_CS_GETDBGLEVEL:
 386                CS_DBGOUT(CS_IOCTL, 4,
 387                          printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 388                break;
 389        case SOUND_MIXER_CS_SETDBGMASK:
 390                CS_DBGOUT(CS_IOCTL, 4,
 391                          printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 392                break;
 393        case SOUND_MIXER_CS_SETDBGLEVEL:
 394                CS_DBGOUT(CS_IOCTL, 4,
 395                          printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 396                break;
 397        case OSS_GETVERSION:
 398                CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 399                break;
 400        case SNDCTL_DSP_SYNC:
 401                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 402                break;
 403        case SNDCTL_DSP_SETDUPLEX:
 404                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 405                break;
 406        case SNDCTL_DSP_GETCAPS:
 407                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 408                break;
 409        case SNDCTL_DSP_RESET:
 410                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 411                break;
 412        case SNDCTL_DSP_SPEED:
 413                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 414                break;
 415        case SNDCTL_DSP_STEREO:
 416                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 417                break;
 418        case SNDCTL_DSP_CHANNELS:
 419                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 420                break;
 421        case SNDCTL_DSP_GETFMTS:
 422                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 423                break;
 424        case SNDCTL_DSP_SETFMT:
 425                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 426                break;
 427        case SNDCTL_DSP_POST:
 428                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 429                break;
 430        case SNDCTL_DSP_GETTRIGGER:
 431                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 432                break;
 433        case SNDCTL_DSP_SETTRIGGER:
 434                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 435                break;
 436        case SNDCTL_DSP_GETOSPACE:
 437                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 438                break;
 439        case SNDCTL_DSP_GETISPACE:
 440                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 441                break;
 442        case SNDCTL_DSP_NONBLOCK:
 443                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 444                break;
 445        case SNDCTL_DSP_GETODELAY:
 446                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 447                break;
 448        case SNDCTL_DSP_GETIPTR:
 449                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 450                break;
 451        case SNDCTL_DSP_GETOPTR:
 452                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 453                break;
 454        case SNDCTL_DSP_GETBLKSIZE:
 455                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 456                break;
 457        case SNDCTL_DSP_SETFRAGMENT:
 458                CS_DBGOUT(CS_IOCTL, 4,
 459                          printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 460                break;
 461        case SNDCTL_DSP_SUBDIVIDE:
 462                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 463                break;
 464        case SOUND_PCM_READ_RATE:
 465                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 466                break;
 467        case SOUND_PCM_READ_CHANNELS:
 468                CS_DBGOUT(CS_IOCTL, 4,
 469                          printk("SOUND_PCM_READ_CHANNELS:\n"));
 470                break;
 471        case SOUND_PCM_READ_BITS:
 472                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 473                break;
 474        case SOUND_PCM_WRITE_FILTER:
 475                CS_DBGOUT(CS_IOCTL, 4,
 476                          printk("SOUND_PCM_WRITE_FILTER:\n"));
 477                break;
 478        case SNDCTL_DSP_SETSYNCRO:
 479                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 480                break;
 481        case SOUND_PCM_READ_FILTER:
 482                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 483                break;
 484        case SOUND_MIXER_PRIVATE1:
 485                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 486                break;
 487        case SOUND_MIXER_PRIVATE2:
 488                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 489                break;
 490        case SOUND_MIXER_PRIVATE3:
 491                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 492                break;
 493        case SOUND_MIXER_PRIVATE4:
 494                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 495                break;
 496        case SOUND_MIXER_PRIVATE5:
 497                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 498                break;
 499        case SOUND_MIXER_INFO:
 500                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 501                break;
 502        case SOUND_OLD_MIXER_INFO:
 503                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 504                break;
 505
 506        default:
 507                switch (_IOC_NR(x)) {
 508                case SOUND_MIXER_VOLUME:
 509                        CS_DBGOUT(CS_IOCTL, 4,
 510                                  printk("SOUND_MIXER_VOLUME:\n"));
 511                        break;
 512                case SOUND_MIXER_SPEAKER:
 513                        CS_DBGOUT(CS_IOCTL, 4,
 514                                  printk("SOUND_MIXER_SPEAKER:\n"));
 515                        break;
 516                case SOUND_MIXER_RECLEV:
 517                        CS_DBGOUT(CS_IOCTL, 4,
 518                                  printk("SOUND_MIXER_RECLEV:\n"));
 519                        break;
 520                case SOUND_MIXER_MIC:
 521                        CS_DBGOUT(CS_IOCTL, 4,
 522                                  printk("SOUND_MIXER_MIC:\n"));
 523                        break;
 524                case SOUND_MIXER_SYNTH:
 525                        CS_DBGOUT(CS_IOCTL, 4,
 526                                  printk("SOUND_MIXER_SYNTH:\n"));
 527                        break;
 528                case SOUND_MIXER_RECSRC:
 529                        CS_DBGOUT(CS_IOCTL, 4,
 530                                  printk("SOUND_MIXER_RECSRC:\n"));
 531                        break;
 532                case SOUND_MIXER_DEVMASK:
 533                        CS_DBGOUT(CS_IOCTL, 4,
 534                                  printk("SOUND_MIXER_DEVMASK:\n"));
 535                        break;
 536                case SOUND_MIXER_RECMASK:
 537                        CS_DBGOUT(CS_IOCTL, 4,
 538                                  printk("SOUND_MIXER_RECMASK:\n"));
 539                        break;
 540                case SOUND_MIXER_STEREODEVS:
 541                        CS_DBGOUT(CS_IOCTL, 4,
 542                                  printk("SOUND_MIXER_STEREODEVS:\n"));
 543                        break;
 544                case SOUND_MIXER_CAPS:
 545                        CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 546                        break;
 547                default:
 548                        i = _IOC_NR(x);
 549                        if (i >= SOUND_MIXER_NRDEVICES
 550                            || !(vidx = mixtable1[i])) {
 551                                CS_DBGOUT(CS_IOCTL, 4, printk
 552                                        ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 553                                                x, i));
 554                        } else {
 555                                CS_DBGOUT(CS_IOCTL, 4, printk
 556                                        ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 557                                                x, i));
 558                        }
 559                        break;
 560                }
 561        }
 562}
 563#endif
 564
 565
 566static int ser_init(struct cs4297a_state *s)
 567{
 568        int i;
 569
 570        CS_DBGOUT(CS_INIT, 2, 
 571                  printk(KERN_INFO "cs4297a: Setting up serial parameters\n"));
 572
 573        out64(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD));
 574
 575        out64(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE));
 576        out64(32, SS_CSR(R_SER_MINFRM_SZ));
 577        out64(32, SS_CSR(R_SER_MAXFRM_SZ));
 578
 579        out64(1, SS_CSR(R_SER_TX_RD_THRSH));
 580        out64(4, SS_CSR(R_SER_TX_WR_THRSH));
 581        out64(8, SS_CSR(R_SER_RX_RD_THRSH));
 582
 583        /* This looks good from experimentation */
 584        out64((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT |
 585               M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE),
 586              SS_CSR(R_SER_LINE_MODE));
 587
 588        /* This looks good from experimentation */
 589        out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 590              SS_TXTBL(0));
 591        out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 592              SS_TXTBL(1));
 593        out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 594              SS_TXTBL(2));
 595        out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE |
 596              M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3));
 597
 598        out64(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE,
 599              SS_RXTBL(0));
 600        out64(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 601              SS_RXTBL(1));
 602        out64(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE,
 603              SS_RXTBL(2));
 604        out64(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE |
 605              M_SYNCSER_SEQ_LAST, SS_RXTBL(3));
 606
 607        for (i=4; i<16; i++) {
 608                /* Just in case... */
 609                out64(M_SYNCSER_SEQ_LAST, SS_TXTBL(i));
 610                out64(M_SYNCSER_SEQ_LAST, SS_RXTBL(i));
 611        }
 612
 613        return 0;
 614}
 615
 616static int init_serdma(serdma_t *dma)
 617{
 618        CS_DBGOUT(CS_INIT, 2,
 619                  printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n",
 620                         DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE));
 621
 622        /* Descriptors */
 623        dma->ringsz = DMA_DESCR;
 624        dma->descrtab = kmalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL);
 625        if (!dma->descrtab) {
 626                printk(KERN_ERR "cs4297a: kmalloc descrtab failed\n");
 627                return -1;
 628        }
 629        memset(dma->descrtab, 0, dma->ringsz * sizeof(serdma_descr_t));
 630        dma->descrtab_end = dma->descrtab + dma->ringsz;
 631        /* XXX bloddy mess, use proper DMA API here ...  */
 632        dma->descrtab_phys = PHYSADDR((long)dma->descrtab);
 633        dma->descr_add = dma->descr_rem = dma->descrtab;
 634
 635        /* Frame buffer area */
 636        dma->dma_buf = kmalloc(DMA_BUF_SIZE, GFP_KERNEL);
 637        if (!dma->dma_buf) {
 638                printk(KERN_ERR "cs4297a: kmalloc dma_buf failed\n");
 639                kfree(dma->descrtab);
 640                return -1;
 641        }
 642        memset(dma->dma_buf, 0, DMA_BUF_SIZE);
 643        dma->dma_buf_phys = PHYSADDR((long)dma->dma_buf);
 644
 645        /* Samples buffer area */
 646        dma->sbufsz = SAMPLE_BUF_SIZE;
 647        dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL);
 648        if (!dma->sample_buf) {
 649                printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n");
 650                kfree(dma->descrtab);
 651                kfree(dma->dma_buf);
 652                return -1;
 653        }
 654        dma->sb_swptr = dma->sb_hwptr = dma->sample_buf;
 655        dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz);
 656        dma->fragsize = dma->sbufsz >> 1;
 657
 658        CS_DBGOUT(CS_INIT, 4, 
 659                  printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n",
 660                         (int)dma->descrtab, (int)dma->dma_buf, 
 661                         (int)dma->sample_buf));
 662
 663        return 0;
 664}
 665
 666static int dma_init(struct cs4297a_state *s)
 667{
 668        int i;
 669
 670        CS_DBGOUT(CS_INIT, 2, 
 671                  printk(KERN_INFO "cs4297a: Setting up DMA\n"));
 672
 673        if (init_serdma(&s->dma_adc) ||
 674            init_serdma(&s->dma_dac))
 675                return -1;
 676
 677        if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))||
 678            in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) {
 679                panic("DMA state corrupted?!");
 680        }
 681
 682        /* Initialize now - the descr/buffer pairings will never
 683           change... */
 684        for (i=0; i<DMA_DESCR; i++) {
 685                s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) | 
 686                        (s->dma_dac.dma_buf_phys + i*FRAME_BYTES);
 687                s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES);
 688                s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) |
 689                        (s->dma_adc.dma_buf_phys + i*FRAME_BYTES);
 690                s->dma_adc.descrtab[i].descr_b = 0;
 691        }
 692
 693        out64((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) |
 694               V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN),
 695              SS_CSR(R_SER_DMA_CONFIG0_RX));
 696        out64(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX));
 697        out64(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX));
 698
 699        out64(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX));
 700        out64(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX));
 701        out64(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX));
 702
 703        /* Prep the receive DMA descriptor ring */
 704        out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
 705
 706        out64(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE));
 707
 708        out64((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT),
 709              SS_CSR(R_SER_INT_MASK));
 710
 711        /* Enable the rx/tx; let the codec warm up to the sync and
 712           start sending good frames before the receive FIFO is
 713           enabled */
 714        out64(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 715        udelay(1000);
 716        out64(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD));
 717
 718        /* XXXKW is this magic? (the "1" part) */
 719        while ((in64(SS_CSR(R_SER_STATUS)) & 0xf1) != 1)
 720                ;
 721
 722        CS_DBGOUT(CS_INIT, 4, 
 723                  printk(KERN_INFO "cs4297a: status: %08x\n",
 724                         (unsigned int)(in64(SS_CSR(R_SER_STATUS)) & 0xffffffff)));
 725
 726        return 0;
 727}
 728
 729static int serdma_reg_access(struct cs4297a_state *s, u64 data)
 730{
 731        serdma_t *d = &s->dma_dac;
 732        u64 *data_p;
 733        unsigned swptr;
 734        int flags;
 735        serdma_descr_t *descr;
 736
 737        if (s->reg_request) {
 738                printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n");
 739                return -1;
 740        }
 741
 742        if (s->ena & FMODE_WRITE) {
 743                /* Since a writer has the DSP open, we have to mux the
 744                   request in */
 745                s->reg_request = data;
 746                interruptible_sleep_on(&s->dma_dac.reg_wait);
 747                /* XXXKW how can I deal with the starvation case where
 748                   the opener isn't writing? */
 749        } else {
 750                /* Be safe when changing ring pointers */
 751                spin_lock_irqsave(&s->lock, flags);
 752                if (d->hwptr != d->swptr) {
 753                        printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n",
 754                               d->hwptr, d->swptr);
 755                        spin_unlock_irqrestore(&s->lock, flags);
 756                        return -1;
 757                }
 758                swptr = d->swptr;
 759                d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz;
 760                spin_unlock_irqrestore(&s->lock, flags);
 761
 762                descr = &d->descrtab[swptr];
 763                data_p = &d->dma_buf[swptr * 4];
 764                *data_p = cpu_to_be64(data);
 765                out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
 766                CS_DBGOUT(CS_DESCR, 4,
 767                          printk(KERN_INFO "cs4297a: add_tx  %p (%x -> %x)\n",
 768                                 data_p, swptr, d->hwptr));
 769        }
 770
 771        CS_DBGOUT(CS_FUNCTION, 6,
 772                  printk(KERN_INFO "cs4297a: serdma_reg_access()-\n"));
 773        
 774        return 0;
 775}
 776
 777//****************************************************************************
 778// "cs4297a_read_ac97" -- Reads an AC97 register
 779//****************************************************************************
 780static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset,
 781                            u32 * value)
 782{
 783        CS_DBGOUT(CS_AC97, 1,
 784                  printk(KERN_INFO "cs4297a: read reg %2x\n", offset));
 785        if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40)))
 786                return -1;
 787
 788        interruptible_sleep_on(&s->dma_adc.reg_wait);
 789        *value = s->read_value;
 790        CS_DBGOUT(CS_AC97, 2,
 791                  printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value));
 792
 793        return 0;
 794}
 795
 796
 797//****************************************************************************
 798// "cs4297a_write_ac97()"-- writes an AC97 register
 799//****************************************************************************
 800static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset,
 801                             u32 value)
 802{
 803        CS_DBGOUT(CS_AC97, 1,
 804                  printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value));
 805        return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12)));
 806}
 807
 808static void stop_dac(struct cs4297a_state *s)
 809{
 810        unsigned long flags;
 811
 812        CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n"));
 813        spin_lock_irqsave(&s->lock, flags);
 814        s->ena &= ~FMODE_WRITE;
 815#if 0
 816        /* XXXKW what do I really want here?  My theory for now is
 817           that I just flip the "ena" bit, and the interrupt handler
 818           will stop processing the xmit channel */
 819        out64((s->ena & FMODE_READ) ? M_SYNCSER_DMA_RX_EN : 0,
 820              SS_CSR(R_SER_DMA_ENABLE));
 821#endif
 822
 823        spin_unlock_irqrestore(&s->lock, flags);
 824}
 825
 826
 827static void start_dac(struct cs4297a_state *s)
 828{
 829        unsigned long flags;
 830
 831        CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n"));
 832        spin_lock_irqsave(&s->lock, flags);
 833        if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
 834                                        (s->dma_dac.count > 0
 835                                        && s->dma_dac.ready))) {
 836                s->ena |= FMODE_WRITE;
 837                /* XXXKW what do I really want here?  My theory for
 838                   now is that I just flip the "ena" bit, and the
 839                   interrupt handler will start processing the xmit
 840                   channel */
 841
 842                CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
 843                        "cs4297a: start_dac(): start dma\n"));
 844
 845        }
 846        spin_unlock_irqrestore(&s->lock, flags);
 847        CS_DBGOUT(CS_FUNCTION, 3,
 848                  printk(KERN_INFO "cs4297a: start_dac()-\n"));
 849}
 850
 851
 852static void stop_adc(struct cs4297a_state *s)
 853{
 854        unsigned long flags;
 855
 856        CS_DBGOUT(CS_FUNCTION, 3,
 857                  printk(KERN_INFO "cs4297a: stop_adc()+\n"));
 858
 859        spin_lock_irqsave(&s->lock, flags);
 860        s->ena &= ~FMODE_READ;
 861
 862        if (s->conversion == 1) {
 863                s->conversion = 0;
 864                s->prop_adc.fmt = s->prop_adc.fmt_original;
 865        }
 866        /* Nothing to do really, I need to keep the DMA going
 867           XXXKW when do I get here, and is there more I should do? */
 868        spin_unlock_irqrestore(&s->lock, flags);
 869        CS_DBGOUT(CS_FUNCTION, 3,
 870                  printk(KERN_INFO "cs4297a: stop_adc()-\n"));
 871}
 872
 873
 874static void start_adc(struct cs4297a_state *s)
 875{
 876        unsigned long flags;
 877
 878        CS_DBGOUT(CS_FUNCTION, 2,
 879                  printk(KERN_INFO "cs4297a: start_adc()+\n"));
 880
 881        if (!(s->ena & FMODE_READ) &&
 882            (s->dma_adc.mapped || s->dma_adc.count <=
 883             (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize))
 884            && s->dma_adc.ready) {
 885                if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
 886                        // 
 887                        // now only use 16 bit capture, due to truncation issue
 888                        // in the chip, noticable distortion occurs.
 889                        // allocate buffer and then convert from 16 bit to 
 890                        // 8 bit for the user buffer.
 891                        //
 892                        s->prop_adc.fmt_original = s->prop_adc.fmt;
 893                        if (s->prop_adc.fmt & AFMT_S8) {
 894                                s->prop_adc.fmt &= ~AFMT_S8;
 895                                s->prop_adc.fmt |= AFMT_S16_LE;
 896                        }
 897                        if (s->prop_adc.fmt & AFMT_U8) {
 898                                s->prop_adc.fmt &= ~AFMT_U8;
 899                                s->prop_adc.fmt |= AFMT_U16_LE;
 900                        }
 901                        //
 902                        // prog_dmabuf_adc performs a stop_adc() but that is
 903                        // ok since we really haven't started the DMA yet.
 904                        //
 905                        prog_codec(s, CS_TYPE_ADC);
 906
 907                        prog_dmabuf_adc(s);
 908                        s->conversion = 1;
 909                }
 910                spin_lock_irqsave(&s->lock, flags);
 911                s->ena |= FMODE_READ;
 912                /* Nothing to do really, I am probably already
 913                   DMAing...  XXXKW when do I get here, and is there
 914                   more I should do? */
 915                spin_unlock_irqrestore(&s->lock, flags);
 916
 917                CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
 918                         "cs4297a: start_adc(): start adc\n"));
 919        }
 920        CS_DBGOUT(CS_FUNCTION, 2,
 921                  printk(KERN_INFO "cs4297a: start_adc()-\n"));
 922
 923}
 924
 925
 926// call with spinlock held! 
 927static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag)
 928{
 929        int good_diff, diff, diff2;
 930        u64 *data_p, data;
 931        u32 *s_ptr;
 932        unsigned hwptr;
 933        u32 status;
 934        serdma_t *d;
 935        serdma_descr_t *descr;
 936
 937        // update ADC pointer 
 938        status = intflag ? in64(SS_CSR(R_SER_STATUS)) : 0;
 939
 940        if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) {
 941                d = &s->dma_adc;
 942                hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
 943                                     d->descrtab_phys) / sizeof(serdma_descr_t));
 944
 945                if (s->ena & FMODE_READ) {
 946                        CS_DBGOUT(CS_FUNCTION, 2, 
 947                                  printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n",
 948                                         d->swptr, d->hwptr, hwptr, intflag));
 949                        /* Number of DMA buffers available for software: */
 950                        diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
 951                        d->hwptr = hwptr;
 952                        good_diff = 0;
 953                        s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]);
 954                        descr = &d->descrtab[d->swptr];
 955                        while (diff2--) {
 956                                u64 data = be64_to_cpu(*(u64 *)s_ptr);
 957                                u64 descr_a;
 958                                u16 left, right;
 959                                descr_a = descr->descr_a;
 960                                descr->descr_a &= ~M_DMA_SERRX_SOP;
 961                                if ((descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((long)s_ptr)) {
 962                                        printk(KERN_ERR "cs4297a: RX Bad address (read)\n");
 963                                }
 964                                if (((data & 0x9800000000000000) != 0x9800000000000000) ||
 965                                    (!(descr_a & M_DMA_SERRX_SOP)) ||
 966                                    (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
 967                                        s->stats.rx_bad++;
 968                                        printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n");
 969                                        continue;
 970                                }
 971                                s->stats.rx_good++;
 972                                if ((data >> 61) == 7) {
 973                                        s->read_value = (data >> 12) & 0xffff;
 974                                        s->read_reg = (data >> 40) & 0x7f;
 975                                        wake_up(&d->reg_wait);
 976                                }
 977                                if (d->count && (d->sb_hwptr == d->sb_swptr)) {
 978                                        s->stats.rx_overflow++;
 979                                        printk(KERN_DEBUG "cs4297a: RX overflow\n");
 980                                        continue;
 981                                }
 982                                good_diff++;
 983                                left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) |
 984                                       ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff);
 985                                right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff;
 986                                *d->sb_hwptr++ = cpu_to_be16(left);
 987                                *d->sb_hwptr++ = cpu_to_be16(right);
 988                                if (d->sb_hwptr == d->sb_end)
 989                                        d->sb_hwptr = d->sample_buf;
 990                                descr++;
 991                                if (descr == d->descrtab_end) {
 992                                        descr = d->descrtab;
 993                                        s_ptr = (u32 *)s->dma_adc.dma_buf;
 994                                } else {
 995                                        s_ptr += 8;
 996                                }
 997                        }
 998                        d->total_bytes += good_diff * FRAME_SAMPLE_BYTES;
 999                        d->count += good_diff * FRAME_SAMPLE_BYTES;
1000                        if (d->count > d->sbufsz) {
1001                                printk(KERN_ERR "cs4297a: bogus receive overflow!!\n");
1002                        }
1003                        d->swptr = (d->swptr + diff) % d->ringsz;
1004                        out64(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1005                        if (d->mapped) {
1006                                if (d->count >= (signed) d->fragsize)
1007                                        wake_up(&d->wait);
1008                        } else {
1009                                if (d->count > 0) {
1010                                        CS_DBGOUT(CS_WAVE_READ, 4,
1011                                                  printk(KERN_INFO
1012                                                         "cs4297a: update count -> %d\n", d->count));
1013                                        wake_up(&d->wait);
1014                                }
1015                        }
1016                } else {
1017                        /* Receive is going even if no one is
1018                           listening (for register accesses and to
1019                           avoid FIFO overrun) */
1020                        diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz;
1021                        if (!diff) {
1022                                printk(KERN_ERR "cs4297a: RX full or empty?\n");
1023                        }
1024                        
1025                        descr = &d->descrtab[d->swptr];
1026                        data_p = &d->dma_buf[d->swptr*4];
1027
1028                        /* Force this to happen at least once; I got
1029                           here because of an interrupt, so there must
1030                           be a buffer to process. */
1031                        do {
1032                                data = be64_to_cpu(*data_p);
1033                                if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != PHYSADDR((long)data_p)) {
1034                                        printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr,
1035                                               (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR),
1036                                               (long)PHYSADDR((long)data_p));
1037                                }
1038                                if (!(data & (1LL << 63)) ||
1039                                    !(descr->descr_a & M_DMA_SERRX_SOP) ||
1040                                    (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) {
1041                                        s->stats.rx_bad++;
1042                                        printk(KERN_DEBUG "cs4297a: RX Bad attributes\n");
1043                                } else {
1044                                        s->stats.rx_good++;
1045                                        if ((data >> 61) == 7) {
1046                                                s->read_value = (data >> 12) & 0xffff;
1047                                                s->read_reg = (data >> 40) & 0x7f;
1048                                                wake_up(&d->reg_wait);
1049                                        }
1050                                }
1051                                descr->descr_a &= ~M_DMA_SERRX_SOP;
1052                                descr++;
1053                                d->swptr++;
1054                                data_p += 4;
1055                                if (descr == d->descrtab_end) {
1056                                        descr = d->descrtab;
1057                                        d->swptr = 0;
1058                                        data_p = d->dma_buf;
1059                                }
1060                                out64(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
1061                        } while (--diff);
1062                        d->hwptr = hwptr;
1063
1064                        CS_DBGOUT(CS_DESCR, 6, 
1065                                  printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr));
1066                }
1067
1068                CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1069                        "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1070                                (unsigned)s, d->hwptr, 
1071                                d->total_bytes, d->count));
1072        }
1073
1074        /* XXXKW worry about s->reg_request -- there is a starvation
1075           case if s->ena has FMODE_WRITE on, but the client isn't
1076           doing writes */
1077
1078        // update DAC pointer 
1079        //
1080        // check for end of buffer, means that we are going to wait for another interrupt
1081        // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
1082        //
1083        if (s->ena & FMODE_WRITE) {
1084                serdma_t *d = &s->dma_dac;
1085                hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1086                                     d->descrtab_phys) / sizeof(serdma_descr_t));
1087                diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz;
1088                CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1089                                                   "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n",
1090                                                   d->hwptr, hwptr, d->swptr, diff, d->count));
1091                d->hwptr = hwptr;
1092                /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */
1093                d->total_bytes += diff * FRAME_SAMPLE_BYTES;
1094                if (d->mapped) {
1095                        d->count += diff * FRAME_SAMPLE_BYTES;
1096                        if (d->count >= d->fragsize) {
1097                                d->wakeup = 1;
1098                                wake_up(&d->wait);
1099                                if (d->count > d->sbufsz)
1100                                        d->count &= d->sbufsz - 1;
1101                        }
1102                } else {
1103                        d->count -= diff * FRAME_SAMPLE_BYTES;
1104                        if (d->count <= 0) {
1105                                //
1106                                // fill with silence, and do not shut down the DAC.
1107                                // Continue to play silence until the _release.
1108                                //
1109                                CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
1110                                        "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n",
1111                                                (unsigned)(s->prop_dac.fmt & 
1112                                                (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, 
1113                                                (unsigned)d->dma_buf, 
1114                                                d->ringsz));
1115                                memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES);
1116                                if (d->count < 0) {
1117                                        d->underrun = 1;
1118                                        s->stats.tx_underrun++;
1119                                        d->count = 0;
1120                                        CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
1121                                         "cs4297a: cs4297a_update_ptr(): underrun\n"));
1122                                }
1123                        } else if (d->count <=
1124                                   (signed) d->fragsize
1125                                   && !d->endcleared) {
1126                          /* XXXKW what is this for? */
1127                                clear_advance(d->dma_buf,
1128                                              d->sbufsz,
1129                                              d->swptr,
1130                                              d->fragsize,
1131                                              0);
1132                                d->endcleared = 1;
1133                        }
1134                        if ( (d->count <= (signed) d->sbufsz/2) || intflag)
1135                        {
1136                                CS_DBGOUT(CS_WAVE_WRITE, 4,
1137                                          printk(KERN_INFO
1138                                                 "cs4297a: update count -> %d\n", d->count));
1139                                wake_up(&d->wait);
1140                        }
1141                }
1142                CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
1143                        "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
1144                                (unsigned) s, d->hwptr, 
1145                                d->total_bytes, d->count));
1146        }
1147}
1148
1149static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd,
1150                       unsigned long arg)
1151{
1152        // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
1153        // Value of array member is recording source Device ID Mask.
1154        static const unsigned int mixer_src[8] = {
1155                SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
1156                SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
1157        };
1158
1159        // Index of mixtable1[] member is Device ID 
1160        // and must be <= SOUND_MIXER_NRDEVICES.
1161        // Value of array member is index into s->mix.vol[]
1162        static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
1163                [SOUND_MIXER_PCM] = 1,  // voice 
1164                [SOUND_MIXER_LINE1] = 2,        // AUX
1165                [SOUND_MIXER_CD] = 3,   // CD 
1166                [SOUND_MIXER_LINE] = 4, // Line 
1167                [SOUND_MIXER_SYNTH] = 5,        // FM
1168                [SOUND_MIXER_MIC] = 6,  // Mic 
1169                [SOUND_MIXER_SPEAKER] = 7,      // Speaker 
1170                [SOUND_MIXER_RECLEV] = 8,       // Recording level 
1171                [SOUND_MIXER_VOLUME] = 9        // Master Volume 
1172        };
1173
1174        static const unsigned mixreg[] = {
1175                AC97_PCMOUT_VOL,
1176                AC97_AUX_VOL,
1177                AC97_CD_VOL,
1178                AC97_LINEIN_VOL
1179        };
1180        unsigned char l, r, rl, rr, vidx;
1181        unsigned char attentbl[11] =
1182            { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
1183        unsigned temp1;
1184        int i, val;
1185
1186        VALIDATE_STATE(s);
1187        CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
1188                 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
1189                         (unsigned) s, cmd));
1190#if CSDEBUG
1191        cs_printioctl(cmd);
1192#endif
1193#if CSDEBUG_INTERFACE
1194
1195        if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
1196            (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
1197            (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
1198            (cmd == SOUND_MIXER_CS_SETDBGLEVEL))
1199        {
1200                switch (cmd) {
1201
1202                case SOUND_MIXER_CS_GETDBGMASK:
1203                        return put_user(cs_debugmask,
1204                                        (unsigned long *) arg);
1205
1206                case SOUND_MIXER_CS_GETDBGLEVEL:
1207                        return put_user(cs_debuglevel,
1208                                        (unsigned long *) arg);
1209
1210                case SOUND_MIXER_CS_SETDBGMASK:
1211                        if (get_user(val, (unsigned long *) arg))
1212                                return -EFAULT;
1213                        cs_debugmask = val;
1214                        return 0;
1215
1216                case SOUND_MIXER_CS_SETDBGLEVEL:
1217                        if (get_user(val, (unsigned long *) arg))
1218                                return -EFAULT;
1219                        cs_debuglevel = val;
1220                        return 0;
1221                default:
1222                        CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
1223                                "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n"));
1224                        return 0;
1225                }
1226        }
1227#endif
1228
1229        if (cmd == SOUND_MIXER_PRIVATE1) {
1230                return -EINVAL;
1231        }
1232        if (cmd == SOUND_MIXER_PRIVATE2) {
1233                // enable/disable/query spatializer 
1234                if (get_user(val, (int *) arg))
1235                        return -EFAULT;
1236                if (val != -1) {
1237                        temp1 = (val & 0x3f) >> 2;
1238                        cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1);
1239                        cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE,
1240                                         &temp1);
1241                        cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE,
1242                                          temp1 | 0x2000);
1243                }
1244                cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1);
1245                return put_user((temp1 << 2) | 3, (int *) arg);
1246        }
1247        if (cmd == SOUND_MIXER_INFO) {
1248                mixer_info info;
1249                strncpy(info.id, "CS4297a", sizeof(info.id));
1250                strncpy(info.name, "Crystal CS4297a", sizeof(info.name));
1251                info.modify_counter = s->mix.modcnt;
1252                if (copy_to_user((void *) arg, &info, sizeof(info)))
1253                        return -EFAULT;
1254                return 0;
1255        }
1256        if (cmd == SOUND_OLD_MIXER_INFO) {
1257                _old_mixer_info info;
1258                strncpy(info.id, "CS4297a", sizeof(info.id));
1259                strncpy(info.name, "Crystal CS4297a", sizeof(info.name));
1260                if (copy_to_user((void *) arg, &info, sizeof(info)))
1261                        return -EFAULT;
1262                return 0;
1263        }
1264        if (cmd == OSS_GETVERSION)
1265                return put_user(SOUND_VERSION, (int *) arg);
1266
1267        if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
1268                return -EINVAL;
1269
1270        // If ioctl has only the SIOC_READ bit(bit 31)
1271        // on, process the only-read commands. 
1272        if (_SIOC_DIR(cmd) == _SIOC_READ) {
1273                switch (_IOC_NR(cmd)) {
1274                case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source 
1275                        cs4297a_read_ac97(s, AC97_RECORD_SELECT,
1276                                         &temp1);
1277                        return put_user(mixer_src[temp1 & 7], (int *) arg);
1278
1279                case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device 
1280                        return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1281                                        SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1282                                        (int *) arg);
1283
1284                case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source 
1285                        return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME,
1286                                        (int *) arg);
1287
1288                case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo 
1289                        return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE |
1290                                        SOUND_MASK_VOLUME | SOUND_MASK_RECLEV,
1291                                        (int *) arg);
1292
1293                case SOUND_MIXER_CAPS:
1294                        return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
1295
1296                default:
1297                        i = _IOC_NR(cmd);
1298                        if (i >= SOUND_MIXER_NRDEVICES
1299                            || !(vidx = mixtable1[i]))
1300                                return -EINVAL;
1301                        return put_user(s->mix.vol[vidx - 1], (int *) arg);
1302                }
1303        }
1304        // If ioctl doesn't have both the SIOC_READ and 
1305        // the SIOC_WRITE bit set, return invalid.
1306        if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
1307                return -EINVAL;
1308
1309        // Increment the count of volume writes.
1310        s->mix.modcnt++;
1311
1312        // Isolate the command; it must be a write.
1313        switch (_IOC_NR(cmd)) {
1314
1315        case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source 
1316                if (get_user(val, (int *) arg))
1317                        return -EFAULT;
1318                i = hweight32(val);     // i = # bits on in val.
1319                if (i != 1)     // One & only 1 bit must be on.
1320                        return 0;
1321                for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
1322                        if (val == mixer_src[i]) {
1323                                temp1 = (i << 8) | i;
1324                                cs4297a_write_ac97(s,
1325                                                  AC97_RECORD_SELECT,
1326                                                  temp1);
1327                                return 0;
1328                        }
1329                }
1330                return 0;
1331
1332        case SOUND_MIXER_VOLUME:
1333                if (get_user(val, (int *) arg))
1334                        return -EFAULT;
1335                l = val & 0xff;
1336                if (l > 100)
1337                        l = 100;        // Max soundcard.h vol is 100.
1338                if (l < 6) {
1339                        rl = 63;
1340                        l = 0;
1341                } else
1342                        rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
1343
1344                r = (val >> 8) & 0xff;
1345                if (r > 100)
1346                        r = 100;        // Max right volume is 100, too
1347                if (r < 6) {
1348                        rr = 63;
1349                        r = 0;
1350                } else
1351                        rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
1352
1353                if ((rl > 60) && (rr > 60))     // If both l & r are 'low',          
1354                        temp1 = 0x8000; //  turn on the mute bit.
1355                else
1356                        temp1 = 0;
1357
1358                temp1 |= (rl << 8) | rr;
1359
1360                cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1);
1361                cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1);
1362
1363#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1364                s->mix.vol[8] = ((unsigned int) r << 8) | l;
1365#else
1366                s->mix.vol[8] = val;
1367#endif
1368                return put_user(s->mix.vol[8], (int *) arg);
1369
1370        case SOUND_MIXER_SPEAKER:
1371                if (get_user(val, (int *) arg))
1372                        return -EFAULT;
1373                l = val & 0xff;
1374                if (l > 100)
1375                        l = 100;
1376                if (l < 3) {
1377                        rl = 0;
1378                        l = 0;
1379                } else {
1380                        rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
1381                        l = (rl * 13 + 5) / 2;
1382                }
1383
1384                if (rl < 3) {
1385                        temp1 = 0x8000;
1386                        rl = 0;
1387                } else
1388                        temp1 = 0;
1389                rl = 15 - rl;   // Convert volume to attenuation.
1390                temp1 |= rl << 1;
1391                cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1);
1392
1393#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1394                s->mix.vol[6] = l << 8;
1395#else
1396                s->mix.vol[6] = val;
1397#endif
1398                return put_user(s->mix.vol[6], (int *) arg);
1399
1400        case SOUND_MIXER_RECLEV:
1401                if (get_user(val, (int *) arg))
1402                        return -EFAULT;
1403                l = val & 0xff;
1404                if (l > 100)
1405                        l = 100;
1406                r = (val >> 8) & 0xff;
1407                if (r > 100)
1408                        r = 100;
1409                rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
1410                rr = (r * 2 - 5) / 13;
1411                if (rl < 3 && rr < 3)
1412                        temp1 = 0x8000;
1413                else
1414                        temp1 = 0;
1415
1416                temp1 = temp1 | (rl << 8) | rr;
1417                cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1);
1418
1419#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1420                s->mix.vol[7] = ((unsigned int) r << 8) | l;
1421#else
1422                s->mix.vol[7] = val;
1423#endif
1424                return put_user(s->mix.vol[7], (int *) arg);
1425
1426        case SOUND_MIXER_MIC:
1427                if (get_user(val, (int *) arg))
1428                        return -EFAULT;
1429                l = val & 0xff;
1430                if (l > 100)
1431                        l = 100;
1432                if (l < 1) {
1433                        l = 0;
1434                        rl = 0;
1435                } else {
1436                        rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
1437                        l = (rl * 16 + 4) / 5;
1438                }
1439                cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1);
1440                temp1 &= 0x40;  // Isolate 20db gain bit.
1441                if (rl < 3) {
1442                        temp1 |= 0x8000;
1443                        rl = 0;
1444                }
1445                rl = 31 - rl;   // Convert volume to attenuation.
1446                temp1 |= rl;
1447                cs4297a_write_ac97(s, AC97_MIC_VOL, temp1);
1448
1449#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1450                s->mix.vol[5] = val << 8;
1451#else
1452                s->mix.vol[5] = val;
1453#endif
1454                return put_user(s->mix.vol[5], (int *) arg);
1455
1456
1457        case SOUND_MIXER_SYNTH:
1458                if (get_user(val, (int *) arg))
1459                        return -EFAULT;
1460                l = val & 0xff;
1461                if (l > 100)
1462                        l = 100;
1463                if (get_user(val, (int *) arg))
1464                        return -EFAULT;
1465                r = (val >> 8) & 0xff;
1466                if (r > 100)
1467                        r = 100;
1468                rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
1469                rr = (r * 2 - 11) / 3;
1470                if (rl < 3)     // If l is low, turn on
1471                        temp1 = 0x0080; //  the mute bit.
1472                else
1473                        temp1 = 0;
1474
1475                rl = 63 - rl;   // Convert vol to attenuation.
1476//              writel(temp1 | rl, s->pBA0 + FMLVC);
1477                if (rr < 3)     //  If rr is low, turn on
1478                        temp1 = 0x0080; //   the mute bit.
1479                else
1480                        temp1 = 0;
1481                rr = 63 - rr;   // Convert vol to attenuation.
1482//              writel(temp1 | rr, s->pBA0 + FMRVC);
1483
1484#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1485                s->mix.vol[4] = (r << 8) | l;
1486#else
1487                s->mix.vol[4] = val;
1488#endif
1489                return put_user(s->mix.vol[4], (int *) arg);
1490
1491
1492        default:
1493                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1494                        "cs4297a: mixer_ioctl(): default\n"));
1495
1496                i = _IOC_NR(cmd);
1497                if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
1498                        return -EINVAL;
1499                if (get_user(val, (int *) arg))
1500                        return -EFAULT;
1501                l = val & 0xff;
1502                if (l > 100)
1503                        l = 100;
1504                if (l < 1) {
1505                        l = 0;
1506                        rl = 31;
1507                } else
1508                        rl = (attentbl[(l * 10) / 100]) >> 1;
1509
1510                r = (val >> 8) & 0xff;
1511                if (r > 100)
1512                        r = 100;
1513                if (r < 1) {
1514                        r = 0;
1515                        rr = 31;
1516                } else
1517                        rr = (attentbl[(r * 10) / 100]) >> 1;
1518                if ((rl > 30) && (rr > 30))
1519                        temp1 = 0x8000;
1520                else
1521                        temp1 = 0;
1522                temp1 = temp1 | (rl << 8) | rr;
1523                cs4297a_write_ac97(s, mixreg[vidx - 1], temp1);
1524
1525#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
1526                s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
1527#else
1528                s->mix.vol[vidx - 1] = val;
1529#endif
1530                return put_user(s->mix.vol[vidx - 1], (int *) arg);
1531        }
1532}
1533
1534
1535// --------------------------------------------------------------------- 
1536
1537static loff_t cs4297a_llseek(struct file *file, loff_t offset, int origin)
1538{
1539        return -ESPIPE;
1540}
1541
1542
1543// --------------------------------------------------------------------- 
1544
1545static int cs4297a_open_mixdev(struct inode *inode, struct file *file)
1546{
1547        int minor = MINOR(inode->i_rdev);
1548        struct cs4297a_state *s=NULL;
1549        struct list_head *entry;
1550
1551        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1552                  printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n"));
1553
1554        list_for_each(entry, &cs4297a_devs)
1555        {
1556                s = list_entry(entry, struct cs4297a_state, list);
1557                if(s->dev_mixer == minor)
1558                        break;
1559        }
1560        if (!s)
1561        {
1562                CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
1563                        printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n"));
1564                return -ENODEV;
1565        }
1566        VALIDATE_STATE(s);
1567        file->private_data = s;
1568        MOD_INC_USE_COUNT;
1569
1570        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
1571                  printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n"));
1572
1573        return 0;
1574}
1575
1576
1577static int cs4297a_release_mixdev(struct inode *inode, struct file *file)
1578{
1579        struct cs4297a_state *s =
1580            (struct cs4297a_state *) file->private_data;
1581
1582        VALIDATE_STATE(s);
1583        MOD_DEC_USE_COUNT;
1584        return 0;
1585}
1586
1587
1588static int cs4297a_ioctl_mixdev(struct inode *inode, struct file *file,
1589                               unsigned int cmd, unsigned long arg)
1590{
1591        return mixer_ioctl((struct cs4297a_state *) file->private_data, cmd,
1592                           arg);
1593}
1594
1595
1596// ******************************************************************************************
1597//   Mixer file operations struct.
1598// ******************************************************************************************
1599static /*const */ struct file_operations cs4297a_mixer_fops = {
1600        llseek:cs4297a_llseek,
1601        ioctl:cs4297a_ioctl_mixdev,
1602        open:cs4297a_open_mixdev,
1603        release:cs4297a_release_mixdev,
1604};
1605
1606// --------------------------------------------------------------------- 
1607
1608
1609static int drain_adc(struct cs4297a_state *s, int nonblock)
1610{
1611        /* This routine serves no purpose currently - any samples
1612           sitting in the receive queue will just be processed by the
1613           background consumer.  This would be different if DMA
1614           actually stopped when there were no clients. */
1615        return 0;
1616}
1617
1618static int drain_dac(struct cs4297a_state *s, int nonblock)
1619{
1620        DECLARE_WAITQUEUE(wait, current);
1621        unsigned long flags;
1622        unsigned hwptr;
1623        unsigned tmo;
1624        int count;
1625
1626        if (s->dma_dac.mapped)
1627                return 0;
1628        if (nonblock)
1629                return -EBUSY;
1630        add_wait_queue(&s->dma_dac.wait, &wait);
1631        while ((count = in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) ||
1632               (s->dma_dac.count > 0)) {
1633                if (!signal_pending(current)) {
1634                        set_current_state(TASK_INTERRUPTIBLE);
1635                        /* XXXKW is this calculation working? */
1636                        tmo = ((count * FRAME_TX_US) * HZ) / 1000000;
1637                        schedule_timeout(tmo + 1);
1638                } else {
1639                        /* XXXKW do I care if there is a signal pending? */
1640                }
1641        }
1642        spin_lock_irqsave(&s->lock, flags);
1643        /* Reset the bookkeeping */
1644        hwptr = (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1645                       s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
1646        s->dma_dac.hwptr = s->dma_dac.swptr = hwptr;
1647        spin_unlock_irqrestore(&s->lock, flags);
1648        remove_wait_queue(&s->dma_dac.wait, &wait);
1649        current->state = TASK_RUNNING;
1650        return 0;
1651}
1652
1653
1654// --------------------------------------------------------------------- 
1655
1656static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count,
1657                           loff_t * ppos)
1658{
1659        struct cs4297a_state *s =
1660            (struct cs4297a_state *) file->private_data;
1661        ssize_t ret;
1662        unsigned long flags;
1663        int cnt, count_fr, cnt_by;
1664        unsigned copied = 0;
1665
1666        CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1667                  printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count));
1668
1669        VALIDATE_STATE(s);
1670        if (ppos != &file->f_pos)
1671                return -ESPIPE;
1672        if (s->dma_adc.mapped)
1673                return -ENXIO;
1674        if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
1675                return ret;
1676        if (!access_ok(VERIFY_WRITE, buffer, count))
1677                return -EFAULT;
1678        ret = 0;
1679//
1680// "count" is the amount of bytes to read (from app), is decremented each loop
1681//      by the amount of bytes that have been returned to the user buffer.
1682// "cnt" is the running total of each read from the buffer (changes each loop)
1683// "buffer" points to the app's buffer
1684// "ret" keeps a running total of the amount of bytes that have been copied
1685//      to the user buffer.
1686// "copied" is the total bytes copied into the user buffer for each loop.
1687//
1688        while (count > 0) {
1689                CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1690                        "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
1691                                count, s->dma_adc.count,
1692                                s->dma_adc.swptr, s->dma_adc.hwptr));
1693                spin_lock_irqsave(&s->lock, flags);
1694
1695                /* cnt will be the number of available samples (16-bit
1696                   stereo); it starts out as the maxmimum consequetive
1697                   samples */
1698                cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2;
1699                count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES;
1700
1701                // dma_adc.count is the current total bytes that have not been read.
1702                // if the amount of unread bytes from the current sw pointer to the
1703                // end of the buffer is greater than the current total bytes that
1704                // have not been read, then set the "cnt" (unread bytes) to the
1705                // amount of unread bytes.  
1706
1707                if (count_fr < cnt)
1708                        cnt = count_fr;
1709                cnt_by = cnt * FRAME_SAMPLE_BYTES;
1710                spin_unlock_irqrestore(&s->lock, flags);
1711                //
1712                // if we are converting from 8/16 then we need to copy
1713                // twice the number of 16 bit bytes then 8 bit bytes.
1714                // 
1715                if (s->conversion) {
1716                        if (cnt_by > (count * 2)) {
1717                                cnt = (count * 2) / FRAME_SAMPLE_BYTES;
1718                                cnt_by = count * 2;
1719                        }
1720                } else {
1721                        if (cnt_by > count) {
1722                                cnt = count / FRAME_SAMPLE_BYTES;
1723                                cnt_by = count;
1724                        }
1725                }
1726                //
1727                // "cnt" NOW is the smaller of the amount that will be read,
1728                // and the amount that is requested in this read (or partial).
1729                // if there are no bytes in the buffer to read, then start the
1730                // ADC and wait for the interrupt handler to wake us up.
1731                //
1732                if (cnt <= 0) {
1733
1734                        // start up the dma engine and then continue back to the top of
1735                        // the loop when wake up occurs.
1736                        start_adc(s);
1737                        if (file->f_flags & O_NONBLOCK)
1738                                return ret ? ret : -EAGAIN;
1739                        interruptible_sleep_on(&s->dma_adc.wait);
1740                        if (signal_pending(current))
1741                                return ret ? ret : -ERESTARTSYS;
1742                        continue;
1743                }
1744                // there are bytes in the buffer to read.
1745                // copy from the hw buffer over to the user buffer.
1746                // user buffer is designated by "buffer"
1747                // virtual address to copy from is dma_buf+swptr
1748                // the "cnt" is the number of bytes to read.
1749
1750                CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
1751                        "_read() copy_to cnt=%d count=%d ", cnt_by, count));
1752                CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
1753                         " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n",
1754                                 s->dma_adc.sbufsz, s->dma_adc.count,
1755                                 (unsigned) buffer, ret));
1756
1757                if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by))
1758                        return ret ? ret : -EFAULT;
1759                copied = cnt_by;
1760
1761                /* Return the descriptors */
1762                spin_lock_irqsave(&s->lock, flags);
1763                CS_DBGOUT(CS_FUNCTION, 2, 
1764                          printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr));
1765                s->dma_adc.count -= cnt_by;
1766                s->dma_adc.sb_swptr += cnt * 2;
1767                if (s->dma_adc.sb_swptr == s->dma_adc.sb_end)
1768                        s->dma_adc.sb_swptr = s->dma_adc.sample_buf;
1769                spin_unlock_irqrestore(&s->lock, flags);
1770                count -= copied;
1771                buffer += copied;
1772                ret += copied;
1773                start_adc(s);
1774        }
1775        CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
1776                  printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret));
1777        return ret;
1778}
1779
1780
1781static ssize_t cs4297a_write(struct file *file, const char *buffer,
1782                            size_t count, loff_t * ppos)
1783{
1784        struct cs4297a_state *s =
1785            (struct cs4297a_state *) file->private_data;
1786        ssize_t ret;
1787        unsigned long flags;
1788        unsigned swptr, hwptr;
1789        int cnt;
1790
1791        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1792                  printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n",
1793                         count));
1794        VALIDATE_STATE(s);
1795
1796        if (ppos != &file->f_pos)
1797                return -ESPIPE;
1798        if (s->dma_dac.mapped)
1799                return -ENXIO;
1800        if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
1801                return ret;
1802        if (!access_ok(VERIFY_READ, buffer, count))
1803                return -EFAULT;
1804        ret = 0;
1805        while (count > 0) {
1806                serdma_t *d = &s->dma_dac;
1807                int copy_cnt;
1808                u32 *s_tmpl;
1809                u32 *t_tmpl;
1810                u32 left, right;
1811                int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE);
1812                
1813                /* XXXXXX this is broken for BLOAT_FACTOR */
1814                spin_lock_irqsave(&s->lock, flags);
1815                if (d->count < 0) {
1816                        d->count = 0;
1817                        d->swptr = d->hwptr;
1818                }
1819                if (d->underrun) {
1820                        d->underrun = 0;
1821                        hwptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
1822                                             d->descrtab_phys) / sizeof(serdma_descr_t));
1823                        d->swptr = d->hwptr = hwptr;
1824                }
1825                swptr = d->swptr;
1826                cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES);
1827                /* Will this write fill up the buffer? */
1828                if (d->count + cnt > d->sbufsz)
1829                        cnt = d->sbufsz - d->count;
1830                spin_unlock_irqrestore(&s->lock, flags);
1831                if (cnt > count)
1832                        cnt = count;
1833                if (cnt <= 0) {
1834                        start_dac(s);
1835                        if (file->f_flags & O_NONBLOCK)
1836                                return ret ? ret : -EAGAIN;
1837                        interruptible_sleep_on(&d->wait);
1838                        if (signal_pending(current))
1839                                return ret ? ret : -ERESTARTSYS;
1840                        continue;
1841                }
1842                if (copy_from_user(d->sample_buf, buffer, cnt))
1843                        return ret ? ret : -EFAULT;
1844
1845                copy_cnt = cnt;
1846                s_tmpl = (u32 *)d->sample_buf;
1847                t_tmpl = (u32 *)(d->dma_buf + (swptr * 4));
1848
1849                /* XXXKW assuming 16-bit stereo! */
1850                do {
1851                        u32 tmp;
1852
1853                        t_tmpl[0] = cpu_to_be32(0x98000000);
1854
1855                        tmp = be32_to_cpu(s_tmpl[0]);
1856                        left = tmp & 0xffff;
1857                        right = tmp >> 16;
1858                        if (swap) {
1859                                left = swab16(left);
1860                                right = swab16(right);
1861                        }
1862                        t_tmpl[1] = cpu_to_be32(left >> 8);
1863                        t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) |
1864                                                (right << 4));
1865
1866                        s_tmpl++;
1867                        t_tmpl += 8;
1868                        copy_cnt -= 4;
1869                } while (copy_cnt);
1870
1871                /* Mux in any pending read/write accesses */
1872                if (s->reg_request) {
1873                        *(u64 *)(d->dma_buf + (swptr * 4)) |=
1874                                cpu_to_be64(s->reg_request);
1875                        s->reg_request = 0;
1876                        wake_up(&s->dma_dac.reg_wait);
1877                }
1878
1879                CS_DBGOUT(CS_WAVE_WRITE, 4,
1880                          printk(KERN_INFO
1881                                 "cs4297a: copy in %d to swptr %x\n", cnt, swptr));
1882
1883                swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz;
1884                out64(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX));
1885                spin_lock_irqsave(&s->lock, flags);
1886                d->swptr = swptr;
1887                d->count += cnt;
1888                d->endcleared = 0;
1889                spin_unlock_irqrestore(&s->lock, flags);
1890                count -= cnt;
1891                buffer += cnt;
1892                ret += cnt;
1893                start_dac(s);
1894        }
1895        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
1896                  printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret));
1897        return ret;
1898}
1899
1900
1901static unsigned int cs4297a_poll(struct file *file,
1902                                struct poll_table_struct *wait)
1903{
1904        struct cs4297a_state *s =
1905            (struct cs4297a_state *) file->private_data;
1906        unsigned long flags;
1907        unsigned int mask = 0;
1908
1909        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1910                  printk(KERN_INFO "cs4297a: cs4297a_poll()+\n"));
1911        VALIDATE_STATE(s);
1912        if (file->f_mode & FMODE_WRITE) {
1913                CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1914                          printk(KERN_INFO
1915                                 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n"));
1916                if(!s->dma_dac.ready && prog_dmabuf_dac(s))
1917                        return 0;
1918                poll_wait(file, &s->dma_dac.wait, wait);
1919        }
1920        if (file->f_mode & FMODE_READ) {
1921                CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1922                          printk(KERN_INFO
1923                                 "cs4297a: cs4297a_poll() wait on FMODE_READ\n"));
1924                if(!s->dma_dac.ready && prog_dmabuf_adc(s))
1925                        return 0;
1926                poll_wait(file, &s->dma_adc.wait, wait);
1927        }
1928        spin_lock_irqsave(&s->lock, flags);
1929        cs4297a_update_ptr(s,CS_FALSE);
1930        if (file->f_mode & FMODE_WRITE) {
1931                if (s->dma_dac.mapped) {
1932                        if (s->dma_dac.count >=
1933                            (signed) s->dma_dac.fragsize) {
1934                                if (s->dma_dac.wakeup)
1935                                        mask |= POLLOUT | POLLWRNORM;
1936                                else
1937                                        mask = 0;
1938                                s->dma_dac.wakeup = 0;
1939                        }
1940                } else {
1941                        if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count)
1942                                mask |= POLLOUT | POLLWRNORM;
1943                }
1944        } else if (file->f_mode & FMODE_READ) {
1945                if (s->dma_adc.mapped) {
1946                        if (s->dma_adc.count >= (signed) s->dma_adc.fragsize) 
1947                                mask |= POLLIN | POLLRDNORM;
1948                } else {
1949                        if (s->dma_adc.count > 0)
1950                                mask |= POLLIN | POLLRDNORM;
1951                }
1952        }
1953        spin_unlock_irqrestore(&s->lock, flags);
1954        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
1955                  printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n",
1956                         mask));
1957        return mask;
1958}
1959
1960
1961static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma)
1962{
1963        /* XXXKW currently no mmap support */
1964        return -EINVAL;
1965        return 0;
1966}
1967
1968
1969static int cs4297a_ioctl(struct inode *inode, struct file *file,
1970                        unsigned int cmd, unsigned long arg)
1971{
1972        struct cs4297a_state *s =
1973            (struct cs4297a_state *) file->private_data;
1974        unsigned long flags;
1975        audio_buf_info abinfo;
1976        count_info cinfo;
1977        int val, mapped, ret;
1978
1979        CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO
1980                 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n",
1981                         (unsigned) file, cmd));
1982#if CSDEBUG
1983        cs_printioctl(cmd);
1984#endif
1985        VALIDATE_STATE(s);
1986        mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
1987            ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
1988        switch (cmd) {
1989        case OSS_GETVERSION:
1990                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
1991                        "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n",
1992                                 SOUND_VERSION));
1993                return put_user(SOUND_VERSION, (int *) arg);
1994
1995        case SNDCTL_DSP_SYNC:
1996                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
1997                         "cs4297a: cs4297a_ioctl(): DSP_SYNC\n"));
1998                if (file->f_mode & FMODE_WRITE)
1999                        return drain_dac(s,
2000                                         0 /*file->f_flags & O_NONBLOCK */
2001                                         );
2002                return 0;
2003
2004        case SNDCTL_DSP_SETDUPLEX:
2005                return 0;
2006
2007        case SNDCTL_DSP_GETCAPS:
2008                return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
2009                                DSP_CAP_TRIGGER | DSP_CAP_MMAP,
2010                                (int *) arg);
2011
2012        case SNDCTL_DSP_RESET:
2013                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2014                         "cs4297a: cs4297a_ioctl(): DSP_RESET\n"));
2015                if (file->f_mode & FMODE_WRITE) {
2016                        stop_dac(s);
2017                        synchronize_irq();
2018                        s->dma_dac.count = s->dma_dac.total_bytes =
2019                                s->dma_dac.blocks = s->dma_dac.wakeup = 0;
2020                        s->dma_dac.swptr = s->dma_dac.hwptr =
2021                                (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) -
2022                                       s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t));
2023                }
2024                if (file->f_mode & FMODE_READ) {
2025                        stop_adc(s);
2026                        synchronize_irq();
2027                        s->dma_adc.count = s->dma_adc.total_bytes =
2028                                s->dma_adc.blocks = s->dma_dac.wakeup = 0;
2029                        s->dma_adc.swptr = s->dma_adc.hwptr =
2030                                (int)(((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2031                                       s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2032                }
2033                return 0;
2034
2035        case SNDCTL_DSP_SPEED:
2036                if (get_user(val, (int *) arg))
2037                        return -EFAULT;
2038                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2039                         "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val));
2040                val = 48000;
2041                return put_user(val, (int *) arg);
2042
2043        case SNDCTL_DSP_STEREO:
2044                if (get_user(val, (int *) arg))
2045                        return -EFAULT;
2046                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2047                         "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val));
2048                if (file->f_mode & FMODE_READ) {
2049                        stop_adc(s);
2050                        s->dma_adc.ready = 0;
2051                        s->prop_adc.channels = val ? 2 : 1;
2052                }
2053                if (file->f_mode & FMODE_WRITE) {
2054                        stop_dac(s);
2055                        s->dma_dac.ready = 0;
2056                        s->prop_dac.channels = val ? 2 : 1;
2057                }
2058                return 0;
2059
2060        case SNDCTL_DSP_CHANNELS:
2061                if (get_user(val, (int *) arg))
2062                        return -EFAULT;
2063                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2064                         "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n",
2065                                 val));
2066                if (val != 0) {
2067                        if (file->f_mode & FMODE_READ) {
2068                                stop_adc(s);
2069                                s->dma_adc.ready = 0;
2070                                if (val >= 2)
2071                                        s->prop_adc.channels = 2;
2072                                else
2073                                        s->prop_adc.channels = 1;
2074                        }
2075                        if (file->f_mode & FMODE_WRITE) {
2076                                stop_dac(s);
2077                                s->dma_dac.ready = 0;
2078                                if (val >= 2)
2079                                        s->prop_dac.channels = 2;
2080                                else
2081                                        s->prop_dac.channels = 1;
2082                        }
2083                }
2084
2085                if (file->f_mode & FMODE_WRITE)
2086                        val = s->prop_dac.channels;
2087                else if (file->f_mode & FMODE_READ)
2088                        val = s->prop_adc.channels;
2089
2090                return put_user(val, (int *) arg);
2091
2092        case SNDCTL_DSP_GETFMTS:        // Returns a mask 
2093                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2094                        "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n",
2095                                 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2096                                 AFMT_U8));
2097                return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
2098                                AFMT_U8, (int *) arg);
2099
2100        case SNDCTL_DSP_SETFMT:
2101                if (get_user(val, (int *) arg))
2102                        return -EFAULT;
2103                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2104                         "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n",
2105                                 val));
2106                if (val != AFMT_QUERY) {
2107                        if (file->f_mode & FMODE_READ) {
2108                                stop_adc(s);
2109                                s->dma_adc.ready = 0;
2110                                if (val != AFMT_S16_LE
2111                                    && val != AFMT_U16_LE && val != AFMT_S8
2112                                    && val != AFMT_U8)
2113                                        val = AFMT_U8;
2114                                s->prop_adc.fmt = val;
2115                                s->prop_adc.fmt_original = s->prop_adc.fmt;
2116                        }
2117                        if (file->f_mode & FMODE_WRITE) {
2118                                stop_dac(s);
2119                                s->dma_dac.ready = 0;
2120                                if (val != AFMT_S16_LE
2121                                    && val != AFMT_U16_LE && val != AFMT_S8
2122                                    && val != AFMT_U8)
2123                                        val = AFMT_U8;
2124                                s->prop_dac.fmt = val;
2125                                s->prop_dac.fmt_original = s->prop_dac.fmt;
2126                        }
2127                } else {
2128                        if (file->f_mode & FMODE_WRITE)
2129                                val = s->prop_dac.fmt_original;
2130                        else if (file->f_mode & FMODE_READ)
2131                                val = s->prop_adc.fmt_original;
2132                }
2133                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
2134                  "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n", 
2135                        val));
2136                return put_user(val, (int *) arg);
2137
2138        case SNDCTL_DSP_POST:
2139                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2140                         "cs4297a: cs4297a_ioctl(): DSP_POST\n"));
2141                return 0;
2142
2143        case SNDCTL_DSP_GETTRIGGER:
2144                val = 0;
2145                if (file->f_mode & s->ena & FMODE_READ)
2146                        val |= PCM_ENABLE_INPUT;
2147                if (file->f_mode & s->ena & FMODE_WRITE)
2148                        val |= PCM_ENABLE_OUTPUT;
2149                return put_user(val, (int *) arg);
2150
2151        case SNDCTL_DSP_SETTRIGGER:
2152                if (get_user(val, (int *) arg))
2153                        return -EFAULT;
2154                if (file->f_mode & FMODE_READ) {
2155                        if (val & PCM_ENABLE_INPUT) {
2156                                if (!s->dma_adc.ready
2157                                    && (ret = prog_dmabuf_adc(s)))
2158                                        return ret;
2159                                start_adc(s);
2160                        } else
2161                                stop_adc(s);
2162                }
2163                if (file->f_mode & FMODE_WRITE) {
2164                        if (val & PCM_ENABLE_OUTPUT) {
2165                                if (!s->dma_dac.ready
2166                                    && (ret = prog_dmabuf_dac(s)))
2167                                        return ret;
2168                                start_dac(s);
2169                        } else
2170                                stop_dac(s);
2171                }
2172                return 0;
2173
2174        case SNDCTL_DSP_GETOSPACE:
2175                if (!(file->f_mode & FMODE_WRITE))
2176                        return -EINVAL;
2177                if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
2178                        return val;
2179                spin_lock_irqsave(&s->lock, flags);
2180                cs4297a_update_ptr(s,CS_FALSE);
2181                abinfo.fragsize = s->dma_dac.fragsize;
2182                if (s->dma_dac.mapped)
2183                        abinfo.bytes = s->dma_dac.sbufsz;
2184                else
2185                        abinfo.bytes =
2186                            s->dma_dac.sbufsz - s->dma_dac.count;
2187                abinfo.fragstotal = s->dma_dac.numfrag;
2188                abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
2189                CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
2190                        "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
2191                                abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
2192                                abinfo.fragments));
2193                spin_unlock_irqrestore(&s->lock, flags);
2194                return copy_to_user((void *) arg, &abinfo,
2195                                    sizeof(abinfo)) ? -EFAULT : 0;
2196
2197        case SNDCTL_DSP_GETISPACE:
2198                if (!(file->f_mode & FMODE_READ))
2199                        return -EINVAL;
2200                if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
2201                        return val;
2202                spin_lock_irqsave(&s->lock, flags);
2203                cs4297a_update_ptr(s,CS_FALSE);
2204                if (s->conversion) {
2205                        abinfo.fragsize = s->dma_adc.fragsize / 2;
2206                        abinfo.bytes = s->dma_adc.count / 2;
2207                        abinfo.fragstotal = s->dma_adc.numfrag;
2208                        abinfo.fragments =
2209                            abinfo.bytes >> (s->dma_adc.fragshift - 1);
2210                } else {
2211                        abinfo.fragsize = s->dma_adc.fragsize;
2212                        abinfo.bytes = s->dma_adc.count;
2213                        abinfo.fragstotal = s->dma_adc.numfrag;
2214                        abinfo.fragments =
2215                            abinfo.bytes >> s->dma_adc.fragshift;
2216                }
2217                spin_unlock_irqrestore(&s->lock, flags);
2218                return copy_to_user((void *) arg, &abinfo,
2219                                    sizeof(abinfo)) ? -EFAULT : 0;
2220
2221        case SNDCTL_DSP_NONBLOCK:
2222                file->f_flags |= O_NONBLOCK;
2223                return 0;
2224
2225        case SNDCTL_DSP_GETODELAY:
2226                if (!(file->f_mode & FMODE_WRITE))
2227                        return -EINVAL;
2228                if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2229                        return 0;
2230                spin_lock_irqsave(&s->lock, flags);
2231                cs4297a_update_ptr(s,CS_FALSE);
2232                val = s->dma_dac.count;
2233                spin_unlock_irqrestore(&s->lock, flags);
2234                return put_user(val, (int *) arg);
2235
2236        case SNDCTL_DSP_GETIPTR:
2237                if (!(file->f_mode & FMODE_READ))
2238                        return -EINVAL;
2239                if(!s->dma_adc.ready && prog_dmabuf_adc(s))
2240                        return 0;
2241                spin_lock_irqsave(&s->lock, flags);
2242                cs4297a_update_ptr(s,CS_FALSE);
2243                cinfo.bytes = s->dma_adc.total_bytes;
2244                if (s->dma_adc.mapped) {
2245                        cinfo.blocks =
2246                            (cinfo.bytes >> s->dma_adc.fragshift) -
2247                            s->dma_adc.blocks;
2248                        s->dma_adc.blocks =
2249                            cinfo.bytes >> s->dma_adc.fragshift;
2250                } else {
2251                        if (s->conversion) {
2252                                cinfo.blocks =
2253                                    s->dma_adc.count /
2254                                    2 >> (s->dma_adc.fragshift - 1);
2255                        } else
2256                                cinfo.blocks =
2257                                    s->dma_adc.count >> s->dma_adc.
2258                                    fragshift;
2259                }
2260                if (s->conversion)
2261                        cinfo.ptr = s->dma_adc.hwptr / 2;
2262                else
2263                        cinfo.ptr = s->dma_adc.hwptr;
2264                if (s->dma_adc.mapped)
2265                        s->dma_adc.count &= s->dma_adc.fragsize - 1;
2266                spin_unlock_irqrestore(&s->lock, flags);
2267                return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
2268
2269        case SNDCTL_DSP_GETOPTR:
2270                if (!(file->f_mode & FMODE_WRITE))
2271                        return -EINVAL;
2272                if(!s->dma_dac.ready && prog_dmabuf_dac(s))
2273                        return 0;
2274                spin_lock_irqsave(&s->lock, flags);
2275                cs4297a_update_ptr(s,CS_FALSE);
2276                cinfo.bytes = s->dma_dac.total_bytes;
2277                if (s->dma_dac.mapped) {
2278                        cinfo.blocks =
2279                            (cinfo.bytes >> s->dma_dac.fragshift) -
2280                            s->dma_dac.blocks;
2281                        s->dma_dac.blocks =
2282                            cinfo.bytes >> s->dma_dac.fragshift;
2283                } else {
2284                        cinfo.blocks =
2285                            s->dma_dac.count >> s->dma_dac.fragshift;
2286                }
2287                cinfo.ptr = s->dma_dac.hwptr;
2288                if (s->dma_dac.mapped)
2289                        s->dma_dac.count &= s->dma_dac.fragsize - 1;
2290                spin_unlock_irqrestore(&s->lock, flags);
2291                return copy_to_user((void *) arg, &cinfo, sizeof(cinfo));
2292
2293        case SNDCTL_DSP_GETBLKSIZE:
2294                if (file->f_mode & FMODE_WRITE) {
2295                        if ((val = prog_dmabuf_dac(s)))
2296                                return val;
2297                        return put_user(s->dma_dac.fragsize, (int *) arg);
2298                }
2299                if ((val = prog_dmabuf_adc(s)))
2300                        return val;
2301                if (s->conversion)
2302                        return put_user(s->dma_adc.fragsize / 2,
2303                                        (int *) arg);
2304                else
2305                        return put_user(s->dma_adc.fragsize, (int *) arg);
2306
2307        case SNDCTL_DSP_SETFRAGMENT:
2308                if (get_user(val, (int *) arg))
2309                        return -EFAULT;
2310                return 0;       // Say OK, but do nothing.
2311
2312        case SNDCTL_DSP_SUBDIVIDE:
2313                if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
2314                    || (file->f_mode & FMODE_WRITE
2315                        && s->dma_dac.subdivision)) return -EINVAL;
2316                if (get_user(val, (int *) arg))
2317                        return -EFAULT;
2318                if (val != 1 && val != 2 && val != 4)
2319                        return -EINVAL;
2320                if (file->f_mode & FMODE_READ)
2321                        s->dma_adc.subdivision = val;
2322                else if (file->f_mode & FMODE_WRITE)
2323                        s->dma_dac.subdivision = val;
2324                return 0;
2325
2326        case SOUND_PCM_READ_RATE:
2327                if (file->f_mode & FMODE_READ)
2328                        return put_user(s->prop_adc.rate, (int *) arg);
2329                else if (file->f_mode & FMODE_WRITE)
2330                        return put_user(s->prop_dac.rate, (int *) arg);
2331
2332        case SOUND_PCM_READ_CHANNELS:
2333                if (file->f_mode & FMODE_READ)
2334                        return put_user(s->prop_adc.channels, (int *) arg);
2335                else if (file->f_mode & FMODE_WRITE)
2336                        return put_user(s->prop_dac.channels, (int *) arg);
2337
2338        case SOUND_PCM_READ_BITS:
2339                if (file->f_mode & FMODE_READ)
2340                        return
2341                            put_user(
2342                                     (s->prop_adc.
2343                                      fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2344                                     (int *) arg);
2345                else if (file->f_mode & FMODE_WRITE)
2346                        return
2347                            put_user(
2348                                     (s->prop_dac.
2349                                      fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
2350                                     (int *) arg);
2351
2352        case SOUND_PCM_WRITE_FILTER:
2353        case SNDCTL_DSP_SETSYNCRO:
2354        case SOUND_PCM_READ_FILTER:
2355                return -EINVAL;
2356        }
2357        return mixer_ioctl(s, cmd, arg);
2358}
2359
2360
2361static int cs4297a_release(struct inode *inode, struct file *file)
2362{
2363        struct cs4297a_state *s =
2364            (struct cs4297a_state *) file->private_data;
2365
2366        CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
2367                 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2368                         (unsigned) inode, (unsigned) file, file->f_mode));
2369        VALIDATE_STATE(s);
2370
2371        if (file->f_mode & FMODE_WRITE) {
2372                drain_dac(s, file->f_flags & O_NONBLOCK);
2373                down(&s->open_sem_dac);
2374                stop_dac(s);
2375                dealloc_dmabuf(s, &s->dma_dac);
2376                s->open_mode &= ~FMODE_WRITE;
2377                up(&s->open_sem_dac);
2378                wake_up(&s->open_wait_dac);
2379                MOD_DEC_USE_COUNT;
2380        }
2381        if (file->f_mode & FMODE_READ) {
2382                drain_adc(s, file->f_flags & O_NONBLOCK);
2383                down(&s->open_sem_adc);
2384                stop_adc(s);
2385                dealloc_dmabuf(s, &s->dma_adc);
2386                s->open_mode &= ~FMODE_READ;
2387                up(&s->open_sem_adc);
2388                wake_up(&s->open_wait_adc);
2389                MOD_DEC_USE_COUNT;
2390        }
2391        return 0;
2392}
2393
2394static int cs4297a_open(struct inode *inode, struct file *file)
2395{
2396        int minor = MINOR(inode->i_rdev);
2397        struct cs4297a_state *s=NULL;
2398        struct list_head *entry;
2399
2400        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2401                "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
2402                        (unsigned) inode, (unsigned) file, file->f_mode));
2403        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2404                "cs4297a: status = %08x\n", (int)in64(SS_CSR(R_SER_STATUS_DEBUG))));
2405
2406        list_for_each(entry, &cs4297a_devs)
2407        {
2408                s = list_entry(entry, struct cs4297a_state, list);
2409
2410                if (!((s->dev_audio ^ minor) & ~0xf))
2411                        break;
2412        }
2413        if (entry == &cs4297a_devs)
2414                return -ENODEV;
2415        if (!s) {
2416                CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
2417                        "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n"));
2418                return -ENODEV;
2419        }
2420        VALIDATE_STATE(s);
2421        file->private_data = s;
2422
2423        // wait for device to become free 
2424        if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
2425                CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
2426                         "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n"));
2427                return -ENODEV;
2428        }
2429        if (file->f_mode & FMODE_WRITE) {
2430                if (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) {
2431                        printk(KERN_ERR "cs4297a: TX pipe needs to drain\n");
2432                        while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)))
2433                                ;
2434                }
2435          
2436                down(&s->open_sem_dac);
2437                while (s->open_mode & FMODE_WRITE) {
2438                        if (file->f_flags & O_NONBLOCK) {
2439                                up(&s->open_sem_dac);
2440                                return -EBUSY;
2441                        }
2442                        up(&s->open_sem_dac);
2443                        interruptible_sleep_on(&s->open_wait_dac);
2444
2445                        if (signal_pending(current)) {
2446                                printk("open - sig pending\n");
2447                                return -ERESTARTSYS;
2448                        }
2449                        down(&s->open_sem_dac);
2450                }
2451        }
2452        if (file->f_mode & FMODE_READ) {
2453                down(&s->open_sem_adc);
2454                while (s->open_mode & FMODE_READ) {
2455                        if (file->f_flags & O_NONBLOCK) {
2456                                up(&s->open_sem_adc);
2457                                return -EBUSY;
2458                        }
2459                        up(&s->open_sem_adc);
2460                        interruptible_sleep_on(&s->open_wait_adc);
2461
2462                        if (signal_pending(current)) {
2463                                printk("open - sig pending\n");
2464                                return -ERESTARTSYS;
2465                        }
2466                        down(&s->open_sem_adc);
2467                }
2468        }
2469        s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
2470        if (file->f_mode & FMODE_READ) {
2471                s->prop_adc.fmt = AFMT_S16_BE;
2472                s->prop_adc.fmt_original = s->prop_adc.fmt;
2473                s->prop_adc.channels = 2;
2474                s->prop_adc.rate = 48000;
2475                s->conversion = 0;
2476                s->ena &= ~FMODE_READ;
2477                s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
2478                    s->dma_adc.subdivision = 0;
2479                up(&s->open_sem_adc);
2480                MOD_INC_USE_COUNT;
2481
2482                if (prog_dmabuf_adc(s)) {
2483                        CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2484                                "cs4297a: adc Program dmabufs failed.\n"));
2485                        cs4297a_release(inode, file);
2486                        return -ENOMEM;
2487                }
2488        }
2489        if (file->f_mode & FMODE_WRITE) {
2490                s->prop_dac.fmt = AFMT_S16_BE;
2491                s->prop_dac.fmt_original = s->prop_dac.fmt;
2492                s->prop_dac.channels = 2;
2493                s->prop_dac.rate = 48000;
2494                s->conversion = 0;
2495                s->ena &= ~FMODE_WRITE;
2496                s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
2497                    s->dma_dac.subdivision = 0;
2498                up(&s->open_sem_dac);
2499                MOD_INC_USE_COUNT;
2500
2501                if (prog_dmabuf_dac(s)) {
2502                        CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
2503                                "cs4297a: dac Program dmabufs failed.\n"));
2504                        cs4297a_release(inode, file);
2505                        return -ENOMEM;
2506                }
2507        }
2508        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
2509                  printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n"));
2510        return 0;
2511}
2512
2513
2514// ******************************************************************************************
2515//   Wave (audio) file operations struct.
2516// ******************************************************************************************
2517static /*const */ struct file_operations cs4297a_audio_fops = {
2518        llseek:cs4297a_llseek,
2519        read:cs4297a_read,
2520        write:cs4297a_write,
2521        poll:cs4297a_poll,
2522        ioctl:cs4297a_ioctl,
2523        mmap:cs4297a_mmap,
2524        open:cs4297a_open,
2525        release:cs4297a_release,
2526};
2527
2528static void cs4297a_interrupt(int irq, void *dev_id, struct pt_regs *regs)
2529{
2530        struct cs4297a_state *s = (struct cs4297a_state *) dev_id;
2531        u32 status;
2532
2533        status = in64(SS_CSR(R_SER_STATUS_DEBUG));
2534
2535        CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2536                 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status));
2537
2538#if 0
2539        /* XXXKW what check *should* be done here? */
2540        if (!(status & (M_SYNCSER_RX_EOP_COUNT | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_SYNC_ERR))) {
2541                status = in64(SS_CSR(R_SER_STATUS));
2542                printk(KERN_ERR "cs4297a: unexpected interrupt (status %08x)\n", status);
2543                return;
2544        }
2545#endif
2546
2547        if (status & M_SYNCSER_RX_SYNC_ERR) {
2548                status = in64(SS_CSR(R_SER_STATUS));
2549                printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status);
2550                return;
2551        }
2552
2553        if (status & M_SYNCSER_RX_OVERRUN) {
2554                int newptr, i;
2555                s->stats.rx_ovrrn++;
2556                printk(KERN_ERR "cs4297a: receive FIFO overrun\n");
2557
2558                /* Fix things up: get the receive descriptor pool
2559                   clean and give them back to the hardware */
2560                while (in64(SS_CSR(R_SER_DMA_DSCR_COUNT_RX)))
2561                        ;
2562                newptr = (unsigned) (((in64(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) -
2563                                     s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t));
2564                for (i=0; i<DMA_DESCR; i++) {
2565                        s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP;
2566                }
2567                s->dma_adc.swptr = s->dma_adc.hwptr = newptr;
2568                s->dma_adc.count = 0;
2569                s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf;
2570                out64(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX));
2571        }
2572
2573        spin_lock(&s->lock);
2574        cs4297a_update_ptr(s,CS_TRUE);
2575        spin_unlock(&s->lock);
2576
2577        CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
2578                  "cs4297a: cs4297a_interrupt()-\n"));
2579}
2580
2581#if 0
2582static struct initvol {
2583        int mixch;
2584        int vol;
2585} initvol[] __initdata = {
2586
2587        {SOUND_MIXER_WRITE_VOLUME, 0x4040},
2588        {SOUND_MIXER_WRITE_PCM, 0x4040},
2589        {SOUND_MIXER_WRITE_SYNTH, 0x4040},
2590        {SOUND_MIXER_WRITE_CD, 0x4040},
2591        {SOUND_MIXER_WRITE_LINE, 0x4040},
2592        {SOUND_MIXER_WRITE_LINE1, 0x4040},
2593        {SOUND_MIXER_WRITE_RECLEV, 0x0000},
2594        {SOUND_MIXER_WRITE_SPEAKER, 0x4040},
2595        {SOUND_MIXER_WRITE_MIC, 0x0000}
2596};
2597#endif
2598
2599static int __init cs4297a_init(void)
2600{
2601        struct cs4297a_state *s;
2602        u32 pwr, id;
2603        mm_segment_t fs;
2604        int rval;
2605#ifndef CONFIG_BCM_CS4297A_CSWARM
2606        u64 cfg;
2607        int mdio_val;
2608#endif
2609
2610        CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO 
2611                "cs4297a: cs4297a_init_module()+ \n"));
2612
2613#ifndef CONFIG_BCM_CS4297A_CSWARM
2614        mdio_val = in64(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) &
2615                (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT);
2616
2617        /* Check syscfg for synchronous serial on port 1 */
2618        cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG);
2619        if (!(cfg & M_SYS_SER1_ENABLE)) {
2620                out64(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG);
2621                cfg = in64(KSEG1 + A_SCD_SYSTEM_CFG);
2622                if (!(cfg & M_SYS_SER1_ENABLE)) {
2623                  printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n");
2624                  return -1;
2625                }
2626
2627                printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n");
2628                
2629                /* Force the codec (on SWARM) to reset by clearing
2630                   GENO, preserving MDIO (no effect on CSWARM) */
2631                out64(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2632                udelay(10);
2633        }
2634
2635        /* Now set GENO */
2636        out64(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO));
2637        /* Give the codec some time to finish resetting (start the bit clock) */
2638        udelay(100);
2639#endif
2640
2641        if (!(s = kmalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) {
2642                CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
2643                      "cs4297a: probe() no memory for state struct.\n"));
2644                return -1;
2645        }
2646        memset(s, 0, sizeof(struct cs4297a_state));
2647        s->magic = CS4297a_MAGIC;
2648        init_waitqueue_head(&s->dma_adc.wait);
2649        init_waitqueue_head(&s->dma_dac.wait);
2650        init_waitqueue_head(&s->dma_adc.reg_wait);
2651        init_waitqueue_head(&s->dma_dac.reg_wait);
2652        init_waitqueue_head(&s->open_wait);
2653        init_waitqueue_head(&s->open_wait_adc);
2654        init_waitqueue_head(&s->open_wait_dac);
2655        init_MUTEX(&s->open_sem_adc);
2656        init_MUTEX(&s->open_sem_dac);
2657        spin_lock_init(&s->lock);
2658
2659        s->irq = K_INT_SER_1;
2660
2661        if (request_irq
2662            (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) {
2663                CS_DBGOUT(CS_INIT | CS_ERROR, 1,
2664                          printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq));
2665                goto err_irq;
2666        }
2667        if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) <
2668            0) {
2669                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2670                         "cs4297a: probe() register_sound_dsp() failed.\n"));
2671                goto err_dev1;
2672        }
2673        if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) <
2674            0) {
2675                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2676                         "cs4297a: probe() register_sound_mixer() failed.\n"));
2677                goto err_dev2;
2678        }
2679
2680        if (ser_init(s) || dma_init(s)) {
2681                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
2682                         "cs4297a: ser_init failed.\n"));
2683                goto err_dev3;
2684        }
2685
2686        do {
2687                udelay(4000);
2688                rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr);
2689        } while (!rval && (pwr != 0xf));
2690
2691        if (!rval) {
2692                fs = get_fs();
2693                set_fs(KERNEL_DS);
2694#if 0
2695                val = SOUND_MASK_LINE;
2696                mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
2697                for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
2698                        val = initvol[i].vol;
2699                        mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
2700                }
2701//                cs4297a_write_ac97(s, 0x18, 0x0808);
2702#else
2703                //                cs4297a_write_ac97(s, 0x5e, 0x180);
2704                cs4297a_write_ac97(s, 0x02, 0x0808);
2705                cs4297a_write_ac97(s, 0x18, 0x0808);
2706#endif
2707                set_fs(fs);
2708
2709                list_add(&s->list, &cs4297a_devs);
2710
2711                cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id);
2712
2713#ifdef CONFIG_SIBYTE_SB1250_DUART       
2714                sb1250_duart_present[1] = 0;
2715#endif
2716                
2717                printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id);
2718
2719                CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2720                          printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n"));
2721                
2722                return 0;
2723        }
2724
2725 err_dev3:
2726        unregister_sound_mixer(s->dev_mixer);
2727 err_dev2:
2728        unregister_sound_dsp(s->dev_audio);
2729 err_dev1:
2730        free_irq(s->irq, s);
2731 err_irq:
2732        kfree(s);
2733
2734        printk(KERN_INFO "cs4297a: initialization failed\n");
2735
2736        return -1;
2737}
2738
2739static void __exit cs4297a_cleanup(void)
2740{
2741        /*
2742          XXXKW 
2743           disable_irq, free_irq
2744           drain DMA queue
2745           disable DMA
2746           disable TX/RX
2747           free memory
2748        */
2749        CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
2750                  printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n"));
2751}
2752
2753// --------------------------------------------------------------------- 
2754
2755EXPORT_NO_SYMBOLS;
2756
2757MODULE_AUTHOR("Kip Walker, Broadcom Corp.");
2758MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board");
2759
2760// --------------------------------------------------------------------- 
2761
2762module_init(cs4297a_init);
2763module_exit(cs4297a_cleanup);
2764