linux-old/drivers/sound/cs4281/cs4281m.c
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   1/*******************************************************************************
   2*
   3*      "cs4281m.c" --  Cirrus Logic-Crystal CS4281 linux audio driver.
   4*
   5*      Copyright (C) 2000,2001  Cirrus Logic Corp.  
   6*            -- adapted from drivers by Thomas Sailer, 
   7*            -- but don't bug him; Problems should go to:
   8*            -- tom woller (twoller@crystal.cirrus.com) or
   9*               (pcaudio@crystal.cirrus.com).
  10*
  11*      This program is free software; you can redistribute it and/or modify
  12*      it under the terms of the GNU General Public License as published by
  13*      the Free Software Foundation; either version 2 of the License, or
  14*      (at your option) any later version.
  15*
  16*      This program is distributed in the hope that it will be useful,
  17*      but WITHOUT ANY WARRANTY; without even the implied warranty of
  18*      MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19*      GNU General Public License for more details.
  20*
  21*      You should have received a copy of the GNU General Public License
  22*      along with this program; if not, write to the Free Software
  23*      Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  24*
  25* Module command line parameters:
  26*   none
  27*
  28*  Supported devices:
  29*  /dev/dsp    standard /dev/dsp device, (mostly) OSS compatible
  30*  /dev/mixer  standard /dev/mixer device, (mostly) OSS compatible
  31*  /dev/midi   simple MIDI UART interface, no ioctl
  32*
  33* Modification History
  34* 08/20/00 trw - silence and no stopping DAC until release
  35* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop.
  36* 09/18/00 trw - added 16bit only record with conversion 
  37* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous 
  38*                capture/playback rates)
  39* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin  
  40*                libOSSm.so)
  41* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal)
  42* 11/03/00 trw - fixed interrupt loss/stutter, added debug.
  43* 11/10/00 bkz - added __devinit to cs4281_hw_init()
  44* 11/10/00 trw - fixed SMP and capture spinlock hang.
  45* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm.
  46* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix.
  47* 12/08/00 trw - added PM support. 
  48* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8 
  49*                (RH/Dell base), 2.2.18, 2.2.12.  cleaned up code mods by ident.
  50* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup.
  51* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use 
  52*                defaultorder-100 as power of 2 for the buffer size. example:
  53*                106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
  54* 04/02/01 trw - reworked the includes, so kgdb wouldn't get confused.
  55* 04/17/01 trw - added ifdef CONFIG_PM for 2.4.x non-pm kernels. static pmprint.
  56* 04/19/01 trw - reworked all of the wrapper macros to keep native 2.4.x code
  57*                predominate in the driver.
  58* 07/01/01 trw - added ability to modify the record source mask to alleviate
  59*                problems with toshiba systems.  also, check for toshiba 
  60*                system to set default up properly.
  61* 11/12/01 trw - removed cs4281_update_ptr() in the polling interface code.
  62*                returning with only a few bytes available in the write buffer
  63*                seems to cause some problems with some apps (xmms OSS plugin).
  64*                Also, fixed bug in cs4281_update_ptr() code to wakeup when
  65*                1/2 buffer is empty, not when completely full.
  66*
  67*******************************************************************************/
  68
  69/* uncomment the following line to disable building PM support into the driver */
  70//#define NOT_CS4281_PM 1 
  71
  72#include <linux/list.h>
  73#include <linux/version.h>
  74#include <linux/module.h>
  75#include <linux/string.h>
  76#include <linux/ioport.h>
  77#include <linux/sched.h>
  78#include <linux/delay.h>
  79#include <linux/sound.h>
  80#include <linux/slab.h>
  81#include <linux/soundcard.h>
  82#include <linux/pci.h>
  83#include <linux/bitops.h>
  84#include <asm/io.h>
  85#include <asm/dma.h>
  86#include <linux/init.h>
  87#include <linux/poll.h>
  88#include <linux/smp_lock.h>
  89#include <linux/wrapper.h>
  90#include <asm/uaccess.h>
  91#include <asm/hardirq.h>
  92#include "cs4281_hwdefs.h"
  93
  94EXPORT_NO_SYMBOLS;
  95
  96struct cs4281_state;
  97int cs4281_suspend(struct cs4281_state *s);
  98int cs4281_resume(struct cs4281_state *s);
  99
 100#include "cs4281_wrapper.h"
 101#include "cs4281pm-24.h"
 102
 103static void stop_dac(struct cs4281_state *s);
 104static void stop_adc(struct cs4281_state *s);
 105static void start_dac(struct cs4281_state *s);
 106static void start_adc(struct cs4281_state *s);
 107#undef OSS_DOCUMENTED_MIXER_SEMANTICS
 108
 109// --------------------------------------------------------------------- 
 110
 111#ifndef PCI_VENDOR_ID_CIRRUS
 112#define PCI_VENDOR_ID_CIRRUS          0x1013
 113#endif
 114#ifndef PCI_DEVICE_ID_CRYSTAL_CS4281
 115#define PCI_DEVICE_ID_CRYSTAL_CS4281  0x6005
 116#endif
 117
 118#ifndef SS_ID_TOSHIBA_1640CDT
 119#define SS_ID_TOSHIBA_1640CDT   0xff00
 120#endif
 121
 122#ifndef PCI_VENDOR_ID_TOSHIBA
 123#define PCI_VENDOR_ID_TOSHIBA   0x1179
 124#endif
 125
 126#define CS4281_MAGIC  ((PCI_DEVICE_ID_CRYSTAL_CS4281<<16) | PCI_VENDOR_ID_CIRRUS)
 127#define CS4281_CFLR_DEFAULT     0x00000001  /* CFLR must be in AC97 link mode */
 128#define CS4281_BA0_CPWR_DEFAULT 0x4281
 129
 130/* buffer order determines the size of the dma buffer for the driver.
 131* under Linux, a smaller buffer allows more responsiveness from many of the 
 132* applications (e.g. games).  A larger buffer allows some of the apps (esound) 
 133* to not underrun the dma buffer as easily.  As default, use 32k (order=3)
 134* rather than 64k as some of the games work more responsively.
 135* (2^N) * PAGE_SIZE = allocated buffer size
 136*
 137* also added fractional "defaultorder" inputs. if >100 then use 
 138* defaultorder-100 as power of 2 for the buffer size. example:
 139* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
 140* games are even MORE responsive now, but prone to underruns.
 141*/
 142static unsigned long defaultorder = 3;
 143MODULE_PARM(defaultorder, "i");
 144
 145/*
 146* use this module parm to invalidate recording sources 
 147* as on some machines (Toshiba Satellites... again) setting to LINE
 148* causes an error and some of the mixers (gmix) to not load.
 149*/
 150static unsigned long recsrc_invalid = 0;
 151MODULE_PARM(recsrc_invalid, "i");
 152//
 153// Turn on/off debugging compilation by commenting out "#define CSDEBUG"
 154//
 155#define CSDEBUG 1
 156#if CSDEBUG
 157#define CSDEBUG_INTERFACE 1
 158#else
 159#undef CSDEBUG_INTERFACE
 160#endif
 161//
 162// cs_debugmask areas
 163//
 164#define CS_INIT         0x00000001      // initialization and probe functions
 165#define CS_ERROR        0x00000002      // tmp debugging bit placeholder
 166#define CS_INTERRUPT    0x00000004      // interrupt handler (separate from all other)
 167#define CS_FUNCTION     0x00000008      // enter/leave functions
 168#define CS_WAVE_WRITE   0x00000010      // write information for wave
 169#define CS_WAVE_READ    0x00000020      // read information for wave
 170#define CS_MIDI_WRITE   0x00000040      // write information for midi
 171#define CS_MIDI_READ    0x00000080      // read information for midi
 172#define CS_MPU401_WRITE 0x00000100      // write information for mpu401
 173#define CS_MPU401_READ  0x00000200      // read information for mpu401
 174#define CS_OPEN         0x00000400      // all open functions in the driver
 175#define CS_RELEASE      0x00000800      // all release functions in the driver
 176#define CS_PARMS        0x00001000      // functional and operational parameters
 177#define CS_IOCTL        0x00002000      // ioctl (non-mixer)
 178#define CS_PM           0x00004000      // power management 
 179#define CS_TMP          0x10000000      // tmp debug mask bit
 180
 181#define CS_IOCTL_CMD_SUSPEND    0x1     // suspend
 182#define CS_IOCTL_CMD_RESUME     0x2     // resume
 183//
 184// CSDEBUG is usual mode is set to 1, then use the
 185// cs_debuglevel and cs_debugmask to turn on or off debugging.
 186// Debug level of 1 has been defined to be kernel errors and info
 187// that should be printed on any released driver.
 188//
 189#if CSDEBUG
 190#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;}
 191#else
 192#define CS_DBGOUT(mask,level,x)
 193#endif
 194
 195#if CSDEBUG
 196static unsigned long cs_debuglevel = 1; // levels range from 1-9
 197static unsigned long cs_debugmask = CS_INIT | CS_ERROR; // use CS_DBGOUT with various mask values
 198MODULE_PARM(cs_debuglevel, "i");
 199MODULE_PARM(cs_debugmask, "i");
 200#endif
 201#define CS_TRUE         1
 202#define CS_FALSE        0
 203
 204// MIDI buffer sizes 
 205#define MIDIINBUF  500
 206#define MIDIOUTBUF 500
 207
 208#define FMODE_MIDI_SHIFT 3
 209#define FMODE_MIDI_READ  (FMODE_READ << FMODE_MIDI_SHIFT)
 210#define FMODE_MIDI_WRITE (FMODE_WRITE << FMODE_MIDI_SHIFT)
 211
 212#define CS4281_MAJOR_VERSION    1
 213#define CS4281_MINOR_VERSION    30
 214#ifdef __ia64__
 215#define CS4281_ARCH             64      //architecture key
 216#else
 217#define CS4281_ARCH             32      //architecture key
 218#endif
 219
 220#define CS_TYPE_ADC 0
 221#define CS_TYPE_DAC 1
 222
 223static const char invalid_magic[] =
 224    KERN_CRIT "cs4281: invalid magic value\n";
 225
 226#define VALIDATE_STATE(s)                         \
 227({                                                \
 228        if (!(s) || (s)->magic != CS4281_MAGIC) { \
 229                printk(invalid_magic);            \
 230                return -ENXIO;                    \
 231        }                                         \
 232})
 233
 234struct list_head cs4281_devs = { &cs4281_devs, &cs4281_devs };
 235
 236struct cs4281_state {
 237        // magic 
 238        unsigned int magic;
 239        u16 ss_id, ss_vendor;  /* subsystem and vendor IDs from pci space */
 240
 241        // we keep the cards in a linked list 
 242        struct cs4281_state *next;
 243
 244        // pcidev is needed to turn off the DDMA controller at driver shutdown 
 245        struct pci_dev *pcidev;
 246        struct list_head list;
 247
 248        // soundcore stuff 
 249        int dev_audio;
 250        int dev_mixer;
 251        int dev_midi;
 252
 253        // hardware resources 
 254        unsigned int pBA0phys, pBA1phys;
 255        char *pBA0, *pBA1;
 256        unsigned int irq;
 257        unsigned recsrc;
 258
 259        // mixer registers 
 260        struct {
 261                unsigned short vol[10];
 262                unsigned int recsrc;
 263                unsigned int modcnt;
 264                unsigned short micpreamp;
 265        } mix;
 266
 267        // wave stuff   
 268        struct properties {
 269                unsigned fmt;
 270                unsigned fmt_original;  // original requested format
 271                unsigned channels;
 272                unsigned rate;
 273                unsigned char clkdiv;
 274        } prop_dac, prop_adc;
 275        unsigned conversion:1;  // conversion from 16 to 8 bit in progress
 276        void *tmpbuff;          // tmp buffer for sample conversions
 277        unsigned ena;
 278        spinlock_t lock;
 279        struct semaphore open_sem;
 280        struct semaphore open_sem_adc;
 281        struct semaphore open_sem_dac;
 282        mode_t open_mode;
 283        wait_queue_head_t open_wait;
 284        wait_queue_head_t open_wait_adc;
 285        wait_queue_head_t open_wait_dac;
 286
 287        dma_addr_t dmaaddr_tmpbuff;
 288        unsigned buforder_tmpbuff;      // Log base 2 of 'rawbuf' size in bytes..
 289        struct dmabuf {
 290                void *rawbuf;   // Physical address of  
 291                dma_addr_t dmaaddr;
 292                unsigned buforder;      // Log base 2 of 'rawbuf' size in bytes..
 293                unsigned numfrag;       // # of 'fragments' in the buffer.
 294                unsigned fragshift;     // Log base 2 of fragment size.
 295                unsigned hwptr, swptr;
 296                unsigned total_bytes;   // # bytes process since open.
 297                unsigned blocks;        // last returned blocks value GETOPTR
 298                unsigned wakeup;        // interrupt occurred on block 
 299                int count;
 300                unsigned underrun;      // underrun flag
 301                unsigned error; // over/underrun 
 302                wait_queue_head_t wait;
 303                // redundant, but makes calculations easier 
 304                unsigned fragsize;      // 2**fragshift..
 305                unsigned dmasize;       // 2**buforder.
 306                unsigned fragsamples;
 307                // OSS stuff 
 308                unsigned mapped:1;      // Buffer mapped in cs4281_mmap()?
 309                unsigned ready:1;       // prog_dmabuf_dac()/adc() successful?
 310                unsigned endcleared:1;
 311                unsigned type:1;        // adc or dac buffer (CS_TYPE_XXX)
 312                unsigned ossfragshift;
 313                int ossmaxfrags;
 314                unsigned subdivision;
 315        } dma_dac, dma_adc;
 316
 317        // midi stuff 
 318        struct {
 319                unsigned ird, iwr, icnt;
 320                unsigned ord, owr, ocnt;
 321                wait_queue_head_t iwait;
 322                wait_queue_head_t owait;
 323                struct timer_list timer;
 324                unsigned char ibuf[MIDIINBUF];
 325                unsigned char obuf[MIDIOUTBUF];
 326        } midi;
 327
 328#ifndef NOT_CS4281_PM
 329        struct cs4281_pm pm;
 330        struct cs4281_pipeline pl[CS4281_NUMBER_OF_PIPELINES];
 331#endif
 332};
 333
 334#if CSDEBUG
 335
 336// DEBUG ROUTINES
 337
 338#define SOUND_MIXER_CS_GETDBGLEVEL      _SIOWR('M',120, int)
 339#define SOUND_MIXER_CS_SETDBGLEVEL      _SIOWR('M',121, int)
 340#define SOUND_MIXER_CS_GETDBGMASK       _SIOWR('M',122, int)
 341#define SOUND_MIXER_CS_SETDBGMASK       _SIOWR('M',123, int)
 342
 343#define SOUND_MIXER_CS_APM              _SIOWR('M',124, int)
 344
 345
 346static void cs_printioctl(unsigned int x)
 347{
 348        unsigned int i;
 349        unsigned char vidx;
 350        // Index of mixtable1[] member is Device ID 
 351        // and must be <= SOUND_MIXER_NRDEVICES.
 352        // Value of array member is index into s->mix.vol[]
 353        static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
 354                [SOUND_MIXER_PCM] = 1,  // voice 
 355                [SOUND_MIXER_LINE1] = 2,        // AUX
 356                [SOUND_MIXER_CD] = 3,   // CD 
 357                [SOUND_MIXER_LINE] = 4, // Line 
 358                [SOUND_MIXER_SYNTH] = 5,        // FM
 359                [SOUND_MIXER_MIC] = 6,  // Mic 
 360                [SOUND_MIXER_SPEAKER] = 7,      // Speaker 
 361                [SOUND_MIXER_RECLEV] = 8,       // Recording level 
 362                [SOUND_MIXER_VOLUME] = 9        // Master Volume 
 363        };
 364
 365        switch (x) {
 366        case SOUND_MIXER_CS_GETDBGMASK:
 367                CS_DBGOUT(CS_IOCTL, 4,
 368                          printk("SOUND_MIXER_CS_GETDBGMASK:\n"));
 369                break;
 370        case SOUND_MIXER_CS_GETDBGLEVEL:
 371                CS_DBGOUT(CS_IOCTL, 4,
 372                          printk("SOUND_MIXER_CS_GETDBGLEVEL:\n"));
 373                break;
 374        case SOUND_MIXER_CS_SETDBGMASK:
 375                CS_DBGOUT(CS_IOCTL, 4,
 376                          printk("SOUND_MIXER_CS_SETDBGMASK:\n"));
 377                break;
 378        case SOUND_MIXER_CS_SETDBGLEVEL:
 379                CS_DBGOUT(CS_IOCTL, 4,
 380                          printk("SOUND_MIXER_CS_SETDBGLEVEL:\n"));
 381                break;
 382        case OSS_GETVERSION:
 383                CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n"));
 384                break;
 385        case SNDCTL_DSP_SYNC:
 386                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n"));
 387                break;
 388        case SNDCTL_DSP_SETDUPLEX:
 389                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n"));
 390                break;
 391        case SNDCTL_DSP_GETCAPS:
 392                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n"));
 393                break;
 394        case SNDCTL_DSP_RESET:
 395                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n"));
 396                break;
 397        case SNDCTL_DSP_SPEED:
 398                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n"));
 399                break;
 400        case SNDCTL_DSP_STEREO:
 401                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n"));
 402                break;
 403        case SNDCTL_DSP_CHANNELS:
 404                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n"));
 405                break;
 406        case SNDCTL_DSP_GETFMTS:
 407                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n"));
 408                break;
 409        case SNDCTL_DSP_SETFMT:
 410                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n"));
 411                break;
 412        case SNDCTL_DSP_POST:
 413                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n"));
 414                break;
 415        case SNDCTL_DSP_GETTRIGGER:
 416                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n"));
 417                break;
 418        case SNDCTL_DSP_SETTRIGGER:
 419                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n"));
 420                break;
 421        case SNDCTL_DSP_GETOSPACE:
 422                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n"));
 423                break;
 424        case SNDCTL_DSP_GETISPACE:
 425                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n"));
 426                break;
 427        case SNDCTL_DSP_NONBLOCK:
 428                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n"));
 429                break;
 430        case SNDCTL_DSP_GETODELAY:
 431                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n"));
 432                break;
 433        case SNDCTL_DSP_GETIPTR:
 434                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n"));
 435                break;
 436        case SNDCTL_DSP_GETOPTR:
 437                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n"));
 438                break;
 439        case SNDCTL_DSP_GETBLKSIZE:
 440                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n"));
 441                break;
 442        case SNDCTL_DSP_SETFRAGMENT:
 443                CS_DBGOUT(CS_IOCTL, 4,
 444                          printk("SNDCTL_DSP_SETFRAGMENT:\n"));
 445                break;
 446        case SNDCTL_DSP_SUBDIVIDE:
 447                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n"));
 448                break;
 449        case SOUND_PCM_READ_RATE:
 450                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n"));
 451                break;
 452        case SOUND_PCM_READ_CHANNELS:
 453                CS_DBGOUT(CS_IOCTL, 4,
 454                          printk("SOUND_PCM_READ_CHANNELS:\n"));
 455                break;
 456        case SOUND_PCM_READ_BITS:
 457                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n"));
 458                break;
 459        case SOUND_PCM_WRITE_FILTER:
 460                CS_DBGOUT(CS_IOCTL, 4,
 461                          printk("SOUND_PCM_WRITE_FILTER:\n"));
 462                break;
 463        case SNDCTL_DSP_SETSYNCRO:
 464                CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n"));
 465                break;
 466        case SOUND_PCM_READ_FILTER:
 467                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n"));
 468                break;
 469        case SOUND_MIXER_PRIVATE1:
 470                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n"));
 471                break;
 472        case SOUND_MIXER_PRIVATE2:
 473                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n"));
 474                break;
 475        case SOUND_MIXER_PRIVATE3:
 476                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n"));
 477                break;
 478        case SOUND_MIXER_PRIVATE4:
 479                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n"));
 480                break;
 481        case SOUND_MIXER_PRIVATE5:
 482                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n"));
 483                break;
 484        case SOUND_MIXER_INFO:
 485                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n"));
 486                break;
 487        case SOUND_OLD_MIXER_INFO:
 488                CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n"));
 489                break;
 490
 491        default:
 492                switch (_IOC_NR(x)) {
 493                case SOUND_MIXER_VOLUME:
 494                        CS_DBGOUT(CS_IOCTL, 4,
 495                                  printk("SOUND_MIXER_VOLUME:\n"));
 496                        break;
 497                case SOUND_MIXER_SPEAKER:
 498                        CS_DBGOUT(CS_IOCTL, 4,
 499                                  printk("SOUND_MIXER_SPEAKER:\n"));
 500                        break;
 501                case SOUND_MIXER_RECLEV:
 502                        CS_DBGOUT(CS_IOCTL, 4,
 503                                  printk("SOUND_MIXER_RECLEV:\n"));
 504                        break;
 505                case SOUND_MIXER_MIC:
 506                        CS_DBGOUT(CS_IOCTL, 4,
 507                                  printk("SOUND_MIXER_MIC:\n"));
 508                        break;
 509                case SOUND_MIXER_SYNTH:
 510                        CS_DBGOUT(CS_IOCTL, 4,
 511                                  printk("SOUND_MIXER_SYNTH:\n"));
 512                        break;
 513                case SOUND_MIXER_RECSRC:
 514                        CS_DBGOUT(CS_IOCTL, 4,
 515                                  printk("SOUND_MIXER_RECSRC:\n"));
 516                        break;
 517                case SOUND_MIXER_DEVMASK:
 518                        CS_DBGOUT(CS_IOCTL, 4,
 519                                  printk("SOUND_MIXER_DEVMASK:\n"));
 520                        break;
 521                case SOUND_MIXER_RECMASK:
 522                        CS_DBGOUT(CS_IOCTL, 4,
 523                                  printk("SOUND_MIXER_RECMASK:\n"));
 524                        break;
 525                case SOUND_MIXER_STEREODEVS:
 526                        CS_DBGOUT(CS_IOCTL, 4,
 527                                  printk("SOUND_MIXER_STEREODEVS:\n"));
 528                        break;
 529                case SOUND_MIXER_CAPS:
 530                        CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n"));
 531                        break;
 532                default:
 533                        i = _IOC_NR(x);
 534                        if (i >= SOUND_MIXER_NRDEVICES
 535                            || !(vidx = mixtable1[i])) {
 536                                CS_DBGOUT(CS_IOCTL, 4, printk
 537                                        ("UNKNOWN IOCTL: 0x%.8x NR=%d\n",
 538                                                x, i));
 539                        } else {
 540                                CS_DBGOUT(CS_IOCTL, 4, printk
 541                                        ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n",
 542                                                x, i));
 543                        }
 544                        break;
 545                }
 546        }
 547}
 548#endif
 549static int prog_dmabuf_adc(struct cs4281_state *s);
 550static void prog_codec(struct cs4281_state *s, unsigned type);
 551
 552// --------------------------------------------------------------------- 
 553//
 554//              Hardware Interfaces For the CS4281
 555//
 556
 557
 558//******************************************************************************
 559// "delayus()-- Delay for the specified # of microseconds.
 560//******************************************************************************
 561static void delayus(struct cs4281_state *s, u32 delay)
 562{
 563        u32 j;
 564        if ((delay > 9999) 
 565#ifndef NOT_CS4281_PM
 566        && (s->pm.flags & CS4281_PM_IDLE))
 567#else
 568        )
 569#endif
 570        {
 571                j = (delay * HZ) / 1000000;     /* calculate delay in jiffies  */
 572                if (j < 1)
 573                        j = 1;  /* minimum one jiffy. */
 574                current->state = TASK_UNINTERRUPTIBLE;
 575                schedule_timeout(j);
 576        } else
 577                udelay(delay);
 578        return;
 579}
 580
 581
 582//******************************************************************************
 583// "cs4281_read_ac97" -- Reads a word from the specified location in the
 584//               CS4281's address space(based on the BA0 register).
 585//
 586// 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 587// 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 register,
 588//                                            0h for reads.
 589// 3. Write ACCTL = Control Register = 460h for initiating the write
 590// 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 17h
 591// 5. if DCV not cleared, break and return error
 592// 6. Read ACSTS = Status Register = 464h, check VSTS bit
 593//****************************************************************************
 594static int cs4281_read_ac97(struct cs4281_state *card, u32 offset,
 595                            u32 * value)
 596{
 597        u32 count, status;
 598
 599        // Make sure that there is not data sitting
 600        // around from a previous uncompleted access.
 601        // ACSDA = Status Data Register = 47Ch
 602        status = readl(card->pBA0 + BA0_ACSDA);
 603
 604        // Setup the AC97 control registers on the CS4281 to send the
 605        // appropriate command to the AC97 to perform the read.
 606        // ACCAD = Command Address Register = 46Ch
 607        // ACCDA = Command Data Register = 470h
 608        // ACCTL = Control Register = 460h
 609        // bit DCV - will clear when process completed
 610        // bit CRW - Read command
 611        // bit VFRM - valid frame enabled
 612        // bit ESYN - ASYNC generation enabled
 613
 614        // Get the actual AC97 register from the offset
 615        writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
 616        writel(0, card->pBA0 + BA0_ACCDA);
 617        writel(ACCTL_DCV | ACCTL_CRW | ACCTL_VFRM | ACCTL_ESYN,
 618               card->pBA0 + BA0_ACCTL);
 619
 620        // Wait for the read to occur.
 621        for (count = 0; count < 100; count++) {
 622                // First, we want to wait for a short time.
 623                udelay(25);
 624
 625                // Now, check to see if the read has completed.
 626                // ACCTL = 460h, DCV should be reset by now and 460h = 17h
 627                if (!(readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV))
 628                        break;
 629        }
 630
 631        // Make sure the read completed.
 632        if (readl(card->pBA0 + BA0_ACCTL) & ACCTL_DCV)
 633                return 1;
 634
 635        // Wait for the valid status bit to go active.
 636        for (count = 0; count < 100; count++) {
 637                // Read the AC97 status register.
 638                // ACSTS = Status Register = 464h
 639                status = readl(card->pBA0 + BA0_ACSTS);
 640
 641                // See if we have valid status.
 642                // VSTS - Valid Status
 643                if (status & ACSTS_VSTS)
 644                        break;
 645                // Wait for a short while.
 646                udelay(25);
 647        }
 648
 649        // Make sure we got valid status.
 650        if (!(status & ACSTS_VSTS))
 651                return 1;
 652
 653        // Read the data returned from the AC97 register.
 654        // ACSDA = Status Data Register = 474h
 655        *value = readl(card->pBA0 + BA0_ACSDA);
 656
 657        // Success.
 658        return (0);
 659}
 660
 661
 662//****************************************************************************
 663//
 664// "cs4281_write_ac97()"-- writes a word to the specified location in the
 665// CS461x's address space (based on the part's base address zero register).
 666//
 667// 1. Write ACCAD = Command Address Register = 46Ch for AC97 register address
 668// 2. Write ACCDA = Command Data Register = 470h for data to write to AC97 reg.
 669// 3. Write ACCTL = Control Register = 460h for initiating the write
 670// 4. Read ACCTL = 460h, DCV should be reset by now and 460h = 07h
 671// 5. if DCV not cleared, break and return error
 672//
 673//****************************************************************************
 674static int cs4281_write_ac97(struct cs4281_state *card, u32 offset,
 675                             u32 value)
 676{
 677        u32 count, status=0;
 678
 679        CS_DBGOUT(CS_FUNCTION, 2,
 680                  printk(KERN_INFO "cs4281: cs_4281_write_ac97()+ \n"));
 681
 682        // Setup the AC97 control registers on the CS4281 to send the
 683        // appropriate command to the AC97 to perform the read.
 684        // ACCAD = Command Address Register = 46Ch
 685        // ACCDA = Command Data Register = 470h
 686        // ACCTL = Control Register = 460h
 687        // set DCV - will clear when process completed
 688        // reset CRW - Write command
 689        // set VFRM - valid frame enabled
 690        // set ESYN - ASYNC generation enabled
 691        // set RSTN - ARST# inactive, AC97 codec not reset
 692
 693        // Get the actual AC97 register from the offset
 694
 695        writel(offset - BA0_AC97_RESET, card->pBA0 + BA0_ACCAD);
 696        writel(value, card->pBA0 + BA0_ACCDA);
 697        writel(ACCTL_DCV | ACCTL_VFRM | ACCTL_ESYN,
 698               card->pBA0 + BA0_ACCTL);
 699
 700        // Wait for the write to occur.
 701        for (count = 0; count < 100; count++) {
 702                // First, we want to wait for a short time.
 703                udelay(25);
 704                // Now, check to see if the write has completed.
 705                // ACCTL = 460h, DCV should be reset by now and 460h = 07h
 706                status = readl(card->pBA0 + BA0_ACCTL);
 707                if (!(status & ACCTL_DCV))
 708                        break;
 709        }
 710
 711        // Make sure the write completed.
 712        if (status & ACCTL_DCV) {
 713                CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
 714                        "cs4281: cs_4281_write_ac97()- unable to write. ACCTL_DCV active\n"));
 715                return 1;
 716        }
 717        CS_DBGOUT(CS_FUNCTION, 2,
 718                  printk(KERN_INFO "cs4281: cs_4281_write_ac97()- 0\n"));
 719        // Success.
 720        return 0;
 721}
 722
 723
 724//******************************************************************************
 725// "Init4281()" -- Bring up the part.
 726//******************************************************************************
 727static __devinit int cs4281_hw_init(struct cs4281_state *card)
 728{
 729        u32 ac97_slotid;
 730        u32 temp1, temp2;
 731
 732        CS_DBGOUT(CS_FUNCTION, 2,
 733                  printk(KERN_INFO "cs4281: cs4281_hw_init()+ \n"));
 734#ifndef NOT_CS4281_PM
 735        if(!card)
 736                return 1;
 737#endif
 738        temp2 = readl(card->pBA0 + BA0_CFLR);
 739        CS_DBGOUT(CS_INIT | CS_ERROR | CS_PARMS, 4, printk(KERN_INFO 
 740                "cs4281: cs4281_hw_init() CFLR 0x%x\n", temp2));
 741        if(temp2 != CS4281_CFLR_DEFAULT)
 742        {
 743                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO 
 744                        "cs4281: cs4281_hw_init() CFLR invalid - resetting from 0x%x to 0x%x\n",
 745                                temp2,CS4281_CFLR_DEFAULT));
 746                temp2 = readl(card->pBA0 + BA0_CWPR);
 747                if(temp2 != CS4281_BA0_CPWR_DEFAULT)
 748                {
 749                        writel(CS4281_BA0_CPWR_DEFAULT, card->pBA0 + BA0_CWPR);
 750                        temp2 = readl(card->pBA0 + BA0_CWPR);
 751                        if(temp2 != CS4281_BA0_CPWR_DEFAULT)
 752                        {
 753                          CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO 
 754                                "cs4281: cs4281_hw_init() Invalid hardware - unable to configure CPWR (0x%x)\n",
 755                                        temp2));
 756                          return 1;
 757                        }
 758                }
 759                writel(CS4281_CFLR_DEFAULT, card->pBA0 + BA0_CFLR);
 760                temp2 = readl(card->pBA0 + BA0_CFLR);
 761                if(temp2 != CS4281_CFLR_DEFAULT)
 762                {
 763                        CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO 
 764                                "cs4281: cs4281_hw_init() Invalid hardware - unable to configure CFLR (0x%x)\n",
 765                                        temp2));
 766                        return 1;
 767                }
 768        }
 769
 770        //***************************************7
 771        //  Set up the Sound System Configuration
 772        //***************************************
 773
 774        // Set the 'Configuration Write Protect' register
 775        // to 4281h.  Allows vendor-defined configuration
 776        // space between 0e4h and 0ffh to be written.
 777
 778        writel(0x4281, card->pBA0 + BA0_CWPR);  // (3e0h)
 779
 780        // (0), Blast the clock control register to zero so that the
 781        // PLL starts out in a known state, and blast the master serial
 782        // port control register to zero so that the serial ports also
 783        // start out in a known state.
 784
 785        writel(0, card->pBA0 + BA0_CLKCR1);     // (400h)
 786        writel(0, card->pBA0 + BA0_SERMC);      // (420h)
 787
 788
 789        // (1), Make ESYN go to zero to turn off
 790        // the Sync pulse on the AC97 link.
 791
 792        writel(0, card->pBA0 + BA0_ACCTL);
 793        udelay(50);
 794
 795
 796        // (2) Drive the ARST# pin low for a minimum of 1uS (as defined in
 797        // the AC97 spec) and then drive it high.  This is done for non
 798        // AC97 modes since there might be logic external to the CS461x
 799        // that uses the ARST# line for a reset.
 800
 801        writel(0, card->pBA0 + BA0_SPMC);       // (3ech)
 802        udelay(100);
 803        writel(SPMC_RSTN, card->pBA0 + BA0_SPMC);
 804        delayus(card,50000);            // Wait 50 ms for ABITCLK to become stable.
 805
 806        // (3) Turn on the Sound System Clocks.
 807        writel(CLKCR1_PLLP, card->pBA0 + BA0_CLKCR1);   // (400h)
 808        delayus(card,50000);            // Wait for the PLL to stabilize.
 809        // Turn on clocking of the core (CLKCR1(400h) = 0x00000030)
 810        writel(CLKCR1_PLLP | CLKCR1_SWCE, card->pBA0 + BA0_CLKCR1);
 811
 812        // (4) Power on everything for now..
 813        writel(0x7E, card->pBA0 + BA0_SSPM);    // (740h)
 814
 815        // (5) Wait for clock stabilization.
 816        for (temp1 = 0; temp1 < 1000; temp1++) {
 817                udelay(1000);
 818                if (readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)
 819                        break;
 820        }
 821        if (!(readl(card->pBA0 + BA0_CLKCR1) & CLKCR1_DLLRDY)) {
 822                CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR 
 823                        "cs4281: DLLRDY failed!\n"));
 824                return -EIO;
 825        }
 826        // (6) Enable ASYNC generation.
 827        writel(ACCTL_ESYN, card->pBA0 + BA0_ACCTL);     // (460h)
 828
 829        // Now wait 'for a short while' to allow the  AC97
 830        // part to start generating bit clock. (so we don't
 831        // Try to start the PLL without an input clock.)
 832        delayus(card,50000);
 833
 834        // Set the serial port timing configuration, so that the
 835        // clock control circuit gets its clock from the right place.
 836        writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
 837
 838        // (7) Wait for the codec ready signal from the AC97 codec.
 839
 840        for (temp1 = 0; temp1 < 1000; temp1++) {
 841                // Delay a mil to let things settle out and
 842                // to prevent retrying the read too quickly.
 843                udelay(1000);
 844                if (readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY) // If ready,  (464h)
 845                        break;  //   exit the 'for' loop.
 846        }
 847        if (!(readl(card->pBA0 + BA0_ACSTS) & ACSTS_CRDY))      // If never came ready,
 848        {
 849                CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
 850                         "cs4281: ACSTS never came ready!\n"));
 851                return -EIO;    //   exit initialization.
 852        }
 853        // (8) Assert the 'valid frame' signal so we can
 854        // begin sending commands to the AC97 codec.
 855        writel(ACCTL_VFRM | ACCTL_ESYN, card->pBA0 + BA0_ACCTL);        // (460h)
 856
 857        // (9), Wait until CODEC calibration is finished.
 858        // Print an error message if it doesn't.
 859        for (temp1 = 0; temp1 < 1000; temp1++) {
 860                delayus(card,10000);
 861                // Read the AC97 Powerdown Control/Status Register.
 862                cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp2);
 863                if ((temp2 & 0x0000000F) == 0x0000000F)
 864                        break;
 865        }
 866        if ((temp2 & 0x0000000F) != 0x0000000F) {
 867                CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_ERR
 868                        "cs4281: Codec failed to calibrate.  Status = %.8x.\n",
 869                                temp2));
 870                return -EIO;
 871        }
 872        // (10), Set the serial port timing configuration, so that the
 873        // clock control circuit gets its clock from the right place.
 874        writel(SERMC_PTC_AC97, card->pBA0 + BA0_SERMC); // (420h)=2.
 875
 876
 877        // (11) Wait until we've sampled input slots 3 & 4 as valid, meaning
 878        // that the codec is pumping ADC data across the AC link.
 879        for (temp1 = 0; temp1 < 1000; temp1++) {
 880                // Delay a mil to let things settle out and
 881                // to prevent retrying the read too quickly.
 882                delayus(card,1000);     //(test)
 883
 884                // Read the input slot valid register;  See
 885                // if input slots 3 and 4 are valid yet.
 886                if (
 887                    (readl(card->pBA0 + BA0_ACISV) &
 888                     (ACISV_ISV3 | ACISV_ISV4)) ==
 889                    (ACISV_ISV3 | ACISV_ISV4)) break;   // Exit the 'for' if slots are valid.
 890        }
 891        // If we never got valid data, exit initialization.
 892        if ((readl(card->pBA0 + BA0_ACISV) & (ACISV_ISV3 | ACISV_ISV4))
 893            != (ACISV_ISV3 | ACISV_ISV4)) {
 894                CS_DBGOUT(CS_FUNCTION, 2,
 895                          printk(KERN_ERR
 896                                 "cs4281: Never got valid data!\n"));
 897                return -EIO;    // If no valid data, exit initialization.
 898        }
 899        // (12), Start digital data transfer of audio data to the codec.
 900        writel(ACOSV_SLV3 | ACOSV_SLV4, card->pBA0 + BA0_ACOSV);        // (468h)
 901
 902
 903        //**************************************
 904        // Unmute the Master and Alternate
 905        // (headphone) volumes.  Set to max.
 906        //**************************************
 907        cs4281_write_ac97(card, BA0_AC97_HEADPHONE_VOLUME, 0);
 908        cs4281_write_ac97(card, BA0_AC97_MASTER_VOLUME, 0);
 909
 910        //******************************************
 911        // Power on the DAC(AddDACUser()from main())
 912        //******************************************
 913        cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 914        cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfdff);
 915
 916        // Wait until we sample a DAC ready state.
 917        for (temp2 = 0; temp2 < 32; temp2++) {
 918                // Let's wait a mil to let things settle.
 919                delayus(card,1000);
 920                // Read the current state of the power control reg.
 921                cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 922                // If the DAC ready state bit is set, stop waiting.
 923                if (temp1 & 0x2)
 924                        break;
 925        }
 926
 927        //******************************************
 928        // Power on the ADC(AddADCUser()from main())
 929        //******************************************
 930        cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 931        cs4281_write_ac97(card, BA0_AC97_POWERDOWN, temp1 &= 0xfeff);
 932
 933        // Wait until we sample ADC ready state.
 934        for (temp2 = 0; temp2 < 32; temp2++) {
 935                // Let's wait a mil to let things settle.
 936                delayus(card,1000);
 937                // Read the current state of the power control reg.
 938                cs4281_read_ac97(card, BA0_AC97_POWERDOWN, &temp1);
 939                // If the ADC ready state bit is set, stop waiting.
 940                if (temp1 & 0x1)
 941                        break;
 942        }
 943        // Set up 4281 Register contents that
 944        // don't change for boot duration.
 945
 946        // For playback, we map AC97 slot 3 and 4(Left
 947        // & Right PCM playback) to DMA Channel 0.
 948        // Set the fifo to be 15 bytes at offset zero.
 949
 950        ac97_slotid = 0x01000f00;       // FCR0.RS[4:0]=1(=>slot4, right PCM playback).
 951        // FCR0.LS[4:0]=0(=>slot3, left PCM playback).
 952        // FCR0.SZ[6-0]=15; FCR0.OF[6-0]=0.
 953        writel(ac97_slotid, card->pBA0 + BA0_FCR0);     // (180h)
 954        writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR0);  // Turn on FIFO Enable.
 955
 956        // For capture, we map AC97 slot 10 and 11(Left
 957        // and Right PCM Record) to DMA Channel 1.
 958        // Set the fifo to be 15 bytes at offset sixteen.
 959        ac97_slotid = 0x0B0A0f10;       // FCR1.RS[4:0]=11(=>slot11, right PCM record).
 960        // FCR1.LS[4:0]=10(=>slot10, left PCM record).
 961        // FCR1.SZ[6-0]=15; FCR1.OF[6-0]=16.
 962        writel(ac97_slotid | FCRn_PSH, card->pBA0 + BA0_FCR1);  // (184h)
 963        writel(ac97_slotid | FCRn_FEN, card->pBA0 + BA0_FCR1);  // Turn on FIFO Enable.
 964
 965        // Map the Playback SRC to the same AC97 slots(3 & 4--
 966        // --Playback left & right)as DMA channel 0.
 967        // Map the record SRC to the same AC97 slots(10 & 11--
 968        // -- Record left & right) as DMA channel 1.
 969
 970        ac97_slotid = 0x0b0a0100;       // SCRSA.PRSS[4:0]=1(=>slot4, right PCM playback).
 971        // SCRSA.PLSS[4:0]=0(=>slot3, left PCM playback).
 972        // SCRSA.CRSS[4:0]=11(=>slot11, right PCM record)
 973        // SCRSA.CLSS[4:0]=10(=>slot10, left PCM record).
 974        writel(ac97_slotid, card->pBA0 + BA0_SRCSA);    // (75ch)
 975
 976        // Set 'Half Terminal Count Interrupt Enable' and 'Terminal
 977        // Count Interrupt Enable' in DMA Control Registers 0 & 1.
 978        // Set 'MSK' flag to 1 to keep the DMA engines paused.
 979        temp1 = (DCRn_HTCIE | DCRn_TCIE | DCRn_MSK);    // (00030001h)
 980        writel(temp1, card->pBA0 + BA0_DCR0);   // (154h
 981        writel(temp1, card->pBA0 + BA0_DCR1);   // (15ch)
 982
 983        // Set 'Auto-Initialize Control' to 'enabled'; For playback,
 984        // set 'Transfer Type Control'(TR[1:0]) to 'read transfer',
 985        // for record, set Transfer Type Control to 'write transfer'.
 986        // All other bits set to zero;  Some will be changed @ transfer start.
 987        temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_READ);  // (20000018h)
 988        writel(temp1, card->pBA0 + BA0_DMR0);   // (150h)
 989        temp1 = (DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE); // (20000014h)
 990        writel(temp1, card->pBA0 + BA0_DMR1);   // (158h)
 991
 992        // Enable DMA interrupts generally, and
 993        // DMA0 & DMA1 interrupts specifically.
 994        temp1 = readl(card->pBA0 + BA0_HIMR) & 0xfffbfcff;
 995        writel(temp1, card->pBA0 + BA0_HIMR);
 996
 997        CS_DBGOUT(CS_FUNCTION, 2,
 998                  printk(KERN_INFO "cs4281: cs4281_hw_init()- 0\n"));
 999        return 0;
1000}
1001
1002#ifndef NOT_CS4281_PM
1003static void printpm(struct cs4281_state *s)
1004{
1005        CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
1006        CS_DBGOUT(CS_PM, 9, printk("flags:0x%x u32CLKCR1_SAVE: 0%x u32SSPMValue: 0x%x\n",
1007                (unsigned)s->pm.flags,s->pm.u32CLKCR1_SAVE,s->pm.u32SSPMValue));
1008        CS_DBGOUT(CS_PM, 9, printk("u32PPLVCvalue: 0x%x u32PPRVCvalue: 0x%x\n",
1009                s->pm.u32PPLVCvalue,s->pm.u32PPRVCvalue));
1010        CS_DBGOUT(CS_PM, 9, printk("u32FMLVCvalue: 0x%x u32FMRVCvalue: 0x%x\n",
1011                s->pm.u32FMLVCvalue,s->pm.u32FMRVCvalue));
1012        CS_DBGOUT(CS_PM, 9, printk("u32GPIORvalue: 0x%x u32JSCTLvalue: 0x%x\n",
1013                s->pm.u32GPIORvalue,s->pm.u32JSCTLvalue));
1014        CS_DBGOUT(CS_PM, 9, printk("u32SSCR: 0x%x u32SRCSA: 0x%x\n",
1015                s->pm.u32SSCR,s->pm.u32SRCSA));
1016        CS_DBGOUT(CS_PM, 9, printk("u32DacASR: 0x%x u32AdcASR: 0x%x\n",
1017                s->pm.u32DacASR,s->pm.u32AdcASR));
1018        CS_DBGOUT(CS_PM, 9, printk("u32DacSR: 0x%x u32AdcSR: 0x%x\n",
1019                s->pm.u32DacSR,s->pm.u32AdcSR));
1020        CS_DBGOUT(CS_PM, 9, printk("u32MIDCR_Save: 0x%x\n",
1021                s->pm.u32MIDCR_Save));
1022
1023}
1024static void printpipe(struct cs4281_pipeline *pl)
1025{
1026
1027        CS_DBGOUT(CS_PM, 9, printk("pm struct:\n"));
1028        CS_DBGOUT(CS_PM, 9, printk("flags:0x%x number: 0%x\n",
1029                (unsigned)pl->flags,pl->number));
1030        CS_DBGOUT(CS_PM, 9, printk("u32DBAnValue: 0%x u32DBCnValue: 0x%x\n",
1031                pl->u32DBAnValue,pl->u32DBCnValue));
1032        CS_DBGOUT(CS_PM, 9, printk("u32DMRnValue: 0x%x u32DCRnValue: 0x%x\n",
1033                pl->u32DMRnValue,pl->u32DCRnValue));
1034        CS_DBGOUT(CS_PM, 9, printk("u32DBAnAddress: 0x%x u32DBCnAddress: 0x%x\n",
1035                pl->u32DBAnAddress,pl->u32DBCnAddress));
1036        CS_DBGOUT(CS_PM, 9, printk("u32DCAnAddress: 0x%x u32DCCnAddress: 0x%x\n",
1037                pl->u32DCCnAddress,pl->u32DCCnAddress));
1038        CS_DBGOUT(CS_PM, 9, printk("u32DMRnAddress: 0x%x u32DCRnAddress: 0x%x\n",
1039                pl->u32DMRnAddress,pl->u32DCRnAddress));
1040        CS_DBGOUT(CS_PM, 9, printk("u32HDSRnAddress: 0x%x u32DBAn_Save: 0x%x\n",
1041                pl->u32HDSRnAddress,pl->u32DBAn_Save));
1042        CS_DBGOUT(CS_PM, 9, printk("u32DBCn_Save: 0x%x u32DMRn_Save: 0x%x\n",
1043                pl->u32DBCn_Save,pl->u32DMRn_Save));
1044        CS_DBGOUT(CS_PM, 9, printk("u32DCRn_Save: 0x%x u32DCCn_Save: 0x%x\n",
1045                pl->u32DCRn_Save,pl->u32DCCn_Save));
1046        CS_DBGOUT(CS_PM, 9, printk("u32DCAn_Save: 0x%x\n",
1047                pl->u32DCAn_Save));
1048        CS_DBGOUT(CS_PM, 9, printk("u32FCRn_Save: 0x%x u32FSICn_Save: 0x%x\n",
1049                pl->u32FCRn_Save,pl->u32FSICn_Save));
1050        CS_DBGOUT(CS_PM, 9, printk("u32FCRnValue: 0x%x u32FSICnValue: 0x%x\n",
1051                pl->u32FCRnValue,pl->u32FSICnValue));
1052        CS_DBGOUT(CS_PM, 9, printk("u32FCRnAddress: 0x%x u32FSICnAddress: 0x%x\n",
1053                pl->u32FCRnAddress,pl->u32FSICnAddress));
1054        CS_DBGOUT(CS_PM, 9, printk("u32FPDRnValue: 0x%x u32FPDRnAddress: 0x%x\n",
1055                pl->u32FPDRnValue,pl->u32FPDRnAddress));
1056}
1057static void printpipelines(struct cs4281_state *s)
1058{
1059        int i;
1060        for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
1061        {
1062                if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1063                {
1064                        printpipe(&s->pl[i]);
1065                }
1066        }
1067}
1068/****************************************************************************
1069*
1070*  Suspend - save the ac97 regs, mute the outputs and power down the part.  
1071*
1072****************************************************************************/
1073void cs4281_ac97_suspend(struct cs4281_state *s)
1074{
1075        int Count,i;
1076
1077        CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()+\n"));
1078
1079        for(Count = 0x2, i=0; (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1080                        && (i < CS4281_AC97_NUMBER_RESTORE_REGS); 
1081                Count += 2, i++)
1082        {
1083                cs4281_read_ac97(s, BA0_AC97_RESET + Count, &s->pm.ac97[i]);
1084        }
1085/*
1086* Save the ac97 volume registers as well as the current powerdown state.
1087* Now, mute the all the outputs (master, headphone, and mono), as well
1088* as the PCM volume, in preparation for powering down the entire part.
1089*/ 
1090        cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME, &s->pm.u32AC97_master_volume);
1091        cs4281_read_ac97(s, BA0_AC97_HEADPHONE_VOLUME, &s->pm.u32AC97_headphone_volume);
1092        cs4281_read_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, &s->pm.u32AC97_master_volume_mono);
1093        cs4281_read_ac97(s, BA0_AC97_PCM_OUT_VOLUME, &s->pm.u32AC97_pcm_out_volume);
1094                
1095        cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, 0x8000);
1096        cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, 0x8000);
1097        cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME_MONO, 0x8000);
1098        cs4281_write_ac97(s, BA0_AC97_PCM_OUT_VOLUME, 0x8000);
1099
1100        cs4281_read_ac97(s, BA0_AC97_POWERDOWN, &s->pm.u32AC97_powerdown);
1101        cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE, &s->pm.u32AC97_general_purpose);
1102
1103/*
1104* And power down everything on the AC97 codec.
1105*/
1106        cs4281_write_ac97(s, BA0_AC97_POWERDOWN, 0xff00);
1107        CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_suspend()-\n"));
1108}
1109
1110/****************************************************************************
1111*
1112*  Resume - power up the part and restore its registers..  
1113*
1114****************************************************************************/
1115void cs4281_ac97_resume(struct cs4281_state *s)
1116{
1117        int Count,i;
1118
1119        CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()+\n"));
1120
1121/* do not save the power state registers at this time
1122    //
1123    // If we saved away the power control registers, write them into the
1124    // shadows so those saved values get restored instead of the current
1125    // shadowed value.
1126    //
1127    if( bPowerStateSaved )
1128    {
1129        PokeShadow( 0x26, ulSaveReg0x26 );
1130        bPowerStateSaved = FALSE;
1131    }
1132*/
1133
1134//
1135// First, we restore the state of the general purpose register.  This
1136// contains the mic select (mic1 or mic2) and if we restore this after
1137// we restore the mic volume/boost state and mic2 was selected at
1138// suspend time, we will end up with a brief period of time where mic1
1139// is selected with the volume/boost settings for mic2, causing
1140// acoustic feedback.  So we restore the general purpose register
1141// first, thereby getting the correct mic selected before we restore
1142// the mic volume/boost.
1143//
1144        cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE, s->pm.u32AC97_general_purpose);
1145
1146//
1147// Now, while the outputs are still muted, restore the state of power
1148// on the AC97 part.
1149//
1150        cs4281_write_ac97(s, BA0_AC97_POWERDOWN, s->pm.u32AC97_powerdown);
1151
1152/*
1153* Restore just the first set of registers, from register number
1154* 0x02 to the register number that ulHighestRegToRestore specifies.
1155*/
1156        for(    Count = 0x2, i=0; 
1157                (Count <= CS4281_AC97_HIGHESTREGTORESTORE)
1158                        && (i < CS4281_AC97_NUMBER_RESTORE_REGS); 
1159                Count += 2, i++)
1160        {
1161                cs4281_write_ac97(s, BA0_AC97_RESET + Count, s->pm.ac97[i]);
1162        }
1163        CS_DBGOUT(CS_PM, 9, printk("cs4281: cs4281_ac97_resume()-\n"));
1164}
1165
1166/* do not save the power state registers at this time
1167****************************************************************************
1168*
1169*  SavePowerState - Save the power registers away. 
1170*
1171****************************************************************************
1172void 
1173HWAC97codec::SavePowerState(void)
1174{
1175    ENTRY(TM_OBJECTCALLS, "HWAC97codec::SavePowerState()\r\n");
1176
1177    ulSaveReg0x26 = PeekShadow(0x26);
1178
1179    //
1180    // Note that we have saved registers that need to be restored during a
1181    // resume instead of ulAC97Regs[].
1182    //
1183    bPowerStateSaved = TRUE;
1184
1185} // SavePowerState
1186*/
1187
1188void cs4281_SuspendFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1189{
1190 /*
1191 * We need to save the contents of the BASIC FIFO Registers.
1192 */
1193        pl->u32FCRn_Save = readl(s->pBA0 + pl->u32FCRnAddress);
1194        pl->u32FSICn_Save = readl(s->pBA0 + pl->u32FSICnAddress);
1195}
1196void cs4281_ResumeFIFO(struct cs4281_state *s, struct cs4281_pipeline *pl)
1197{
1198 /*
1199 * We need to restore the contents of the BASIC FIFO Registers.
1200 */
1201        writel(pl->u32FCRn_Save,s->pBA0 + pl->u32FCRnAddress);
1202        writel(pl->u32FSICn_Save,s->pBA0 + pl->u32FSICnAddress);
1203}
1204void cs4281_SuspendDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1205{
1206        //
1207        // We need to save the contents of the BASIC DMA Registers.
1208        //
1209        pl->u32DBAn_Save = readl(s->pBA0 + pl->u32DBAnAddress);
1210        pl->u32DBCn_Save = readl(s->pBA0 + pl->u32DBCnAddress);
1211        pl->u32DMRn_Save = readl(s->pBA0 + pl->u32DMRnAddress);
1212        pl->u32DCRn_Save = readl(s->pBA0 + pl->u32DCRnAddress);
1213        pl->u32DCCn_Save = readl(s->pBA0 + pl->u32DCCnAddress);
1214        pl->u32DCAn_Save = readl(s->pBA0 + pl->u32DCAnAddress);
1215}
1216void cs4281_ResumeDMAengine(struct cs4281_state *s, struct cs4281_pipeline *pl)
1217{
1218        //
1219        // We need to save the contents of the BASIC DMA Registers.
1220        //
1221        writel( pl->u32DBAn_Save, s->pBA0 + pl->u32DBAnAddress);
1222        writel( pl->u32DBCn_Save, s->pBA0 + pl->u32DBCnAddress);
1223        writel( pl->u32DMRn_Save, s->pBA0 + pl->u32DMRnAddress);
1224        writel( pl->u32DCRn_Save, s->pBA0 + pl->u32DCRnAddress);
1225        writel( pl->u32DCCn_Save, s->pBA0 + pl->u32DCCnAddress);
1226        writel( pl->u32DCAn_Save, s->pBA0 + pl->u32DCAnAddress);
1227}
1228
1229int cs4281_suspend(struct cs4281_state *s)
1230{
1231        int i;
1232        u32 u32CLKCR1;
1233        struct cs4281_pm *pm = &s->pm;
1234        CS_DBGOUT(CS_PM | CS_FUNCTION, 9, 
1235                printk("cs4281: cs4281_suspend()+ flags=%d\n",
1236                        (unsigned)s->pm.flags));
1237/*
1238* check the current state, only suspend if IDLE
1239*/
1240        if(!(s->pm.flags & CS4281_PM_IDLE))
1241        {
1242                CS_DBGOUT(CS_PM | CS_ERROR, 2, 
1243                        printk("cs4281: cs4281_suspend() unable to suspend, not IDLE\n"));
1244                return 1;
1245        }
1246        s->pm.flags &= ~CS4281_PM_IDLE;
1247        s->pm.flags |= CS4281_PM_SUSPENDING;
1248
1249//
1250// Gershwin CLKRUN - Set CKRA
1251//
1252        u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1253
1254        pm->u32CLKCR1_SAVE = u32CLKCR1;
1255        if(!(u32CLKCR1 & 0x00010000 ) )
1256                writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1257
1258//
1259// First, turn on the clocks (yikes) to the devices, so that they will
1260// respond when we try to save their state.
1261//
1262        if(!(u32CLKCR1 & CLKCR1_SWCE))
1263        {
1264                writel(u32CLKCR1 | CLKCR1_SWCE , s->pBA0 + BA0_CLKCR1);
1265        }
1266    
1267        //
1268        // Save the power state
1269        //
1270        pm->u32SSPMValue = readl(s->pBA0 + BA0_SSPM);
1271
1272        //
1273        // Disable interrupts.
1274        //
1275        writel(HICR_CHGM, s->pBA0 + BA0_HICR);
1276
1277        //
1278        // Save the PCM Playback Left and Right Volume Control.
1279        //
1280        pm->u32PPLVCvalue = readl(s->pBA0 + BA0_PPLVC);
1281        pm->u32PPRVCvalue = readl(s->pBA0 + BA0_PPRVC);
1282
1283        //
1284        // Save the FM Synthesis Left and Right Volume Control.
1285        //
1286        pm->u32FMLVCvalue = readl(s->pBA0 + BA0_FMLVC);
1287        pm->u32FMRVCvalue = readl(s->pBA0 + BA0_FMRVC);
1288
1289        //
1290        // Save the GPIOR value.
1291        //
1292        pm->u32GPIORvalue = readl(s->pBA0 + BA0_GPIOR);
1293
1294        //
1295        // Save the JSCTL value.
1296        //
1297        pm->u32JSCTLvalue = readl(s->pBA0 + BA0_GPIOR);
1298
1299        //
1300        // Save Sound System Control Register
1301        //
1302        pm->u32SSCR = readl(s->pBA0 + BA0_SSCR);
1303
1304        //
1305        // Save SRC Slot Assinment register
1306        //
1307        pm->u32SRCSA = readl(s->pBA0 + BA0_SRCSA);
1308
1309        //
1310        // Save sample rate
1311        //
1312        pm->u32DacASR = readl(s->pBA0 + BA0_PASR);
1313        pm->u32AdcASR = readl(s->pBA0 + BA0_CASR);
1314        pm->u32DacSR = readl(s->pBA0 + BA0_DACSR);
1315        pm->u32AdcSR = readl(s->pBA0 + BA0_ADCSR);
1316
1317/*
1318* save the current hwptr, then stop the dac/adc
1319*/
1320        pm->u32hwptr_playback = readl(s->pBA0 + BA0_DCA0);
1321        pm->u32hwptr_capture = readl(s->pBA0 + BA0_DCA1);
1322        stop_dac(s);
1323        stop_adc(s);
1324
1325        //
1326        // Loop through all of the PipeLines 
1327        //
1328        for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1329        {
1330                if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1331                {
1332                //
1333                // Ask the DMAengines and FIFOs to Suspend.
1334                //
1335                        cs4281_SuspendDMAengine(s,&s->pl[i]);
1336                        cs4281_SuspendFIFO(s,&s->pl[i]);
1337                }
1338        }
1339        //
1340        // We need to save the contents of the Midi Control Register.
1341        //
1342        pm->u32MIDCR_Save = readl(s->pBA0 + BA0_MIDCR);
1343/*
1344* save off the AC97 part information
1345*/
1346        cs4281_ac97_suspend(s);
1347    
1348        //
1349        // Turn off the serial ports.
1350        //
1351        writel(0, s->pBA0 + BA0_SERMC);
1352
1353        //
1354        // Power off FM, Joystick, AC link, 
1355        //
1356        writel(0, s->pBA0 + BA0_SSPM);
1357
1358        //
1359        // DLL off.
1360        //
1361        writel(0, s->pBA0 + BA0_CLKCR1);
1362
1363        //
1364        // AC link off.
1365        //
1366        writel(0, s->pBA0 + BA0_SPMC);
1367
1368        //
1369        // Put the chip into D3(hot) state.
1370        //
1371        // PokeBA0(BA0_PMCS, 0x00000003);
1372
1373        //
1374        // Gershwin CLKRUN - Clear CKRA
1375        //
1376        u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1377        writel(u32CLKCR1 & 0xFFFEFFFF, s->pBA0 + BA0_CLKCR1);
1378
1379#ifdef CSDEBUG
1380        printpm(s);
1381        printpipelines(s);
1382#endif
1383
1384        s->pm.flags &= ~CS4281_PM_SUSPENDING;
1385        s->pm.flags |= CS4281_PM_SUSPENDED;
1386
1387        CS_DBGOUT(CS_PM | CS_FUNCTION, 9, 
1388                printk("cs4281: cs4281_suspend()- flags=%d\n",
1389                        (unsigned)s->pm.flags));
1390        return 0;
1391}
1392
1393int cs4281_resume(struct cs4281_state *s)
1394{
1395        int i;
1396        unsigned temp1;
1397        u32 u32CLKCR1;
1398        struct cs4281_pm *pm = &s->pm;
1399        CS_DBGOUT(CS_PM | CS_FUNCTION, 4, 
1400                printk( "cs4281: cs4281_resume()+ flags=%d\n",
1401                        (unsigned)s->pm.flags));
1402        if(!(s->pm.flags & CS4281_PM_SUSPENDED))
1403        {
1404                CS_DBGOUT(CS_PM | CS_ERROR, 2, 
1405                        printk("cs4281: cs4281_resume() unable to resume, not SUSPENDED\n"));
1406                return 1;
1407        }
1408        s->pm.flags &= ~CS4281_PM_SUSPENDED;
1409        s->pm.flags |= CS4281_PM_RESUMING;
1410
1411//
1412// Gershwin CLKRUN - Set CKRA
1413//
1414        u32CLKCR1 = readl(s->pBA0 + BA0_CLKCR1);
1415        writel(u32CLKCR1 | 0x00010000, s->pBA0 + BA0_CLKCR1);
1416
1417        //
1418        // set the power state.
1419        //
1420        //old PokeBA0(BA0_PMCS, 0);
1421
1422        //
1423        // Program the clock circuit and serial ports.
1424        //
1425        temp1 = cs4281_hw_init(s);
1426        if (temp1) {
1427                CS_DBGOUT(CS_ERROR | CS_INIT, 1,
1428                    printk(KERN_ERR
1429                        "cs4281: resume cs4281_hw_init() error.\n"));
1430                return -1;
1431        }
1432
1433        //
1434        // restore the Power state
1435        //
1436        writel(pm->u32SSPMValue, s->pBA0 + BA0_SSPM);
1437
1438        //
1439        // Set post SRC mix setting (FM or ALT48K)
1440        //
1441        writel(pm->u32SSPM_BITS, s->pBA0 + BA0_SSPM);
1442
1443        //
1444        // Loop through all of the PipeLines 
1445        //
1446        for(i = 0; i < CS4281_NUMBER_OF_PIPELINES; i++)
1447        {
1448                if(s->pl[i].flags & CS4281_PIPELINE_VALID)
1449                {
1450                //
1451                // Ask the DMAengines and FIFOs to Resume.
1452                //
1453                        cs4281_ResumeDMAengine(s,&s->pl[i]);
1454                        cs4281_ResumeFIFO(s,&s->pl[i]);
1455                }
1456        }
1457        //
1458        // We need to restore the contents of the Midi Control Register.
1459        //
1460        writel(pm->u32MIDCR_Save, s->pBA0 + BA0_MIDCR);
1461
1462        cs4281_ac97_resume(s);
1463        //
1464        // Restore the PCM Playback Left and Right Volume Control.
1465        //
1466        writel(pm->u32PPLVCvalue, s->pBA0 + BA0_PPLVC);
1467        writel(pm->u32PPRVCvalue, s->pBA0 + BA0_PPRVC);
1468
1469        //
1470        // Restore the FM Synthesis Left and Right Volume Control.
1471        //
1472        writel(pm->u32FMLVCvalue, s->pBA0 + BA0_FMLVC);
1473        writel(pm->u32FMRVCvalue, s->pBA0 + BA0_FMRVC);
1474
1475        //
1476        // Restore the JSCTL value.
1477        //
1478        writel(pm->u32JSCTLvalue, s->pBA0 + BA0_JSCTL);
1479
1480        //
1481        // Restore the GPIOR register value.
1482        //
1483        writel(pm->u32GPIORvalue, s->pBA0 + BA0_GPIOR);
1484
1485        //
1486        // Restore Sound System Control Register
1487        //
1488        writel(pm->u32SSCR, s->pBA0 + BA0_SSCR);
1489
1490        //
1491        // Restore SRC Slot Assignment register
1492        //
1493        writel(pm->u32SRCSA, s->pBA0 + BA0_SRCSA);
1494
1495        //
1496        // Restore sample rate
1497        //
1498        writel(pm->u32DacASR, s->pBA0 + BA0_PASR);
1499        writel(pm->u32AdcASR, s->pBA0 + BA0_CASR);
1500        writel(pm->u32DacSR, s->pBA0 + BA0_DACSR);
1501        writel(pm->u32AdcSR, s->pBA0 + BA0_ADCSR);
1502
1503        // 
1504        // Restore CFL1/2 registers we saved to compensate for OEM bugs.
1505        //
1506        //      PokeBA0(BA0_CFLR, ulConfig);
1507
1508        //
1509        // Gershwin CLKRUN - Clear CKRA
1510        //
1511        writel(pm->u32CLKCR1_SAVE, s->pBA0 + BA0_CLKCR1);
1512
1513        //
1514        // Enable interrupts on the part.
1515        //
1516        writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
1517
1518#ifdef CSDEBUG
1519        printpm(s);
1520        printpipelines(s);
1521#endif
1522/*
1523* change the state, restore the current hwptrs, then stop the dac/adc
1524*/
1525        s->pm.flags |= CS4281_PM_IDLE;
1526        s->pm.flags &= ~(CS4281_PM_SUSPENDING | CS4281_PM_SUSPENDED 
1527                        | CS4281_PM_RESUMING | CS4281_PM_RESUMED);
1528
1529        writel(s->pm.u32hwptr_playback, s->pBA0 + BA0_DCA0);
1530        writel(s->pm.u32hwptr_capture, s->pBA0 + BA0_DCA1);
1531        start_dac(s);
1532        start_adc(s);
1533
1534        CS_DBGOUT(CS_PM | CS_FUNCTION, 9, printk("cs4281: cs4281_resume()- flags=%d\n",
1535                (unsigned)s->pm.flags));
1536        return 0;
1537}
1538
1539#endif
1540
1541//******************************************************************************
1542// "cs4281_play_rate()" --
1543//******************************************************************************
1544static void cs4281_play_rate(struct cs4281_state *card, u32 playrate)
1545{
1546        u32 DACSRvalue = 1;
1547
1548        // Based on the sample rate, program the DACSR register.
1549        if (playrate == 8000)
1550                DACSRvalue = 5;
1551        if (playrate == 11025)
1552                DACSRvalue = 4;
1553        else if (playrate == 22050)
1554                DACSRvalue = 2;
1555        else if (playrate == 44100)
1556                DACSRvalue = 1;
1557        else if ((playrate <= 48000) && (playrate >= 6023))
1558                DACSRvalue = 24576000 / (playrate * 16);
1559        else if (playrate < 6023)
1560                // Not allowed by open.
1561                return;
1562        else if (playrate > 48000)
1563                // Not allowed by open.
1564                return;
1565        CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 2, printk(KERN_INFO
1566                "cs4281: cs4281_play_rate(): DACSRvalue=0x%.8x playrate=%d\n",
1567                        DACSRvalue, playrate));
1568        //  Write the 'sample rate select code'
1569        //  to the 'DAC Sample Rate' register.
1570        writel(DACSRvalue, card->pBA0 + BA0_DACSR);     // (744h)
1571}
1572
1573//******************************************************************************
1574// "cs4281_record_rate()" -- Initialize the record sample rate converter.
1575//******************************************************************************
1576static void cs4281_record_rate(struct cs4281_state *card, u32 outrate)
1577{
1578        u32 ADCSRvalue = 1;
1579
1580        //
1581        // Based on the sample rate, program the ADCSR register
1582        //
1583        if (outrate == 8000)
1584                ADCSRvalue = 5;
1585        if (outrate == 11025)
1586                ADCSRvalue = 4;
1587        else if (outrate == 22050)
1588                ADCSRvalue = 2;
1589        else if (outrate == 44100)
1590                ADCSRvalue = 1;
1591        else if ((outrate <= 48000) && (outrate >= 6023))
1592                ADCSRvalue = 24576000 / (outrate * 16);
1593        else if (outrate < 6023) {
1594                // Not allowed by open.
1595                return;
1596        } else if (outrate > 48000) {
1597                // Not allowed by open.
1598                return;
1599        }
1600        CS_DBGOUT(CS_WAVE_READ | CS_PARMS, 2, printk(KERN_INFO
1601                "cs4281: cs4281_record_rate(): ADCSRvalue=0x%.8x outrate=%d\n",
1602                        ADCSRvalue, outrate));
1603        //  Write the 'sample rate select code
1604        //  to the 'ADC Sample Rate' register.
1605        writel(ADCSRvalue, card->pBA0 + BA0_ADCSR);     // (748h)
1606}
1607
1608
1609
1610static void stop_dac(struct cs4281_state *s)
1611{
1612        unsigned long flags;
1613        unsigned temp1;
1614
1615        CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4281: stop_dac():\n"));
1616        spin_lock_irqsave(&s->lock, flags);
1617        s->ena &= ~FMODE_WRITE;
1618        temp1 = readl(s->pBA0 + BA0_DCR0) | DCRn_MSK;
1619        writel(temp1, s->pBA0 + BA0_DCR0);
1620
1621        spin_unlock_irqrestore(&s->lock, flags);
1622}
1623
1624
1625static void start_dac(struct cs4281_state *s)
1626{
1627        unsigned long flags;
1628        unsigned temp1;
1629
1630        CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4281: start_dac()+\n"));
1631        spin_lock_irqsave(&s->lock, flags);
1632        if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped ||
1633                                        (s->dma_dac.count > 0
1634                                        && s->dma_dac.ready))
1635#ifndef NOT_CS4281_PM
1636        && (s->pm.flags & CS4281_PM_IDLE))
1637#else
1638        )
1639#endif
1640        {
1641                s->ena |= FMODE_WRITE;
1642                temp1 = readl(s->pBA0 + BA0_DCR0) & ~DCRn_MSK;  // Clear DMA0 channel mask.
1643                writel(temp1, s->pBA0 + BA0_DCR0);      // Start DMA'ing.
1644                writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts.              
1645
1646                writel(7, s->pBA0 + BA0_PPRVC);
1647                writel(7, s->pBA0 + BA0_PPLVC);
1648                CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO
1649                        "cs4281: start_dac(): writel 0x%x start dma\n", temp1));
1650
1651        }
1652        spin_unlock_irqrestore(&s->lock, flags);
1653        CS_DBGOUT(CS_FUNCTION, 3,
1654                  printk(KERN_INFO "cs4281: start_dac()-\n"));
1655}
1656
1657
1658static void stop_adc(struct cs4281_state *s)
1659{
1660        unsigned long flags;
1661        unsigned temp1;
1662
1663        CS_DBGOUT(CS_FUNCTION, 3,
1664                  printk(KERN_INFO "cs4281: stop_adc()+\n"));
1665
1666        spin_lock_irqsave(&s->lock, flags);
1667        s->ena &= ~FMODE_READ;
1668
1669        if (s->conversion == 1) {
1670                s->conversion = 0;
1671                s->prop_adc.fmt = s->prop_adc.fmt_original;
1672        }
1673        temp1 = readl(s->pBA0 + BA0_DCR1) | DCRn_MSK;
1674        writel(temp1, s->pBA0 + BA0_DCR1);
1675        spin_unlock_irqrestore(&s->lock, flags);
1676        CS_DBGOUT(CS_FUNCTION, 3,
1677                  printk(KERN_INFO "cs4281: stop_adc()-\n"));
1678}
1679
1680
1681static void start_adc(struct cs4281_state *s)
1682{
1683        unsigned long flags;
1684        unsigned temp1;
1685
1686        CS_DBGOUT(CS_FUNCTION, 2,
1687                  printk(KERN_INFO "cs4281: start_adc()+\n"));
1688
1689        if (!(s->ena & FMODE_READ) &&
1690            (s->dma_adc.mapped || s->dma_adc.count <=
1691             (signed) (s->dma_adc.dmasize - 2 * s->dma_adc.fragsize))
1692            && s->dma_adc.ready
1693#ifndef NOT_CS4281_PM
1694        && (s->pm.flags & CS4281_PM_IDLE))
1695#else
1696        ) 
1697#endif
1698        {
1699                if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) {
1700                        // 
1701                        // now only use 16 bit capture, due to truncation issue
1702                        // in the chip, noticable distortion occurs.
1703                        // allocate buffer and then convert from 16 bit to 
1704                        // 8 bit for the user buffer.
1705                        //
1706                        s->prop_adc.fmt_original = s->prop_adc.fmt;
1707                        if (s->prop_adc.fmt & AFMT_S8) {
1708                                s->prop_adc.fmt &= ~AFMT_S8;
1709                                s->prop_adc.fmt |= AFMT_S16_LE;
1710                        }
1711                        if (s->prop_adc.fmt & AFMT_U8) {
1712                                s->prop_adc.fmt &= ~AFMT_U8;
1713                                s->prop_adc.fmt |= AFMT_U16_LE;
1714                        }
1715                        //
1716                        // prog_dmabuf_adc performs a stop_adc() but that is
1717                        // ok since we really haven't started the DMA yet.
1718                        //
1719                        prog_codec(s, CS_TYPE_ADC);
1720
1721                        if (prog_dmabuf_adc(s) != 0) {
1722                                CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO
1723                                         "cs4281: start_adc(): error in prog_dmabuf_adc\n"));
1724                        }
1725                        s->conversion = 1;
1726                }
1727                spin_lock_irqsave(&s->lock, flags);
1728                s->ena |= FMODE_READ;
1729                temp1 = readl(s->pBA0 + BA0_DCR1) & ~DCRn_MSK;  // Clear DMA1 channel mask bit.
1730                writel(temp1, s->pBA0 + BA0_DCR1);      // Start recording
1731                writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts.
1732                spin_unlock_irqrestore(&s->lock, flags);
1733
1734                CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
1735                         "cs4281: start_adc(): writel 0x%x \n", temp1));
1736        }
1737        CS_DBGOUT(CS_FUNCTION, 2,
1738                  printk(KERN_INFO "cs4281: start_adc()-\n"));
1739
1740}
1741
1742
1743// --------------------------------------------------------------------- 
1744
1745#define DMABUF_MINORDER 0       // ==> min buffer size = 8K.
1746
1747
1748extern void dealloc_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1749{
1750        struct page *map, *mapend;
1751
1752        if (db->rawbuf) {
1753                // Undo prog_dmabuf()'s marking the pages as reserved 
1754                mapend = virt_to_page(db->rawbuf + 
1755                        (PAGE_SIZE << db->buforder) - 1);
1756                for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1757                        cs4x_mem_map_unreserve(map);
1758                pci_free_consistent(s->pcidev, PAGE_SIZE << db->buforder, 
1759                            db->rawbuf, db->dmaaddr);
1760        }
1761        if (s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1762                // Undo prog_dmabuf()'s marking the pages as reserved 
1763                mapend = virt_to_page(s->tmpbuff +
1764                         (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1765                for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1766                        cs4x_mem_map_unreserve(map);
1767                pci_free_consistent(s->pcidev, PAGE_SIZE << s->buforder_tmpbuff,
1768                                    s->tmpbuff, s->dmaaddr_tmpbuff);
1769        }
1770        s->tmpbuff = NULL;
1771        db->rawbuf = NULL;
1772        db->mapped = db->ready = 0;
1773}
1774
1775static int prog_dmabuf(struct cs4281_state *s, struct dmabuf *db)
1776{
1777        int order;
1778        unsigned bytespersec, temp1;
1779        unsigned bufs, sample_shift = 0;
1780        struct page *map, *mapend;
1781        unsigned long df;
1782
1783        CS_DBGOUT(CS_FUNCTION, 2,
1784                  printk(KERN_INFO "cs4281: prog_dmabuf()+\n"));
1785        db->hwptr = db->swptr = db->total_bytes = db->count = db->error =
1786            db->endcleared = db->blocks = db->wakeup = db->underrun = 0;
1787/*
1788* check for order within limits, but do not overwrite value, check
1789* later for a fractional defaultorder (i.e. 100+).
1790*/
1791        if((defaultorder >= 0) && (defaultorder < 12))
1792                df = defaultorder;
1793        else
1794                df = 1; 
1795
1796        if (!db->rawbuf) {
1797                db->ready = db->mapped = 0;
1798                for (order = df; order >= DMABUF_MINORDER; order--)
1799                        if ( (db->rawbuf = (void *) pci_alloc_consistent(
1800                                s->pcidev, PAGE_SIZE << order, &db->dmaaddr)))
1801                                    break;
1802                if (!db->rawbuf) {
1803                        CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1804                                "cs4281: prog_dmabuf(): unable to allocate rawbuf\n"));
1805                        return -ENOMEM;
1806                }
1807                db->buforder = order;
1808                // Now mark the pages as reserved; otherwise the 
1809                // remap_page_range() in cs4281_mmap doesn't work.
1810                // 1. get index to last page in mem_map array for rawbuf.
1811                mapend = virt_to_page(db->rawbuf + 
1812                        (PAGE_SIZE << db->buforder) - 1);
1813
1814                // 2. mark each physical page in range as 'reserved'.
1815                for (map = virt_to_page(db->rawbuf); map <= mapend; map++)
1816                        cs4x_mem_map_reserve(map);
1817        }
1818        if (!s->tmpbuff && (db->type == CS_TYPE_ADC)) {
1819                for (order = df; order >= DMABUF_MINORDER;
1820                     order--)
1821                        if ( (s->tmpbuff = (void *) pci_alloc_consistent(
1822                                        s->pcidev, PAGE_SIZE << order, 
1823                                        &s->dmaaddr_tmpbuff)))
1824                                    break;
1825                if (!s->tmpbuff) {
1826                        CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
1827                                "cs4281: prog_dmabuf(): unable to allocate tmpbuff\n"));
1828                        return -ENOMEM;
1829                }
1830                s->buforder_tmpbuff = order;
1831                // Now mark the pages as reserved; otherwise the 
1832                // remap_page_range() in cs4281_mmap doesn't work.
1833                // 1. get index to last page in mem_map array for rawbuf.
1834                mapend = virt_to_page(s->tmpbuff + 
1835                                (PAGE_SIZE << s->buforder_tmpbuff) - 1);
1836
1837                // 2. mark each physical page in range as 'reserved'.
1838                for (map = virt_to_page(s->tmpbuff); map <= mapend; map++)
1839                        cs4x_mem_map_reserve(map);
1840        }
1841        if (db->type == CS_TYPE_DAC) {
1842                if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1843                        sample_shift++;
1844                if (s->prop_dac.channels > 1)
1845                        sample_shift++;
1846                bytespersec = s->prop_dac.rate << sample_shift;
1847        } else                  // CS_TYPE_ADC
1848        {
1849                if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
1850                        sample_shift++;
1851                if (s->prop_adc.channels > 1)
1852                        sample_shift++;
1853                bytespersec = s->prop_adc.rate << sample_shift;
1854        }
1855        bufs = PAGE_SIZE << db->buforder;
1856
1857/*
1858* added fractional "defaultorder" inputs. if >100 then use 
1859* defaultorder-100 as power of 2 for the buffer size. example:
1860* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size.
1861*/
1862        if(defaultorder >= 100)
1863        {
1864                bufs = 1 << (defaultorder-100);
1865        }
1866
1867#define INTERRUPT_RATE_MS       100     // Interrupt rate in milliseconds.
1868        db->numfrag = 2;
1869/* 
1870* Nominal frag size(bytes/interrupt)
1871*/
1872        temp1 = bytespersec / (1000 / INTERRUPT_RATE_MS);
1873        db->fragshift = 8;      // Min 256 bytes.
1874        while (1 << db->fragshift < temp1)      // Calc power of 2 frag size.
1875                db->fragshift += 1;
1876        db->fragsize = 1 << db->fragshift;
1877        db->dmasize = db->fragsize * 2;
1878        db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1879
1880// If the calculated size is larger than the allocated
1881//  buffer, divide the allocated buffer into 2 fragments.
1882        if (db->dmasize > bufs) {
1883
1884                db->numfrag = 2;        // Two fragments.
1885                db->fragsize = bufs >> 1;       // Each 1/2 the alloc'ed buffer.
1886                db->fragsamples = db->fragsize >> sample_shift; // # samples/fragment.
1887                db->dmasize = bufs;     // Use all the alloc'ed buffer.
1888
1889                db->fragshift = 0;      // Calculate 'fragshift'.
1890                temp1 = db->fragsize;   // update_ptr() uses it 
1891                while ((temp1 >>= 1) > 1)       // to calc 'total-bytes'
1892                        db->fragshift += 1;     // returned in DSP_GETI/OPTR. 
1893        }
1894        CS_DBGOUT(CS_PARMS, 3, printk(KERN_INFO
1895                "cs4281: prog_dmabuf(): numfrag=%d fragsize=%d fragsamples=%d fragshift=%d bufs=%d fmt=0x%x ch=%d\n",
1896                        db->numfrag, db->fragsize, db->fragsamples, 
1897                        db->fragshift, bufs, 
1898                        (db->type == CS_TYPE_DAC) ? s->prop_dac.fmt : 
1899                                s->prop_adc.fmt, 
1900                        (db->type == CS_TYPE_DAC) ? s->prop_dac.channels : 
1901                                s->prop_adc.channels));
1902        CS_DBGOUT(CS_FUNCTION, 2,
1903                  printk(KERN_INFO "cs4281: prog_dmabuf()-\n"));
1904        return 0;
1905}
1906
1907
1908static int prog_dmabuf_adc(struct cs4281_state *s)
1909{
1910        unsigned long va;
1911        unsigned count;
1912        int c;
1913        stop_adc(s);
1914        s->dma_adc.type = CS_TYPE_ADC;
1915        if ((c = prog_dmabuf(s, &s->dma_adc)))
1916                return c;
1917
1918        if (s->dma_adc.rawbuf) {
1919                memset(s->dma_adc.rawbuf,
1920                       (s->prop_adc.
1921                        fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1922                       s->dma_adc.dmasize);
1923        }
1924        if (s->tmpbuff) {
1925                memset(s->tmpbuff,
1926                       (s->prop_adc.
1927                        fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1928                       PAGE_SIZE << s->buforder_tmpbuff);
1929        }
1930
1931        va = virt_to_bus(s->dma_adc.rawbuf);
1932
1933        count = s->dma_adc.dmasize;
1934
1935        if (s->prop_adc.
1936            fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1937                    count /= 2; // 16-bit.
1938
1939        if (s->prop_adc.channels > 1)
1940                count /= 2;     // Assume stereo.
1941
1942        CS_DBGOUT(CS_WAVE_READ, 3, printk(KERN_INFO
1943                "cs4281: prog_dmabuf_adc(): count=%d va=0x%.8x\n",
1944                        count, (unsigned) va));
1945
1946        writel(va, s->pBA0 + BA0_DBA1); // Set buffer start address.
1947        writel(count - 1, s->pBA0 + BA0_DBC1);  // Set count. 
1948        s->dma_adc.ready = 1;
1949        return 0;
1950}
1951
1952
1953static int prog_dmabuf_dac(struct cs4281_state *s)
1954{
1955        unsigned long va;
1956        unsigned count;
1957        int c;
1958        stop_dac(s);
1959        s->dma_dac.type = CS_TYPE_DAC;
1960        if ((c = prog_dmabuf(s, &s->dma_dac)))
1961                return c;
1962        memset(s->dma_dac.rawbuf,
1963               (s->prop_dac.fmt & (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0,
1964               s->dma_dac.dmasize);
1965
1966        va = virt_to_bus(s->dma_dac.rawbuf);
1967
1968        count = s->dma_dac.dmasize;
1969        if (s->prop_dac.
1970            fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE))
1971                    count /= 2; // 16-bit.
1972
1973        if (s->prop_dac.channels > 1)
1974                count /= 2;     // Assume stereo.
1975
1976        writel(va, s->pBA0 + BA0_DBA0); // Set buffer start address.
1977        writel(count - 1, s->pBA0 + BA0_DBC0);  // Set count.             
1978
1979        CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO
1980                "cs4281: prog_dmabuf_dac(): count=%d va=0x%.8x\n",
1981                        count, (unsigned) va));
1982
1983        s->dma_dac.ready = 1;
1984        return 0;
1985}
1986
1987
1988static void clear_advance(void *buf, unsigned bsize, unsigned bptr,
1989                          unsigned len, unsigned char c)
1990{
1991        if (bptr + len > bsize) {
1992                unsigned x = bsize - bptr;
1993                memset(((char *) buf) + bptr, c, x);
1994                bptr = 0;
1995                len -= x;
1996        }
1997        CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO
1998                "cs4281: clear_advance(): memset %d at 0x%.8x for %d size \n",
1999                        (unsigned)c, (unsigned)((char *) buf) + bptr, len));
2000        memset(((char *) buf) + bptr, c, len);
2001}
2002
2003
2004
2005// call with spinlock held! 
2006static void cs4281_update_ptr(struct cs4281_state *s, int intflag)
2007{
2008        int diff;
2009        unsigned hwptr, va;
2010
2011        // update ADC pointer 
2012        if (s->ena & FMODE_READ) {
2013                hwptr = readl(s->pBA0 + BA0_DCA1);      // Read capture DMA address.
2014                va = virt_to_bus(s->dma_adc.rawbuf);
2015                hwptr -= (unsigned) va;
2016                diff =
2017                    (s->dma_adc.dmasize + hwptr -
2018                     s->dma_adc.hwptr) % s->dma_adc.dmasize;
2019                s->dma_adc.hwptr = hwptr;
2020                s->dma_adc.total_bytes += diff;
2021                s->dma_adc.count += diff;
2022                if (s->dma_adc.count > s->dma_adc.dmasize)
2023                        s->dma_adc.count = s->dma_adc.dmasize;
2024                if (s->dma_adc.mapped) {
2025                        if (s->dma_adc.count >= (signed) s->dma_adc.fragsize) 
2026                                wake_up(&s->dma_adc.wait);
2027                } else {
2028                        if (s->dma_adc.count > 0)
2029                                wake_up(&s->dma_adc.wait);
2030                }
2031                CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
2032                        "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
2033                                (unsigned)s, s->dma_adc.hwptr, 
2034                                s->dma_adc.total_bytes, s->dma_adc.count));
2035        }
2036        // update DAC pointer 
2037        //
2038        // check for end of buffer, means that we are going to wait for another interrupt
2039        // to allow silence to fill the fifos on the part, to keep pops down to a minimum.
2040        //
2041        if (s->ena & FMODE_WRITE) {
2042                hwptr = readl(s->pBA0 + BA0_DCA0);      // Read play DMA address.
2043                va = virt_to_bus(s->dma_dac.rawbuf);
2044                hwptr -= (unsigned) va;
2045                diff = (s->dma_dac.dmasize + hwptr -
2046                     s->dma_dac.hwptr) % s->dma_dac.dmasize;
2047                s->dma_dac.hwptr = hwptr;
2048                s->dma_dac.total_bytes += diff;
2049                if (s->dma_dac.mapped) {
2050                        s->dma_dac.count += diff;
2051                        if (s->dma_dac.count >= s->dma_dac.fragsize) {
2052                                s->dma_dac.wakeup = 1;
2053                                wake_up(&s->dma_dac.wait);
2054                                if (s->dma_dac.count > s->dma_dac.dmasize)
2055                                        s->dma_dac.count &=
2056                                            s->dma_dac.dmasize - 1;
2057                        }
2058                } else {
2059                        s->dma_dac.count -= diff;
2060                        if (s->dma_dac.count <= 0) {
2061                                //
2062                                // fill with silence, and do not shut down the DAC.
2063                                // Continue to play silence until the _release.
2064                                //
2065                                CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO
2066                                        "cs4281: cs4281_update_ptr(): memset %d at 0x%.8x for %d size \n",
2067                                                (unsigned)(s->prop_dac.fmt & 
2068                                                (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, 
2069                                                (unsigned)s->dma_dac.rawbuf, 
2070                                                s->dma_dac.dmasize));
2071                                memset(s->dma_dac.rawbuf,
2072                                       (s->prop_dac.
2073                                        fmt & (AFMT_U8 | AFMT_U16_LE)) ?
2074                                       0x80 : 0, s->dma_dac.dmasize);
2075                                if (s->dma_dac.count < 0) {
2076                                        s->dma_dac.underrun = 1;
2077                                        s->dma_dac.count = 0;
2078                                        CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO
2079                                         "cs4281: cs4281_update_ptr(): underrun\n"));
2080                                }
2081                        } else if (s->dma_dac.count <=
2082                                   (signed) s->dma_dac.fragsize
2083                                   && !s->dma_dac.endcleared) {
2084                                clear_advance(s->dma_dac.rawbuf,
2085                                              s->dma_dac.dmasize,
2086                                              s->dma_dac.swptr,
2087                                              s->dma_dac.fragsize,
2088                                              (s->prop_dac.
2089                                               fmt & (AFMT_U8 |
2090                                                      AFMT_U16_LE)) ? 0x80
2091                                              : 0);
2092                                s->dma_dac.endcleared = 1;
2093                        }
2094                        if ( (s->dma_dac.count <= (signed) s->dma_dac.dmasize/2) ||
2095                                intflag)
2096                        {
2097                                wake_up(&s->dma_dac.wait);
2098                        }
2099                }
2100                CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO
2101                        "cs4281: cs4281_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n",
2102                                (unsigned) s, s->dma_dac.hwptr, 
2103                                s->dma_dac.total_bytes, s->dma_dac.count));
2104        }
2105}
2106
2107
2108// --------------------------------------------------------------------- 
2109
2110static void prog_codec(struct cs4281_state *s, unsigned type)
2111{
2112        unsigned long flags;
2113        unsigned temp1, format;
2114
2115        CS_DBGOUT(CS_FUNCTION, 2,
2116                  printk(KERN_INFO "cs4281: prog_codec()+ \n"));
2117
2118        spin_lock_irqsave(&s->lock, flags);
2119        if (type == CS_TYPE_ADC) {
2120                temp1 = readl(s->pBA0 + BA0_DCR1);
2121                writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR1);   // Stop capture DMA, if active.
2122
2123                // program sampling rates  
2124                // Note, for CS4281, capture & play rates can be set independently.
2125                cs4281_record_rate(s, s->prop_adc.rate);
2126
2127                // program ADC parameters 
2128                format = DMRn_DMA | DMRn_AUTO | DMRn_TR_WRITE;
2129                if (s->prop_adc.
2130                    fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) {    // 16-bit
2131                        if (s->prop_adc.fmt & (AFMT_S16_BE | AFMT_U16_BE))      // Big-endian?
2132                                format |= DMRn_BEND;
2133                        if (s->prop_adc.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2134                                format |= DMRn_USIGN;   // Unsigned.      
2135                } else
2136                        format |= DMRn_SIZE8 | DMRn_USIGN;      // 8-bit, unsigned
2137                if (s->prop_adc.channels < 2)
2138                        format |= DMRn_MONO;
2139
2140                writel(format, s->pBA0 + BA0_DMR1);
2141
2142                CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2143                        "cs4281: prog_codec(): adc %s %s %s rate=%d DMR0 format=0x%.8x\n",
2144                                (format & DMRn_SIZE8) ? "8" : "16",
2145                                (format & DMRn_USIGN) ?  "Unsigned" : "Signed", 
2146                                (format & DMRn_MONO) ? "Mono" : "Stereo", 
2147                                s->prop_adc.rate, format));
2148
2149                s->ena &= ~FMODE_READ;  // not capturing data yet
2150        }
2151
2152
2153        if (type == CS_TYPE_DAC) {
2154                temp1 = readl(s->pBA0 + BA0_DCR0);
2155                writel(temp1 | DCRn_MSK, s->pBA0 + BA0_DCR0);   // Stop play DMA, if active.
2156
2157                // program sampling rates  
2158                // Note, for CS4281, capture & play rates can be set independently.
2159                cs4281_play_rate(s, s->prop_dac.rate);
2160
2161                // program DAC parameters 
2162                format = DMRn_DMA | DMRn_AUTO | DMRn_TR_READ;
2163                if (s->prop_dac.
2164                    fmt & (AFMT_S16_LE | AFMT_U16_LE | AFMT_S16_BE | AFMT_U16_BE)) {    // 16-bit
2165                        if (s->prop_dac.fmt & (AFMT_S16_BE | AFMT_U16_BE))
2166                                format |= DMRn_BEND;    // Big Endian.
2167                        if (s->prop_dac.fmt & (AFMT_U16_LE | AFMT_U16_BE))
2168                                format |= DMRn_USIGN;   // Unsigned.      
2169                } else
2170                        format |= DMRn_SIZE8 | DMRn_USIGN;      // 8-bit, unsigned
2171
2172                if (s->prop_dac.channels < 2)
2173                        format |= DMRn_MONO;
2174
2175                writel(format, s->pBA0 + BA0_DMR0);
2176
2177
2178                CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
2179                        "cs4281: prog_codec(): dac %s %s %s rate=%d DMR0 format=0x%.8x\n",
2180                                (format & DMRn_SIZE8) ? "8" : "16",
2181                                (format & DMRn_USIGN) ?  "Unsigned" : "Signed",
2182                                (format & DMRn_MONO) ? "Mono" : "Stereo", 
2183                                s->prop_dac.rate, format));
2184
2185                s->ena &= ~FMODE_WRITE; // not capturing data yet
2186
2187        }
2188        spin_unlock_irqrestore(&s->lock, flags);
2189        CS_DBGOUT(CS_FUNCTION, 2,
2190                  printk(KERN_INFO "cs4281: prog_codec()- \n"));
2191}
2192
2193
2194static int mixer_ioctl(struct cs4281_state *s, unsigned int cmd,
2195                       unsigned long arg)
2196{
2197        int return_mask=0;
2198        // Index to mixer_src[] is value of AC97 Input Mux Select Reg.
2199        // Value of array member is recording source Device ID Mask.
2200        static const unsigned int mixer_src[8] = {
2201                SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1,
2202                SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0
2203        };
2204
2205        // Index of mixtable1[] member is Device ID 
2206        // and must be <= SOUND_MIXER_NRDEVICES.
2207        // Value of array member is index into s->mix.vol[]
2208        static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = {
2209                [SOUND_MIXER_PCM] = 1,  // voice 
2210                [SOUND_MIXER_LINE1] = 2,        // AUX
2211                [SOUND_MIXER_CD] = 3,   // CD 
2212                [SOUND_MIXER_LINE] = 4, // Line 
2213                [SOUND_MIXER_SYNTH] = 5,        // FM
2214                [SOUND_MIXER_MIC] = 6,  // Mic 
2215                [SOUND_MIXER_SPEAKER] = 7,      // Speaker 
2216                [SOUND_MIXER_RECLEV] = 8,       // Recording level 
2217                [SOUND_MIXER_VOLUME] = 9        // Master Volume 
2218        };
2219
2220
2221        static const unsigned mixreg[] = {
2222                BA0_AC97_PCM_OUT_VOLUME,
2223                BA0_AC97_AUX_VOLUME,
2224                BA0_AC97_CD_VOLUME,
2225                BA0_AC97_LINE_IN_VOLUME
2226        };
2227        unsigned char l, r, rl, rr, vidx;
2228        unsigned char attentbl[11] =
2229            { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 };
2230        unsigned temp1;
2231        int i, val;
2232
2233        VALIDATE_STATE(s);
2234        CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
2235                 "cs4281: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n",
2236                         (unsigned) s, cmd));
2237#if CSDEBUG
2238        cs_printioctl(cmd);
2239#endif
2240#if CSDEBUG_INTERFACE
2241
2242        if ((cmd == SOUND_MIXER_CS_GETDBGMASK) ||
2243            (cmd == SOUND_MIXER_CS_SETDBGMASK) ||
2244            (cmd == SOUND_MIXER_CS_GETDBGLEVEL) ||
2245            (cmd == SOUND_MIXER_CS_SETDBGLEVEL) ||
2246            (cmd == SOUND_MIXER_CS_APM))
2247        {
2248                switch (cmd) {
2249
2250                case SOUND_MIXER_CS_GETDBGMASK:
2251                        return put_user(cs_debugmask,
2252                                        (unsigned long *) arg);
2253
2254                case SOUND_MIXER_CS_GETDBGLEVEL:
2255                        return put_user(cs_debuglevel,
2256                                        (unsigned long *) arg);
2257
2258                case SOUND_MIXER_CS_SETDBGMASK:
2259                        if (get_user(val, (unsigned long *) arg))
2260                                return -EFAULT;
2261                        cs_debugmask = val;
2262                        return 0;
2263
2264                case SOUND_MIXER_CS_SETDBGLEVEL:
2265                        if (get_user(val, (unsigned long *) arg))
2266                                return -EFAULT;
2267                        cs_debuglevel = val;
2268                        return 0;
2269#ifndef NOT_CS4281_PM
2270                case SOUND_MIXER_CS_APM:
2271                        if (get_user(val, (unsigned long *) arg))
2272                                return -EFAULT;
2273                        if(val == CS_IOCTL_CMD_SUSPEND)
2274                                cs4281_suspend(s);
2275                        else if(val == CS_IOCTL_CMD_RESUME)
2276                                cs4281_resume(s);
2277                        else
2278                        {
2279                                CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2280                                    "cs4281: mixer_ioctl(): invalid APM cmd (%d)\n",
2281                                        val));
2282                        }
2283                        return 0;
2284#endif
2285                default:
2286                        CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO
2287                                "cs4281: mixer_ioctl(): ERROR unknown debug cmd\n"));
2288                        return 0;
2289                }
2290        }
2291#endif
2292
2293        if (cmd == SOUND_MIXER_PRIVATE1) {
2294                // enable/disable/query mixer preamp 
2295                if (get_user(val, (int *) arg))
2296                        return -EFAULT;
2297                if (val != -1) {
2298                        cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2299                        temp1 = val ? (temp1 | 0x40) : (temp1 & 0xffbf);
2300                        cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2301                }
2302                cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2303                val = (temp1 & 0x40) ? 1 : 0;
2304                return put_user(val, (int *) arg);
2305        }
2306        if (cmd == SOUND_MIXER_PRIVATE2) {
2307                // enable/disable/query spatializer 
2308                if (get_user(val, (int *) arg))
2309                        return -EFAULT;
2310                if (val != -1) {
2311                        temp1 = (val & 0x3f) >> 2;
2312                        cs4281_write_ac97(s, BA0_AC97_3D_CONTROL, temp1);
2313                        cs4281_read_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2314                                         &temp1);
2315                        cs4281_write_ac97(s, BA0_AC97_GENERAL_PURPOSE,
2316                                          temp1 | 0x2000);
2317                }
2318                cs4281_read_ac97(s, BA0_AC97_3D_CONTROL, &temp1);
2319                return put_user((temp1 << 2) | 3, (int *) arg);
2320        }
2321        if (cmd == SOUND_MIXER_INFO) {
2322                mixer_info info;
2323                strncpy(info.id, "CS4281", sizeof(info.id));
2324                strncpy(info.name, "Crystal CS4281", sizeof(info.name));
2325                info.modify_counter = s->mix.modcnt;
2326                if (copy_to_user((void *) arg, &info, sizeof(info)))
2327                        return -EFAULT;
2328                return 0;
2329        }
2330        if (cmd == SOUND_OLD_MIXER_INFO) {
2331                _old_mixer_info info;
2332                strncpy(info.id, "CS4281", sizeof(info.id));
2333                strncpy(info.name, "Crystal CS4281", sizeof(info.name));
2334                if (copy_to_user((void *) arg, &info, sizeof(info)))
2335                        return -EFAULT;
2336                return 0;
2337        }
2338        if (cmd == OSS_GETVERSION)
2339                return put_user(SOUND_VERSION, (int *) arg);
2340
2341        if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int))
2342                return -EINVAL;
2343
2344        // If ioctl has only the SIOC_READ bit(bit 31)
2345        // on, process the only-read commands. 
2346        if (_SIOC_DIR(cmd) == _SIOC_READ) {
2347                switch (_IOC_NR(cmd)) {
2348                case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source 
2349                        cs4281_read_ac97(s, BA0_AC97_RECORD_SELECT,
2350                                         &temp1);
2351                        return put_user(mixer_src[temp1 & 7], (int *) arg);
2352
2353                case SOUND_MIXER_DEVMASK:       // Arg contains a bit for each supported device 
2354                        return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2355                                        SOUND_MASK_CD | SOUND_MASK_LINE |
2356                                        SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2357                                        SOUND_MASK_VOLUME |
2358                                        SOUND_MASK_RECLEV |
2359                                        SOUND_MASK_SPEAKER, (int *) arg);
2360
2361                case SOUND_MIXER_RECMASK:       // Arg contains a bit for each supported recording source 
2362                        return_mask = (((SOUND_MASK_LINE | SOUND_MASK_MIC |
2363                                        SOUND_MASK_CD | SOUND_MASK_VOLUME |
2364                                        SOUND_MASK_LINE1) ) & ~recsrc_invalid);
2365
2366                        CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO
2367                                "cs4281: mixer_ioctl(): return_mask=0x%x recsrc_invalid=0x%x\n",
2368                                        (unsigned)return_mask,(unsigned)recsrc_invalid));
2369                        return put_user(return_mask, (int *) arg);
2370
2371                case SOUND_MIXER_STEREODEVS:    // Mixer channels supporting stereo 
2372                        return put_user(SOUND_MASK_PCM | SOUND_MASK_SYNTH |
2373                                        SOUND_MASK_CD | SOUND_MASK_LINE |
2374                                        SOUND_MASK_LINE1 | SOUND_MASK_MIC |
2375                                        SOUND_MASK_VOLUME |
2376                                        SOUND_MASK_RECLEV, (int *) arg);
2377
2378                case SOUND_MIXER_CAPS:
2379                        return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg);
2380
2381                default:
2382                        i = _IOC_NR(cmd);
2383                        if (i >= SOUND_MIXER_NRDEVICES
2384                            || !(vidx = mixtable1[i]))
2385                                return -EINVAL;
2386                        return put_user(s->mix.vol[vidx - 1], (int *) arg);
2387                }
2388        }
2389        // If ioctl doesn't have both the SIOC_READ and 
2390        // the SIOC_WRITE bit set, return invalid.
2391        if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE))
2392                return -EINVAL;
2393
2394        // Increment the count of volume writes.
2395        s->mix.modcnt++;
2396
2397        // Isolate the command; it must be a write.
2398        switch (_IOC_NR(cmd)) {
2399
2400        case SOUND_MIXER_RECSRC:        // Arg contains a bit for each recording source 
2401                if (get_user(val, (int *) arg))
2402                        return -EFAULT;
2403                i = hweight32(val);     // i = # bits on in val.
2404                if (i != 1)     // One & only 1 bit must be on.
2405                        return 0;
2406                if(val & recsrc_invalid)
2407                {
2408                        CS_DBGOUT(CS_ERROR, 2, printk(KERN_INFO
2409                                "cs4281: mixer_ioctl(): REC SOURCE select error - record source invalid on this system (0x%x)\n",
2410                                        val));
2411                        return -EINVAL;
2412                }
2413                for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) {
2414                        if (val == mixer_src[i]) {
2415                                temp1 = (i << 8) | i;
2416                                cs4281_write_ac97(s,
2417                                                  BA0_AC97_RECORD_SELECT,
2418                                                  temp1);
2419                                return 0;
2420                        }
2421                }
2422                return 0;
2423
2424        case SOUND_MIXER_VOLUME:
2425                if (get_user(val, (int *) arg))
2426                        return -EFAULT;
2427                l = val & 0xff;
2428                if (l > 100)
2429                        l = 100;        // Max soundcard.h vol is 100.
2430                if (l < 6) {
2431                        rl = 63;
2432                        l = 0;
2433                } else
2434                        rl = attentbl[(10 * l) / 100];  // Convert 0-100 vol to 63-0 atten.
2435
2436                r = (val >> 8) & 0xff;
2437                if (r > 100)
2438                        r = 100;        // Max right volume is 100, too
2439                if (r < 6) {
2440                        rr = 63;
2441                        r = 0;
2442                } else
2443                        rr = attentbl[(10 * r) / 100];  // Convert volume to attenuation.
2444
2445                if ((rl > 60) && (rr > 60))     // If both l & r are 'low',          
2446                        temp1 = 0x8000; //  turn on the mute bit.
2447                else
2448                        temp1 = 0;
2449
2450                temp1 |= (rl << 8) | rr;
2451
2452                cs4281_write_ac97(s, BA0_AC97_MASTER_VOLUME, temp1);
2453                cs4281_write_ac97(s, BA0_AC97_HEADPHONE_VOLUME, temp1);
2454
2455#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2456                s->mix.vol[8] = ((unsigned int) r << 8) | l;
2457#else
2458                s->mix.vol[8] = val;
2459#endif
2460                return put_user(s->mix.vol[8], (int *) arg);
2461
2462        case SOUND_MIXER_SPEAKER:
2463                if (get_user(val, (int *) arg))
2464                        return -EFAULT;
2465                l = val & 0xff;
2466                if (l > 100)
2467                        l = 100;
2468                if (l < 3) {
2469                        rl = 0;
2470                        l = 0;
2471                } else {
2472                        rl = (l * 2 - 5) / 13;  // Convert 0-100 range to 0-15.
2473                        l = (rl * 13 + 5) / 2;
2474                }
2475
2476                if (rl < 3) {
2477                        temp1 = 0x8000;
2478                        rl = 0;
2479                } else
2480                        temp1 = 0;
2481                rl = 15 - rl;   // Convert volume to attenuation.
2482                temp1 |= rl << 1;
2483                cs4281_write_ac97(s, BA0_AC97_PC_BEEP_VOLUME, temp1);
2484
2485#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2486                s->mix.vol[6] = l << 8;
2487#else
2488                s->mix.vol[6] = val;
2489#endif
2490                return put_user(s->mix.vol[6], (int *) arg);
2491
2492        case SOUND_MIXER_RECLEV:
2493                if (get_user(val, (int *) arg))
2494                        return -EFAULT;
2495                l = val & 0xff;
2496                if (l > 100)
2497                        l = 100;
2498                r = (val >> 8) & 0xff;
2499                if (r > 100)
2500                        r = 100;
2501                rl = (l * 2 - 5) / 13;  // Convert 0-100 scale to 0-15.
2502                rr = (r * 2 - 5) / 13;
2503                if (rl < 3 && rr < 3)
2504                        temp1 = 0x8000;
2505                else
2506                        temp1 = 0;
2507
2508                temp1 = temp1 | (rl << 8) | rr;
2509                cs4281_write_ac97(s, BA0_AC97_RECORD_GAIN, temp1);
2510
2511#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2512                s->mix.vol[7] = ((unsigned int) r << 8) | l;
2513#else
2514                s->mix.vol[7] = val;
2515#endif
2516                return put_user(s->mix.vol[7], (int *) arg);
2517
2518        case SOUND_MIXER_MIC:
2519                if (get_user(val, (int *) arg))
2520                        return -EFAULT;
2521                l = val & 0xff;
2522                if (l > 100)
2523                        l = 100;
2524                if (l < 1) {
2525                        l = 0;
2526                        rl = 0;
2527                } else {
2528                        rl = ((unsigned) l * 5 - 4) / 16;       // Convert 0-100 range to 0-31.
2529                        l = (rl * 16 + 4) / 5;
2530                }
2531                cs4281_read_ac97(s, BA0_AC97_MIC_VOLUME, &temp1);
2532                temp1 &= 0x40;  // Isolate 20db gain bit.
2533                if (rl < 3) {
2534                        temp1 |= 0x8000;
2535                        rl = 0;
2536                }
2537                rl = 31 - rl;   // Convert volume to attenuation.
2538                temp1 |= rl;
2539                cs4281_write_ac97(s, BA0_AC97_MIC_VOLUME, temp1);
2540
2541#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2542                s->mix.vol[5] = val << 8;
2543#else
2544                s->mix.vol[5] = val;
2545#endif
2546                return put_user(s->mix.vol[5], (int *) arg);
2547
2548
2549        case SOUND_MIXER_SYNTH:
2550                if (get_user(val, (int *) arg))
2551                        return -EFAULT;
2552                l = val & 0xff;
2553                if (l > 100)
2554                        l = 100;
2555                if (get_user(val, (int *) arg))
2556                        return -EFAULT;
2557                r = (val >> 8) & 0xff;
2558                if (r > 100)
2559                        r = 100;
2560                rl = (l * 2 - 11) / 3;  // Convert 0-100 range to 0-63.
2561                rr = (r * 2 - 11) / 3;
2562                if (rl < 3)     // If l is low, turn on
2563                        temp1 = 0x0080; //  the mute bit.
2564                else
2565                        temp1 = 0;
2566
2567                rl = 63 - rl;   // Convert vol to attenuation.
2568                writel(temp1 | rl, s->pBA0 + BA0_FMLVC);
2569                if (rr < 3)     //  If rr is low, turn on
2570                        temp1 = 0x0080; //   the mute bit.
2571                else
2572                        temp1 = 0;
2573                rr = 63 - rr;   // Convert vol to attenuation.
2574                writel(temp1 | rr, s->pBA0 + BA0_FMRVC);
2575
2576#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2577                s->mix.vol[4] = (r << 8) | l;
2578#else
2579                s->mix.vol[4] = val;
2580#endif
2581                return put_user(s->mix.vol[4], (int *) arg);
2582
2583
2584        default:
2585                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
2586                        "cs4281: mixer_ioctl(): default\n"));
2587
2588                i = _IOC_NR(cmd);
2589                if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i]))
2590                        return -EINVAL;
2591                if (get_user(val, (int *) arg))
2592                        return -EFAULT;
2593                l = val & 0xff;
2594                if (l > 100)
2595                        l = 100;
2596                if (l < 1) {
2597                        l = 0;
2598                        rl = 31;
2599                } else
2600                        rl = (attentbl[(l * 10) / 100]) >> 1;
2601
2602                r = (val >> 8) & 0xff;
2603                if (r > 100)
2604                        r = 100;
2605                if (r < 1) {
2606                        r = 0;
2607                        rr = 31;
2608                } else
2609                        rr = (attentbl[(r * 10) / 100]) >> 1;
2610                if ((rl > 30) && (rr > 30))
2611                        temp1 = 0x8000;
2612                else
2613                        temp1 = 0;
2614                temp1 = temp1 | (rl << 8) | rr;
2615                cs4281_write_ac97(s, mixreg[vidx - 1], temp1);
2616
2617#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS
2618                s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l;
2619#else
2620                s->mix.vol[vidx - 1] = val;
2621#endif
2622#ifndef NOT_CS4281_PM
2623                CS_DBGOUT(CS_PM, 9, printk(KERN_INFO 
2624                        "write ac97 mixreg[%d]=0x%x mix.vol[]=0x%x\n", 
2625                                vidx-1,temp1,s->mix.vol[vidx-1]));
2626#endif
2627                return put_user(s->mix.vol[vidx - 1], (int *) arg);
2628        }
2629}
2630
2631static int cs4281_open_mixdev(struct inode *inode, struct file *file)
2632{
2633        int minor = MINOR(inode->i_rdev);
2634        struct cs4281_state *s=NULL;
2635        struct list_head *entry;
2636
2637        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2638                  printk(KERN_INFO "cs4281: cs4281_open_mixdev()+\n"));
2639
2640        list_for_each(entry, &cs4281_devs)
2641        {
2642                s = list_entry(entry, struct cs4281_state, list);
2643                if(s->dev_mixer == minor)
2644                        break;
2645        }
2646        if (!s)
2647        {
2648                CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2,
2649                        printk(KERN_INFO "cs4281: cs4281_open_mixdev()- -ENODEV\n"));
2650                return -ENODEV;
2651        }
2652        VALIDATE_STATE(s);
2653        file->private_data = s;
2654        MOD_INC_USE_COUNT;
2655
2656        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4,
2657                  printk(KERN_INFO "cs4281: cs4281_open_mixdev()- 0\n"));
2658
2659        return 0;
2660}
2661
2662
2663static int cs4281_release_mixdev(struct inode *inode, struct file *file)
2664{
2665        struct cs4281_state *s =
2666            (struct cs4281_state *) file->private_data;
2667
2668        VALIDATE_STATE(s);
2669        MOD_DEC_USE_COUNT;
2670        return 0;
2671}
2672
2673
2674static int cs4281_ioctl_mixdev(struct inode *inode, struct file *file,
2675                               unsigned int cmd, unsigned long arg)
2676{
2677        return mixer_ioctl((struct cs4281_state *) file->private_data, cmd,
2678                           arg);
2679}
2680
2681
2682// ******************************************************************************************
2683//   Mixer file operations struct.
2684// ******************************************************************************************
2685static /*const */ struct file_operations cs4281_mixer_fops = {
2686        llseek:no_llseek,
2687        ioctl:cs4281_ioctl_mixdev,
2688        open:cs4281_open_mixdev,
2689        release:cs4281_release_mixdev,
2690};
2691
2692// --------------------------------------------------------------------- 
2693
2694
2695static int drain_adc(struct cs4281_state *s, int nonblock)
2696{
2697        DECLARE_WAITQUEUE(wait, current);
2698        unsigned long flags;
2699        int count;
2700        unsigned tmo;
2701
2702        if (s->dma_adc.mapped)
2703                return 0;
2704        add_wait_queue(&s->dma_adc.wait, &wait);
2705        for (;;) {
2706                set_current_state(TASK_INTERRUPTIBLE);
2707                spin_lock_irqsave(&s->lock, flags);
2708                count = s->dma_adc.count;
2709                CS_DBGOUT(CS_FUNCTION, 2,
2710                          printk(KERN_INFO "cs4281: drain_adc() %d\n", count));
2711                spin_unlock_irqrestore(&s->lock, flags);
2712                if (count <= 0) {
2713                        CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2714                                 "cs4281: drain_adc() count<0\n"));
2715                        break;
2716                }
2717                if (signal_pending(current))
2718                        break;
2719                if (nonblock) {
2720                        remove_wait_queue(&s->dma_adc.wait, &wait);
2721                        current->state = TASK_RUNNING;
2722                        return -EBUSY;
2723                }
2724                tmo =
2725                    3 * HZ * (count +
2726                              s->dma_adc.fragsize) / 2 / s->prop_adc.rate;
2727                if (s->prop_adc.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2728                        tmo >>= 1;
2729                if (s->prop_adc.channels > 1)
2730                        tmo >>= 1;
2731                if (!schedule_timeout(tmo + 1))
2732                        printk(KERN_DEBUG "cs4281: dma timed out??\n");
2733        }
2734        remove_wait_queue(&s->dma_adc.wait, &wait);
2735        current->state = TASK_RUNNING;
2736        if (signal_pending(current))
2737                return -ERESTARTSYS;
2738        return 0;
2739}
2740
2741static int drain_dac(struct cs4281_state *s, int nonblock)
2742{
2743        DECLARE_WAITQUEUE(wait, current);
2744        unsigned long flags;
2745        int count;
2746        unsigned tmo;
2747
2748        CS_DBGOUT(CS_FUNCTION, 2,
2749                  printk(KERN_INFO "cs4281: drain_dac()+\n"));
2750        if (s->dma_dac.mapped)
2751        {
2752                CS_DBGOUT(CS_FUNCTION, 2,
2753                          printk(KERN_INFO "cs4281: drain_dac()- (mmap) 0\n"));
2754                return 0;
2755        }
2756        if (s->ena & FMODE_WRITE)
2757                add_wait_queue(&s->dma_dac.wait, &wait);
2758        else
2759                return 0;
2760        for (;;) {
2761                set_current_state(TASK_INTERRUPTIBLE);
2762                spin_lock_irqsave(&s->lock, flags);
2763                count = s->dma_dac.count;
2764                spin_unlock_irqrestore(&s->lock, flags);
2765                if (count <= 0)
2766                        break;
2767                if (signal_pending(current))
2768                        break;
2769                if (nonblock) {
2770                        remove_wait_queue(&s->dma_dac.wait, &wait);
2771                        current->state = TASK_RUNNING;
2772                        CS_DBGOUT(CS_FUNCTION, 2,
2773                                  printk(KERN_INFO "cs4281: drain_dac()- -EBUSY\n"));
2774                        return -EBUSY;
2775                }
2776                tmo =
2777                    3 * HZ * (count +
2778                              s->dma_dac.fragsize) / 2 / s->prop_dac.rate;
2779                if (s->prop_dac.fmt & (AFMT_S16_LE | AFMT_U16_LE))
2780                        tmo >>= 1;
2781                if (s->prop_dac.channels > 1)
2782                        tmo >>= 1;
2783                if (!schedule_timeout(tmo + 1))
2784                        printk(KERN_DEBUG "cs4281: dma timed out??\n");
2785        }
2786        remove_wait_queue(&s->dma_dac.wait, &wait);
2787        current->state = TASK_RUNNING;
2788        if (signal_pending(current))
2789        {
2790                CS_DBGOUT(CS_FUNCTION, 2,
2791                          printk(KERN_INFO "cs4281: drain_dac()- -ERESTARTSYS\n"));
2792                return -ERESTARTSYS;
2793        }
2794        CS_DBGOUT(CS_FUNCTION, 2,
2795                  printk(KERN_INFO "cs4281: drain_dac()- 0\n"));
2796        return 0;
2797}
2798
2799//****************************************************************************
2800//
2801// CopySamples copies 16-bit stereo samples from the source to the
2802// destination, possibly converting down to either 8-bit or mono or both.
2803// count specifies the number of output bytes to write.
2804//
2805//  Arguments:
2806//
2807//  dst             - Pointer to a destination buffer.
2808//  src             - Pointer to a source buffer
2809//  count           - The number of bytes to copy into the destination buffer.
2810//  iChannels       - Stereo - 2
2811//                    Mono   - 1
2812//  fmt             - AFMT_xxx (soundcard.h formats)
2813//
2814// NOTES: only call this routine for conversion to 8bit from 16bit
2815//
2816//****************************************************************************
2817static void CopySamples(char *dst, char *src, int count, int iChannels,
2818                        unsigned fmt)
2819{
2820
2821        unsigned short *psSrc;
2822        long lAudioSample;
2823
2824        CS_DBGOUT(CS_FUNCTION, 2,
2825                  printk(KERN_INFO "cs4281: CopySamples()+ "));
2826        CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2827                 " dst=0x%x src=0x%x count=%d iChannels=%d fmt=0x%x\n",
2828                         (unsigned) dst, (unsigned) src, (unsigned) count,
2829                         (unsigned) iChannels, (unsigned) fmt));
2830
2831        // Gershwin does format conversion in hardware so normally
2832        // we don't do any host based coversion. The data formatter
2833        // truncates 16 bit data to 8 bit and that causes some hiss.
2834        // We have already forced the HW to do 16 bit sampling and 
2835        // 2 channel so that we can use software to round instead 
2836        // of truncate
2837
2838        //
2839        // See if the data should be output as 8-bit unsigned stereo.
2840        // or if the data should be output at 8-bit unsigned mono.
2841        //
2842        if ( ((iChannels == 2) && (fmt & AFMT_U8)) ||
2843                ((iChannels == 1) && (fmt & AFMT_U8)) ) {
2844                //
2845                // Convert each 16-bit unsigned stereo sample to 8-bit unsigned 
2846                // stereo using rounding.
2847                //
2848                psSrc = (unsigned short *) src;
2849                count = count / 2;
2850                while (count--) {
2851                        lAudioSample = (long) psSrc[count] + (long) 0x80;
2852                        if (lAudioSample > 0xffff) {
2853                                lAudioSample = 0xffff;
2854                        }
2855                        dst[count] = (char) (lAudioSample >> 8);
2856                }
2857        }
2858        //
2859        // check for 8-bit signed stereo.
2860        //
2861        else if ((iChannels == 2) && (fmt & AFMT_S8)) {
2862                //
2863                // Convert each 16-bit stereo sample to 8-bit stereo using rounding.
2864                //
2865                psSrc = (short *) src;
2866                while (count--) {
2867                        lAudioSample =
2868                            (((long) psSrc[0] + (long) psSrc[1]) / 2);
2869                        psSrc += 2;
2870                        *dst++ = (char) ((short) lAudioSample >> 8);
2871                }
2872        }
2873        //
2874        // Otherwise, the data should be output as 8-bit signed mono.
2875        //
2876        else if ((iChannels == 1) && (fmt & AFMT_S8)) {
2877                //
2878                // Convert each 16-bit signed mono sample to 8-bit signed mono 
2879                // using rounding.
2880                //
2881                psSrc = (short *) src;
2882                count = count / 2;
2883                while (count--) {
2884                        lAudioSample =
2885                            (((long) psSrc[0] + (long) psSrc[1]) / 2);
2886                        if (lAudioSample > 0x7fff) {
2887                                lAudioSample = 0x7fff;
2888                        }
2889                        psSrc += 2;
2890                        *dst++ = (char) ((short) lAudioSample >> 8);
2891                }
2892        }
2893}
2894
2895//
2896// cs_copy_to_user()
2897// replacement for the standard copy_to_user, to allow for a conversion from
2898// 16 bit to 8 bit if the record conversion is active.  the cs4281 has some
2899// issues with 8 bit capture, so the driver always captures data in 16 bit
2900// and then if the user requested 8 bit, converts from 16 to 8 bit.
2901//
2902static unsigned cs_copy_to_user(struct cs4281_state *s, void *dest,
2903                                unsigned *hwsrc, unsigned cnt,
2904                                unsigned *copied)
2905{
2906        void *src = hwsrc;      //default to the standard destination buffer addr
2907
2908        CS_DBGOUT(CS_FUNCTION, 6, printk(KERN_INFO
2909                "cs_copy_to_user()+ fmt=0x%x fmt_o=0x%x cnt=%d dest=0x%.8x\n",
2910                        s->prop_adc.fmt, s->prop_adc.fmt_original,
2911                        (unsigned) cnt, (unsigned) dest));
2912
2913        if (cnt > s->dma_adc.dmasize) {
2914                cnt = s->dma_adc.dmasize;
2915        }
2916        if (!cnt) {
2917                *copied = 0;
2918                return 0;
2919        }
2920        if (s->conversion) {
2921                if (!s->tmpbuff) {
2922                        *copied = cnt / 2;
2923                        return 0;
2924                }
2925                CopySamples(s->tmpbuff, (void *) hwsrc, cnt,
2926                            (unsigned) s->prop_adc.channels,
2927                            s->prop_adc.fmt_original);
2928                src = s->tmpbuff;
2929                cnt = cnt / 2;
2930        }
2931
2932        if (copy_to_user(dest, src, cnt)) {
2933                *copied = 0;
2934                return -EFAULT;
2935        }
2936        *copied = cnt;
2937        CS_DBGOUT(CS_FUNCTION, 2, printk(KERN_INFO
2938                "cs4281: cs_copy_to_user()- copied bytes is %d \n", cnt));
2939        return 0;
2940}
2941
2942// --------------------------------------------------------------------- 
2943
2944static ssize_t cs4281_read(struct file *file, char *buffer, size_t count,
2945                           loff_t * ppos)
2946{
2947        struct cs4281_state *s =
2948            (struct cs4281_state *) file->private_data;
2949        ssize_t ret;
2950        unsigned long flags;
2951        unsigned swptr;
2952        int cnt;
2953        unsigned copied = 0;
2954
2955        CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
2956                  printk(KERN_INFO "cs4281: cs4281_read()+ %d \n", count));
2957
2958        VALIDATE_STATE(s);
2959        if (ppos != &file->f_pos)
2960                return -ESPIPE;
2961        if (s->dma_adc.mapped)
2962                return -ENXIO;
2963        if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s)))
2964                return ret;
2965        if (!access_ok(VERIFY_WRITE, buffer, count))
2966                return -EFAULT;
2967        ret = 0;
2968//
2969// "count" is the amount of bytes to read (from app), is decremented each loop
2970//      by the amount of bytes that have been returned to the user buffer.
2971// "cnt" is the running total of each read from the buffer (changes each loop)
2972// "buffer" points to the app's buffer
2973// "ret" keeps a running total of the amount of bytes that have been copied
2974//      to the user buffer.
2975// "copied" is the total bytes copied into the user buffer for each loop.
2976//
2977        while (count > 0) {
2978                CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
2979                        "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n",
2980                                count, s->dma_adc.count,
2981                                s->dma_adc.swptr, s->dma_adc.hwptr));
2982                spin_lock_irqsave(&s->lock, flags);
2983
2984                // get the current copy point of the sw buffer
2985                swptr = s->dma_adc.swptr;
2986
2987                // cnt is the amount of unread bytes from the end of the 
2988                // hw buffer to the current sw pointer
2989                cnt = s->dma_adc.dmasize - swptr;
2990
2991                // dma_adc.count is the current total bytes that have not been read.
2992                // if the amount of unread bytes from the current sw pointer to the
2993                // end of the buffer is greater than the current total bytes that
2994                // have not been read, then set the "cnt" (unread bytes) to the
2995                // amount of unread bytes.  
2996
2997                if (s->dma_adc.count < cnt)
2998                        cnt = s->dma_adc.count;
2999                spin_unlock_irqrestore(&s->lock, flags);
3000                //
3001                // if we are converting from 8/16 then we need to copy
3002                // twice the number of 16 bit bytes then 8 bit bytes.
3003                // 
3004                if (s->conversion) {
3005                        if (cnt > (count * 2))
3006                                cnt = (count * 2);
3007                } else {
3008                        if (cnt > count)
3009                                cnt = count;
3010                }
3011                //
3012                // "cnt" NOW is the smaller of the amount that will be read,
3013                // and the amount that is requested in this read (or partial).
3014                // if there are no bytes in the buffer to read, then start the
3015                // ADC and wait for the interrupt handler to wake us up.
3016                //
3017                if (cnt <= 0) {
3018
3019                        // start up the dma engine and then continue back to the top of
3020                        // the loop when wake up occurs.
3021                        start_adc(s);
3022                        if (file->f_flags & O_NONBLOCK)
3023                                return ret ? ret : -EAGAIN;
3024                        interruptible_sleep_on(&s->dma_adc.wait);
3025                        if (signal_pending(current))
3026                                return ret ? ret : -ERESTARTSYS;
3027                        continue;
3028                }
3029                // there are bytes in the buffer to read.
3030                // copy from the hw buffer over to the user buffer.
3031                // user buffer is designated by "buffer"
3032                // virtual address to copy from is rawbuf+swptr
3033                // the "cnt" is the number of bytes to read.
3034
3035                CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO
3036                        "_read() copy_to cnt=%d count=%d ", cnt, count));
3037                CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO
3038                         " .dmasize=%d .count=%d buffer=0x%.8x ret=%d\n",
3039                                 s->dma_adc.dmasize, s->dma_adc.count,
3040                                 (unsigned) buffer, ret));
3041
3042                if (cs_copy_to_user
3043                    (s, buffer, s->dma_adc.rawbuf + swptr, cnt, &copied))
3044                        return ret ? ret : -EFAULT;
3045                swptr = (swptr + cnt) % s->dma_adc.dmasize;
3046                spin_lock_irqsave(&s->lock, flags);
3047                s->dma_adc.swptr = swptr;
3048                s->dma_adc.count -= cnt;
3049                spin_unlock_irqrestore(&s->lock, flags);
3050                count -= copied;
3051                buffer += copied;
3052                ret += copied;
3053                start_adc(s);
3054        }
3055        CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2,
3056                  printk(KERN_INFO "cs4281: cs4281_read()- %d\n", ret));
3057        return ret;
3058}
3059
3060
3061static ssize_t cs4281_write(struct file *file, const char *buffer,
3062                            size_t count, loff_t * ppos)
3063{
3064        struct cs4281_state *s =
3065            (struct cs4281_state *) file->private_data;
3066        ssize_t ret;
3067        unsigned long flags;
3068        unsigned swptr, hwptr, busaddr;
3069        int cnt;
3070
3071        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
3072                  printk(KERN_INFO "cs4281: cs4281_write()+ count=%d\n",
3073                         count));
3074        VALIDATE_STATE(s);
3075
3076        if (ppos != &file->f_pos)
3077                return -ESPIPE;
3078        if (s->dma_dac.mapped)
3079                return -ENXIO;
3080        if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s)))
3081                return ret;
3082        if (!access_ok(VERIFY_READ, buffer, count))
3083                return -EFAULT;
3084        ret = 0;
3085        while (count > 0) {
3086                spin_lock_irqsave(&s->lock, flags);
3087                if (s->dma_dac.count < 0) {
3088                        s->dma_dac.count = 0;
3089                        s->dma_dac.swptr = s->dma_dac.hwptr;
3090                }
3091                if (s->dma_dac.underrun) {
3092                        s->dma_dac.underrun = 0;
3093                        hwptr = readl(s->pBA0 + BA0_DCA0);
3094                        busaddr = virt_to_bus(s->dma_dac.rawbuf);
3095                        hwptr -= (unsigned) busaddr;
3096                        s->dma_dac.swptr = s->dma_dac.hwptr = hwptr;
3097                }
3098                swptr = s->dma_dac.swptr;
3099                cnt = s->dma_dac.dmasize - swptr;
3100                if (s->dma_dac.count + cnt > s->dma_dac.dmasize)
3101                        cnt = s->dma_dac.dmasize - s->dma_dac.count;
3102                spin_unlock_irqrestore(&s->lock, flags);
3103                if (cnt > count)
3104                        cnt = count;
3105                if (cnt <= 0) {
3106                        start_dac(s);
3107                        if (file->f_flags & O_NONBLOCK)
3108                                return ret ? ret : -EAGAIN;
3109                        interruptible_sleep_on(&s->dma_dac.wait);
3110                        if (signal_pending(current))
3111                                return ret ? ret : -ERESTARTSYS;
3112                        continue;
3113                }
3114                if (copy_from_user(s->dma_dac.rawbuf + swptr, buffer, cnt))
3115                        return ret ? ret : -EFAULT;
3116                swptr = (swptr + cnt) % s->dma_dac.dmasize;
3117                spin_lock_irqsave(&s->lock, flags);
3118                s->dma_dac.swptr = swptr;
3119                s->dma_dac.count += cnt;
3120                s->dma_dac.endcleared = 0;
3121                spin_unlock_irqrestore(&s->lock, flags);
3122                count -= cnt;
3123                buffer += cnt;
3124                ret += cnt;
3125                start_dac(s);
3126        }
3127        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2,
3128                  printk(KERN_INFO "cs4281: cs4281_write()- %d\n", ret));
3129        return ret;
3130}
3131
3132/*
3133* cs4281_poll(struct file *file, struct poll_table_struct *wait)
3134*/
3135
3136static unsigned int cs4281_poll(struct file *file,
3137                                struct poll_table_struct *wait)
3138{
3139        struct cs4281_state *s =
3140            (struct cs4281_state *) file->private_data;
3141        unsigned long flags;
3142        unsigned int mask = 0;
3143
3144        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3145                  printk(KERN_INFO "cs4281: cs4281_poll()+ wait=0x%x\n", (unsigned)wait));
3146        VALIDATE_STATE(s);
3147        if (file->f_mode & FMODE_WRITE) {
3148                CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3149                          printk(KERN_INFO
3150                                 "cs4281: cs4281_poll() wait on FMODE_WRITE\n"));
3151                if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3152                        return 0;
3153                poll_wait(file, &s->dma_dac.wait, wait);
3154
3155        } else if (file->f_mode & FMODE_READ) {
3156                CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3157                          printk(KERN_INFO
3158                                 "cs4281: cs4281_poll() wait on FMODE_READ\n"));
3159                if(!s->dma_adc.ready && prog_dmabuf_adc(s))
3160                        return 0;
3161                poll_wait(file, &s->dma_adc.wait, wait);
3162
3163        }
3164        spin_lock_irqsave(&s->lock, flags);
3165        if (file->f_mode & FMODE_WRITE) {
3166                if (s->dma_dac.mapped) {
3167                        if (s->dma_dac.count >=
3168                            (signed) s->dma_dac.fragsize) {
3169                                if (s->dma_dac.wakeup)
3170                                        mask |= POLLOUT | POLLWRNORM;
3171                                else
3172                                        mask = 0;
3173                                s->dma_dac.wakeup = 0;
3174                        }
3175                } else {
3176                        if ((signed) (s->dma_dac.dmasize/2) >= s->dma_dac.count)
3177                                mask |= POLLOUT | POLLWRNORM;
3178                }
3179        } else if (file->f_mode & FMODE_READ) {
3180                if (s->dma_adc.mapped) {
3181                        if (s->dma_adc.count >= (signed) s->dma_adc.fragsize) 
3182                                mask |= POLLIN | POLLRDNORM;
3183                } else {
3184                        if (s->dma_adc.count > 0)
3185                                mask |= POLLIN | POLLRDNORM;
3186                }
3187        }
3188        spin_unlock_irqrestore(&s->lock, flags);
3189        CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4,
3190                  printk(KERN_INFO "cs4281: cs4281_poll()- 0x%.8x\n",
3191                         mask));
3192        return mask;
3193}
3194
3195
3196static int cs4281_mmap(struct file *file, struct vm_area_struct *vma)
3197{
3198        struct cs4281_state *s =
3199            (struct cs4281_state *) file->private_data;
3200        struct dmabuf *db;
3201        int ret;
3202        unsigned long size;
3203
3204        CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3205                  printk(KERN_INFO "cs4281: cs4281_mmap()+\n"));
3206
3207        VALIDATE_STATE(s);
3208        if (vma->vm_flags & VM_WRITE) {
3209                if ((ret = prog_dmabuf_dac(s)) != 0)
3210                        return ret;
3211                db = &s->dma_dac;
3212        } else if (vma->vm_flags & VM_READ) {
3213                if ((ret = prog_dmabuf_adc(s)) != 0)
3214                        return ret;
3215                db = &s->dma_adc;
3216        } else
3217                return -EINVAL;
3218//
3219// only support PLAYBACK for now
3220//
3221        db = &s->dma_dac;
3222
3223        if ((vma->vm_pgoff) != 0)
3224                return -EINVAL;
3225        size = vma->vm_end - vma->vm_start;
3226        if (size > (PAGE_SIZE << db->buforder))
3227                return -EINVAL;
3228        if (remap_page_range
3229            (vma->vm_start, virt_to_phys(db->rawbuf), size,
3230             vma->vm_page_prot)) return -EAGAIN;
3231        db->mapped = 1;
3232
3233        CS_DBGOUT(CS_FUNCTION | CS_PARMS | CS_OPEN, 4,
3234                  printk(KERN_INFO "cs4281: cs4281_mmap()- 0 size=%d\n",
3235                         (unsigned) size));
3236
3237        return 0;
3238}
3239
3240
3241static int cs4281_ioctl(struct inode *inode, struct file *file,
3242                        unsigned int cmd, unsigned long arg)
3243{
3244        struct cs4281_state *s =
3245            (struct cs4281_state *) file->private_data;
3246        unsigned long flags;
3247        audio_buf_info abinfo;
3248        count_info cinfo;
3249        int val, mapped, ret;
3250
3251        CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO
3252                 "cs4281: cs4281_ioctl(): file=0x%.8x cmd=0x%.8x\n",
3253                         (unsigned) file, cmd));
3254#if CSDEBUG
3255        cs_printioctl(cmd);
3256#endif
3257        VALIDATE_STATE(s);
3258        mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) ||
3259            ((file->f_mode & FMODE_READ) && s->dma_adc.mapped);
3260        switch (cmd) {
3261        case OSS_GETVERSION:
3262                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3263                        "cs4281: cs4281_ioctl(): SOUND_VERSION=0x%.8x\n",
3264                                 SOUND_VERSION));
3265                return put_user(SOUND_VERSION, (int *) arg);
3266
3267        case SNDCTL_DSP_SYNC:
3268                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3269                         "cs4281: cs4281_ioctl(): DSP_SYNC\n"));
3270                if (file->f_mode & FMODE_WRITE)
3271                        return drain_dac(s,
3272                                         0 /*file->f_flags & O_NONBLOCK */
3273                                         );
3274                return 0;
3275
3276        case SNDCTL_DSP_SETDUPLEX:
3277                return 0;
3278
3279        case SNDCTL_DSP_GETCAPS:
3280                return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME |
3281                                DSP_CAP_TRIGGER | DSP_CAP_MMAP,
3282                                (int *) arg);
3283
3284        case SNDCTL_DSP_RESET:
3285                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3286                         "cs4281: cs4281_ioctl(): DSP_RESET\n"));
3287                if (file->f_mode & FMODE_WRITE) {
3288                        stop_dac(s);
3289                        synchronize_irq();
3290                        s->dma_dac.swptr = s->dma_dac.hwptr =
3291                            s->dma_dac.count = s->dma_dac.total_bytes =
3292                            s->dma_dac.blocks = s->dma_dac.wakeup = 0;
3293                        prog_codec(s, CS_TYPE_DAC);
3294                }
3295                if (file->f_mode & FMODE_READ) {
3296                        stop_adc(s);
3297                        synchronize_irq();
3298                        s->dma_adc.swptr = s->dma_adc.hwptr =
3299                            s->dma_adc.count = s->dma_adc.total_bytes =
3300                            s->dma_adc.blocks = s->dma_dac.wakeup = 0;
3301                        prog_codec(s, CS_TYPE_ADC);
3302                }
3303                return 0;
3304
3305        case SNDCTL_DSP_SPEED:
3306                if (get_user(val, (int *) arg))
3307                        return -EFAULT;
3308                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3309                         "cs4281: cs4281_ioctl(): DSP_SPEED val=%d\n", val));
3310                //
3311                // support independent capture and playback channels
3312                // assume that the file mode bit determines the 
3313                // direction of the data flow.
3314                //
3315                if (file->f_mode & FMODE_READ) {
3316                        if (val >= 0) {
3317                                stop_adc(s);
3318                                s->dma_adc.ready = 0;
3319                                // program sampling rates 
3320                                if (val > 48000)
3321                                        val = 48000;
3322                                if (val < 6300)
3323                                        val = 6300;
3324                                s->prop_adc.rate = val;
3325                                prog_codec(s, CS_TYPE_ADC);
3326                        }
3327                }
3328                if (file->f_mode & FMODE_WRITE) {
3329                        if (val >= 0) {
3330                                stop_dac(s);
3331                                s->dma_dac.ready = 0;
3332                                // program sampling rates 
3333                                if (val > 48000)
3334                                        val = 48000;
3335                                if (val < 6300)
3336                                        val = 6300;
3337                                s->prop_dac.rate = val;
3338                                prog_codec(s, CS_TYPE_DAC);
3339                        }
3340                }
3341
3342                if (file->f_mode & FMODE_WRITE)
3343                        val = s->prop_dac.rate;
3344                else if (file->f_mode & FMODE_READ)
3345                        val = s->prop_adc.rate;
3346
3347                return put_user(val, (int *) arg);
3348
3349        case SNDCTL_DSP_STEREO:
3350                if (get_user(val, (int *) arg))
3351                        return -EFAULT;
3352                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3353                         "cs4281: cs4281_ioctl(): DSP_STEREO val=%d\n", val));
3354                if (file->f_mode & FMODE_READ) {
3355                        stop_adc(s);
3356                        s->dma_adc.ready = 0;
3357                        s->prop_adc.channels = val ? 2 : 1;
3358                        prog_codec(s, CS_TYPE_ADC);
3359                }
3360                if (file->f_mode & FMODE_WRITE) {
3361                        stop_dac(s);
3362                        s->dma_dac.ready = 0;
3363                        s->prop_dac.channels = val ? 2 : 1;
3364                        prog_codec(s, CS_TYPE_DAC);
3365                }
3366                return 0;
3367
3368        case SNDCTL_DSP_CHANNELS:
3369                if (get_user(val, (int *) arg))
3370                        return -EFAULT;
3371                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3372                         "cs4281: cs4281_ioctl(): DSP_CHANNELS val=%d\n",
3373                                 val));
3374                if (val != 0) {
3375                        if (file->f_mode & FMODE_READ) {
3376                                stop_adc(s);
3377                                s->dma_adc.ready = 0;
3378                                if (val >= 2)
3379                                        s->prop_adc.channels = 2;
3380                                else
3381                                        s->prop_adc.channels = 1;
3382                                prog_codec(s, CS_TYPE_ADC);
3383                        }
3384                        if (file->f_mode & FMODE_WRITE) {
3385                                stop_dac(s);
3386                                s->dma_dac.ready = 0;
3387                                if (val >= 2)
3388                                        s->prop_dac.channels = 2;
3389                                else
3390                                        s->prop_dac.channels = 1;
3391                                prog_codec(s, CS_TYPE_DAC);
3392                        }
3393                }
3394
3395                if (file->f_mode & FMODE_WRITE)
3396                        val = s->prop_dac.channels;
3397                else if (file->f_mode & FMODE_READ)
3398                        val = s->prop_adc.channels;
3399
3400                return put_user(val, (int *) arg);
3401
3402        case SNDCTL_DSP_GETFMTS:        // Returns a mask 
3403                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3404                        "cs4281: cs4281_ioctl(): DSP_GETFMT val=0x%.8x\n",
3405                                 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3406                                 AFMT_U8));
3407                return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 |
3408                                AFMT_U8, (int *) arg);
3409
3410        case SNDCTL_DSP_SETFMT:
3411                if (get_user(val, (int *) arg))
3412                        return -EFAULT;
3413                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3414                         "cs4281: cs4281_ioctl(): DSP_SETFMT val=0x%.8x\n",
3415                                 val));
3416                if (val != AFMT_QUERY) {
3417                        if (file->f_mode & FMODE_READ) {
3418                                stop_adc(s);
3419                                s->dma_adc.ready = 0;
3420                                if (val != AFMT_S16_LE
3421                                    && val != AFMT_U16_LE && val != AFMT_S8
3422                                    && val != AFMT_U8)
3423                                        val = AFMT_U8;
3424                                s->prop_adc.fmt = val;
3425                                s->prop_adc.fmt_original = s->prop_adc.fmt;
3426                                prog_codec(s, CS_TYPE_ADC);
3427                        }
3428                        if (file->f_mode & FMODE_WRITE) {
3429                                stop_dac(s);
3430                                s->dma_dac.ready = 0;
3431                                if (val != AFMT_S16_LE
3432                                    && val != AFMT_U16_LE && val != AFMT_S8
3433                                    && val != AFMT_U8)
3434                                        val = AFMT_U8;
3435                                s->prop_dac.fmt = val;
3436                                s->prop_dac.fmt_original = s->prop_dac.fmt;
3437                                prog_codec(s, CS_TYPE_DAC);
3438                        }
3439                } else {
3440                        if (file->f_mode & FMODE_WRITE)
3441                                val = s->prop_dac.fmt_original;
3442                        else if (file->f_mode & FMODE_READ)
3443                                val = s->prop_adc.fmt_original;
3444                }
3445                CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO
3446                  "cs4281: cs4281_ioctl(): DSP_SETFMT return val=0x%.8x\n", 
3447                        val));
3448                return put_user(val, (int *) arg);
3449
3450        case SNDCTL_DSP_POST:
3451                CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO
3452                         "cs4281: cs4281_ioctl(): DSP_POST\n"));
3453                return 0;
3454
3455        case SNDCTL_DSP_GETTRIGGER:
3456                val = 0;
3457                if (file->f_mode & s->ena & FMODE_READ)
3458                        val |= PCM_ENABLE_INPUT;
3459                if (file->f_mode & s->ena & FMODE_WRITE)
3460                        val |= PCM_ENABLE_OUTPUT;
3461                return put_user(val, (int *) arg);
3462
3463        case SNDCTL_DSP_SETTRIGGER:
3464                if (get_user(val, (int *) arg))
3465                        return -EFAULT;
3466                if (file->f_mode & FMODE_READ) {
3467                        if (val & PCM_ENABLE_INPUT) {
3468                                if (!s->dma_adc.ready
3469                                    && (ret = prog_dmabuf_adc(s)))
3470                                        return ret;
3471                                start_adc(s);
3472                        } else
3473                                stop_adc(s);
3474                }
3475                if (file->f_mode & FMODE_WRITE) {
3476                        if (val & PCM_ENABLE_OUTPUT) {
3477                                if (!s->dma_dac.ready
3478                                    && (ret = prog_dmabuf_dac(s)))
3479                                        return ret;
3480                                start_dac(s);
3481                        } else
3482                                stop_dac(s);
3483                }
3484                return 0;
3485
3486        case SNDCTL_DSP_GETOSPACE:
3487                if (!(file->f_mode & FMODE_WRITE))
3488                        return -EINVAL;
3489                if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s)))
3490                        return val;
3491                spin_lock_irqsave(&s->lock, flags);
3492                cs4281_update_ptr(s,CS_TRUE);
3493                abinfo.fragsize = s->dma_dac.fragsize;
3494                if (s->dma_dac.mapped)
3495                        abinfo.bytes = s->dma_dac.dmasize;
3496                else
3497                        abinfo.bytes =
3498                            s->dma_dac.dmasize - s->dma_dac.count;
3499                abinfo.fragstotal = s->dma_dac.numfrag;
3500                abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift;
3501                CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO
3502                        "cs4281: cs4281_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n",
3503                                abinfo.fragsize,abinfo.bytes,abinfo.fragstotal,
3504                                abinfo.fragments));
3505                spin_unlock_irqrestore(&s->lock, flags);
3506                return copy_to_user((void *) arg, &abinfo,
3507                                    sizeof(abinfo)) ? -EFAULT : 0;
3508
3509        case SNDCTL_DSP_GETISPACE:
3510                if (!(file->f_mode & FMODE_READ))
3511                        return -EINVAL;
3512                if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s)))
3513                        return val;
3514                spin_lock_irqsave(&s->lock, flags);
3515                cs4281_update_ptr(s,CS_TRUE);
3516                if (s->conversion) {
3517                        abinfo.fragsize = s->dma_adc.fragsize / 2;
3518                        abinfo.bytes = s->dma_adc.count / 2;
3519                        abinfo.fragstotal = s->dma_adc.numfrag;
3520                        abinfo.fragments =
3521                            abinfo.bytes >> (s->dma_adc.fragshift - 1);
3522                } else {
3523                        abinfo.fragsize = s->dma_adc.fragsize;
3524                        abinfo.bytes = s->dma_adc.count;
3525                        abinfo.fragstotal = s->dma_adc.numfrag;
3526                        abinfo.fragments =
3527                            abinfo.bytes >> s->dma_adc.fragshift;
3528                }
3529                spin_unlock_irqrestore(&s->lock, flags);
3530                return copy_to_user((void *) arg, &abinfo,
3531                                    sizeof(abinfo)) ? -EFAULT : 0;
3532
3533        case SNDCTL_DSP_NONBLOCK:
3534                file->f_flags |= O_NONBLOCK;
3535                return 0;
3536
3537        case SNDCTL_DSP_GETODELAY:
3538                if (!(file->f_mode & FMODE_WRITE))
3539                        return -EINVAL;
3540                if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3541                        return 0;
3542                spin_lock_irqsave(&s->lock, flags);
3543                cs4281_update_ptr(s,CS_TRUE);
3544                val = s->dma_dac.count;
3545                spin_unlock_irqrestore(&s->lock, flags);
3546                return put_user(val, (int *) arg);
3547
3548        case SNDCTL_DSP_GETIPTR:
3549                if (!(file->f_mode & FMODE_READ))
3550                        return -EINVAL;
3551                if(!s->dma_adc.ready && prog_dmabuf_adc(s))
3552                        return 0;
3553                spin_lock_irqsave(&s->lock, flags);
3554                cs4281_update_ptr(s,CS_TRUE);
3555                cinfo.bytes = s->dma_adc.total_bytes;
3556                if (s->dma_adc.mapped) {
3557                        cinfo.blocks =
3558                            (cinfo.bytes >> s->dma_adc.fragshift) -
3559                            s->dma_adc.blocks;
3560                        s->dma_adc.blocks =
3561                            cinfo.bytes >> s->dma_adc.fragshift;
3562                } else {
3563                        if (s->conversion) {
3564                                cinfo.blocks =
3565                                    s->dma_adc.count /
3566                                    2 >> (s->dma_adc.fragshift - 1);
3567                        } else
3568                                cinfo.blocks =
3569                                    s->dma_adc.count >> s->dma_adc.
3570                                    fragshift;
3571                }
3572                if (s->conversion)
3573                        cinfo.ptr = s->dma_adc.hwptr / 2;
3574                else
3575                        cinfo.ptr = s->dma_adc.hwptr;
3576                if (s->dma_adc.mapped)
3577                        s->dma_adc.count &= s->dma_adc.fragsize - 1;
3578                spin_unlock_irqrestore(&s->lock, flags);
3579                return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
3580
3581        case SNDCTL_DSP_GETOPTR:
3582                if (!(file->f_mode & FMODE_WRITE))
3583                        return -EINVAL;
3584                if(!s->dma_dac.ready && prog_dmabuf_dac(s))
3585                        return 0;
3586                spin_lock_irqsave(&s->lock, flags);
3587                cs4281_update_ptr(s,CS_TRUE);
3588                cinfo.bytes = s->dma_dac.total_bytes;
3589                if (s->dma_dac.mapped) {
3590                        cinfo.blocks =
3591                            (cinfo.bytes >> s->dma_dac.fragshift) -
3592                            s->dma_dac.blocks;
3593                        s->dma_dac.blocks =
3594                            cinfo.bytes >> s->dma_dac.fragshift;
3595                } else {
3596                        cinfo.blocks =
3597                            s->dma_dac.count >> s->dma_dac.fragshift;
3598                }
3599                cinfo.ptr = s->dma_dac.hwptr;
3600                if (s->dma_dac.mapped)
3601                        s->dma_dac.count &= s->dma_dac.fragsize - 1;
3602                spin_unlock_irqrestore(&s->lock, flags);
3603                return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0;
3604
3605        case SNDCTL_DSP_GETBLKSIZE:
3606                if (file->f_mode & FMODE_WRITE) {
3607                        if ((val = prog_dmabuf_dac(s)))
3608                                return val;
3609                        return put_user(s->dma_dac.fragsize, (int *) arg);
3610                }
3611                if ((val = prog_dmabuf_adc(s)))
3612                        return val;
3613                if (s->conversion)
3614                        return put_user(s->dma_adc.fragsize / 2,
3615                                        (int *) arg);
3616                else
3617                        return put_user(s->dma_adc.fragsize, (int *) arg);
3618
3619        case SNDCTL_DSP_SETFRAGMENT:
3620                if (get_user(val, (int *) arg))
3621                        return -EFAULT;
3622
3623                CS_DBGOUT(CS_PARMS, 4, printk(KERN_INFO
3624                        "cs4281: cs4281_ioctl(): Attempt to set fragsize=%d fragnum=%d\n",
3625                                1 << (val & 0xffff), (val >> 16) & 0xffff  ));
3626                return 0;       // Say OK, but do nothing.
3627
3628        case SNDCTL_DSP_SUBDIVIDE:
3629                if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision)
3630                    || (file->f_mode & FMODE_WRITE
3631                        && s->dma_dac.subdivision)) return -EINVAL;
3632                if (get_user(val, (int *) arg))
3633                        return -EFAULT;
3634                if (val != 1 && val != 2 && val != 4)
3635                        return -EINVAL;
3636                if (file->f_mode & FMODE_READ)
3637                        s->dma_adc.subdivision = val;
3638                else if (file->f_mode & FMODE_WRITE)
3639                        s->dma_dac.subdivision = val;
3640                return 0;
3641
3642        case SOUND_PCM_READ_RATE:
3643                if (file->f_mode & FMODE_READ)
3644                        return put_user(s->prop_adc.rate, (int *) arg);
3645                else if (file->f_mode & FMODE_WRITE)
3646                        return put_user(s->prop_dac.rate, (int *) arg);
3647
3648        case SOUND_PCM_READ_CHANNELS:
3649                if (file->f_mode & FMODE_READ)
3650                        return put_user(s->prop_adc.channels, (int *) arg);
3651                else if (file->f_mode & FMODE_WRITE)
3652                        return put_user(s->prop_dac.channels, (int *) arg);
3653
3654        case SOUND_PCM_READ_BITS:
3655                if (file->f_mode & FMODE_READ)
3656                        return
3657                            put_user(
3658                                     (s->prop_adc.
3659                                      fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3660                                     (int *) arg);
3661                else if (file->f_mode & FMODE_WRITE)
3662                        return
3663                            put_user(
3664                                     (s->prop_dac.
3665                                      fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16,
3666                                     (int *) arg);
3667
3668        case SOUND_PCM_WRITE_FILTER:
3669        case SNDCTL_DSP_SETSYNCRO:
3670        case SOUND_PCM_READ_FILTER:
3671                return -EINVAL;
3672        }
3673        return mixer_ioctl(s, cmd, arg);
3674}
3675
3676
3677static int cs4281_release(struct inode *inode, struct file *file)
3678{
3679        struct cs4281_state *s =
3680            (struct cs4281_state *) file->private_data;
3681
3682        CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO
3683                 "cs4281: cs4281_release(): inode=0x%.8x file=0x%.8x f_mode=%d\n",
3684                         (unsigned) inode, (unsigned) file, file->f_mode));
3685
3686        VALIDATE_STATE(s);
3687
3688        if (file->f_mode & FMODE_WRITE) {
3689                drain_dac(s, file->f_flags & O_NONBLOCK);
3690                down(&s->open_sem_dac);
3691                stop_dac(s);
3692                dealloc_dmabuf(s, &s->dma_dac);
3693                s->open_mode &= ~FMODE_WRITE;
3694                up(&s->open_sem_dac);
3695                wake_up(&s->open_wait_dac);
3696                MOD_DEC_USE_COUNT;
3697        }
3698        if (file->f_mode & FMODE_READ) {
3699                drain_adc(s, file->f_flags & O_NONBLOCK);
3700                down(&s->open_sem_adc);
3701                stop_adc(s);
3702                dealloc_dmabuf(s, &s->dma_adc);
3703                s->open_mode &= ~FMODE_READ;
3704                up(&s->open_sem_adc);
3705                wake_up(&s->open_wait_adc);
3706                MOD_DEC_USE_COUNT;
3707        }
3708        return 0;
3709}
3710
3711static int cs4281_open(struct inode *inode, struct file *file)
3712{
3713        int minor = MINOR(inode->i_rdev);
3714        struct cs4281_state *s=NULL;
3715        struct list_head *entry;
3716
3717        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3718                "cs4281: cs4281_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n",
3719                        (unsigned) inode, (unsigned) file, file->f_mode));
3720
3721        list_for_each(entry, &cs4281_devs)
3722        {
3723                s = list_entry(entry, struct cs4281_state, list);
3724
3725                if (!((s->dev_audio ^ minor) & ~0xf))
3726                        break;
3727        }
3728        if (entry == &cs4281_devs)
3729                return -ENODEV;
3730        if (!s) {
3731                CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
3732                        "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
3733                return -ENODEV;
3734        }
3735        VALIDATE_STATE(s);
3736        file->private_data = s;
3737
3738        // wait for device to become free 
3739        if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) {
3740                CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO
3741                         "cs4281: cs4281_open(): Error - must open READ and/or WRITE\n"));
3742                return -ENODEV;
3743        }
3744        if (file->f_mode & FMODE_WRITE) {
3745                down(&s->open_sem_dac);
3746                while (s->open_mode & FMODE_WRITE) {
3747                        if (file->f_flags & O_NONBLOCK) {
3748                                up(&s->open_sem_dac);
3749                                return -EBUSY;
3750                        }
3751                        up(&s->open_sem_dac);
3752                        interruptible_sleep_on(&s->open_wait_dac);
3753
3754                        if (signal_pending(current))
3755                                return -ERESTARTSYS;
3756                        down(&s->open_sem_dac);
3757                }
3758        }
3759        if (file->f_mode & FMODE_READ) {
3760                down(&s->open_sem_adc);
3761                while (s->open_mode & FMODE_READ) {
3762                        if (file->f_flags & O_NONBLOCK) {
3763                                up(&s->open_sem_adc);
3764                                return -EBUSY;
3765                        }
3766                        up(&s->open_sem_adc);
3767                        interruptible_sleep_on(&s->open_wait_adc);
3768
3769                        if (signal_pending(current))
3770                                return -ERESTARTSYS;
3771                        down(&s->open_sem_adc);
3772                }
3773        }
3774        s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE);
3775        if (file->f_mode & FMODE_READ) {
3776                s->prop_adc.fmt = AFMT_U8;
3777                s->prop_adc.fmt_original = s->prop_adc.fmt;
3778                s->prop_adc.channels = 1;
3779                s->prop_adc.rate = 8000;
3780                s->prop_adc.clkdiv = 96 | 0x80;
3781                s->conversion = 0;
3782                s->ena &= ~FMODE_READ;
3783                s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags =
3784                    s->dma_adc.subdivision = 0;
3785                up(&s->open_sem_adc);
3786                MOD_INC_USE_COUNT;
3787
3788                if (prog_dmabuf_adc(s)) {
3789                        CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3790                                "cs4281: adc Program dmabufs failed.\n"));
3791                        cs4281_release(inode, file);
3792                        return -ENOMEM;
3793                }
3794                prog_codec(s, CS_TYPE_ADC);
3795        }
3796        if (file->f_mode & FMODE_WRITE) {
3797                s->prop_dac.fmt = AFMT_U8;
3798                s->prop_dac.fmt_original = s->prop_dac.fmt;
3799                s->prop_dac.channels = 1;
3800                s->prop_dac.rate = 8000;
3801                s->prop_dac.clkdiv = 96 | 0x80;
3802                s->conversion = 0;
3803                s->ena &= ~FMODE_WRITE;
3804                s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags =
3805                    s->dma_dac.subdivision = 0;
3806                up(&s->open_sem_dac);
3807                MOD_INC_USE_COUNT;
3808
3809                if (prog_dmabuf_dac(s)) {
3810                        CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR
3811                                "cs4281: dac Program dmabufs failed.\n"));
3812                        cs4281_release(inode, file);
3813                        return -ENOMEM;
3814                }
3815                prog_codec(s, CS_TYPE_DAC);
3816        }
3817        CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2,
3818                  printk(KERN_INFO "cs4281: cs4281_open()- 0\n"));
3819        return 0;
3820}
3821
3822
3823// ******************************************************************************************
3824//   Wave (audio) file operations struct.
3825// ******************************************************************************************
3826static /*const */ struct file_operations cs4281_audio_fops = {
3827        llseek:no_llseek,
3828        read:cs4281_read,
3829        write:cs4281_write,
3830        poll:cs4281_poll,
3831        ioctl:cs4281_ioctl,
3832        mmap:cs4281_mmap,
3833        open:cs4281_open,
3834        release:cs4281_release,
3835};
3836
3837// --------------------------------------------------------------------- 
3838
3839// hold spinlock for the following! 
3840static void cs4281_handle_midi(struct cs4281_state *s)
3841{
3842        unsigned char ch;
3843        int wake;
3844        unsigned temp1;
3845
3846        wake = 0;
3847        while (!(readl(s->pBA0 + BA0_MIDSR) & 0x80)) {
3848                ch = readl(s->pBA0 + BA0_MIDRP);
3849                if (s->midi.icnt < MIDIINBUF) {
3850                        s->midi.ibuf[s->midi.iwr] = ch;
3851                        s->midi.iwr = (s->midi.iwr + 1) % MIDIINBUF;
3852                        s->midi.icnt++;
3853                }
3854                wake = 1;
3855        }
3856        if (wake)
3857                wake_up(&s->midi.iwait);
3858        wake = 0;
3859        while (!(readl(s->pBA0 + BA0_MIDSR) & 0x40) && s->midi.ocnt > 0) {
3860                temp1 = (s->midi.obuf[s->midi.ord]) & 0x000000ff;
3861                writel(temp1, s->pBA0 + BA0_MIDWP);
3862                s->midi.ord = (s->midi.ord + 1) % MIDIOUTBUF;
3863                s->midi.ocnt--;
3864                if (s->midi.ocnt < MIDIOUTBUF - 16)
3865                        wake = 1;
3866        }
3867        if (wake)
3868                wake_up(&s->midi.owait);
3869}
3870
3871
3872
3873static void cs4281_interrupt(int irq, void *dev_id, struct pt_regs *regs)
3874{
3875        struct cs4281_state *s = (struct cs4281_state *) dev_id;
3876        unsigned int temp1;
3877
3878        // fastpath out, to ease interrupt sharing 
3879        temp1 = readl(s->pBA0 + BA0_HISR);      // Get Int Status reg.
3880
3881        CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO
3882                  "cs4281: cs4281_interrupt() BA0_HISR=0x%.8x\n", temp1));
3883/*
3884* If not DMA or MIDI interrupt, then just return.
3885*/
3886        if (!(temp1 & (HISR_DMA0 | HISR_DMA1 | HISR_MIDI))) {
3887                writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);
3888                CS_DBGOUT(CS_INTERRUPT, 9, printk(KERN_INFO
3889                        "cs4281: cs4281_interrupt(): returning not cs4281 interrupt.\n"));
3890                return;
3891        }
3892
3893        if (temp1 & HISR_DMA0)  // If play interrupt,
3894                readl(s->pBA0 + BA0_HDSR0);     //   clear the source.
3895
3896        if (temp1 & HISR_DMA1)  // Same for play.
3897                readl(s->pBA0 + BA0_HDSR1);
3898        writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Local EOI
3899
3900        spin_lock(&s->lock);
3901        cs4281_update_ptr(s,CS_TRUE);
3902        cs4281_handle_midi(s);
3903        spin_unlock(&s->lock);
3904}
3905
3906// **************************************************************************
3907
3908static void cs4281_midi_timer(unsigned long data)
3909{
3910        struct cs4281_state *s = (struct cs4281_state *) data;
3911        unsigned long flags;
3912
3913        spin_lock_irqsave(&s->lock, flags);
3914        cs4281_handle_midi(s);
3915        spin_unlock_irqrestore(&s->lock, flags);
3916        s->midi.timer.expires = jiffies + 1;
3917        add_timer(&s->midi.timer);
3918}
3919
3920
3921// --------------------------------------------------------------------- 
3922
3923static ssize_t cs4281_midi_read(struct file *file, char *buffer,
3924                                size_t count, loff_t * ppos)
3925{
3926        struct cs4281_state *s =
3927            (struct cs4281_state *) file->private_data;
3928        ssize_t ret;
3929        unsigned long flags;
3930        unsigned ptr;
3931        int cnt;
3932
3933        VALIDATE_STATE(s);
3934        if (ppos != &file->f_pos)
3935                return -ESPIPE;
3936        if (!access_ok(VERIFY_WRITE, buffer, count))
3937                return -EFAULT;
3938        ret = 0;
3939        while (count > 0) {
3940                spin_lock_irqsave(&s->lock, flags);
3941                ptr = s->midi.ird;
3942                cnt = MIDIINBUF - ptr;
3943                if (s->midi.icnt < cnt)
3944                        cnt = s->midi.icnt;
3945                spin_unlock_irqrestore(&s->lock, flags);
3946                if (cnt > count)
3947                        cnt = count;
3948                if (cnt <= 0) {
3949                        if (file->f_flags & O_NONBLOCK)
3950                                return ret ? ret : -EAGAIN;
3951                        interruptible_sleep_on(&s->midi.iwait);
3952                        if (signal_pending(current))
3953                                return ret ? ret : -ERESTARTSYS;
3954                        continue;
3955                }
3956                if (copy_to_user(buffer, s->midi.ibuf + ptr, cnt))
3957                        return ret ? ret : -EFAULT;
3958                ptr = (ptr + cnt) % MIDIINBUF;
3959                spin_lock_irqsave(&s->lock, flags);
3960                s->midi.ird = ptr;
3961                s->midi.icnt -= cnt;
3962                spin_unlock_irqrestore(&s->lock, flags);
3963                count -= cnt;
3964                buffer += cnt;
3965                ret += cnt;
3966        }
3967        return ret;
3968}
3969
3970
3971static ssize_t cs4281_midi_write(struct file *file, const char *buffer,
3972                                 size_t count, loff_t * ppos)
3973{
3974        struct cs4281_state *s =
3975            (struct cs4281_state *) file->private_data;
3976        ssize_t ret;
3977        unsigned long flags;
3978        unsigned ptr;
3979        int cnt;
3980
3981        VALIDATE_STATE(s);
3982        if (ppos != &file->f_pos)
3983                return -ESPIPE;
3984        if (!access_ok(VERIFY_READ, buffer, count))
3985                return -EFAULT;
3986        ret = 0;
3987        while (count > 0) {
3988                spin_lock_irqsave(&s->lock, flags);
3989                ptr = s->midi.owr;
3990                cnt = MIDIOUTBUF - ptr;
3991                if (s->midi.ocnt + cnt > MIDIOUTBUF)
3992                        cnt = MIDIOUTBUF - s->midi.ocnt;
3993                if (cnt <= 0)
3994                        cs4281_handle_midi(s);
3995                spin_unlock_irqrestore(&s->lock, flags);
3996                if (cnt > count)
3997                        cnt = count;
3998                if (cnt <= 0) {
3999                        if (file->f_flags & O_NONBLOCK)
4000                                return ret ? ret : -EAGAIN;
4001                        interruptible_sleep_on(&s->midi.owait);
4002                        if (signal_pending(current))
4003                                return ret ? ret : -ERESTARTSYS;
4004                        continue;
4005                }
4006                if (copy_from_user(s->midi.obuf + ptr, buffer, cnt))
4007                        return ret ? ret : -EFAULT;
4008                ptr = (ptr + cnt) % MIDIOUTBUF;
4009                spin_lock_irqsave(&s->lock, flags);
4010                s->midi.owr = ptr;
4011                s->midi.ocnt += cnt;
4012                spin_unlock_irqrestore(&s->lock, flags);
4013                count -= cnt;
4014                buffer += cnt;
4015                ret += cnt;
4016                spin_lock_irqsave(&s->lock, flags);
4017                cs4281_handle_midi(s);
4018                spin_unlock_irqrestore(&s->lock, flags);
4019        }
4020        return ret;
4021}
4022
4023
4024static unsigned int cs4281_midi_poll(struct file *file,
4025                                     struct poll_table_struct *wait)
4026{
4027        struct cs4281_state *s =
4028            (struct cs4281_state *) file->private_data;
4029        unsigned long flags;
4030        unsigned int mask = 0;
4031
4032        VALIDATE_STATE(s);
4033        if (file->f_flags & FMODE_WRITE)
4034                poll_wait(file, &s->midi.owait, wait);
4035        if (file->f_flags & FMODE_READ)
4036                poll_wait(file, &s->midi.iwait, wait);
4037        spin_lock_irqsave(&s->lock, flags);
4038        if (file->f_flags & FMODE_READ) {
4039                if (s->midi.icnt > 0)
4040                        mask |= POLLIN | POLLRDNORM;
4041        }
4042        if (file->f_flags & FMODE_WRITE) {
4043                if (s->midi.ocnt < MIDIOUTBUF)
4044                        mask |= POLLOUT | POLLWRNORM;
4045        }
4046        spin_unlock_irqrestore(&s->lock, flags);
4047        return mask;
4048}
4049
4050
4051static int cs4281_midi_open(struct inode *inode, struct file *file)
4052{
4053        unsigned long flags, temp1;
4054        int minor = MINOR(inode->i_rdev);
4055        struct cs4281_state *s=NULL;
4056        struct list_head *entry;
4057        list_for_each(entry, &cs4281_devs)
4058        {
4059                s = list_entry(entry, struct cs4281_state, list);
4060
4061                if (s->dev_midi == minor)
4062                        break;
4063        }
4064
4065        if (entry == &cs4281_devs)
4066                return -ENODEV;
4067        if (!s)
4068        {
4069                CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO
4070                        "cs4281: cs4281_open(): Error - unable to find audio state struct\n"));
4071                return -ENODEV;
4072        }
4073        VALIDATE_STATE(s);
4074        file->private_data = s;
4075        // wait for device to become free 
4076        down(&s->open_sem);
4077        while (s->open_mode & (file->f_mode << FMODE_MIDI_SHIFT)) {
4078                if (file->f_flags & O_NONBLOCK) {
4079                        up(&s->open_sem);
4080                        return -EBUSY;
4081                }
4082                up(&s->open_sem);
4083                interruptible_sleep_on(&s->open_wait);
4084                if (signal_pending(current))
4085                        return -ERESTARTSYS;
4086                down(&s->open_sem);
4087        }
4088        spin_lock_irqsave(&s->lock, flags);
4089        if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4090                s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4091                s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4092                writel(1, s->pBA0 + BA0_MIDCR); // Reset the interface.
4093                writel(0, s->pBA0 + BA0_MIDCR); // Return to normal mode.
4094                s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4095                writel(0x0000000f, s->pBA0 + BA0_MIDCR);        // Enable transmit, record, ints.
4096                temp1 = readl(s->pBA0 + BA0_HIMR);
4097                writel(temp1 & 0xffbfffff, s->pBA0 + BA0_HIMR); // Enable midi int. recognition.
4098                writel(HICR_IEV | HICR_CHGM, s->pBA0 + BA0_HICR);       // Enable interrupts
4099                init_timer(&s->midi.timer);
4100                s->midi.timer.expires = jiffies + 1;
4101                s->midi.timer.data = (unsigned long) s;
4102                s->midi.timer.function = cs4281_midi_timer;
4103                add_timer(&s->midi.timer);
4104        }
4105        if (file->f_mode & FMODE_READ) {
4106                s->midi.ird = s->midi.iwr = s->midi.icnt = 0;
4107        }
4108        if (file->f_mode & FMODE_WRITE) {
4109                s->midi.ord = s->midi.owr = s->midi.ocnt = 0;
4110        }
4111        spin_unlock_irqrestore(&s->lock, flags);
4112        s->open_mode |=
4113            (file->
4114             f_mode << FMODE_MIDI_SHIFT) & (FMODE_MIDI_READ |
4115                                            FMODE_MIDI_WRITE);
4116        up(&s->open_sem);
4117        MOD_INC_USE_COUNT;
4118        return 0;
4119}
4120
4121
4122static int cs4281_midi_release(struct inode *inode, struct file *file)
4123{
4124        struct cs4281_state *s =
4125            (struct cs4281_state *) file->private_data;
4126        DECLARE_WAITQUEUE(wait, current);
4127        unsigned long flags;
4128        unsigned count, tmo;
4129
4130        VALIDATE_STATE(s);
4131
4132        if (file->f_mode & FMODE_WRITE) {
4133                add_wait_queue(&s->midi.owait, &wait);
4134                for (;;) {
4135                        set_current_state(TASK_INTERRUPTIBLE);
4136                        spin_lock_irqsave(&s->lock, flags);
4137                        count = s->midi.ocnt;
4138                        spin_unlock_irqrestore(&s->lock, flags);
4139                        if (count <= 0)
4140                                break;
4141                        if (signal_pending(current))
4142                                break;
4143                        if (file->f_flags & O_NONBLOCK) {
4144                                remove_wait_queue(&s->midi.owait, &wait);
4145                                current->state = TASK_RUNNING;
4146                                return -EBUSY;
4147                        }
4148                        tmo = (count * HZ) / 3100;
4149                        if (!schedule_timeout(tmo ? : 1) && tmo)
4150                                printk(KERN_DEBUG
4151                                       "cs4281: midi timed out??\n");
4152                }
4153                remove_wait_queue(&s->midi.owait, &wait);
4154                current->state = TASK_RUNNING;
4155        }
4156        down(&s->open_sem);
4157        s->open_mode &=
4158            (~(file->f_mode << FMODE_MIDI_SHIFT)) & (FMODE_MIDI_READ |
4159                                                     FMODE_MIDI_WRITE);
4160        spin_lock_irqsave(&s->lock, flags);
4161        if (!(s->open_mode & (FMODE_MIDI_READ | FMODE_MIDI_WRITE))) {
4162                writel(0, s->pBA0 + BA0_MIDCR); // Disable Midi interrupts.  
4163                del_timer(&s->midi.timer);
4164        }
4165        spin_unlock_irqrestore(&s->lock, flags);
4166        up(&s->open_sem);
4167        wake_up(&s->open_wait);
4168        MOD_DEC_USE_COUNT;
4169        return 0;
4170}
4171
4172// ******************************************************************************************
4173//   Midi file operations struct.
4174// ******************************************************************************************
4175static /*const */ struct file_operations cs4281_midi_fops = {
4176        llseek:no_llseek,
4177        read:cs4281_midi_read,
4178        write:cs4281_midi_write,
4179        poll:cs4281_midi_poll,
4180        open:cs4281_midi_open,
4181        release:cs4281_midi_release,
4182};
4183
4184
4185// --------------------------------------------------------------------- 
4186
4187// maximum number of devices 
4188#define NR_DEVICE 8             // Only eight devices supported currently.
4189
4190// --------------------------------------------------------------------- 
4191
4192static struct initvol {
4193        int mixch;
4194        int vol;
4195} initvol[] __initdata = {
4196
4197        {
4198        SOUND_MIXER_WRITE_VOLUME, 0x4040}, {
4199        SOUND_MIXER_WRITE_PCM, 0x4040}, {
4200        SOUND_MIXER_WRITE_SYNTH, 0x4040}, {
4201        SOUND_MIXER_WRITE_CD, 0x4040}, {
4202        SOUND_MIXER_WRITE_LINE, 0x4040}, {
4203        SOUND_MIXER_WRITE_LINE1, 0x4040}, {
4204        SOUND_MIXER_WRITE_RECLEV, 0x0000}, {
4205        SOUND_MIXER_WRITE_SPEAKER, 0x4040}, {
4206        SOUND_MIXER_WRITE_MIC, 0x0000}
4207};
4208
4209
4210#ifndef NOT_CS4281_PM
4211void __devinit cs4281_BuildFIFO(
4212        struct cs4281_pipeline *p, 
4213        struct cs4281_state *s)
4214{
4215        switch(p->number)
4216        {
4217                case 0:  /* playback */
4218                {
4219                        p->u32FCRnAddress  =  BA0_FCR0;
4220                        p->u32FSICnAddress = BA0_FSIC0;
4221                        p->u32FPDRnAddress = BA0_FPDR0;
4222                        break;
4223                }
4224                case 1:  /* capture */
4225                {
4226                        p->u32FCRnAddress  =  BA0_FCR1;
4227                        p->u32FSICnAddress = BA0_FSIC1;
4228                        p->u32FPDRnAddress = BA0_FPDR1;
4229                        break;
4230                }
4231
4232                case 2: 
4233                {
4234                        p->u32FCRnAddress  =  BA0_FCR2;
4235                        p->u32FSICnAddress = BA0_FSIC2;
4236                        p->u32FPDRnAddress = BA0_FPDR2;
4237                        break;
4238                }
4239                case 3: 
4240                {
4241                        p->u32FCRnAddress  =  BA0_FCR3;
4242                        p->u32FSICnAddress = BA0_FSIC3;
4243                        p->u32FPDRnAddress = BA0_FPDR3;
4244                        break;
4245                }
4246                default:
4247                        break;
4248        }
4249        //
4250        // first read the hardware to initialize the member variables
4251        //
4252        p->u32FCRnValue = readl(s->pBA0 + p->u32FCRnAddress);
4253        p->u32FSICnValue = readl(s->pBA0 + p->u32FSICnAddress);
4254        p->u32FPDRnValue = readl(s->pBA0 + p->u32FPDRnAddress);
4255
4256}
4257
4258void __devinit cs4281_BuildDMAengine(
4259        struct cs4281_pipeline *p, 
4260        struct cs4281_state *s)
4261{
4262/*
4263* initialize all the addresses of this pipeline dma info.
4264*/
4265        switch(p->number)
4266        {
4267                case 0:  /* playback */
4268                {
4269                        p->u32DBAnAddress = BA0_DBA0;
4270                        p->u32DCAnAddress = BA0_DCA0;
4271                        p->u32DBCnAddress = BA0_DBC0;
4272                        p->u32DCCnAddress = BA0_DCC0;
4273                        p->u32DMRnAddress = BA0_DMR0;
4274                        p->u32DCRnAddress = BA0_DCR0;
4275                        p->u32HDSRnAddress = BA0_HDSR0;
4276                        break;
4277                }
4278
4279                case 1: /* capture */
4280                {
4281                        p->u32DBAnAddress = BA0_DBA1;
4282                        p->u32DCAnAddress = BA0_DCA1;
4283                        p->u32DBCnAddress = BA0_DBC1;
4284                        p->u32DCCnAddress = BA0_DCC1;
4285                        p->u32DMRnAddress = BA0_DMR1;
4286                        p->u32DCRnAddress = BA0_DCR1;
4287                        p->u32HDSRnAddress = BA0_HDSR1;
4288                        break;
4289                }
4290
4291                case 2:
4292                {
4293                        p->u32DBAnAddress = BA0_DBA2;
4294                        p->u32DCAnAddress = BA0_DCA2;
4295                        p->u32DBCnAddress = BA0_DBC2;
4296                        p->u32DCCnAddress = BA0_DCC2;
4297                        p->u32DMRnAddress = BA0_DMR2;
4298                        p->u32DCRnAddress = BA0_DCR2;
4299                        p->u32HDSRnAddress = BA0_HDSR2;
4300                        break;
4301                }
4302
4303                case 3:
4304                {
4305                        p->u32DBAnAddress = BA0_DBA3;
4306                        p->u32DCAnAddress = BA0_DCA3;
4307                        p->u32DBCnAddress = BA0_DBC3;
4308                        p->u32DCCnAddress = BA0_DCC3;
4309                        p->u32DMRnAddress = BA0_DMR3;
4310                        p->u32DCRnAddress = BA0_DCR3;
4311                        p->u32HDSRnAddress = BA0_HDSR3;
4312                        break;
4313                }
4314                default:
4315                        break;
4316        }
4317
4318//
4319// Initialize the dma values for this pipeline
4320//
4321        p->u32DBAnValue = readl(s->pBA0 + p->u32DBAnAddress);
4322        p->u32DBCnValue = readl(s->pBA0 + p->u32DBCnAddress);
4323        p->u32DMRnValue = readl(s->pBA0 + p->u32DMRnAddress);
4324        p->u32DCRnValue = readl(s->pBA0 + p->u32DCRnAddress);
4325
4326}
4327
4328void __devinit cs4281_InitPM(struct cs4281_state *s)
4329{
4330        int i;
4331        struct cs4281_pipeline *p;
4332
4333        for(i=0;i<CS4281_NUMBER_OF_PIPELINES;i++)
4334        {
4335                p = &s->pl[i];
4336                p->number = i;
4337                cs4281_BuildDMAengine(p,s);
4338                cs4281_BuildFIFO(p,s);
4339        /*
4340        * currently only  2 pipelines are used
4341        * so, only set the valid bit on the playback and capture.
4342        */
4343                if( (i == CS4281_PLAYBACK_PIPELINE_NUMBER) || 
4344                        (i == CS4281_CAPTURE_PIPELINE_NUMBER))
4345                        p->flags |= CS4281_PIPELINE_VALID;
4346        }
4347        s->pm.u32SSPM_BITS = 0x7e;  /* rev c, use 0x7c for rev a or b */
4348}
4349#endif
4350
4351/*
4352* ss_vendor and ss_id must be setup prior to calling this routine.
4353* setup the invalid recording source bitmask,
4354* and also return a valid default initialization value as
4355* the return value;
4356*/
4357static int cs4281_setup_record_src(struct cs4281_state *s)
4358{
4359        if(s->ss_vendor == PCI_VENDOR_ID_TOSHIBA)
4360        {
4361                if(s->ss_id == SS_ID_TOSHIBA_1640CDT)
4362                {
4363                        CS_DBGOUT(CS_PARMS, 2, printk(KERN_INFO
4364                          "cs4281: cs4281_setup_record_src(): setting LINE invalid\n"));
4365                        recsrc_invalid |= SOUND_MASK_LINE;
4366                }
4367        }
4368/*
4369* only return a valid recsrc value here, default to something useful.
4370*/
4371        if(!(recsrc_invalid & SOUND_MASK_MIC))
4372                return(SOUND_MASK_MIC);
4373        else if(!(recsrc_invalid & SOUND_MASK_LINE))
4374                return(SOUND_MASK_LINE);
4375        else if(!(recsrc_invalid & SOUND_MASK_LINE1))
4376                return(SOUND_MASK_LINE1);
4377        return 0;
4378}
4379
4380static int __devinit cs4281_probe(struct pci_dev *pcidev,
4381                                  const struct pci_device_id *pciid)
4382{
4383#ifndef NOT_CS4281_PM
4384        struct pm_dev *pmdev;
4385#endif
4386        struct cs4281_state *s;
4387        dma_addr_t dma_mask;
4388        mm_segment_t fs;
4389        int i, val;
4390        unsigned int temp1, temp2;
4391
4392        CS_DBGOUT(CS_FUNCTION | CS_INIT, 2,
4393                  printk(KERN_INFO "cs4281: probe()+\n"));
4394
4395        if (pci_enable_device(pcidev)) {
4396                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4397                         "cs4281: pci_enable_device() failed\n"));
4398                return -1;
4399        }
4400        if (!(pci_resource_flags(pcidev, 0) & IORESOURCE_MEM) ||
4401            !(pci_resource_flags(pcidev, 1) & IORESOURCE_MEM)) {
4402                CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4403                         "cs4281: probe()- Memory region not assigned\n"));
4404                return -ENODEV;
4405        }
4406        if (pcidev->irq == 0) {
4407                CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4408                         "cs4281: probe() IRQ not assigned\n"));
4409                return -ENODEV;
4410        }
4411        dma_mask = 0xffffffff;  /* this enables playback and recording */
4412        i = pci_set_dma_mask(pcidev, dma_mask);
4413        if (i) {
4414                CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4415                      "cs4281: probe() architecture does not support 32bit PCI busmaster DMA\n"));
4416                return i;
4417        }
4418        if (!(s = kmalloc(sizeof(struct cs4281_state), GFP_KERNEL))) {
4419                CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR
4420                      "cs4281: probe() no memory for state struct.\n"));
4421                return -1;
4422        }
4423        memset(s, 0, sizeof(struct cs4281_state));
4424        init_waitqueue_head(&s->dma_adc.wait);
4425        init_waitqueue_head(&s->dma_dac.wait);
4426        init_waitqueue_head(&s->open_wait);
4427        init_waitqueue_head(&s->open_wait_adc);
4428        init_waitqueue_head(&s->open_wait_dac);
4429        init_waitqueue_head(&s->midi.iwait);
4430        init_waitqueue_head(&s->midi.owait);
4431        init_MUTEX(&s->open_sem);
4432        init_MUTEX(&s->open_sem_adc);
4433        init_MUTEX(&s->open_sem_dac);
4434        spin_lock_init(&s->lock);
4435        s->pBA0phys = pci_resource_start(pcidev, 0);
4436        s->pBA1phys = pci_resource_start(pcidev, 1);
4437
4438        /* Convert phys to linear. */
4439        s->pBA0 = ioremap_nocache(s->pBA0phys, 4096);
4440        if (!s->pBA0) {
4441                CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4442                         "cs4281: BA0 I/O mapping failed. Skipping part.\n"));
4443                goto err_free;
4444        }
4445        s->pBA1 = ioremap_nocache(s->pBA1phys, 65536);
4446        if (!s->pBA1) {
4447                CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4448                         "cs4281: BA1 I/O mapping failed. Skipping part.\n"));
4449                goto err_unmap;
4450        }
4451
4452        temp1 = readl(s->pBA0 + BA0_PCICFG00);
4453        temp2 = readl(s->pBA0 + BA0_PCICFG04);
4454
4455        CS_DBGOUT(CS_INIT, 2,
4456                  printk(KERN_INFO
4457                         "cs4281: probe() BA0=0x%.8x BA1=0x%.8x pBA0=0x%.8x pBA1=0x%.8x \n",
4458                         (unsigned) temp1, (unsigned) temp2,
4459                         (unsigned) s->pBA0, (unsigned) s->pBA1));
4460
4461        CS_DBGOUT(CS_INIT, 2,
4462                  printk(KERN_INFO
4463                         "cs4281: probe() pBA0phys=0x%.8x pBA1phys=0x%.8x\n",
4464                         (unsigned) s->pBA0phys, (unsigned) s->pBA1phys));
4465
4466#ifndef NOT_CS4281_PM
4467        s->pm.flags = CS4281_PM_IDLE;
4468#endif
4469        temp1 = cs4281_hw_init(s);
4470        if (temp1) {
4471                CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk(KERN_ERR
4472                         "cs4281: cs4281_hw_init() failed. Skipping part.\n"));
4473                goto err_irq;
4474        }
4475        s->magic = CS4281_MAGIC;
4476        s->pcidev = pcidev;
4477        s->irq = pcidev->irq;
4478        if (request_irq
4479            (s->irq, cs4281_interrupt, SA_SHIRQ, "Crystal CS4281", s)) {
4480                CS_DBGOUT(CS_INIT | CS_ERROR, 1,
4481                          printk(KERN_ERR "cs4281: irq %u in use\n", s->irq));
4482                goto err_irq;
4483        }
4484        if ((s->dev_audio = register_sound_dsp(&cs4281_audio_fops, -1)) <
4485            0) {
4486                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4487                         "cs4281: probe() register_sound_dsp() failed.\n"));
4488                goto err_dev1;
4489        }
4490        if ((s->dev_mixer = register_sound_mixer(&cs4281_mixer_fops, -1)) <
4491            0) {
4492                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4493                         "cs4281: probe() register_sound_mixer() failed.\n"));
4494                goto err_dev2;
4495        }
4496        if ((s->dev_midi = register_sound_midi(&cs4281_midi_fops, -1)) < 0) {
4497                CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR
4498                         "cs4281: probe() register_sound_midi() failed.\n"));
4499                goto err_dev3;
4500        }
4501#ifndef NOT_CS4281_PM
4502        cs4281_InitPM(s);
4503        pmdev = cs_pm_register(PM_PCI_DEV, PM_PCI_ID(pcidev), cs4281_pm_callback);
4504        if (pmdev)
4505        {
4506                CS_DBGOUT(CS_INIT | CS_PM, 4, printk(KERN_INFO
4507                         "cs4281: probe() pm_register() succeeded (0x%x).\n",
4508                                (unsigned)pmdev));
4509                pmdev->data = s;
4510        }
4511        else
4512        {
4513                CS_DBGOUT(CS_INIT | CS_PM | CS_ERROR, 0, printk(KERN_INFO
4514                         "cs4281: probe() pm_register() failed (0x%x).\n",
4515                                (unsigned)pmdev));
4516                s->pm.flags |= CS4281_PM_NOT_REGISTERED;
4517        }
4518#endif
4519
4520        pci_set_master(pcidev); // enable bus mastering 
4521        pci_read_config_word(pcidev, PCI_SUBSYSTEM_VENDOR_ID, &s->ss_vendor);
4522        pci_read_config_word(pcidev, PCI_SUBSYSTEM_ID, &s->ss_id);
4523        printk(KERN_INFO "cs4281: Subsystem vendor/id (%04X:%04X) IRQ %d\n",
4524                s->ss_vendor, s->ss_id, s->irq);
4525        
4526        if(!recsrc_invalid)
4527                val = cs4281_setup_record_src(s);
4528        else
4529                val = SOUND_MASK_MIC;
4530
4531        fs = get_fs();
4532        set_fs(KERNEL_DS);
4533        mixer_ioctl(s, SOUND_MIXER_WRITE_RECSRC, (unsigned long) &val);
4534        for (i = 0; i < sizeof(initvol) / sizeof(initvol[0]); i++) {
4535                val = initvol[i].vol;
4536                mixer_ioctl(s, initvol[i].mixch, (unsigned long) &val);
4537        }
4538        val = 1;                // enable mic preamp 
4539        mixer_ioctl(s, SOUND_MIXER_PRIVATE1, (unsigned long) &val);
4540        set_fs(fs);
4541
4542        pci_set_drvdata(pcidev, s);
4543        list_add(&s->list, &cs4281_devs);
4544        CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4545                "cs4281: probe()- device allocated successfully\n"));
4546        return 0;
4547
4548      err_dev3:
4549        unregister_sound_mixer(s->dev_mixer);
4550      err_dev2:
4551        unregister_sound_dsp(s->dev_audio);
4552      err_dev1:
4553        free_irq(s->irq, s);
4554      err_irq:
4555        iounmap(s->pBA1);
4556      err_unmap:
4557        iounmap(s->pBA0);
4558      err_free:
4559        kfree(s);
4560
4561        CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_INFO
4562                "cs4281: probe()- no device allocated\n"));
4563        return -ENODEV;
4564} // probe_cs4281
4565
4566
4567// --------------------------------------------------------------------- 
4568
4569static void __devinit cs4281_remove(struct pci_dev *pci_dev)
4570{
4571        struct cs4281_state *s = pci_get_drvdata(pci_dev);
4572        // stop DMA controller 
4573        synchronize_irq();
4574        free_irq(s->irq, s);
4575        unregister_sound_dsp(s->dev_audio);
4576        unregister_sound_mixer(s->dev_mixer);
4577        unregister_sound_midi(s->dev_midi);
4578        iounmap(s->pBA1);
4579        iounmap(s->pBA0);
4580        pci_set_drvdata(pci_dev, s);
4581        list_del(&s->list);
4582        kfree(s);
4583        CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4584                 "cs4281: cs4281_remove()-: remove successful\n"));
4585}
4586
4587static struct pci_device_id cs4281_pci_tbl[] __devinitdata = {
4588        {PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CRYSTAL_CS4281,
4589         PCI_ANY_ID, PCI_ANY_ID, 0, 0},
4590        {0,}
4591};
4592
4593MODULE_DEVICE_TABLE(pci, cs4281_pci_tbl);
4594
4595struct pci_driver cs4281_pci_driver = {
4596        name:"cs4281",
4597        id_table:cs4281_pci_tbl,
4598        probe:cs4281_probe,
4599        remove:cs4281_remove,
4600        suspend:CS4281_SUSPEND_TBL,
4601        resume:CS4281_RESUME_TBL,
4602};
4603
4604int __init cs4281_init_module(void)
4605{
4606        int rtn = 0;
4607        CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO 
4608                "cs4281: cs4281_init_module()+ \n"));
4609        if (!pci_present()) {   /* No PCI bus in this machine! */
4610                CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO
4611                        "cs4281: cs4281_init_module()- no pci bus found\n"));
4612                return -ENODEV;
4613        }
4614        printk(KERN_INFO "cs4281: version v%d.%02d.%d time " __TIME__ " "
4615               __DATE__ "\n", CS4281_MAJOR_VERSION, CS4281_MINOR_VERSION,
4616               CS4281_ARCH);
4617        rtn = pci_module_init(&cs4281_pci_driver);
4618
4619        if(rtn == -ENODEV)
4620        {
4621                CS_DBGOUT(CS_ERROR | CS_INIT, 1, printk( 
4622                        "cs4281: Unable to locate any cs4281 device with valid IDs 0x%x-0x%x\n",
4623                                PCI_VENDOR_ID_CIRRUS, PCI_DEVICE_ID_CRYSTAL_CS4281));
4624        }
4625        CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4626                  printk(KERN_INFO "cs4281: cs4281_init_module()- (%d)\n",rtn));
4627        return rtn;
4628}
4629
4630void __exit cs4281_cleanup_module(void)
4631{
4632        pci_unregister_driver(&cs4281_pci_driver);
4633#ifndef NOT_CS4281_PM
4634        cs_pm_unregister_all(cs4281_pm_callback);
4635#endif
4636        CS_DBGOUT(CS_INIT | CS_FUNCTION, 2,
4637                  printk(KERN_INFO "cs4281: cleanup_cs4281() finished\n"));
4638}
4639// --------------------------------------------------------------------- 
4640
4641MODULE_AUTHOR("gw boynton, pcaudio@crystal.cirrus.com");
4642MODULE_DESCRIPTION("Cirrus Logic CS4281 Driver");
4643MODULE_LICENSE("GPL");
4644
4645// --------------------------------------------------------------------- 
4646
4647module_init(cs4281_init_module);
4648module_exit(cs4281_cleanup_module);
4649
4650#ifndef MODULE
4651int __init init_cs4281(void)
4652{
4653        return cs4281_init_module();
4654}
4655#endif
4656#include "cs4281pm-24.c"
4657