| altera-fpga2sdram-bridge.txt | 456 | 2019-12-13 07:49:56 | |
| altera-freeze-bridge.txt | 800 | 2019-12-13 07:49:56 | |
| altera-hps2fpga-bridge.txt | 1150 | 2019-12-13 07:49:56 | |
| altera-passive-serial.txt | 988 | 2021-08-29 15:04:50 -0700 | |
| altera-pr-ip.txt | 276 | 2021-08-29 15:04:50 -0700 | |
| altera-socfpga-a10-fpga-mgr.txt | 629 | 2021-08-29 15:04:50 -0700 | |
| altera-socfpga-fpga-mgr.txt | 533 | 2021-08-29 15:04:50 -0700 | |
| fpga-region.txt | 17707 | 2019-12-13 07:49:56 | |
| intel-stratix10-soc-fpga-mgr.txt | 333 | 2019-12-13 07:49:56 | |
| lattice-ice40-fpga-mgr.txt | 729 | 2021-08-29 15:04:50 -0700 | |
| lattice-machxo2-spi.txt | 656 | 2021-08-29 15:04:50 -0700 | |
| xilinx-pr-decoupler.txt | 1272 | 2019-12-13 07:49:56 | |
| xilinx-slave-serial.txt | 1270 | 2019-12-13 07:49:56 | |
| xilinx-zynq-fpga-mgr.txt | 560 | 2019-12-13 07:49:56 | |
| xlnx,zynqmp-pcap-fpga.txt | 641 | 2021-08-29 15:04:50 -0700 |