linux/sound/soc/codecs/wcd938x.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2// Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
   3
   4#include <linux/module.h>
   5#include <linux/slab.h>
   6#include <linux/platform_device.h>
   7#include <linux/device.h>
   8#include <linux/delay.h>
   9#include <linux/kernel.h>
  10#include <linux/pm_runtime.h>
  11#include <linux/component.h>
  12#include <sound/tlv.h>
  13#include <linux/of_gpio.h>
  14#include <linux/of.h>
  15#include <sound/jack.h>
  16#include <sound/pcm.h>
  17#include <sound/pcm_params.h>
  18#include <linux/regmap.h>
  19#include <sound/soc.h>
  20#include <sound/soc-dapm.h>
  21#include <linux/regulator/consumer.h>
  22
  23#include "wcd-clsh-v2.h"
  24#include "wcd938x.h"
  25
  26#define WCD938X_MAX_MICBIAS             (4)
  27#define WCD938X_MAX_SUPPLY              (4)
  28#define WCD938X_MBHC_MAX_BUTTONS        (8)
  29#define TX_ADC_MAX                      (4)
  30#define WCD938X_TX_MAX_SWR_PORTS        (5)
  31
  32#define WCD938X_RATES_MASK (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\
  33                            SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\
  34                            SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000)
  35/* Fractional Rates */
  36#define WCD938X_FRAC_RATES_MASK (SNDRV_PCM_RATE_44100 | SNDRV_PCM_RATE_88200 |\
  37                                 SNDRV_PCM_RATE_176400)
  38#define WCD938X_FORMATS_S16_S24_LE (SNDRV_PCM_FMTBIT_S16_LE | \
  39                                    SNDRV_PCM_FMTBIT_S24_LE)
  40/* Convert from vout ctl to micbias voltage in mV */
  41#define  WCD_VOUT_CTL_TO_MICB(v)        (1000 + v * 50)
  42#define SWR_CLK_RATE_0P6MHZ             (600000)
  43#define SWR_CLK_RATE_1P2MHZ             (1200000)
  44#define SWR_CLK_RATE_2P4MHZ             (2400000)
  45#define SWR_CLK_RATE_4P8MHZ             (4800000)
  46#define SWR_CLK_RATE_9P6MHZ             (9600000)
  47#define SWR_CLK_RATE_11P2896MHZ         (1128960)
  48
  49#define WCD938X_DRV_NAME "wcd938x_codec"
  50#define WCD938X_VERSION_1_0             (1)
  51#define EAR_RX_PATH_AUX                 (1)
  52
  53#define ADC_MODE_VAL_HIFI               0x01
  54#define ADC_MODE_VAL_LO_HIF             0x02
  55#define ADC_MODE_VAL_NORMAL             0x03
  56#define ADC_MODE_VAL_LP                 0x05
  57#define ADC_MODE_VAL_ULP1               0x09
  58#define ADC_MODE_VAL_ULP2               0x0B
  59
  60/* Z value defined in milliohm */
  61#define WCD938X_ZDET_VAL_32             (32000)
  62#define WCD938X_ZDET_VAL_400            (400000)
  63#define WCD938X_ZDET_VAL_1200           (1200000)
  64#define WCD938X_ZDET_VAL_100K           (100000000)
  65/* Z floating defined in ohms */
  66#define WCD938X_ZDET_FLOATING_IMPEDANCE (0x0FFFFFFE)
  67#define WCD938X_ZDET_NUM_MEASUREMENTS   (900)
  68#define WCD938X_MBHC_GET_C1(c)          ((c & 0xC000) >> 14)
  69#define WCD938X_MBHC_GET_X1(x)          (x & 0x3FFF)
  70/* Z value compared in milliOhm */
  71#define WCD938X_MBHC_IS_SECOND_RAMP_REQUIRED(z) ((z > 400000) || (z < 32000))
  72#define WCD938X_MBHC_ZDET_CONST         (86 * 16384)
  73#define WCD938X_MBHC_MOISTURE_RREF      R_24_KOHM
  74#define WCD_MBHC_HS_V_MAX           1600
  75
  76#define WCD938X_EAR_PA_GAIN_TLV(xname, reg, shift, max, invert, tlv_array) \
  77{       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
  78        .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
  79                 SNDRV_CTL_ELEM_ACCESS_READWRITE,\
  80        .tlv.p = (tlv_array), \
  81        .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
  82        .put = wcd938x_ear_pa_put_gain, \
  83        .private_value = SOC_SINGLE_VALUE(reg, shift, max, invert, 0) }
  84
  85enum {
  86        WCD9380 = 0,
  87        WCD9385 = 5,
  88};
  89
  90enum {
  91        TX_HDR12 = 0,
  92        TX_HDR34,
  93        TX_HDR_MAX,
  94};
  95
  96enum {
  97        WCD_RX1,
  98        WCD_RX2,
  99        WCD_RX3
 100};
 101
 102enum {
 103        /* INTR_CTRL_INT_MASK_0 */
 104        WCD938X_IRQ_MBHC_BUTTON_PRESS_DET = 0,
 105        WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET,
 106        WCD938X_IRQ_MBHC_ELECT_INS_REM_DET,
 107        WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET,
 108        WCD938X_IRQ_MBHC_SW_DET,
 109        WCD938X_IRQ_HPHR_OCP_INT,
 110        WCD938X_IRQ_HPHR_CNP_INT,
 111        WCD938X_IRQ_HPHL_OCP_INT,
 112
 113        /* INTR_CTRL_INT_MASK_1 */
 114        WCD938X_IRQ_HPHL_CNP_INT,
 115        WCD938X_IRQ_EAR_CNP_INT,
 116        WCD938X_IRQ_EAR_SCD_INT,
 117        WCD938X_IRQ_AUX_CNP_INT,
 118        WCD938X_IRQ_AUX_SCD_INT,
 119        WCD938X_IRQ_HPHL_PDM_WD_INT,
 120        WCD938X_IRQ_HPHR_PDM_WD_INT,
 121        WCD938X_IRQ_AUX_PDM_WD_INT,
 122
 123        /* INTR_CTRL_INT_MASK_2 */
 124        WCD938X_IRQ_LDORT_SCD_INT,
 125        WCD938X_IRQ_MBHC_MOISTURE_INT,
 126        WCD938X_IRQ_HPHL_SURGE_DET_INT,
 127        WCD938X_IRQ_HPHR_SURGE_DET_INT,
 128        WCD938X_NUM_IRQS,
 129};
 130
 131enum {
 132        WCD_ADC1 = 0,
 133        WCD_ADC2,
 134        WCD_ADC3,
 135        WCD_ADC4,
 136        ALLOW_BUCK_DISABLE,
 137        HPH_COMP_DELAY,
 138        HPH_PA_DELAY,
 139        AMIC2_BCS_ENABLE,
 140        WCD_SUPPLIES_LPM_MODE,
 141};
 142
 143enum {
 144        ADC_MODE_INVALID = 0,
 145        ADC_MODE_HIFI,
 146        ADC_MODE_LO_HIF,
 147        ADC_MODE_NORMAL,
 148        ADC_MODE_LP,
 149        ADC_MODE_ULP1,
 150        ADC_MODE_ULP2,
 151};
 152
 153enum {
 154        AIF1_PB = 0,
 155        AIF1_CAP,
 156        NUM_CODEC_DAIS,
 157};
 158
 159static u8 tx_mode_bit[] = {
 160        [ADC_MODE_INVALID] = 0x00,
 161        [ADC_MODE_HIFI] = 0x01,
 162        [ADC_MODE_LO_HIF] = 0x02,
 163        [ADC_MODE_NORMAL] = 0x04,
 164        [ADC_MODE_LP] = 0x08,
 165        [ADC_MODE_ULP1] = 0x10,
 166        [ADC_MODE_ULP2] = 0x20,
 167};
 168
 169struct wcd938x_priv {
 170        struct sdw_slave *tx_sdw_dev;
 171        struct wcd938x_sdw_priv *sdw_priv[NUM_CODEC_DAIS];
 172        struct device *txdev;
 173        struct device *rxdev;
 174        struct device_node *rxnode, *txnode;
 175        struct regmap *regmap;
 176        struct wcd_clsh_ctrl *clsh_info;
 177        struct irq_domain *virq;
 178        struct regmap_irq_chip *wcd_regmap_irq_chip;
 179        struct regmap_irq_chip_data *irq_chip;
 180        struct regulator_bulk_data supplies[WCD938X_MAX_SUPPLY];
 181        struct snd_soc_jack *jack;
 182        unsigned long status_mask;
 183        s32 micb_ref[WCD938X_MAX_MICBIAS];
 184        s32 pullup_ref[WCD938X_MAX_MICBIAS];
 185        u32 hph_mode;
 186        u32 tx_mode[TX_ADC_MAX];
 187        int flyback_cur_det_disable;
 188        int ear_rx_path;
 189        int variant;
 190        int reset_gpio;
 191        u32 micb1_mv;
 192        u32 micb2_mv;
 193        u32 micb3_mv;
 194        u32 micb4_mv;
 195        int hphr_pdm_wd_int;
 196        int hphl_pdm_wd_int;
 197        int aux_pdm_wd_int;
 198        bool comp1_enable;
 199        bool comp2_enable;
 200        bool ldoh;
 201        bool bcs_dis;
 202};
 203
 204enum {
 205        MIC_BIAS_1 = 1,
 206        MIC_BIAS_2,
 207        MIC_BIAS_3,
 208        MIC_BIAS_4
 209};
 210
 211enum {
 212        MICB_PULLUP_ENABLE,
 213        MICB_PULLUP_DISABLE,
 214        MICB_ENABLE,
 215        MICB_DISABLE,
 216};
 217
 218static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(ear_pa_gain, 600, -1800);
 219static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(line_gain, 600, -3000);
 220static const SNDRV_CTL_TLVD_DECLARE_DB_MINMAX(analog_gain, 0, 3000);
 221
 222static const struct reg_default wcd938x_defaults[] = {
 223        {WCD938X_ANA_PAGE_REGISTER,                            0x00},
 224        {WCD938X_ANA_BIAS,                                     0x00},
 225        {WCD938X_ANA_RX_SUPPLIES,                              0x00},
 226        {WCD938X_ANA_HPH,                                      0x0C},
 227        {WCD938X_ANA_EAR,                                      0x00},
 228        {WCD938X_ANA_EAR_COMPANDER_CTL,                        0x02},
 229        {WCD938X_ANA_TX_CH1,                                   0x20},
 230        {WCD938X_ANA_TX_CH2,                                   0x00},
 231        {WCD938X_ANA_TX_CH3,                                   0x20},
 232        {WCD938X_ANA_TX_CH4,                                   0x00},
 233        {WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC,                 0x00},
 234        {WCD938X_ANA_MICB3_DSP_EN_LOGIC,                       0x00},
 235        {WCD938X_ANA_MBHC_MECH,                                0x39},
 236        {WCD938X_ANA_MBHC_ELECT,                               0x08},
 237        {WCD938X_ANA_MBHC_ZDET,                                0x00},
 238        {WCD938X_ANA_MBHC_RESULT_1,                            0x00},
 239        {WCD938X_ANA_MBHC_RESULT_2,                            0x00},
 240        {WCD938X_ANA_MBHC_RESULT_3,                            0x00},
 241        {WCD938X_ANA_MBHC_BTN0,                                0x00},
 242        {WCD938X_ANA_MBHC_BTN1,                                0x10},
 243        {WCD938X_ANA_MBHC_BTN2,                                0x20},
 244        {WCD938X_ANA_MBHC_BTN3,                                0x30},
 245        {WCD938X_ANA_MBHC_BTN4,                                0x40},
 246        {WCD938X_ANA_MBHC_BTN5,                                0x50},
 247        {WCD938X_ANA_MBHC_BTN6,                                0x60},
 248        {WCD938X_ANA_MBHC_BTN7,                                0x70},
 249        {WCD938X_ANA_MICB1,                                    0x10},
 250        {WCD938X_ANA_MICB2,                                    0x10},
 251        {WCD938X_ANA_MICB2_RAMP,                               0x00},
 252        {WCD938X_ANA_MICB3,                                    0x10},
 253        {WCD938X_ANA_MICB4,                                    0x10},
 254        {WCD938X_BIAS_CTL,                                     0x2A},
 255        {WCD938X_BIAS_VBG_FINE_ADJ,                            0x55},
 256        {WCD938X_LDOL_VDDCX_ADJUST,                            0x01},
 257        {WCD938X_LDOL_DISABLE_LDOL,                            0x00},
 258        {WCD938X_MBHC_CTL_CLK,                                 0x00},
 259        {WCD938X_MBHC_CTL_ANA,                                 0x00},
 260        {WCD938X_MBHC_CTL_SPARE_1,                             0x00},
 261        {WCD938X_MBHC_CTL_SPARE_2,                             0x00},
 262        {WCD938X_MBHC_CTL_BCS,                                 0x00},
 263        {WCD938X_MBHC_MOISTURE_DET_FSM_STATUS,                 0x00},
 264        {WCD938X_MBHC_TEST_CTL,                                0x00},
 265        {WCD938X_LDOH_MODE,                                    0x2B},
 266        {WCD938X_LDOH_BIAS,                                    0x68},
 267        {WCD938X_LDOH_STB_LOADS,                               0x00},
 268        {WCD938X_LDOH_SLOWRAMP,                                0x50},
 269        {WCD938X_MICB1_TEST_CTL_1,                             0x1A},
 270        {WCD938X_MICB1_TEST_CTL_2,                             0x00},
 271        {WCD938X_MICB1_TEST_CTL_3,                             0xA4},
 272        {WCD938X_MICB2_TEST_CTL_1,                             0x1A},
 273        {WCD938X_MICB2_TEST_CTL_2,                             0x00},
 274        {WCD938X_MICB2_TEST_CTL_3,                             0x24},
 275        {WCD938X_MICB3_TEST_CTL_1,                             0x1A},
 276        {WCD938X_MICB3_TEST_CTL_2,                             0x00},
 277        {WCD938X_MICB3_TEST_CTL_3,                             0xA4},
 278        {WCD938X_MICB4_TEST_CTL_1,                             0x1A},
 279        {WCD938X_MICB4_TEST_CTL_2,                             0x00},
 280        {WCD938X_MICB4_TEST_CTL_3,                             0xA4},
 281        {WCD938X_TX_COM_ADC_VCM,                               0x39},
 282        {WCD938X_TX_COM_BIAS_ATEST,                            0xE0},
 283        {WCD938X_TX_COM_SPARE1,                                0x00},
 284        {WCD938X_TX_COM_SPARE2,                                0x00},
 285        {WCD938X_TX_COM_TXFE_DIV_CTL,                          0x22},
 286        {WCD938X_TX_COM_TXFE_DIV_START,                        0x00},
 287        {WCD938X_TX_COM_SPARE3,                                0x00},
 288        {WCD938X_TX_COM_SPARE4,                                0x00},
 289        {WCD938X_TX_1_2_TEST_EN,                               0xCC},
 290        {WCD938X_TX_1_2_ADC_IB,                                0xE9},
 291        {WCD938X_TX_1_2_ATEST_REFCTL,                          0x0A},
 292        {WCD938X_TX_1_2_TEST_CTL,                              0x38},
 293        {WCD938X_TX_1_2_TEST_BLK_EN1,                          0xFF},
 294        {WCD938X_TX_1_2_TXFE1_CLKDIV,                          0x00},
 295        {WCD938X_TX_1_2_SAR2_ERR,                              0x00},
 296        {WCD938X_TX_1_2_SAR1_ERR,                              0x00},
 297        {WCD938X_TX_3_4_TEST_EN,                               0xCC},
 298        {WCD938X_TX_3_4_ADC_IB,                                0xE9},
 299        {WCD938X_TX_3_4_ATEST_REFCTL,                          0x0A},
 300        {WCD938X_TX_3_4_TEST_CTL,                              0x38},
 301        {WCD938X_TX_3_4_TEST_BLK_EN3,                          0xFF},
 302        {WCD938X_TX_3_4_TXFE3_CLKDIV,                          0x00},
 303        {WCD938X_TX_3_4_SAR4_ERR,                              0x00},
 304        {WCD938X_TX_3_4_SAR3_ERR,                              0x00},
 305        {WCD938X_TX_3_4_TEST_BLK_EN2,                          0xFB},
 306        {WCD938X_TX_3_4_TXFE2_CLKDIV,                          0x00},
 307        {WCD938X_TX_3_4_SPARE1,                                0x00},
 308        {WCD938X_TX_3_4_TEST_BLK_EN4,                          0xFB},
 309        {WCD938X_TX_3_4_TXFE4_CLKDIV,                          0x00},
 310        {WCD938X_TX_3_4_SPARE2,                                0x00},
 311        {WCD938X_CLASSH_MODE_1,                                0x40},
 312        {WCD938X_CLASSH_MODE_2,                                0x3A},
 313        {WCD938X_CLASSH_MODE_3,                                0x00},
 314        {WCD938X_CLASSH_CTRL_VCL_1,                            0x70},
 315        {WCD938X_CLASSH_CTRL_VCL_2,                            0x82},
 316        {WCD938X_CLASSH_CTRL_CCL_1,                            0x31},
 317        {WCD938X_CLASSH_CTRL_CCL_2,                            0x80},
 318        {WCD938X_CLASSH_CTRL_CCL_3,                            0x80},
 319        {WCD938X_CLASSH_CTRL_CCL_4,                            0x51},
 320        {WCD938X_CLASSH_CTRL_CCL_5,                            0x00},
 321        {WCD938X_CLASSH_BUCK_TMUX_A_D,                         0x00},
 322        {WCD938X_CLASSH_BUCK_SW_DRV_CNTL,                      0x77},
 323        {WCD938X_CLASSH_SPARE,                                 0x00},
 324        {WCD938X_FLYBACK_EN,                                   0x4E},
 325        {WCD938X_FLYBACK_VNEG_CTRL_1,                          0x0B},
 326        {WCD938X_FLYBACK_VNEG_CTRL_2,                          0x45},
 327        {WCD938X_FLYBACK_VNEG_CTRL_3,                          0x74},
 328        {WCD938X_FLYBACK_VNEG_CTRL_4,                          0x7F},
 329        {WCD938X_FLYBACK_VNEG_CTRL_5,                          0x83},
 330        {WCD938X_FLYBACK_VNEG_CTRL_6,                          0x98},
 331        {WCD938X_FLYBACK_VNEG_CTRL_7,                          0xA9},
 332        {WCD938X_FLYBACK_VNEG_CTRL_8,                          0x68},
 333        {WCD938X_FLYBACK_VNEG_CTRL_9,                          0x64},
 334        {WCD938X_FLYBACK_VNEGDAC_CTRL_1,                       0xED},
 335        {WCD938X_FLYBACK_VNEGDAC_CTRL_2,                       0xF0},
 336        {WCD938X_FLYBACK_VNEGDAC_CTRL_3,                       0xA6},
 337        {WCD938X_FLYBACK_CTRL_1,                               0x65},
 338        {WCD938X_FLYBACK_TEST_CTL,                             0x00},
 339        {WCD938X_RX_AUX_SW_CTL,                                0x00},
 340        {WCD938X_RX_PA_AUX_IN_CONN,                            0x01},
 341        {WCD938X_RX_TIMER_DIV,                                 0x32},
 342        {WCD938X_RX_OCP_CTL,                                   0x1F},
 343        {WCD938X_RX_OCP_COUNT,                                 0x77},
 344        {WCD938X_RX_BIAS_EAR_DAC,                              0xA0},
 345        {WCD938X_RX_BIAS_EAR_AMP,                              0xAA},
 346        {WCD938X_RX_BIAS_HPH_LDO,                              0xA9},
 347        {WCD938X_RX_BIAS_HPH_PA,                               0xAA},
 348        {WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2,                    0x8A},
 349        {WCD938X_RX_BIAS_HPH_RDAC_LDO,                         0x88},
 350        {WCD938X_RX_BIAS_HPH_CNP1,                             0x82},
 351        {WCD938X_RX_BIAS_HPH_LOWPOWER,                         0x82},
 352        {WCD938X_RX_BIAS_AUX_DAC,                              0xA0},
 353        {WCD938X_RX_BIAS_AUX_AMP,                              0xAA},
 354        {WCD938X_RX_BIAS_VNEGDAC_BLEEDER,                      0x50},
 355        {WCD938X_RX_BIAS_MISC,                                 0x00},
 356        {WCD938X_RX_BIAS_BUCK_RST,                             0x08},
 357        {WCD938X_RX_BIAS_BUCK_VREF_ERRAMP,                     0x44},
 358        {WCD938X_RX_BIAS_FLYB_ERRAMP,                          0x40},
 359        {WCD938X_RX_BIAS_FLYB_BUFF,                            0xAA},
 360        {WCD938X_RX_BIAS_FLYB_MID_RST,                         0x14},
 361        {WCD938X_HPH_L_STATUS,                                 0x04},
 362        {WCD938X_HPH_R_STATUS,                                 0x04},
 363        {WCD938X_HPH_CNP_EN,                                   0x80},
 364        {WCD938X_HPH_CNP_WG_CTL,                               0x9A},
 365        {WCD938X_HPH_CNP_WG_TIME,                              0x14},
 366        {WCD938X_HPH_OCP_CTL,                                  0x28},
 367        {WCD938X_HPH_AUTO_CHOP,                                0x16},
 368        {WCD938X_HPH_CHOP_CTL,                                 0x83},
 369        {WCD938X_HPH_PA_CTL1,                                  0x46},
 370        {WCD938X_HPH_PA_CTL2,                                  0x50},
 371        {WCD938X_HPH_L_EN,                                     0x80},
 372        {WCD938X_HPH_L_TEST,                                   0xE0},
 373        {WCD938X_HPH_L_ATEST,                                  0x50},
 374        {WCD938X_HPH_R_EN,                                     0x80},
 375        {WCD938X_HPH_R_TEST,                                   0xE0},
 376        {WCD938X_HPH_R_ATEST,                                  0x54},
 377        {WCD938X_HPH_RDAC_CLK_CTL1,                            0x99},
 378        {WCD938X_HPH_RDAC_CLK_CTL2,                            0x9B},
 379        {WCD938X_HPH_RDAC_LDO_CTL,                             0x33},
 380        {WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL,                     0x00},
 381        {WCD938X_HPH_REFBUFF_UHQA_CTL,                         0x68},
 382        {WCD938X_HPH_REFBUFF_LP_CTL,                           0x0E},
 383        {WCD938X_HPH_L_DAC_CTL,                                0x20},
 384        {WCD938X_HPH_R_DAC_CTL,                                0x20},
 385        {WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL,               0x55},
 386        {WCD938X_HPH_SURGE_HPHLR_SURGE_EN,                     0x19},
 387        {WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1,                  0xA0},
 388        {WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS,                 0x00},
 389        {WCD938X_EAR_EAR_EN_REG,                               0x22},
 390        {WCD938X_EAR_EAR_PA_CON,                               0x44},
 391        {WCD938X_EAR_EAR_SP_CON,                               0xDB},
 392        {WCD938X_EAR_EAR_DAC_CON,                              0x80},
 393        {WCD938X_EAR_EAR_CNP_FSM_CON,                          0xB2},
 394        {WCD938X_EAR_TEST_CTL,                                 0x00},
 395        {WCD938X_EAR_STATUS_REG_1,                             0x00},
 396        {WCD938X_EAR_STATUS_REG_2,                             0x08},
 397        {WCD938X_ANA_NEW_PAGE_REGISTER,                        0x00},
 398        {WCD938X_HPH_NEW_ANA_HPH2,                             0x00},
 399        {WCD938X_HPH_NEW_ANA_HPH3,                             0x00},
 400        {WCD938X_SLEEP_CTL,                                    0x16},
 401        {WCD938X_SLEEP_WATCHDOG_CTL,                           0x00},
 402        {WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL,                 0x00},
 403        {WCD938X_MBHC_NEW_CTL_1,                               0x02},
 404        {WCD938X_MBHC_NEW_CTL_2,                               0x05},
 405        {WCD938X_MBHC_NEW_PLUG_DETECT_CTL,                     0xE9},
 406        {WCD938X_MBHC_NEW_ZDET_ANA_CTL,                        0x0F},
 407        {WCD938X_MBHC_NEW_ZDET_RAMP_CTL,                       0x00},
 408        {WCD938X_MBHC_NEW_FSM_STATUS,                          0x00},
 409        {WCD938X_MBHC_NEW_ADC_RESULT,                          0x00},
 410        {WCD938X_TX_NEW_AMIC_MUX_CFG,                          0x00},
 411        {WCD938X_AUX_AUXPA,                                    0x00},
 412        {WCD938X_LDORXTX_MODE,                                 0x0C},
 413        {WCD938X_LDORXTX_CONFIG,                               0x10},
 414        {WCD938X_DIE_CRACK_DIE_CRK_DET_EN,                     0x00},
 415        {WCD938X_DIE_CRACK_DIE_CRK_DET_OUT,                    0x00},
 416        {WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,                    0x40},
 417        {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,                   0x81},
 418        {WCD938X_HPH_NEW_INT_RDAC_VREF_CTL,                    0x10},
 419        {WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL,                0x00},
 420        {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,                   0x81},
 421        {WCD938X_HPH_NEW_INT_PA_MISC1,                         0x22},
 422        {WCD938X_HPH_NEW_INT_PA_MISC2,                         0x00},
 423        {WCD938X_HPH_NEW_INT_PA_RDAC_MISC,                     0x00},
 424        {WCD938X_HPH_NEW_INT_HPH_TIMER1,                       0xFE},
 425        {WCD938X_HPH_NEW_INT_HPH_TIMER2,                       0x02},
 426        {WCD938X_HPH_NEW_INT_HPH_TIMER3,                       0x4E},
 427        {WCD938X_HPH_NEW_INT_HPH_TIMER4,                       0x54},
 428        {WCD938X_HPH_NEW_INT_PA_RDAC_MISC2,                    0x00},
 429        {WCD938X_HPH_NEW_INT_PA_RDAC_MISC3,                    0x00},
 430        {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,               0x90},
 431        {WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,               0x90},
 432        {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI,              0x62},
 433        {WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP,                 0x01},
 434        {WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP,                   0x11},
 435        {WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL,            0x57},
 436        {WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL,       0x01},
 437        {WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT,                0x00},
 438        {WCD938X_MBHC_NEW_INT_SPARE_2,                         0x00},
 439        {WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON,                  0xA8},
 440        {WCD938X_EAR_INT_NEW_CNP_VCM_CON1,                     0x42},
 441        {WCD938X_EAR_INT_NEW_CNP_VCM_CON2,                     0x22},
 442        {WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS,                 0x00},
 443        {WCD938X_AUX_INT_EN_REG,                               0x00},
 444        {WCD938X_AUX_INT_PA_CTRL,                              0x06},
 445        {WCD938X_AUX_INT_SP_CTRL,                              0xD2},
 446        {WCD938X_AUX_INT_DAC_CTRL,                             0x80},
 447        {WCD938X_AUX_INT_CLK_CTRL,                             0x50},
 448        {WCD938X_AUX_INT_TEST_CTRL,                            0x00},
 449        {WCD938X_AUX_INT_STATUS_REG,                           0x00},
 450        {WCD938X_AUX_INT_MISC,                                 0x00},
 451        {WCD938X_LDORXTX_INT_BIAS,                             0x6E},
 452        {WCD938X_LDORXTX_INT_STB_LOADS_DTEST,                  0x50},
 453        {WCD938X_LDORXTX_INT_TEST0,                            0x1C},
 454        {WCD938X_LDORXTX_INT_STARTUP_TIMER,                    0xFF},
 455        {WCD938X_LDORXTX_INT_TEST1,                            0x1F},
 456        {WCD938X_LDORXTX_INT_STATUS,                           0x00},
 457        {WCD938X_SLEEP_INT_WATCHDOG_CTL_1,                     0x0A},
 458        {WCD938X_SLEEP_INT_WATCHDOG_CTL_2,                     0x0A},
 459        {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1,               0x02},
 460        {WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2,               0x60},
 461        {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2,               0xFF},
 462        {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1,               0x7F},
 463        {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0,               0x3F},
 464        {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M,          0x1F},
 465        {WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M,          0x0F},
 466        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1,          0xD7},
 467        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0,            0xC8},
 468        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP,           0xC6},
 469        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1,      0xD5},
 470        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0,        0xCA},
 471        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,       0x05},
 472        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0,    0xA5},
 473        {WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,       0x13},
 474        {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1,             0x88},
 475        {WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP,            0x42},
 476        {WCD938X_TX_COM_NEW_INT_TXADC_INT_L2,                  0xFF},
 477        {WCD938X_TX_COM_NEW_INT_TXADC_INT_L1,                  0x64},
 478        {WCD938X_TX_COM_NEW_INT_TXADC_INT_L0,                  0x64},
 479        {WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP,                 0x77},
 480        {WCD938X_DIGITAL_PAGE_REGISTER,                        0x00},
 481        {WCD938X_DIGITAL_CHIP_ID0,                             0x00},
 482        {WCD938X_DIGITAL_CHIP_ID1,                             0x00},
 483        {WCD938X_DIGITAL_CHIP_ID2,                             0x0D},
 484        {WCD938X_DIGITAL_CHIP_ID3,                             0x01},
 485        {WCD938X_DIGITAL_SWR_TX_CLK_RATE,                      0x00},
 486        {WCD938X_DIGITAL_CDC_RST_CTL,                          0x03},
 487        {WCD938X_DIGITAL_TOP_CLK_CFG,                          0x00},
 488        {WCD938X_DIGITAL_CDC_ANA_CLK_CTL,                      0x00},
 489        {WCD938X_DIGITAL_CDC_DIG_CLK_CTL,                      0xF0},
 490        {WCD938X_DIGITAL_SWR_RST_EN,                           0x00},
 491        {WCD938X_DIGITAL_CDC_PATH_MODE,                        0x55},
 492        {WCD938X_DIGITAL_CDC_RX_RST,                           0x00},
 493        {WCD938X_DIGITAL_CDC_RX0_CTL,                          0xFC},
 494        {WCD938X_DIGITAL_CDC_RX1_CTL,                          0xFC},
 495        {WCD938X_DIGITAL_CDC_RX2_CTL,                          0xFC},
 496        {WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,                  0x00},
 497        {WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,                  0x00},
 498        {WCD938X_DIGITAL_CDC_COMP_CTL_0,                       0x00},
 499        {WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,                   0x1E},
 500        {WCD938X_DIGITAL_CDC_HPH_DSM_A1_0,                     0x00},
 501        {WCD938X_DIGITAL_CDC_HPH_DSM_A1_1,                     0x01},
 502        {WCD938X_DIGITAL_CDC_HPH_DSM_A2_0,                     0x63},
 503        {WCD938X_DIGITAL_CDC_HPH_DSM_A2_1,                     0x04},
 504        {WCD938X_DIGITAL_CDC_HPH_DSM_A3_0,                     0xAC},
 505        {WCD938X_DIGITAL_CDC_HPH_DSM_A3_1,                     0x04},
 506        {WCD938X_DIGITAL_CDC_HPH_DSM_A4_0,                     0x1A},
 507        {WCD938X_DIGITAL_CDC_HPH_DSM_A4_1,                     0x03},
 508        {WCD938X_DIGITAL_CDC_HPH_DSM_A5_0,                     0xBC},
 509        {WCD938X_DIGITAL_CDC_HPH_DSM_A5_1,                     0x02},
 510        {WCD938X_DIGITAL_CDC_HPH_DSM_A6_0,                     0xC7},
 511        {WCD938X_DIGITAL_CDC_HPH_DSM_A7_0,                     0xF8},
 512        {WCD938X_DIGITAL_CDC_HPH_DSM_C_0,                      0x47},
 513        {WCD938X_DIGITAL_CDC_HPH_DSM_C_1,                      0x43},
 514        {WCD938X_DIGITAL_CDC_HPH_DSM_C_2,                      0xB1},
 515        {WCD938X_DIGITAL_CDC_HPH_DSM_C_3,                      0x17},
 516        {WCD938X_DIGITAL_CDC_HPH_DSM_R1,                       0x4D},
 517        {WCD938X_DIGITAL_CDC_HPH_DSM_R2,                       0x29},
 518        {WCD938X_DIGITAL_CDC_HPH_DSM_R3,                       0x34},
 519        {WCD938X_DIGITAL_CDC_HPH_DSM_R4,                       0x59},
 520        {WCD938X_DIGITAL_CDC_HPH_DSM_R5,                       0x66},
 521        {WCD938X_DIGITAL_CDC_HPH_DSM_R6,                       0x87},
 522        {WCD938X_DIGITAL_CDC_HPH_DSM_R7,                       0x64},
 523        {WCD938X_DIGITAL_CDC_AUX_DSM_A1_0,                     0x00},
 524        {WCD938X_DIGITAL_CDC_AUX_DSM_A1_1,                     0x01},
 525        {WCD938X_DIGITAL_CDC_AUX_DSM_A2_0,                     0x96},
 526        {WCD938X_DIGITAL_CDC_AUX_DSM_A2_1,                     0x09},
 527        {WCD938X_DIGITAL_CDC_AUX_DSM_A3_0,                     0xAB},
 528        {WCD938X_DIGITAL_CDC_AUX_DSM_A3_1,                     0x05},
 529        {WCD938X_DIGITAL_CDC_AUX_DSM_A4_0,                     0x1C},
 530        {WCD938X_DIGITAL_CDC_AUX_DSM_A4_1,                     0x02},
 531        {WCD938X_DIGITAL_CDC_AUX_DSM_A5_0,                     0x17},
 532        {WCD938X_DIGITAL_CDC_AUX_DSM_A5_1,                     0x02},
 533        {WCD938X_DIGITAL_CDC_AUX_DSM_A6_0,                     0xAA},
 534        {WCD938X_DIGITAL_CDC_AUX_DSM_A7_0,                     0xE3},
 535        {WCD938X_DIGITAL_CDC_AUX_DSM_C_0,                      0x69},
 536        {WCD938X_DIGITAL_CDC_AUX_DSM_C_1,                      0x54},
 537        {WCD938X_DIGITAL_CDC_AUX_DSM_C_2,                      0x02},
 538        {WCD938X_DIGITAL_CDC_AUX_DSM_C_3,                      0x15},
 539        {WCD938X_DIGITAL_CDC_AUX_DSM_R1,                       0xA4},
 540        {WCD938X_DIGITAL_CDC_AUX_DSM_R2,                       0xB5},
 541        {WCD938X_DIGITAL_CDC_AUX_DSM_R3,                       0x86},
 542        {WCD938X_DIGITAL_CDC_AUX_DSM_R4,                       0x85},
 543        {WCD938X_DIGITAL_CDC_AUX_DSM_R5,                       0xAA},
 544        {WCD938X_DIGITAL_CDC_AUX_DSM_R6,                       0xE2},
 545        {WCD938X_DIGITAL_CDC_AUX_DSM_R7,                       0x62},
 546        {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0,                    0x55},
 547        {WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1,                    0xA9},
 548        {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0,                   0x3D},
 549        {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1,                   0x2E},
 550        {WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2,                   0x01},
 551        {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0,                   0x00},
 552        {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1,                   0xFC},
 553        {WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2,                   0x01},
 554        {WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,                     0x00},
 555        {WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,                     0x00},
 556        {WCD938X_DIGITAL_CDC_EAR_PATH_CTL,                     0x00},
 557        {WCD938X_DIGITAL_CDC_SWR_CLH,                          0x00},
 558        {WCD938X_DIGITAL_SWR_CLH_BYP,                          0x00},
 559        {WCD938X_DIGITAL_CDC_TX0_CTL,                          0x68},
 560        {WCD938X_DIGITAL_CDC_TX1_CTL,                          0x68},
 561        {WCD938X_DIGITAL_CDC_TX2_CTL,                          0x68},
 562        {WCD938X_DIGITAL_CDC_TX_RST,                           0x00},
 563        {WCD938X_DIGITAL_CDC_REQ_CTL,                          0x01},
 564        {WCD938X_DIGITAL_CDC_RST,                              0x00},
 565        {WCD938X_DIGITAL_CDC_AMIC_CTL,                         0x0F},
 566        {WCD938X_DIGITAL_CDC_DMIC_CTL,                         0x04},
 567        {WCD938X_DIGITAL_CDC_DMIC1_CTL,                        0x01},
 568        {WCD938X_DIGITAL_CDC_DMIC2_CTL,                        0x01},
 569        {WCD938X_DIGITAL_CDC_DMIC3_CTL,                        0x01},
 570        {WCD938X_DIGITAL_CDC_DMIC4_CTL,                        0x01},
 571        {WCD938X_DIGITAL_EFUSE_PRG_CTL,                        0x00},
 572        {WCD938X_DIGITAL_EFUSE_CTL,                            0x2B},
 573        {WCD938X_DIGITAL_CDC_DMIC_RATE_1_2,                    0x11},
 574        {WCD938X_DIGITAL_CDC_DMIC_RATE_3_4,                    0x11},
 575        {WCD938X_DIGITAL_PDM_WD_CTL0,                          0x00},
 576        {WCD938X_DIGITAL_PDM_WD_CTL1,                          0x00},
 577        {WCD938X_DIGITAL_PDM_WD_CTL2,                          0x00},
 578        {WCD938X_DIGITAL_INTR_MODE,                            0x00},
 579        {WCD938X_DIGITAL_INTR_MASK_0,                          0xFF},
 580        {WCD938X_DIGITAL_INTR_MASK_1,                          0xFF},
 581        {WCD938X_DIGITAL_INTR_MASK_2,                          0x3F},
 582        {WCD938X_DIGITAL_INTR_STATUS_0,                        0x00},
 583        {WCD938X_DIGITAL_INTR_STATUS_1,                        0x00},
 584        {WCD938X_DIGITAL_INTR_STATUS_2,                        0x00},
 585        {WCD938X_DIGITAL_INTR_CLEAR_0,                         0x00},
 586        {WCD938X_DIGITAL_INTR_CLEAR_1,                         0x00},
 587        {WCD938X_DIGITAL_INTR_CLEAR_2,                         0x00},
 588        {WCD938X_DIGITAL_INTR_LEVEL_0,                         0x00},
 589        {WCD938X_DIGITAL_INTR_LEVEL_1,                         0x00},
 590        {WCD938X_DIGITAL_INTR_LEVEL_2,                         0x00},
 591        {WCD938X_DIGITAL_INTR_SET_0,                           0x00},
 592        {WCD938X_DIGITAL_INTR_SET_1,                           0x00},
 593        {WCD938X_DIGITAL_INTR_SET_2,                           0x00},
 594        {WCD938X_DIGITAL_INTR_TEST_0,                          0x00},
 595        {WCD938X_DIGITAL_INTR_TEST_1,                          0x00},
 596        {WCD938X_DIGITAL_INTR_TEST_2,                          0x00},
 597        {WCD938X_DIGITAL_TX_MODE_DBG_EN,                       0x00},
 598        {WCD938X_DIGITAL_TX_MODE_DBG_0_1,                      0x00},
 599        {WCD938X_DIGITAL_TX_MODE_DBG_2_3,                      0x00},
 600        {WCD938X_DIGITAL_LB_IN_SEL_CTL,                        0x00},
 601        {WCD938X_DIGITAL_LOOP_BACK_MODE,                       0x00},
 602        {WCD938X_DIGITAL_SWR_DAC_TEST,                         0x00},
 603        {WCD938X_DIGITAL_SWR_HM_TEST_RX_0,                     0x40},
 604        {WCD938X_DIGITAL_SWR_HM_TEST_TX_0,                     0x40},
 605        {WCD938X_DIGITAL_SWR_HM_TEST_RX_1,                     0x00},
 606        {WCD938X_DIGITAL_SWR_HM_TEST_TX_1,                     0x00},
 607        {WCD938X_DIGITAL_SWR_HM_TEST_TX_2,                     0x00},
 608        {WCD938X_DIGITAL_SWR_HM_TEST_0,                        0x00},
 609        {WCD938X_DIGITAL_SWR_HM_TEST_1,                        0x00},
 610        {WCD938X_DIGITAL_PAD_CTL_SWR_0,                        0x8F},
 611        {WCD938X_DIGITAL_PAD_CTL_SWR_1,                        0x06},
 612        {WCD938X_DIGITAL_I2C_CTL,                              0x00},
 613        {WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE,                0x00},
 614        {WCD938X_DIGITAL_EFUSE_TEST_CTL_0,                     0x00},
 615        {WCD938X_DIGITAL_EFUSE_TEST_CTL_1,                     0x00},
 616        {WCD938X_DIGITAL_EFUSE_T_DATA_0,                       0x00},
 617        {WCD938X_DIGITAL_EFUSE_T_DATA_1,                       0x00},
 618        {WCD938X_DIGITAL_PAD_CTL_PDM_RX0,                      0xF1},
 619        {WCD938X_DIGITAL_PAD_CTL_PDM_RX1,                      0xF1},
 620        {WCD938X_DIGITAL_PAD_CTL_PDM_TX0,                      0xF1},
 621        {WCD938X_DIGITAL_PAD_CTL_PDM_TX1,                      0xF1},
 622        {WCD938X_DIGITAL_PAD_CTL_PDM_TX2,                      0xF1},
 623        {WCD938X_DIGITAL_PAD_INP_DIS_0,                        0x00},
 624        {WCD938X_DIGITAL_PAD_INP_DIS_1,                        0x00},
 625        {WCD938X_DIGITAL_DRIVE_STRENGTH_0,                     0x00},
 626        {WCD938X_DIGITAL_DRIVE_STRENGTH_1,                     0x00},
 627        {WCD938X_DIGITAL_DRIVE_STRENGTH_2,                     0x00},
 628        {WCD938X_DIGITAL_RX_DATA_EDGE_CTL,                     0x1F},
 629        {WCD938X_DIGITAL_TX_DATA_EDGE_CTL,                     0x80},
 630        {WCD938X_DIGITAL_GPIO_MODE,                            0x00},
 631        {WCD938X_DIGITAL_PIN_CTL_OE,                           0x00},
 632        {WCD938X_DIGITAL_PIN_CTL_DATA_0,                       0x00},
 633        {WCD938X_DIGITAL_PIN_CTL_DATA_1,                       0x00},
 634        {WCD938X_DIGITAL_PIN_STATUS_0,                         0x00},
 635        {WCD938X_DIGITAL_PIN_STATUS_1,                         0x00},
 636        {WCD938X_DIGITAL_DIG_DEBUG_CTL,                        0x00},
 637        {WCD938X_DIGITAL_DIG_DEBUG_EN,                         0x00},
 638        {WCD938X_DIGITAL_ANA_CSR_DBG_ADD,                      0x00},
 639        {WCD938X_DIGITAL_ANA_CSR_DBG_CTL,                      0x48},
 640        {WCD938X_DIGITAL_SSP_DBG,                              0x00},
 641        {WCD938X_DIGITAL_MODE_STATUS_0,                        0x00},
 642        {WCD938X_DIGITAL_MODE_STATUS_1,                        0x00},
 643        {WCD938X_DIGITAL_SPARE_0,                              0x00},
 644        {WCD938X_DIGITAL_SPARE_1,                              0x00},
 645        {WCD938X_DIGITAL_SPARE_2,                              0x00},
 646        {WCD938X_DIGITAL_EFUSE_REG_0,                          0x00},
 647        {WCD938X_DIGITAL_EFUSE_REG_1,                          0xFF},
 648        {WCD938X_DIGITAL_EFUSE_REG_2,                          0xFF},
 649        {WCD938X_DIGITAL_EFUSE_REG_3,                          0xFF},
 650        {WCD938X_DIGITAL_EFUSE_REG_4,                          0xFF},
 651        {WCD938X_DIGITAL_EFUSE_REG_5,                          0xFF},
 652        {WCD938X_DIGITAL_EFUSE_REG_6,                          0xFF},
 653        {WCD938X_DIGITAL_EFUSE_REG_7,                          0xFF},
 654        {WCD938X_DIGITAL_EFUSE_REG_8,                          0xFF},
 655        {WCD938X_DIGITAL_EFUSE_REG_9,                          0xFF},
 656        {WCD938X_DIGITAL_EFUSE_REG_10,                         0xFF},
 657        {WCD938X_DIGITAL_EFUSE_REG_11,                         0xFF},
 658        {WCD938X_DIGITAL_EFUSE_REG_12,                         0xFF},
 659        {WCD938X_DIGITAL_EFUSE_REG_13,                         0xFF},
 660        {WCD938X_DIGITAL_EFUSE_REG_14,                         0xFF},
 661        {WCD938X_DIGITAL_EFUSE_REG_15,                         0xFF},
 662        {WCD938X_DIGITAL_EFUSE_REG_16,                         0xFF},
 663        {WCD938X_DIGITAL_EFUSE_REG_17,                         0xFF},
 664        {WCD938X_DIGITAL_EFUSE_REG_18,                         0xFF},
 665        {WCD938X_DIGITAL_EFUSE_REG_19,                         0xFF},
 666        {WCD938X_DIGITAL_EFUSE_REG_20,                         0x0E},
 667        {WCD938X_DIGITAL_EFUSE_REG_21,                         0x00},
 668        {WCD938X_DIGITAL_EFUSE_REG_22,                         0x00},
 669        {WCD938X_DIGITAL_EFUSE_REG_23,                         0xF8},
 670        {WCD938X_DIGITAL_EFUSE_REG_24,                         0x16},
 671        {WCD938X_DIGITAL_EFUSE_REG_25,                         0x00},
 672        {WCD938X_DIGITAL_EFUSE_REG_26,                         0x00},
 673        {WCD938X_DIGITAL_EFUSE_REG_27,                         0x00},
 674        {WCD938X_DIGITAL_EFUSE_REG_28,                         0x00},
 675        {WCD938X_DIGITAL_EFUSE_REG_29,                         0x00},
 676        {WCD938X_DIGITAL_EFUSE_REG_30,                         0x00},
 677        {WCD938X_DIGITAL_EFUSE_REG_31,                         0x00},
 678        {WCD938X_DIGITAL_TX_REQ_FB_CTL_0,                      0x88},
 679        {WCD938X_DIGITAL_TX_REQ_FB_CTL_1,                      0x88},
 680        {WCD938X_DIGITAL_TX_REQ_FB_CTL_2,                      0x88},
 681        {WCD938X_DIGITAL_TX_REQ_FB_CTL_3,                      0x88},
 682        {WCD938X_DIGITAL_TX_REQ_FB_CTL_4,                      0x88},
 683        {WCD938X_DIGITAL_DEM_BYPASS_DATA0,                     0x55},
 684        {WCD938X_DIGITAL_DEM_BYPASS_DATA1,                     0x55},
 685        {WCD938X_DIGITAL_DEM_BYPASS_DATA2,                     0x55},
 686        {WCD938X_DIGITAL_DEM_BYPASS_DATA3,                     0x01},
 687};
 688
 689static bool wcd938x_rdwr_register(struct device *dev, unsigned int reg)
 690{
 691        switch (reg) {
 692        case WCD938X_ANA_PAGE_REGISTER:
 693        case WCD938X_ANA_BIAS:
 694        case WCD938X_ANA_RX_SUPPLIES:
 695        case WCD938X_ANA_HPH:
 696        case WCD938X_ANA_EAR:
 697        case WCD938X_ANA_EAR_COMPANDER_CTL:
 698        case WCD938X_ANA_TX_CH1:
 699        case WCD938X_ANA_TX_CH2:
 700        case WCD938X_ANA_TX_CH3:
 701        case WCD938X_ANA_TX_CH4:
 702        case WCD938X_ANA_MICB1_MICB2_DSP_EN_LOGIC:
 703        case WCD938X_ANA_MICB3_DSP_EN_LOGIC:
 704        case WCD938X_ANA_MBHC_MECH:
 705        case WCD938X_ANA_MBHC_ELECT:
 706        case WCD938X_ANA_MBHC_ZDET:
 707        case WCD938X_ANA_MBHC_BTN0:
 708        case WCD938X_ANA_MBHC_BTN1:
 709        case WCD938X_ANA_MBHC_BTN2:
 710        case WCD938X_ANA_MBHC_BTN3:
 711        case WCD938X_ANA_MBHC_BTN4:
 712        case WCD938X_ANA_MBHC_BTN5:
 713        case WCD938X_ANA_MBHC_BTN6:
 714        case WCD938X_ANA_MBHC_BTN7:
 715        case WCD938X_ANA_MICB1:
 716        case WCD938X_ANA_MICB2:
 717        case WCD938X_ANA_MICB2_RAMP:
 718        case WCD938X_ANA_MICB3:
 719        case WCD938X_ANA_MICB4:
 720        case WCD938X_BIAS_CTL:
 721        case WCD938X_BIAS_VBG_FINE_ADJ:
 722        case WCD938X_LDOL_VDDCX_ADJUST:
 723        case WCD938X_LDOL_DISABLE_LDOL:
 724        case WCD938X_MBHC_CTL_CLK:
 725        case WCD938X_MBHC_CTL_ANA:
 726        case WCD938X_MBHC_CTL_SPARE_1:
 727        case WCD938X_MBHC_CTL_SPARE_2:
 728        case WCD938X_MBHC_CTL_BCS:
 729        case WCD938X_MBHC_TEST_CTL:
 730        case WCD938X_LDOH_MODE:
 731        case WCD938X_LDOH_BIAS:
 732        case WCD938X_LDOH_STB_LOADS:
 733        case WCD938X_LDOH_SLOWRAMP:
 734        case WCD938X_MICB1_TEST_CTL_1:
 735        case WCD938X_MICB1_TEST_CTL_2:
 736        case WCD938X_MICB1_TEST_CTL_3:
 737        case WCD938X_MICB2_TEST_CTL_1:
 738        case WCD938X_MICB2_TEST_CTL_2:
 739        case WCD938X_MICB2_TEST_CTL_3:
 740        case WCD938X_MICB3_TEST_CTL_1:
 741        case WCD938X_MICB3_TEST_CTL_2:
 742        case WCD938X_MICB3_TEST_CTL_3:
 743        case WCD938X_MICB4_TEST_CTL_1:
 744        case WCD938X_MICB4_TEST_CTL_2:
 745        case WCD938X_MICB4_TEST_CTL_3:
 746        case WCD938X_TX_COM_ADC_VCM:
 747        case WCD938X_TX_COM_BIAS_ATEST:
 748        case WCD938X_TX_COM_SPARE1:
 749        case WCD938X_TX_COM_SPARE2:
 750        case WCD938X_TX_COM_TXFE_DIV_CTL:
 751        case WCD938X_TX_COM_TXFE_DIV_START:
 752        case WCD938X_TX_COM_SPARE3:
 753        case WCD938X_TX_COM_SPARE4:
 754        case WCD938X_TX_1_2_TEST_EN:
 755        case WCD938X_TX_1_2_ADC_IB:
 756        case WCD938X_TX_1_2_ATEST_REFCTL:
 757        case WCD938X_TX_1_2_TEST_CTL:
 758        case WCD938X_TX_1_2_TEST_BLK_EN1:
 759        case WCD938X_TX_1_2_TXFE1_CLKDIV:
 760        case WCD938X_TX_3_4_TEST_EN:
 761        case WCD938X_TX_3_4_ADC_IB:
 762        case WCD938X_TX_3_4_ATEST_REFCTL:
 763        case WCD938X_TX_3_4_TEST_CTL:
 764        case WCD938X_TX_3_4_TEST_BLK_EN3:
 765        case WCD938X_TX_3_4_TXFE3_CLKDIV:
 766        case WCD938X_TX_3_4_TEST_BLK_EN2:
 767        case WCD938X_TX_3_4_TXFE2_CLKDIV:
 768        case WCD938X_TX_3_4_SPARE1:
 769        case WCD938X_TX_3_4_TEST_BLK_EN4:
 770        case WCD938X_TX_3_4_TXFE4_CLKDIV:
 771        case WCD938X_TX_3_4_SPARE2:
 772        case WCD938X_CLASSH_MODE_1:
 773        case WCD938X_CLASSH_MODE_2:
 774        case WCD938X_CLASSH_MODE_3:
 775        case WCD938X_CLASSH_CTRL_VCL_1:
 776        case WCD938X_CLASSH_CTRL_VCL_2:
 777        case WCD938X_CLASSH_CTRL_CCL_1:
 778        case WCD938X_CLASSH_CTRL_CCL_2:
 779        case WCD938X_CLASSH_CTRL_CCL_3:
 780        case WCD938X_CLASSH_CTRL_CCL_4:
 781        case WCD938X_CLASSH_CTRL_CCL_5:
 782        case WCD938X_CLASSH_BUCK_TMUX_A_D:
 783        case WCD938X_CLASSH_BUCK_SW_DRV_CNTL:
 784        case WCD938X_CLASSH_SPARE:
 785        case WCD938X_FLYBACK_EN:
 786        case WCD938X_FLYBACK_VNEG_CTRL_1:
 787        case WCD938X_FLYBACK_VNEG_CTRL_2:
 788        case WCD938X_FLYBACK_VNEG_CTRL_3:
 789        case WCD938X_FLYBACK_VNEG_CTRL_4:
 790        case WCD938X_FLYBACK_VNEG_CTRL_5:
 791        case WCD938X_FLYBACK_VNEG_CTRL_6:
 792        case WCD938X_FLYBACK_VNEG_CTRL_7:
 793        case WCD938X_FLYBACK_VNEG_CTRL_8:
 794        case WCD938X_FLYBACK_VNEG_CTRL_9:
 795        case WCD938X_FLYBACK_VNEGDAC_CTRL_1:
 796        case WCD938X_FLYBACK_VNEGDAC_CTRL_2:
 797        case WCD938X_FLYBACK_VNEGDAC_CTRL_3:
 798        case WCD938X_FLYBACK_CTRL_1:
 799        case WCD938X_FLYBACK_TEST_CTL:
 800        case WCD938X_RX_AUX_SW_CTL:
 801        case WCD938X_RX_PA_AUX_IN_CONN:
 802        case WCD938X_RX_TIMER_DIV:
 803        case WCD938X_RX_OCP_CTL:
 804        case WCD938X_RX_OCP_COUNT:
 805        case WCD938X_RX_BIAS_EAR_DAC:
 806        case WCD938X_RX_BIAS_EAR_AMP:
 807        case WCD938X_RX_BIAS_HPH_LDO:
 808        case WCD938X_RX_BIAS_HPH_PA:
 809        case WCD938X_RX_BIAS_HPH_RDACBUFF_CNP2:
 810        case WCD938X_RX_BIAS_HPH_RDAC_LDO:
 811        case WCD938X_RX_BIAS_HPH_CNP1:
 812        case WCD938X_RX_BIAS_HPH_LOWPOWER:
 813        case WCD938X_RX_BIAS_AUX_DAC:
 814        case WCD938X_RX_BIAS_AUX_AMP:
 815        case WCD938X_RX_BIAS_VNEGDAC_BLEEDER:
 816        case WCD938X_RX_BIAS_MISC:
 817        case WCD938X_RX_BIAS_BUCK_RST:
 818        case WCD938X_RX_BIAS_BUCK_VREF_ERRAMP:
 819        case WCD938X_RX_BIAS_FLYB_ERRAMP:
 820        case WCD938X_RX_BIAS_FLYB_BUFF:
 821        case WCD938X_RX_BIAS_FLYB_MID_RST:
 822        case WCD938X_HPH_CNP_EN:
 823        case WCD938X_HPH_CNP_WG_CTL:
 824        case WCD938X_HPH_CNP_WG_TIME:
 825        case WCD938X_HPH_OCP_CTL:
 826        case WCD938X_HPH_AUTO_CHOP:
 827        case WCD938X_HPH_CHOP_CTL:
 828        case WCD938X_HPH_PA_CTL1:
 829        case WCD938X_HPH_PA_CTL2:
 830        case WCD938X_HPH_L_EN:
 831        case WCD938X_HPH_L_TEST:
 832        case WCD938X_HPH_L_ATEST:
 833        case WCD938X_HPH_R_EN:
 834        case WCD938X_HPH_R_TEST:
 835        case WCD938X_HPH_R_ATEST:
 836        case WCD938X_HPH_RDAC_CLK_CTL1:
 837        case WCD938X_HPH_RDAC_CLK_CTL2:
 838        case WCD938X_HPH_RDAC_LDO_CTL:
 839        case WCD938X_HPH_RDAC_CHOP_CLK_LP_CTL:
 840        case WCD938X_HPH_REFBUFF_UHQA_CTL:
 841        case WCD938X_HPH_REFBUFF_LP_CTL:
 842        case WCD938X_HPH_L_DAC_CTL:
 843        case WCD938X_HPH_R_DAC_CTL:
 844        case WCD938X_HPH_SURGE_HPHLR_SURGE_COMP_SEL:
 845        case WCD938X_HPH_SURGE_HPHLR_SURGE_EN:
 846        case WCD938X_HPH_SURGE_HPHLR_SURGE_MISC1:
 847        case WCD938X_EAR_EAR_EN_REG:
 848        case WCD938X_EAR_EAR_PA_CON:
 849        case WCD938X_EAR_EAR_SP_CON:
 850        case WCD938X_EAR_EAR_DAC_CON:
 851        case WCD938X_EAR_EAR_CNP_FSM_CON:
 852        case WCD938X_EAR_TEST_CTL:
 853        case WCD938X_ANA_NEW_PAGE_REGISTER:
 854        case WCD938X_HPH_NEW_ANA_HPH2:
 855        case WCD938X_HPH_NEW_ANA_HPH3:
 856        case WCD938X_SLEEP_CTL:
 857        case WCD938X_SLEEP_WATCHDOG_CTL:
 858        case WCD938X_MBHC_NEW_ELECT_REM_CLAMP_CTL:
 859        case WCD938X_MBHC_NEW_CTL_1:
 860        case WCD938X_MBHC_NEW_CTL_2:
 861        case WCD938X_MBHC_NEW_PLUG_DETECT_CTL:
 862        case WCD938X_MBHC_NEW_ZDET_ANA_CTL:
 863        case WCD938X_MBHC_NEW_ZDET_RAMP_CTL:
 864        case WCD938X_TX_NEW_AMIC_MUX_CFG:
 865        case WCD938X_AUX_AUXPA:
 866        case WCD938X_LDORXTX_MODE:
 867        case WCD938X_LDORXTX_CONFIG:
 868        case WCD938X_DIE_CRACK_DIE_CRK_DET_EN:
 869        case WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL:
 870        case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L:
 871        case WCD938X_HPH_NEW_INT_RDAC_VREF_CTL:
 872        case WCD938X_HPH_NEW_INT_RDAC_OVERRIDE_CTL:
 873        case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R:
 874        case WCD938X_HPH_NEW_INT_PA_MISC1:
 875        case WCD938X_HPH_NEW_INT_PA_MISC2:
 876        case WCD938X_HPH_NEW_INT_PA_RDAC_MISC:
 877        case WCD938X_HPH_NEW_INT_HPH_TIMER1:
 878        case WCD938X_HPH_NEW_INT_HPH_TIMER2:
 879        case WCD938X_HPH_NEW_INT_HPH_TIMER3:
 880        case WCD938X_HPH_NEW_INT_HPH_TIMER4:
 881        case WCD938X_HPH_NEW_INT_PA_RDAC_MISC2:
 882        case WCD938X_HPH_NEW_INT_PA_RDAC_MISC3:
 883        case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW:
 884        case WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW:
 885        case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI:
 886        case WCD938X_RX_NEW_INT_HPH_RDAC_BIAS_ULP:
 887        case WCD938X_RX_NEW_INT_HPH_RDAC_LDO_LP:
 888        case WCD938X_MBHC_NEW_INT_MOISTURE_DET_DC_CTRL:
 889        case WCD938X_MBHC_NEW_INT_MOISTURE_DET_POLLING_CTRL:
 890        case WCD938X_MBHC_NEW_INT_MECH_DET_CURRENT:
 891        case WCD938X_MBHC_NEW_INT_SPARE_2:
 892        case WCD938X_EAR_INT_NEW_EAR_CHOPPER_CON:
 893        case WCD938X_EAR_INT_NEW_CNP_VCM_CON1:
 894        case WCD938X_EAR_INT_NEW_CNP_VCM_CON2:
 895        case WCD938X_EAR_INT_NEW_EAR_DYNAMIC_BIAS:
 896        case WCD938X_AUX_INT_EN_REG:
 897        case WCD938X_AUX_INT_PA_CTRL:
 898        case WCD938X_AUX_INT_SP_CTRL:
 899        case WCD938X_AUX_INT_DAC_CTRL:
 900        case WCD938X_AUX_INT_CLK_CTRL:
 901        case WCD938X_AUX_INT_TEST_CTRL:
 902        case WCD938X_AUX_INT_MISC:
 903        case WCD938X_LDORXTX_INT_BIAS:
 904        case WCD938X_LDORXTX_INT_STB_LOADS_DTEST:
 905        case WCD938X_LDORXTX_INT_TEST0:
 906        case WCD938X_LDORXTX_INT_STARTUP_TIMER:
 907        case WCD938X_LDORXTX_INT_TEST1:
 908        case WCD938X_SLEEP_INT_WATCHDOG_CTL_1:
 909        case WCD938X_SLEEP_INT_WATCHDOG_CTL_2:
 910        case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT1:
 911        case WCD938X_DIE_CRACK_INT_DIE_CRK_DET_INT2:
 912        case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L2:
 913        case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L1:
 914        case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_L0:
 915        case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP1P2M:
 916        case WCD938X_TX_COM_NEW_INT_TXFE_DIVSTOP_ULP0P6M:
 917        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L2L1:
 918        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_L0:
 919        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG1_ULP:
 920        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L2L1:
 921        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_L0:
 922        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP:
 923        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_L2L1L0:
 924        case WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP:
 925        case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L2L1:
 926        case WCD938X_TX_COM_NEW_INT_TXADC_SCBIAS_L0ULP:
 927        case WCD938X_TX_COM_NEW_INT_TXADC_INT_L2:
 928        case WCD938X_TX_COM_NEW_INT_TXADC_INT_L1:
 929        case WCD938X_TX_COM_NEW_INT_TXADC_INT_L0:
 930        case WCD938X_TX_COM_NEW_INT_TXADC_INT_ULP:
 931        case WCD938X_DIGITAL_PAGE_REGISTER:
 932        case WCD938X_DIGITAL_SWR_TX_CLK_RATE:
 933        case WCD938X_DIGITAL_CDC_RST_CTL:
 934        case WCD938X_DIGITAL_TOP_CLK_CFG:
 935        case WCD938X_DIGITAL_CDC_ANA_CLK_CTL:
 936        case WCD938X_DIGITAL_CDC_DIG_CLK_CTL:
 937        case WCD938X_DIGITAL_SWR_RST_EN:
 938        case WCD938X_DIGITAL_CDC_PATH_MODE:
 939        case WCD938X_DIGITAL_CDC_RX_RST:
 940        case WCD938X_DIGITAL_CDC_RX0_CTL:
 941        case WCD938X_DIGITAL_CDC_RX1_CTL:
 942        case WCD938X_DIGITAL_CDC_RX2_CTL:
 943        case WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1:
 944        case WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3:
 945        case WCD938X_DIGITAL_CDC_COMP_CTL_0:
 946        case WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL:
 947        case WCD938X_DIGITAL_CDC_HPH_DSM_A1_0:
 948        case WCD938X_DIGITAL_CDC_HPH_DSM_A1_1:
 949        case WCD938X_DIGITAL_CDC_HPH_DSM_A2_0:
 950        case WCD938X_DIGITAL_CDC_HPH_DSM_A2_1:
 951        case WCD938X_DIGITAL_CDC_HPH_DSM_A3_0:
 952        case WCD938X_DIGITAL_CDC_HPH_DSM_A3_1:
 953        case WCD938X_DIGITAL_CDC_HPH_DSM_A4_0:
 954        case WCD938X_DIGITAL_CDC_HPH_DSM_A4_1:
 955        case WCD938X_DIGITAL_CDC_HPH_DSM_A5_0:
 956        case WCD938X_DIGITAL_CDC_HPH_DSM_A5_1:
 957        case WCD938X_DIGITAL_CDC_HPH_DSM_A6_0:
 958        case WCD938X_DIGITAL_CDC_HPH_DSM_A7_0:
 959        case WCD938X_DIGITAL_CDC_HPH_DSM_C_0:
 960        case WCD938X_DIGITAL_CDC_HPH_DSM_C_1:
 961        case WCD938X_DIGITAL_CDC_HPH_DSM_C_2:
 962        case WCD938X_DIGITAL_CDC_HPH_DSM_C_3:
 963        case WCD938X_DIGITAL_CDC_HPH_DSM_R1:
 964        case WCD938X_DIGITAL_CDC_HPH_DSM_R2:
 965        case WCD938X_DIGITAL_CDC_HPH_DSM_R3:
 966        case WCD938X_DIGITAL_CDC_HPH_DSM_R4:
 967        case WCD938X_DIGITAL_CDC_HPH_DSM_R5:
 968        case WCD938X_DIGITAL_CDC_HPH_DSM_R6:
 969        case WCD938X_DIGITAL_CDC_HPH_DSM_R7:
 970        case WCD938X_DIGITAL_CDC_AUX_DSM_A1_0:
 971        case WCD938X_DIGITAL_CDC_AUX_DSM_A1_1:
 972        case WCD938X_DIGITAL_CDC_AUX_DSM_A2_0:
 973        case WCD938X_DIGITAL_CDC_AUX_DSM_A2_1:
 974        case WCD938X_DIGITAL_CDC_AUX_DSM_A3_0:
 975        case WCD938X_DIGITAL_CDC_AUX_DSM_A3_1:
 976        case WCD938X_DIGITAL_CDC_AUX_DSM_A4_0:
 977        case WCD938X_DIGITAL_CDC_AUX_DSM_A4_1:
 978        case WCD938X_DIGITAL_CDC_AUX_DSM_A5_0:
 979        case WCD938X_DIGITAL_CDC_AUX_DSM_A5_1:
 980        case WCD938X_DIGITAL_CDC_AUX_DSM_A6_0:
 981        case WCD938X_DIGITAL_CDC_AUX_DSM_A7_0:
 982        case WCD938X_DIGITAL_CDC_AUX_DSM_C_0:
 983        case WCD938X_DIGITAL_CDC_AUX_DSM_C_1:
 984        case WCD938X_DIGITAL_CDC_AUX_DSM_C_2:
 985        case WCD938X_DIGITAL_CDC_AUX_DSM_C_3:
 986        case WCD938X_DIGITAL_CDC_AUX_DSM_R1:
 987        case WCD938X_DIGITAL_CDC_AUX_DSM_R2:
 988        case WCD938X_DIGITAL_CDC_AUX_DSM_R3:
 989        case WCD938X_DIGITAL_CDC_AUX_DSM_R4:
 990        case WCD938X_DIGITAL_CDC_AUX_DSM_R5:
 991        case WCD938X_DIGITAL_CDC_AUX_DSM_R6:
 992        case WCD938X_DIGITAL_CDC_AUX_DSM_R7:
 993        case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_0:
 994        case WCD938X_DIGITAL_CDC_HPH_GAIN_RX_1:
 995        case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_0:
 996        case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_1:
 997        case WCD938X_DIGITAL_CDC_HPH_GAIN_DSD_2:
 998        case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_0:
 999        case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_1:
1000        case WCD938X_DIGITAL_CDC_AUX_GAIN_DSD_2:
1001        case WCD938X_DIGITAL_CDC_HPH_GAIN_CTL:
1002        case WCD938X_DIGITAL_CDC_AUX_GAIN_CTL:
1003        case WCD938X_DIGITAL_CDC_EAR_PATH_CTL:
1004        case WCD938X_DIGITAL_CDC_SWR_CLH:
1005        case WCD938X_DIGITAL_SWR_CLH_BYP:
1006        case WCD938X_DIGITAL_CDC_TX0_CTL:
1007        case WCD938X_DIGITAL_CDC_TX1_CTL:
1008        case WCD938X_DIGITAL_CDC_TX2_CTL:
1009        case WCD938X_DIGITAL_CDC_TX_RST:
1010        case WCD938X_DIGITAL_CDC_REQ_CTL:
1011        case WCD938X_DIGITAL_CDC_RST:
1012        case WCD938X_DIGITAL_CDC_AMIC_CTL:
1013        case WCD938X_DIGITAL_CDC_DMIC_CTL:
1014        case WCD938X_DIGITAL_CDC_DMIC1_CTL:
1015        case WCD938X_DIGITAL_CDC_DMIC2_CTL:
1016        case WCD938X_DIGITAL_CDC_DMIC3_CTL:
1017        case WCD938X_DIGITAL_CDC_DMIC4_CTL:
1018        case WCD938X_DIGITAL_EFUSE_PRG_CTL:
1019        case WCD938X_DIGITAL_EFUSE_CTL:
1020        case WCD938X_DIGITAL_CDC_DMIC_RATE_1_2:
1021        case WCD938X_DIGITAL_CDC_DMIC_RATE_3_4:
1022        case WCD938X_DIGITAL_PDM_WD_CTL0:
1023        case WCD938X_DIGITAL_PDM_WD_CTL1:
1024        case WCD938X_DIGITAL_PDM_WD_CTL2:
1025        case WCD938X_DIGITAL_INTR_MODE:
1026        case WCD938X_DIGITAL_INTR_MASK_0:
1027        case WCD938X_DIGITAL_INTR_MASK_1:
1028        case WCD938X_DIGITAL_INTR_MASK_2:
1029        case WCD938X_DIGITAL_INTR_CLEAR_0:
1030        case WCD938X_DIGITAL_INTR_CLEAR_1:
1031        case WCD938X_DIGITAL_INTR_CLEAR_2:
1032        case WCD938X_DIGITAL_INTR_LEVEL_0:
1033        case WCD938X_DIGITAL_INTR_LEVEL_1:
1034        case WCD938X_DIGITAL_INTR_LEVEL_2:
1035        case WCD938X_DIGITAL_INTR_SET_0:
1036        case WCD938X_DIGITAL_INTR_SET_1:
1037        case WCD938X_DIGITAL_INTR_SET_2:
1038        case WCD938X_DIGITAL_INTR_TEST_0:
1039        case WCD938X_DIGITAL_INTR_TEST_1:
1040        case WCD938X_DIGITAL_INTR_TEST_2:
1041        case WCD938X_DIGITAL_TX_MODE_DBG_EN:
1042        case WCD938X_DIGITAL_TX_MODE_DBG_0_1:
1043        case WCD938X_DIGITAL_TX_MODE_DBG_2_3:
1044        case WCD938X_DIGITAL_LB_IN_SEL_CTL:
1045        case WCD938X_DIGITAL_LOOP_BACK_MODE:
1046        case WCD938X_DIGITAL_SWR_DAC_TEST:
1047        case WCD938X_DIGITAL_SWR_HM_TEST_RX_0:
1048        case WCD938X_DIGITAL_SWR_HM_TEST_TX_0:
1049        case WCD938X_DIGITAL_SWR_HM_TEST_RX_1:
1050        case WCD938X_DIGITAL_SWR_HM_TEST_TX_1:
1051        case WCD938X_DIGITAL_SWR_HM_TEST_TX_2:
1052        case WCD938X_DIGITAL_PAD_CTL_SWR_0:
1053        case WCD938X_DIGITAL_PAD_CTL_SWR_1:
1054        case WCD938X_DIGITAL_I2C_CTL:
1055        case WCD938X_DIGITAL_CDC_TX_TANGGU_SW_MODE:
1056        case WCD938X_DIGITAL_EFUSE_TEST_CTL_0:
1057        case WCD938X_DIGITAL_EFUSE_TEST_CTL_1:
1058        case WCD938X_DIGITAL_PAD_CTL_PDM_RX0:
1059        case WCD938X_DIGITAL_PAD_CTL_PDM_RX1:
1060        case WCD938X_DIGITAL_PAD_CTL_PDM_TX0:
1061        case WCD938X_DIGITAL_PAD_CTL_PDM_TX1:
1062        case WCD938X_DIGITAL_PAD_CTL_PDM_TX2:
1063        case WCD938X_DIGITAL_PAD_INP_DIS_0:
1064        case WCD938X_DIGITAL_PAD_INP_DIS_1:
1065        case WCD938X_DIGITAL_DRIVE_STRENGTH_0:
1066        case WCD938X_DIGITAL_DRIVE_STRENGTH_1:
1067        case WCD938X_DIGITAL_DRIVE_STRENGTH_2:
1068        case WCD938X_DIGITAL_RX_DATA_EDGE_CTL:
1069        case WCD938X_DIGITAL_TX_DATA_EDGE_CTL:
1070        case WCD938X_DIGITAL_GPIO_MODE:
1071        case WCD938X_DIGITAL_PIN_CTL_OE:
1072        case WCD938X_DIGITAL_PIN_CTL_DATA_0:
1073        case WCD938X_DIGITAL_PIN_CTL_DATA_1:
1074        case WCD938X_DIGITAL_DIG_DEBUG_CTL:
1075        case WCD938X_DIGITAL_DIG_DEBUG_EN:
1076        case WCD938X_DIGITAL_ANA_CSR_DBG_ADD:
1077        case WCD938X_DIGITAL_ANA_CSR_DBG_CTL:
1078        case WCD938X_DIGITAL_SSP_DBG:
1079        case WCD938X_DIGITAL_SPARE_0:
1080        case WCD938X_DIGITAL_SPARE_1:
1081        case WCD938X_DIGITAL_SPARE_2:
1082        case WCD938X_DIGITAL_TX_REQ_FB_CTL_0:
1083        case WCD938X_DIGITAL_TX_REQ_FB_CTL_1:
1084        case WCD938X_DIGITAL_TX_REQ_FB_CTL_2:
1085        case WCD938X_DIGITAL_TX_REQ_FB_CTL_3:
1086        case WCD938X_DIGITAL_TX_REQ_FB_CTL_4:
1087        case WCD938X_DIGITAL_DEM_BYPASS_DATA0:
1088        case WCD938X_DIGITAL_DEM_BYPASS_DATA1:
1089        case WCD938X_DIGITAL_DEM_BYPASS_DATA2:
1090        case WCD938X_DIGITAL_DEM_BYPASS_DATA3:
1091                return true;
1092        }
1093
1094        return false;
1095}
1096
1097static bool wcd938x_readonly_register(struct device *dev, unsigned int reg)
1098{
1099        switch (reg) {
1100        case WCD938X_ANA_MBHC_RESULT_1:
1101        case WCD938X_ANA_MBHC_RESULT_2:
1102        case WCD938X_ANA_MBHC_RESULT_3:
1103        case WCD938X_MBHC_MOISTURE_DET_FSM_STATUS:
1104        case WCD938X_TX_1_2_SAR2_ERR:
1105        case WCD938X_TX_1_2_SAR1_ERR:
1106        case WCD938X_TX_3_4_SAR4_ERR:
1107        case WCD938X_TX_3_4_SAR3_ERR:
1108        case WCD938X_HPH_L_STATUS:
1109        case WCD938X_HPH_R_STATUS:
1110        case WCD938X_HPH_SURGE_HPHLR_SURGE_STATUS:
1111        case WCD938X_EAR_STATUS_REG_1:
1112        case WCD938X_EAR_STATUS_REG_2:
1113        case WCD938X_MBHC_NEW_FSM_STATUS:
1114        case WCD938X_MBHC_NEW_ADC_RESULT:
1115        case WCD938X_DIE_CRACK_DIE_CRK_DET_OUT:
1116        case WCD938X_AUX_INT_STATUS_REG:
1117        case WCD938X_LDORXTX_INT_STATUS:
1118        case WCD938X_DIGITAL_CHIP_ID0:
1119        case WCD938X_DIGITAL_CHIP_ID1:
1120        case WCD938X_DIGITAL_CHIP_ID2:
1121        case WCD938X_DIGITAL_CHIP_ID3:
1122        case WCD938X_DIGITAL_INTR_STATUS_0:
1123        case WCD938X_DIGITAL_INTR_STATUS_1:
1124        case WCD938X_DIGITAL_INTR_STATUS_2:
1125        case WCD938X_DIGITAL_SWR_HM_TEST_0:
1126        case WCD938X_DIGITAL_SWR_HM_TEST_1:
1127        case WCD938X_DIGITAL_EFUSE_T_DATA_0:
1128        case WCD938X_DIGITAL_EFUSE_T_DATA_1:
1129        case WCD938X_DIGITAL_PIN_STATUS_0:
1130        case WCD938X_DIGITAL_PIN_STATUS_1:
1131        case WCD938X_DIGITAL_MODE_STATUS_0:
1132        case WCD938X_DIGITAL_MODE_STATUS_1:
1133        case WCD938X_DIGITAL_EFUSE_REG_0:
1134        case WCD938X_DIGITAL_EFUSE_REG_1:
1135        case WCD938X_DIGITAL_EFUSE_REG_2:
1136        case WCD938X_DIGITAL_EFUSE_REG_3:
1137        case WCD938X_DIGITAL_EFUSE_REG_4:
1138        case WCD938X_DIGITAL_EFUSE_REG_5:
1139        case WCD938X_DIGITAL_EFUSE_REG_6:
1140        case WCD938X_DIGITAL_EFUSE_REG_7:
1141        case WCD938X_DIGITAL_EFUSE_REG_8:
1142        case WCD938X_DIGITAL_EFUSE_REG_9:
1143        case WCD938X_DIGITAL_EFUSE_REG_10:
1144        case WCD938X_DIGITAL_EFUSE_REG_11:
1145        case WCD938X_DIGITAL_EFUSE_REG_12:
1146        case WCD938X_DIGITAL_EFUSE_REG_13:
1147        case WCD938X_DIGITAL_EFUSE_REG_14:
1148        case WCD938X_DIGITAL_EFUSE_REG_15:
1149        case WCD938X_DIGITAL_EFUSE_REG_16:
1150        case WCD938X_DIGITAL_EFUSE_REG_17:
1151        case WCD938X_DIGITAL_EFUSE_REG_18:
1152        case WCD938X_DIGITAL_EFUSE_REG_19:
1153        case WCD938X_DIGITAL_EFUSE_REG_20:
1154        case WCD938X_DIGITAL_EFUSE_REG_21:
1155        case WCD938X_DIGITAL_EFUSE_REG_22:
1156        case WCD938X_DIGITAL_EFUSE_REG_23:
1157        case WCD938X_DIGITAL_EFUSE_REG_24:
1158        case WCD938X_DIGITAL_EFUSE_REG_25:
1159        case WCD938X_DIGITAL_EFUSE_REG_26:
1160        case WCD938X_DIGITAL_EFUSE_REG_27:
1161        case WCD938X_DIGITAL_EFUSE_REG_28:
1162        case WCD938X_DIGITAL_EFUSE_REG_29:
1163        case WCD938X_DIGITAL_EFUSE_REG_30:
1164        case WCD938X_DIGITAL_EFUSE_REG_31:
1165                return true;
1166        }
1167        return false;
1168}
1169
1170static bool wcd938x_readable_register(struct device *dev, unsigned int reg)
1171{
1172        bool ret;
1173
1174        ret = wcd938x_readonly_register(dev, reg);
1175        if (!ret)
1176                return wcd938x_rdwr_register(dev, reg);
1177
1178        return ret;
1179}
1180
1181static bool wcd938x_writeable_register(struct device *dev, unsigned int reg)
1182{
1183        return wcd938x_rdwr_register(dev, reg);
1184}
1185
1186static bool wcd938x_volatile_register(struct device *dev, unsigned int reg)
1187{
1188        if (reg <= WCD938X_BASE_ADDRESS)
1189                return false;
1190
1191        if (reg == WCD938X_DIGITAL_SWR_TX_CLK_RATE)
1192                return true;
1193
1194        if (wcd938x_readonly_register(dev, reg))
1195                return true;
1196
1197        return false;
1198}
1199
1200static struct regmap_config wcd938x_regmap_config = {
1201        .name = "wcd938x_csr",
1202        .reg_bits = 32,
1203        .val_bits = 8,
1204        .cache_type = REGCACHE_RBTREE,
1205        .reg_defaults = wcd938x_defaults,
1206        .num_reg_defaults = ARRAY_SIZE(wcd938x_defaults),
1207        .max_register = WCD938X_MAX_REGISTER,
1208        .readable_reg = wcd938x_readable_register,
1209        .writeable_reg = wcd938x_writeable_register,
1210        .volatile_reg = wcd938x_volatile_register,
1211        .can_multi_write = true,
1212};
1213
1214static const struct regmap_irq wcd938x_irqs[WCD938X_NUM_IRQS] = {
1215        REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_PRESS_DET, 0, 0x01),
1216        REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_BUTTON_RELEASE_DET, 0, 0x02),
1217        REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_DET, 0, 0x04),
1218        REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_ELECT_INS_REM_LEG_DET, 0, 0x08),
1219        REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_SW_DET, 0, 0x10),
1220        REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_OCP_INT, 0, 0x20),
1221        REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_CNP_INT, 0, 0x40),
1222        REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_OCP_INT, 0, 0x80),
1223        REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_CNP_INT, 1, 0x01),
1224        REGMAP_IRQ_REG(WCD938X_IRQ_EAR_CNP_INT, 1, 0x02),
1225        REGMAP_IRQ_REG(WCD938X_IRQ_EAR_SCD_INT, 1, 0x04),
1226        REGMAP_IRQ_REG(WCD938X_IRQ_AUX_CNP_INT, 1, 0x08),
1227        REGMAP_IRQ_REG(WCD938X_IRQ_AUX_SCD_INT, 1, 0x10),
1228        REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_PDM_WD_INT, 1, 0x20),
1229        REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_PDM_WD_INT, 1, 0x40),
1230        REGMAP_IRQ_REG(WCD938X_IRQ_AUX_PDM_WD_INT, 1, 0x80),
1231        REGMAP_IRQ_REG(WCD938X_IRQ_LDORT_SCD_INT, 2, 0x01),
1232        REGMAP_IRQ_REG(WCD938X_IRQ_MBHC_MOISTURE_INT, 2, 0x02),
1233        REGMAP_IRQ_REG(WCD938X_IRQ_HPHL_SURGE_DET_INT, 2, 0x04),
1234        REGMAP_IRQ_REG(WCD938X_IRQ_HPHR_SURGE_DET_INT, 2, 0x08),
1235};
1236
1237static struct regmap_irq_chip wcd938x_regmap_irq_chip = {
1238        .name = "wcd938x",
1239        .irqs = wcd938x_irqs,
1240        .num_irqs = ARRAY_SIZE(wcd938x_irqs),
1241        .num_regs = 3,
1242        .status_base = WCD938X_DIGITAL_INTR_STATUS_0,
1243        .mask_base = WCD938X_DIGITAL_INTR_MASK_0,
1244        .type_base = WCD938X_DIGITAL_INTR_LEVEL_0,
1245        .ack_base = WCD938X_DIGITAL_INTR_CLEAR_0,
1246        .use_ack = 1,
1247        .runtime_pm = true,
1248        .irq_drv_data = NULL,
1249};
1250
1251static int wcd938x_get_clk_rate(int mode)
1252{
1253        int rate;
1254
1255        switch (mode) {
1256        case ADC_MODE_ULP2:
1257                rate = SWR_CLK_RATE_0P6MHZ;
1258                break;
1259        case ADC_MODE_ULP1:
1260                rate = SWR_CLK_RATE_1P2MHZ;
1261                break;
1262        case ADC_MODE_LP:
1263                rate = SWR_CLK_RATE_4P8MHZ;
1264                break;
1265        case ADC_MODE_NORMAL:
1266        case ADC_MODE_LO_HIF:
1267        case ADC_MODE_HIFI:
1268        case ADC_MODE_INVALID:
1269        default:
1270                rate = SWR_CLK_RATE_9P6MHZ;
1271                break;
1272        }
1273
1274        return rate;
1275}
1276
1277static int wcd938x_set_swr_clk_rate(struct snd_soc_component *component, int rate, int bank)
1278{
1279        u8 mask = (bank ? 0xF0 : 0x0F);
1280        u8 val = 0;
1281
1282        switch (rate) {
1283        case SWR_CLK_RATE_0P6MHZ:
1284                val = (bank ? 0x60 : 0x06);
1285                break;
1286        case SWR_CLK_RATE_1P2MHZ:
1287                val = (bank ? 0x50 : 0x05);
1288                break;
1289        case SWR_CLK_RATE_2P4MHZ:
1290                val = (bank ? 0x30 : 0x03);
1291                break;
1292        case SWR_CLK_RATE_4P8MHZ:
1293                val = (bank ? 0x10 : 0x01);
1294                break;
1295        case SWR_CLK_RATE_9P6MHZ:
1296        default:
1297                val = 0x00;
1298                break;
1299        }
1300        snd_soc_component_update_bits(component, WCD938X_DIGITAL_SWR_TX_CLK_RATE,
1301                                      mask, val);
1302
1303        return 0;
1304}
1305
1306static int wcd938x_io_init(struct wcd938x_priv *wcd938x)
1307{
1308        struct regmap *rm = wcd938x->regmap;
1309
1310        regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x0E, 0x0E);
1311        regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x80, 0x80);
1312        /* 1 msec delay as per HW requirement */
1313        usleep_range(1000, 1010);
1314        regmap_update_bits(rm, WCD938X_SLEEP_CTL, 0x40, 0x40);
1315        /* 1 msec delay as per HW requirement */
1316        usleep_range(1000, 1010);
1317        regmap_update_bits(rm, WCD938X_LDORXTX_CONFIG, 0x10, 0x00);
1318        regmap_update_bits(rm, WCD938X_BIAS_VBG_FINE_ADJ,
1319                                                                0xF0, 0x80);
1320        regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x80, 0x80);
1321        regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x40);
1322        /* 10 msec delay as per HW requirement */
1323        usleep_range(10000, 10010);
1324
1325        regmap_update_bits(rm, WCD938X_ANA_BIAS, 0x40, 0x00);
1326        regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_GAIN_CTL,
1327                                      0xF0, 0x00);
1328        regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L_NEW,
1329                                      0x1F, 0x15);
1330        regmap_update_bits(rm, WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R_NEW,
1331                                      0x1F, 0x15);
1332        regmap_update_bits(rm, WCD938X_HPH_REFBUFF_UHQA_CTL,
1333                                      0xC0, 0x80);
1334        regmap_update_bits(rm, WCD938X_DIGITAL_CDC_DMIC_CTL,
1335                                      0x02, 0x02);
1336
1337        regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2CASC_ULP,
1338                           0xFF, 0x14);
1339        regmap_update_bits(rm, WCD938X_TX_COM_NEW_INT_TXFE_ICTRL_STG2MAIN_ULP,
1340                           0x1F, 0x08);
1341
1342        regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_0, 0xFF, 0x55);
1343        regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_1, 0xFF, 0x44);
1344        regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_2, 0xFF, 0x11);
1345        regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_3, 0xFF, 0x00);
1346        regmap_update_bits(rm, WCD938X_DIGITAL_TX_REQ_FB_CTL_4, 0xFF, 0x00);
1347
1348        /* Set Noise Filter Resistor value */
1349        regmap_update_bits(rm, WCD938X_MICB1_TEST_CTL_1, 0xE0, 0xE0);
1350        regmap_update_bits(rm, WCD938X_MICB2_TEST_CTL_1, 0xE0, 0xE0);
1351        regmap_update_bits(rm, WCD938X_MICB3_TEST_CTL_1, 0xE0, 0xE0);
1352        regmap_update_bits(rm, WCD938X_MICB4_TEST_CTL_1, 0xE0, 0xE0);
1353
1354        regmap_update_bits(rm, WCD938X_TX_3_4_TEST_BLK_EN2, 0x01, 0x00);
1355        regmap_update_bits(rm, WCD938X_HPH_SURGE_HPHLR_SURGE_EN, 0xC0, 0xC0);
1356
1357        return 0;
1358
1359}
1360
1361static int wcd938x_sdw_connect_port(struct wcd938x_sdw_ch_info *ch_info,
1362                                    struct sdw_port_config *port_config,
1363                                    u32 mstr_port_num,
1364                                    u8 enable)
1365{
1366        u8 ch_mask, port_num;
1367
1368        port_num = ch_info->port_num;
1369        ch_mask = ch_info->ch_mask;
1370
1371        port_config->num = port_num;
1372
1373        if (enable)
1374                port_config->ch_mask |= ch_mask;
1375        else
1376                port_config->ch_mask &= ~ch_mask;
1377
1378        return 0;
1379}
1380
1381static int wcd938x_connect_port(struct wcd938x_sdw_priv *wcd, u8 ch_id, u8 enable)
1382{
1383        u8 port_num, mstr_port_num;
1384
1385        port_num = wcd->ch_info[ch_id].port_num;
1386        mstr_port_num = wcd->port_map[port_num - 1];
1387
1388        return wcd938x_sdw_connect_port(&wcd->ch_info[ch_id],
1389                                        &wcd->port_config[port_num],
1390                                        mstr_port_num,
1391                                        enable);
1392}
1393
1394static int wcd938x_codec_enable_rxclk(struct snd_soc_dapm_widget *w,
1395                                      struct snd_kcontrol *kcontrol,
1396                                      int event)
1397{
1398        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1399
1400        switch (event) {
1401        case SND_SOC_DAPM_PRE_PMU:
1402                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1403                                WCD938X_ANA_RX_CLK_EN_MASK, 1);
1404                snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1405                                WCD938X_RX_BIAS_EN_MASK, 1);
1406                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX0_CTL,
1407                                WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1408                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX1_CTL,
1409                                WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1410                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_RX2_CTL,
1411                                WCD938X_DEM_DITHER_ENABLE_MASK, 0);
1412                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1413                                WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 1);
1414                snd_soc_component_write_field(component, WCD938X_AUX_AUXPA,
1415                                              WCD938X_AUXPA_CLK_EN_MASK, 1);
1416                break;
1417        case SND_SOC_DAPM_POST_PMD:
1418                snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1419                                WCD938X_VNEG_EN_MASK, 0);
1420                snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1421                                WCD938X_VPOS_EN_MASK, 0);
1422                snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1423                                WCD938X_RX_BIAS_EN_MASK, 0);
1424                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1425                                WCD938X_ANA_RX_DIV2_CLK_EN_MASK, 0);
1426                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1427                                WCD938X_ANA_RX_CLK_EN_MASK, 0);
1428                break;
1429        }
1430        return 0;
1431}
1432
1433static int wcd938x_codec_hphl_dac_event(struct snd_soc_dapm_widget *w,
1434                                        struct snd_kcontrol *kcontrol,
1435                                        int event)
1436{
1437        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1438        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1439
1440        switch (event) {
1441        case SND_SOC_DAPM_PRE_PMU:
1442                snd_soc_component_write_field(component,
1443                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1444                                WCD938X_RXD0_CLK_EN_MASK, 0x01);
1445                snd_soc_component_write_field(component,
1446                                WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1447                                WCD938X_HPHL_RX_EN_MASK, 1);
1448                snd_soc_component_write_field(component,
1449                                WCD938X_HPH_RDAC_CLK_CTL1,
1450                                WCD938X_CHOP_CLK_EN_MASK, 0);
1451                break;
1452        case SND_SOC_DAPM_POST_PMU:
1453                snd_soc_component_write_field(component,
1454                                WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_L,
1455                                WCD938X_HPH_RES_DIV_MASK, 0x02);
1456                if (wcd938x->comp1_enable) {
1457                        snd_soc_component_write_field(component,
1458                                WCD938X_DIGITAL_CDC_COMP_CTL_0,
1459                                WCD938X_HPHL_COMP_EN_MASK, 1);
1460                        /* 5msec compander delay as per HW requirement */
1461                        if (!wcd938x->comp2_enable || (snd_soc_component_read(component,
1462                                                         WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x01))
1463                                usleep_range(5000, 5010);
1464                        snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1465                                              WCD938X_AUTOCHOP_TIMER_EN, 0);
1466                } else {
1467                        snd_soc_component_write_field(component,
1468                                        WCD938X_DIGITAL_CDC_COMP_CTL_0,
1469                                        WCD938X_HPHL_COMP_EN_MASK, 0);
1470                        snd_soc_component_write_field(component,
1471                                        WCD938X_HPH_L_EN,
1472                                        WCD938X_GAIN_SRC_SEL_MASK,
1473                                        WCD938X_GAIN_SRC_SEL_REGISTER);
1474
1475                }
1476                break;
1477        case SND_SOC_DAPM_POST_PMD:
1478                snd_soc_component_write_field(component,
1479                        WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1480                        WCD938X_HPH_RES_DIV_MASK, 0x1);
1481                break;
1482        }
1483
1484        return 0;
1485}
1486
1487static int wcd938x_codec_hphr_dac_event(struct snd_soc_dapm_widget *w,
1488                                        struct snd_kcontrol *kcontrol,
1489                                        int event)
1490{
1491        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1492        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1493
1494        switch (event) {
1495        case SND_SOC_DAPM_PRE_PMU:
1496                snd_soc_component_write_field(component,
1497                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1498                                WCD938X_RXD1_CLK_EN_MASK, 1);
1499                snd_soc_component_write_field(component,
1500                                WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1501                                WCD938X_HPHR_RX_EN_MASK, 1);
1502                snd_soc_component_write_field(component,
1503                                WCD938X_HPH_RDAC_CLK_CTL1,
1504                                WCD938X_CHOP_CLK_EN_MASK, 0);
1505                break;
1506        case SND_SOC_DAPM_POST_PMU:
1507                snd_soc_component_write_field(component,
1508                                WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1509                                WCD938X_HPH_RES_DIV_MASK, 0x02);
1510                if (wcd938x->comp2_enable) {
1511                        snd_soc_component_write_field(component,
1512                                WCD938X_DIGITAL_CDC_COMP_CTL_0,
1513                                WCD938X_HPHR_COMP_EN_MASK, 1);
1514                        /* 5msec compander delay as per HW requirement */
1515                        if (!wcd938x->comp1_enable ||
1516                                (snd_soc_component_read(component,
1517                                        WCD938X_DIGITAL_CDC_COMP_CTL_0) & 0x02))
1518                                usleep_range(5000, 5010);
1519                        snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1520                                              WCD938X_AUTOCHOP_TIMER_EN, 0);
1521                } else {
1522                        snd_soc_component_write_field(component,
1523                                        WCD938X_DIGITAL_CDC_COMP_CTL_0,
1524                                        WCD938X_HPHR_COMP_EN_MASK, 0);
1525                        snd_soc_component_write_field(component,
1526                                        WCD938X_HPH_R_EN,
1527                                        WCD938X_GAIN_SRC_SEL_MASK,
1528                                        WCD938X_GAIN_SRC_SEL_REGISTER);
1529                }
1530                break;
1531        case SND_SOC_DAPM_POST_PMD:
1532                snd_soc_component_write_field(component,
1533                        WCD938X_HPH_NEW_INT_RDAC_HD2_CTL_R,
1534                        WCD938X_HPH_RES_DIV_MASK, 0x01);
1535                break;
1536        }
1537
1538        return 0;
1539}
1540
1541static int wcd938x_codec_ear_dac_event(struct snd_soc_dapm_widget *w,
1542                                       struct snd_kcontrol *kcontrol,
1543                                       int event)
1544{
1545        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1546        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1547
1548        switch (event) {
1549        case SND_SOC_DAPM_PRE_PMU:
1550                wcd938x->ear_rx_path =
1551                        snd_soc_component_read(
1552                                component, WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1553                if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1554                        snd_soc_component_write_field(component,
1555                                WCD938X_EAR_EAR_DAC_CON,
1556                                WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 0);
1557                        snd_soc_component_write_field(component,
1558                                WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1559                                WCD938X_AUX_EN_MASK, 1);
1560                        snd_soc_component_write_field(component,
1561                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1562                                WCD938X_RXD2_CLK_EN_MASK, 1);
1563                        snd_soc_component_write_field(component,
1564                                WCD938X_ANA_EAR_COMPANDER_CTL,
1565                                WCD938X_GAIN_OVRD_REG_MASK, 1);
1566                } else {
1567                        snd_soc_component_write_field(component,
1568                                WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1569                                WCD938X_HPHL_RX_EN_MASK, 1);
1570                        snd_soc_component_write_field(component,
1571                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1572                                WCD938X_RXD0_CLK_EN_MASK, 1);
1573                        if (wcd938x->comp1_enable)
1574                                snd_soc_component_write_field(component,
1575                                        WCD938X_DIGITAL_CDC_COMP_CTL_0,
1576                                        WCD938X_HPHL_COMP_EN_MASK, 1);
1577                }
1578                /* 5 msec delay as per HW requirement */
1579                usleep_range(5000, 5010);
1580                if (wcd938x->flyback_cur_det_disable == 0)
1581                        snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1582                                                      WCD938X_EN_CUR_DET_MASK, 0);
1583                wcd938x->flyback_cur_det_disable++;
1584                wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1585                             WCD_CLSH_EVENT_PRE_DAC,
1586                             WCD_CLSH_STATE_EAR,
1587                             wcd938x->hph_mode);
1588                break;
1589        case SND_SOC_DAPM_POST_PMD:
1590                if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX) {
1591                        snd_soc_component_write_field(component,
1592                                WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1593                                WCD938X_AUX_EN_MASK, 0);
1594                        snd_soc_component_write_field(component,
1595                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1596                                WCD938X_RXD2_CLK_EN_MASK, 0);
1597                } else {
1598                        snd_soc_component_write_field(component,
1599                                WCD938X_DIGITAL_CDC_HPH_GAIN_CTL,
1600                                WCD938X_HPHL_RX_EN_MASK, 0);
1601                        snd_soc_component_write_field(component,
1602                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1603                                WCD938X_RXD0_CLK_EN_MASK, 0);
1604                        if (wcd938x->comp1_enable)
1605                                snd_soc_component_write_field(component,
1606                                        WCD938X_DIGITAL_CDC_COMP_CTL_0,
1607                                        WCD938X_HPHL_COMP_EN_MASK, 0);
1608                }
1609                snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1610                                              WCD938X_GAIN_OVRD_REG_MASK, 0);
1611                snd_soc_component_write_field(component,
1612                                WCD938X_EAR_EAR_DAC_CON,
1613                                WCD938X_DAC_SAMPLE_EDGE_SEL_MASK, 1);
1614                break;
1615        }
1616        return 0;
1617
1618}
1619
1620static int wcd938x_codec_aux_dac_event(struct snd_soc_dapm_widget *w,
1621                                       struct snd_kcontrol *kcontrol,
1622                                       int event)
1623{
1624        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1625        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1626        int ret = 0;
1627
1628        switch (event) {
1629        case SND_SOC_DAPM_PRE_PMU:
1630                snd_soc_component_write_field(component,
1631                                WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1632                                WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 1);
1633                snd_soc_component_write_field(component,
1634                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
1635                                WCD938X_RXD2_CLK_EN_MASK, 1);
1636                snd_soc_component_write_field(component,
1637                                WCD938X_DIGITAL_CDC_AUX_GAIN_CTL,
1638                                WCD938X_AUX_EN_MASK, 1);
1639                if (wcd938x->flyback_cur_det_disable == 0)
1640                        snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1641                                                      WCD938X_EN_CUR_DET_MASK, 0);
1642                wcd938x->flyback_cur_det_disable++;
1643                wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1644                             WCD_CLSH_EVENT_PRE_DAC,
1645                             WCD_CLSH_STATE_AUX,
1646                             wcd938x->hph_mode);
1647                break;
1648        case SND_SOC_DAPM_POST_PMD:
1649                snd_soc_component_write_field(component,
1650                                WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
1651                                WCD938X_ANA_RX_DIV4_CLK_EN_MASK, 0);
1652                break;
1653        }
1654        return ret;
1655
1656}
1657
1658static int wcd938x_codec_enable_hphr_pa(struct snd_soc_dapm_widget *w,
1659                                        struct snd_kcontrol *kcontrol, int event)
1660{
1661        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1662        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1663        int hph_mode = wcd938x->hph_mode;
1664
1665        switch (event) {
1666        case SND_SOC_DAPM_PRE_PMU:
1667                if (wcd938x->ldoh)
1668                        snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1669                                                      WCD938X_LDOH_EN_MASK, 1);
1670                wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1671                                        WCD_CLSH_STATE_HPHR, hph_mode);
1672                wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1673
1674                if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1675                    hph_mode == CLS_H_ULP) {
1676                        snd_soc_component_write_field(component,
1677                                WCD938X_HPH_REFBUFF_LP_CTL,
1678                                WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1679                }
1680                snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1681                                              WCD938X_HPHR_REF_EN_MASK, 1);
1682                wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1683                /* 100 usec delay as per HW requirement */
1684                usleep_range(100, 110);
1685                set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1686                snd_soc_component_write_field(component,
1687                                              WCD938X_DIGITAL_PDM_WD_CTL1,
1688                                              WCD938X_PDM_WD_EN_MASK, 0x3);
1689                break;
1690        case SND_SOC_DAPM_POST_PMU:
1691                /*
1692                 * 7ms sleep is required if compander is enabled as per
1693                 * HW requirement. If compander is disabled, then
1694                 * 20ms delay is required.
1695                 */
1696                if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1697                        if (!wcd938x->comp2_enable)
1698                                usleep_range(20000, 20100);
1699                        else
1700                                usleep_range(7000, 7100);
1701
1702                        if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1703                            hph_mode == CLS_H_ULP)
1704                                snd_soc_component_write_field(component,
1705                                                WCD938X_HPH_REFBUFF_LP_CTL,
1706                                                WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1707                        clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1708                }
1709                snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1710                                              WCD938X_AUTOCHOP_TIMER_EN, 1);
1711                if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1712                        hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1713                        snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1714                                        WCD938X_REGULATOR_MODE_MASK,
1715                                        WCD938X_REGULATOR_MODE_CLASS_AB);
1716                enable_irq(wcd938x->hphr_pdm_wd_int);
1717                break;
1718        case SND_SOC_DAPM_PRE_PMD:
1719                disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
1720                /*
1721                 * 7ms sleep is required if compander is enabled as per
1722                 * HW requirement. If compander is disabled, then
1723                 * 20ms delay is required.
1724                 */
1725                if (!wcd938x->comp2_enable)
1726                        usleep_range(20000, 20100);
1727                else
1728                        usleep_range(7000, 7100);
1729                snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1730                                              WCD938X_HPHR_EN_MASK, 0);
1731                set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1732                break;
1733        case SND_SOC_DAPM_POST_PMD:
1734                /*
1735                 * 7ms sleep is required if compander is enabled as per
1736                 * HW requirement. If compander is disabled, then
1737                 * 20ms delay is required.
1738                 */
1739                if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1740                        if (!wcd938x->comp2_enable)
1741                                usleep_range(20000, 20100);
1742                        else
1743                                usleep_range(7000, 7100);
1744                        clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1745                }
1746                snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1747                                              WCD938X_HPHR_REF_EN_MASK, 0);
1748                snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL1,
1749                                              WCD938X_PDM_WD_EN_MASK, 0);
1750                wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1751                                        WCD_CLSH_STATE_HPHR, hph_mode);
1752                if (wcd938x->ldoh)
1753                        snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1754                                                      WCD938X_LDOH_EN_MASK, 0);
1755                break;
1756        }
1757
1758        return 0;
1759}
1760
1761static int wcd938x_codec_enable_hphl_pa(struct snd_soc_dapm_widget *w,
1762                                        struct snd_kcontrol *kcontrol, int event)
1763{
1764        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1765        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1766        int hph_mode = wcd938x->hph_mode;
1767
1768        switch (event) {
1769        case SND_SOC_DAPM_PRE_PMU:
1770                if (wcd938x->ldoh)
1771                        snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1772                                                      WCD938X_LDOH_EN_MASK, 1);
1773                wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_PRE_DAC,
1774                                        WCD_CLSH_STATE_HPHL, hph_mode);
1775                wcd_clsh_set_hph_mode(wcd938x->clsh_info, CLS_H_HIFI);
1776                if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1777                    hph_mode == CLS_H_ULP) {
1778                        snd_soc_component_write_field(component,
1779                                        WCD938X_HPH_REFBUFF_LP_CTL,
1780                                        WCD938X_PREREF_FLIT_BYPASS_MASK, 1);
1781                }
1782                snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1783                                              WCD938X_HPHL_REF_EN_MASK, 1);
1784                wcd_clsh_set_hph_mode(wcd938x->clsh_info, hph_mode);
1785                /* 100 usec delay as per HW requirement */
1786                usleep_range(100, 110);
1787                set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1788                snd_soc_component_write_field(component,
1789                                        WCD938X_DIGITAL_PDM_WD_CTL0,
1790                                        WCD938X_PDM_WD_EN_MASK, 0x3);
1791                break;
1792        case SND_SOC_DAPM_POST_PMU:
1793                /*
1794                 * 7ms sleep is required if compander is enabled as per
1795                 * HW requirement. If compander is disabled, then
1796                 * 20ms delay is required.
1797                 */
1798                if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1799                        if (!wcd938x->comp1_enable)
1800                                usleep_range(20000, 20100);
1801                        else
1802                                usleep_range(7000, 7100);
1803                        if (hph_mode == CLS_H_LP || hph_mode == CLS_H_LOHIFI ||
1804                            hph_mode == CLS_H_ULP)
1805                                snd_soc_component_write_field(component,
1806                                        WCD938X_HPH_REFBUFF_LP_CTL,
1807                                        WCD938X_PREREF_FLIT_BYPASS_MASK, 0);
1808                        clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1809                }
1810
1811                snd_soc_component_write_field(component, WCD938X_HPH_NEW_INT_HPH_TIMER1,
1812                                              WCD938X_AUTOCHOP_TIMER_EN, 1);
1813                if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1814                        hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1815                        snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1816                                        WCD938X_REGULATOR_MODE_MASK,
1817                                        WCD938X_REGULATOR_MODE_CLASS_AB);
1818                enable_irq(wcd938x->hphl_pdm_wd_int);
1819                break;
1820        case SND_SOC_DAPM_PRE_PMD:
1821                disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1822                /*
1823                 * 7ms sleep is required if compander is enabled as per
1824                 * HW requirement. If compander is disabled, then
1825                 * 20ms delay is required.
1826                 */
1827                if (!wcd938x->comp1_enable)
1828                        usleep_range(20000, 20100);
1829                else
1830                        usleep_range(7000, 7100);
1831                snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1832                                              WCD938X_HPHL_EN_MASK, 0);
1833                set_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1834                break;
1835        case SND_SOC_DAPM_POST_PMD:
1836                /*
1837                 * 7ms sleep is required if compander is enabled as per
1838                 * HW requirement. If compander is disabled, then
1839                 * 20ms delay is required.
1840                 */
1841                if (test_bit(HPH_PA_DELAY, &wcd938x->status_mask)) {
1842                        if (!wcd938x->comp1_enable)
1843                                usleep_range(21000, 21100);
1844                        else
1845                                usleep_range(7000, 7100);
1846                        clear_bit(HPH_PA_DELAY, &wcd938x->status_mask);
1847                }
1848                snd_soc_component_write_field(component, WCD938X_ANA_HPH,
1849                                              WCD938X_HPHL_REF_EN_MASK, 0);
1850                snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1851                                              WCD938X_PDM_WD_EN_MASK, 0);
1852                wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1853                                        WCD_CLSH_STATE_HPHL, hph_mode);
1854                if (wcd938x->ldoh)
1855                        snd_soc_component_write_field(component, WCD938X_LDOH_MODE,
1856                                                      WCD938X_LDOH_EN_MASK, 0);
1857                break;
1858        }
1859
1860        return 0;
1861}
1862
1863static int wcd938x_codec_enable_aux_pa(struct snd_soc_dapm_widget *w,
1864                                       struct snd_kcontrol *kcontrol, int event)
1865{
1866        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1867        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1868        int hph_mode = wcd938x->hph_mode;
1869        int ret = 0;
1870
1871        switch (event) {
1872        case SND_SOC_DAPM_PRE_PMU:
1873                snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1874                                              WCD938X_AUX_PDM_WD_EN_MASK, 1);
1875                break;
1876        case SND_SOC_DAPM_POST_PMU:
1877                /* 1 msec delay as per HW requirement */
1878                usleep_range(1000, 1010);
1879                if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1880                        hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1881                        snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1882                                        WCD938X_REGULATOR_MODE_MASK,
1883                                        WCD938X_REGULATOR_MODE_CLASS_AB);
1884                enable_irq(wcd938x->aux_pdm_wd_int);
1885                break;
1886        case SND_SOC_DAPM_PRE_PMD:
1887                disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1888                break;
1889        case SND_SOC_DAPM_POST_PMD:
1890                /* 1 msec delay as per HW requirement */
1891                usleep_range(1000, 1010);
1892                snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1893                                              WCD938X_AUX_PDM_WD_EN_MASK, 0);
1894                wcd_clsh_ctrl_set_state(wcd938x->clsh_info,
1895                             WCD_CLSH_EVENT_POST_PA,
1896                             WCD_CLSH_STATE_AUX,
1897                             hph_mode);
1898
1899                wcd938x->flyback_cur_det_disable--;
1900                if (wcd938x->flyback_cur_det_disable == 0)
1901                        snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1902                                                      WCD938X_EN_CUR_DET_MASK, 1);
1903                break;
1904        }
1905        return ret;
1906}
1907
1908static int wcd938x_codec_enable_ear_pa(struct snd_soc_dapm_widget *w,
1909                                       struct snd_kcontrol *kcontrol, int event)
1910{
1911        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1912        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
1913        int hph_mode = wcd938x->hph_mode;
1914
1915        switch (event) {
1916        case SND_SOC_DAPM_PRE_PMU:
1917                /*
1918                 * Enable watchdog interrupt for HPHL or AUX
1919                 * depending on mux value
1920                 */
1921                wcd938x->ear_rx_path = snd_soc_component_read(component,
1922                                                              WCD938X_DIGITAL_CDC_EAR_PATH_CTL);
1923                if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1924                        snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1925                                              WCD938X_AUX_PDM_WD_EN_MASK, 1);
1926                else
1927                        snd_soc_component_write_field(component,
1928                                                      WCD938X_DIGITAL_PDM_WD_CTL0,
1929                                                      WCD938X_PDM_WD_EN_MASK, 0x3);
1930                if (!wcd938x->comp1_enable)
1931                        snd_soc_component_write_field(component,
1932                                                      WCD938X_ANA_EAR_COMPANDER_CTL,
1933                                                      WCD938X_GAIN_OVRD_REG_MASK, 1);
1934
1935                break;
1936        case SND_SOC_DAPM_POST_PMU:
1937                /* 6 msec delay as per HW requirement */
1938                usleep_range(6000, 6010);
1939                if (hph_mode == CLS_AB || hph_mode == CLS_AB_HIFI ||
1940                        hph_mode == CLS_AB_LP || hph_mode == CLS_AB_LOHIFI)
1941                        snd_soc_component_write_field(component, WCD938X_ANA_RX_SUPPLIES,
1942                                        WCD938X_REGULATOR_MODE_MASK,
1943                                        WCD938X_REGULATOR_MODE_CLASS_AB);
1944                if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1945                        enable_irq(wcd938x->aux_pdm_wd_int);
1946                else
1947                        enable_irq(wcd938x->hphl_pdm_wd_int);
1948                break;
1949        case SND_SOC_DAPM_PRE_PMD:
1950                if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1951                        disable_irq_nosync(wcd938x->aux_pdm_wd_int);
1952                else
1953                        disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
1954                break;
1955        case SND_SOC_DAPM_POST_PMD:
1956                if (!wcd938x->comp1_enable)
1957                        snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
1958                                                      WCD938X_GAIN_OVRD_REG_MASK, 0);
1959                /* 7 msec delay as per HW requirement */
1960                usleep_range(7000, 7010);
1961                if (wcd938x->ear_rx_path & EAR_RX_PATH_AUX)
1962                        snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL2,
1963                                              WCD938X_AUX_PDM_WD_EN_MASK, 0);
1964                else
1965                        snd_soc_component_write_field(component, WCD938X_DIGITAL_PDM_WD_CTL0,
1966                                        WCD938X_PDM_WD_EN_MASK, 0);
1967
1968                wcd_clsh_ctrl_set_state(wcd938x->clsh_info, WCD_CLSH_EVENT_POST_PA,
1969                                        WCD_CLSH_STATE_EAR, hph_mode);
1970
1971                wcd938x->flyback_cur_det_disable--;
1972                if (wcd938x->flyback_cur_det_disable == 0)
1973                        snd_soc_component_write_field(component, WCD938X_FLYBACK_EN,
1974                                                      WCD938X_EN_CUR_DET_MASK, 1);
1975                break;
1976        }
1977
1978        return 0;
1979}
1980
1981static int wcd938x_codec_enable_dmic(struct snd_soc_dapm_widget *w,
1982                                     struct snd_kcontrol *kcontrol,
1983                                     int event)
1984{
1985        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
1986        u16 dmic_clk_reg, dmic_clk_en_reg;
1987        u8 dmic_sel_mask, dmic_clk_mask;
1988
1989        switch (w->shift) {
1990        case 0:
1991        case 1:
1992                dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
1993                dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC1_CTL;
1994                dmic_clk_mask = WCD938X_DMIC1_RATE_MASK;
1995                dmic_sel_mask = WCD938X_AMIC1_IN_SEL_MASK;
1996                break;
1997        case 2:
1998        case 3:
1999                dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_1_2;
2000                dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC2_CTL;
2001                dmic_clk_mask = WCD938X_DMIC2_RATE_MASK;
2002                dmic_sel_mask = WCD938X_AMIC3_IN_SEL_MASK;
2003                break;
2004        case 4:
2005        case 5:
2006                dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2007                dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC3_CTL;
2008                dmic_clk_mask = WCD938X_DMIC3_RATE_MASK;
2009                dmic_sel_mask = WCD938X_AMIC4_IN_SEL_MASK;
2010                break;
2011        case 6:
2012        case 7:
2013                dmic_clk_reg = WCD938X_DIGITAL_CDC_DMIC_RATE_3_4;
2014                dmic_clk_en_reg = WCD938X_DIGITAL_CDC_DMIC4_CTL;
2015                dmic_clk_mask = WCD938X_DMIC4_RATE_MASK;
2016                dmic_sel_mask = WCD938X_AMIC5_IN_SEL_MASK;
2017                break;
2018        default:
2019                dev_err(component->dev, "%s: Invalid DMIC Selection\n",
2020                        __func__);
2021                return -EINVAL;
2022        }
2023
2024        switch (event) {
2025        case SND_SOC_DAPM_PRE_PMU:
2026                snd_soc_component_write_field(component,
2027                                WCD938X_DIGITAL_CDC_AMIC_CTL,
2028                                dmic_sel_mask,
2029                                WCD938X_AMIC1_IN_SEL_DMIC);
2030                /* 250us sleep as per HW requirement */
2031                usleep_range(250, 260);
2032                /* Setting DMIC clock rate to 2.4MHz */
2033                snd_soc_component_write_field(component, dmic_clk_reg,
2034                                              dmic_clk_mask,
2035                                              WCD938X_DMIC4_RATE_2P4MHZ);
2036                snd_soc_component_write_field(component, dmic_clk_en_reg,
2037                                              WCD938X_DMIC_CLK_EN_MASK, 1);
2038                /* enable clock scaling */
2039                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_DMIC_CTL,
2040                                              WCD938X_DMIC_CLK_SCALING_EN_MASK, 0x3);
2041                break;
2042        case SND_SOC_DAPM_POST_PMD:
2043                snd_soc_component_write_field(component,
2044                                WCD938X_DIGITAL_CDC_AMIC_CTL,
2045                                dmic_sel_mask, WCD938X_AMIC1_IN_SEL_AMIC);
2046                snd_soc_component_write_field(component, dmic_clk_en_reg,
2047                                              WCD938X_DMIC_CLK_EN_MASK, 0);
2048                break;
2049        }
2050        return 0;
2051}
2052
2053static int wcd938x_tx_swr_ctrl(struct snd_soc_dapm_widget *w,
2054                               struct snd_kcontrol *kcontrol, int event)
2055{
2056        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2057        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2058        int bank;
2059        int rate;
2060
2061        bank = (wcd938x_swr_get_current_bank(wcd938x->sdw_priv[AIF1_CAP]->sdev)) ? 0 : 1;
2062        bank = bank ? 0 : 1;
2063
2064        switch (event) {
2065        case SND_SOC_DAPM_PRE_PMU:
2066                if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2067                        int i = 0, mode = 0;
2068
2069                        if (test_bit(WCD_ADC1, &wcd938x->status_mask))
2070                                mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC1]];
2071                        if (test_bit(WCD_ADC2, &wcd938x->status_mask))
2072                                mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC2]];
2073                        if (test_bit(WCD_ADC3, &wcd938x->status_mask))
2074                                mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC3]];
2075                        if (test_bit(WCD_ADC4, &wcd938x->status_mask))
2076                                mode |= tx_mode_bit[wcd938x->tx_mode[WCD_ADC4]];
2077
2078                        if (mode != 0) {
2079                                for (i = 0; i < ADC_MODE_ULP2; i++) {
2080                                        if (mode & (1 << i)) {
2081                                                i++;
2082                                                break;
2083                                        }
2084                                }
2085                        }
2086                        rate = wcd938x_get_clk_rate(i);
2087                        wcd938x_set_swr_clk_rate(component, rate, bank);
2088                        /* Copy clk settings to active bank */
2089                        wcd938x_set_swr_clk_rate(component, rate, !bank);
2090                }
2091                break;
2092        case SND_SOC_DAPM_POST_PMD:
2093                if (strnstr(w->name, "ADC", sizeof("ADC"))) {
2094                        rate = wcd938x_get_clk_rate(ADC_MODE_INVALID);
2095                        wcd938x_set_swr_clk_rate(component, rate, !bank);
2096                        wcd938x_set_swr_clk_rate(component, rate, bank);
2097                }
2098                break;
2099        }
2100
2101        return 0;
2102}
2103
2104static int wcd938x_get_adc_mode(int val)
2105{
2106        int ret = 0;
2107
2108        switch (val) {
2109        case ADC_MODE_INVALID:
2110                ret = ADC_MODE_VAL_NORMAL;
2111                break;
2112        case ADC_MODE_HIFI:
2113                ret = ADC_MODE_VAL_HIFI;
2114                break;
2115        case ADC_MODE_LO_HIF:
2116                ret = ADC_MODE_VAL_LO_HIF;
2117                break;
2118        case ADC_MODE_NORMAL:
2119                ret = ADC_MODE_VAL_NORMAL;
2120                break;
2121        case ADC_MODE_LP:
2122                ret = ADC_MODE_VAL_LP;
2123                break;
2124        case ADC_MODE_ULP1:
2125                ret = ADC_MODE_VAL_ULP1;
2126                break;
2127        case ADC_MODE_ULP2:
2128                ret = ADC_MODE_VAL_ULP2;
2129                break;
2130        default:
2131                ret = -EINVAL;
2132                break;
2133        }
2134        return ret;
2135}
2136
2137static int wcd938x_codec_enable_adc(struct snd_soc_dapm_widget *w,
2138                                    struct snd_kcontrol *kcontrol, int event)
2139{
2140        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2141        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2142
2143        switch (event) {
2144        case SND_SOC_DAPM_PRE_PMU:
2145                snd_soc_component_write_field(component,
2146                                              WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2147                                              WCD938X_ANA_TX_CLK_EN_MASK, 1);
2148                snd_soc_component_write_field(component,
2149                                              WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2150                                              WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2151                set_bit(w->shift, &wcd938x->status_mask);
2152                break;
2153        case SND_SOC_DAPM_POST_PMD:
2154                snd_soc_component_write_field(component, WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2155                                              WCD938X_ANA_TX_CLK_EN_MASK, 0);
2156                clear_bit(w->shift, &wcd938x->status_mask);
2157                break;
2158        }
2159
2160        return 0;
2161}
2162
2163static void wcd938x_tx_channel_config(struct snd_soc_component *component,
2164                                     int channel, int mode)
2165{
2166        int reg, mask;
2167
2168        switch (channel) {
2169        case 0:
2170                reg = WCD938X_ANA_TX_CH2;
2171                mask = WCD938X_HPF1_INIT_MASK;
2172                break;
2173        case 1:
2174                reg = WCD938X_ANA_TX_CH2;
2175                mask = WCD938X_HPF2_INIT_MASK;
2176                break;
2177        case 2:
2178                reg = WCD938X_ANA_TX_CH4;
2179                mask = WCD938X_HPF3_INIT_MASK;
2180                break;
2181        case 3:
2182                reg = WCD938X_ANA_TX_CH4;
2183                mask = WCD938X_HPF4_INIT_MASK;
2184                break;
2185        default:
2186                return;
2187        }
2188
2189        snd_soc_component_write_field(component, reg, mask, mode);
2190}
2191
2192static int wcd938x_adc_enable_req(struct snd_soc_dapm_widget *w,
2193                                  struct snd_kcontrol *kcontrol, int event)
2194{
2195        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2196        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2197        int mode;
2198
2199        switch (event) {
2200        case SND_SOC_DAPM_PRE_PMU:
2201                snd_soc_component_write_field(component,
2202                                WCD938X_DIGITAL_CDC_REQ_CTL,
2203                                WCD938X_FS_RATE_4P8_MASK, 1);
2204                snd_soc_component_write_field(component,
2205                                WCD938X_DIGITAL_CDC_REQ_CTL,
2206                                WCD938X_NO_NOTCH_MASK, 0);
2207                wcd938x_tx_channel_config(component, w->shift, 1);
2208                mode = wcd938x_get_adc_mode(wcd938x->tx_mode[w->shift]);
2209                if (mode < 0) {
2210                        dev_info(component->dev, "Invalid ADC mode\n");
2211                        return -EINVAL;
2212                }
2213                switch (w->shift) {
2214                case 0:
2215                        snd_soc_component_write_field(component,
2216                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2217                                WCD938X_TXD0_MODE_MASK, mode);
2218                        snd_soc_component_write_field(component,
2219                                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2220                                                WCD938X_TXD0_CLK_EN_MASK, 1);
2221                        break;
2222                case 1:
2223                        snd_soc_component_write_field(component,
2224                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2225                                WCD938X_TXD1_MODE_MASK, mode);
2226                        snd_soc_component_write_field(component,
2227                                              WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2228                                              WCD938X_TXD1_CLK_EN_MASK, 1);
2229                        break;
2230                case 2:
2231                        snd_soc_component_write_field(component,
2232                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2233                                WCD938X_TXD2_MODE_MASK, mode);
2234                        snd_soc_component_write_field(component,
2235                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2236                                WCD938X_TXD2_CLK_EN_MASK, 1);
2237                        break;
2238                case 3:
2239                        snd_soc_component_write_field(component,
2240                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2241                                WCD938X_TXD3_MODE_MASK, mode);
2242                        snd_soc_component_write_field(component,
2243                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2244                                WCD938X_TXD3_CLK_EN_MASK, 1);
2245                        break;
2246                default:
2247                        break;
2248                }
2249
2250                wcd938x_tx_channel_config(component, w->shift, 0);
2251                break;
2252        case SND_SOC_DAPM_POST_PMD:
2253                switch (w->shift) {
2254                case 0:
2255                        snd_soc_component_write_field(component,
2256                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2257                                WCD938X_TXD0_MODE_MASK, 0);
2258                        snd_soc_component_write_field(component,
2259                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2260                                WCD938X_TXD0_CLK_EN_MASK, 0);
2261                        break;
2262                case 1:
2263                        snd_soc_component_write_field(component,
2264                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_0_1,
2265                                WCD938X_TXD1_MODE_MASK, 0);
2266                        snd_soc_component_write_field(component,
2267                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2268                                WCD938X_TXD1_CLK_EN_MASK, 0);
2269                        break;
2270                case 2:
2271                        snd_soc_component_write_field(component,
2272                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2273                                WCD938X_TXD2_MODE_MASK, 0);
2274                        snd_soc_component_write_field(component,
2275                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2276                                WCD938X_TXD2_CLK_EN_MASK, 0);
2277                        break;
2278                case 3:
2279                        snd_soc_component_write_field(component,
2280                                WCD938X_DIGITAL_CDC_TX_ANA_MODE_2_3,
2281                                WCD938X_TXD3_MODE_MASK, 0);
2282                        snd_soc_component_write_field(component,
2283                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2284                                WCD938X_TXD3_CLK_EN_MASK, 0);
2285                        break;
2286                default:
2287                        break;
2288                }
2289                snd_soc_component_write_field(component,
2290                                WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2291                                WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 0);
2292                break;
2293        }
2294
2295        return 0;
2296}
2297
2298static int wcd938x_micbias_control(struct snd_soc_component *component,
2299                                   int micb_num, int req, bool is_dapm)
2300{
2301        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2302        int micb_index = micb_num - 1;
2303        u16 micb_reg;
2304
2305        switch (micb_num) {
2306        case MIC_BIAS_1:
2307                micb_reg = WCD938X_ANA_MICB1;
2308                break;
2309        case MIC_BIAS_2:
2310                micb_reg = WCD938X_ANA_MICB2;
2311                break;
2312        case MIC_BIAS_3:
2313                micb_reg = WCD938X_ANA_MICB3;
2314                break;
2315        case MIC_BIAS_4:
2316                micb_reg = WCD938X_ANA_MICB4;
2317                break;
2318        default:
2319                dev_err(component->dev, "%s: Invalid micbias number: %d\n",
2320                        __func__, micb_num);
2321                return -EINVAL;
2322        }
2323
2324        switch (req) {
2325        case MICB_PULLUP_ENABLE:
2326                wcd938x->pullup_ref[micb_index]++;
2327                if ((wcd938x->pullup_ref[micb_index] == 1) &&
2328                    (wcd938x->micb_ref[micb_index] == 0))
2329                        snd_soc_component_write_field(component, micb_reg,
2330                                                      WCD938X_MICB_EN_MASK,
2331                                                      WCD938X_MICB_PULL_UP);
2332                break;
2333        case MICB_PULLUP_DISABLE:
2334                if (wcd938x->pullup_ref[micb_index] > 0)
2335                        wcd938x->pullup_ref[micb_index]--;
2336
2337                if ((wcd938x->pullup_ref[micb_index] == 0) &&
2338                    (wcd938x->micb_ref[micb_index] == 0))
2339                        snd_soc_component_write_field(component, micb_reg,
2340                                                      WCD938X_MICB_EN_MASK, 0);
2341                break;
2342        case MICB_ENABLE:
2343                wcd938x->micb_ref[micb_index]++;
2344                if (wcd938x->micb_ref[micb_index] == 1) {
2345                        snd_soc_component_write_field(component,
2346                                WCD938X_DIGITAL_CDC_DIG_CLK_CTL,
2347                                WCD938X_TX_CLK_EN_MASK, 0xF);
2348                        snd_soc_component_write_field(component,
2349                                WCD938X_DIGITAL_CDC_ANA_CLK_CTL,
2350                                WCD938X_ANA_TX_DIV2_CLK_EN_MASK, 1);
2351                        snd_soc_component_write_field(component,
2352                               WCD938X_DIGITAL_CDC_ANA_TX_CLK_CTL,
2353                               WCD938X_TX_SC_CLK_EN_MASK, 1);
2354
2355                        snd_soc_component_write_field(component, micb_reg,
2356                                                      WCD938X_MICB_EN_MASK,
2357                                                      WCD938X_MICB_ENABLE);
2358                }
2359
2360                break;
2361        case MICB_DISABLE:
2362                if (wcd938x->micb_ref[micb_index] > 0)
2363                        wcd938x->micb_ref[micb_index]--;
2364
2365                if ((wcd938x->micb_ref[micb_index] == 0) &&
2366                    (wcd938x->pullup_ref[micb_index] > 0))
2367                        snd_soc_component_write_field(component, micb_reg,
2368                                                      WCD938X_MICB_EN_MASK,
2369                                                      WCD938X_MICB_PULL_UP);
2370                else if ((wcd938x->micb_ref[micb_index] == 0) &&
2371                         (wcd938x->pullup_ref[micb_index] == 0)) {
2372
2373                        snd_soc_component_write_field(component, micb_reg,
2374                                                      WCD938X_MICB_EN_MASK, 0);
2375                }
2376                break;
2377        }
2378
2379        return 0;
2380}
2381
2382static int wcd938x_codec_enable_micbias(struct snd_soc_dapm_widget *w,
2383                                        struct snd_kcontrol *kcontrol,
2384                                        int event)
2385{
2386        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2387        int micb_num = w->shift;
2388
2389        switch (event) {
2390        case SND_SOC_DAPM_PRE_PMU:
2391                wcd938x_micbias_control(component, micb_num, MICB_ENABLE, true);
2392                break;
2393        case SND_SOC_DAPM_POST_PMU:
2394                /* 1 msec delay as per HW requirement */
2395                usleep_range(1000, 1100);
2396                break;
2397        case SND_SOC_DAPM_POST_PMD:
2398                wcd938x_micbias_control(component, micb_num, MICB_DISABLE, true);
2399                break;
2400        }
2401
2402        return 0;
2403}
2404
2405static int wcd938x_codec_enable_micbias_pullup(struct snd_soc_dapm_widget *w,
2406                                               struct snd_kcontrol *kcontrol,
2407                                               int event)
2408{
2409        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
2410        int micb_num = w->shift;
2411
2412        switch (event) {
2413        case SND_SOC_DAPM_PRE_PMU:
2414                wcd938x_micbias_control(component, micb_num,
2415                                        MICB_PULLUP_ENABLE, true);
2416                break;
2417        case SND_SOC_DAPM_POST_PMU:
2418                /* 1 msec delay as per HW requirement */
2419                usleep_range(1000, 1100);
2420                break;
2421        case SND_SOC_DAPM_POST_PMD:
2422                wcd938x_micbias_control(component, micb_num,
2423                                        MICB_PULLUP_DISABLE, true);
2424                break;
2425        }
2426
2427        return 0;
2428}
2429
2430static int wcd938x_tx_mode_get(struct snd_kcontrol *kcontrol,
2431                               struct snd_ctl_elem_value *ucontrol)
2432{
2433        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2434        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2435        struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2436        int path = e->shift_l;
2437
2438        ucontrol->value.integer.value[0] = wcd938x->tx_mode[path];
2439
2440        return 0;
2441}
2442
2443static int wcd938x_tx_mode_put(struct snd_kcontrol *kcontrol,
2444                               struct snd_ctl_elem_value *ucontrol)
2445{
2446        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2447        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2448        struct soc_enum *e = (struct soc_enum *)kcontrol->private_value;
2449        int path = e->shift_l;
2450
2451        wcd938x->tx_mode[path] = ucontrol->value.enumerated.item[0];
2452
2453        return 1;
2454}
2455
2456static int wcd938x_rx_hph_mode_get(struct snd_kcontrol *kcontrol,
2457                                 struct snd_ctl_elem_value *ucontrol)
2458{
2459        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2460        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2461
2462        ucontrol->value.integer.value[0] = wcd938x->hph_mode;
2463
2464        return 0;
2465}
2466
2467static int wcd938x_rx_hph_mode_put(struct snd_kcontrol *kcontrol,
2468                                   struct snd_ctl_elem_value *ucontrol)
2469{
2470        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2471        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2472
2473        wcd938x->hph_mode = ucontrol->value.enumerated.item[0];
2474
2475        return 1;
2476}
2477
2478static int wcd938x_ear_pa_put_gain(struct snd_kcontrol *kcontrol,
2479                                   struct snd_ctl_elem_value *ucontrol)
2480{
2481        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2482        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2483
2484        if (wcd938x->comp1_enable) {
2485                dev_err(component->dev, "Can not set EAR PA Gain, compander1 is enabled\n");
2486                return -EINVAL;
2487        }
2488
2489        snd_soc_component_write_field(component, WCD938X_ANA_EAR_COMPANDER_CTL,
2490                                      WCD938X_EAR_GAIN_MASK,
2491                                      ucontrol->value.integer.value[0]);
2492
2493        return 0;
2494}
2495
2496static int wcd938x_get_compander(struct snd_kcontrol *kcontrol,
2497                                 struct snd_ctl_elem_value *ucontrol)
2498{
2499
2500        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2501        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2502        struct soc_mixer_control *mc;
2503        bool hphr;
2504
2505        mc = (struct soc_mixer_control *)(kcontrol->private_value);
2506        hphr = mc->shift;
2507
2508        if (hphr)
2509                ucontrol->value.integer.value[0] = wcd938x->comp2_enable;
2510        else
2511                ucontrol->value.integer.value[0] = wcd938x->comp1_enable;
2512
2513        return 0;
2514}
2515
2516static int wcd938x_set_compander(struct snd_kcontrol *kcontrol,
2517                                 struct snd_ctl_elem_value *ucontrol)
2518{
2519        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2520        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2521        struct wcd938x_sdw_priv *wcd;
2522        int value = ucontrol->value.integer.value[0];
2523        struct soc_mixer_control *mc;
2524        bool hphr;
2525
2526        mc = (struct soc_mixer_control *)(kcontrol->private_value);
2527        hphr = mc->shift;
2528
2529        wcd = wcd938x->sdw_priv[AIF1_PB];
2530
2531        if (hphr)
2532                wcd938x->comp2_enable = value;
2533        else
2534                wcd938x->comp1_enable = value;
2535
2536        if (value)
2537                wcd938x_connect_port(wcd, mc->reg, true);
2538        else
2539                wcd938x_connect_port(wcd, mc->reg, false);
2540
2541        return 0;
2542}
2543
2544static int wcd938x_ldoh_get(struct snd_kcontrol *kcontrol,
2545                            struct snd_ctl_elem_value *ucontrol)
2546{
2547        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2548        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2549
2550        ucontrol->value.integer.value[0] = wcd938x->ldoh;
2551
2552        return 0;
2553}
2554
2555static int wcd938x_ldoh_put(struct snd_kcontrol *kcontrol,
2556                            struct snd_ctl_elem_value *ucontrol)
2557{
2558        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2559        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2560
2561        wcd938x->ldoh = ucontrol->value.integer.value[0];
2562
2563        return 1;
2564}
2565
2566static int wcd938x_bcs_get(struct snd_kcontrol *kcontrol,
2567                           struct snd_ctl_elem_value *ucontrol)
2568{
2569        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2570        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2571
2572        ucontrol->value.integer.value[0] = wcd938x->bcs_dis;
2573
2574        return 0;
2575}
2576
2577static int wcd938x_bcs_put(struct snd_kcontrol *kcontrol,
2578                           struct snd_ctl_elem_value *ucontrol)
2579{
2580        struct snd_soc_component *component = snd_soc_kcontrol_component(kcontrol);
2581        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
2582
2583        wcd938x->bcs_dis = ucontrol->value.integer.value[0];
2584
2585        return 1;
2586}
2587
2588static const char * const tx_mode_mux_text_wcd9380[] = {
2589        "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2590};
2591
2592static const char * const tx_mode_mux_text[] = {
2593        "ADC_INVALID", "ADC_HIFI", "ADC_LO_HIF", "ADC_NORMAL", "ADC_LP",
2594        "ADC_ULP1", "ADC_ULP2",
2595};
2596
2597static const char * const rx_hph_mode_mux_text_wcd9380[] = {
2598        "CLS_H_INVALID", "CLS_H_INVALID_1", "CLS_H_LP", "CLS_AB",
2599        "CLS_H_LOHIFI", "CLS_H_ULP", "CLS_H_INVALID_2", "CLS_AB_LP",
2600        "CLS_AB_LOHIFI",
2601};
2602
2603static const char * const rx_hph_mode_mux_text[] = {
2604        "CLS_H_INVALID", "CLS_H_HIFI", "CLS_H_LP", "CLS_AB", "CLS_H_LOHIFI",
2605        "CLS_H_ULP", "CLS_AB_HIFI", "CLS_AB_LP", "CLS_AB_LOHIFI",
2606};
2607
2608static const char * const adc2_mux_text[] = {
2609        "INP2", "INP3"
2610};
2611
2612static const char * const adc3_mux_text[] = {
2613        "INP4", "INP6"
2614};
2615
2616static const char * const adc4_mux_text[] = {
2617        "INP5", "INP7"
2618};
2619
2620static const char * const rdac3_mux_text[] = {
2621        "RX1", "RX3"
2622};
2623
2624static const char * const hdr12_mux_text[] = {
2625        "NO_HDR12", "HDR12"
2626};
2627
2628static const char * const hdr34_mux_text[] = {
2629        "NO_HDR34", "HDR34"
2630};
2631
2632static const struct soc_enum tx0_mode_enum_wcd9380 =
2633        SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2634                        tx_mode_mux_text_wcd9380);
2635
2636static const struct soc_enum tx1_mode_enum_wcd9380 =
2637        SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2638                        tx_mode_mux_text_wcd9380);
2639
2640static const struct soc_enum tx2_mode_enum_wcd9380 =
2641        SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2642                        tx_mode_mux_text_wcd9380);
2643
2644static const struct soc_enum tx3_mode_enum_wcd9380 =
2645        SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text_wcd9380),
2646                        tx_mode_mux_text_wcd9380);
2647
2648static const struct soc_enum tx0_mode_enum_wcd9385 =
2649        SOC_ENUM_SINGLE(SND_SOC_NOPM, 0, ARRAY_SIZE(tx_mode_mux_text),
2650                        tx_mode_mux_text);
2651
2652static const struct soc_enum tx1_mode_enum_wcd9385 =
2653        SOC_ENUM_SINGLE(SND_SOC_NOPM, 1, ARRAY_SIZE(tx_mode_mux_text),
2654                        tx_mode_mux_text);
2655
2656static const struct soc_enum tx2_mode_enum_wcd9385 =
2657        SOC_ENUM_SINGLE(SND_SOC_NOPM, 2, ARRAY_SIZE(tx_mode_mux_text),
2658                        tx_mode_mux_text);
2659
2660static const struct soc_enum tx3_mode_enum_wcd9385 =
2661        SOC_ENUM_SINGLE(SND_SOC_NOPM, 3, ARRAY_SIZE(tx_mode_mux_text),
2662                        tx_mode_mux_text);
2663
2664static const struct soc_enum rx_hph_mode_mux_enum_wcd9380 =
2665                SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text_wcd9380),
2666                                    rx_hph_mode_mux_text_wcd9380);
2667
2668static const struct soc_enum rx_hph_mode_mux_enum =
2669                SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(rx_hph_mode_mux_text),
2670                                    rx_hph_mode_mux_text);
2671
2672static const struct soc_enum adc2_enum =
2673                SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 7,
2674                                ARRAY_SIZE(adc2_mux_text), adc2_mux_text);
2675
2676static const struct soc_enum adc3_enum =
2677                SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 6,
2678                                ARRAY_SIZE(adc3_mux_text), adc3_mux_text);
2679
2680static const struct soc_enum adc4_enum =
2681                SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 5,
2682                                ARRAY_SIZE(adc4_mux_text), adc4_mux_text);
2683
2684static const struct soc_enum hdr12_enum =
2685                SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 4,
2686                                ARRAY_SIZE(hdr12_mux_text), hdr12_mux_text);
2687
2688static const struct soc_enum hdr34_enum =
2689                SOC_ENUM_SINGLE(WCD938X_TX_NEW_AMIC_MUX_CFG, 3,
2690                                ARRAY_SIZE(hdr34_mux_text), hdr34_mux_text);
2691
2692static const struct soc_enum rdac3_enum =
2693                SOC_ENUM_SINGLE(WCD938X_DIGITAL_CDC_EAR_PATH_CTL, 0,
2694                                ARRAY_SIZE(rdac3_mux_text), rdac3_mux_text);
2695
2696static const struct snd_kcontrol_new adc1_switch[] = {
2697        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2698};
2699
2700static const struct snd_kcontrol_new adc2_switch[] = {
2701        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2702};
2703
2704static const struct snd_kcontrol_new adc3_switch[] = {
2705        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2706};
2707
2708static const struct snd_kcontrol_new adc4_switch[] = {
2709        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2710};
2711
2712static const struct snd_kcontrol_new dmic1_switch[] = {
2713        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2714};
2715
2716static const struct snd_kcontrol_new dmic2_switch[] = {
2717        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2718};
2719
2720static const struct snd_kcontrol_new dmic3_switch[] = {
2721        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2722};
2723
2724static const struct snd_kcontrol_new dmic4_switch[] = {
2725        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2726};
2727
2728static const struct snd_kcontrol_new dmic5_switch[] = {
2729        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2730};
2731
2732static const struct snd_kcontrol_new dmic6_switch[] = {
2733        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2734};
2735
2736static const struct snd_kcontrol_new dmic7_switch[] = {
2737        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2738};
2739
2740static const struct snd_kcontrol_new dmic8_switch[] = {
2741        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2742};
2743
2744static const struct snd_kcontrol_new ear_rdac_switch[] = {
2745        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2746};
2747
2748static const struct snd_kcontrol_new aux_rdac_switch[] = {
2749        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2750};
2751
2752static const struct snd_kcontrol_new hphl_rdac_switch[] = {
2753        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2754};
2755
2756static const struct snd_kcontrol_new hphr_rdac_switch[] = {
2757        SOC_DAPM_SINGLE("Switch", SND_SOC_NOPM, 0, 1, 0)
2758};
2759
2760static const struct snd_kcontrol_new tx_adc2_mux =
2761        SOC_DAPM_ENUM("ADC2 MUX Mux", adc2_enum);
2762
2763static const struct snd_kcontrol_new tx_adc3_mux =
2764        SOC_DAPM_ENUM("ADC3 MUX Mux", adc3_enum);
2765
2766static const struct snd_kcontrol_new tx_adc4_mux =
2767        SOC_DAPM_ENUM("ADC4 MUX Mux", adc4_enum);
2768
2769static const struct snd_kcontrol_new tx_hdr12_mux =
2770        SOC_DAPM_ENUM("HDR12 MUX Mux", hdr12_enum);
2771
2772static const struct snd_kcontrol_new tx_hdr34_mux =
2773        SOC_DAPM_ENUM("HDR34 MUX Mux", hdr34_enum);
2774
2775static const struct snd_kcontrol_new rx_rdac3_mux =
2776        SOC_DAPM_ENUM("RDAC3_MUX Mux", rdac3_enum);
2777
2778static const struct snd_kcontrol_new wcd9380_snd_controls[] = {
2779        SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum_wcd9380,
2780                     wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2781        SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9380,
2782                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2783        SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9380,
2784                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2785        SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9380,
2786                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2787        SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9380,
2788                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2789};
2790
2791static const struct snd_kcontrol_new wcd9385_snd_controls[] = {
2792        SOC_ENUM_EXT("RX HPH Mode", rx_hph_mode_mux_enum,
2793                     wcd938x_rx_hph_mode_get, wcd938x_rx_hph_mode_put),
2794        SOC_ENUM_EXT("TX0 MODE", tx0_mode_enum_wcd9385,
2795                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2796        SOC_ENUM_EXT("TX1 MODE", tx1_mode_enum_wcd9385,
2797                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2798        SOC_ENUM_EXT("TX2 MODE", tx2_mode_enum_wcd9385,
2799                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2800        SOC_ENUM_EXT("TX3 MODE", tx3_mode_enum_wcd9385,
2801                     wcd938x_tx_mode_get, wcd938x_tx_mode_put),
2802};
2803
2804static int wcd938x_get_swr_port(struct snd_kcontrol *kcontrol,
2805                            struct snd_ctl_elem_value *ucontrol)
2806{
2807        struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2808        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2809        struct wcd938x_sdw_priv *wcd;
2810        struct soc_mixer_control *mixer = (struct soc_mixer_control *)kcontrol->private_value;
2811        int dai_id = mixer->shift;
2812        int portidx = mixer->reg;
2813
2814        wcd = wcd938x->sdw_priv[dai_id];
2815
2816        ucontrol->value.integer.value[0] = wcd->port_enable[portidx];
2817
2818        return 0;
2819}
2820
2821static int wcd938x_set_swr_port(struct snd_kcontrol *kcontrol,
2822                            struct snd_ctl_elem_value *ucontrol)
2823{
2824        struct snd_soc_component *comp = snd_soc_kcontrol_component(kcontrol);
2825        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(comp);
2826        struct wcd938x_sdw_priv *wcd;
2827        struct soc_mixer_control *mixer =
2828                (struct soc_mixer_control *)kcontrol->private_value;
2829        int portidx = mixer->reg;
2830        int dai_id = mixer->shift;
2831        bool enable;
2832
2833        wcd = wcd938x->sdw_priv[dai_id];
2834
2835        if (ucontrol->value.integer.value[0])
2836                enable = true;
2837        else
2838                enable = false;
2839
2840        wcd->port_enable[portidx] = enable;
2841
2842        wcd938x_connect_port(wcd, portidx, enable);
2843
2844        return 0;
2845
2846}
2847
2848static const struct snd_kcontrol_new wcd938x_snd_controls[] = {
2849        SOC_SINGLE_EXT("HPHL_COMP Switch", WCD938X_COMP_L, 0, 1, 0,
2850                       wcd938x_get_compander, wcd938x_set_compander),
2851        SOC_SINGLE_EXT("HPHR_COMP Switch", WCD938X_COMP_R, 1, 1, 0,
2852                       wcd938x_get_compander, wcd938x_set_compander),
2853        SOC_SINGLE_EXT("HPHL Switch", WCD938X_HPH_L, 0, 1, 0,
2854                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2855        SOC_SINGLE_EXT("HPHR Switch", WCD938X_HPH_R, 0, 1, 0,
2856                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2857        SOC_SINGLE_EXT("CLSH Switch", WCD938X_CLSH, 0, 1, 0,
2858                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2859        SOC_SINGLE_EXT("LO Switch", WCD938X_LO, 0, 1, 0,
2860                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2861        SOC_SINGLE_EXT("DSD_L Switch", WCD938X_DSD_L, 0, 1, 0,
2862                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2863        SOC_SINGLE_EXT("DSD_R Switch", WCD938X_DSD_R, 0, 1, 0,
2864                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2865        SOC_SINGLE_TLV("HPHL Volume", WCD938X_HPH_L_EN, 0, 0x18, 0, line_gain),
2866        SOC_SINGLE_TLV("HPHR Volume", WCD938X_HPH_R_EN, 0, 0x18, 0, line_gain),
2867        WCD938X_EAR_PA_GAIN_TLV("EAR_PA Volume", WCD938X_ANA_EAR_COMPANDER_CTL,
2868                                2, 0x10, 0, ear_pa_gain),
2869        SOC_SINGLE_EXT("ADC1 Switch", WCD938X_ADC1, 1, 1, 0,
2870                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2871        SOC_SINGLE_EXT("ADC2 Switch", WCD938X_ADC2, 1, 1, 0,
2872                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2873        SOC_SINGLE_EXT("ADC3 Switch", WCD938X_ADC3, 1, 1, 0,
2874                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2875        SOC_SINGLE_EXT("ADC4 Switch", WCD938X_ADC4, 1, 1, 0,
2876                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2877        SOC_SINGLE_EXT("DMIC0 Switch", WCD938X_DMIC0, 1, 1, 0,
2878                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2879        SOC_SINGLE_EXT("DMIC1 Switch", WCD938X_DMIC1, 1, 1, 0,
2880                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2881        SOC_SINGLE_EXT("MBHC Switch", WCD938X_MBHC, 1, 1, 0,
2882                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2883        SOC_SINGLE_EXT("DMIC2 Switch", WCD938X_DMIC2, 1, 1, 0,
2884                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2885        SOC_SINGLE_EXT("DMIC3 Switch", WCD938X_DMIC3, 1, 1, 0,
2886                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2887        SOC_SINGLE_EXT("DMIC4 Switch", WCD938X_DMIC4, 1, 1, 0,
2888                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2889        SOC_SINGLE_EXT("DMIC5 Switch", WCD938X_DMIC5, 1, 1, 0,
2890                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2891        SOC_SINGLE_EXT("DMIC6 Switch", WCD938X_DMIC6, 1, 1, 0,
2892                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2893        SOC_SINGLE_EXT("DMIC7 Switch", WCD938X_DMIC7, 1, 1, 0,
2894                       wcd938x_get_swr_port, wcd938x_set_swr_port),
2895        SOC_SINGLE_EXT("LDOH Enable Switch", SND_SOC_NOPM, 0, 1, 0,
2896                       wcd938x_ldoh_get, wcd938x_ldoh_put),
2897        SOC_SINGLE_EXT("ADC2_BCS Disable Switch", SND_SOC_NOPM, 0, 1, 0,
2898                       wcd938x_bcs_get, wcd938x_bcs_put),
2899
2900        SOC_SINGLE_TLV("ADC1 Volume", WCD938X_ANA_TX_CH1, 0, 20, 0, analog_gain),
2901        SOC_SINGLE_TLV("ADC2 Volume", WCD938X_ANA_TX_CH2, 0, 20, 0, analog_gain),
2902        SOC_SINGLE_TLV("ADC3 Volume", WCD938X_ANA_TX_CH3, 0, 20, 0, analog_gain),
2903        SOC_SINGLE_TLV("ADC4 Volume", WCD938X_ANA_TX_CH4, 0, 20, 0, analog_gain),
2904};
2905
2906static const struct snd_soc_dapm_widget wcd938x_dapm_widgets[] = {
2907
2908        /*input widgets*/
2909        SND_SOC_DAPM_INPUT("AMIC1"),
2910        SND_SOC_DAPM_INPUT("AMIC2"),
2911        SND_SOC_DAPM_INPUT("AMIC3"),
2912        SND_SOC_DAPM_INPUT("AMIC4"),
2913        SND_SOC_DAPM_INPUT("AMIC5"),
2914        SND_SOC_DAPM_INPUT("AMIC6"),
2915        SND_SOC_DAPM_INPUT("AMIC7"),
2916        SND_SOC_DAPM_MIC("Analog Mic1", NULL),
2917        SND_SOC_DAPM_MIC("Analog Mic2", NULL),
2918        SND_SOC_DAPM_MIC("Analog Mic3", NULL),
2919        SND_SOC_DAPM_MIC("Analog Mic4", NULL),
2920        SND_SOC_DAPM_MIC("Analog Mic5", NULL),
2921
2922        /*tx widgets*/
2923        SND_SOC_DAPM_ADC_E("ADC1", NULL, SND_SOC_NOPM, 0, 0,
2924                           wcd938x_codec_enable_adc,
2925                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2926        SND_SOC_DAPM_ADC_E("ADC2", NULL, SND_SOC_NOPM, 1, 0,
2927                           wcd938x_codec_enable_adc,
2928                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2929        SND_SOC_DAPM_ADC_E("ADC3", NULL, SND_SOC_NOPM, 2, 0,
2930                           wcd938x_codec_enable_adc,
2931                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2932        SND_SOC_DAPM_ADC_E("ADC4", NULL, SND_SOC_NOPM, 3, 0,
2933                           wcd938x_codec_enable_adc,
2934                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2935        SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0,
2936                           wcd938x_codec_enable_dmic,
2937                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2938        SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 1, 0,
2939                           wcd938x_codec_enable_dmic,
2940                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2941        SND_SOC_DAPM_ADC_E("DMIC3", NULL, SND_SOC_NOPM, 2, 0,
2942                           wcd938x_codec_enable_dmic,
2943                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2944        SND_SOC_DAPM_ADC_E("DMIC4", NULL, SND_SOC_NOPM, 3, 0,
2945                           wcd938x_codec_enable_dmic,
2946                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2947        SND_SOC_DAPM_ADC_E("DMIC5", NULL, SND_SOC_NOPM, 4, 0,
2948                           wcd938x_codec_enable_dmic,
2949                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2950        SND_SOC_DAPM_ADC_E("DMIC6", NULL, SND_SOC_NOPM, 5, 0,
2951                           wcd938x_codec_enable_dmic,
2952                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2953        SND_SOC_DAPM_ADC_E("DMIC7", NULL, SND_SOC_NOPM, 6, 0,
2954                           wcd938x_codec_enable_dmic,
2955                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2956        SND_SOC_DAPM_ADC_E("DMIC8", NULL, SND_SOC_NOPM, 7, 0,
2957                           wcd938x_codec_enable_dmic,
2958                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2959
2960        SND_SOC_DAPM_MIXER_E("ADC1 REQ", SND_SOC_NOPM, 0, 0,
2961                             NULL, 0, wcd938x_adc_enable_req,
2962                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2963        SND_SOC_DAPM_MIXER_E("ADC2 REQ", SND_SOC_NOPM, 1, 0,
2964                             NULL, 0, wcd938x_adc_enable_req,
2965                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2966        SND_SOC_DAPM_MIXER_E("ADC3 REQ", SND_SOC_NOPM, 2, 0,
2967                             NULL, 0, wcd938x_adc_enable_req,
2968                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2969        SND_SOC_DAPM_MIXER_E("ADC4 REQ", SND_SOC_NOPM, 3, 0, NULL, 0,
2970                             wcd938x_adc_enable_req,
2971                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2972
2973        SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux),
2974        SND_SOC_DAPM_MUX("ADC3 MUX", SND_SOC_NOPM, 0, 0, &tx_adc3_mux),
2975        SND_SOC_DAPM_MUX("ADC4 MUX", SND_SOC_NOPM, 0, 0, &tx_adc4_mux),
2976        SND_SOC_DAPM_MUX("HDR12 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr12_mux),
2977        SND_SOC_DAPM_MUX("HDR34 MUX", SND_SOC_NOPM, 0, 0, &tx_hdr34_mux),
2978
2979        /*tx mixers*/
2980        SND_SOC_DAPM_MIXER_E("ADC1_MIXER", SND_SOC_NOPM, 0, 0, adc1_switch,
2981                             ARRAY_SIZE(adc1_switch), wcd938x_tx_swr_ctrl,
2982                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2983        SND_SOC_DAPM_MIXER_E("ADC2_MIXER", SND_SOC_NOPM, 0, 0, adc2_switch,
2984                             ARRAY_SIZE(adc2_switch), wcd938x_tx_swr_ctrl,
2985                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2986        SND_SOC_DAPM_MIXER_E("ADC3_MIXER", SND_SOC_NOPM, 0, 0, adc3_switch,
2987                             ARRAY_SIZE(adc3_switch), wcd938x_tx_swr_ctrl,
2988                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2989        SND_SOC_DAPM_MIXER_E("ADC4_MIXER", SND_SOC_NOPM, 0, 0, adc4_switch,
2990                             ARRAY_SIZE(adc4_switch), wcd938x_tx_swr_ctrl,
2991                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2992        SND_SOC_DAPM_MIXER_E("DMIC1_MIXER", SND_SOC_NOPM, 0, 0, dmic1_switch,
2993                             ARRAY_SIZE(dmic1_switch), wcd938x_tx_swr_ctrl,
2994                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2995        SND_SOC_DAPM_MIXER_E("DMIC2_MIXER", SND_SOC_NOPM, 0, 0, dmic2_switch,
2996                             ARRAY_SIZE(dmic2_switch), wcd938x_tx_swr_ctrl,
2997                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
2998        SND_SOC_DAPM_MIXER_E("DMIC3_MIXER", SND_SOC_NOPM, 0, 0, dmic3_switch,
2999                             ARRAY_SIZE(dmic3_switch), wcd938x_tx_swr_ctrl,
3000                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3001        SND_SOC_DAPM_MIXER_E("DMIC4_MIXER", SND_SOC_NOPM, 0, 0, dmic4_switch,
3002                             ARRAY_SIZE(dmic4_switch), wcd938x_tx_swr_ctrl,
3003                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3004        SND_SOC_DAPM_MIXER_E("DMIC5_MIXER", SND_SOC_NOPM, 0, 0, dmic5_switch,
3005                             ARRAY_SIZE(dmic5_switch), wcd938x_tx_swr_ctrl,
3006                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3007        SND_SOC_DAPM_MIXER_E("DMIC6_MIXER", SND_SOC_NOPM, 0, 0, dmic6_switch,
3008                             ARRAY_SIZE(dmic6_switch), wcd938x_tx_swr_ctrl,
3009                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3010        SND_SOC_DAPM_MIXER_E("DMIC7_MIXER", SND_SOC_NOPM, 0, 0, dmic7_switch,
3011                             ARRAY_SIZE(dmic7_switch), wcd938x_tx_swr_ctrl,
3012                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3013        SND_SOC_DAPM_MIXER_E("DMIC8_MIXER", SND_SOC_NOPM, 0, 0, dmic8_switch,
3014                             ARRAY_SIZE(dmic8_switch), wcd938x_tx_swr_ctrl,
3015                             SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3016        /* micbias widgets*/
3017        SND_SOC_DAPM_SUPPLY("MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3018                            wcd938x_codec_enable_micbias,
3019                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3020                            SND_SOC_DAPM_POST_PMD),
3021        SND_SOC_DAPM_SUPPLY("MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3022                            wcd938x_codec_enable_micbias,
3023                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3024                            SND_SOC_DAPM_POST_PMD),
3025        SND_SOC_DAPM_SUPPLY("MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3026                            wcd938x_codec_enable_micbias,
3027                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3028                            SND_SOC_DAPM_POST_PMD),
3029        SND_SOC_DAPM_SUPPLY("MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3030                            wcd938x_codec_enable_micbias,
3031                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3032                            SND_SOC_DAPM_POST_PMD),
3033
3034        /* micbias pull up widgets*/
3035        SND_SOC_DAPM_SUPPLY("VA MIC BIAS1", SND_SOC_NOPM, MIC_BIAS_1, 0,
3036                                wcd938x_codec_enable_micbias_pullup,
3037                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3038                                SND_SOC_DAPM_POST_PMD),
3039        SND_SOC_DAPM_SUPPLY("VA MIC BIAS2", SND_SOC_NOPM, MIC_BIAS_2, 0,
3040                                wcd938x_codec_enable_micbias_pullup,
3041                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3042                                SND_SOC_DAPM_POST_PMD),
3043        SND_SOC_DAPM_SUPPLY("VA MIC BIAS3", SND_SOC_NOPM, MIC_BIAS_3, 0,
3044                                wcd938x_codec_enable_micbias_pullup,
3045                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3046                                SND_SOC_DAPM_POST_PMD),
3047        SND_SOC_DAPM_SUPPLY("VA MIC BIAS4", SND_SOC_NOPM, MIC_BIAS_4, 0,
3048                                wcd938x_codec_enable_micbias_pullup,
3049                                SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3050                                SND_SOC_DAPM_POST_PMD),
3051
3052        /*output widgets tx*/
3053        SND_SOC_DAPM_OUTPUT("ADC1_OUTPUT"),
3054        SND_SOC_DAPM_OUTPUT("ADC2_OUTPUT"),
3055        SND_SOC_DAPM_OUTPUT("ADC3_OUTPUT"),
3056        SND_SOC_DAPM_OUTPUT("ADC4_OUTPUT"),
3057        SND_SOC_DAPM_OUTPUT("DMIC1_OUTPUT"),
3058        SND_SOC_DAPM_OUTPUT("DMIC2_OUTPUT"),
3059        SND_SOC_DAPM_OUTPUT("DMIC3_OUTPUT"),
3060        SND_SOC_DAPM_OUTPUT("DMIC4_OUTPUT"),
3061        SND_SOC_DAPM_OUTPUT("DMIC5_OUTPUT"),
3062        SND_SOC_DAPM_OUTPUT("DMIC6_OUTPUT"),
3063        SND_SOC_DAPM_OUTPUT("DMIC7_OUTPUT"),
3064        SND_SOC_DAPM_OUTPUT("DMIC8_OUTPUT"),
3065
3066        SND_SOC_DAPM_INPUT("IN1_HPHL"),
3067        SND_SOC_DAPM_INPUT("IN2_HPHR"),
3068        SND_SOC_DAPM_INPUT("IN3_AUX"),
3069
3070        /*rx widgets*/
3071        SND_SOC_DAPM_PGA_E("EAR PGA", WCD938X_ANA_EAR, 7, 0, NULL, 0,
3072                           wcd938x_codec_enable_ear_pa,
3073                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3074                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3075        SND_SOC_DAPM_PGA_E("AUX PGA", WCD938X_AUX_AUXPA, 7, 0, NULL, 0,
3076                           wcd938x_codec_enable_aux_pa,
3077                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3078                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3079        SND_SOC_DAPM_PGA_E("HPHL PGA", WCD938X_ANA_HPH, 7, 0, NULL, 0,
3080                           wcd938x_codec_enable_hphl_pa,
3081                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3082                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3083        SND_SOC_DAPM_PGA_E("HPHR PGA", WCD938X_ANA_HPH, 6, 0, NULL, 0,
3084                           wcd938x_codec_enable_hphr_pa,
3085                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3086                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3087
3088        SND_SOC_DAPM_DAC_E("RDAC1", NULL, SND_SOC_NOPM, 0, 0,
3089                           wcd938x_codec_hphl_dac_event,
3090                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3091                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3092        SND_SOC_DAPM_DAC_E("RDAC2", NULL, SND_SOC_NOPM, 0, 0,
3093                           wcd938x_codec_hphr_dac_event,
3094                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3095                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3096        SND_SOC_DAPM_DAC_E("RDAC3", NULL, SND_SOC_NOPM, 0, 0,
3097                           wcd938x_codec_ear_dac_event,
3098                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3099                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3100        SND_SOC_DAPM_DAC_E("RDAC4", NULL, SND_SOC_NOPM, 0, 0,
3101                           wcd938x_codec_aux_dac_event,
3102                           SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3103                           SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD),
3104
3105        SND_SOC_DAPM_MUX("RDAC3_MUX", SND_SOC_NOPM, 0, 0, &rx_rdac3_mux),
3106
3107        SND_SOC_DAPM_SUPPLY("VDD_BUCK", SND_SOC_NOPM, 0, 0, NULL, 0),
3108        SND_SOC_DAPM_SUPPLY("RXCLK", SND_SOC_NOPM, 0, 0,
3109                            wcd938x_codec_enable_rxclk,
3110                            SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU |
3111                            SND_SOC_DAPM_POST_PMD),
3112
3113        SND_SOC_DAPM_SUPPLY_S("CLS_H_PORT", 1, SND_SOC_NOPM, 0, 0, NULL, 0),
3114
3115        SND_SOC_DAPM_MIXER_E("RX1", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3116        SND_SOC_DAPM_MIXER_E("RX2", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3117        SND_SOC_DAPM_MIXER_E("RX3", SND_SOC_NOPM, 0, 0, NULL, 0, NULL, 0),
3118
3119        /* rx mixer widgets*/
3120        SND_SOC_DAPM_MIXER("EAR_RDAC", SND_SOC_NOPM, 0, 0,
3121                           ear_rdac_switch, ARRAY_SIZE(ear_rdac_switch)),
3122        SND_SOC_DAPM_MIXER("AUX_RDAC", SND_SOC_NOPM, 0, 0,
3123                           aux_rdac_switch, ARRAY_SIZE(aux_rdac_switch)),
3124        SND_SOC_DAPM_MIXER("HPHL_RDAC", SND_SOC_NOPM, 0, 0,
3125                           hphl_rdac_switch, ARRAY_SIZE(hphl_rdac_switch)),
3126        SND_SOC_DAPM_MIXER("HPHR_RDAC", SND_SOC_NOPM, 0, 0,
3127                           hphr_rdac_switch, ARRAY_SIZE(hphr_rdac_switch)),
3128
3129        /*output widgets rx*/
3130        SND_SOC_DAPM_OUTPUT("EAR"),
3131        SND_SOC_DAPM_OUTPUT("AUX"),
3132        SND_SOC_DAPM_OUTPUT("HPHL"),
3133        SND_SOC_DAPM_OUTPUT("HPHR"),
3134
3135};
3136
3137static const struct snd_soc_dapm_route wcd938x_audio_map[] = {
3138        {"ADC1_OUTPUT", NULL, "ADC1_MIXER"},
3139        {"ADC1_MIXER", "Switch", "ADC1 REQ"},
3140        {"ADC1 REQ", NULL, "ADC1"},
3141        {"ADC1", NULL, "AMIC1"},
3142
3143        {"ADC2_OUTPUT", NULL, "ADC2_MIXER"},
3144        {"ADC2_MIXER", "Switch", "ADC2 REQ"},
3145        {"ADC2 REQ", NULL, "ADC2"},
3146        {"ADC2", NULL, "HDR12 MUX"},
3147        {"HDR12 MUX", "NO_HDR12", "ADC2 MUX"},
3148        {"HDR12 MUX", "HDR12", "AMIC1"},
3149        {"ADC2 MUX", "INP3", "AMIC3"},
3150        {"ADC2 MUX", "INP2", "AMIC2"},
3151
3152        {"ADC3_OUTPUT", NULL, "ADC3_MIXER"},
3153        {"ADC3_MIXER", "Switch", "ADC3 REQ"},
3154        {"ADC3 REQ", NULL, "ADC3"},
3155        {"ADC3", NULL, "HDR34 MUX"},
3156        {"HDR34 MUX", "NO_HDR34", "ADC3 MUX"},
3157        {"HDR34 MUX", "HDR34", "AMIC5"},
3158        {"ADC3 MUX", "INP4", "AMIC4"},
3159        {"ADC3 MUX", "INP6", "AMIC6"},
3160
3161        {"ADC4_OUTPUT", NULL, "ADC4_MIXER"},
3162        {"ADC4_MIXER", "Switch", "ADC4 REQ"},
3163        {"ADC4 REQ", NULL, "ADC4"},
3164        {"ADC4", NULL, "ADC4 MUX"},
3165        {"ADC4 MUX", "INP5", "AMIC5"},
3166        {"ADC4 MUX", "INP7", "AMIC7"},
3167
3168        {"DMIC1_OUTPUT", NULL, "DMIC1_MIXER"},
3169        {"DMIC1_MIXER", "Switch", "DMIC1"},
3170
3171        {"DMIC2_OUTPUT", NULL, "DMIC2_MIXER"},
3172        {"DMIC2_MIXER", "Switch", "DMIC2"},
3173
3174        {"DMIC3_OUTPUT", NULL, "DMIC3_MIXER"},
3175        {"DMIC3_MIXER", "Switch", "DMIC3"},
3176
3177        {"DMIC4_OUTPUT", NULL, "DMIC4_MIXER"},
3178        {"DMIC4_MIXER", "Switch", "DMIC4"},
3179
3180        {"DMIC5_OUTPUT", NULL, "DMIC5_MIXER"},
3181        {"DMIC5_MIXER", "Switch", "DMIC5"},
3182
3183        {"DMIC6_OUTPUT", NULL, "DMIC6_MIXER"},
3184        {"DMIC6_MIXER", "Switch", "DMIC6"},
3185
3186        {"DMIC7_OUTPUT", NULL, "DMIC7_MIXER"},
3187        {"DMIC7_MIXER", "Switch", "DMIC7"},
3188
3189        {"DMIC8_OUTPUT", NULL, "DMIC8_MIXER"},
3190        {"DMIC8_MIXER", "Switch", "DMIC8"},
3191
3192        {"IN1_HPHL", NULL, "VDD_BUCK"},
3193        {"IN1_HPHL", NULL, "CLS_H_PORT"},
3194
3195        {"RX1", NULL, "IN1_HPHL"},
3196        {"RX1", NULL, "RXCLK"},
3197        {"RDAC1", NULL, "RX1"},
3198        {"HPHL_RDAC", "Switch", "RDAC1"},
3199        {"HPHL PGA", NULL, "HPHL_RDAC"},
3200        {"HPHL", NULL, "HPHL PGA"},
3201
3202        {"IN2_HPHR", NULL, "VDD_BUCK"},
3203        {"IN2_HPHR", NULL, "CLS_H_PORT"},
3204        {"RX2", NULL, "IN2_HPHR"},
3205        {"RDAC2", NULL, "RX2"},
3206        {"RX2", NULL, "RXCLK"},
3207        {"HPHR_RDAC", "Switch", "RDAC2"},
3208        {"HPHR PGA", NULL, "HPHR_RDAC"},
3209        {"HPHR", NULL, "HPHR PGA"},
3210
3211        {"IN3_AUX", NULL, "VDD_BUCK"},
3212        {"IN3_AUX", NULL, "CLS_H_PORT"},
3213        {"RX3", NULL, "IN3_AUX"},
3214        {"RDAC4", NULL, "RX3"},
3215        {"RX3", NULL, "RXCLK"},
3216        {"AUX_RDAC", "Switch", "RDAC4"},
3217        {"AUX PGA", NULL, "AUX_RDAC"},
3218        {"AUX", NULL, "AUX PGA"},
3219
3220        {"RDAC3_MUX", "RX3", "RX3"},
3221        {"RDAC3_MUX", "RX1", "RX1"},
3222        {"RDAC3", NULL, "RDAC3_MUX"},
3223        {"EAR_RDAC", "Switch", "RDAC3"},
3224        {"EAR PGA", NULL, "EAR_RDAC"},
3225        {"EAR", NULL, "EAR PGA"},
3226};
3227
3228static int wcd938x_get_micb_vout_ctl_val(u32 micb_mv)
3229{
3230        /* min micbias voltage is 1V and maximum is 2.85V */
3231        if (micb_mv < 1000 || micb_mv > 2850)
3232                return -EINVAL;
3233
3234        return (micb_mv - 1000) / 50;
3235}
3236
3237static int wcd938x_set_micbias_data(struct wcd938x_priv *wcd938x)
3238{
3239        int vout_ctl_1, vout_ctl_2, vout_ctl_3, vout_ctl_4;
3240
3241        /* set micbias voltage */
3242        vout_ctl_1 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb1_mv);
3243        vout_ctl_2 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb2_mv);
3244        vout_ctl_3 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb3_mv);
3245        vout_ctl_4 = wcd938x_get_micb_vout_ctl_val(wcd938x->micb4_mv);
3246        if (vout_ctl_1 < 0 || vout_ctl_2 < 0 || vout_ctl_3 < 0 || vout_ctl_4 < 0)
3247                return -EINVAL;
3248
3249        regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB1,
3250                           WCD938X_MICB_VOUT_MASK, vout_ctl_1);
3251        regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB2,
3252                           WCD938X_MICB_VOUT_MASK, vout_ctl_2);
3253        regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB3,
3254                           WCD938X_MICB_VOUT_MASK, vout_ctl_3);
3255        regmap_update_bits(wcd938x->regmap, WCD938X_ANA_MICB4,
3256                           WCD938X_MICB_VOUT_MASK, vout_ctl_4);
3257
3258        return 0;
3259}
3260
3261static irqreturn_t wcd938x_wd_handle_irq(int irq, void *data)
3262{
3263        return IRQ_HANDLED;
3264}
3265
3266static struct irq_chip wcd_irq_chip = {
3267        .name = "WCD938x",
3268};
3269
3270static int wcd_irq_chip_map(struct irq_domain *irqd, unsigned int virq,
3271                        irq_hw_number_t hw)
3272{
3273        irq_set_chip_and_handler(virq, &wcd_irq_chip, handle_simple_irq);
3274        irq_set_nested_thread(virq, 1);
3275        irq_set_noprobe(virq);
3276
3277        return 0;
3278}
3279
3280static const struct irq_domain_ops wcd_domain_ops = {
3281        .map = wcd_irq_chip_map,
3282};
3283
3284static int wcd938x_irq_init(struct wcd938x_priv *wcd, struct device *dev)
3285{
3286
3287        wcd->virq = irq_domain_add_linear(NULL, 1, &wcd_domain_ops, NULL);
3288        if (!(wcd->virq)) {
3289                dev_err(dev, "%s: Failed to add IRQ domain\n", __func__);
3290                return -EINVAL;
3291        }
3292
3293        return devm_regmap_add_irq_chip(dev, wcd->regmap,
3294                                        irq_create_mapping(wcd->virq, 0),
3295                                        IRQF_ONESHOT, 0, &wcd938x_regmap_irq_chip,
3296                                        &wcd->irq_chip);
3297}
3298
3299static int wcd938x_soc_codec_probe(struct snd_soc_component *component)
3300{
3301        struct wcd938x_priv *wcd938x = snd_soc_component_get_drvdata(component);
3302        struct device *dev = component->dev;
3303        int ret, i;
3304
3305        snd_soc_component_init_regmap(component, wcd938x->regmap);
3306
3307        wcd938x->variant = snd_soc_component_read_field(component,
3308                                                 WCD938X_DIGITAL_EFUSE_REG_0,
3309                                                 WCD938X_ID_MASK);
3310
3311        wcd938x->clsh_info = wcd_clsh_ctrl_alloc(component, WCD938X);
3312
3313        wcd938x_io_init(wcd938x);
3314        /* Set all interrupts as edge triggered */
3315        for (i = 0; i < wcd938x_regmap_irq_chip.num_regs; i++) {
3316                regmap_write(wcd938x->regmap,
3317                             (WCD938X_DIGITAL_INTR_LEVEL_0 + i), 0);
3318        }
3319
3320        wcd938x->hphr_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3321                                                       WCD938X_IRQ_HPHR_PDM_WD_INT);
3322        wcd938x->hphl_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3323                                                       WCD938X_IRQ_HPHL_PDM_WD_INT);
3324        wcd938x->aux_pdm_wd_int = regmap_irq_get_virq(wcd938x->irq_chip,
3325                                                       WCD938X_IRQ_AUX_PDM_WD_INT);
3326
3327        /* Request for watchdog interrupt */
3328        ret = request_threaded_irq(wcd938x->hphr_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3329                                   IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3330                                   "HPHR PDM WD INT", wcd938x);
3331        if (ret)
3332                dev_err(dev, "Failed to request HPHR WD interrupt (%d)\n", ret);
3333
3334        ret = request_threaded_irq(wcd938x->hphl_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3335                                   IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3336                                   "HPHL PDM WD INT", wcd938x);
3337        if (ret)
3338                dev_err(dev, "Failed to request HPHL WD interrupt (%d)\n", ret);
3339
3340        ret = request_threaded_irq(wcd938x->aux_pdm_wd_int, NULL, wcd938x_wd_handle_irq,
3341                                   IRQF_ONESHOT | IRQF_TRIGGER_RISING,
3342                                   "AUX PDM WD INT", wcd938x);
3343        if (ret)
3344                dev_err(dev, "Failed to request Aux WD interrupt (%d)\n", ret);
3345
3346        /* Disable watchdog interrupt for HPH and AUX */
3347        disable_irq_nosync(wcd938x->hphr_pdm_wd_int);
3348        disable_irq_nosync(wcd938x->hphl_pdm_wd_int);
3349        disable_irq_nosync(wcd938x->aux_pdm_wd_int);
3350
3351        switch (wcd938x->variant) {
3352        case WCD9380:
3353                ret = snd_soc_add_component_controls(component, wcd9380_snd_controls,
3354                                        ARRAY_SIZE(wcd9380_snd_controls));
3355                if (ret < 0) {
3356                        dev_err(component->dev,
3357                                "%s: Failed to add snd ctrls for variant: %d\n",
3358                                __func__, wcd938x->variant);
3359                        goto err;
3360                }
3361                break;
3362        case WCD9385:
3363                ret = snd_soc_add_component_controls(component, wcd9385_snd_controls,
3364                                        ARRAY_SIZE(wcd9385_snd_controls));
3365                if (ret < 0) {
3366                        dev_err(component->dev,
3367                                "%s: Failed to add snd ctrls for variant: %d\n",
3368                                __func__, wcd938x->variant);
3369                        goto err;
3370                }
3371                break;
3372        default:
3373                break;
3374        }
3375err:
3376        return ret;
3377}
3378
3379static const struct snd_soc_component_driver soc_codec_dev_wcd938x = {
3380        .name = "wcd938x_codec",
3381        .probe = wcd938x_soc_codec_probe,
3382        .controls = wcd938x_snd_controls,
3383        .num_controls = ARRAY_SIZE(wcd938x_snd_controls),
3384        .dapm_widgets = wcd938x_dapm_widgets,
3385        .num_dapm_widgets = ARRAY_SIZE(wcd938x_dapm_widgets),
3386        .dapm_routes = wcd938x_audio_map,
3387        .num_dapm_routes = ARRAY_SIZE(wcd938x_audio_map),
3388};
3389
3390static void wcd938x_dt_parse_micbias_info(struct device *dev, struct wcd938x_priv *wcd)
3391{
3392        struct device_node *np = dev->of_node;
3393        u32 prop_val = 0;
3394        int rc = 0;
3395
3396        rc = of_property_read_u32(np, "qcom,micbias1-microvolt",  &prop_val);
3397        if (!rc)
3398                wcd->micb1_mv = prop_val/1000;
3399        else
3400                dev_info(dev, "%s: Micbias1 DT property not found\n", __func__);
3401
3402        rc = of_property_read_u32(np, "qcom,micbias2-microvolt",  &prop_val);
3403        if (!rc)
3404                wcd->micb2_mv = prop_val/1000;
3405        else
3406                dev_info(dev, "%s: Micbias2 DT property not found\n", __func__);
3407
3408        rc = of_property_read_u32(np, "qcom,micbias3-microvolt", &prop_val);
3409        if (!rc)
3410                wcd->micb3_mv = prop_val/1000;
3411        else
3412                dev_info(dev, "%s: Micbias3 DT property not found\n", __func__);
3413
3414        rc = of_property_read_u32(np, "qcom,micbias4-microvolt",  &prop_val);
3415        if (!rc)
3416                wcd->micb4_mv = prop_val/1000;
3417        else
3418                dev_info(dev, "%s: Micbias4 DT property not found\n", __func__);
3419}
3420
3421static int wcd938x_populate_dt_data(struct wcd938x_priv *wcd938x, struct device *dev)
3422{
3423        int ret;
3424
3425        wcd938x->reset_gpio = of_get_named_gpio(dev->of_node, "reset-gpios", 0);
3426        if (wcd938x->reset_gpio < 0) {
3427                dev_err(dev, "Failed to get reset gpio: err = %d\n",
3428                        wcd938x->reset_gpio);
3429                return wcd938x->reset_gpio;
3430        }
3431
3432        wcd938x->supplies[0].supply = "vdd-rxtx";
3433        wcd938x->supplies[1].supply = "vdd-io";
3434        wcd938x->supplies[2].supply = "vdd-buck";
3435        wcd938x->supplies[3].supply = "vdd-mic-bias";
3436
3437        ret = regulator_bulk_get(dev, WCD938X_MAX_SUPPLY, wcd938x->supplies);
3438        if (ret) {
3439                dev_err(dev, "Failed to get supplies: err = %d\n", ret);
3440                return ret;
3441        }
3442
3443        ret = regulator_bulk_enable(WCD938X_MAX_SUPPLY, wcd938x->supplies);
3444        if (ret) {
3445                dev_err(dev, "Failed to enable supplies: err = %d\n", ret);
3446                return ret;
3447        }
3448
3449        wcd938x_dt_parse_micbias_info(dev, wcd938x);
3450
3451        return 0;
3452}
3453
3454static int wcd938x_reset(struct wcd938x_priv *wcd938x)
3455{
3456        gpio_direction_output(wcd938x->reset_gpio, 0);
3457        /* 20us sleep required after pulling the reset gpio to LOW */
3458        usleep_range(20, 30);
3459        gpio_set_value(wcd938x->reset_gpio, 1);
3460        /* 20us sleep required after pulling the reset gpio to HIGH */
3461        usleep_range(20, 30);
3462
3463        return 0;
3464}
3465
3466static int wcd938x_codec_hw_params(struct snd_pcm_substream *substream,
3467                                struct snd_pcm_hw_params *params,
3468                                struct snd_soc_dai *dai)
3469{
3470        struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3471        struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3472
3473        return wcd938x_sdw_hw_params(wcd, substream, params, dai);
3474}
3475
3476static int wcd938x_codec_free(struct snd_pcm_substream *substream,
3477                              struct snd_soc_dai *dai)
3478{
3479        struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3480        struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3481
3482        return wcd938x_sdw_free(wcd, substream, dai);
3483}
3484
3485static int wcd938x_codec_set_sdw_stream(struct snd_soc_dai *dai,
3486                                  void *stream, int direction)
3487{
3488        struct wcd938x_priv *wcd938x = dev_get_drvdata(dai->dev);
3489        struct wcd938x_sdw_priv *wcd = wcd938x->sdw_priv[dai->id];
3490
3491        return wcd938x_sdw_set_sdw_stream(wcd, dai, stream, direction);
3492
3493}
3494
3495static const struct snd_soc_dai_ops wcd938x_sdw_dai_ops = {
3496        .hw_params = wcd938x_codec_hw_params,
3497        .hw_free = wcd938x_codec_free,
3498        .set_sdw_stream = wcd938x_codec_set_sdw_stream,
3499};
3500
3501static struct snd_soc_dai_driver wcd938x_dais[] = {
3502        [0] = {
3503                .name = "wcd938x-sdw-rx",
3504                .playback = {
3505                        .stream_name = "WCD AIF1 Playback",
3506                        .rates = WCD938X_RATES_MASK | WCD938X_FRAC_RATES_MASK,
3507                        .formats = WCD938X_FORMATS_S16_S24_LE,
3508                        .rate_max = 192000,
3509                        .rate_min = 8000,
3510                        .channels_min = 1,
3511                        .channels_max = 2,
3512                },
3513                .ops = &wcd938x_sdw_dai_ops,
3514        },
3515        [1] = {
3516                .name = "wcd938x-sdw-tx",
3517                .capture = {
3518                        .stream_name = "WCD AIF1 Capture",
3519                        .rates = WCD938X_RATES_MASK,
3520                        .formats = SNDRV_PCM_FMTBIT_S16_LE,
3521                        .rate_min = 8000,
3522                        .rate_max = 192000,
3523                        .channels_min = 1,
3524                        .channels_max = 4,
3525                },
3526                .ops = &wcd938x_sdw_dai_ops,
3527        },
3528};
3529
3530static int wcd938x_bind(struct device *dev)
3531{
3532        struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
3533        int ret;
3534
3535        ret = component_bind_all(dev, wcd938x);
3536        if (ret) {
3537                dev_err(dev, "%s: Slave bind failed, ret = %d\n",
3538                        __func__, ret);
3539                return ret;
3540        }
3541
3542        wcd938x->rxdev = wcd938x_sdw_device_get(wcd938x->rxnode);
3543        if (!wcd938x->rxdev) {
3544                dev_err(dev, "could not find slave with matching of node\n");
3545                return -EINVAL;
3546        }
3547        wcd938x->sdw_priv[AIF1_PB] = dev_get_drvdata(wcd938x->rxdev);
3548        wcd938x->sdw_priv[AIF1_PB]->wcd938x = wcd938x;
3549
3550        wcd938x->txdev = wcd938x_sdw_device_get(wcd938x->txnode);
3551        if (!wcd938x->txdev) {
3552                dev_err(dev, "could not find txslave with matching of node\n");
3553                return -EINVAL;
3554        }
3555        wcd938x->sdw_priv[AIF1_CAP] = dev_get_drvdata(wcd938x->txdev);
3556        wcd938x->sdw_priv[AIF1_CAP]->wcd938x = wcd938x;
3557        wcd938x->tx_sdw_dev = dev_to_sdw_dev(wcd938x->txdev);
3558        if (!wcd938x->tx_sdw_dev) {
3559                dev_err(dev, "could not get txslave with matching of dev\n");
3560                return -EINVAL;
3561        }
3562
3563        /* As TX is main CSR reg interface, which should not be suspended first.
3564         * expicilty add the dependency link */
3565        if (!device_link_add(wcd938x->rxdev, wcd938x->txdev, DL_FLAG_STATELESS |
3566                            DL_FLAG_PM_RUNTIME)) {
3567                dev_err(dev, "could not devlink tx and rx\n");
3568                return -EINVAL;
3569        }
3570
3571        if (!device_link_add(dev, wcd938x->txdev, DL_FLAG_STATELESS |
3572                                        DL_FLAG_PM_RUNTIME)) {
3573                dev_err(dev, "could not devlink wcd and tx\n");
3574                return -EINVAL;
3575        }
3576
3577        if (!device_link_add(dev, wcd938x->rxdev, DL_FLAG_STATELESS |
3578                                        DL_FLAG_PM_RUNTIME)) {
3579                dev_err(dev, "could not devlink wcd and rx\n");
3580                return -EINVAL;
3581        }
3582
3583        wcd938x->regmap = devm_regmap_init_sdw(wcd938x->tx_sdw_dev, &wcd938x_regmap_config);
3584        if (IS_ERR(wcd938x->regmap)) {
3585                dev_err(dev, "%s: tx csr regmap not found\n", __func__);
3586                return PTR_ERR(wcd938x->regmap);
3587        }
3588
3589        ret = wcd938x_irq_init(wcd938x, dev);
3590        if (ret) {
3591                dev_err(dev, "%s: IRQ init failed: %d\n", __func__, ret);
3592                return ret;
3593        }
3594
3595        wcd938x->sdw_priv[AIF1_PB]->slave_irq = wcd938x->virq;
3596        wcd938x->sdw_priv[AIF1_CAP]->slave_irq = wcd938x->virq;
3597
3598        ret = wcd938x_set_micbias_data(wcd938x);
3599        if (ret < 0) {
3600                dev_err(dev, "%s: bad micbias pdata\n", __func__);
3601                return ret;
3602        }
3603
3604        ret = snd_soc_register_component(dev, &soc_codec_dev_wcd938x,
3605                                         wcd938x_dais, ARRAY_SIZE(wcd938x_dais));
3606        if (ret)
3607                dev_err(dev, "%s: Codec registration failed\n",
3608                                __func__);
3609
3610        return ret;
3611
3612}
3613
3614static void wcd938x_unbind(struct device *dev)
3615{
3616        struct wcd938x_priv *wcd938x = dev_get_drvdata(dev);
3617
3618        device_link_remove(dev, wcd938x->txdev);
3619        device_link_remove(dev, wcd938x->rxdev);
3620        device_link_remove(wcd938x->rxdev, wcd938x->txdev);
3621        snd_soc_unregister_component(dev);
3622        component_unbind_all(dev, wcd938x);
3623}
3624
3625static const struct component_master_ops wcd938x_comp_ops = {
3626        .bind   = wcd938x_bind,
3627        .unbind = wcd938x_unbind,
3628};
3629
3630static int wcd938x_compare_of(struct device *dev, void *data)
3631{
3632        return dev->of_node == data;
3633}
3634
3635static void wcd938x_release_of(struct device *dev, void *data)
3636{
3637        of_node_put(data);
3638}
3639
3640static int wcd938x_add_slave_components(struct wcd938x_priv *wcd938x,
3641                                        struct device *dev,
3642                                        struct component_match **matchptr)
3643{
3644        struct device_node *np;
3645
3646        np = dev->of_node;
3647
3648        wcd938x->rxnode = of_parse_phandle(np, "qcom,rx-device", 0);
3649        if (!wcd938x->rxnode) {
3650                dev_err(dev, "%s: Rx-device node not defined\n", __func__);
3651                return -ENODEV;
3652        }
3653
3654        of_node_get(wcd938x->rxnode);
3655        component_match_add_release(dev, matchptr, wcd938x_release_of,
3656                                    wcd938x_compare_of, wcd938x->rxnode);
3657
3658        wcd938x->txnode = of_parse_phandle(np, "qcom,tx-device", 0);
3659        if (!wcd938x->txnode) {
3660                dev_err(dev, "%s: Tx-device node not defined\n", __func__);
3661                return -ENODEV;
3662        }
3663        of_node_get(wcd938x->txnode);
3664        component_match_add_release(dev, matchptr, wcd938x_release_of,
3665                                    wcd938x_compare_of, wcd938x->txnode);
3666        return 0;
3667}
3668
3669static int wcd938x_probe(struct platform_device *pdev)
3670{
3671        struct component_match *match = NULL;
3672        struct wcd938x_priv *wcd938x = NULL;
3673        struct device *dev = &pdev->dev;
3674        int ret;
3675
3676        wcd938x = devm_kzalloc(dev, sizeof(struct wcd938x_priv),
3677                                GFP_KERNEL);
3678        if (!wcd938x)
3679                return -ENOMEM;
3680
3681        dev_set_drvdata(dev, wcd938x);
3682
3683        ret = wcd938x_populate_dt_data(wcd938x, dev);
3684        if (ret) {
3685                dev_err(dev, "%s: Fail to obtain platform data\n", __func__);
3686                return -EINVAL;
3687        }
3688
3689        ret = wcd938x_add_slave_components(wcd938x, dev, &match);
3690        if (ret)
3691                return ret;
3692
3693        wcd938x_reset(wcd938x);
3694
3695        ret = component_master_add_with_match(dev, &wcd938x_comp_ops, match);
3696        if (ret)
3697                return ret;
3698
3699        pm_runtime_set_autosuspend_delay(dev, 1000);
3700        pm_runtime_use_autosuspend(dev);
3701        pm_runtime_mark_last_busy(dev);
3702        pm_runtime_set_active(dev);
3703        pm_runtime_enable(dev);
3704        pm_runtime_idle(dev);
3705
3706        return ret;
3707}
3708
3709static int wcd938x_remove(struct platform_device *pdev)
3710{
3711        component_master_del(&pdev->dev, &wcd938x_comp_ops);
3712
3713        return 0;
3714}
3715
3716#if defined(CONFIG_OF)
3717static const struct of_device_id wcd938x_dt_match[] = {
3718        { .compatible = "qcom,wcd9380-codec" },
3719        { .compatible = "qcom,wcd9385-codec" },
3720        {}
3721};
3722MODULE_DEVICE_TABLE(of, wcd938x_dt_match);
3723#endif
3724
3725static struct platform_driver wcd938x_codec_driver = {
3726        .probe = wcd938x_probe,
3727        .remove = wcd938x_remove,
3728        .driver = {
3729                .name = "wcd938x_codec",
3730                .of_match_table = of_match_ptr(wcd938x_dt_match),
3731                .suppress_bind_attrs = true,
3732        },
3733};
3734
3735module_platform_driver(wcd938x_codec_driver);
3736MODULE_DESCRIPTION("WCD938X Codec driver");
3737MODULE_LICENSE("GPL");
3738