linux/sound/soc/codecs/tlv320aic32x4.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * linux/sound/soc/codecs/tlv320aic32x4.c
   4 *
   5 * Copyright 2011 Vista Silicon S.L.
   6 *
   7 * Author: Javier Martin <javier.martin@vista-silicon.com>
   8 *
   9 * Based on sound/soc/codecs/wm8974 and TI driver for kernel 2.6.27.
  10 */
  11
  12#include <linux/module.h>
  13#include <linux/moduleparam.h>
  14#include <linux/init.h>
  15#include <linux/delay.h>
  16#include <linux/pm.h>
  17#include <linux/gpio.h>
  18#include <linux/of_gpio.h>
  19#include <linux/cdev.h>
  20#include <linux/slab.h>
  21#include <linux/clk.h>
  22#include <linux/of_clk.h>
  23#include <linux/regulator/consumer.h>
  24
  25#include <sound/tlv320aic32x4.h>
  26#include <sound/core.h>
  27#include <sound/pcm.h>
  28#include <sound/pcm_params.h>
  29#include <sound/soc.h>
  30#include <sound/soc-dapm.h>
  31#include <sound/initval.h>
  32#include <sound/tlv.h>
  33
  34#include "tlv320aic32x4.h"
  35
  36struct aic32x4_priv {
  37        struct regmap *regmap;
  38        u32 power_cfg;
  39        u32 micpga_routing;
  40        bool swapdacs;
  41        int rstn_gpio;
  42        const char *mclk_name;
  43
  44        struct regulator *supply_ldo;
  45        struct regulator *supply_iov;
  46        struct regulator *supply_dv;
  47        struct regulator *supply_av;
  48
  49        struct aic32x4_setup_data *setup;
  50        struct device *dev;
  51        enum aic32x4_type type;
  52};
  53
  54static int aic32x4_reset_adc(struct snd_soc_dapm_widget *w,
  55                             struct snd_kcontrol *kcontrol, int event)
  56{
  57        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  58        u32 adc_reg;
  59
  60        /*
  61         * Workaround: the datasheet does not mention a required programming
  62         * sequence but experiments show the ADC needs to be reset after each
  63         * capture to avoid audible artifacts.
  64         */
  65        switch (event) {
  66        case SND_SOC_DAPM_POST_PMD:
  67                adc_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
  68                snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg |
  69                                        AIC32X4_LADC_EN | AIC32X4_RADC_EN);
  70                snd_soc_component_write(component, AIC32X4_ADCSETUP, adc_reg);
  71                break;
  72        }
  73        return 0;
  74};
  75
  76static int mic_bias_event(struct snd_soc_dapm_widget *w,
  77        struct snd_kcontrol *kcontrol, int event)
  78{
  79        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
  80
  81        switch (event) {
  82        case SND_SOC_DAPM_POST_PMU:
  83                /* Change Mic Bias Registor */
  84                snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
  85                                AIC32x4_MICBIAS_MASK,
  86                                AIC32X4_MICBIAS_LDOIN |
  87                                AIC32X4_MICBIAS_2075V);
  88                printk(KERN_DEBUG "%s: Mic Bias will be turned ON\n", __func__);
  89                break;
  90        case SND_SOC_DAPM_PRE_PMD:
  91                snd_soc_component_update_bits(component, AIC32X4_MICBIAS,
  92                                AIC32x4_MICBIAS_MASK, 0);
  93                printk(KERN_DEBUG "%s: Mic Bias will be turned OFF\n",
  94                                __func__);
  95                break;
  96        }
  97
  98        return 0;
  99}
 100
 101
 102static int aic32x4_get_mfp1_gpio(struct snd_kcontrol *kcontrol,
 103        struct snd_ctl_elem_value *ucontrol)
 104{
 105        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 106        u8 val;
 107
 108        val = snd_soc_component_read(component, AIC32X4_DINCTL);
 109
 110        ucontrol->value.integer.value[0] = (val & 0x01);
 111
 112        return 0;
 113};
 114
 115static int aic32x4_set_mfp2_gpio(struct snd_kcontrol *kcontrol,
 116        struct snd_ctl_elem_value *ucontrol)
 117{
 118        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 119        u8 val;
 120        u8 gpio_check;
 121
 122        val = snd_soc_component_read(component, AIC32X4_DOUTCTL);
 123        gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
 124        if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
 125                printk(KERN_ERR "%s: MFP2 is not configure as a GPIO output\n",
 126                        __func__);
 127                return -EINVAL;
 128        }
 129
 130        if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP2_GPIO_OUT_HIGH))
 131                return 0;
 132
 133        if (ucontrol->value.integer.value[0])
 134                val |= ucontrol->value.integer.value[0];
 135        else
 136                val &= ~AIC32X4_MFP2_GPIO_OUT_HIGH;
 137
 138        snd_soc_component_write(component, AIC32X4_DOUTCTL, val);
 139
 140        return 0;
 141};
 142
 143static int aic32x4_get_mfp3_gpio(struct snd_kcontrol *kcontrol,
 144        struct snd_ctl_elem_value *ucontrol)
 145{
 146        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 147        u8 val;
 148
 149        val = snd_soc_component_read(component, AIC32X4_SCLKCTL);
 150
 151        ucontrol->value.integer.value[0] = (val & 0x01);
 152
 153        return 0;
 154};
 155
 156static int aic32x4_set_mfp4_gpio(struct snd_kcontrol *kcontrol,
 157        struct snd_ctl_elem_value *ucontrol)
 158{
 159        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 160        u8 val;
 161        u8 gpio_check;
 162
 163        val = snd_soc_component_read(component, AIC32X4_MISOCTL);
 164        gpio_check = (val & AIC32X4_MFP_GPIO_ENABLED);
 165        if (gpio_check != AIC32X4_MFP_GPIO_ENABLED) {
 166                printk(KERN_ERR "%s: MFP4 is not configure as a GPIO output\n",
 167                        __func__);
 168                return -EINVAL;
 169        }
 170
 171        if (ucontrol->value.integer.value[0] == (val & AIC32X4_MFP5_GPIO_OUT_HIGH))
 172                return 0;
 173
 174        if (ucontrol->value.integer.value[0])
 175                val |= ucontrol->value.integer.value[0];
 176        else
 177                val &= ~AIC32X4_MFP5_GPIO_OUT_HIGH;
 178
 179        snd_soc_component_write(component, AIC32X4_MISOCTL, val);
 180
 181        return 0;
 182};
 183
 184static int aic32x4_get_mfp5_gpio(struct snd_kcontrol *kcontrol,
 185        struct snd_ctl_elem_value *ucontrol)
 186{
 187        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 188        u8 val;
 189
 190        val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
 191        ucontrol->value.integer.value[0] = ((val & 0x2) >> 1);
 192
 193        return 0;
 194};
 195
 196static int aic32x4_set_mfp5_gpio(struct snd_kcontrol *kcontrol,
 197        struct snd_ctl_elem_value *ucontrol)
 198{
 199        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
 200        u8 val;
 201        u8 gpio_check;
 202
 203        val = snd_soc_component_read(component, AIC32X4_GPIOCTL);
 204        gpio_check = (val & AIC32X4_MFP5_GPIO_OUTPUT);
 205        if (gpio_check != AIC32X4_MFP5_GPIO_OUTPUT) {
 206                printk(KERN_ERR "%s: MFP5 is not configure as a GPIO output\n",
 207                        __func__);
 208                return -EINVAL;
 209        }
 210
 211        if (ucontrol->value.integer.value[0] == (val & 0x1))
 212                return 0;
 213
 214        if (ucontrol->value.integer.value[0])
 215                val |= ucontrol->value.integer.value[0];
 216        else
 217                val &= 0xfe;
 218
 219        snd_soc_component_write(component, AIC32X4_GPIOCTL, val);
 220
 221        return 0;
 222};
 223
 224static const struct snd_kcontrol_new aic32x4_mfp1[] = {
 225        SOC_SINGLE_BOOL_EXT("MFP1 GPIO", 0, aic32x4_get_mfp1_gpio, NULL),
 226};
 227
 228static const struct snd_kcontrol_new aic32x4_mfp2[] = {
 229        SOC_SINGLE_BOOL_EXT("MFP2 GPIO", 0, NULL, aic32x4_set_mfp2_gpio),
 230};
 231
 232static const struct snd_kcontrol_new aic32x4_mfp3[] = {
 233        SOC_SINGLE_BOOL_EXT("MFP3 GPIO", 0, aic32x4_get_mfp3_gpio, NULL),
 234};
 235
 236static const struct snd_kcontrol_new aic32x4_mfp4[] = {
 237        SOC_SINGLE_BOOL_EXT("MFP4 GPIO", 0, NULL, aic32x4_set_mfp4_gpio),
 238};
 239
 240static const struct snd_kcontrol_new aic32x4_mfp5[] = {
 241        SOC_SINGLE_BOOL_EXT("MFP5 GPIO", 0, aic32x4_get_mfp5_gpio,
 242                aic32x4_set_mfp5_gpio),
 243};
 244
 245/* 0dB min, 0.5dB steps */
 246static DECLARE_TLV_DB_SCALE(tlv_step_0_5, 0, 50, 0);
 247/* -63.5dB min, 0.5dB steps */
 248static DECLARE_TLV_DB_SCALE(tlv_pcm, -6350, 50, 0);
 249/* -6dB min, 1dB steps */
 250static DECLARE_TLV_DB_SCALE(tlv_driver_gain, -600, 100, 0);
 251/* -12dB min, 0.5dB steps */
 252static DECLARE_TLV_DB_SCALE(tlv_adc_vol, -1200, 50, 0);
 253/* -6dB min, 1dB steps */
 254static DECLARE_TLV_DB_SCALE(tlv_tas_driver_gain, -5850, 50, 0);
 255static DECLARE_TLV_DB_SCALE(tlv_amp_vol, 0, 600, 1);
 256
 257static const char * const lo_cm_text[] = {
 258        "Full Chip", "1.65V",
 259};
 260
 261static SOC_ENUM_SINGLE_DECL(lo_cm_enum, AIC32X4_CMMODE, 3, lo_cm_text);
 262
 263static const char * const ptm_text[] = {
 264        "P3", "P2", "P1",
 265};
 266
 267static SOC_ENUM_SINGLE_DECL(l_ptm_enum, AIC32X4_LPLAYBACK, 2, ptm_text);
 268static SOC_ENUM_SINGLE_DECL(r_ptm_enum, AIC32X4_RPLAYBACK, 2, ptm_text);
 269
 270static const struct snd_kcontrol_new aic32x4_snd_controls[] = {
 271        SOC_DOUBLE_R_S_TLV("PCM Playback Volume", AIC32X4_LDACVOL,
 272                        AIC32X4_RDACVOL, 0, -0x7f, 0x30, 7, 0, tlv_pcm),
 273        SOC_ENUM("DAC Left Playback PowerTune Switch", l_ptm_enum),
 274        SOC_ENUM("DAC Right Playback PowerTune Switch", r_ptm_enum),
 275        SOC_DOUBLE_R_S_TLV("HP Driver Gain Volume", AIC32X4_HPLGAIN,
 276                        AIC32X4_HPRGAIN, 0, -0x6, 0x1d, 5, 0,
 277                        tlv_driver_gain),
 278        SOC_DOUBLE_R_S_TLV("LO Driver Gain Volume", AIC32X4_LOLGAIN,
 279                        AIC32X4_LORGAIN, 0, -0x6, 0x1d, 5, 0,
 280                        tlv_driver_gain),
 281        SOC_DOUBLE_R("HP DAC Playback Switch", AIC32X4_HPLGAIN,
 282                        AIC32X4_HPRGAIN, 6, 0x01, 1),
 283        SOC_DOUBLE_R("LO DAC Playback Switch", AIC32X4_LOLGAIN,
 284                        AIC32X4_LORGAIN, 6, 0x01, 1),
 285        SOC_ENUM("LO Playback Common Mode Switch", lo_cm_enum),
 286        SOC_DOUBLE_R("Mic PGA Switch", AIC32X4_LMICPGAVOL,
 287                        AIC32X4_RMICPGAVOL, 7, 0x01, 1),
 288
 289        SOC_SINGLE("ADCFGA Left Mute Switch", AIC32X4_ADCFGA, 7, 1, 0),
 290        SOC_SINGLE("ADCFGA Right Mute Switch", AIC32X4_ADCFGA, 3, 1, 0),
 291
 292        SOC_DOUBLE_R_S_TLV("ADC Level Volume", AIC32X4_LADCVOL,
 293                        AIC32X4_RADCVOL, 0, -0x18, 0x28, 6, 0, tlv_adc_vol),
 294        SOC_DOUBLE_R_TLV("PGA Level Volume", AIC32X4_LMICPGAVOL,
 295                        AIC32X4_RMICPGAVOL, 0, 0x5f, 0, tlv_step_0_5),
 296
 297        SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
 298
 299        SOC_SINGLE("AGC Left Switch", AIC32X4_LAGC1, 7, 1, 0),
 300        SOC_SINGLE("AGC Right Switch", AIC32X4_RAGC1, 7, 1, 0),
 301        SOC_DOUBLE_R("AGC Target Level", AIC32X4_LAGC1, AIC32X4_RAGC1,
 302                        4, 0x07, 0),
 303        SOC_DOUBLE_R("AGC Gain Hysteresis", AIC32X4_LAGC1, AIC32X4_RAGC1,
 304                        0, 0x03, 0),
 305        SOC_DOUBLE_R("AGC Hysteresis", AIC32X4_LAGC2, AIC32X4_RAGC2,
 306                        6, 0x03, 0),
 307        SOC_DOUBLE_R("AGC Noise Threshold", AIC32X4_LAGC2, AIC32X4_RAGC2,
 308                        1, 0x1F, 0),
 309        SOC_DOUBLE_R("AGC Max PGA", AIC32X4_LAGC3, AIC32X4_RAGC3,
 310                        0, 0x7F, 0),
 311        SOC_DOUBLE_R("AGC Attack Time", AIC32X4_LAGC4, AIC32X4_RAGC4,
 312                        3, 0x1F, 0),
 313        SOC_DOUBLE_R("AGC Decay Time", AIC32X4_LAGC5, AIC32X4_RAGC5,
 314                        3, 0x1F, 0),
 315        SOC_DOUBLE_R("AGC Noise Debounce", AIC32X4_LAGC6, AIC32X4_RAGC6,
 316                        0, 0x1F, 0),
 317        SOC_DOUBLE_R("AGC Signal Debounce", AIC32X4_LAGC7, AIC32X4_RAGC7,
 318                        0, 0x0F, 0),
 319};
 320
 321static const struct snd_kcontrol_new hpl_output_mixer_controls[] = {
 322        SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
 323        SOC_DAPM_SINGLE("IN1_L Switch", AIC32X4_HPLROUTE, 2, 1, 0),
 324};
 325
 326static const struct snd_kcontrol_new hpr_output_mixer_controls[] = {
 327        SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_HPRROUTE, 3, 1, 0),
 328        SOC_DAPM_SINGLE("IN1_R Switch", AIC32X4_HPRROUTE, 2, 1, 0),
 329};
 330
 331static const struct snd_kcontrol_new lol_output_mixer_controls[] = {
 332        SOC_DAPM_SINGLE("L_DAC Switch", AIC32X4_LOLROUTE, 3, 1, 0),
 333};
 334
 335static const struct snd_kcontrol_new lor_output_mixer_controls[] = {
 336        SOC_DAPM_SINGLE("R_DAC Switch", AIC32X4_LORROUTE, 3, 1, 0),
 337};
 338
 339static const char * const resistor_text[] = {
 340        "Off", "10 kOhm", "20 kOhm", "40 kOhm",
 341};
 342
 343/* Left mixer pins */
 344static SOC_ENUM_SINGLE_DECL(in1l_lpga_p_enum, AIC32X4_LMICPGAPIN, 6, resistor_text);
 345static SOC_ENUM_SINGLE_DECL(in2l_lpga_p_enum, AIC32X4_LMICPGAPIN, 4, resistor_text);
 346static SOC_ENUM_SINGLE_DECL(in3l_lpga_p_enum, AIC32X4_LMICPGAPIN, 2, resistor_text);
 347static SOC_ENUM_SINGLE_DECL(in1r_lpga_p_enum, AIC32X4_LMICPGAPIN, 0, resistor_text);
 348
 349static SOC_ENUM_SINGLE_DECL(cml_lpga_n_enum, AIC32X4_LMICPGANIN, 6, resistor_text);
 350static SOC_ENUM_SINGLE_DECL(in2r_lpga_n_enum, AIC32X4_LMICPGANIN, 4, resistor_text);
 351static SOC_ENUM_SINGLE_DECL(in3r_lpga_n_enum, AIC32X4_LMICPGANIN, 2, resistor_text);
 352
 353static const struct snd_kcontrol_new in1l_to_lmixer_controls[] = {
 354        SOC_DAPM_ENUM("IN1_L L+ Switch", in1l_lpga_p_enum),
 355};
 356static const struct snd_kcontrol_new in2l_to_lmixer_controls[] = {
 357        SOC_DAPM_ENUM("IN2_L L+ Switch", in2l_lpga_p_enum),
 358};
 359static const struct snd_kcontrol_new in3l_to_lmixer_controls[] = {
 360        SOC_DAPM_ENUM("IN3_L L+ Switch", in3l_lpga_p_enum),
 361};
 362static const struct snd_kcontrol_new in1r_to_lmixer_controls[] = {
 363        SOC_DAPM_ENUM("IN1_R L+ Switch", in1r_lpga_p_enum),
 364};
 365static const struct snd_kcontrol_new cml_to_lmixer_controls[] = {
 366        SOC_DAPM_ENUM("CM_L L- Switch", cml_lpga_n_enum),
 367};
 368static const struct snd_kcontrol_new in2r_to_lmixer_controls[] = {
 369        SOC_DAPM_ENUM("IN2_R L- Switch", in2r_lpga_n_enum),
 370};
 371static const struct snd_kcontrol_new in3r_to_lmixer_controls[] = {
 372        SOC_DAPM_ENUM("IN3_R L- Switch", in3r_lpga_n_enum),
 373};
 374
 375/*      Right mixer pins */
 376static SOC_ENUM_SINGLE_DECL(in1r_rpga_p_enum, AIC32X4_RMICPGAPIN, 6, resistor_text);
 377static SOC_ENUM_SINGLE_DECL(in2r_rpga_p_enum, AIC32X4_RMICPGAPIN, 4, resistor_text);
 378static SOC_ENUM_SINGLE_DECL(in3r_rpga_p_enum, AIC32X4_RMICPGAPIN, 2, resistor_text);
 379static SOC_ENUM_SINGLE_DECL(in2l_rpga_p_enum, AIC32X4_RMICPGAPIN, 0, resistor_text);
 380static SOC_ENUM_SINGLE_DECL(cmr_rpga_n_enum, AIC32X4_RMICPGANIN, 6, resistor_text);
 381static SOC_ENUM_SINGLE_DECL(in1l_rpga_n_enum, AIC32X4_RMICPGANIN, 4, resistor_text);
 382static SOC_ENUM_SINGLE_DECL(in3l_rpga_n_enum, AIC32X4_RMICPGANIN, 2, resistor_text);
 383
 384static const struct snd_kcontrol_new in1r_to_rmixer_controls[] = {
 385        SOC_DAPM_ENUM("IN1_R R+ Switch", in1r_rpga_p_enum),
 386};
 387static const struct snd_kcontrol_new in2r_to_rmixer_controls[] = {
 388        SOC_DAPM_ENUM("IN2_R R+ Switch", in2r_rpga_p_enum),
 389};
 390static const struct snd_kcontrol_new in3r_to_rmixer_controls[] = {
 391        SOC_DAPM_ENUM("IN3_R R+ Switch", in3r_rpga_p_enum),
 392};
 393static const struct snd_kcontrol_new in2l_to_rmixer_controls[] = {
 394        SOC_DAPM_ENUM("IN2_L R+ Switch", in2l_rpga_p_enum),
 395};
 396static const struct snd_kcontrol_new cmr_to_rmixer_controls[] = {
 397        SOC_DAPM_ENUM("CM_R R- Switch", cmr_rpga_n_enum),
 398};
 399static const struct snd_kcontrol_new in1l_to_rmixer_controls[] = {
 400        SOC_DAPM_ENUM("IN1_L R- Switch", in1l_rpga_n_enum),
 401};
 402static const struct snd_kcontrol_new in3l_to_rmixer_controls[] = {
 403        SOC_DAPM_ENUM("IN3_L R- Switch", in3l_rpga_n_enum),
 404};
 405
 406static const struct snd_soc_dapm_widget aic32x4_dapm_widgets[] = {
 407        SND_SOC_DAPM_DAC("Left DAC", "Left Playback", AIC32X4_DACSETUP, 7, 0),
 408        SND_SOC_DAPM_MIXER("HPL Output Mixer", SND_SOC_NOPM, 0, 0,
 409                           &hpl_output_mixer_controls[0],
 410                           ARRAY_SIZE(hpl_output_mixer_controls)),
 411        SND_SOC_DAPM_PGA("HPL Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
 412
 413        SND_SOC_DAPM_MIXER("LOL Output Mixer", SND_SOC_NOPM, 0, 0,
 414                           &lol_output_mixer_controls[0],
 415                           ARRAY_SIZE(lol_output_mixer_controls)),
 416        SND_SOC_DAPM_PGA("LOL Power", AIC32X4_OUTPWRCTL, 3, 0, NULL, 0),
 417
 418        SND_SOC_DAPM_DAC("Right DAC", "Right Playback", AIC32X4_DACSETUP, 6, 0),
 419        SND_SOC_DAPM_MIXER("HPR Output Mixer", SND_SOC_NOPM, 0, 0,
 420                           &hpr_output_mixer_controls[0],
 421                           ARRAY_SIZE(hpr_output_mixer_controls)),
 422        SND_SOC_DAPM_PGA("HPR Power", AIC32X4_OUTPWRCTL, 4, 0, NULL, 0),
 423        SND_SOC_DAPM_MIXER("LOR Output Mixer", SND_SOC_NOPM, 0, 0,
 424                           &lor_output_mixer_controls[0],
 425                           ARRAY_SIZE(lor_output_mixer_controls)),
 426        SND_SOC_DAPM_PGA("LOR Power", AIC32X4_OUTPWRCTL, 2, 0, NULL, 0),
 427
 428        SND_SOC_DAPM_ADC("Right ADC", "Right Capture", AIC32X4_ADCSETUP, 6, 0),
 429        SND_SOC_DAPM_MUX("IN1_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 430                        in1r_to_rmixer_controls),
 431        SND_SOC_DAPM_MUX("IN2_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 432                        in2r_to_rmixer_controls),
 433        SND_SOC_DAPM_MUX("IN3_R to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 434                        in3r_to_rmixer_controls),
 435        SND_SOC_DAPM_MUX("IN2_L to Right Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 436                        in2l_to_rmixer_controls),
 437        SND_SOC_DAPM_MUX("CM_R to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 438                        cmr_to_rmixer_controls),
 439        SND_SOC_DAPM_MUX("IN1_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 440                        in1l_to_rmixer_controls),
 441        SND_SOC_DAPM_MUX("IN3_L to Right Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 442                        in3l_to_rmixer_controls),
 443
 444        SND_SOC_DAPM_ADC("Left ADC", "Left Capture", AIC32X4_ADCSETUP, 7, 0),
 445        SND_SOC_DAPM_MUX("IN1_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 446                        in1l_to_lmixer_controls),
 447        SND_SOC_DAPM_MUX("IN2_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 448                        in2l_to_lmixer_controls),
 449        SND_SOC_DAPM_MUX("IN3_L to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 450                        in3l_to_lmixer_controls),
 451        SND_SOC_DAPM_MUX("IN1_R to Left Mixer Positive Resistor", SND_SOC_NOPM, 0, 0,
 452                        in1r_to_lmixer_controls),
 453        SND_SOC_DAPM_MUX("CM_L to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 454                        cml_to_lmixer_controls),
 455        SND_SOC_DAPM_MUX("IN2_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 456                        in2r_to_lmixer_controls),
 457        SND_SOC_DAPM_MUX("IN3_R to Left Mixer Negative Resistor", SND_SOC_NOPM, 0, 0,
 458                        in3r_to_lmixer_controls),
 459
 460        SND_SOC_DAPM_SUPPLY("Mic Bias", AIC32X4_MICBIAS, 6, 0, mic_bias_event,
 461                        SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_PRE_PMD),
 462
 463        SND_SOC_DAPM_POST("ADC Reset", aic32x4_reset_adc),
 464
 465        SND_SOC_DAPM_OUTPUT("HPL"),
 466        SND_SOC_DAPM_OUTPUT("HPR"),
 467        SND_SOC_DAPM_OUTPUT("LOL"),
 468        SND_SOC_DAPM_OUTPUT("LOR"),
 469        SND_SOC_DAPM_INPUT("IN1_L"),
 470        SND_SOC_DAPM_INPUT("IN1_R"),
 471        SND_SOC_DAPM_INPUT("IN2_L"),
 472        SND_SOC_DAPM_INPUT("IN2_R"),
 473        SND_SOC_DAPM_INPUT("IN3_L"),
 474        SND_SOC_DAPM_INPUT("IN3_R"),
 475        SND_SOC_DAPM_INPUT("CM_L"),
 476        SND_SOC_DAPM_INPUT("CM_R"),
 477};
 478
 479static const struct snd_soc_dapm_route aic32x4_dapm_routes[] = {
 480        /* Left Output */
 481        {"HPL Output Mixer", "L_DAC Switch", "Left DAC"},
 482        {"HPL Output Mixer", "IN1_L Switch", "IN1_L"},
 483
 484        {"HPL Power", NULL, "HPL Output Mixer"},
 485        {"HPL", NULL, "HPL Power"},
 486
 487        {"LOL Output Mixer", "L_DAC Switch", "Left DAC"},
 488
 489        {"LOL Power", NULL, "LOL Output Mixer"},
 490        {"LOL", NULL, "LOL Power"},
 491
 492        /* Right Output */
 493        {"HPR Output Mixer", "R_DAC Switch", "Right DAC"},
 494        {"HPR Output Mixer", "IN1_R Switch", "IN1_R"},
 495
 496        {"HPR Power", NULL, "HPR Output Mixer"},
 497        {"HPR", NULL, "HPR Power"},
 498
 499        {"LOR Output Mixer", "R_DAC Switch", "Right DAC"},
 500
 501        {"LOR Power", NULL, "LOR Output Mixer"},
 502        {"LOR", NULL, "LOR Power"},
 503
 504        /* Right Input */
 505        {"Right ADC", NULL, "IN1_R to Right Mixer Positive Resistor"},
 506        {"IN1_R to Right Mixer Positive Resistor", "10 kOhm", "IN1_R"},
 507        {"IN1_R to Right Mixer Positive Resistor", "20 kOhm", "IN1_R"},
 508        {"IN1_R to Right Mixer Positive Resistor", "40 kOhm", "IN1_R"},
 509
 510        {"Right ADC", NULL, "IN2_R to Right Mixer Positive Resistor"},
 511        {"IN2_R to Right Mixer Positive Resistor", "10 kOhm", "IN2_R"},
 512        {"IN2_R to Right Mixer Positive Resistor", "20 kOhm", "IN2_R"},
 513        {"IN2_R to Right Mixer Positive Resistor", "40 kOhm", "IN2_R"},
 514
 515        {"Right ADC", NULL, "IN3_R to Right Mixer Positive Resistor"},
 516        {"IN3_R to Right Mixer Positive Resistor", "10 kOhm", "IN3_R"},
 517        {"IN3_R to Right Mixer Positive Resistor", "20 kOhm", "IN3_R"},
 518        {"IN3_R to Right Mixer Positive Resistor", "40 kOhm", "IN3_R"},
 519
 520        {"Right ADC", NULL, "IN2_L to Right Mixer Positive Resistor"},
 521        {"IN2_L to Right Mixer Positive Resistor", "10 kOhm", "IN2_L"},
 522        {"IN2_L to Right Mixer Positive Resistor", "20 kOhm", "IN2_L"},
 523        {"IN2_L to Right Mixer Positive Resistor", "40 kOhm", "IN2_L"},
 524
 525        {"Right ADC", NULL, "CM_R to Right Mixer Negative Resistor"},
 526        {"CM_R to Right Mixer Negative Resistor", "10 kOhm", "CM_R"},
 527        {"CM_R to Right Mixer Negative Resistor", "20 kOhm", "CM_R"},
 528        {"CM_R to Right Mixer Negative Resistor", "40 kOhm", "CM_R"},
 529
 530        {"Right ADC", NULL, "IN1_L to Right Mixer Negative Resistor"},
 531        {"IN1_L to Right Mixer Negative Resistor", "10 kOhm", "IN1_L"},
 532        {"IN1_L to Right Mixer Negative Resistor", "20 kOhm", "IN1_L"},
 533        {"IN1_L to Right Mixer Negative Resistor", "40 kOhm", "IN1_L"},
 534
 535        {"Right ADC", NULL, "IN3_L to Right Mixer Negative Resistor"},
 536        {"IN3_L to Right Mixer Negative Resistor", "10 kOhm", "IN3_L"},
 537        {"IN3_L to Right Mixer Negative Resistor", "20 kOhm", "IN3_L"},
 538        {"IN3_L to Right Mixer Negative Resistor", "40 kOhm", "IN3_L"},
 539
 540        /* Left Input */
 541        {"Left ADC", NULL, "IN1_L to Left Mixer Positive Resistor"},
 542        {"IN1_L to Left Mixer Positive Resistor", "10 kOhm", "IN1_L"},
 543        {"IN1_L to Left Mixer Positive Resistor", "20 kOhm", "IN1_L"},
 544        {"IN1_L to Left Mixer Positive Resistor", "40 kOhm", "IN1_L"},
 545
 546        {"Left ADC", NULL, "IN2_L to Left Mixer Positive Resistor"},
 547        {"IN2_L to Left Mixer Positive Resistor", "10 kOhm", "IN2_L"},
 548        {"IN2_L to Left Mixer Positive Resistor", "20 kOhm", "IN2_L"},
 549        {"IN2_L to Left Mixer Positive Resistor", "40 kOhm", "IN2_L"},
 550
 551        {"Left ADC", NULL, "IN3_L to Left Mixer Positive Resistor"},
 552        {"IN3_L to Left Mixer Positive Resistor", "10 kOhm", "IN3_L"},
 553        {"IN3_L to Left Mixer Positive Resistor", "20 kOhm", "IN3_L"},
 554        {"IN3_L to Left Mixer Positive Resistor", "40 kOhm", "IN3_L"},
 555
 556        {"Left ADC", NULL, "IN1_R to Left Mixer Positive Resistor"},
 557        {"IN1_R to Left Mixer Positive Resistor", "10 kOhm", "IN1_R"},
 558        {"IN1_R to Left Mixer Positive Resistor", "20 kOhm", "IN1_R"},
 559        {"IN1_R to Left Mixer Positive Resistor", "40 kOhm", "IN1_R"},
 560
 561        {"Left ADC", NULL, "CM_L to Left Mixer Negative Resistor"},
 562        {"CM_L to Left Mixer Negative Resistor", "10 kOhm", "CM_L"},
 563        {"CM_L to Left Mixer Negative Resistor", "20 kOhm", "CM_L"},
 564        {"CM_L to Left Mixer Negative Resistor", "40 kOhm", "CM_L"},
 565
 566        {"Left ADC", NULL, "IN2_R to Left Mixer Negative Resistor"},
 567        {"IN2_R to Left Mixer Negative Resistor", "10 kOhm", "IN2_R"},
 568        {"IN2_R to Left Mixer Negative Resistor", "20 kOhm", "IN2_R"},
 569        {"IN2_R to Left Mixer Negative Resistor", "40 kOhm", "IN2_R"},
 570
 571        {"Left ADC", NULL, "IN3_R to Left Mixer Negative Resistor"},
 572        {"IN3_R to Left Mixer Negative Resistor", "10 kOhm", "IN3_R"},
 573        {"IN3_R to Left Mixer Negative Resistor", "20 kOhm", "IN3_R"},
 574        {"IN3_R to Left Mixer Negative Resistor", "40 kOhm", "IN3_R"},
 575};
 576
 577static const struct regmap_range_cfg aic32x4_regmap_pages[] = {
 578        {
 579                .selector_reg = 0,
 580                .selector_mask  = 0xff,
 581                .window_start = 0,
 582                .window_len = 128,
 583                .range_min = 0,
 584                .range_max = AIC32X4_REFPOWERUP,
 585        },
 586};
 587
 588const struct regmap_config aic32x4_regmap_config = {
 589        .max_register = AIC32X4_REFPOWERUP,
 590        .ranges = aic32x4_regmap_pages,
 591        .num_ranges = ARRAY_SIZE(aic32x4_regmap_pages),
 592};
 593EXPORT_SYMBOL(aic32x4_regmap_config);
 594
 595static int aic32x4_set_dai_sysclk(struct snd_soc_dai *codec_dai,
 596                                  int clk_id, unsigned int freq, int dir)
 597{
 598        struct snd_soc_component *component = codec_dai->component;
 599        struct clk *mclk;
 600        struct clk *pll;
 601
 602        pll = devm_clk_get(component->dev, "pll");
 603        if (IS_ERR(pll))
 604                return PTR_ERR(pll);
 605
 606        mclk = clk_get_parent(pll);
 607
 608        return clk_set_rate(mclk, freq);
 609}
 610
 611static int aic32x4_set_dai_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
 612{
 613        struct snd_soc_component *component = codec_dai->component;
 614        u8 iface_reg_1 = 0;
 615        u8 iface_reg_2 = 0;
 616        u8 iface_reg_3 = 0;
 617
 618        /* set master/slave audio interface */
 619        switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
 620        case SND_SOC_DAIFMT_CBM_CFM:
 621                iface_reg_1 |= AIC32X4_BCLKMASTER | AIC32X4_WCLKMASTER;
 622                break;
 623        case SND_SOC_DAIFMT_CBS_CFS:
 624                break;
 625        default:
 626                printk(KERN_ERR "aic32x4: invalid DAI master/slave interface\n");
 627                return -EINVAL;
 628        }
 629
 630        switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
 631        case SND_SOC_DAIFMT_I2S:
 632                break;
 633        case SND_SOC_DAIFMT_DSP_A:
 634                iface_reg_1 |= (AIC32X4_DSP_MODE <<
 635                                AIC32X4_IFACE1_DATATYPE_SHIFT);
 636                iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
 637                iface_reg_2 = 0x01; /* add offset 1 */
 638                break;
 639        case SND_SOC_DAIFMT_DSP_B:
 640                iface_reg_1 |= (AIC32X4_DSP_MODE <<
 641                                AIC32X4_IFACE1_DATATYPE_SHIFT);
 642                iface_reg_3 |= AIC32X4_BCLKINV_MASK; /* invert bit clock */
 643                break;
 644        case SND_SOC_DAIFMT_RIGHT_J:
 645                iface_reg_1 |= (AIC32X4_RIGHT_JUSTIFIED_MODE <<
 646                                AIC32X4_IFACE1_DATATYPE_SHIFT);
 647                break;
 648        case SND_SOC_DAIFMT_LEFT_J:
 649                iface_reg_1 |= (AIC32X4_LEFT_JUSTIFIED_MODE <<
 650                                AIC32X4_IFACE1_DATATYPE_SHIFT);
 651                break;
 652        default:
 653                printk(KERN_ERR "aic32x4: invalid DAI interface format\n");
 654                return -EINVAL;
 655        }
 656
 657        snd_soc_component_update_bits(component, AIC32X4_IFACE1,
 658                                AIC32X4_IFACE1_DATATYPE_MASK |
 659                                AIC32X4_IFACE1_MASTER_MASK, iface_reg_1);
 660        snd_soc_component_update_bits(component, AIC32X4_IFACE2,
 661                                AIC32X4_DATA_OFFSET_MASK, iface_reg_2);
 662        snd_soc_component_update_bits(component, AIC32X4_IFACE3,
 663                                AIC32X4_BCLKINV_MASK, iface_reg_3);
 664
 665        return 0;
 666}
 667
 668static int aic32x4_set_aosr(struct snd_soc_component *component, u8 aosr)
 669{
 670        return snd_soc_component_write(component, AIC32X4_AOSR, aosr);
 671}
 672
 673static int aic32x4_set_dosr(struct snd_soc_component *component, u16 dosr)
 674{
 675        snd_soc_component_write(component, AIC32X4_DOSRMSB, dosr >> 8);
 676        snd_soc_component_write(component, AIC32X4_DOSRLSB,
 677                      (dosr & 0xff));
 678
 679        return 0;
 680}
 681
 682static int aic32x4_set_processing_blocks(struct snd_soc_component *component,
 683                                                u8 r_block, u8 p_block)
 684{
 685        struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 686
 687        if (aic32x4->type == AIC32X4_TYPE_TAS2505) {
 688                if (r_block || p_block > 3)
 689                        return -EINVAL;
 690
 691                snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
 692        } else { /* AIC32x4 */
 693                if (r_block > 18 || p_block > 25)
 694                        return -EINVAL;
 695
 696                snd_soc_component_write(component, AIC32X4_ADCSPB, r_block);
 697                snd_soc_component_write(component, AIC32X4_DACSPB, p_block);
 698        }
 699
 700        return 0;
 701}
 702
 703static int aic32x4_setup_clocks(struct snd_soc_component *component,
 704                                unsigned int sample_rate, unsigned int channels,
 705                                unsigned int bit_depth)
 706{
 707        struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 708        u8 aosr;
 709        u16 dosr;
 710        u8 adc_resource_class, dac_resource_class;
 711        u8 madc, nadc, mdac, ndac, max_nadc, min_mdac, max_ndac;
 712        u8 dosr_increment;
 713        u16 max_dosr, min_dosr;
 714        unsigned long adc_clock_rate, dac_clock_rate;
 715        int ret;
 716
 717        struct clk_bulk_data clocks[] = {
 718                { .id = "pll" },
 719                { .id = "nadc" },
 720                { .id = "madc" },
 721                { .id = "ndac" },
 722                { .id = "mdac" },
 723                { .id = "bdiv" },
 724        };
 725        ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 726        if (ret)
 727                return ret;
 728
 729        if (sample_rate <= 48000) {
 730                aosr = 128;
 731                adc_resource_class = 6;
 732                dac_resource_class = 8;
 733                dosr_increment = 8;
 734                if (aic32x4->type == AIC32X4_TYPE_TAS2505)
 735                        aic32x4_set_processing_blocks(component, 0, 1);
 736                else
 737                        aic32x4_set_processing_blocks(component, 1, 1);
 738        } else if (sample_rate <= 96000) {
 739                aosr = 64;
 740                adc_resource_class = 6;
 741                dac_resource_class = 8;
 742                dosr_increment = 4;
 743                if (aic32x4->type == AIC32X4_TYPE_TAS2505)
 744                        aic32x4_set_processing_blocks(component, 0, 1);
 745                else
 746                        aic32x4_set_processing_blocks(component, 1, 9);
 747        } else if (sample_rate == 192000) {
 748                aosr = 32;
 749                adc_resource_class = 3;
 750                dac_resource_class = 4;
 751                dosr_increment = 2;
 752                if (aic32x4->type == AIC32X4_TYPE_TAS2505)
 753                        aic32x4_set_processing_blocks(component, 0, 1);
 754                else
 755                        aic32x4_set_processing_blocks(component, 13, 19);
 756        } else {
 757                dev_err(component->dev, "Sampling rate not supported\n");
 758                return -EINVAL;
 759        }
 760
 761        madc = DIV_ROUND_UP((32 * adc_resource_class), aosr);
 762        max_dosr = (AIC32X4_MAX_DOSR_FREQ / sample_rate / dosr_increment) *
 763                        dosr_increment;
 764        min_dosr = (AIC32X4_MIN_DOSR_FREQ / sample_rate / dosr_increment) *
 765                        dosr_increment;
 766        max_nadc = AIC32X4_MAX_CODEC_CLKIN_FREQ / (madc * aosr * sample_rate);
 767
 768        for (nadc = max_nadc; nadc > 0; --nadc) {
 769                adc_clock_rate = nadc * madc * aosr * sample_rate;
 770                for (dosr = max_dosr; dosr >= min_dosr;
 771                                dosr -= dosr_increment) {
 772                        min_mdac = DIV_ROUND_UP((32 * dac_resource_class), dosr);
 773                        max_ndac = AIC32X4_MAX_CODEC_CLKIN_FREQ /
 774                                        (min_mdac * dosr * sample_rate);
 775                        for (mdac = min_mdac; mdac <= 128; ++mdac) {
 776                                for (ndac = max_ndac; ndac > 0; --ndac) {
 777                                        dac_clock_rate = ndac * mdac * dosr *
 778                                                        sample_rate;
 779                                        if (dac_clock_rate == adc_clock_rate) {
 780                                                if (clk_round_rate(clocks[0].clk, dac_clock_rate) == 0)
 781                                                        continue;
 782
 783                                                clk_set_rate(clocks[0].clk,
 784                                                        dac_clock_rate);
 785
 786                                                clk_set_rate(clocks[1].clk,
 787                                                        sample_rate * aosr *
 788                                                        madc);
 789                                                clk_set_rate(clocks[2].clk,
 790                                                        sample_rate * aosr);
 791                                                aic32x4_set_aosr(component,
 792                                                        aosr);
 793
 794                                                clk_set_rate(clocks[3].clk,
 795                                                        sample_rate * dosr *
 796                                                        mdac);
 797                                                clk_set_rate(clocks[4].clk,
 798                                                        sample_rate * dosr);
 799                                                aic32x4_set_dosr(component,
 800                                                        dosr);
 801
 802                                                clk_set_rate(clocks[5].clk,
 803                                                        sample_rate * channels *
 804                                                        bit_depth);
 805
 806                                                return 0;
 807                                        }
 808                                }
 809                        }
 810                }
 811        }
 812
 813        dev_err(component->dev,
 814                "Could not set clocks to support sample rate.\n");
 815        return -EINVAL;
 816}
 817
 818static int aic32x4_hw_params(struct snd_pcm_substream *substream,
 819                                 struct snd_pcm_hw_params *params,
 820                                 struct snd_soc_dai *dai)
 821{
 822        struct snd_soc_component *component = dai->component;
 823        struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 824        u8 iface1_reg = 0;
 825        u8 dacsetup_reg = 0;
 826
 827        aic32x4_setup_clocks(component, params_rate(params),
 828                             params_channels(params),
 829                             params_physical_width(params));
 830
 831        switch (params_physical_width(params)) {
 832        case 16:
 833                iface1_reg |= (AIC32X4_WORD_LEN_16BITS <<
 834                                   AIC32X4_IFACE1_DATALEN_SHIFT);
 835                break;
 836        case 20:
 837                iface1_reg |= (AIC32X4_WORD_LEN_20BITS <<
 838                                   AIC32X4_IFACE1_DATALEN_SHIFT);
 839                break;
 840        case 24:
 841                iface1_reg |= (AIC32X4_WORD_LEN_24BITS <<
 842                                   AIC32X4_IFACE1_DATALEN_SHIFT);
 843                break;
 844        case 32:
 845                iface1_reg |= (AIC32X4_WORD_LEN_32BITS <<
 846                                   AIC32X4_IFACE1_DATALEN_SHIFT);
 847                break;
 848        }
 849        snd_soc_component_update_bits(component, AIC32X4_IFACE1,
 850                                AIC32X4_IFACE1_DATALEN_MASK, iface1_reg);
 851
 852        if (params_channels(params) == 1) {
 853                dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2LCHN;
 854        } else {
 855                if (aic32x4->swapdacs)
 856                        dacsetup_reg = AIC32X4_RDAC2LCHN | AIC32X4_LDAC2RCHN;
 857                else
 858                        dacsetup_reg = AIC32X4_LDAC2LCHN | AIC32X4_RDAC2RCHN;
 859        }
 860        snd_soc_component_update_bits(component, AIC32X4_DACSETUP,
 861                                AIC32X4_DAC_CHAN_MASK, dacsetup_reg);
 862
 863        return 0;
 864}
 865
 866static int aic32x4_mute(struct snd_soc_dai *dai, int mute, int direction)
 867{
 868        struct snd_soc_component *component = dai->component;
 869
 870        snd_soc_component_update_bits(component, AIC32X4_DACMUTE,
 871                                AIC32X4_MUTEON, mute ? AIC32X4_MUTEON : 0);
 872
 873        return 0;
 874}
 875
 876static int aic32x4_set_bias_level(struct snd_soc_component *component,
 877                                  enum snd_soc_bias_level level)
 878{
 879        int ret;
 880
 881        struct clk_bulk_data clocks[] = {
 882                { .id = "madc" },
 883                { .id = "mdac" },
 884                { .id = "bdiv" },
 885        };
 886
 887        ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
 888        if (ret)
 889                return ret;
 890
 891        switch (level) {
 892        case SND_SOC_BIAS_ON:
 893                ret = clk_bulk_prepare_enable(ARRAY_SIZE(clocks), clocks);
 894                if (ret) {
 895                        dev_err(component->dev, "Failed to enable clocks\n");
 896                        return ret;
 897                }
 898                break;
 899        case SND_SOC_BIAS_PREPARE:
 900                break;
 901        case SND_SOC_BIAS_STANDBY:
 902                /* Initial cold start */
 903                if (snd_soc_component_get_bias_level(component) == SND_SOC_BIAS_OFF)
 904                        break;
 905
 906                clk_bulk_disable_unprepare(ARRAY_SIZE(clocks), clocks);
 907                break;
 908        case SND_SOC_BIAS_OFF:
 909                break;
 910        }
 911        return 0;
 912}
 913
 914#define AIC32X4_RATES   SNDRV_PCM_RATE_8000_192000
 915#define AIC32X4_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | SNDRV_PCM_FMTBIT_S20_3LE \
 916                         | SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S24_3LE \
 917                         | SNDRV_PCM_FMTBIT_S32_LE)
 918
 919static const struct snd_soc_dai_ops aic32x4_ops = {
 920        .hw_params = aic32x4_hw_params,
 921        .mute_stream = aic32x4_mute,
 922        .set_fmt = aic32x4_set_dai_fmt,
 923        .set_sysclk = aic32x4_set_dai_sysclk,
 924        .no_capture_mute = 1,
 925};
 926
 927static struct snd_soc_dai_driver aic32x4_dai = {
 928        .name = "tlv320aic32x4-hifi",
 929        .playback = {
 930                         .stream_name = "Playback",
 931                         .channels_min = 1,
 932                         .channels_max = 2,
 933                         .rates = AIC32X4_RATES,
 934                         .formats = AIC32X4_FORMATS,},
 935        .capture = {
 936                        .stream_name = "Capture",
 937                        .channels_min = 1,
 938                        .channels_max = 8,
 939                        .rates = AIC32X4_RATES,
 940                        .formats = AIC32X4_FORMATS,},
 941        .ops = &aic32x4_ops,
 942        .symmetric_rate = 1,
 943};
 944
 945static void aic32x4_setup_gpios(struct snd_soc_component *component)
 946{
 947        struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 948
 949        /* setup GPIO functions */
 950        /* MFP1 */
 951        if (aic32x4->setup->gpio_func[0] != AIC32X4_MFPX_DEFAULT_VALUE) {
 952                snd_soc_component_write(component, AIC32X4_DINCTL,
 953                          aic32x4->setup->gpio_func[0]);
 954                snd_soc_add_component_controls(component, aic32x4_mfp1,
 955                        ARRAY_SIZE(aic32x4_mfp1));
 956        }
 957
 958        /* MFP2 */
 959        if (aic32x4->setup->gpio_func[1] != AIC32X4_MFPX_DEFAULT_VALUE) {
 960                snd_soc_component_write(component, AIC32X4_DOUTCTL,
 961                          aic32x4->setup->gpio_func[1]);
 962                snd_soc_add_component_controls(component, aic32x4_mfp2,
 963                        ARRAY_SIZE(aic32x4_mfp2));
 964        }
 965
 966        /* MFP3 */
 967        if (aic32x4->setup->gpio_func[2] != AIC32X4_MFPX_DEFAULT_VALUE) {
 968                snd_soc_component_write(component, AIC32X4_SCLKCTL,
 969                          aic32x4->setup->gpio_func[2]);
 970                snd_soc_add_component_controls(component, aic32x4_mfp3,
 971                        ARRAY_SIZE(aic32x4_mfp3));
 972        }
 973
 974        /* MFP4 */
 975        if (aic32x4->setup->gpio_func[3] != AIC32X4_MFPX_DEFAULT_VALUE) {
 976                snd_soc_component_write(component, AIC32X4_MISOCTL,
 977                          aic32x4->setup->gpio_func[3]);
 978                snd_soc_add_component_controls(component, aic32x4_mfp4,
 979                        ARRAY_SIZE(aic32x4_mfp4));
 980        }
 981
 982        /* MFP5 */
 983        if (aic32x4->setup->gpio_func[4] != AIC32X4_MFPX_DEFAULT_VALUE) {
 984                snd_soc_component_write(component, AIC32X4_GPIOCTL,
 985                          aic32x4->setup->gpio_func[4]);
 986                snd_soc_add_component_controls(component, aic32x4_mfp5,
 987                        ARRAY_SIZE(aic32x4_mfp5));
 988        }
 989}
 990
 991static int aic32x4_component_probe(struct snd_soc_component *component)
 992{
 993        struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
 994        u32 tmp_reg;
 995        int ret;
 996
 997        struct clk_bulk_data clocks[] = {
 998                { .id = "codec_clkin" },
 999                { .id = "pll" },
1000                { .id = "bdiv" },
1001                { .id = "mdac" },
1002        };
1003
1004        ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1005        if (ret)
1006                return ret;
1007
1008        if (aic32x4->setup)
1009                aic32x4_setup_gpios(component);
1010
1011        clk_set_parent(clocks[0].clk, clocks[1].clk);
1012        clk_set_parent(clocks[2].clk, clocks[3].clk);
1013
1014        /* Power platform configuration */
1015        if (aic32x4->power_cfg & AIC32X4_PWR_MICBIAS_2075_LDOIN) {
1016                snd_soc_component_write(component, AIC32X4_MICBIAS,
1017                                AIC32X4_MICBIAS_LDOIN | AIC32X4_MICBIAS_2075V);
1018        }
1019        if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1020                snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1021
1022        tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1023                        AIC32X4_LDOCTLEN : 0;
1024        snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1025
1026        tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1027        if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1028                tmp_reg |= AIC32X4_LDOIN_18_36;
1029        if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1030                tmp_reg |= AIC32X4_LDOIN2HP;
1031        snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1032
1033        /* Mic PGA routing */
1034        if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_LMIC_IN2R_10K)
1035                snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1036                                AIC32X4_LMICPGANIN_IN2R_10K);
1037        else
1038                snd_soc_component_write(component, AIC32X4_LMICPGANIN,
1039                                AIC32X4_LMICPGANIN_CM1L_10K);
1040        if (aic32x4->micpga_routing & AIC32X4_MICPGA_ROUTE_RMIC_IN1L_10K)
1041                snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1042                                AIC32X4_RMICPGANIN_IN1L_10K);
1043        else
1044                snd_soc_component_write(component, AIC32X4_RMICPGANIN,
1045                                AIC32X4_RMICPGANIN_CM1R_10K);
1046
1047        /*
1048         * Workaround: for an unknown reason, the ADC needs to be powered up
1049         * and down for the first capture to work properly. It seems related to
1050         * a HW BUG or some kind of behavior not documented in the datasheet.
1051         */
1052        tmp_reg = snd_soc_component_read(component, AIC32X4_ADCSETUP);
1053        snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg |
1054                                AIC32X4_LADC_EN | AIC32X4_RADC_EN);
1055        snd_soc_component_write(component, AIC32X4_ADCSETUP, tmp_reg);
1056
1057        /*
1058         * Enable the fast charging feature and ensure the needed 40ms ellapsed
1059         * before using the analog circuits.
1060         */
1061        snd_soc_component_write(component, AIC32X4_REFPOWERUP,
1062                                AIC32X4_REFPOWERUP_40MS);
1063        msleep(40);
1064
1065        return 0;
1066}
1067
1068static const struct snd_soc_component_driver soc_component_dev_aic32x4 = {
1069        .probe                  = aic32x4_component_probe,
1070        .set_bias_level         = aic32x4_set_bias_level,
1071        .controls               = aic32x4_snd_controls,
1072        .num_controls           = ARRAY_SIZE(aic32x4_snd_controls),
1073        .dapm_widgets           = aic32x4_dapm_widgets,
1074        .num_dapm_widgets       = ARRAY_SIZE(aic32x4_dapm_widgets),
1075        .dapm_routes            = aic32x4_dapm_routes,
1076        .num_dapm_routes        = ARRAY_SIZE(aic32x4_dapm_routes),
1077        .suspend_bias_off       = 1,
1078        .idle_bias_on           = 1,
1079        .use_pmdown_time        = 1,
1080        .endianness             = 1,
1081        .non_legacy_dai_naming  = 1,
1082};
1083
1084static const struct snd_kcontrol_new aic32x4_tas2505_snd_controls[] = {
1085        SOC_SINGLE_S8_TLV("PCM Playback Volume",
1086                          AIC32X4_LDACVOL, -0x7f, 0x30, tlv_pcm),
1087        SOC_ENUM("DAC Playback PowerTune Switch", l_ptm_enum),
1088
1089        SOC_SINGLE_TLV("HP Driver Gain Volume",
1090                        AIC32X4_HPLGAIN, 0, 0x74, 1, tlv_tas_driver_gain),
1091        SOC_SINGLE("HP DAC Playback Switch", AIC32X4_HPLGAIN, 6, 1, 1),
1092
1093        SOC_SINGLE_TLV("Speaker Driver Playback Volume",
1094                        TAS2505_SPKVOL1, 0, 0x74, 1, tlv_tas_driver_gain),
1095        SOC_SINGLE_TLV("Speaker Amplifier Playback Volume",
1096                        TAS2505_SPKVOL2, 4, 5, 0, tlv_amp_vol),
1097
1098        SOC_SINGLE("Auto-mute Switch", AIC32X4_DACMUTE, 4, 7, 0),
1099};
1100
1101static const struct snd_kcontrol_new hp_output_mixer_controls[] = {
1102        SOC_DAPM_SINGLE("DAC Switch", AIC32X4_HPLROUTE, 3, 1, 0),
1103};
1104
1105static const struct snd_soc_dapm_widget aic32x4_tas2505_dapm_widgets[] = {
1106        SND_SOC_DAPM_DAC("DAC", "Playback", AIC32X4_DACSETUP, 7, 0),
1107        SND_SOC_DAPM_MIXER("HP Output Mixer", SND_SOC_NOPM, 0, 0,
1108                           &hp_output_mixer_controls[0],
1109                           ARRAY_SIZE(hp_output_mixer_controls)),
1110        SND_SOC_DAPM_PGA("HP Power", AIC32X4_OUTPWRCTL, 5, 0, NULL, 0),
1111
1112        SND_SOC_DAPM_PGA("Speaker Driver", TAS2505_SPK, 1, 0, NULL, 0),
1113
1114        SND_SOC_DAPM_OUTPUT("HP"),
1115        SND_SOC_DAPM_OUTPUT("Speaker"),
1116};
1117
1118static const struct snd_soc_dapm_route aic32x4_tas2505_dapm_routes[] = {
1119        /* Left Output */
1120        {"HP Output Mixer", "DAC Switch", "DAC"},
1121
1122        {"HP Power", NULL, "HP Output Mixer"},
1123        {"HP", NULL, "HP Power"},
1124
1125        {"Speaker Driver", NULL, "DAC"},
1126        {"Speaker", NULL, "Speaker Driver"},
1127};
1128
1129static struct snd_soc_dai_driver aic32x4_tas2505_dai = {
1130        .name = "tas2505-hifi",
1131        .playback = {
1132                         .stream_name = "Playback",
1133                         .channels_min = 1,
1134                         .channels_max = 1,
1135                         .rates = SNDRV_PCM_RATE_8000_96000,
1136                         .formats = AIC32X4_FORMATS,},
1137        .ops = &aic32x4_ops,
1138        .symmetric_rate = 1,
1139};
1140
1141static int aic32x4_tas2505_component_probe(struct snd_soc_component *component)
1142{
1143        struct aic32x4_priv *aic32x4 = snd_soc_component_get_drvdata(component);
1144        u32 tmp_reg;
1145        int ret;
1146
1147        struct clk_bulk_data clocks[] = {
1148                { .id = "codec_clkin" },
1149                { .id = "pll" },
1150                { .id = "bdiv" },
1151                { .id = "mdac" },
1152        };
1153
1154        ret = devm_clk_bulk_get(component->dev, ARRAY_SIZE(clocks), clocks);
1155        if (ret)
1156                return ret;
1157
1158        if (aic32x4->setup)
1159                aic32x4_setup_gpios(component);
1160
1161        clk_set_parent(clocks[0].clk, clocks[1].clk);
1162        clk_set_parent(clocks[2].clk, clocks[3].clk);
1163
1164        /* Power platform configuration */
1165        if (aic32x4->power_cfg & AIC32X4_PWR_AVDD_DVDD_WEAK_DISABLE)
1166                snd_soc_component_write(component, AIC32X4_PWRCFG, AIC32X4_AVDDWEAKDISABLE);
1167
1168        tmp_reg = (aic32x4->power_cfg & AIC32X4_PWR_AIC32X4_LDO_ENABLE) ?
1169                        AIC32X4_LDOCTLEN : 0;
1170        snd_soc_component_write(component, AIC32X4_LDOCTL, tmp_reg);
1171
1172        tmp_reg = snd_soc_component_read(component, AIC32X4_CMMODE);
1173        if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_LDOIN_RANGE_18_36)
1174                tmp_reg |= AIC32X4_LDOIN_18_36;
1175        if (aic32x4->power_cfg & AIC32X4_PWR_CMMODE_HP_LDOIN_POWERED)
1176                tmp_reg |= AIC32X4_LDOIN2HP;
1177        snd_soc_component_write(component, AIC32X4_CMMODE, tmp_reg);
1178
1179        /*
1180         * Enable the fast charging feature and ensure the needed 40ms ellapsed
1181         * before using the analog circuits.
1182         */
1183        snd_soc_component_write(component, TAS2505_REFPOWERUP,
1184                                AIC32X4_REFPOWERUP_40MS);
1185        msleep(40);
1186
1187        return 0;
1188}
1189
1190static const struct snd_soc_component_driver soc_component_dev_aic32x4_tas2505 = {
1191        .probe                  = aic32x4_tas2505_component_probe,
1192        .set_bias_level         = aic32x4_set_bias_level,
1193        .controls               = aic32x4_tas2505_snd_controls,
1194        .num_controls           = ARRAY_SIZE(aic32x4_tas2505_snd_controls),
1195        .dapm_widgets           = aic32x4_tas2505_dapm_widgets,
1196        .num_dapm_widgets       = ARRAY_SIZE(aic32x4_tas2505_dapm_widgets),
1197        .dapm_routes            = aic32x4_tas2505_dapm_routes,
1198        .num_dapm_routes        = ARRAY_SIZE(aic32x4_tas2505_dapm_routes),
1199        .suspend_bias_off       = 1,
1200        .idle_bias_on           = 1,
1201        .use_pmdown_time        = 1,
1202        .endianness             = 1,
1203        .non_legacy_dai_naming  = 1,
1204};
1205
1206static int aic32x4_parse_dt(struct aic32x4_priv *aic32x4,
1207                struct device_node *np)
1208{
1209        struct aic32x4_setup_data *aic32x4_setup;
1210        int ret;
1211
1212        aic32x4_setup = devm_kzalloc(aic32x4->dev, sizeof(*aic32x4_setup),
1213                                                        GFP_KERNEL);
1214        if (!aic32x4_setup)
1215                return -ENOMEM;
1216
1217        ret = of_property_match_string(np, "clock-names", "mclk");
1218        if (ret < 0)
1219                return -EINVAL;
1220        aic32x4->mclk_name = of_clk_get_parent_name(np, ret);
1221
1222        aic32x4->swapdacs = false;
1223        aic32x4->micpga_routing = 0;
1224        aic32x4->rstn_gpio = of_get_named_gpio(np, "reset-gpios", 0);
1225
1226        if (of_property_read_u32_array(np, "aic32x4-gpio-func",
1227                                aic32x4_setup->gpio_func, 5) >= 0)
1228                aic32x4->setup = aic32x4_setup;
1229        return 0;
1230}
1231
1232static void aic32x4_disable_regulators(struct aic32x4_priv *aic32x4)
1233{
1234        regulator_disable(aic32x4->supply_iov);
1235
1236        if (!IS_ERR(aic32x4->supply_ldo))
1237                regulator_disable(aic32x4->supply_ldo);
1238
1239        if (!IS_ERR(aic32x4->supply_dv))
1240                regulator_disable(aic32x4->supply_dv);
1241
1242        if (!IS_ERR(aic32x4->supply_av))
1243                regulator_disable(aic32x4->supply_av);
1244}
1245
1246static int aic32x4_setup_regulators(struct device *dev,
1247                struct aic32x4_priv *aic32x4)
1248{
1249        int ret = 0;
1250
1251        aic32x4->supply_ldo = devm_regulator_get_optional(dev, "ldoin");
1252        aic32x4->supply_iov = devm_regulator_get(dev, "iov");
1253        aic32x4->supply_dv = devm_regulator_get_optional(dev, "dv");
1254        aic32x4->supply_av = devm_regulator_get_optional(dev, "av");
1255
1256        /* Check if the regulator requirements are fulfilled */
1257
1258        if (IS_ERR(aic32x4->supply_iov)) {
1259                dev_err(dev, "Missing supply 'iov'\n");
1260                return PTR_ERR(aic32x4->supply_iov);
1261        }
1262
1263        if (IS_ERR(aic32x4->supply_ldo)) {
1264                if (PTR_ERR(aic32x4->supply_ldo) == -EPROBE_DEFER)
1265                        return -EPROBE_DEFER;
1266
1267                if (IS_ERR(aic32x4->supply_dv)) {
1268                        dev_err(dev, "Missing supply 'dv' or 'ldoin'\n");
1269                        return PTR_ERR(aic32x4->supply_dv);
1270                }
1271                if (IS_ERR(aic32x4->supply_av)) {
1272                        dev_err(dev, "Missing supply 'av' or 'ldoin'\n");
1273                        return PTR_ERR(aic32x4->supply_av);
1274                }
1275        } else {
1276                if (PTR_ERR(aic32x4->supply_dv) == -EPROBE_DEFER)
1277                        return -EPROBE_DEFER;
1278                if (PTR_ERR(aic32x4->supply_av) == -EPROBE_DEFER)
1279                        return -EPROBE_DEFER;
1280        }
1281
1282        ret = regulator_enable(aic32x4->supply_iov);
1283        if (ret) {
1284                dev_err(dev, "Failed to enable regulator iov\n");
1285                return ret;
1286        }
1287
1288        if (!IS_ERR(aic32x4->supply_ldo)) {
1289                ret = regulator_enable(aic32x4->supply_ldo);
1290                if (ret) {
1291                        dev_err(dev, "Failed to enable regulator ldo\n");
1292                        goto error_ldo;
1293                }
1294        }
1295
1296        if (!IS_ERR(aic32x4->supply_dv)) {
1297                ret = regulator_enable(aic32x4->supply_dv);
1298                if (ret) {
1299                        dev_err(dev, "Failed to enable regulator dv\n");
1300                        goto error_dv;
1301                }
1302        }
1303
1304        if (!IS_ERR(aic32x4->supply_av)) {
1305                ret = regulator_enable(aic32x4->supply_av);
1306                if (ret) {
1307                        dev_err(dev, "Failed to enable regulator av\n");
1308                        goto error_av;
1309                }
1310        }
1311
1312        if (!IS_ERR(aic32x4->supply_ldo) && IS_ERR(aic32x4->supply_av))
1313                aic32x4->power_cfg |= AIC32X4_PWR_AIC32X4_LDO_ENABLE;
1314
1315        return 0;
1316
1317error_av:
1318        if (!IS_ERR(aic32x4->supply_dv))
1319                regulator_disable(aic32x4->supply_dv);
1320
1321error_dv:
1322        if (!IS_ERR(aic32x4->supply_ldo))
1323                regulator_disable(aic32x4->supply_ldo);
1324
1325error_ldo:
1326        regulator_disable(aic32x4->supply_iov);
1327        return ret;
1328}
1329
1330int aic32x4_probe(struct device *dev, struct regmap *regmap)
1331{
1332        struct aic32x4_priv *aic32x4;
1333        struct aic32x4_pdata *pdata = dev->platform_data;
1334        struct device_node *np = dev->of_node;
1335        int ret;
1336
1337        if (IS_ERR(regmap))
1338                return PTR_ERR(regmap);
1339
1340        aic32x4 = devm_kzalloc(dev, sizeof(struct aic32x4_priv),
1341                                   GFP_KERNEL);
1342        if (aic32x4 == NULL)
1343                return -ENOMEM;
1344
1345        aic32x4->dev = dev;
1346        aic32x4->type = (enum aic32x4_type)dev_get_drvdata(dev);
1347
1348        dev_set_drvdata(dev, aic32x4);
1349
1350        if (pdata) {
1351                aic32x4->power_cfg = pdata->power_cfg;
1352                aic32x4->swapdacs = pdata->swapdacs;
1353                aic32x4->micpga_routing = pdata->micpga_routing;
1354                aic32x4->rstn_gpio = pdata->rstn_gpio;
1355                aic32x4->mclk_name = "mclk";
1356        } else if (np) {
1357                ret = aic32x4_parse_dt(aic32x4, np);
1358                if (ret) {
1359                        dev_err(dev, "Failed to parse DT node\n");
1360                        return ret;
1361                }
1362        } else {
1363                aic32x4->power_cfg = 0;
1364                aic32x4->swapdacs = false;
1365                aic32x4->micpga_routing = 0;
1366                aic32x4->rstn_gpio = -1;
1367                aic32x4->mclk_name = "mclk";
1368        }
1369
1370        if (gpio_is_valid(aic32x4->rstn_gpio)) {
1371                ret = devm_gpio_request_one(dev, aic32x4->rstn_gpio,
1372                                GPIOF_OUT_INIT_LOW, "tlv320aic32x4 rstn");
1373                if (ret != 0)
1374                        return ret;
1375        }
1376
1377        ret = aic32x4_setup_regulators(dev, aic32x4);
1378        if (ret) {
1379                dev_err(dev, "Failed to setup regulators\n");
1380                return ret;
1381        }
1382
1383        if (gpio_is_valid(aic32x4->rstn_gpio)) {
1384                ndelay(10);
1385                gpio_set_value_cansleep(aic32x4->rstn_gpio, 1);
1386                mdelay(1);
1387        }
1388
1389        ret = regmap_write(regmap, AIC32X4_RESET, 0x01);
1390        if (ret)
1391                goto err_disable_regulators;
1392
1393        ret = aic32x4_register_clocks(dev, aic32x4->mclk_name);
1394        if (ret)
1395                goto err_disable_regulators;
1396
1397        switch (aic32x4->type) {
1398        case AIC32X4_TYPE_TAS2505:
1399                ret = devm_snd_soc_register_component(dev,
1400                        &soc_component_dev_aic32x4_tas2505, &aic32x4_tas2505_dai, 1);
1401                break;
1402        default:
1403                ret = devm_snd_soc_register_component(dev,
1404                        &soc_component_dev_aic32x4, &aic32x4_dai, 1);
1405        }
1406
1407        if (ret) {
1408                dev_err(dev, "Failed to register component\n");
1409                goto err_disable_regulators;
1410        }
1411
1412        return 0;
1413
1414err_disable_regulators:
1415        aic32x4_disable_regulators(aic32x4);
1416
1417        return ret;
1418}
1419EXPORT_SYMBOL(aic32x4_probe);
1420
1421int aic32x4_remove(struct device *dev)
1422{
1423        struct aic32x4_priv *aic32x4 = dev_get_drvdata(dev);
1424
1425        aic32x4_disable_regulators(aic32x4);
1426
1427        return 0;
1428}
1429EXPORT_SYMBOL(aic32x4_remove);
1430
1431MODULE_DESCRIPTION("ASoC tlv320aic32x4 codec driver");
1432MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
1433MODULE_LICENSE("GPL");
1434