// SPDX-License-Identifier: GPL-2.0-only
/*
 * rt5677.c  --  RT5677 ALSA SoC audio codec driver
 *
 * Copyright 2013 Realtek Semiconductor Corp.
 * Author: Oder Chiou <oder_chiou@realtek.com>
 */

#include <linux/acpi.h>
#include <linux/fs.h>
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/init.h>
#include <linux/delay.h>
#include <linux/pm.h>
#include <linux/regmap.h>
#include <linux/i2c.h>
#include <linux/platform_device.h>
#include <linux/spi/spi.h>
#include <linux/firmware.h>
#include <linux/of_device.h>
#include <linux/property.h>
#include <linux/irq.h>
#include <linux/interrupt.h>
#include <linux/irqdomain.h>
#include <linux/workqueue.h>
#include <sound/core.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <sound/soc-dapm.h>
#include <sound/initval.h>
#include <sound/tlv.h>

#include "rl6231.h"
#include "rt5677.h"
#include "rt5677-spi.h"

#define RT5677_DEVICE_ID 0x6327

/* Register controlling boot vector */
#define RT5677_DSP_BOOT_VECTOR          0x1801f090
#define RT5677_MODEL_ADDR               0x5FFC9800

#define RT5677_PR_RANGE_BASE (0xff + 1)
#define RT5677_PR_SPACING 0x100

#define RT5677_PR_BASE (RT5677_PR_RANGE_BASE + (0 * RT5677_PR_SPACING))

static const struct regmap_range_cfg rt5677_ranges[] = {
        {
                .name = "PR",
                .range_min = RT5677_PR_BASE,
                .range_max = RT5677_PR_BASE + 0xfd,
                .selector_reg = RT5677_PRIV_INDEX,
                .selector_mask = 0xff,
                .selector_shift = 0x0,
                .window_start = RT5677_PRIV_DATA,
                .window_len = 0x1,
        },
};

static const struct reg_sequence init_list[] = {
        {RT5677_ASRC_12,        0x0018},
        {RT5677_PR_BASE + 0x3d, 0x364d},
        {RT5677_PR_BASE + 0x17, 0x4fc0},
        {RT5677_PR_BASE + 0x13, 0x0312},
        {RT5677_PR_BASE + 0x1e, 0x0000},
        {RT5677_PR_BASE + 0x12, 0x0eaa},
        {RT5677_PR_BASE + 0x14, 0x018a},
        {RT5677_PR_BASE + 0x15, 0x0490},
        {RT5677_PR_BASE + 0x38, 0x0f71},
        {RT5677_PR_BASE + 0x39, 0x0f71},
};
#define RT5677_INIT_REG_LEN ARRAY_SIZE(init_list)

static const struct reg_default rt5677_reg[] = {
        {RT5677_RESET                   , 0x0000},
        {RT5677_LOUT1                   , 0xa800},
        {RT5677_IN1                     , 0x0000},
        {RT5677_MICBIAS                 , 0x0000},
        {RT5677_SLIMBUS_PARAM           , 0x0000},
        {RT5677_SLIMBUS_RX              , 0x0000},
        {RT5677_SLIMBUS_CTRL            , 0x0000},
        {RT5677_SIDETONE_CTRL           , 0x000b},
        {RT5677_ANA_DAC1_2_3_SRC        , 0x0000},
        {RT5677_IF_DSP_DAC3_4_MIXER     , 0x1111},
        {RT5677_DAC4_DIG_VOL            , 0xafaf},
        {RT5677_DAC3_DIG_VOL            , 0xafaf},
        {RT5677_DAC1_DIG_VOL            , 0xafaf},
        {RT5677_DAC2_DIG_VOL            , 0xafaf},
        {RT5677_IF_DSP_DAC2_MIXER       , 0x0011},
        {RT5677_STO1_ADC_DIG_VOL        , 0x2f2f},
        {RT5677_MONO_ADC_DIG_VOL        , 0x2f2f},
        {RT5677_STO1_2_ADC_BST          , 0x0000},
        {RT5677_STO2_ADC_DIG_VOL        , 0x2f2f},
        {RT5677_ADC_BST_CTRL2           , 0x0000},
        {RT5677_STO3_4_ADC_BST          , 0x0000},
        {RT5677_STO3_ADC_DIG_VOL        , 0x2f2f},
        {RT5677_STO4_ADC_DIG_VOL        , 0x2f2f},
        {RT5677_STO4_ADC_MIXER          , 0xd4c0},
        {RT5677_STO3_ADC_MIXER          , 0xd4c0},
        {RT5677_STO2_ADC_MIXER          , 0xd4c0},
        {RT5677_STO1_ADC_MIXER          , 0xd4c0},
        {RT5677_MONO_ADC_MIXER          , 0xd4d1},
        {RT5677_ADC_IF_DSP_DAC1_MIXER   , 0x8080},
        {RT5677_STO1_DAC_MIXER          , 0xaaaa},
        {RT5677_MONO_DAC_MIXER          , 0xaaaa},
        {RT5677_DD1_MIXER               , 0xaaaa},
        {RT5677_DD2_MIXER               , 0xaaaa},
        {RT5677_IF3_DATA                , 0x0000},
        {RT5677_IF4_DATA                , 0x0000},
        {RT5677_PDM_OUT_CTRL            , 0x8888},
        {RT5677_PDM_DATA_CTRL1          , 0x0000},
        {RT5677_PDM_DATA_CTRL2          , 0x0000},
        {RT5677_PDM1_DATA_CTRL2         , 0x0000},
        {RT5677_PDM1_DATA_CTRL3         , 0x0000},
        {RT5677_PDM1_DATA_CTRL4         , 0x0000},
        {RT5677_PDM2_DATA_CTRL2         , 0x0000},
        {RT5677_PDM2_DATA_CTRL3         , 0x0000},
        {RT5677_PDM2_DATA_CTRL4         , 0x0000},
        {RT5677_TDM1_CTRL1              , 0x0300},
        {RT5677_TDM1_CTRL2              , 0x0000},
        {RT5677_TDM1_CTRL3              , 0x4000},
        {RT5677_TDM1_CTRL4              , 0x0123},
        {RT5677_TDM1_CTRL5              , 0x4567},
        {RT5677_TDM2_CTRL1              , 0x0300},
        {RT5677_TDM2_CTRL2              , 0x0000},
        {RT5677_TDM2_CTRL3              , 0x4000},
        {RT5677_TDM2_CTRL4              , 0x0123},
        {RT5677_TDM2_CTRL5              , 0x4567},
        {RT5677_I2C_MASTER_CTRL1        , 0x0001},
        {RT5677_I2C_MASTER_CTRL2        , 0x0000},
        {RT5677_I2C_MASTER_CTRL3        , 0x0000},
        {RT5677_I2C_MASTER_CTRL4        , 0x0000},
        {RT5677_I2C_MASTER_CTRL5        , 0x0000},
        {RT5677_I2C_MASTER_CTRL6        , 0x0000},
        {RT5677_I2C_MASTER_CTRL7        , 0x0000},
        {RT5677_I2C_MASTER_CTRL8        , 0x0000},
        {RT5677_DMIC_CTRL1              , 0x1505},
        {RT5677_DMIC_CTRL2              , 0x0055},
        {RT5677_HAP_GENE_CTRL1          , 0x0111},
        {RT5677_HAP_GENE_CTRL2          , 0x0064},
        {RT5677_HAP_GENE_CTRL3          , 0xef0e},
        {RT5677_HAP_GENE_CTRL4          , 0xf0f0},
        {RT5677_HAP_GENE_CTRL5          , 0xef0e},
        {RT5677_HAP_GENE_CTRL6          , 0xf0f0},
        {RT5677_HAP_GENE_CTRL7          , 0xef0e},
        {RT5677_HAP_GENE_CTRL8          , 0xf0f0},
        {RT5677_HAP_GENE_CTRL9          , 0xf000},
        {RT5677_HAP_GENE_CTRL10         , 0x0000},
        {RT5677_PWR_DIG1                , 0x0000},
        {RT5677_PWR_DIG2                , 0x0000},
        {RT5677_PWR_ANLG1               , 0x0055},
        {RT5677_PWR_ANLG2               , 0x0000},
        {RT5677_PWR_DSP1                , 0x0001},
        {RT5677_PWR_DSP_ST              , 0x0000},
        {RT5677_PWR_DSP2                , 0x0000},
        {RT5677_ADC_DAC_HPF_CTRL1       , 0x0e00},
        {RT5677_PRIV_INDEX              , 0x0000},
        {RT5677_PRIV_DATA               , 0x0000},
        {RT5677_I2S4_SDP                , 0x8000},
        {RT5677_I2S1_SDP                , 0x8000},
        {RT5677_I2S2_SDP                , 0x8000},
        {RT5677_I2S3_SDP                , 0x8000},
        {RT5677_CLK_TREE_CTRL1          , 0x1111},
        {RT5677_CLK_TREE_CTRL2          , 0x1111},
        {RT5677_CLK_TREE_CTRL3          , 0x0000},
        {RT5677_PLL1_CTRL1              , 0x0000},
        {RT5677_PLL1_CTRL2              , 0x0000},
        {RT5677_PLL2_CTRL1              , 0x0c60},
        {RT5677_PLL2_CTRL2              , 0x2000},
        {RT5677_GLB_CLK1                , 0x0000},
        {RT5677_GLB_CLK2                , 0x0000},
        {RT5677_ASRC_1                  , 0x0000},
        {RT5677_ASRC_2                  , 0x0000},
        {RT5677_ASRC_3                  , 0x0000},
        {RT5677_ASRC_4                  , 0x0000},
        {RT5677_ASRC_5                  , 0x0000},
        {RT5677_ASRC_6                  , 0x0000},
        {RT5677_ASRC_7                  , 0x0000},
        {RT5677_ASRC_8                  , 0x0000},
        {RT5677_ASRC_9                  , 0x0000},
        {RT5677_ASRC_10                 , 0x0000},
        {RT5677_ASRC_11                 , 0x0000},
        {RT5677_ASRC_12                 , 0x0018},
        {RT5677_ASRC_13                 , 0x0000},
        {RT5677_ASRC_14                 , 0x0000},
        {RT5677_ASRC_15                 , 0x0000},
        {RT5677_ASRC_16                 , 0x0000},
        {RT5677_ASRC_17                 , 0x0000},
        {RT5677_ASRC_18                 , 0x0000},
        {RT5677_ASRC_19                 , 0x0000},
        {RT5677_ASRC_20                 , 0x0000},
        {RT5677_ASRC_21                 , 0x000c},
        {RT5677_ASRC_22                 , 0x0000},
        {RT5677_ASRC_23                 , 0x0000},
        {RT5677_VAD_CTRL1               , 0x2184},
        {RT5677_VAD_CTRL2               , 0x010a},
        {RT5677_VAD_CTRL3               , 0x0aea},
        {RT5677_VAD_CTRL4               , 0x000c},
        {RT5677_VAD_CTRL5               , 0x0000},
        {RT5677_DSP_INB_CTRL1           , 0x0000},
        {RT5677_DSP_INB_CTRL2           , 0x0000},
        {RT5677_DSP_IN_OUTB_CTRL        , 0x0000},
        {RT5677_DSP_OUTB0_1_DIG_VOL     , 0x2f2f},
        {RT5677_DSP_OUTB2_3_DIG_VOL     , 0x2f2f},
        {RT5677_DSP_OUTB4_5_DIG_VOL     , 0x2f2f},
        {RT5677_DSP_OUTB6_7_DIG_VOL     , 0x2f2f},
        {RT5677_ADC_EQ_CTRL1            , 0x6000},
        {RT5677_ADC_EQ_CTRL2            , 0x0000},
        {RT5677_EQ_CTRL1                , 0xc000},
        {RT5677_EQ_CTRL2                , 0x0000},
        {RT5677_EQ_CTRL3                , 0x0000},
        {RT5677_SOFT_VOL_ZERO_CROSS1    , 0x0009},
        {RT5677_JD_CTRL1                , 0x0000},
        {RT5677_JD_CTRL2                , 0x0000},
        {RT5677_JD_CTRL3                , 0x0000},
        {RT5677_IRQ_CTRL1               , 0x0000},
        {RT5677_IRQ_CTRL2               , 0x0000},
        {RT5677_GPIO_ST                 , 0x0000},
        {RT5677_GPIO_CTRL1              , 0x0000},
        {RT5677_GPIO_CTRL2              , 0x0000},
        {RT5677_GPIO_CTRL3              , 0x0000},
        {RT5677_STO1_ADC_HI_FILTER1     , 0xb320},
        {RT5677_STO1_ADC_HI_FILTER2     , 0x0000},
        {RT5677_MONO_ADC_HI_FILTER1     , 0xb300},
        {RT5677_MONO_ADC_HI_FILTER2     , 0x0000},
        {RT5677_STO2_ADC_HI_FILTER1     , 0xb300},
        {RT5677_STO2_ADC_HI_FILTER2     , 0x0000},
        {RT5677_STO3_ADC_HI_FILTER1     , 0xb300},
        {RT5677_STO3_ADC_HI_FILTER2     , 0x0000},
        {RT5677_STO4_ADC_HI_FILTER1     , 0xb300},
        {RT5677_STO4_ADC_HI_FILTER2     , 0x0000},
        {RT5677_MB_DRC_CTRL1            , 0x0f20},
        {RT5677_DRC1_CTRL1              , 0x001f},
        {RT5677_DRC1_CTRL2              , 0x020c},
        {RT5677_DRC1_CTRL3              , 0x1f00},
        {RT5677_DRC1_CTRL4              , 0x0000},
        {RT5677_DRC1_CTRL5              , 0x0000},
        {RT5677_DRC1_CTRL6              , 0x0029},
        {RT5677_DRC2_CTRL1              , 0x001f},
        {RT5677_DRC2_CTRL2              , 0x020c},
        {RT5677_DRC2_CTRL3              , 0x1f00},
        {RT5677_DRC2_CTRL4              , 0x0000},
        {RT5677_DRC2_CTRL5              , 0x0000},
        {RT5677_DRC2_CTRL6              , 0x0029},
        {RT5677_DRC1_HL_CTRL1           , 0x8000},
        {RT5677_DRC1_HL_CTRL2           , 0x0200},
        {RT5677_DRC2_HL_CTRL1           , 0x8000},
        {RT5677_DRC2_HL_CTRL2           , 0x0200},
        {RT5677_DSP_INB1_SRC_CTRL1      , 0x5800},
        {RT5677_DSP_INB1_SRC_CTRL2      , 0x0000},
        {RT5677_DSP_INB1_SRC_CTRL3      , 0x0000},
        {RT5677_DSP_INB1_SRC_CTRL4      , 0x0800},
        {RT5677_DSP_INB2_SRC_CTRL1      , 0x5800},
        {RT5677_DSP_INB2_SRC_CTRL2      , 0x0000},
        {RT5677_DSP_INB2_SRC_CTRL3      , 0x0000},
        {RT5677_DSP_INB2_SRC_CTRL4      , 0x0800},
        {RT5677_DSP_INB3_SRC_CTRL1      , 0x5800},
        {RT5677_DSP_INB3_SRC_CTRL2      , 0x0000},
        {RT5677_DSP_INB3_SRC_CTRL3      , 0x0000},
        {RT5677_DSP_INB3_SRC_CTRL4      , 0x0800},
        {RT5677_DSP_OUTB1_SRC_CTRL1     , 0x5800},
        {RT5677_DSP_OUTB1_SRC_CTRL2     , 0x0000},
        {RT5677_DSP_OUTB1_SRC_CTRL3     , 0x0000},
        {RT5677_DSP_OUTB1_SRC_CTRL4     , 0x0800},
        {RT5677_DSP_OUTB2_SRC_CTRL1     , 0x5800},
        {RT5677_DSP_OUTB2_SRC_CTRL2     , 0x0000},
        {RT5677_DSP_OUTB2_SRC_CTRL3     , 0x0000},
        {RT5677_DSP_OUTB2_SRC_CTRL4     , 0x0800},
        {RT5677_DSP_OUTB_0123_MIXER_CTRL, 0xfefe},
        {RT5677_DSP_OUTB_45_MIXER_CTRL  , 0xfefe},
        {RT5677_DSP_OUTB_67_MIXER_CTRL  , 0xfefe},
        {RT5677_DIG_MISC                , 0x0000},
        {RT5677_GEN_CTRL1               , 0x0000},
        {RT5677_GEN_CTRL2               , 0x0000},
        {RT5677_VENDOR_ID               , 0x0000},
        {RT5677_VENDOR_ID1              , 0x10ec},
        {RT5677_VENDOR_ID2              , 0x6327},
};

static bool rt5677_volatile_register(struct device *dev, unsigned int reg)
{
        int i;

        for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
                if (reg >= rt5677_ranges[i].range_min &&
                        reg <= rt5677_ranges[i].range_max) {
                        return true;
                }
        }

        switch (reg) {
        case RT5677_RESET:
        case RT5677_SLIMBUS_PARAM:
        case RT5677_PDM_DATA_CTRL1:
        case RT5677_PDM_DATA_CTRL2:
        case RT5677_PDM1_DATA_CTRL4:
        case RT5677_PDM2_DATA_CTRL4:
        case RT5677_I2C_MASTER_CTRL1:
        case RT5677_I2C_MASTER_CTRL7:
        case RT5677_I2C_MASTER_CTRL8:
        case RT5677_HAP_GENE_CTRL2:
        case RT5677_PWR_ANLG2: /* Modified by DSP firmware */
        case RT5677_PWR_DSP_ST:
        case RT5677_PRIV_DATA:
        case RT5677_ASRC_22:
        case RT5677_ASRC_23:
        case RT5677_VAD_CTRL5:
        case RT5677_ADC_EQ_CTRL1:
        case RT5677_EQ_CTRL1:
        case RT5677_IRQ_CTRL1:
        case RT5677_IRQ_CTRL2:
        case RT5677_GPIO_ST:
        case RT5677_GPIO_CTRL1: /* Modified by DSP firmware */
        case RT5677_GPIO_CTRL2: /* Modified by DSP firmware */
        case RT5677_DSP_INB1_SRC_CTRL4:
        case RT5677_DSP_INB2_SRC_CTRL4:
        case RT5677_DSP_INB3_SRC_CTRL4:
        case RT5677_DSP_OUTB1_SRC_CTRL4:
        case RT5677_DSP_OUTB2_SRC_CTRL4:
        case RT5677_VENDOR_ID:
        case RT5677_VENDOR_ID1:
        case RT5677_VENDOR_ID2:
                return true;
        default:
                return false;
        }
}

static bool rt5677_readable_register(struct device *dev, unsigned int reg)
{
        int i;

        for (i = 0; i < ARRAY_SIZE(rt5677_ranges); i++) {
                if (reg >= rt5677_ranges[i].range_min &&
                        reg <= rt5677_ranges[i].range_max) {
                        return true;
                }
        }

        switch (reg) {
        case RT5677_RESET:
        case RT5677_LOUT1:
        case RT5677_IN1:
        case RT5677_MICBIAS:
        case RT5677_SLIMBUS_PARAM:
        case RT5677_SLIMBUS_RX:
        case RT5677_SLIMBUS_CTRL:
        case RT5677_SIDETONE_CTRL:
        case RT5677_ANA_DAC1_2_3_SRC:
        case RT5677_IF_DSP_DAC3_4_MIXER:
        case RT5677_DAC4_DIG_VOL:
        case RT5677_DAC3_DIG_VOL:
        case RT5677_DAC1_DIG_VOL:
        case RT5677_DAC2_DIG_VOL:
        case RT5677_IF_DSP_DAC2_MIXER:
        case RT5677_STO1_ADC_DIG_VOL:
        case RT5677_MONO_ADC_DIG_VOL:
        case RT5677_STO1_2_ADC_BST:
        case RT5677_STO2_ADC_DIG_VOL:
        case RT5677_ADC_BST_CTRL2:
        case RT5677_STO3_4_ADC_BST:
        case RT5677_STO3_ADC_DIG_VOL:
        case RT5677_STO4_ADC_DIG_VOL:
        case RT5677_STO4_ADC_MIXER:
        case RT5677_STO3_ADC_MIXER:
        case RT5677_STO2_ADC_MIXER:
        case RT5677_STO1_ADC_MIXER:
        case RT5677_MONO_ADC_MIXER:
        case RT5677_ADC_IF_DSP_DAC1_MIXER:
        case RT5677_STO1_DAC_MIXER:
        case RT5677_MONO_DAC_MIXER:
        case RT5677_DD1_MIXER:
        case RT5677_DD2_MIXER:
        case RT5677_IF3_DATA:
        case RT5677_IF4_DATA:
        case RT5677_PDM_OUT_CTRL:
        case RT5677_PDM_DATA_CTRL1:
        case RT5677_PDM_DATA_CTRL2:
        case RT5677_PDM1_DATA_CTRL2:
        case RT5677_PDM1_DATA_CTRL3:
        case RT5677_PDM1_DATA_CTRL4:
        case RT5677_PDM2_DATA_CTRL2:
        case RT5677_PDM2_DATA_CTRL3:
        case RT5677_PDM2_DATA_CTRL4:
        case RT5677_TDM1_CTRL1:
        case RT5677_TDM1_CTRL2:
        case RT5677_TDM1_CTRL3:
        case RT5677_TDM1_CTRL4:
        case RT5677_TDM1_CTRL5:
        case RT5677_TDM2_CTRL1:
        case RT5677_TDM2_CTRL2:
        case RT5677_TDM2_CTRL3:
        case RT5677_TDM2_CTRL4:
        case RT5677_TDM2_CTRL5:
        case RT5677_I2C_MASTER_CTRL1:
        case RT5677_I2C_MASTER_CTRL2:
        case RT5677_I2C_MASTER_CTRL3:
        case RT5677_I2C_MASTER_CTRL4:
        case RT5677_I2C_MASTER_CTRL5:
        case RT5677_I2C_MASTER_CTRL6:
        case RT5677_I2C_MASTER_CTRL7:
        case RT5677_I2C_MASTER_CTRL8:
        case RT5677_DMIC_CTRL1:
        case RT5677_DMIC_CTRL2:
        case RT5677_HAP_GENE_CTRL1:
        case RT5677_HAP_GENE_CTRL2:
        case RT5677_HAP_GENE_CTRL3:
        case RT5677_HAP_GENE_CTRL4:
        case RT5677_HAP_GENE_CTRL5:
        case RT5677_HAP_GENE_CTRL6:
        case RT5677_HAP_GENE_CTRL7:
        case RT5677_HAP_GENE_CTRL8:
        case RT5677_HAP_GENE_CTRL9:
        case RT5677_HAP_GENE_CTRL10:
        case RT5677_PWR_DIG1:
        case RT5677_PWR_DIG2:
        case RT5677_PWR_ANLG1:
        case RT5677_PWR_ANLG2:
        case RT5677_PWR_DSP1:
        case RT5677_PWR_DSP_ST:
        case RT5677_PWR_DSP2:
        case RT5677_ADC_DAC_HPF_CTRL1:
        case RT5677_PRIV_INDEX:
        case RT5677_PRIV_DATA:
        case RT5677_I2S4_SDP:
        case RT5677_I2S1_SDP:
        case RT5677_I2S2_SDP:
        case RT5677_I2S3_SDP:
        case RT5677_CLK_TREE_CTRL1:
        case RT5677_CLK_TREE_CTRL2:
        case RT5677_CLK_TREE_CTRL3:
        case RT5677_PLL1_CTRL1:
        case RT5677_PLL1_CTRL2:
        case RT5677_PLL2_CTRL1:
        case RT5677_PLL2_CTRL2:
        case RT5677_GLB_CLK1:
        case RT5677_GLB_CLK2:
        case RT5677_ASRC_1:
        case RT5677_ASRC_2:
        case RT5677_ASRC_3:
        case RT5677_ASRC_4:
        case RT5677_ASRC_5:
        case RT5677_ASRC_6:
        case RT5677_ASRC_7:
        case RT5677_ASRC_8:
        case RT5677_ASRC_9:
        case RT5677_ASRC_10:
        case RT5677_ASRC_11:
        case RT5677_ASRC_12:
        case RT5677_ASRC_13:
        case RT5677_ASRC_14:
        case RT5677_ASRC_15:
        case RT5677_ASRC_16:
        case RT5677_ASRC_17:
        case RT5677_ASRC_18:
        case RT5677_ASRC_19:
        case RT5677_ASRC_20:
        case RT5677_ASRC_21:
        case RT5677_ASRC_22:
        case RT5677_ASRC_23:
        case RT5677_VAD_CTRL1:
        case RT5677_VAD_CTRL2:
        case RT5677_VAD_CTRL3:
        case RT5677_VAD_CTRL4:
        case RT5677_VAD_CTRL5:
        case RT5677_DSP_INB_CTRL1:
        case RT5677_DSP_INB_CTRL2:
        case RT5677_DSP_IN_OUTB_CTRL:
        case RT5677_DSP_OUTB0_1_DIG_VOL:
        case RT5677_DSP_OUTB2_3_DIG_VOL:
        case RT5677_DSP_OUTB4_5_DIG_VOL:
        case RT5677_DSP_OUTB6_7_DIG_VOL:
        case RT5677_ADC_EQ_CTRL1:
        case RT5677_ADC_EQ_CTRL2:
        case RT5677_EQ_CTRL1:
        case RT5677_EQ_CTRL2:
        case RT5677_EQ_CTRL3:
        case RT5677_SOFT_VOL_ZERO_CROSS1:
        case RT5677_JD_CTRL1:
        case RT5677_JD_CTRL2:
        case RT5677_JD_CTRL3:
        case RT5677_IRQ_CTRL1:
        case RT5677_IRQ_CTRL2:
        case RT5677_GPIO_ST:
        case RT5677_GPIO_CTRL1:
        case RT5677_GPIO_CTRL2:
        case RT5677_GPIO_CTRL3:
        case RT5677_STO1_ADC_HI_FILTER1:
        case RT5677_STO1_ADC_HI_FILTER2:
        case RT5677_MONO_ADC_HI_FILTER1:
        case RT5677_MONO_ADC_HI_FILTER2:
        case RT5677_STO2_ADC_HI_FILTER1:
        case RT5677_STO2_ADC_HI_FILTER2:
        case RT5677_STO3_ADC_HI_FILTER1:
        case RT5677_STO3_ADC_HI_FILTER2:
        case RT5677_STO4_ADC_HI_FILTER1:
        case RT5677_STO4_ADC_HI_FILTER2:
        case RT5677_MB_DRC_CTRL1:
        case RT5677_DRC1_CTRL1:
        case RT5677_DRC1_CTRL2:
        case RT5677_DRC1_CTRL3:
        case RT5677_DRC1_CTRL4:
        case RT5677_DRC1_CTRL5:
        case RT5677_DRC1_CTRL6:
        case RT5677_DRC2_CTRL1:
        case RT5677_DRC2_CTRL2:
        case RT5677_DRC2_CTRL3:
        case RT5677_DRC2_CTRL4:
        case RT5677_DRC2_CTRL5:
        case RT5677_DRC2_CTRL6:
        case RT5677_DRC1_HL_CTRL1:
        case RT5677_DRC1_HL_CTRL2:
        case RT5677_DRC2_HL_CTRL1:
        case RT5677_DRC2_HL_CTRL2:
        case RT5677_DSP_INB1_SRC_CTRL1:
        case RT5677_DSP_INB1_SRC_CTRL2:
        case RT5677_DSP_INB1_SRC_CTRL3:
        case RT5677_DSP_INB1_SRC_CTRL4:
        case RT5677_DSP_INB2_SRC_CTRL1:
        case RT5677_DSP_INB2_SRC_CTRL2:
        case RT5677_DSP_INB2_SRC_CTRL3:
        case RT5677_DSP_INB2_SRC_CTRL4:
        case RT5677_DSP_INB3_SRC_CTRL1:
        case RT5677_DSP_INB3_SRC_CTRL2:
        case RT5677_DSP_INB3_SRC_CTRL3:
        case RT5677_DSP_INB3_SRC_CTRL4:
        case RT5677_DSP_OUTB1_SRC_CTRL1:
        case RT5677_DSP_OUTB1_SRC_CTRL2:
        case RT5677_DSP_OUTB1_SRC_CTRL3:
        case RT5677_DSP_OUTB1_SRC_CTRL4:
        case RT5677_DSP_OUTB2_SRC_CTRL1:
        case RT5677_DSP_OUTB2_SRC_CTRL2:
        case RT5677_DSP_OUTB2_SRC_CTRL3:
        case RT5677_DSP_OUTB2_SRC_CTRL4:
        case RT5677_DSP_OUTB_0123_MIXER_CTRL:
        case RT5677_DSP_OUTB_45_MIXER_CTRL:
        case RT5677_DSP_OUTB_67_MIXER_CTRL:
        case RT5677_DIG_MISC:
        case RT5677_GEN_CTRL1:
        case RT5677_GEN_CTRL2:
        case RT5677_VENDOR_ID:
        case RT5677_VENDOR_ID1:
        case RT5677_VENDOR_ID2:
                return true;
        default:
                return false;
        }
}

/**
 * rt5677_dsp_mode_i2c_write_addr - Write value to address on DSP mode.
 * @rt5677: Private Data.
 * @addr: Address index.
 * @value: Address data.
 * @opcode: opcode value
 *
 * Returns 0 for success or negative error code.
 */
static int rt5677_dsp_mode_i2c_write_addr(struct rt5677_priv *rt5677,
                unsigned int addr, unsigned int value, unsigned int opcode)
{
        struct snd_soc_component *component = rt5677->component;
        int ret;

        mutex_lock(&rt5677->dsp_cmd_lock);

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
                addr >> 16);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
                goto err;
        }

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
                addr & 0xffff);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
                goto err;
        }

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB,
                value >> 16);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set data msb value: %d\n", ret);
                goto err;
        }

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB,
                value & 0xffff);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set data lsb value: %d\n", ret);
                goto err;
        }

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
                opcode);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set op code value: %d\n", ret);
                goto err;
        }

err:
        mutex_unlock(&rt5677->dsp_cmd_lock);

        return ret;
}

/**
 * rt5677_dsp_mode_i2c_read_addr - Read value from address on DSP mode.
 * @rt5677: Private Data.
 * @addr: Address index.
 * @value: Address data.
 *
 *
 * Returns 0 for success or negative error code.
 */
static int rt5677_dsp_mode_i2c_read_addr(
        struct rt5677_priv *rt5677, unsigned int addr, unsigned int *value)
{
        struct snd_soc_component *component = rt5677->component;
        int ret;
        unsigned int msb, lsb;

        mutex_lock(&rt5677->dsp_cmd_lock);

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_MSB,
                addr >> 16);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set addr msb value: %d\n", ret);
                goto err;
        }

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_ADDR_LSB,
                addr & 0xffff);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set addr lsb value: %d\n", ret);
                goto err;
        }

        ret = regmap_write(rt5677->regmap_physical, RT5677_DSP_I2C_OP_CODE,
                0x0002);
        if (ret < 0) {
                dev_err(component->dev, "Failed to set op code value: %d\n", ret);
                goto err;
        }

        regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_MSB, &msb);
        regmap_read(rt5677->regmap_physical, RT5677_DSP_I2C_DATA_LSB, &lsb);
        *value = (msb << 16) | lsb;

err:
        mutex_unlock(&rt5677->dsp_cmd_lock);

        return ret;
}

/**
 * rt5677_dsp_mode_i2c_write - Write register on DSP mode.
 * @rt5677: Private Data.
 * @reg: Register index.
 * @value: Register data.
 *
 *
 * Returns 0 for success or negative error code.
 */
static int rt5677_dsp_mode_i2c_write(struct rt5677_priv *rt5677,
                unsigned int reg, unsigned int value)
{
        return rt5677_dsp_mode_i2c_write_addr(rt5677, 0x18020000 + reg * 2,
                value, 0x0001);
}

/**
 * rt5677_dsp_mode_i2c_read - Read register on DSP mode.
 * @rt5677: Private Data
 * @reg: Register index.
 * @value: Register data.
 *
 *
 * Returns 0 for success or negative error code.
 */
static int rt5677_dsp_mode_i2c_read(
        struct rt5677_priv *rt5677, unsigned int reg, unsigned int *value)
{
        int ret = rt5677_dsp_mode_i2c_read_addr(rt5677, 0x18020000 + reg * 2,
                value);

        *value &= 0xffff;

        return ret;
}

static void rt5677_set_dsp_mode(struct rt5677_priv *rt5677, bool on)
{
        if (on) {
                regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
                        RT5677_PWR_DSP, RT5677_PWR_DSP);
                rt5677->is_dsp_mode = true;
        } else {
                regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
                        RT5677_PWR_DSP, 0x0);
                rt5677->is_dsp_mode = false;
        }
}

static unsigned int rt5677_set_vad_source(struct rt5677_priv *rt5677)
{
        struct snd_soc_dapm_context *dapm =
                        snd_soc_component_get_dapm(rt5677->component);
        /* Force dapm to sync before we enable the
         * DSP to prevent write corruption
         */
        snd_soc_dapm_sync(dapm);

        /* DMIC1 power = enabled
         * DMIC CLK = 256 * fs / 12
         */
        regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
                RT5677_DMIC_CLK_MASK, 5 << RT5677_DMIC_CLK_SFT);

        /* I2S pre divide 2 = /6 (clk_sys2) */
        regmap_update_bits(rt5677->regmap, RT5677_CLK_TREE_CTRL1,
                RT5677_I2S_PD2_MASK, RT5677_I2S_PD2_6);

        /* DSP Clock = MCLK1 (bypassed PLL2) */
        regmap_write(rt5677->regmap, RT5677_GLB_CLK2,
                RT5677_DSP_CLK_SRC_BYPASS);

        /* SAD Threshold1 */
        regmap_write(rt5677->regmap, RT5677_VAD_CTRL2, 0x013f);
        /* SAD Threshold2 */
        regmap_write(rt5677->regmap, RT5677_VAD_CTRL3, 0x0ae5);
        /* SAD Sample Rate Converter = Up 6 (8K to 48K)
         * SAD Output Sample Rate = Same as I2S
         * SAD Threshold3
         */
        regmap_update_bits(rt5677->regmap, RT5677_VAD_CTRL4,
                RT5677_VAD_OUT_SRC_RATE_MASK | RT5677_VAD_OUT_SRC_MASK |
                RT5677_VAD_LV_DIFF_MASK, 0x7f << RT5677_VAD_LV_DIFF_SFT);
        /* Minimum frame level within a pre-determined duration = 32 frames
         * Bypass ADPCM Encoder/Decoder = Bypass ADPCM
         * Automatic Push Data to SAD Buffer Once SAD Flag is triggered = enable
         * SAD Buffer Over-Writing = enable
         * SAD Buffer Pop Mode Control = disable
         * SAD Buffer Push Mode Control = enable
         * SAD Detector Control = enable
         * SAD Function Control = enable
         * SAD Function Reset = normal
         */
        regmap_write(rt5677->regmap, RT5677_VAD_CTRL1,
                RT5677_VAD_FUNC_RESET | RT5677_VAD_FUNC_ENABLE |
                RT5677_VAD_DET_ENABLE | RT5677_VAD_BUF_PUSH |
                RT5677_VAD_BUF_OW | RT5677_VAD_FG2ENC |
                RT5677_VAD_ADPCM_BYPASS | 1 << RT5677_VAD_MIN_DUR_SFT);

        /* VAD/SAD is not routed to the IRQ output (i.e. MX-BE[14] = 0), but it
         * is routed to DSP_IRQ_0, so DSP firmware may use it to sleep and save
         * power. See ALC5677 datasheet section 9.17 "GPIO, Interrupt and Jack
         * Detection" for more info.
         */

        /* Private register, no doc */
        regmap_update_bits(rt5677->regmap, RT5677_PR_BASE + RT5677_BIAS_CUR4,
                0x0f00, 0x0100);

        /* LDO2 output = 1.2V
         * LDO1 output = 1.2V (LDO_IN = 1.8V)
         */
        regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG1,
                RT5677_LDO1_SEL_MASK | RT5677_LDO2_SEL_MASK,
                5 << RT5677_LDO1_SEL_SFT | 5 << RT5677_LDO2_SEL_SFT);

        /* Codec core power =  power on
         * LDO1 power = power on
         */
        regmap_update_bits(rt5677->regmap, RT5677_PWR_ANLG2,
                RT5677_PWR_CORE | RT5677_PWR_LDO1,
                RT5677_PWR_CORE | RT5677_PWR_LDO1);

        /* Isolation for DCVDD4 = normal (set during probe)
         * Isolation for DCVDD2 = normal (set during probe)
         * Isolation for DSP = normal
         * Isolation for Band 0~7 = disable
         * Isolation for InBound 4~10 and OutBound 4~10 = disable
         */
        regmap_write(rt5677->regmap, RT5677_PWR_DSP2,
                RT5677_PWR_CORE_ISO | RT5677_PWR_DSP_ISO |
                RT5677_PWR_SR7_ISO | RT5677_PWR_SR6_ISO |
                RT5677_PWR_SR5_ISO | RT5677_PWR_SR4_ISO |
                RT5677_PWR_SR3_ISO | RT5677_PWR_SR2_ISO |
                RT5677_PWR_SR1_ISO | RT5677_PWR_SR0_ISO |
                RT5677_PWR_MLT_ISO);

        /* System Band 0~7 = power on
         * InBound 4~10 and OutBound 4~10 = power on
         * DSP = power on
         * DSP CPU = stop (will be set to "run" after firmware loaded)
         */
        regmap_write(rt5677->regmap, RT5677_PWR_DSP1,
                RT5677_PWR_SR7 | RT5677_PWR_SR6 |
                RT5677_PWR_SR5 | RT5677_PWR_SR4 |
                RT5677_PWR_SR3 | RT5677_PWR_SR2 |
                RT5677_PWR_SR1 | RT5677_PWR_SR0 |
                RT5677_PWR_MLT | RT5677_PWR_DSP |
                RT5677_PWR_DSP_CPU);

        return 0;
}

static int rt5677_parse_and_load_dsp(struct rt5677_priv *rt5677, const u8 *buf,
                unsigned int len)
{
        struct snd_soc_component *component = rt5677->component;
        Elf32_Ehdr *elf_hdr;
        Elf32_Phdr *pr_hdr;
        Elf32_Half i;
        int ret = 0;

        if (!buf || (len < sizeof(Elf32_Ehdr)))
                return -ENOMEM;

        elf_hdr = (Elf32_Ehdr *)buf;
#ifndef EM_XTENSA
#define EM_XTENSA       94
#endif
        if (strncmp(elf_hdr->e_ident, ELFMAG, sizeof(ELFMAG) - 1))
                dev_err(component->dev, "Wrong ELF header prefix\n");
        if (elf_hdr->e_ehsize != sizeof(Elf32_Ehdr))
                dev_err(component->dev, "Wrong Elf header size\n");
        if (elf_hdr->e_machine != EM_XTENSA)
                dev_err(component->dev, "Wrong DSP code file\n");

        if (len < elf_hdr->e_phoff)
                return -ENOMEM;
        pr_hdr = (Elf32_Phdr *)(buf + elf_hdr->e_phoff);
        for (i = 0; i < elf_hdr->e_phnum; i++) {
                /* TODO: handle p_memsz != p_filesz */
                if (pr_hdr->p_paddr && pr_hdr->p_filesz) {
                        dev_info(component->dev, "Load 0x%x bytes to 0x%x\n",
                                        pr_hdr->p_filesz, pr_hdr->p_paddr);

                        ret = rt5677_spi_write(pr_hdr->p_paddr,
                                        buf + pr_hdr->p_offset,
                                        pr_hdr->p_filesz);
                        if (ret)
                                dev_err(component->dev, "Load firmware failed %d\n",
                                                ret);
                }
                pr_hdr++;
        }
        return ret;
}

static int rt5677_load_dsp_from_file(struct rt5677_priv *rt5677)
{
        const struct firmware *fwp;
        struct device *dev = rt5677->component->dev;
        int ret = 0;

        /* Load dsp firmware from rt5677_elf_vad file */
        ret = request_firmware(&fwp, "rt5677_elf_vad", dev);
        if (ret) {
                dev_err(dev, "Request rt5677_elf_vad failed %d\n", ret);
                return ret;
        }
        dev_info(dev, "Requested rt5677_elf_vad (%zu)\n", fwp->size);

        ret = rt5677_parse_and_load_dsp(rt5677, fwp->data, fwp->size);
        release_firmware(fwp);
        return ret;
}

static int rt5677_set_dsp_vad(struct snd_soc_component *component, bool on)
{
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
        rt5677->dsp_vad_en_request = on;
        rt5677->dsp_vad_en = on;

        if (!IS_ENABLED(CONFIG_SND_SOC_RT5677_SPI))
                return -ENXIO;

        schedule_delayed_work(&rt5677->dsp_work, 0);
        return 0;
}

static void rt5677_dsp_work(struct work_struct *work)
{
        struct rt5677_priv *rt5677 =
                container_of(work, struct rt5677_priv, dsp_work.work);
        static bool activity;
        bool enable = rt5677->dsp_vad_en;
        int i, val;


        dev_info(rt5677->component->dev, "DSP VAD: enable=%d, activity=%d\n",
                        enable, activity);

        if (enable && !activity) {
                activity = true;

                /* Before a hotword is detected, GPIO1 pin is configured as IRQ
                 * output so that jack detect works. When a hotword is detected,
                 * the DSP firmware configures the GPIO1 pin as GPIO1 and
                 * drives a 1. rt5677_irq() is called after a rising edge on
                 * the GPIO1 pin, due to either jack detect event or hotword
                 * event, or both. All possible events are checked and handled
                 * in rt5677_irq() where GPIO1 pin is configured back to IRQ
                 * output if a hotword is detected.
                 */

                rt5677_set_vad_source(rt5677);
                rt5677_set_dsp_mode(rt5677, true);

#define RT5677_BOOT_RETRY 20
                for (i = 0; i < RT5677_BOOT_RETRY; i++) {
                        regmap_read(rt5677->regmap, RT5677_PWR_DSP_ST, &val);
                        if (val == 0x3ff)
                                break;
                        udelay(500);
                }
                if (i == RT5677_BOOT_RETRY && val != 0x3ff) {
                        dev_err(rt5677->component->dev, "DSP Boot Timed Out!");
                        return;
                }

                /* Boot the firmware from IRAM instead of SRAM0. */
                rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
                        0x0009, 0x0003);
                rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
                        0x0019, 0x0003);
                rt5677_dsp_mode_i2c_write_addr(rt5677, RT5677_DSP_BOOT_VECTOR,
                        0x0009, 0x0003);

                rt5677_load_dsp_from_file(rt5677);

                /* Set DSP CPU to Run */
                regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
                        RT5677_PWR_DSP_CPU, 0x0);
        } else if (!enable && activity) {
                activity = false;

                /* Don't turn off the DSP while handling irqs */
                mutex_lock(&rt5677->irq_lock);
                /* Set DSP CPU to Stop */
                regmap_update_bits(rt5677->regmap, RT5677_PWR_DSP1,
                        RT5677_PWR_DSP_CPU, RT5677_PWR_DSP_CPU);

                rt5677_set_dsp_mode(rt5677, false);

                /* Disable and clear VAD interrupt */
                regmap_write(rt5677->regmap, RT5677_VAD_CTRL1, 0x2184);

                /* Set GPIO1 pin back to be IRQ output for jack detect */
                regmap_update_bits(rt5677->regmap, RT5677_GPIO_CTRL1,
                        RT5677_GPIO1_PIN_MASK, RT5677_GPIO1_PIN_IRQ);

                mutex_unlock(&rt5677->irq_lock);
        }
}

static const DECLARE_TLV_DB_SCALE(dac_vol_tlv, -6525, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_vol_tlv, -1725, 75, 0);
static const DECLARE_TLV_DB_SCALE(adc_bst_tlv, 0, 1200, 0);
static const DECLARE_TLV_DB_SCALE(st_vol_tlv, -4650, 150, 0);

/* {0, +20, +24, +30, +35, +40, +44, +50, +52} dB */
static const DECLARE_TLV_DB_RANGE(bst_tlv,
        0, 0, TLV_DB_SCALE_ITEM(0, 0, 0),
        1, 1, TLV_DB_SCALE_ITEM(2000, 0, 0),
        2, 2, TLV_DB_SCALE_ITEM(2400, 0, 0),
        3, 5, TLV_DB_SCALE_ITEM(3000, 500, 0),
        6, 6, TLV_DB_SCALE_ITEM(4400, 0, 0),
        7, 7, TLV_DB_SCALE_ITEM(5000, 0, 0),
        8, 8, TLV_DB_SCALE_ITEM(5200, 0, 0)
);

static int rt5677_dsp_vad_get(struct snd_kcontrol *kcontrol,
                struct snd_ctl_elem_value *ucontrol)
{
        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);

        ucontrol->value.integer.value[0] = rt5677->dsp_vad_en_request;

        return 0;
}

static int rt5677_dsp_vad_put(struct snd_kcontrol *kcontrol,
                struct snd_ctl_elem_value *ucontrol)
{
        struct snd_soc_component *component = snd_kcontrol_chip(kcontrol);

        rt5677_set_dsp_vad(component, !!ucontrol->value.integer.value[0]);

        return 0;
}

static const struct snd_kcontrol_new rt5677_snd_controls[] = {
        /* OUTPUT Control */
        SOC_SINGLE("OUT1 Playback Switch", RT5677_LOUT1,
                RT5677_LOUT1_L_MUTE_SFT, 1, 1),
        SOC_SINGLE("OUT2 Playback Switch", RT5677_LOUT1,
                RT5677_LOUT2_L_MUTE_SFT, 1, 1),
        SOC_SINGLE("OUT3 Playback Switch", RT5677_LOUT1,
                RT5677_LOUT3_L_MUTE_SFT, 1, 1),

        /* DAC Digital Volume */
        SOC_DOUBLE_TLV("DAC1 Playback Volume", RT5677_DAC1_DIG_VOL,
                RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
        SOC_DOUBLE_TLV("DAC2 Playback Volume", RT5677_DAC2_DIG_VOL,
                RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
        SOC_DOUBLE_TLV("DAC3 Playback Volume", RT5677_DAC3_DIG_VOL,
                RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),
        SOC_DOUBLE_TLV("DAC4 Playback Volume", RT5677_DAC4_DIG_VOL,
                RT5677_L_VOL_SFT, RT5677_R_VOL_SFT, 127, 0, dac_vol_tlv),

        /* IN1/IN2 Control */
        SOC_SINGLE_TLV("IN1 Boost", RT5677_IN1, RT5677_BST_SFT1, 8, 0, bst_tlv),
        SOC_SINGLE_TLV("IN2 Boost", RT5677_IN1, RT5677_BST_SFT2, 8, 0, bst_tlv),

        /* ADC Digital Volume Control */
        SOC_DOUBLE("ADC1 Capture Switch", RT5677_STO1_ADC_DIG_VOL,
                RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
        SOC_DOUBLE("ADC2 Capture Switch", RT5677_STO2_ADC_DIG_VOL,
                RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
        SOC_DOUBLE("ADC3 Capture Switch", RT5677_STO3_ADC_DIG_VOL,
                RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
        SOC_DOUBLE("ADC4 Capture Switch", RT5677_STO4_ADC_DIG_VOL,
                RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),
        SOC_DOUBLE("Mono ADC Capture Switch", RT5677_MONO_ADC_DIG_VOL,
                RT5677_L_MUTE_SFT, RT5677_R_MUTE_SFT, 1, 1),

        SOC_DOUBLE_TLV("ADC1 Capture Volume", RT5677_STO1_ADC_DIG_VOL,
                RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
                adc_vol_tlv),
        SOC_DOUBLE_TLV("ADC2 Capture Volume", RT5677_STO2_ADC_DIG_VOL,
                RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
                adc_vol_tlv),
        SOC_DOUBLE_TLV("ADC3 Capture Volume", RT5677_STO3_ADC_DIG_VOL,
                RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
                adc_vol_tlv),
        SOC_DOUBLE_TLV("ADC4 Capture Volume", RT5677_STO4_ADC_DIG_VOL,
                RT5677_STO1_ADC_L_VOL_SFT, RT5677_STO1_ADC_R_VOL_SFT, 63, 0,
                adc_vol_tlv),
        SOC_DOUBLE_TLV("Mono ADC Capture Volume", RT5677_MONO_ADC_DIG_VOL,
                RT5677_MONO_ADC_L_VOL_SFT, RT5677_MONO_ADC_R_VOL_SFT, 63, 0,
                adc_vol_tlv),

        /* Sidetone Control */
        SOC_SINGLE_TLV("Sidetone Volume", RT5677_SIDETONE_CTRL,
                RT5677_ST_VOL_SFT, 31, 0, st_vol_tlv),

        /* ADC Boost Volume Control */
        SOC_DOUBLE_TLV("STO1 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
                RT5677_STO1_ADC_L_BST_SFT, RT5677_STO1_ADC_R_BST_SFT, 3, 0,
                adc_bst_tlv),
        SOC_DOUBLE_TLV("STO2 ADC Boost Volume", RT5677_STO1_2_ADC_BST,
                RT5677_STO2_ADC_L_BST_SFT, RT5677_STO2_ADC_R_BST_SFT, 3, 0,
                adc_bst_tlv),
        SOC_DOUBLE_TLV("STO3 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
                RT5677_STO3_ADC_L_BST_SFT, RT5677_STO3_ADC_R_BST_SFT, 3, 0,
                adc_bst_tlv),
        SOC_DOUBLE_TLV("STO4 ADC Boost Volume", RT5677_STO3_4_ADC_BST,
                RT5677_STO4_ADC_L_BST_SFT, RT5677_STO4_ADC_R_BST_SFT, 3, 0,
                adc_bst_tlv),
        SOC_DOUBLE_TLV("Mono ADC Boost Volume", RT5677_ADC_BST_CTRL2,
                RT5677_MONO_ADC_L_BST_SFT, RT5677_MONO_ADC_R_BST_SFT, 3, 0,
                adc_bst_tlv),

        SOC_SINGLE_EXT("DSP VAD Switch", SND_SOC_NOPM, 0, 1, 0,
                rt5677_dsp_vad_get, rt5677_dsp_vad_put),
};

/**
 * set_dmic_clk - Set parameter of dmic.
 *
 * @w: DAPM widget.
 * @kcontrol: The kcontrol of this widget.
 * @event: Event id.
 *
 * Choose dmic clock between 1MHz and 3MHz.
 * It is better for clock to approximate 3MHz.
 */
static int set_dmic_clk(struct snd_soc_dapm_widget *w,
        struct snd_kcontrol *kcontrol, int event)
{
        struct snd_soc_component *component = snd_soc_dapm_to_component(w->dapm);
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
        int idx, rate;

        rate = rt5677->sysclk / rl6231_get_pre_div(rt5677->regmap,
                RT5677_CLK_TREE_CTRL1, RT5677_I2S_PD1_SFT);
        idx = rl6231_calc_dmic_clk(rate);
        if (idx < 0)
                dev_err(component->dev, "Failed to set DMIC clock\n");
        else
                regmap_update_bits(rt5677->regmap, RT5677_DMIC_CTRL1,
                        RT5677_DMIC_CLK_MASK, idx << RT5677_DMIC_CLK_SFT);
        return idx;
}

static int is_sys_clk_from_pll(struct snd_soc_dapm_widget *source,
                         struct snd_soc_dapm_widget *sink)
{
        struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
        unsigned int val;

        regmap_read(rt5677->regmap, RT5677_GLB_CLK1, &val);
        val &= RT5677_SCLK_SRC_MASK;
        if (val == RT5677_SCLK_SRC_PLL1)
                return 1;
        else
                return 0;
}

static int is_using_asrc(struct snd_soc_dapm_widget *source,
                         struct snd_soc_dapm_widget *sink)
{
        struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
        unsigned int reg, shift, val;

        if (source->reg == RT5677_ASRC_1) {
                switch (source->shift) {
                case 12:
                        reg = RT5677_ASRC_4;
                        shift = 0;
                        break;
                case 13:
                        reg = RT5677_ASRC_4;
                        shift = 4;
                        break;
                case 14:
                        reg = RT5677_ASRC_4;
                        shift = 8;
                        break;
                case 15:
                        reg = RT5677_ASRC_4;
                        shift = 12;
                        break;
                default:
                        return 0;
                }
        } else {
                switch (source->shift) {
                case 0:
                        reg = RT5677_ASRC_6;
                        shift = 8;
                        break;
                case 1:
                        reg = RT5677_ASRC_6;
                        shift = 12;
                        break;
                case 2:
                        reg = RT5677_ASRC_5;
                        shift = 0;
                        break;
                case 3:
                        reg = RT5677_ASRC_5;
                        shift = 4;
                        break;
                case 4:
                        reg = RT5677_ASRC_5;
                        shift = 8;
                        break;
                case 5:
                        reg = RT5677_ASRC_5;
                        shift = 12;
                        break;
                case 12:
                        reg = RT5677_ASRC_3;
                        shift = 0;
                        break;
                case 13:
                        reg = RT5677_ASRC_3;
                        shift = 4;
                        break;
                case 14:
                        reg = RT5677_ASRC_3;
                        shift = 12;
                        break;
                default:
                        return 0;
                }
        }

        regmap_read(rt5677->regmap, reg, &val);
        val = (val >> shift) & 0xf;

        switch (val) {
        case 1 ... 6:
                return 1;
        default:
                return 0;
        }

}

static int can_use_asrc(struct snd_soc_dapm_widget *source,
                         struct snd_soc_dapm_widget *sink)
{
        struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);

        if (rt5677->sysclk > rt5677->lrck[RT5677_AIF1] * 384)
                return 1;

        return 0;
}

/**
 * rt5677_sel_asrc_clk_src - select ASRC clock source for a set of filters
 * @component: SoC audio component device.
 * @filter_mask: mask of filters.
 * @clk_src: clock source
 *
 * The ASRC function is for asynchronous MCLK and LRCK. Also, since RT5677 can
 * only support standard 32fs or 64fs i2s format, ASRC should be enabled to
 * support special i2s clock format such as Intel's 100fs(100 * sampling rate).
 * ASRC function will track i2s clock and generate a corresponding system clock
 * for codec. This function provides an API to select the clock source for a
 * set of filters specified by the mask. And the codec driver will turn on ASRC
 * for these filters if ASRC is selected as their clock source.
 */
int rt5677_sel_asrc_clk_src(struct snd_soc_component *component,
                unsigned int filter_mask, unsigned int clk_src)
{
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
        unsigned int asrc3_mask = 0, asrc3_value = 0;
        unsigned int asrc4_mask = 0, asrc4_value = 0;
        unsigned int asrc5_mask = 0, asrc5_value = 0;
        unsigned int asrc6_mask = 0, asrc6_value = 0;
        unsigned int asrc7_mask = 0, asrc7_value = 0;
        unsigned int asrc8_mask = 0, asrc8_value = 0;

        switch (clk_src) {
        case RT5677_CLK_SEL_SYS:
        case RT5677_CLK_SEL_I2S1_ASRC:
        case RT5677_CLK_SEL_I2S2_ASRC:
        case RT5677_CLK_SEL_I2S3_ASRC:
        case RT5677_CLK_SEL_I2S4_ASRC:
        case RT5677_CLK_SEL_I2S5_ASRC:
        case RT5677_CLK_SEL_I2S6_ASRC:
        case RT5677_CLK_SEL_SYS2:
        case RT5677_CLK_SEL_SYS3:
        case RT5677_CLK_SEL_SYS4:
        case RT5677_CLK_SEL_SYS5:
        case RT5677_CLK_SEL_SYS6:
        case RT5677_CLK_SEL_SYS7:
                break;

        default:
                return -EINVAL;
        }

        /* ASRC 3 */
        if (filter_mask & RT5677_DA_STEREO_FILTER) {
                asrc3_mask |= RT5677_DA_STO_CLK_SEL_MASK;
                asrc3_value = (asrc3_value & ~RT5677_DA_STO_CLK_SEL_MASK)
                        | (clk_src << RT5677_DA_STO_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_DA_MONO2_L_FILTER) {
                asrc3_mask |= RT5677_DA_MONO2L_CLK_SEL_MASK;
                asrc3_value = (asrc3_value & ~RT5677_DA_MONO2L_CLK_SEL_MASK)
                        | (clk_src << RT5677_DA_MONO2L_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_DA_MONO2_R_FILTER) {
                asrc3_mask |= RT5677_DA_MONO2R_CLK_SEL_MASK;
                asrc3_value = (asrc3_value & ~RT5677_DA_MONO2R_CLK_SEL_MASK)
                        | (clk_src << RT5677_DA_MONO2R_CLK_SEL_SFT);
        }

        if (asrc3_mask)
                regmap_update_bits(rt5677->regmap, RT5677_ASRC_3, asrc3_mask,
                        asrc3_value);

        /* ASRC 4 */
        if (filter_mask & RT5677_DA_MONO3_L_FILTER) {
                asrc4_mask |= RT5677_DA_MONO3L_CLK_SEL_MASK;
                asrc4_value = (asrc4_value & ~RT5677_DA_MONO3L_CLK_SEL_MASK)
                        | (clk_src << RT5677_DA_MONO3L_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_DA_MONO3_R_FILTER) {
                asrc4_mask |= RT5677_DA_MONO3R_CLK_SEL_MASK;
                asrc4_value = (asrc4_value & ~RT5677_DA_MONO3R_CLK_SEL_MASK)
                        | (clk_src << RT5677_DA_MONO3R_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_DA_MONO4_L_FILTER) {
                asrc4_mask |= RT5677_DA_MONO4L_CLK_SEL_MASK;
                asrc4_value = (asrc4_value & ~RT5677_DA_MONO4L_CLK_SEL_MASK)
                        | (clk_src << RT5677_DA_MONO4L_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_DA_MONO4_R_FILTER) {
                asrc4_mask |= RT5677_DA_MONO4R_CLK_SEL_MASK;
                asrc4_value = (asrc4_value & ~RT5677_DA_MONO4R_CLK_SEL_MASK)
                        | (clk_src << RT5677_DA_MONO4R_CLK_SEL_SFT);
        }

        if (asrc4_mask)
                regmap_update_bits(rt5677->regmap, RT5677_ASRC_4, asrc4_mask,
                        asrc4_value);

        /* ASRC 5 */
        if (filter_mask & RT5677_AD_STEREO1_FILTER) {
                asrc5_mask |= RT5677_AD_STO1_CLK_SEL_MASK;
                asrc5_value = (asrc5_value & ~RT5677_AD_STO1_CLK_SEL_MASK)
                        | (clk_src << RT5677_AD_STO1_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_AD_STEREO2_FILTER) {
                asrc5_mask |= RT5677_AD_STO2_CLK_SEL_MASK;
                asrc5_value = (asrc5_value & ~RT5677_AD_STO2_CLK_SEL_MASK)
                        | (clk_src << RT5677_AD_STO2_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_AD_STEREO3_FILTER) {
                asrc5_mask |= RT5677_AD_STO3_CLK_SEL_MASK;
                asrc5_value = (asrc5_value & ~RT5677_AD_STO3_CLK_SEL_MASK)
                        | (clk_src << RT5677_AD_STO3_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_AD_STEREO4_FILTER) {
                asrc5_mask |= RT5677_AD_STO4_CLK_SEL_MASK;
                asrc5_value = (asrc5_value & ~RT5677_AD_STO4_CLK_SEL_MASK)
                        | (clk_src << RT5677_AD_STO4_CLK_SEL_SFT);
        }

        if (asrc5_mask)
                regmap_update_bits(rt5677->regmap, RT5677_ASRC_5, asrc5_mask,
                        asrc5_value);

        /* ASRC 6 */
        if (filter_mask & RT5677_AD_MONO_L_FILTER) {
                asrc6_mask |= RT5677_AD_MONOL_CLK_SEL_MASK;
                asrc6_value = (asrc6_value & ~RT5677_AD_MONOL_CLK_SEL_MASK)
                        | (clk_src << RT5677_AD_MONOL_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_AD_MONO_R_FILTER) {
                asrc6_mask |= RT5677_AD_MONOR_CLK_SEL_MASK;
                asrc6_value = (asrc6_value & ~RT5677_AD_MONOR_CLK_SEL_MASK)
                        | (clk_src << RT5677_AD_MONOR_CLK_SEL_SFT);
        }

        if (asrc6_mask)
                regmap_update_bits(rt5677->regmap, RT5677_ASRC_6, asrc6_mask,
                        asrc6_value);

        /* ASRC 7 */
        if (filter_mask & RT5677_DSP_OB_0_3_FILTER) {
                asrc7_mask |= RT5677_DSP_OB_0_3_CLK_SEL_MASK;
                asrc7_value = (asrc7_value & ~RT5677_DSP_OB_0_3_CLK_SEL_MASK)
                        | (clk_src << RT5677_DSP_OB_0_3_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_DSP_OB_4_7_FILTER) {
                asrc7_mask |= RT5677_DSP_OB_4_7_CLK_SEL_MASK;
                asrc7_value = (asrc7_value & ~RT5677_DSP_OB_4_7_CLK_SEL_MASK)
                        | (clk_src << RT5677_DSP_OB_4_7_CLK_SEL_SFT);
        }

        if (asrc7_mask)
                regmap_update_bits(rt5677->regmap, RT5677_ASRC_7, asrc7_mask,
                        asrc7_value);

        /* ASRC 8 */
        if (filter_mask & RT5677_I2S1_SOURCE) {
                asrc8_mask |= RT5677_I2S1_CLK_SEL_MASK;
                asrc8_value = (asrc8_value & ~RT5677_I2S1_CLK_SEL_MASK)
                        | ((clk_src - 1) << RT5677_I2S1_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_I2S2_SOURCE) {
                asrc8_mask |= RT5677_I2S2_CLK_SEL_MASK;
                asrc8_value = (asrc8_value & ~RT5677_I2S2_CLK_SEL_MASK)
                        | ((clk_src - 1) << RT5677_I2S2_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_I2S3_SOURCE) {
                asrc8_mask |= RT5677_I2S3_CLK_SEL_MASK;
                asrc8_value = (asrc8_value & ~RT5677_I2S3_CLK_SEL_MASK)
                        | ((clk_src - 1) << RT5677_I2S3_CLK_SEL_SFT);
        }

        if (filter_mask & RT5677_I2S4_SOURCE) {
                asrc8_mask |= RT5677_I2S4_CLK_SEL_MASK;
                asrc8_value = (asrc8_value & ~RT5677_I2S4_CLK_SEL_MASK)
                        | ((clk_src - 1) << RT5677_I2S4_CLK_SEL_SFT);
        }

        if (asrc8_mask)
                regmap_update_bits(rt5677->regmap, RT5677_ASRC_8, asrc8_mask,
                        asrc8_value);

        return 0;
}
EXPORT_SYMBOL_GPL(rt5677_sel_asrc_clk_src);

static int rt5677_dmic_use_asrc(struct snd_soc_dapm_widget *source,
                         struct snd_soc_dapm_widget *sink)
{
        struct snd_soc_component *component = snd_soc_dapm_to_component(source->dapm);
        struct rt5677_priv *rt5677 = snd_soc_component_get_drvdata(component);
        unsigned int asrc_setting;

        switch (source->shift) {
        case 11:
                regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
                asrc_setting = (asrc_setting & RT5677_AD_STO1_CLK_SEL_MASK) >>
                                RT5677_AD_STO1_CLK_SEL_SFT;
                break;

        case 10:
                regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
                asrc_setting = (asrc_setting & RT5677_AD_STO2_CLK_SEL_MASK) >>
                                RT5677_AD_STO2_CLK_SEL_SFT;
                break;

        case 9:
                regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
                asrc_setting = (asrc_setting & RT5677_AD_STO3_CLK_SEL_MASK) >>
                                RT5677_AD_STO3_CLK_SEL_SFT;
                break;

        case 8:
                regmap_read(rt5677->regmap, RT5677_ASRC_5, &asrc_setting);
                asrc_setting = (asrc_setting & RT5677_AD_STO4_CLK_SEL_MASK) >>
                        RT5677_AD_STO4_CLK_SEL_SFT;
                break;

        case 7:
                regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
                asrc_setting = (asrc_setting & RT5677_AD_MONOL_CLK_SEL_MASK) >>
                        RT5677_AD_MONOL_CLK_SEL_SFT;
                break;

        case 6:
                regmap_read(rt5677->regmap, RT5677_ASRC_6, &asrc_setting);
                asrc_setting = (asrc_setting & RT5677_AD_MONOR_CLK_SEL_MASK) >>
                        RT5677_AD_MONOR_CLK_SEL_SFT;
                break;

        default:
                return 0;
        }

        if (asrc_setting >= RT5677_CLK_SEL_I2S1_ASRC &&
            asrc_setting <= RT5677_CLK_SEL_I2S6_ASRC)
                return 1;

        return 0;
}

/* Digital Mixer */
static const struct snd_kcontrol_new rt5677_sto1_adc_l_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
                        RT5677_M_STO1_ADC_L1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
                        RT5677_M_STO1_ADC_L2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto1_adc_r_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO1_ADC_MIXER,
                        RT5677_M_STO1_ADC_R1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO1_ADC_MIXER,
                        RT5677_M_STO1_ADC_R2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto2_adc_l_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
                        RT5677_M_STO2_ADC_L1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
                        RT5677_M_STO2_ADC_L2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto2_adc_r_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO2_ADC_MIXER,
                        RT5677_M_STO2_ADC_R1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO2_ADC_MIXER,
                        RT5677_M_STO2_ADC_R2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto3_adc_l_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
                        RT5677_M_STO3_ADC_L1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
                        RT5677_M_STO3_ADC_L2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto3_adc_r_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO3_ADC_MIXER,
                        RT5677_M_STO3_ADC_R1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO3_ADC_MIXER,
                        RT5677_M_STO3_ADC_R2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto4_adc_l_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
                        RT5677_M_STO4_ADC_L1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
                        RT5677_M_STO4_ADC_L2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto4_adc_r_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_STO4_ADC_MIXER,
                        RT5677_M_STO4_ADC_R1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_STO4_ADC_MIXER,
                        RT5677_M_STO4_ADC_R2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_mono_adc_l_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
                        RT5677_M_MONO_ADC_L1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
                        RT5677_M_MONO_ADC_L2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_mono_adc_r_mix[] = {
        SOC_DAPM_SINGLE("ADC1 Switch", RT5677_MONO_ADC_MIXER,
                        RT5677_M_MONO_ADC_R1_SFT, 1, 1),
        SOC_DAPM_SINGLE("ADC2 Switch", RT5677_MONO_ADC_MIXER,
                        RT5677_M_MONO_ADC_R2_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_dac_l_mix[] = {
        SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
                        RT5677_M_ADDA_MIXER1_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
                        RT5677_M_DAC1_L_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_dac_r_mix[] = {
        SOC_DAPM_SINGLE("Stereo ADC Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
                        RT5677_M_ADDA_MIXER1_R_SFT, 1, 1),
        SOC_DAPM_SINGLE("DAC1 Switch", RT5677_ADC_IF_DSP_DAC1_MIXER,
                        RT5677_M_DAC1_R_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto1_dac_l_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_ST_DAC1_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_DAC1_L_STO_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_DAC2_L_STO_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_DAC1_R_STO_L_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_sto1_dac_r_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_ST_DAC1_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_DAC1_R_STO_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_DAC2_R_STO_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_STO1_DAC_MIXER,
                        RT5677_M_DAC1_L_STO_R_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_mono_dac_l_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("ST L Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_ST_DAC2_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC1 L Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_DAC1_L_MONO_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_DAC2_L_MONO_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_DAC2_R_MONO_L_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_mono_dac_r_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("ST R Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_ST_DAC2_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC1 R Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_DAC1_R_MONO_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC2 R Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_DAC2_R_MONO_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC2 L Switch", RT5677_MONO_DAC_MIXER,
                        RT5677_M_DAC2_L_MONO_R_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_dd1_l_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD1_MIXER,
                        RT5677_M_STO_L_DD1_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD1_MIXER,
                        RT5677_M_MONO_L_DD1_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
                        RT5677_M_DAC3_L_DD1_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
                        RT5677_M_DAC3_R_DD1_L_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_dd1_r_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD1_MIXER,
                        RT5677_M_STO_R_DD1_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD1_MIXER,
                        RT5677_M_MONO_R_DD1_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC3 R Switch", RT5677_DD1_MIXER,
                        RT5677_M_DAC3_R_DD1_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC3 L Switch", RT5677_DD1_MIXER,
                        RT5677_M_DAC3_L_DD1_R_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_dd2_l_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix L Switch", RT5677_DD2_MIXER,
                        RT5677_M_STO_L_DD2_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix L Switch", RT5677_DD2_MIXER,
                        RT5677_M_MONO_L_DD2_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
                        RT5677_M_DAC4_L_DD2_L_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
                        RT5677_M_DAC4_R_DD2_L_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_dd2_r_mix[] = {
        SOC_DAPM_SINGLE_AUTODISABLE("Sto DAC Mix R Switch", RT5677_DD2_MIXER,
                        RT5677_M_STO_R_DD2_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("Mono DAC Mix R Switch", RT5677_DD2_MIXER,
                        RT5677_M_MONO_R_DD2_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC4 R Switch", RT5677_DD2_MIXER,
                        RT5677_M_DAC4_R_DD2_R_SFT, 1, 1),
        SOC_DAPM_SINGLE_AUTODISABLE("DAC4 L Switch", RT5677_DD2_MIXER,
                        RT5677_M_DAC4_L_DD2_R_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_ob_01_mix[] = {
        SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_01_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_23_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_45_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_6_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_7_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_8_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_9_H_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_ob_23_mix[] = {
        SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_01_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_23_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_45_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_6_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_7_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_8_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_0123_MIXER_CTRL,
                        RT5677_DSP_IB_9_L_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_ob_4_mix[] = {
        SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_01_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_23_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_45_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_6_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_7_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_8_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_9_H_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_ob_5_mix[] = {
        SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_01_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_23_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_45_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_6_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_7_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_8_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_45_MIXER_CTRL,
                        RT5677_DSP_IB_9_L_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_ob_6_mix[] = {
        SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_01_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_23_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_45_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_6_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_7_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_8_H_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_9_H_SFT, 1, 1),
};

static const struct snd_kcontrol_new rt5677_ob_7_mix[] = {
        SOC_DAPM_SINGLE("IB01 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_01_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB23 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_23_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB45 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_45_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB6 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_6_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB7 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_7_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB8 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_8_L_SFT, 1, 1),
        SOC_DAPM_SINGLE("IB9 Switch", RT5677_DSP_OUTB_67_MIXER_CTRL,
                        RT5677_DSP_IB_9_L_SFT, 1, 1),
};


/* Mux */
/* DAC1 L/R Source */ /* MX-29 [10:8] */
static const char * const rt5677_dac1_src[] = {
        "IF1 DAC 01", "IF2 DAC 01", "IF3 DAC LR", "IF4 DAC LR", "SLB DAC 01",
        "OB 01"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_dac1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
        RT5677_DAC1_L_SEL_SFT, rt5677_dac1_src);

static const struct snd_kcontrol_new rt5677_dac1_mux =
        SOC_DAPM_ENUM("DAC1 Source", rt5677_dac1_enum);

/* ADDA1 L/R Source */ /* MX-29 [1:0] */
static const char * const rt5677_adda1_src[] = {
        "STO1 ADC MIX", "STO2 ADC MIX", "OB 67",
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_adda1_enum, RT5677_ADC_IF_DSP_DAC1_MIXER,
        RT5677_ADDA1_SEL_SFT, rt5677_adda1_src);

static const struct snd_kcontrol_new rt5677_adda1_mux =
        SOC_DAPM_ENUM("ADDA1 Source", rt5677_adda1_enum);


/*DAC2 L/R Source*/ /* MX-1B [6:4] [2:0] */
static const char * const rt5677_dac2l_src[] = {
        "IF1 DAC 2", "IF2 DAC 2", "IF3 DAC L", "IF4 DAC L", "SLB DAC 2",
        "OB 2",
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_dac2l_enum, RT5677_IF_DSP_DAC2_MIXER,
        RT5677_SEL_DAC2_L_SRC_SFT, rt5677_dac2l_src);

static const struct snd_kcontrol_new rt5677_dac2_l_mux =
        SOC_DAPM_ENUM("DAC2 L Source", rt5677_dac2l_enum);

static const char * const rt5677_dac2r_src[] = {
        "IF1 DAC 3", "IF2 DAC 3", "IF3 DAC R", "IF4 DAC R", "SLB DAC 3",
        "OB 3", "Haptic Generator", "VAD ADC"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_dac2r_enum, RT5677_IF_DSP_DAC2_MIXER,
        RT5677_SEL_DAC2_R_SRC_SFT, rt5677_dac2r_src);

static const struct snd_kcontrol_new rt5677_dac2_r_mux =
        SOC_DAPM_ENUM("DAC2 R Source", rt5677_dac2r_enum);

/*DAC3 L/R Source*/ /* MX-16 [6:4] [2:0] */
static const char * const rt5677_dac3l_src[] = {
        "IF1 DAC 4", "IF2 DAC 4", "IF3 DAC L", "IF4 DAC L",
        "SLB DAC 4", "OB 4"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_dac3l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
        RT5677_SEL_DAC3_L_SRC_SFT, rt5677_dac3l_src);

static const struct snd_kcontrol_new rt5677_dac3_l_mux =
        SOC_DAPM_ENUM("DAC3 L Source", rt5677_dac3l_enum);

static const char * const rt5677_dac3r_src[] = {
        "IF1 DAC 5", "IF2 DAC 5", "IF3 DAC R", "IF4 DAC R",
        "SLB DAC 5", "OB 5"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_dac3r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
        RT5677_SEL_DAC3_R_SRC_SFT, rt5677_dac3r_src);

static const struct snd_kcontrol_new rt5677_dac3_r_mux =
        SOC_DAPM_ENUM("DAC3 R Source", rt5677_dac3r_enum);

/*DAC4 L/R Source*/ /* MX-16 [14:12] [10:8] */
static const char * const rt5677_dac4l_src[] = {
        "IF1 DAC 6", "IF2 DAC 6", "IF3 DAC L", "IF4 DAC L",
        "SLB DAC 6", "OB 6"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_dac4l_enum, RT5677_IF_DSP_DAC3_4_MIXER,
        RT5677_SEL_DAC4_L_SRC_SFT, rt5677_dac4l_src);

static const struct snd_kcontrol_new rt5677_dac4_l_mux =
        SOC_DAPM_ENUM("DAC4 L Source", rt5677_dac4l_enum);

static const char * const rt5677_dac4r_src[] = {
        "IF1 DAC 7", "IF2 DAC 7", "IF3 DAC R", "IF4 DAC R",
        "SLB DAC 7", "OB 7"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_dac4r_enum, RT5677_IF_DSP_DAC3_4_MIXER,
        RT5677_SEL_DAC4_R_SRC_SFT, rt5677_dac4r_src);

static const struct snd_kcontrol_new rt5677_dac4_r_mux =
        SOC_DAPM_ENUM("DAC4 R Source", rt5677_dac4r_enum);

/* In/OutBound Source Pass SRC */ /* MX-A5 [3] [4] [0] [1] [2] */
static const char * const rt5677_iob_bypass_src[] = {
        "Bypass", "Pass SRC"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_ob01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
        RT5677_SEL_SRC_OB01_SFT, rt5677_iob_bypass_src);

static const struct snd_kcontrol_new rt5677_ob01_bypass_src_mux =
        SOC_DAPM_ENUM("OB01 Bypass Source", rt5677_ob01_bypass_src_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_ob23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
        RT5677_SEL_SRC_OB23_SFT, rt5677_iob_bypass_src);

static const struct snd_kcontrol_new rt5677_ob23_bypass_src_mux =
        SOC_DAPM_ENUM("OB23 Bypass Source", rt5677_ob23_bypass_src_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_ib01_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
        RT5677_SEL_SRC_IB01_SFT, rt5677_iob_bypass_src);

static const struct snd_kcontrol_new rt5677_ib01_bypass_src_mux =
        SOC_DAPM_ENUM("IB01 Bypass Source", rt5677_ib01_bypass_src_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_ib23_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
        RT5677_SEL_SRC_IB23_SFT, rt5677_iob_bypass_src);

static const struct snd_kcontrol_new rt5677_ib23_bypass_src_mux =
        SOC_DAPM_ENUM("IB23 Bypass Source", rt5677_ib23_bypass_src_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_ib45_bypass_src_enum, RT5677_DSP_IN_OUTB_CTRL,
        RT5677_SEL_SRC_IB45_SFT, rt5677_iob_bypass_src);

static const struct snd_kcontrol_new rt5677_ib45_bypass_src_mux =
        SOC_DAPM_ENUM("IB45 Bypass Source", rt5677_ib45_bypass_src_enum);

/* Stereo ADC Source 2 */ /* MX-27 MX26 MX25 [11:10] */
static const char * const rt5677_stereo_adc2_src[] = {
        "DD MIX1", "DMIC", "Stereo DAC MIX"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo1_adc2_enum, RT5677_STO1_ADC_MIXER,
        RT5677_SEL_STO1_ADC2_SFT, rt5677_stereo_adc2_src);

static const struct snd_kcontrol_new rt5677_sto1_adc2_mux =
        SOC_DAPM_ENUM("Stereo1 ADC2 Source", rt5677_stereo1_adc2_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo2_adc2_enum, RT5677_STO2_ADC_MIXER,
        RT5677_SEL_STO2_ADC2_SFT, rt5677_stereo_adc2_src);

static const struct snd_kcontrol_new rt5677_sto2_adc2_mux =
        SOC_DAPM_ENUM("Stereo2 ADC2 Source", rt5677_stereo2_adc2_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo3_adc2_enum, RT5677_STO3_ADC_MIXER,
        RT5677_SEL_STO3_ADC2_SFT, rt5677_stereo_adc2_src);

static const struct snd_kcontrol_new rt5677_sto3_adc2_mux =
        SOC_DAPM_ENUM("Stereo3 ADC2 Source", rt5677_stereo3_adc2_enum);

/* DMIC Source */ /* MX-28 [9:8][1:0] MX-27 MX-26 MX-25 MX-24 [9:8] */
static const char * const rt5677_dmic_src[] = {
        "DMIC1", "DMIC2", "DMIC3", "DMIC4"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_mono_dmic_l_enum, RT5677_MONO_ADC_MIXER,
        RT5677_SEL_MONO_DMIC_L_SFT, rt5677_dmic_src);

static const struct snd_kcontrol_new rt5677_mono_dmic_l_mux =
        SOC_DAPM_ENUM("Mono DMIC L Source", rt5677_mono_dmic_l_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_mono_dmic_r_enum, RT5677_MONO_ADC_MIXER,
        RT5677_SEL_MONO_DMIC_R_SFT, rt5677_dmic_src);

static const struct snd_kcontrol_new rt5677_mono_dmic_r_mux =
        SOC_DAPM_ENUM("Mono DMIC R Source", rt5677_mono_dmic_r_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo1_dmic_enum, RT5677_STO1_ADC_MIXER,
        RT5677_SEL_STO1_DMIC_SFT, rt5677_dmic_src);

static const struct snd_kcontrol_new rt5677_sto1_dmic_mux =
        SOC_DAPM_ENUM("Stereo1 DMIC Source", rt5677_stereo1_dmic_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo2_dmic_enum, RT5677_STO2_ADC_MIXER,
        RT5677_SEL_STO2_DMIC_SFT, rt5677_dmic_src);

static const struct snd_kcontrol_new rt5677_sto2_dmic_mux =
        SOC_DAPM_ENUM("Stereo2 DMIC Source", rt5677_stereo2_dmic_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo3_dmic_enum, RT5677_STO3_ADC_MIXER,
        RT5677_SEL_STO3_DMIC_SFT, rt5677_dmic_src);

static const struct snd_kcontrol_new rt5677_sto3_dmic_mux =
        SOC_DAPM_ENUM("Stereo3 DMIC Source", rt5677_stereo3_dmic_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo4_dmic_enum, RT5677_STO4_ADC_MIXER,
        RT5677_SEL_STO4_DMIC_SFT, rt5677_dmic_src);

static const struct snd_kcontrol_new rt5677_sto4_dmic_mux =
        SOC_DAPM_ENUM("Stereo4 DMIC Source", rt5677_stereo4_dmic_enum);

/* Stereo2 ADC Source */ /* MX-26 [0] */
static const char * const rt5677_stereo2_adc_lr_src[] = {
        "L", "LR"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo2_adc_lr_enum, RT5677_STO2_ADC_MIXER,
        RT5677_SEL_STO2_LR_MIX_SFT, rt5677_stereo2_adc_lr_src);

static const struct snd_kcontrol_new rt5677_sto2_adc_lr_mux =
        SOC_DAPM_ENUM("Stereo2 ADC LR Source", rt5677_stereo2_adc_lr_enum);

/* Stereo1 ADC Source 1 */ /* MX-27 MX26 MX25 [13:12] */
static const char * const rt5677_stereo_adc1_src[] = {
        "DD MIX1", "ADC1/2", "Stereo DAC MIX"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo1_adc1_enum, RT5677_STO1_ADC_MIXER,
        RT5677_SEL_STO1_ADC1_SFT, rt5677_stereo_adc1_src);

static const struct snd_kcontrol_new rt5677_sto1_adc1_mux =
        SOC_DAPM_ENUM("Stereo1 ADC1 Source", rt5677_stereo1_adc1_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo2_adc1_enum, RT5677_STO2_ADC_MIXER,
        RT5677_SEL_STO2_ADC1_SFT, rt5677_stereo_adc1_src);

static const struct snd_kcontrol_new rt5677_sto2_adc1_mux =
        SOC_DAPM_ENUM("Stereo2 ADC1 Source", rt5677_stereo2_adc1_enum);

static SOC_ENUM_SINGLE_DECL(
        rt5677_stereo3_adc1_enum, RT5677_STO3_ADC_MIXER,
        RT5677_SEL_STO3_ADC1_SFT, rt5677_stereo_adc1_src);

static const struct snd_kcontrol_new rt5677_sto3_adc1_mux =
        SOC_DAPM_ENUM("Stereo3 ADC1 Source", rt5677_stereo3_adc1_enum);

/* Mono ADC Left Source 2 */ /* MX-28 [11:10] */
static const char * const rt5677_mono_adc2_l_src[] = {
        "DD MIX1L", "DMIC", "MONO DAC MIXL"
};

static SOC_ENUM_SINGLE_DECL(
        rt5677_mono_adc2_l_enum, RT5677_MONO_ADC_MIXER,
        RT5677_SEL_MONO_ADC_L2_SFT, rt5677_mono_adc2_l_src);