1
2
3
4
5
6
7
8
9#include <linux/clk.h>
10#include <linux/io.h>
11#include <linux/module.h>
12#include <linux/regmap.h>
13#include <linux/spinlock.h>
14
15#include <sound/dmaengine_pcm.h>
16#include <sound/pcm_params.h>
17#include <sound/soc.h>
18
19
20
21
22#define SPDIFRX_CR 0x00
23#define SPDIFRX_MR 0x04
24
25#define SPDIFRX_IER 0x10
26#define SPDIFRX_IDR 0x14
27#define SPDIFRX_IMR 0x18
28#define SPDIFRX_ISR 0x1c
29#define SPDIFRX_RSR 0x20
30#define SPDIFRX_RHR 0x24
31
32#define SPDIFRX_CHSR(channel, reg) \
33 (0x30 + (channel) * 0x30 + (reg) * 4)
34
35#define SPDIFRX_CHUD(channel, reg) \
36 (0x48 + (channel) * 0x30 + (reg) * 4)
37
38#define SPDIFRX_WPMR 0xE4
39#define SPDIFRX_WPSR 0xE8
40
41#define SPDIFRX_VERSION 0xFC
42
43
44
45
46#define SPDIFRX_CR_SWRST BIT(0)
47
48
49
50
51
52#define SPDIFRX_MR_RXEN_MASK GENMASK(0, 0)
53#define SPDIFRX_MR_RXEN_DISABLE (0 << 0)
54#define SPDIFRX_MR_RXEN_ENABLE (1 << 0)
55
56
57#define SPDIFRX_MR_VBMODE_MASK GENAMSK(1, 1)
58#define SPDIFRX_MR_VBMODE_ALWAYS_LOAD \
59 (0 << 1)
60#define SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 \
61 (1 << 1)
62
63
64#define SPDIFRX_MR_ENDIAN_MASK GENMASK(2, 2)
65#define SPDIFRX_MR_ENDIAN_LITTLE (0 << 2)
66#define SPDIFRX_MR_ENDIAN_BIG (1 << 2)
67
68
69#define SPDIFRX_MR_PBMODE_MASK GENMASK(3, 3)
70#define SPDIFRX_MR_PBMODE_PARCHECK (0 << 3)
71#define SPDIFRX_MR_PBMODE_NOPARCHECK (1 << 3)
72
73
74#define SPDIFRX_MR_DATAWIDTH_MASK GENMASK(5, 4)
75#define SPDIFRX_MR_DATAWIDTH(width) \
76 (((6 - (width) / 4) << 4) & SPDIFRX_MR_DATAWIDTH_MASK)
77
78
79#define SPDIFRX_MR_PACK_MASK GENMASK(7, 7)
80#define SPDIFRX_MR_PACK_DISABLED (0 << 7)
81#define SPDIFRX_MR_PACK_ENABLED (1 << 7)
82
83
84#define SPDIFRX_MR_SBMODE_MASK GENMASK(8, 8)
85#define SPDIFRX_MR_SBMODE_ALWAYS_LOAD (0 << 8)
86#define SPDIFRX_MR_SBMODE_DISCARD (1 << 8)
87
88
89#define SPDIFRX_MR_AUTORST_MASK GENMASK(24, 24)
90#define SPDIFRX_MR_AUTORST_NOACTION (0 << 24)
91#define SPDIFRX_MR_AUTORST_UNLOCK_ON_PRE_ERR (1 << 24)
92
93
94
95
96#define SPDIFRX_IR_RXRDY BIT(0)
97#define SPDIFRX_IR_LOCKED BIT(1)
98#define SPDIFRX_IR_LOSS BIT(2)
99#define SPDIFRX_IR_BLOCKEND BIT(3)
100#define SPDIFRX_IR_SFE BIT(4)
101#define SPDIFRX_IR_PAR_ERR BIT(5)
102#define SPDIFRX_IR_OVERRUN BIT(6)
103#define SPDIFRX_IR_RXFULL BIT(7)
104#define SPDIFRX_IR_CSC(ch) BIT((ch) + 8)
105#define SPDIFRX_IR_SECE BIT(10)
106#define SPDIFRX_IR_BLOCKST BIT(11)
107#define SPDIFRX_IR_NRZ_ERR BIT(12)
108#define SPDIFRX_IR_PRE_ERR BIT(13)
109#define SPDIFRX_IR_CP_ERR BIT(14)
110
111
112
113
114
115#define SPDIFRX_RSR_ULOCK BIT(0)
116#define SPDIFRX_RSR_BADF BIT(1)
117#define SPDIFRX_RSR_LOWF BIT(2)
118#define SPDIFRX_RSR_NOSIGNAL BIT(3)
119#define SPDIFRX_RSR_IFS_MASK GENMASK(27, 16)
120#define SPDIFRX_RSR_IFS(reg) \
121 (((reg) & SPDIFRX_RSR_IFS_MASK) >> 16)
122
123
124
125
126#define SPDIFRX_VERSION_MASK GENMASK(11, 0)
127#define SPDIFRX_VERSION_MFN_MASK GENMASK(18, 16)
128#define SPDIFRX_VERSION_MFN(reg) (((reg) & SPDIFRX_VERSION_MFN_MASK) >> 16)
129
130static bool mchp_spdifrx_readable_reg(struct device *dev, unsigned int reg)
131{
132 switch (reg) {
133 case SPDIFRX_MR:
134 case SPDIFRX_IMR:
135 case SPDIFRX_ISR:
136 case SPDIFRX_RSR:
137 case SPDIFRX_CHSR(0, 0):
138 case SPDIFRX_CHSR(0, 1):
139 case SPDIFRX_CHSR(0, 2):
140 case SPDIFRX_CHSR(0, 3):
141 case SPDIFRX_CHSR(0, 4):
142 case SPDIFRX_CHSR(0, 5):
143 case SPDIFRX_CHUD(0, 0):
144 case SPDIFRX_CHUD(0, 1):
145 case SPDIFRX_CHUD(0, 2):
146 case SPDIFRX_CHUD(0, 3):
147 case SPDIFRX_CHUD(0, 4):
148 case SPDIFRX_CHUD(0, 5):
149 case SPDIFRX_CHSR(1, 0):
150 case SPDIFRX_CHSR(1, 1):
151 case SPDIFRX_CHSR(1, 2):
152 case SPDIFRX_CHSR(1, 3):
153 case SPDIFRX_CHSR(1, 4):
154 case SPDIFRX_CHSR(1, 5):
155 case SPDIFRX_CHUD(1, 0):
156 case SPDIFRX_CHUD(1, 1):
157 case SPDIFRX_CHUD(1, 2):
158 case SPDIFRX_CHUD(1, 3):
159 case SPDIFRX_CHUD(1, 4):
160 case SPDIFRX_CHUD(1, 5):
161 case SPDIFRX_WPMR:
162 case SPDIFRX_WPSR:
163 case SPDIFRX_VERSION:
164 return true;
165 default:
166 return false;
167 }
168}
169
170static bool mchp_spdifrx_writeable_reg(struct device *dev, unsigned int reg)
171{
172 switch (reg) {
173 case SPDIFRX_CR:
174 case SPDIFRX_MR:
175 case SPDIFRX_IER:
176 case SPDIFRX_IDR:
177 case SPDIFRX_WPMR:
178 return true;
179 default:
180 return false;
181 }
182}
183
184static bool mchp_spdifrx_precious_reg(struct device *dev, unsigned int reg)
185{
186 switch (reg) {
187 case SPDIFRX_ISR:
188 case SPDIFRX_RHR:
189 return true;
190 default:
191 return false;
192 }
193}
194
195static const struct regmap_config mchp_spdifrx_regmap_config = {
196 .reg_bits = 32,
197 .reg_stride = 4,
198 .val_bits = 32,
199 .max_register = SPDIFRX_VERSION,
200 .readable_reg = mchp_spdifrx_readable_reg,
201 .writeable_reg = mchp_spdifrx_writeable_reg,
202 .precious_reg = mchp_spdifrx_precious_reg,
203};
204
205#define SPDIFRX_GCLK_RATIO_MIN (12 * 64)
206
207#define SPDIFRX_CS_BITS 192
208#define SPDIFRX_UD_BITS 192
209
210#define SPDIFRX_CHANNELS 2
211
212struct mchp_spdifrx_ch_stat {
213 unsigned char data[SPDIFRX_CS_BITS / 8];
214 struct completion done;
215};
216
217struct mchp_spdifrx_user_data {
218 unsigned char data[SPDIFRX_UD_BITS / 8];
219 struct completion done;
220 spinlock_t lock;
221};
222
223struct mchp_spdifrx_mixer_control {
224 struct mchp_spdifrx_ch_stat ch_stat[SPDIFRX_CHANNELS];
225 struct mchp_spdifrx_user_data user_data[SPDIFRX_CHANNELS];
226 bool ulock;
227 bool badf;
228 bool signal;
229};
230
231struct mchp_spdifrx_dev {
232 struct snd_dmaengine_dai_dma_data capture;
233 struct mchp_spdifrx_mixer_control control;
234 spinlock_t blockend_lock;
235 int blockend_refcount;
236 struct device *dev;
237 struct regmap *regmap;
238 struct clk *pclk;
239 struct clk *gclk;
240 unsigned int fmt;
241 unsigned int gclk_enabled:1;
242};
243
244static void mchp_spdifrx_channel_status_read(struct mchp_spdifrx_dev *dev,
245 int channel)
246{
247 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
248 u8 *ch_stat = &ctrl->ch_stat[channel].data[0];
249 u32 val;
250 int i;
251
252 for (i = 0; i < ARRAY_SIZE(ctrl->ch_stat[channel].data) / 4; i++) {
253 regmap_read(dev->regmap, SPDIFRX_CHSR(channel, i), &val);
254 *ch_stat++ = val & 0xFF;
255 *ch_stat++ = (val >> 8) & 0xFF;
256 *ch_stat++ = (val >> 16) & 0xFF;
257 *ch_stat++ = (val >> 24) & 0xFF;
258 }
259}
260
261static void mchp_spdifrx_channel_user_data_read(struct mchp_spdifrx_dev *dev,
262 int channel)
263{
264 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
265 u8 *user_data = &ctrl->user_data[channel].data[0];
266 u32 val;
267 int i;
268
269 for (i = 0; i < ARRAY_SIZE(ctrl->user_data[channel].data) / 4; i++) {
270 regmap_read(dev->regmap, SPDIFRX_CHUD(channel, i), &val);
271 *user_data++ = val & 0xFF;
272 *user_data++ = (val >> 8) & 0xFF;
273 *user_data++ = (val >> 16) & 0xFF;
274 *user_data++ = (val >> 24) & 0xFF;
275 }
276}
277
278
279static void mchp_spdifrx_isr_blockend_en(struct mchp_spdifrx_dev *dev)
280{
281 unsigned long flags;
282
283 spin_lock_irqsave(&dev->blockend_lock, flags);
284 dev->blockend_refcount++;
285
286 if (dev->blockend_refcount == 1)
287 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_BLOCKEND);
288 spin_unlock_irqrestore(&dev->blockend_lock, flags);
289}
290
291
292static void mchp_spdifrx_isr_blockend_dis(struct mchp_spdifrx_dev *dev)
293{
294 spin_lock(&dev->blockend_lock);
295 dev->blockend_refcount--;
296
297 if (dev->blockend_refcount == 0)
298 regmap_write(dev->regmap, SPDIFRX_IDR, SPDIFRX_IR_BLOCKEND);
299 spin_unlock(&dev->blockend_lock);
300}
301
302static irqreturn_t mchp_spdif_interrupt(int irq, void *dev_id)
303{
304 struct mchp_spdifrx_dev *dev = dev_id;
305 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
306 u32 sr, imr, pending, idr = 0;
307 irqreturn_t ret = IRQ_NONE;
308 int ch;
309
310 regmap_read(dev->regmap, SPDIFRX_ISR, &sr);
311 regmap_read(dev->regmap, SPDIFRX_IMR, &imr);
312 pending = sr & imr;
313 dev_dbg(dev->dev, "ISR: %#x, IMR: %#x, pending: %#x\n", sr, imr,
314 pending);
315
316 if (!pending)
317 return IRQ_NONE;
318
319 if (pending & SPDIFRX_IR_BLOCKEND) {
320 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
321 spin_lock(&ctrl->user_data[ch].lock);
322 mchp_spdifrx_channel_user_data_read(dev, ch);
323 spin_unlock(&ctrl->user_data[ch].lock);
324
325 complete(&ctrl->user_data[ch].done);
326 }
327 mchp_spdifrx_isr_blockend_dis(dev);
328 ret = IRQ_HANDLED;
329 }
330
331 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
332 if (pending & SPDIFRX_IR_CSC(ch)) {
333 mchp_spdifrx_channel_status_read(dev, ch);
334 complete(&ctrl->ch_stat[ch].done);
335 idr |= SPDIFRX_IR_CSC(ch);
336 ret = IRQ_HANDLED;
337 }
338 }
339
340 if (pending & SPDIFRX_IR_OVERRUN) {
341 dev_warn(dev->dev, "Overrun detected\n");
342 ret = IRQ_HANDLED;
343 }
344
345 regmap_write(dev->regmap, SPDIFRX_IDR, idr);
346
347 return ret;
348}
349
350static int mchp_spdifrx_trigger(struct snd_pcm_substream *substream, int cmd,
351 struct snd_soc_dai *dai)
352{
353 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
354 u32 mr;
355 int running;
356 int ret;
357
358 regmap_read(dev->regmap, SPDIFRX_MR, &mr);
359 running = !!(mr & SPDIFRX_MR_RXEN_ENABLE);
360
361 switch (cmd) {
362 case SNDRV_PCM_TRIGGER_START:
363 case SNDRV_PCM_TRIGGER_RESUME:
364 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
365 if (!running) {
366 mr &= ~SPDIFRX_MR_RXEN_MASK;
367 mr |= SPDIFRX_MR_RXEN_ENABLE;
368
369 regmap_write(dev->regmap, SPDIFRX_IER,
370 SPDIFRX_IR_OVERRUN);
371 }
372 break;
373 case SNDRV_PCM_TRIGGER_STOP:
374 case SNDRV_PCM_TRIGGER_SUSPEND:
375 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
376 if (running) {
377 mr &= ~SPDIFRX_MR_RXEN_MASK;
378 mr |= SPDIFRX_MR_RXEN_DISABLE;
379
380 regmap_write(dev->regmap, SPDIFRX_IDR,
381 SPDIFRX_IR_OVERRUN);
382 }
383 break;
384 default:
385 return -EINVAL;
386 }
387
388 ret = regmap_write(dev->regmap, SPDIFRX_MR, mr);
389 if (ret) {
390 dev_err(dev->dev, "unable to enable/disable RX: %d\n", ret);
391 return ret;
392 }
393
394 return 0;
395}
396
397static int mchp_spdifrx_hw_params(struct snd_pcm_substream *substream,
398 struct snd_pcm_hw_params *params,
399 struct snd_soc_dai *dai)
400{
401 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
402 u32 mr;
403 int ret;
404
405 dev_dbg(dev->dev, "%s() rate=%u format=%#x width=%u channels=%u\n",
406 __func__, params_rate(params), params_format(params),
407 params_width(params), params_channels(params));
408
409 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
410 dev_err(dev->dev, "Playback is not supported\n");
411 return -EINVAL;
412 }
413
414 regmap_read(dev->regmap, SPDIFRX_MR, &mr);
415
416 if (mr & SPDIFRX_MR_RXEN_ENABLE) {
417 dev_err(dev->dev, "PCM already running\n");
418 return -EBUSY;
419 }
420
421 if (params_channels(params) != SPDIFRX_CHANNELS) {
422 dev_err(dev->dev, "unsupported number of channels: %d\n",
423 params_channels(params));
424 return -EINVAL;
425 }
426
427 switch (params_format(params)) {
428 case SNDRV_PCM_FORMAT_S16_BE:
429 case SNDRV_PCM_FORMAT_S20_3BE:
430 case SNDRV_PCM_FORMAT_S24_3BE:
431 case SNDRV_PCM_FORMAT_S24_BE:
432 mr |= SPDIFRX_MR_ENDIAN_BIG;
433 fallthrough;
434 case SNDRV_PCM_FORMAT_S16_LE:
435 case SNDRV_PCM_FORMAT_S20_3LE:
436 case SNDRV_PCM_FORMAT_S24_3LE:
437 case SNDRV_PCM_FORMAT_S24_LE:
438 mr |= SPDIFRX_MR_DATAWIDTH(params_width(params));
439 break;
440 default:
441 dev_err(dev->dev, "unsupported PCM format: %d\n",
442 params_format(params));
443 return -EINVAL;
444 }
445
446 if (dev->gclk_enabled) {
447 clk_disable_unprepare(dev->gclk);
448 dev->gclk_enabled = 0;
449 }
450 ret = clk_set_min_rate(dev->gclk, params_rate(params) *
451 SPDIFRX_GCLK_RATIO_MIN + 1);
452 if (ret) {
453 dev_err(dev->dev,
454 "unable to set gclk min rate: rate %u * ratio %u + 1\n",
455 params_rate(params), SPDIFRX_GCLK_RATIO_MIN);
456 return ret;
457 }
458 ret = clk_prepare_enable(dev->gclk);
459 if (ret) {
460 dev_err(dev->dev, "unable to enable gclk: %d\n", ret);
461 return ret;
462 }
463 dev->gclk_enabled = 1;
464
465 dev_dbg(dev->dev, "GCLK range min set to %d\n",
466 params_rate(params) * SPDIFRX_GCLK_RATIO_MIN + 1);
467
468 return regmap_write(dev->regmap, SPDIFRX_MR, mr);
469}
470
471static int mchp_spdifrx_hw_free(struct snd_pcm_substream *substream,
472 struct snd_soc_dai *dai)
473{
474 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
475
476 if (dev->gclk_enabled) {
477 clk_disable_unprepare(dev->gclk);
478 dev->gclk_enabled = 0;
479 }
480 return 0;
481}
482
483static const struct snd_soc_dai_ops mchp_spdifrx_dai_ops = {
484 .trigger = mchp_spdifrx_trigger,
485 .hw_params = mchp_spdifrx_hw_params,
486 .hw_free = mchp_spdifrx_hw_free,
487};
488
489#define MCHP_SPDIF_RATES SNDRV_PCM_RATE_8000_192000
490
491#define MCHP_SPDIF_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
492 SNDRV_PCM_FMTBIT_U16_BE | \
493 SNDRV_PCM_FMTBIT_S20_3LE | \
494 SNDRV_PCM_FMTBIT_S20_3BE | \
495 SNDRV_PCM_FMTBIT_S24_3LE | \
496 SNDRV_PCM_FMTBIT_S24_3BE | \
497 SNDRV_PCM_FMTBIT_S24_LE | \
498 SNDRV_PCM_FMTBIT_S24_BE \
499 )
500
501static int mchp_spdifrx_info(struct snd_kcontrol *kcontrol,
502 struct snd_ctl_elem_info *uinfo)
503{
504 uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
505 uinfo->count = 1;
506
507 return 0;
508}
509
510static int mchp_spdifrx_cs_get(struct mchp_spdifrx_dev *dev,
511 int channel,
512 struct snd_ctl_elem_value *uvalue)
513{
514 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
515 struct mchp_spdifrx_ch_stat *ch_stat = &ctrl->ch_stat[channel];
516 int ret;
517
518 regmap_write(dev->regmap, SPDIFRX_IER, SPDIFRX_IR_CSC(channel));
519
520 ret = wait_for_completion_interruptible_timeout(&ch_stat->done,
521 msecs_to_jiffies(100));
522
523 if (ret < 0) {
524 dev_dbg(dev->dev, "channel status for channel %d timeout\n",
525 channel);
526 }
527
528 memcpy(uvalue->value.iec958.status, ch_stat->data,
529 sizeof(ch_stat->data));
530
531 return 0;
532}
533
534static int mchp_spdifrx_cs1_get(struct snd_kcontrol *kcontrol,
535 struct snd_ctl_elem_value *uvalue)
536{
537 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
538 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
539
540 return mchp_spdifrx_cs_get(dev, 0, uvalue);
541}
542
543static int mchp_spdifrx_cs2_get(struct snd_kcontrol *kcontrol,
544 struct snd_ctl_elem_value *uvalue)
545{
546 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
547 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
548
549 return mchp_spdifrx_cs_get(dev, 1, uvalue);
550}
551
552static int mchp_spdifrx_cs_mask(struct snd_kcontrol *kcontrol,
553 struct snd_ctl_elem_value *uvalue)
554{
555 memset(uvalue->value.iec958.status, 0xff,
556 sizeof(uvalue->value.iec958.status));
557
558 return 0;
559}
560
561static int mchp_spdifrx_subcode_ch_get(struct mchp_spdifrx_dev *dev,
562 int channel,
563 struct snd_ctl_elem_value *uvalue)
564{
565 unsigned long flags;
566 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
567 struct mchp_spdifrx_user_data *user_data = &ctrl->user_data[channel];
568 int ret;
569
570 reinit_completion(&user_data->done);
571 mchp_spdifrx_isr_blockend_en(dev);
572 ret = wait_for_completion_interruptible_timeout(&user_data->done,
573 msecs_to_jiffies(100));
574
575 if (ret <= 0) {
576 dev_dbg(dev->dev, "user data for channel %d timeout\n",
577 channel);
578 return ret;
579 }
580
581 spin_lock_irqsave(&user_data->lock, flags);
582 memcpy(uvalue->value.iec958.subcode, user_data->data,
583 sizeof(user_data->data));
584 spin_unlock_irqrestore(&user_data->lock, flags);
585
586 return 0;
587}
588
589static int mchp_spdifrx_subcode_ch1_get(struct snd_kcontrol *kcontrol,
590 struct snd_ctl_elem_value *uvalue)
591{
592 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
593 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
594
595 return mchp_spdifrx_subcode_ch_get(dev, 0, uvalue);
596}
597
598static int mchp_spdifrx_subcode_ch2_get(struct snd_kcontrol *kcontrol,
599 struct snd_ctl_elem_value *uvalue)
600{
601 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
602 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
603
604 return mchp_spdifrx_subcode_ch_get(dev, 1, uvalue);
605}
606
607static int mchp_spdifrx_boolean_info(struct snd_kcontrol *kcontrol,
608 struct snd_ctl_elem_info *uinfo)
609{
610 uinfo->type = SNDRV_CTL_ELEM_TYPE_BOOLEAN;
611 uinfo->count = 1;
612 uinfo->value.integer.min = 0;
613 uinfo->value.integer.max = 1;
614
615 return 0;
616}
617
618static int mchp_spdifrx_ulock_get(struct snd_kcontrol *kcontrol,
619 struct snd_ctl_elem_value *uvalue)
620{
621 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
622 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
623 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
624 u32 val;
625 bool ulock_old = ctrl->ulock;
626
627 regmap_read(dev->regmap, SPDIFRX_RSR, &val);
628 ctrl->ulock = !(val & SPDIFRX_RSR_ULOCK);
629 uvalue->value.integer.value[0] = ctrl->ulock;
630
631 return ulock_old != ctrl->ulock;
632}
633
634static int mchp_spdifrx_badf_get(struct snd_kcontrol *kcontrol,
635 struct snd_ctl_elem_value *uvalue)
636{
637 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
638 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
639 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
640 u32 val;
641 bool badf_old = ctrl->badf;
642
643 regmap_read(dev->regmap, SPDIFRX_RSR, &val);
644 ctrl->badf = !!(val & SPDIFRX_RSR_BADF);
645 uvalue->value.integer.value[0] = ctrl->badf;
646
647 return badf_old != ctrl->badf;
648}
649
650static int mchp_spdifrx_signal_get(struct snd_kcontrol *kcontrol,
651 struct snd_ctl_elem_value *uvalue)
652{
653 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
654 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
655 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
656 u32 val;
657 bool signal_old = ctrl->signal;
658
659 regmap_read(dev->regmap, SPDIFRX_RSR, &val);
660 ctrl->signal = !(val & SPDIFRX_RSR_NOSIGNAL);
661 uvalue->value.integer.value[0] = ctrl->signal;
662
663 return signal_old != ctrl->signal;
664}
665
666static int mchp_spdifrx_rate_info(struct snd_kcontrol *kcontrol,
667 struct snd_ctl_elem_info *uinfo)
668{
669 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
670 uinfo->count = 1;
671 uinfo->value.integer.min = 0;
672 uinfo->value.integer.max = 192000;
673
674 return 0;
675}
676
677static int mchp_spdifrx_rate_get(struct snd_kcontrol *kcontrol,
678 struct snd_ctl_elem_value *ucontrol)
679{
680 struct snd_soc_dai *dai = snd_kcontrol_chip(kcontrol);
681 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
682 u32 val;
683 int rate;
684
685 regmap_read(dev->regmap, SPDIFRX_RSR, &val);
686
687
688 if (val & SPDIFRX_RSR_ULOCK || !(val & SPDIFRX_RSR_IFS_MASK)) {
689 ucontrol->value.integer.value[0] = 0;
690 return 0;
691 }
692
693 rate = clk_get_rate(dev->gclk);
694
695 ucontrol->value.integer.value[0] = rate / (32 * SPDIFRX_RSR_IFS(val));
696
697 return 0;
698}
699
700static struct snd_kcontrol_new mchp_spdifrx_ctrls[] = {
701
702 {
703 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
704 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT)
705 " Channel 1",
706 .access = SNDRV_CTL_ELEM_ACCESS_READ |
707 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
708 .info = mchp_spdifrx_info,
709 .get = mchp_spdifrx_cs1_get,
710 },
711 {
712 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
713 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, DEFAULT)
714 " Channel 2",
715 .access = SNDRV_CTL_ELEM_ACCESS_READ |
716 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
717 .info = mchp_spdifrx_info,
718 .get = mchp_spdifrx_cs2_get,
719 },
720 {
721 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
722 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, MASK),
723 .access = SNDRV_CTL_ELEM_ACCESS_READ,
724 .info = mchp_spdifrx_info,
725 .get = mchp_spdifrx_cs_mask,
726 },
727
728 {
729 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
730 .name = "IEC958 Subcode Capture Default Channel 1",
731 .access = SNDRV_CTL_ELEM_ACCESS_READ |
732 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
733 .info = mchp_spdifrx_info,
734 .get = mchp_spdifrx_subcode_ch1_get,
735 },
736 {
737 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
738 .name = "IEC958 Subcode Capture Default Channel 2",
739 .access = SNDRV_CTL_ELEM_ACCESS_READ |
740 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
741 .info = mchp_spdifrx_info,
742 .get = mchp_spdifrx_subcode_ch2_get,
743 },
744
745 {
746 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
747 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Unlocked",
748 .access = SNDRV_CTL_ELEM_ACCESS_READ |
749 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
750 .info = mchp_spdifrx_boolean_info,
751 .get = mchp_spdifrx_ulock_get,
752 },
753
754 {
755 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
756 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE)"Bad Format",
757 .access = SNDRV_CTL_ELEM_ACCESS_READ |
758 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
759 .info = mchp_spdifrx_boolean_info,
760 .get = mchp_spdifrx_badf_get,
761 },
762
763 {
764 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
765 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Signal",
766 .access = SNDRV_CTL_ELEM_ACCESS_READ |
767 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
768 .info = mchp_spdifrx_boolean_info,
769 .get = mchp_spdifrx_signal_get,
770 },
771
772 {
773 .iface = SNDRV_CTL_ELEM_IFACE_PCM,
774 .name = SNDRV_CTL_NAME_IEC958("", CAPTURE, NONE) "Rate",
775 .access = SNDRV_CTL_ELEM_ACCESS_READ |
776 SNDRV_CTL_ELEM_ACCESS_VOLATILE,
777 .info = mchp_spdifrx_rate_info,
778 .get = mchp_spdifrx_rate_get,
779 },
780};
781
782static int mchp_spdifrx_dai_probe(struct snd_soc_dai *dai)
783{
784 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
785 struct mchp_spdifrx_mixer_control *ctrl = &dev->control;
786 int ch;
787 int err;
788
789 err = clk_prepare_enable(dev->pclk);
790 if (err) {
791 dev_err(dev->dev,
792 "failed to enable the peripheral clock: %d\n", err);
793 return err;
794 }
795
796 snd_soc_dai_init_dma_data(dai, NULL, &dev->capture);
797
798
799 regmap_write(dev->regmap, SPDIFRX_CR, SPDIFRX_CR_SWRST);
800
801
802 regmap_write(dev->regmap, SPDIFRX_MR,
803 SPDIFRX_MR_VBMODE_DISCARD_IF_VB1 |
804 SPDIFRX_MR_SBMODE_DISCARD |
805 SPDIFRX_MR_AUTORST_NOACTION |
806 SPDIFRX_MR_PACK_DISABLED);
807
808 dev->blockend_refcount = 0;
809 for (ch = 0; ch < SPDIFRX_CHANNELS; ch++) {
810 init_completion(&ctrl->ch_stat[ch].done);
811 init_completion(&ctrl->user_data[ch].done);
812 spin_lock_init(&ctrl->user_data[ch].lock);
813 }
814
815
816 snd_soc_add_dai_controls(dai, mchp_spdifrx_ctrls,
817 ARRAY_SIZE(mchp_spdifrx_ctrls));
818
819 return 0;
820}
821
822static int mchp_spdifrx_dai_remove(struct snd_soc_dai *dai)
823{
824 struct mchp_spdifrx_dev *dev = snd_soc_dai_get_drvdata(dai);
825
826
827 regmap_write(dev->regmap, SPDIFRX_IDR, 0xFF);
828
829 clk_disable_unprepare(dev->pclk);
830
831 return 0;
832}
833
834static struct snd_soc_dai_driver mchp_spdifrx_dai = {
835 .name = "mchp-spdifrx",
836 .probe = mchp_spdifrx_dai_probe,
837 .remove = mchp_spdifrx_dai_remove,
838 .capture = {
839 .stream_name = "S/PDIF Capture",
840 .channels_min = SPDIFRX_CHANNELS,
841 .channels_max = SPDIFRX_CHANNELS,
842 .rates = MCHP_SPDIF_RATES,
843 .formats = MCHP_SPDIF_FORMATS,
844 },
845 .ops = &mchp_spdifrx_dai_ops,
846};
847
848static const struct snd_soc_component_driver mchp_spdifrx_component = {
849 .name = "mchp-spdifrx",
850};
851
852static const struct of_device_id mchp_spdifrx_dt_ids[] = {
853 {
854 .compatible = "microchip,sama7g5-spdifrx",
855 },
856 { }
857};
858MODULE_DEVICE_TABLE(of, mchp_spdifrx_dt_ids);
859
860static int mchp_spdifrx_probe(struct platform_device *pdev)
861{
862 struct mchp_spdifrx_dev *dev;
863 struct resource *mem;
864 struct regmap *regmap;
865 void __iomem *base;
866 int irq;
867 int err;
868 u32 vers;
869
870
871 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
872 if (!dev)
873 return -ENOMEM;
874
875
876 base = devm_platform_get_and_ioremap_resource(pdev, 0, &mem);
877 if (IS_ERR(base))
878 return PTR_ERR(base);
879
880 regmap = devm_regmap_init_mmio(&pdev->dev, base,
881 &mchp_spdifrx_regmap_config);
882 if (IS_ERR(regmap))
883 return PTR_ERR(regmap);
884
885
886 irq = platform_get_irq(pdev, 0);
887 if (irq < 0)
888 return irq;
889
890 err = devm_request_irq(&pdev->dev, irq, mchp_spdif_interrupt, 0,
891 dev_name(&pdev->dev), dev);
892 if (err)
893 return err;
894
895
896 dev->pclk = devm_clk_get(&pdev->dev, "pclk");
897 if (IS_ERR(dev->pclk)) {
898 err = PTR_ERR(dev->pclk);
899 dev_err(&pdev->dev, "failed to get the peripheral clock: %d\n",
900 err);
901 return err;
902 }
903
904
905 dev->gclk = devm_clk_get(&pdev->dev, "gclk");
906 if (IS_ERR(dev->gclk)) {
907 err = PTR_ERR(dev->gclk);
908 dev_err(&pdev->dev,
909 "failed to get the PMC generated clock: %d\n", err);
910 return err;
911 }
912 spin_lock_init(&dev->blockend_lock);
913
914 dev->dev = &pdev->dev;
915 dev->regmap = regmap;
916 platform_set_drvdata(pdev, dev);
917
918 dev->capture.addr = (dma_addr_t)mem->start + SPDIFRX_RHR;
919 dev->capture.maxburst = 1;
920
921 err = devm_snd_dmaengine_pcm_register(&pdev->dev, NULL, 0);
922 if (err) {
923 dev_err(&pdev->dev, "failed to register PMC: %d\n", err);
924 return err;
925 }
926
927 err = devm_snd_soc_register_component(&pdev->dev,
928 &mchp_spdifrx_component,
929 &mchp_spdifrx_dai, 1);
930 if (err) {
931 dev_err(&pdev->dev, "fail to register dai\n");
932 return err;
933 }
934
935 regmap_read(regmap, SPDIFRX_VERSION, &vers);
936 dev_info(&pdev->dev, "hw version: %#lx\n", vers & SPDIFRX_VERSION_MASK);
937
938 return 0;
939}
940
941static struct platform_driver mchp_spdifrx_driver = {
942 .probe = mchp_spdifrx_probe,
943 .driver = {
944 .name = "mchp_spdifrx",
945 .of_match_table = of_match_ptr(mchp_spdifrx_dt_ids),
946 },
947};
948
949module_platform_driver(mchp_spdifrx_driver);
950
951MODULE_AUTHOR("Codrin Ciubotariu <codrin.ciubotariu@microchip.com>");
952MODULE_DESCRIPTION("Microchip S/PDIF RX Controller Driver");
953MODULE_LICENSE("GPL v2");
954
