// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *   ALSA driver for RME Hammerfall DSP audio interface(s)
 *
 *      Copyright (c) 2002  Paul Davis
 *                          Marcus Andersson
 *                          Thomas Charbonnel
 */

#include <linux/init.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/firmware.h>
#include <linux/module.h>
#include <linux/math64.h>
#include <linux/vmalloc.h>
#include <linux/io.h>
#include <linux/nospec.h>

#include <sound/core.h>
#include <sound/control.h>
#include <sound/pcm.h>
#include <sound/info.h>
#include <sound/asoundef.h>
#include <sound/rawmidi.h>
#include <sound/hwdep.h>
#include <sound/initval.h>
#include <sound/hdsp.h>

#include <asm/byteorder.h>
#include <asm/current.h>

static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;      /* Index 0-MAX */
static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;       /* ID for this card */
static bool enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;     /* Enable this card */

module_param_array(index, int, NULL, 0444);
MODULE_PARM_DESC(index, "Index value for RME Hammerfall DSP interface.");
module_param_array(id, charp, NULL, 0444);
MODULE_PARM_DESC(id, "ID string for RME Hammerfall DSP interface.");
module_param_array(enable, bool, NULL, 0444);
MODULE_PARM_DESC(enable, "Enable/disable specific Hammerfall DSP soundcards.");
MODULE_AUTHOR("Paul Davis <paul@linuxaudiosystems.com>, Marcus Andersson, Thomas Charbonnel <thomas@undata.org>");
MODULE_DESCRIPTION("RME Hammerfall DSP");
MODULE_LICENSE("GPL");
MODULE_FIRMWARE("rpm_firmware.bin");
MODULE_FIRMWARE("multiface_firmware.bin");
MODULE_FIRMWARE("multiface_firmware_rev11.bin");
MODULE_FIRMWARE("digiface_firmware.bin");
MODULE_FIRMWARE("digiface_firmware_rev11.bin");

#define HDSP_MAX_CHANNELS        26
#define HDSP_MAX_DS_CHANNELS     14
#define HDSP_MAX_QS_CHANNELS     8
#define DIGIFACE_SS_CHANNELS     26
#define DIGIFACE_DS_CHANNELS     14
#define MULTIFACE_SS_CHANNELS    18
#define MULTIFACE_DS_CHANNELS    14
#define H9652_SS_CHANNELS        26
#define H9652_DS_CHANNELS        14
/* This does not include possible Analog Extension Boards
   AEBs are detected at card initialization
*/
#define H9632_SS_CHANNELS        12
#define H9632_DS_CHANNELS        8
#define H9632_QS_CHANNELS        4
#define RPM_CHANNELS             6

/* Write registers. These are defined as byte-offsets from the iobase value.
 */
#define HDSP_resetPointer               0
#define HDSP_freqReg                    0
#define HDSP_outputBufferAddress        32
#define HDSP_inputBufferAddress         36
#define HDSP_controlRegister            64
#define HDSP_interruptConfirmation      96
#define HDSP_outputEnable               128
#define HDSP_control2Reg                256
#define HDSP_midiDataOut0               352
#define HDSP_midiDataOut1               356
#define HDSP_fifoData                   368
#define HDSP_inputEnable                384

/* Read registers. These are defined as byte-offsets from the iobase value
 */

#define HDSP_statusRegister    0
#define HDSP_timecode        128
#define HDSP_status2Register 192
#define HDSP_midiDataIn0     360
#define HDSP_midiDataIn1     364
#define HDSP_midiStatusOut0  384
#define HDSP_midiStatusOut1  388
#define HDSP_midiStatusIn0   392
#define HDSP_midiStatusIn1   396
#define HDSP_fifoStatus      400

/* the meters are regular i/o-mapped registers, but offset
   considerably from the rest. the peak registers are reset
   when read; the least-significant 4 bits are full-scale counters;
   the actual peak value is in the most-significant 24 bits.
*/

#define HDSP_playbackPeakLevel  4096  /* 26 * 32 bit values */
#define HDSP_inputPeakLevel     4224  /* 26 * 32 bit values */
#define HDSP_outputPeakLevel    4352  /* (26+2) * 32 bit values */
#define HDSP_playbackRmsLevel   4612  /* 26 * 64 bit values */
#define HDSP_inputRmsLevel      4868  /* 26 * 64 bit values */


/* This is for H9652 cards
   Peak values are read downward from the base
   Rms values are read upward
   There are rms values for the outputs too
   26*3 values are read in ss mode
   14*3 in ds mode, with no gap between values
*/
#define HDSP_9652_peakBase      7164
#define HDSP_9652_rmsBase       4096

/* c.f. the hdsp_9632_meters_t struct */
#define HDSP_9632_metersBase    4096

#define HDSP_IO_EXTENT     7168

/* control2 register bits */

#define HDSP_TMS                0x01
#define HDSP_TCK                0x02
#define HDSP_TDI                0x04
#define HDSP_JTAG               0x08
#define HDSP_PWDN               0x10
#define HDSP_PROGRAM            0x020
#define HDSP_CONFIG_MODE_0      0x040
#define HDSP_CONFIG_MODE_1      0x080
#define HDSP_VERSION_BIT        (0x100 | HDSP_S_LOAD)
#define HDSP_BIGENDIAN_MODE     0x200
#define HDSP_RD_MULTIPLE        0x400
#define HDSP_9652_ENABLE_MIXER  0x800
#define HDSP_S200               0x800
#define HDSP_S300               (0x100 | HDSP_S200) /* dummy, purpose of 0x100 unknown */
#define HDSP_CYCLIC_MODE        0x1000
#define HDSP_TDO                0x10000000

#define HDSP_S_PROGRAM      (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_0)
#define HDSP_S_LOAD         (HDSP_CYCLIC_MODE|HDSP_PROGRAM|HDSP_CONFIG_MODE_1)

/* Control Register bits */

#define HDSP_Start                (1<<0)  /* start engine */
#define HDSP_Latency0             (1<<1)  /* buffer size = 2^n where n is defined by Latency{2,1,0} */
#define HDSP_Latency1             (1<<2)  /* [ see above ] */
#define HDSP_Latency2             (1<<3)  /* [ see above ] */
#define HDSP_ClockModeMaster      (1<<4)  /* 1=Master, 0=Slave/Autosync */
#define HDSP_AudioInterruptEnable (1<<5)  /* what do you think ? */
#define HDSP_Frequency0           (1<<6)  /* 0=44.1kHz/88.2kHz/176.4kHz 1=48kHz/96kHz/192kHz */
#define HDSP_Frequency1           (1<<7)  /* 0=32kHz/64kHz/128kHz */
#define HDSP_DoubleSpeed          (1<<8)  /* 0=normal speed, 1=double speed */
#define HDSP_SPDIFProfessional    (1<<9)  /* 0=consumer, 1=professional */
#define HDSP_SPDIFEmphasis        (1<<10) /* 0=none, 1=on */
#define HDSP_SPDIFNonAudio        (1<<11) /* 0=off, 1=on */
#define HDSP_SPDIFOpticalOut      (1<<12) /* 1=use 1st ADAT connector for SPDIF, 0=do not */
#define HDSP_SyncRef2             (1<<13)
#define HDSP_SPDIFInputSelect0    (1<<14)
#define HDSP_SPDIFInputSelect1    (1<<15)
#define HDSP_SyncRef0             (1<<16)
#define HDSP_SyncRef1             (1<<17)
#define HDSP_AnalogExtensionBoard (1<<18) /* For H9632 cards */
#define HDSP_XLRBreakoutCable     (1<<20) /* For H9632 cards */
#define HDSP_Midi0InterruptEnable (1<<22)
#define HDSP_Midi1InterruptEnable (1<<23)
#define HDSP_LineOut              (1<<24)
#define HDSP_ADGain0              (1<<25) /* From here : H9632 specific */
#define HDSP_ADGain1              (1<<26)
#define HDSP_DAGain0              (1<<27)
#define HDSP_DAGain1              (1<<28)
#define HDSP_PhoneGain0           (1<<29)
#define HDSP_PhoneGain1           (1<<30)
#define HDSP_QuadSpeed            (1<<31)

/* RPM uses some of the registers for special purposes */
#define HDSP_RPM_Inp12            0x04A00
#define HDSP_RPM_Inp12_Phon_6dB   0x00800  /* Dolby */
#define HDSP_RPM_Inp12_Phon_0dB   0x00000  /* .. */
#define HDSP_RPM_Inp12_Phon_n6dB  0x04000  /* inp_0 */
#define HDSP_RPM_Inp12_Line_0dB   0x04200  /* Dolby+PRO */
#define HDSP_RPM_Inp12_Line_n6dB  0x00200  /* PRO */

#define HDSP_RPM_Inp34            0x32000
#define HDSP_RPM_Inp34_Phon_6dB   0x20000  /* SyncRef1 */
#define HDSP_RPM_Inp34_Phon_0dB   0x00000  /* .. */
#define HDSP_RPM_Inp34_Phon_n6dB  0x02000  /* SyncRef2 */
#define HDSP_RPM_Inp34_Line_0dB   0x30000  /* SyncRef1+SyncRef0 */
#define HDSP_RPM_Inp34_Line_n6dB  0x10000  /* SyncRef0 */

#define HDSP_RPM_Bypass           0x01000

#define HDSP_RPM_Disconnect       0x00001

#define HDSP_ADGainMask       (HDSP_ADGain0|HDSP_ADGain1)
#define HDSP_ADGainMinus10dBV  HDSP_ADGainMask
#define HDSP_ADGainPlus4dBu   (HDSP_ADGain0)
#define HDSP_ADGainLowGain     0

#define HDSP_DAGainMask         (HDSP_DAGain0|HDSP_DAGain1)
#define HDSP_DAGainHighGain      HDSP_DAGainMask
#define HDSP_DAGainPlus4dBu     (HDSP_DAGain0)
#define HDSP_DAGainMinus10dBV    0

#define HDSP_PhoneGainMask      (HDSP_PhoneGain0|HDSP_PhoneGain1)
#define HDSP_PhoneGain0dB        HDSP_PhoneGainMask
#define HDSP_PhoneGainMinus6dB  (HDSP_PhoneGain0)
#define HDSP_PhoneGainMinus12dB  0

#define HDSP_LatencyMask    (HDSP_Latency0|HDSP_Latency1|HDSP_Latency2)
#define HDSP_FrequencyMask  (HDSP_Frequency0|HDSP_Frequency1|HDSP_DoubleSpeed|HDSP_QuadSpeed)

#define HDSP_SPDIFInputMask    (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)
#define HDSP_SPDIFInputADAT1    0
#define HDSP_SPDIFInputCoaxial (HDSP_SPDIFInputSelect0)
#define HDSP_SPDIFInputCdrom   (HDSP_SPDIFInputSelect1)
#define HDSP_SPDIFInputAES     (HDSP_SPDIFInputSelect0|HDSP_SPDIFInputSelect1)

#define HDSP_SyncRefMask        (HDSP_SyncRef0|HDSP_SyncRef1|HDSP_SyncRef2)
#define HDSP_SyncRef_ADAT1       0
#define HDSP_SyncRef_ADAT2      (HDSP_SyncRef0)
#define HDSP_SyncRef_ADAT3      (HDSP_SyncRef1)
#define HDSP_SyncRef_SPDIF      (HDSP_SyncRef0|HDSP_SyncRef1)
#define HDSP_SyncRef_WORD       (HDSP_SyncRef2)
#define HDSP_SyncRef_ADAT_SYNC  (HDSP_SyncRef0|HDSP_SyncRef2)

/* Sample Clock Sources */

#define HDSP_CLOCK_SOURCE_AUTOSYNC           0
#define HDSP_CLOCK_SOURCE_INTERNAL_32KHZ     1
#define HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ   2
#define HDSP_CLOCK_SOURCE_INTERNAL_48KHZ     3
#define HDSP_CLOCK_SOURCE_INTERNAL_64KHZ     4
#define HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ   5
#define HDSP_CLOCK_SOURCE_INTERNAL_96KHZ     6
#define HDSP_CLOCK_SOURCE_INTERNAL_128KHZ    7
#define HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ  8
#define HDSP_CLOCK_SOURCE_INTERNAL_192KHZ    9

/* Preferred sync reference choices - used by "pref_sync_ref" control switch */

#define HDSP_SYNC_FROM_WORD      0
#define HDSP_SYNC_FROM_SPDIF     1
#define HDSP_SYNC_FROM_ADAT1     2
#define HDSP_SYNC_FROM_ADAT_SYNC 3
#define HDSP_SYNC_FROM_ADAT2     4
#define HDSP_SYNC_FROM_ADAT3     5

/* SyncCheck status */

#define HDSP_SYNC_CHECK_NO_LOCK 0
#define HDSP_SYNC_CHECK_LOCK    1
#define HDSP_SYNC_CHECK_SYNC    2

/* AutoSync references - used by "autosync_ref" control switch */

#define HDSP_AUTOSYNC_FROM_WORD      0
#define HDSP_AUTOSYNC_FROM_ADAT_SYNC 1
#define HDSP_AUTOSYNC_FROM_SPDIF     2
#define HDSP_AUTOSYNC_FROM_NONE      3
#define HDSP_AUTOSYNC_FROM_ADAT1     4
#define HDSP_AUTOSYNC_FROM_ADAT2     5
#define HDSP_AUTOSYNC_FROM_ADAT3     6

/* Possible sources of S/PDIF input */

#define HDSP_SPDIFIN_OPTICAL  0 /* optical  (ADAT1) */
#define HDSP_SPDIFIN_COAXIAL  1 /* coaxial (RCA) */
#define HDSP_SPDIFIN_INTERNAL 2 /* internal (CDROM) */
#define HDSP_SPDIFIN_AES      3 /* xlr for H9632 (AES)*/

#define HDSP_Frequency32KHz    HDSP_Frequency0
#define HDSP_Frequency44_1KHz  HDSP_Frequency1
#define HDSP_Frequency48KHz    (HDSP_Frequency1|HDSP_Frequency0)
#define HDSP_Frequency64KHz    (HDSP_DoubleSpeed|HDSP_Frequency0)
#define HDSP_Frequency88_2KHz  (HDSP_DoubleSpeed|HDSP_Frequency1)
#define HDSP_Frequency96KHz    (HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
/* For H9632 cards */
#define HDSP_Frequency128KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency0)
#define HDSP_Frequency176_4KHz (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1)
#define HDSP_Frequency192KHz   (HDSP_QuadSpeed|HDSP_DoubleSpeed|HDSP_Frequency1|HDSP_Frequency0)
/* RME says n = 104857600000000, but in the windows MADI driver, I see:
        return 104857600000000 / rate; // 100 MHz
        return 110100480000000 / rate; // 105 MHz
*/
#define DDS_NUMERATOR 104857600000000ULL  /*  =  2^20 * 10^8 */

#define hdsp_encode_latency(x)       (((x)<<1) & HDSP_LatencyMask)
#define hdsp_decode_latency(x)       (((x) & HDSP_LatencyMask)>>1)

#define hdsp_encode_spdif_in(x) (((x)&0x3)<<14)
#define hdsp_decode_spdif_in(x) (((x)>>14)&0x3)

/* Status Register bits */

#define HDSP_audioIRQPending    (1<<0)
#define HDSP_Lock2              (1<<1)     /* this is for Digiface and H9652 */
#define HDSP_spdifFrequency3    HDSP_Lock2 /* this is for H9632 only */
#define HDSP_Lock1              (1<<2)
#define HDSP_Lock0              (1<<3)
#define HDSP_SPDIFSync          (1<<4)
#define HDSP_TimecodeLock       (1<<5)
#define HDSP_BufferPositionMask 0x000FFC0 /* Bit 6..15 : h/w buffer pointer */
#define HDSP_Sync2              (1<<16)
#define HDSP_Sync1              (1<<17)
#define HDSP_Sync0              (1<<18)
#define HDSP_DoubleSpeedStatus  (1<<19)
#define HDSP_ConfigError        (1<<20)
#define HDSP_DllError           (1<<21)
#define HDSP_spdifFrequency0    (1<<22)
#define HDSP_spdifFrequency1    (1<<23)
#define HDSP_spdifFrequency2    (1<<24)
#define HDSP_SPDIFErrorFlag     (1<<25)
#define HDSP_BufferID           (1<<26)
#define HDSP_TimecodeSync       (1<<27)
#define HDSP_AEBO               (1<<28) /* H9632 specific Analog Extension Boards */
#define HDSP_AEBI               (1<<29) /* 0 = present, 1 = absent */
#define HDSP_midi0IRQPending    (1<<30)
#define HDSP_midi1IRQPending    (1<<31)

#define HDSP_spdifFrequencyMask    (HDSP_spdifFrequency0|HDSP_spdifFrequency1|HDSP_spdifFrequency2)
#define HDSP_spdifFrequencyMask_9632 (HDSP_spdifFrequency0|\
                                      HDSP_spdifFrequency1|\
                                      HDSP_spdifFrequency2|\
                                      HDSP_spdifFrequency3)

#define HDSP_spdifFrequency32KHz   (HDSP_spdifFrequency0)
#define HDSP_spdifFrequency44_1KHz (HDSP_spdifFrequency1)
#define HDSP_spdifFrequency48KHz   (HDSP_spdifFrequency0|HDSP_spdifFrequency1)

#define HDSP_spdifFrequency64KHz   (HDSP_spdifFrequency2)
#define HDSP_spdifFrequency88_2KHz (HDSP_spdifFrequency0|HDSP_spdifFrequency2)
#define HDSP_spdifFrequency96KHz   (HDSP_spdifFrequency2|HDSP_spdifFrequency1)

/* This is for H9632 cards */
#define HDSP_spdifFrequency128KHz   (HDSP_spdifFrequency0|\
                                     HDSP_spdifFrequency1|\
                                     HDSP_spdifFrequency2)
#define HDSP_spdifFrequency176_4KHz HDSP_spdifFrequency3
#define HDSP_spdifFrequency192KHz   (HDSP_spdifFrequency3|HDSP_spdifFrequency0)

/* Status2 Register bits */

#define HDSP_version0     (1<<0)
#define HDSP_version1     (1<<1)
#define HDSP_version2     (1<<2)
#define HDSP_wc_lock      (1<<3)
#define HDSP_wc_sync      (1<<4)
#define HDSP_inp_freq0    (1<<5)
#define HDSP_inp_freq1    (1<<6)
#define HDSP_inp_freq2    (1<<7)
#define HDSP_SelSyncRef0  (1<<8)
#define HDSP_SelSyncRef1  (1<<9)
#define HDSP_SelSyncRef2  (1<<10)

#define HDSP_wc_valid (HDSP_wc_lock|HDSP_wc_sync)

#define HDSP_systemFrequencyMask (HDSP_inp_freq0|HDSP_inp_freq1|HDSP_inp_freq2)
#define HDSP_systemFrequency32   (HDSP_inp_freq0)
#define HDSP_systemFrequency44_1 (HDSP_inp_freq1)
#define HDSP_systemFrequency48   (HDSP_inp_freq0|HDSP_inp_freq1)
#define HDSP_systemFrequency64   (HDSP_inp_freq2)
#define HDSP_systemFrequency88_2 (HDSP_inp_freq0|HDSP_inp_freq2)
#define HDSP_systemFrequency96   (HDSP_inp_freq1|HDSP_inp_freq2)
/* FIXME : more values for 9632 cards ? */

#define HDSP_SelSyncRefMask        (HDSP_SelSyncRef0|HDSP_SelSyncRef1|HDSP_SelSyncRef2)
#define HDSP_SelSyncRef_ADAT1      0
#define HDSP_SelSyncRef_ADAT2      (HDSP_SelSyncRef0)
#define HDSP_SelSyncRef_ADAT3      (HDSP_SelSyncRef1)
#define HDSP_SelSyncRef_SPDIF      (HDSP_SelSyncRef0|HDSP_SelSyncRef1)
#define HDSP_SelSyncRef_WORD       (HDSP_SelSyncRef2)
#define HDSP_SelSyncRef_ADAT_SYNC  (HDSP_SelSyncRef0|HDSP_SelSyncRef2)

/* Card state flags */

#define HDSP_InitializationComplete  (1<<0)
#define HDSP_FirmwareLoaded          (1<<1)
#define HDSP_FirmwareCached          (1<<2)

/* FIFO wait times, defined in terms of 1/10ths of msecs */

#define HDSP_LONG_WAIT   5000
#define HDSP_SHORT_WAIT  30

#define UNITY_GAIN                       32768
#define MINUS_INFINITY_GAIN              0

/* the size of a substream (1 mono data stream) */

#define HDSP_CHANNEL_BUFFER_SAMPLES  (16*1024)
#define HDSP_CHANNEL_BUFFER_BYTES    (4*HDSP_CHANNEL_BUFFER_SAMPLES)

/* the size of the area we need to allocate for DMA transfers. the
   size is the same regardless of the number of channels - the
   Multiface still uses the same memory area.

   Note that we allocate 1 more channel than is apparently needed
   because the h/w seems to write 1 byte beyond the end of the last
   page. Sigh.
*/

#define HDSP_DMA_AREA_BYTES ((HDSP_MAX_CHANNELS+1) * HDSP_CHANNEL_BUFFER_BYTES)
#define HDSP_DMA_AREA_KILOBYTES (HDSP_DMA_AREA_BYTES/1024)

#define HDSP_FIRMWARE_SIZE      (24413 * 4)

struct hdsp_9632_meters {
    u32 input_peak[16];
    u32 playback_peak[16];
    u32 output_peak[16];
    u32 xxx_peak[16];
    u32 padding[64];
    u32 input_rms_low[16];
    u32 playback_rms_low[16];
    u32 output_rms_low[16];
    u32 xxx_rms_low[16];
    u32 input_rms_high[16];
    u32 playback_rms_high[16];
    u32 output_rms_high[16];
    u32 xxx_rms_high[16];
};

struct hdsp_midi {
    struct hdsp             *hdsp;
    int                      id;
    struct snd_rawmidi           *rmidi;
    struct snd_rawmidi_substream *input;
    struct snd_rawmidi_substream *output;
    char                     istimer; /* timer in use */
    struct timer_list        timer;
    spinlock_t               lock;
    int                      pending;
};

struct hdsp {
        spinlock_t            lock;
        struct snd_pcm_substream *capture_substream;
        struct snd_pcm_substream *playback_substream;
        struct hdsp_midi      midi[2];
        struct work_struct    midi_work;
        int                   use_midi_work;
        int                   precise_ptr;
        u32                   control_register;      /* cached value */
        u32                   control2_register;     /* cached value */
        u32                   creg_spdif;
        u32                   creg_spdif_stream;
        int                   clock_source_locked;
        char                 *card_name;         /* digiface/multiface/rpm */
        enum HDSP_IO_Type     io_type;               /* ditto, but for code use */
        unsigned short        firmware_rev;
        unsigned short        state;                 /* stores state bits */
        const struct firmware *firmware;
        u32                  *fw_uploaded;
        size_t                period_bytes;          /* guess what this is */
        unsigned char         max_channels;
        unsigned char         qs_in_channels;        /* quad speed mode for H9632 */
        unsigned char         ds_in_channels;
        unsigned char         ss_in_channels;       /* different for multiface/digiface */
        unsigned char         qs_out_channels;
        unsigned char         ds_out_channels;
        unsigned char         ss_out_channels;
        u32                   io_loopback;          /* output loopback channel states*/

        struct snd_dma_buffer capture_dma_buf;
        struct snd_dma_buffer playback_dma_buf;
        unsigned char        *capture_buffer;       /* suitably aligned address */
        unsigned char        *playback_buffer;      /* suitably aligned address */

        pid_t                 capture_pid;
        pid_t                 playback_pid;
        int                   running;
        int                   system_sample_rate;
        const char           *channel_map;
        int                   dev;
        int                   irq;
        unsigned long         port;
        void __iomem         *iobase;
        struct snd_card *card;
        struct snd_pcm *pcm;
        struct snd_hwdep          *hwdep;
        struct pci_dev       *pci;
        struct snd_kcontrol *spdif_ctl;
        unsigned short        mixer_matrix[HDSP_MATRIX_MIXER_SIZE];
        unsigned int          dds_value; /* last value written to freq register */
};

/* These tables map the ALSA channels 1..N to the channels that we
   need to use in order to find the relevant channel buffer. RME
   refer to this kind of mapping as between "the ADAT channel and
   the DMA channel." We index it using the logical audio channel,
   and the value is the DMA channel (i.e. channel buffer number)
   where the data for that channel can be read/written from/to.
*/

static const char channel_map_df_ss[HDSP_MAX_CHANNELS] = {
        0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,
        18, 19, 20, 21, 22, 23, 24, 25
};

static const char channel_map_mf_ss[HDSP_MAX_CHANNELS] = { /* Multiface */
        /* Analog */
        0, 1, 2, 3, 4, 5, 6, 7,
        /* ADAT 2 */
        16, 17, 18, 19, 20, 21, 22, 23,
        /* SPDIF */
        24, 25,
        -1, -1, -1, -1, -1, -1, -1, -1
};

static const char channel_map_ds[HDSP_MAX_CHANNELS] = {
        /* ADAT channels are remapped */
        1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23,
        /* channels 12 and 13 are S/PDIF */
        24, 25,
        /* others don't exist */
        -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1
};

static const char channel_map_H9632_ss[HDSP_MAX_CHANNELS] = {
        /* ADAT channels */
        0, 1, 2, 3, 4, 5, 6, 7,
        /* SPDIF */
        8, 9,
        /* Analog */
        10, 11,
        /* AO4S-192 and AI4S-192 extension boards */
        12, 13, 14, 15,
        /* others don't exist */
        -1, -1, -1, -1, -1, -1, -1, -1,
        -1, -1
};

static const char channel_map_H9632_ds[HDSP_MAX_CHANNELS] = {
        /* ADAT */
        1, 3, 5, 7,
        /* SPDIF */
        8, 9,
        /* Analog */
        10, 11,
        /* AO4S-192 and AI4S-192 extension boards */
        12, 13, 14, 15,
        /* others don't exist */
        -1, -1, -1, -1, -1, -1, -1, -1,
        -1, -1, -1, -1, -1, -1
};

static const char channel_map_H9632_qs[HDSP_MAX_CHANNELS] = {
        /* ADAT is disabled in this mode */
        /* SPDIF */
        8, 9,
        /* Analog */
        10, 11,
        /* AO4S-192 and AI4S-192 extension boards */
        12, 13, 14, 15,
        /* others don't exist */
        -1, -1, -1, -1, -1, -1, -1, -1,
        -1, -1, -1, -1, -1, -1, -1, -1,
        -1, -1
};

static int snd_hammerfall_get_buffer(struct pci_dev *pci, struct snd_dma_buffer *dmab, size_t size)
{
        return snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV, &pci->dev, size, dmab);
}

static void snd_hammerfall_free_buffer(struct snd_dma_buffer *dmab, struct pci_dev *pci)
{
        if (dmab->area)
                snd_dma_free_pages(dmab);
}


static const struct pci_device_id snd_hdsp_ids[] = {
        {
                .vendor = PCI_VENDOR_ID_XILINX,
                .device = PCI_DEVICE_ID_XILINX_HAMMERFALL_DSP,
                .subvendor = PCI_ANY_ID,
                .subdevice = PCI_ANY_ID,
        }, /* RME Hammerfall-DSP */
        { 0, },
};

MODULE_DEVICE_TABLE(pci, snd_hdsp_ids);

/* prototypes */
static int snd_hdsp_create_alsa_devices(struct snd_card *card, struct hdsp *hdsp);
static int snd_hdsp_create_pcm(struct snd_card *card, struct hdsp *hdsp);
static int snd_hdsp_enable_io (struct hdsp *hdsp);
static void snd_hdsp_initialize_midi_flush (struct hdsp *hdsp);
static void snd_hdsp_initialize_channels (struct hdsp *hdsp);
static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout);
static int hdsp_autosync_ref(struct hdsp *hdsp);
static int snd_hdsp_set_defaults(struct hdsp *hdsp);
static void snd_hdsp_9652_enable_mixer (struct hdsp *hdsp);

static int hdsp_playback_to_output_key (struct hdsp *hdsp, int in, int out)
{
        switch (hdsp->io_type) {
        case Multiface:
        case Digiface:
        case RPM:
        default:
                if (hdsp->firmware_rev == 0xa)
                        return (64 * out) + (32 + (in));
                else
                        return (52 * out) + (26 + (in));
        case H9632:
                return (32 * out) + (16 + (in));
        case H9652:
                return (52 * out) + (26 + (in));
        }
}

static int hdsp_input_to_output_key (struct hdsp *hdsp, int in, int out)
{
        switch (hdsp->io_type) {
        case Multiface:
        case Digiface:
        case RPM:
        default:
                if (hdsp->firmware_rev == 0xa)
                        return (64 * out) + in;
                else
                        return (52 * out) + in;
        case H9632:
                return (32 * out) + in;
        case H9652:
                return (52 * out) + in;
        }
}

static void hdsp_write(struct hdsp *hdsp, int reg, int val)
{
        writel(val, hdsp->iobase + reg);
}

static unsigned int hdsp_read(struct hdsp *hdsp, int reg)
{
        return readl (hdsp->iobase + reg);
}

static int hdsp_check_for_iobox (struct hdsp *hdsp)
{
        int i;

        if (hdsp->io_type == H9652 || hdsp->io_type == H9632) return 0;
        for (i = 0; i < 500; i++) {
                if (0 == (hdsp_read(hdsp, HDSP_statusRegister) &
                                        HDSP_ConfigError)) {
                        if (i) {
                                dev_dbg(hdsp->card->dev,
                                        "IO box found after %d ms\n",
                                                (20 * i));
                        }
                        return 0;
                }
                msleep(20);
        }
        dev_err(hdsp->card->dev, "no IO box connected!\n");
        hdsp->state &= ~HDSP_FirmwareLoaded;
        return -EIO;
}

static int hdsp_wait_for_iobox(struct hdsp *hdsp, unsigned int loops,
                               unsigned int delay)
{
        unsigned int i;

        if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
                return 0;

        for (i = 0; i != loops; ++i) {
                if (hdsp_read(hdsp, HDSP_statusRegister) & HDSP_ConfigError)
                        msleep(delay);
                else {
                        dev_dbg(hdsp->card->dev, "iobox found after %ums!\n",
                                   i * delay);
                        return 0;
                }
        }

        dev_info(hdsp->card->dev, "no IO box connected!\n");
        hdsp->state &= ~HDSP_FirmwareLoaded;
        return -EIO;
}

static int snd_hdsp_load_firmware_from_cache(struct hdsp *hdsp) {

        int i;
        unsigned long flags;
        const u32 *cache;

        if (hdsp->fw_uploaded)
                cache = hdsp->fw_uploaded;
        else {
                if (!hdsp->firmware)
                        return -ENODEV;
                cache = (u32 *)hdsp->firmware->data;
                if (!cache)
                        return -ENODEV;
        }

        if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {

                dev_info(hdsp->card->dev, "loading firmware\n");

                hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_PROGRAM);
                hdsp_write (hdsp, HDSP_fifoData, 0);

                if (hdsp_fifo_wait (hdsp, 0, HDSP_LONG_WAIT)) {
                        dev_info(hdsp->card->dev,
                                 "timeout waiting for download preparation\n");
                        hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
                        return -EIO;
                }

                hdsp_write (hdsp, HDSP_control2Reg, HDSP_S_LOAD);

                for (i = 0; i < HDSP_FIRMWARE_SIZE / 4; ++i) {
                        hdsp_write(hdsp, HDSP_fifoData, cache[i]);
                        if (hdsp_fifo_wait (hdsp, 127, HDSP_LONG_WAIT)) {
                                dev_info(hdsp->card->dev,
                                         "timeout during firmware loading\n");
                                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);
                                return -EIO;
                        }
                }

                hdsp_fifo_wait(hdsp, 3, HDSP_LONG_WAIT);
                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200);

                ssleep(3);
#ifdef SNDRV_BIG_ENDIAN
                hdsp->control2_register = HDSP_BIGENDIAN_MODE;
#else
                hdsp->control2_register = 0;
#endif
                hdsp_write (hdsp, HDSP_control2Reg, hdsp->control2_register);
                dev_info(hdsp->card->dev, "finished firmware loading\n");

        }
        if (hdsp->state & HDSP_InitializationComplete) {
                dev_info(hdsp->card->dev,
                         "firmware loaded from cache, restoring defaults\n");
                spin_lock_irqsave(&hdsp->lock, flags);
                snd_hdsp_set_defaults(hdsp);
                spin_unlock_irqrestore(&hdsp->lock, flags);
        }

        hdsp->state |= HDSP_FirmwareLoaded;

        return 0;
}

static int hdsp_get_iobox_version (struct hdsp *hdsp)
{
        if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {

                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
                hdsp_write(hdsp, HDSP_fifoData, 0);

                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0) {
                        hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
                        hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
                }

                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S200 | HDSP_PROGRAM);
                hdsp_write (hdsp, HDSP_fifoData, 0);
                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
                        goto set_multi;

                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
                hdsp_write(hdsp, HDSP_fifoData, 0);
                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0) {
                        hdsp->io_type = Digiface;
                        dev_info(hdsp->card->dev, "Digiface found\n");
                        return 0;
                }

                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
                hdsp_write(hdsp, HDSP_fifoData, 0);
                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) == 0)
                        goto set_multi;

                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S300);
                hdsp_write(hdsp, HDSP_control2Reg, HDSP_S_LOAD);
                hdsp_write(hdsp, HDSP_fifoData, 0);
                if (hdsp_fifo_wait(hdsp, 0, HDSP_SHORT_WAIT) < 0)
                        goto set_multi;

                hdsp->io_type = RPM;
                dev_info(hdsp->card->dev, "RPM found\n");
                return 0;
        } else {
                /* firmware was already loaded, get iobox type */
                if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version2)
                        hdsp->io_type = RPM;
                else if (hdsp_read(hdsp, HDSP_status2Register) & HDSP_version1)
                        hdsp->io_type = Multiface;
                else
                        hdsp->io_type = Digiface;
        }
        return 0;

set_multi:
        hdsp->io_type = Multiface;
        dev_info(hdsp->card->dev, "Multiface found\n");
        return 0;
}


static int hdsp_request_fw_loader(struct hdsp *hdsp);

static int hdsp_check_for_firmware (struct hdsp *hdsp, int load_on_demand)
{
        if (hdsp->io_type == H9652 || hdsp->io_type == H9632)
                return 0;
        if ((hdsp_read (hdsp, HDSP_statusRegister) & HDSP_DllError) != 0) {
                hdsp->state &= ~HDSP_FirmwareLoaded;
                if (! load_on_demand)
                        return -EIO;
                dev_err(hdsp->card->dev, "firmware not present.\n");
                /* try to load firmware */
                if (! (hdsp->state & HDSP_FirmwareCached)) {
                        if (! hdsp_request_fw_loader(hdsp))
                                return 0;
                        dev_err(hdsp->card->dev,
                                   "No firmware loaded nor cached, please upload firmware.\n");
                        return -EIO;
                }
                if (snd_hdsp_load_firmware_from_cache(hdsp) != 0) {
                        dev_err(hdsp->card->dev,
                                   "Firmware loading from cache failed, please upload manually.\n");
                        return -EIO;
                }
        }
        return 0;
}


static int hdsp_fifo_wait(struct hdsp *hdsp, int count, int timeout)
{
        int i;

        /* the fifoStatus registers reports on how many words
           are available in the command FIFO.
        */

        for (i = 0; i < timeout; i++) {

                if ((int)(hdsp_read (hdsp, HDSP_fifoStatus) & 0xff) <= count)
                        return 0;

                /* not very friendly, but we only do this during a firmware
                   load and changing the mixer, so we just put up with it.
                */

                udelay (100);
        }

        dev_warn(hdsp->card->dev,
                 "wait for FIFO status <= %d failed after %d iterations\n",
                    count, timeout);
        return -1;
}

static int hdsp_read_gain (struct hdsp *hdsp, unsigned int addr)
{
        if (addr >= HDSP_MATRIX_MIXER_SIZE)
                return 0;

        return hdsp->mixer_matrix[addr];
}

static int hdsp_write_gain(struct hdsp *hdsp, unsigned int addr, unsigned short data)
{
        unsigned int ad;

        if (addr >= HDSP_MATRIX_MIXER_SIZE)
                return -1;

        if (hdsp->io_type == H9652 || hdsp->io_type == H9632) {

                /* from martin bjornsen:

                   "You can only write dwords to the
                   mixer memory which contain two
                   mixer values in the low and high
                   word. So if you want to change
                   value 0 you have to read value 1
                   from the cache and write both to
                   the first dword in the mixer
                   memory."
                */

                if (hdsp->io_type == H9632 && addr >= 512)
                        return 0;

                if (hdsp->io_type == H9652 && addr >= 1352)
                        return 0;

                hdsp->mixer_matrix[addr] = data;


                /* `addr' addresses a 16-bit wide address, but
                   the address space accessed via hdsp_write
                   uses byte offsets. put another way, addr
                   varies from 0 to 1351, but to access the
                   corresponding memory location, we need
                   to access 0 to 2703 ...
                */
                ad = addr/2;

                hdsp_write (hdsp, 4096 + (ad*4),
                            (hdsp->mixer_matrix[(addr&0x7fe)+1] << 16) +
                            hdsp->mixer_matrix[addr&0x7fe]);

                return 0;

        } else {

                ad = (addr << 16) + data;

                if (hdsp_fifo_wait(hdsp, 127, HDSP_LONG_WAIT))
                        return -1;

                hdsp_write (hdsp, HDSP_fifoData, ad);
                hdsp->mixer_matrix[addr] = data;

        }

        return 0;
}

static int snd_hdsp_use_is_exclusive(struct hdsp *hdsp)
{
        unsigned long flags;
        int ret = 1;

        spin_lock_irqsave(&hdsp->lock, flags);
        if ((hdsp->playback_pid != hdsp->capture_pid) &&
            (hdsp->playback_pid >= 0) && (hdsp->capture_pid >= 0))
                ret = 0;
        spin_unlock_irqrestore(&hdsp->lock, flags);
        return ret;
}

static int hdsp_spdif_sample_rate(struct hdsp *hdsp)
{
        unsigned int status = hdsp_read(hdsp, HDSP_statusRegister);
        unsigned int rate_bits = (status & HDSP_spdifFrequencyMask);

        /* For the 9632, the mask is different */
        if (hdsp->io_type == H9632)
                 rate_bits = (status & HDSP_spdifFrequencyMask_9632);

        if (status & HDSP_SPDIFErrorFlag)
                return 0;

        switch (rate_bits) {
        case HDSP_spdifFrequency32KHz: return 32000;
        case HDSP_spdifFrequency44_1KHz: return 44100;
        case HDSP_spdifFrequency48KHz: return 48000;
        case HDSP_spdifFrequency64KHz: return 64000;
        case HDSP_spdifFrequency88_2KHz: return 88200;
        case HDSP_spdifFrequency96KHz: return 96000;
        case HDSP_spdifFrequency128KHz:
                if (hdsp->io_type == H9632) return 128000;
                break;
        case HDSP_spdifFrequency176_4KHz:
                if (hdsp->io_type == H9632) return 176400;
                break;
        case HDSP_spdifFrequency192KHz:
                if (hdsp->io_type == H9632) return 192000;
                break;
        default:
                break;
        }
        dev_warn(hdsp->card->dev,
                 "unknown spdif frequency status; bits = 0x%x, status = 0x%x\n",
                 rate_bits, status);
        return 0;
}

static int hdsp_external_sample_rate(struct hdsp *hdsp)
{
        unsigned int status2 = hdsp_read(hdsp, HDSP_status2Register);
        unsigned int rate_bits = status2 & HDSP_systemFrequencyMask;

        /* For the 9632 card, there seems to be no bit for indicating external
         * sample rate greater than 96kHz. The card reports the corresponding
         * single speed. So the best means seems to get spdif rate when

         * autosync reference is spdif */
        if (hdsp->io_type == H9632 &&
            hdsp_autosync_ref(hdsp) == HDSP_AUTOSYNC_FROM_SPDIF)
                 return hdsp_spdif_sample_rate(hdsp);

        switch (rate_bits) {
        case HDSP_systemFrequency32:   return 32000;
        case HDSP_systemFrequency44_1: return 44100;
        case HDSP_systemFrequency48:   return 48000;
        case HDSP_systemFrequency64:   return 64000;
        case HDSP_systemFrequency88_2: return 88200;
        case HDSP_systemFrequency96:   return 96000;
        default:
                return 0;
        }
}

static void hdsp_compute_period_size(struct hdsp *hdsp)
{
        hdsp->period_bytes = 1 << ((hdsp_decode_latency(hdsp->control_register) + 8));
}

static snd_pcm_uframes_t hdsp_hw_pointer(struct hdsp *hdsp)
{
        int position;

        position = hdsp_read(hdsp, HDSP_statusRegister);

        if (!hdsp->precise_ptr)
                return (position & HDSP_BufferID) ? (hdsp->period_bytes / 4) : 0;

        position &= HDSP_BufferPositionMask;
        position /= 4;
        position &= (hdsp->period_bytes/2) - 1;
        return position;
}

static void hdsp_reset_hw_pointer(struct hdsp *hdsp)
{
        hdsp_write (hdsp, HDSP_resetPointer, 0);
        if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
                /* HDSP_resetPointer = HDSP_freqReg, which is strange and
                 * requires (?) to write again DDS value after a reset pointer
                 * (at least, it works like this) */
                hdsp_write (hdsp, HDSP_freqReg, hdsp->dds_value);
}

static void hdsp_start_audio(struct hdsp *s)
{
        s->control_register |= (HDSP_AudioInterruptEnable | HDSP_Start);
        hdsp_write(s, HDSP_controlRegister, s->control_register);
}

static void hdsp_stop_audio(struct hdsp *s)
{
        s->control_register &= ~(HDSP_Start | HDSP_AudioInterruptEnable);
        hdsp_write(s, HDSP_controlRegister, s->control_register);
}

static void hdsp_silence_playback(struct hdsp *hdsp)
{
        memset(hdsp->playback_buffer, 0, HDSP_DMA_AREA_BYTES);
}

static int hdsp_set_interrupt_interval(struct hdsp *s, unsigned int frames)
{
        int n;

        spin_lock_irq(&s->lock);

        frames >>= 7;
        n = 0;
        while (frames) {
                n++;
                frames >>= 1;
        }

        s->control_register &= ~HDSP_LatencyMask;
        s->control_register |= hdsp_encode_latency(n);

        hdsp_write(s, HDSP_controlRegister, s->control_register);

        hdsp_compute_period_size(s);

        spin_unlock_irq(&s->lock);

        return 0;
}

static void hdsp_set_dds_value(struct hdsp *hdsp, int rate)
{
        u64 n;

        if (rate >= 112000)
                rate /= 4;
        else if (rate >= 56000)
                rate /= 2;

        n = DDS_NUMERATOR;
        n = div_u64(n, rate);
        /* n should be less than 2^32 for being written to FREQ register */
        snd_BUG_ON(n >> 32);
        /* HDSP_freqReg and HDSP_resetPointer are the same, so keep the DDS
           value to write it after a reset */
        hdsp->dds_value = n;
        hdsp_write(hdsp, HDSP_freqReg, hdsp->dds_value);
}

static int hdsp_set_rate(struct hdsp *hdsp, int rate, int called_internally)
{
        int reject_if_open = 0;
        int current_rate;
        int rate_bits;

        /* ASSUMPTION: hdsp->lock is either held, or
           there is no need for it (e.g. during module
           initialization).
        */

        if (!(hdsp->control_register & HDSP_ClockModeMaster)) {
                if (called_internally) {
                        /* request from ctl or card initialization */
                        dev_err(hdsp->card->dev,
                                "device is not running as a clock master: cannot set sample rate.\n");
                        return -1;
                } else {
                        /* hw_param request while in AutoSync mode */
                        int external_freq = hdsp_external_sample_rate(hdsp);
                        int spdif_freq = hdsp_spdif_sample_rate(hdsp);

                        if ((spdif_freq == external_freq*2) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
                                dev_info(hdsp->card->dev,
                                         "Detected ADAT in double speed mode\n");
                        else if (hdsp->io_type == H9632 && (spdif_freq == external_freq*4) && (hdsp_autosync_ref(hdsp) >= HDSP_AUTOSYNC_FROM_ADAT1))
                                dev_info(hdsp->card->dev,
                                         "Detected ADAT in quad speed mode\n");
                        else if (rate != external_freq) {
                                dev_info(hdsp->card->dev,
                                         "No AutoSync source for requested rate\n");
                                return -1;
                        }
                }
        }

        current_rate = hdsp->system_sample_rate;

        /* Changing from a "single speed" to a "double speed" rate is
           not allowed if any substreams are open. This is because
           such a change causes a shift in the location of
           the DMA buffers and a reduction in the number of available
           buffers.

           Note that a similar but essentially insoluble problem
           exists for externally-driven rate changes. All we can do
           is to flag rate changes in the read/write routines.  */

        if (rate > 96000 && hdsp->io_type != H9632)
                return -EINVAL;

        switch (rate) {
        case 32000:
                if (current_rate > 48000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency32KHz;
                break;
        case 44100:
                if (current_rate > 48000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency44_1KHz;
                break;
        case 48000:
                if (current_rate > 48000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency48KHz;
                break;
        case 64000:
                if (current_rate <= 48000 || current_rate > 96000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency64KHz;
                break;
        case 88200:
                if (current_rate <= 48000 || current_rate > 96000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency88_2KHz;
                break;
        case 96000:
                if (current_rate <= 48000 || current_rate > 96000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency96KHz;
                break;
        case 128000:
                if (current_rate < 128000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency128KHz;
                break;
        case 176400:
                if (current_rate < 128000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency176_4KHz;
                break;
        case 192000:
                if (current_rate < 128000)
                        reject_if_open = 1;
                rate_bits = HDSP_Frequency192KHz;
                break;
        default:
                return -EINVAL;
        }

        if (reject_if_open && (hdsp->capture_pid >= 0 || hdsp->playback_pid >= 0)) {
                dev_warn(hdsp->card->dev,
                         "cannot change speed mode (capture PID = %d, playback PID = %d)\n",
                            hdsp->capture_pid,
                            hdsp->playback_pid);
                return -EBUSY;
        }

        hdsp->control_register &= ~HDSP_FrequencyMask;
        hdsp->control_register |= rate_bits;
        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);

        /* For HDSP9632 rev 152, need to set DDS value in FREQ register */
        if (hdsp->io_type == H9632 && hdsp->firmware_rev >= 152)
                hdsp_set_dds_value(hdsp, rate);

        if (rate >= 128000) {
                hdsp->channel_map = channel_map_H9632_qs;
        } else if (rate > 48000) {
                if (hdsp->io_type == H9632)
                        hdsp->channel_map = channel_map_H9632_ds;
                else
                        hdsp->channel_map = channel_map_ds;
        } else {
                switch (hdsp->io_type) {
                case RPM:
                case Multiface:
                        hdsp->channel_map = channel_map_mf_ss;
                        break;
                case Digiface:
                case H9652:
                        hdsp->channel_map = channel_map_df_ss;
                        break;
                case H9632:
                        hdsp->channel_map = channel_map_H9632_ss;
                        break;
                default:
                        /* should never happen */
                        break;
                }
        }

        hdsp->system_sample_rate = rate;

        return 0;
}

/*----------------------------------------------------------------------------
   MIDI
  ----------------------------------------------------------------------------*/

static unsigned char snd_hdsp_midi_read_byte (struct hdsp *hdsp, int id)
{
        /* the hardware already does the relevant bit-mask with 0xff */
        if (id)
                return hdsp_read(hdsp, HDSP_midiDataIn1);
        else
                return hdsp_read(hdsp, HDSP_midiDataIn0);
}

static void snd_hdsp_midi_write_byte (struct hdsp *hdsp, int id, int val)
{
        /* the hardware already does the relevant bit-mask with 0xff */
        if (id)
                hdsp_write(hdsp, HDSP_midiDataOut1, val);
        else
                hdsp_write(hdsp, HDSP_midiDataOut0, val);
}

static int snd_hdsp_midi_input_available (struct hdsp *hdsp, int id)
{
        if (id)
                return (hdsp_read(hdsp, HDSP_midiStatusIn1) & 0xff);
        else
                return (hdsp_read(hdsp, HDSP_midiStatusIn0) & 0xff);
}

static int snd_hdsp_midi_output_possible (struct hdsp *hdsp, int id)
{
        int fifo_bytes_used;

        if (id)
                fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut1) & 0xff;
        else
                fifo_bytes_used = hdsp_read(hdsp, HDSP_midiStatusOut0) & 0xff;

        if (fifo_bytes_used < 128)
                return  128 - fifo_bytes_used;
        else
                return 0;
}

static void snd_hdsp_flush_midi_input (struct hdsp *hdsp, int id)
{
        while (snd_hdsp_midi_input_available (hdsp, id))
                snd_hdsp_midi_read_byte (hdsp, id);
}

static int snd_hdsp_midi_output_write (struct hdsp_midi *hmidi)
{
        unsigned long flags;
        int n_pending;
        int to_write;
        int i;
        unsigned char buf[128];

        /* Output is not interrupt driven */

        spin_lock_irqsave (&hmidi->lock, flags);
        if (hmidi->output) {
                if (!snd_rawmidi_transmit_empty (hmidi->output)) {
                        n_pending = snd_hdsp_midi_output_possible(hmidi->hdsp, hmidi->id);
                        if (n_pending > 0) {
                                if (n_pending > (int)sizeof (buf))
                                        n_pending = sizeof (buf);

                                to_write = snd_rawmidi_transmit(hmidi->output, buf, n_pending);
                                if (to_write > 0) {
                                        for (i = 0; i < to_write; ++i)
                                                snd_hdsp_midi_write_byte (hmidi->hdsp, hmidi->id, buf[i]);
                                }
                        }
                }
        }
        spin_unlock_irqrestore (&hmidi->lock, flags);
        return 0;
}

static int snd_hdsp_midi_input_read (struct hdsp_midi *hmidi)
{
        unsigned char buf[128]; /* this buffer is designed to match the MIDI input FIFO size */
        unsigned long flags;
        int n_pending;
        int i;

        spin_lock_irqsave (&hmidi->lock, flags);
        n_pending = snd_hdsp_midi_input_available(hmidi->hdsp, hmidi->id);
        if (n_pending > 0) {
                if (hmidi->input) {
                        if (n_pending > (int)sizeof (buf))
                                n_pending = sizeof (buf);
                        for (i = 0; i < n_pending; ++i)
                                buf[i] = snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
                        if (n_pending)
                                snd_rawmidi_receive (hmidi->input, buf, n_pending);
                } else {
                        /* flush the MIDI input FIFO */
                        while (--n_pending)
                                snd_hdsp_midi_read_byte (hmidi->hdsp, hmidi->id);
                }
        }
        hmidi->pending = 0;
        if (hmidi->id)
                hmidi->hdsp->control_register |= HDSP_Midi1InterruptEnable;
        else
                hmidi->hdsp->control_register |= HDSP_Midi0InterruptEnable;
        hdsp_write(hmidi->hdsp, HDSP_controlRegister, hmidi->hdsp->control_register);
        spin_unlock_irqrestore (&hmidi->lock, flags);
        return snd_hdsp_midi_output_write (hmidi);
}

static void snd_hdsp_midi_input_trigger(struct snd_rawmidi_substream *substream, int up)
{
        struct hdsp *hdsp;
        struct hdsp_midi *hmidi;
        unsigned long flags;
        u32 ie;

        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
        hdsp = hmidi->hdsp;
        ie = hmidi->id ? HDSP_Midi1InterruptEnable : HDSP_Midi0InterruptEnable;
        spin_lock_irqsave (&hdsp->lock, flags);
        if (up) {
                if (!(hdsp->control_register & ie)) {
                        snd_hdsp_flush_midi_input (hdsp, hmidi->id);
                        hdsp->control_register |= ie;
                }
        } else {
                hdsp->control_register &= ~ie;
        }

        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
        spin_unlock_irqrestore (&hdsp->lock, flags);
}

static void snd_hdsp_midi_output_timer(struct timer_list *t)
{
        struct hdsp_midi *hmidi = from_timer(hmidi, t, timer);
        unsigned long flags;

        snd_hdsp_midi_output_write(hmidi);
        spin_lock_irqsave (&hmidi->lock, flags);

        /* this does not bump hmidi->istimer, because the
           kernel automatically removed the timer when it
           expired, and we are now adding it back, thus
           leaving istimer wherever it was set before.
        */

        if (hmidi->istimer)
                mod_timer(&hmidi->timer, 1 + jiffies);

        spin_unlock_irqrestore (&hmidi->lock, flags);
}

static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up)
{
        struct hdsp_midi *hmidi;
        unsigned long flags;

        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
        spin_lock_irqsave (&hmidi->lock, flags);
        if (up) {
                if (!hmidi->istimer) {
                        timer_setup(&hmidi->timer, snd_hdsp_midi_output_timer,
                                    0);
                        mod_timer(&hmidi->timer, 1 + jiffies);
                        hmidi->istimer++;
                }
        } else {
                if (hmidi->istimer && --hmidi->istimer <= 0)
                        del_timer (&hmidi->timer);
        }
        spin_unlock_irqrestore (&hmidi->lock, flags);
        if (up)
                snd_hdsp_midi_output_write(hmidi);
}

static int snd_hdsp_midi_input_open(struct snd_rawmidi_substream *substream)
{
        struct hdsp_midi *hmidi;

        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
        spin_lock_irq (&hmidi->lock);
        snd_hdsp_flush_midi_input (hmidi->hdsp, hmidi->id);
        hmidi->input = substream;
        spin_unlock_irq (&hmidi->lock);

        return 0;
}

static int snd_hdsp_midi_output_open(struct snd_rawmidi_substream *substream)
{
        struct hdsp_midi *hmidi;

        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
        spin_lock_irq (&hmidi->lock);
        hmidi->output = substream;
        spin_unlock_irq (&hmidi->lock);

        return 0;
}

static int snd_hdsp_midi_input_close(struct snd_rawmidi_substream *substream)
{
        struct hdsp_midi *hmidi;

        snd_hdsp_midi_input_trigger (substream, 0);

        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
        spin_lock_irq (&hmidi->lock);
        hmidi->input = NULL;
        spin_unlock_irq (&hmidi->lock);

        return 0;
}

static int snd_hdsp_midi_output_close(struct snd_rawmidi_substream *substream)
{
        struct hdsp_midi *hmidi;

        snd_hdsp_midi_output_trigger (substream, 0);

        hmidi = (struct hdsp_midi *) substream->rmidi->private_data;
        spin_lock_irq (&hmidi->lock);
        hmidi->output = NULL;
        spin_unlock_irq (&hmidi->lock);

        return 0;
}

static const struct snd_rawmidi_ops snd_hdsp_midi_output =
{
        .open =         snd_hdsp_midi_output_open,
        .close =        snd_hdsp_midi_output_close,
        .trigger =      snd_hdsp_midi_output_trigger,
};

static const struct snd_rawmidi_ops snd_hdsp_midi_input =
{
        .open =         snd_hdsp_midi_input_open,
        .close =        snd_hdsp_midi_input_close,
        .trigger =      snd_hdsp_midi_input_trigger,
};

static int snd_hdsp_create_midi (struct snd_card *card, struct hdsp *hdsp, int id)
{
        char buf[40];

        hdsp->midi[id].id = id;
        hdsp->midi[id].rmidi = NULL;
        hdsp->midi[id].input = NULL;
        hdsp->midi[id].output = NULL;
        hdsp->midi[id].hdsp = hdsp;
        hdsp->midi[id].istimer = 0;
        hdsp->midi[id].pending = 0;
        spin_lock_init (&hdsp->midi[id].lock);

        snprintf(buf, sizeof(buf), "%s MIDI %d", card->shortname, id + 1);
        if (snd_rawmidi_new (card, buf, id, 1, 1, &hdsp->midi[id].rmidi) < 0)
                return -1;

        sprintf(hdsp->midi[id].rmidi->name, "HDSP MIDI %d", id+1);
        hdsp->midi[id].rmidi->private_data = &hdsp->midi[id];

        snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_OUTPUT, &snd_hdsp_midi_output);
        snd_rawmidi_set_ops (hdsp->midi[id].rmidi, SNDRV_RAWMIDI_STREAM_INPUT, &snd_hdsp_midi_input);

        hdsp->midi[id].rmidi->info_flags |= SNDRV_RAWMIDI_INFO_OUTPUT |
                SNDRV_RAWMIDI_INFO_INPUT |
                SNDRV_RAWMIDI_INFO_DUPLEX;

        return 0;
}

/*-----------------------------------------------------------------------------
  Control Interface
  ----------------------------------------------------------------------------*/

static u32 snd_hdsp_convert_from_aes(struct snd_aes_iec958 *aes)
{
        u32 val = 0;
        val |= (aes->status[0] & IEC958_AES0_PROFESSIONAL) ? HDSP_SPDIFProfessional : 0;
        val |= (aes->status[0] & IEC958_AES0_NONAUDIO) ? HDSP_SPDIFNonAudio : 0;
        if (val & HDSP_SPDIFProfessional)
                val |= (aes->status[0] & IEC958_AES0_PRO_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
        else
                val |= (aes->status[0] & IEC958_AES0_CON_EMPHASIS_5015) ? HDSP_SPDIFEmphasis : 0;
        return val;
}

static void snd_hdsp_convert_to_aes(struct snd_aes_iec958 *aes, u32 val)
{
        aes->status[0] = ((val & HDSP_SPDIFProfessional) ? IEC958_AES0_PROFESSIONAL : 0) |
                         ((val & HDSP_SPDIFNonAudio) ? IEC958_AES0_NONAUDIO : 0);
        if (val & HDSP_SPDIFProfessional)
                aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_PRO_EMPHASIS_5015 : 0;
        else
                aes->status[0] |= (val & HDSP_SPDIFEmphasis) ? IEC958_AES0_CON_EMPHASIS_5015 : 0;
}

static int snd_hdsp_control_spdif_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
        uinfo->count = 1;
        return 0;
}

static int snd_hdsp_control_spdif_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif);
        return 0;
}

static int snd_hdsp_control_spdif_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
        int change;
        u32 val;

        val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
        spin_lock_irq(&hdsp->lock);
        change = val != hdsp->creg_spdif;
        hdsp->creg_spdif = val;
        spin_unlock_irq(&hdsp->lock);
        return change;
}

static int snd_hdsp_control_spdif_stream_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
        uinfo->count = 1;
        return 0;
}

static int snd_hdsp_control_spdif_stream_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        snd_hdsp_convert_to_aes(&ucontrol->value.iec958, hdsp->creg_spdif_stream);
        return 0;
}

static int snd_hdsp_control_spdif_stream_put(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
        int change;
        u32 val;

        val = snd_hdsp_convert_from_aes(&ucontrol->value.iec958);
        spin_lock_irq(&hdsp->lock);
        change = val != hdsp->creg_spdif_stream;
        hdsp->creg_spdif_stream = val;
        hdsp->control_register &= ~(HDSP_SPDIFProfessional | HDSP_SPDIFNonAudio | HDSP_SPDIFEmphasis);
        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register |= val);
        spin_unlock_irq(&hdsp->lock);
        return change;
}

static int snd_hdsp_control_spdif_mask_info(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        uinfo->type = SNDRV_CTL_ELEM_TYPE_IEC958;
        uinfo->count = 1;
        return 0;
}

static int snd_hdsp_control_spdif_mask_get(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        ucontrol->value.iec958.status[0] = kcontrol->private_value;
        return 0;
}

#define HDSP_SPDIF_IN(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  .name = xname, \
  .index = xindex, \
  .info = snd_hdsp_info_spdif_in, \
  .get = snd_hdsp_get_spdif_in, \
  .put = snd_hdsp_put_spdif_in }

static unsigned int hdsp_spdif_in(struct hdsp *hdsp)
{
        return hdsp_decode_spdif_in(hdsp->control_register & HDSP_SPDIFInputMask);
}

static int hdsp_set_spdif_input(struct hdsp *hdsp, int in)
{
        hdsp->control_register &= ~HDSP_SPDIFInputMask;
        hdsp->control_register |= hdsp_encode_spdif_in(in);
        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
        return 0;
}

static int snd_hdsp_info_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        static const char * const texts[4] = {
                "Optical", "Coaxial", "Internal", "AES"
        };
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 4 : 3,
                                 texts);
}

static int snd_hdsp_get_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        ucontrol->value.enumerated.item[0] = hdsp_spdif_in(hdsp);
        return 0;
}

static int snd_hdsp_put_spdif_in(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
        int change;
        unsigned int val;

        if (!snd_hdsp_use_is_exclusive(hdsp))
                return -EBUSY;
        val = ucontrol->value.enumerated.item[0] % ((hdsp->io_type == H9632) ? 4 : 3);
        spin_lock_irq(&hdsp->lock);
        change = val != hdsp_spdif_in(hdsp);
        if (change)
                hdsp_set_spdif_input(hdsp, val);
        spin_unlock_irq(&hdsp->lock);
        return change;
}

#define HDSP_TOGGLE_SETTING(xname, xindex) \
{   .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
        .name = xname, \
        .private_value = xindex, \
        .info = snd_hdsp_info_toggle_setting, \
        .get = snd_hdsp_get_toggle_setting, \
        .put = snd_hdsp_put_toggle_setting \
}

static int hdsp_toggle_setting(struct hdsp *hdsp, u32 regmask)
{
        return (hdsp->control_register & regmask) ? 1 : 0;
}

static int hdsp_set_toggle_setting(struct hdsp *hdsp, u32 regmask, int out)
{
        if (out)
                hdsp->control_register |= regmask;
        else
                hdsp->control_register &= ~regmask;
        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);

        return 0;
}

#define snd_hdsp_info_toggle_setting               snd_ctl_boolean_mono_info

static int snd_hdsp_get_toggle_setting(struct snd_kcontrol *kcontrol,
                struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
        u32 regmask = kcontrol->private_value;

        spin_lock_irq(&hdsp->lock);
        ucontrol->value.integer.value[0] = hdsp_toggle_setting(hdsp, regmask);
        spin_unlock_irq(&hdsp->lock);
        return 0;
}

static int snd_hdsp_put_toggle_setting(struct snd_kcontrol *kcontrol,
                struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
        u32 regmask = kcontrol->private_value;
        int change;
        unsigned int val;

        if (!snd_hdsp_use_is_exclusive(hdsp))
                return -EBUSY;
        val = ucontrol->value.integer.value[0] & 1;
        spin_lock_irq(&hdsp->lock);
        change = (int) val != hdsp_toggle_setting(hdsp, regmask);
        if (change)
                hdsp_set_toggle_setting(hdsp, regmask, val);
        spin_unlock_irq(&hdsp->lock);
        return change;
}

#define HDSP_SPDIF_SAMPLE_RATE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  .name = xname, \
  .index = xindex, \
  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
  .info = snd_hdsp_info_spdif_sample_rate, \
  .get = snd_hdsp_get_spdif_sample_rate \
}

static int snd_hdsp_info_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        static const char * const texts[] = {
                "32000", "44100", "48000", "64000", "88200", "96000",
                "None", "128000", "176400", "192000"
        };
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
                                 texts);
}

static int snd_hdsp_get_spdif_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        switch (hdsp_spdif_sample_rate(hdsp)) {
        case 32000:
                ucontrol->value.enumerated.item[0] = 0;
                break;
        case 44100:
                ucontrol->value.enumerated.item[0] = 1;
                break;
        case 48000:
                ucontrol->value.enumerated.item[0] = 2;
                break;
        case 64000:
                ucontrol->value.enumerated.item[0] = 3;
                break;
        case 88200:
                ucontrol->value.enumerated.item[0] = 4;
                break;
        case 96000:
                ucontrol->value.enumerated.item[0] = 5;
                break;
        case 128000:
                ucontrol->value.enumerated.item[0] = 7;
                break;
        case 176400:
                ucontrol->value.enumerated.item[0] = 8;
                break;
        case 192000:
                ucontrol->value.enumerated.item[0] = 9;
                break;
        default:
                ucontrol->value.enumerated.item[0] = 6;
        }
        return 0;
}

#define HDSP_SYSTEM_SAMPLE_RATE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  .name = xname, \
  .index = xindex, \
  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
  .info = snd_hdsp_info_system_sample_rate, \
  .get = snd_hdsp_get_system_sample_rate \
}

static int snd_hdsp_info_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
        uinfo->count = 1;
        return 0;
}

static int snd_hdsp_get_system_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        ucontrol->value.enumerated.item[0] = hdsp->system_sample_rate;
        return 0;
}

#define HDSP_AUTOSYNC_SAMPLE_RATE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  .name = xname, \
  .index = xindex, \
  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
  .info = snd_hdsp_info_autosync_sample_rate, \
  .get = snd_hdsp_get_autosync_sample_rate \
}

static int snd_hdsp_info_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);
        static const char * const texts[] = {
                "32000", "44100", "48000", "64000", "88200", "96000",
                "None", "128000", "176400", "192000"
        };

        return snd_ctl_enum_info(uinfo, 1, (hdsp->io_type == H9632) ? 10 : 7,
                                 texts);
}

static int snd_hdsp_get_autosync_sample_rate(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        switch (hdsp_external_sample_rate(hdsp)) {
        case 32000:
                ucontrol->value.enumerated.item[0] = 0;
                break;
        case 44100:
                ucontrol->value.enumerated.item[0] = 1;
                break;
        case 48000:
                ucontrol->value.enumerated.item[0] = 2;
                break;
        case 64000:
                ucontrol->value.enumerated.item[0] = 3;
                break;
        case 88200:
                ucontrol->value.enumerated.item[0] = 4;
                break;
        case 96000:
                ucontrol->value.enumerated.item[0] = 5;
                break;
        case 128000:
                ucontrol->value.enumerated.item[0] = 7;
                break;
        case 176400:
                ucontrol->value.enumerated.item[0] = 8;
                break;
        case 192000:
                ucontrol->value.enumerated.item[0] = 9;
                break;
        default:
                ucontrol->value.enumerated.item[0] = 6;
        }
        return 0;
}

#define HDSP_SYSTEM_CLOCK_MODE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  .name = xname, \
  .index = xindex, \
  .access = SNDRV_CTL_ELEM_ACCESS_READ, \
  .info = snd_hdsp_info_system_clock_mode, \
  .get = snd_hdsp_get_system_clock_mode \
}

static int hdsp_system_clock_mode(struct hdsp *hdsp)
{
        if (hdsp->control_register & HDSP_ClockModeMaster)
                return 0;
        else if (hdsp_external_sample_rate(hdsp) != hdsp->system_sample_rate)
                        return 0;
        return 1;
}

static int snd_hdsp_info_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo)
{
        static const char * const texts[] = {"Master", "Slave" };

        return snd_ctl_enum_info(uinfo, 1, 2, texts);
}

static int snd_hdsp_get_system_clock_mode(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol)
{
        struct hdsp *hdsp = snd_kcontrol_chip(kcontrol);

        ucontrol->value.enumerated.item[0] = hdsp_system_clock_mode(hdsp);
        return 0;
}

#define HDSP_CLOCK_SOURCE(xname, xindex) \
{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
  .name = xname, \
  .index = xindex, \
  .info = snd_hdsp_info_clock_source, \
  .get = snd_hdsp_get_clock_source, \
  .put = snd_hdsp_put_clock_source \
}

static int hdsp_clock_source(struct hdsp *hdsp)
{
        if (hdsp->control_register & HDSP_ClockModeMaster) {
                switch (hdsp->system_sample_rate) {
                case 32000:
                        return 1;
                case 44100:
                        return 2;
                case 48000:
                        return 3;
                case 64000:
                        return 4;
                case 88200:
                        return 5;
                case 96000:
                        return 6;
                case 128000:
                        return 7;
                case 176400:
                        return 8;
                case 192000:
                        return 9;
                default:
                        return 3;
                }
        } else {
                return 0;
        }
}

static int hdsp_set_clock_source(struct hdsp *hdsp, int mode)
{
        int rate;
        switch (mode) {
        case HDSP_CLOCK_SOURCE_AUTOSYNC:
                if (hdsp_external_sample_rate(hdsp) != 0) {
                    if (!hdsp_set_rate(hdsp, hdsp_external_sample_rate(hdsp), 1)) {
                        hdsp->control_register &= ~HDSP_ClockModeMaster;
                        hdsp_write(hdsp, HDSP_controlRegister, hdsp->control_register);
                        return 0;
                    }
                }
                return -1;
        case HDSP_CLOCK_SOURCE_INTERNAL_32KHZ:
                rate = 32000;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_44_1KHZ:
                rate = 44100;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_48KHZ:
                rate = 48000;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_64KHZ:
                rate = 64000;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_88_2KHZ:
                rate = 88200;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_96KHZ:
                rate = 96000;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_128KHZ:
                rate = 128000;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_176_4KHZ:
                rate = 176400;
                break;
        case HDSP_CLOCK_SOURCE_INTERNAL_192KHZ: