linux/drivers/video/fbdev/s3c-fb.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/* linux/drivers/video/s3c-fb.c
   3 *
   4 * Copyright 2008 Openmoko Inc.
   5 * Copyright 2008-2010 Simtec Electronics
   6 *      Ben Dooks <ben@simtec.co.uk>
   7 *      http://armlinux.simtec.co.uk/
   8 *
   9 * Samsung SoC Framebuffer driver
  10*/
  11
  12#include <linux/kernel.h>
  13#include <linux/module.h>
  14#include <linux/platform_device.h>
  15#include <linux/dma-mapping.h>
  16#include <linux/slab.h>
  17#include <linux/init.h>
  18#include <linux/clk.h>
  19#include <linux/fb.h>
  20#include <linux/io.h>
  21#include <linux/uaccess.h>
  22#include <linux/interrupt.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/platform_data/video_s3c.h>
  25
  26#include <video/samsung_fimd.h>
  27
  28/* This driver will export a number of framebuffer interfaces depending
  29 * on the configuration passed in via the platform data. Each fb instance
  30 * maps to a hardware window. Currently there is no support for runtime
  31 * setting of the alpha-blending functions that each window has, so only
  32 * window 0 is actually useful.
  33 *
  34 * Window 0 is treated specially, it is used for the basis of the LCD
  35 * output timings and as the control for the output power-down state.
  36*/
  37
  38/* note, the previous use of <mach/regs-fb.h> to get platform specific data
  39 * has been replaced by using the platform device name to pick the correct
  40 * configuration data for the system.
  41*/
  42
  43#ifdef CONFIG_FB_S3C_DEBUG_REGWRITE
  44#undef writel
  45#define writel(v, r) do { \
  46        pr_debug("%s: %08x => %p\n", __func__, (unsigned int)v, r); \
  47        __raw_writel(v, r); \
  48} while (0)
  49#endif /* FB_S3C_DEBUG_REGWRITE */
  50
  51/* irq_flags bits */
  52#define S3C_FB_VSYNC_IRQ_EN     0
  53
  54#define VSYNC_TIMEOUT_MSEC 50
  55
  56struct s3c_fb;
  57
  58#define VALID_BPP(x) (1 << ((x) - 1))
  59
  60#define OSD_BASE(win, variant) ((variant).osd + ((win) * (variant).osd_stride))
  61#define VIDOSD_A(win, variant) (OSD_BASE(win, variant) + 0x00)
  62#define VIDOSD_B(win, variant) (OSD_BASE(win, variant) + 0x04)
  63#define VIDOSD_C(win, variant) (OSD_BASE(win, variant) + 0x08)
  64#define VIDOSD_D(win, variant) (OSD_BASE(win, variant) + 0x0C)
  65
  66/**
  67 * struct s3c_fb_variant - fb variant information
  68 * @is_2443: Set if S3C2443/S3C2416 style hardware.
  69 * @nr_windows: The number of windows.
  70 * @vidtcon: The base for the VIDTCONx registers
  71 * @wincon: The base for the WINxCON registers.
  72 * @winmap: The base for the WINxMAP registers.
  73 * @keycon: The abse for the WxKEYCON registers.
  74 * @buf_start: Offset of buffer start registers.
  75 * @buf_size: Offset of buffer size registers.
  76 * @buf_end: Offset of buffer end registers.
  77 * @osd: The base for the OSD registers.
  78 * @osd_stride: stride of osd
  79 * @palette: Address of palette memory, or 0 if none.
  80 * @has_prtcon: Set if has PRTCON register.
  81 * @has_shadowcon: Set if has SHADOWCON register.
  82 * @has_blendcon: Set if has BLENDCON register.
  83 * @has_clksel: Set if VIDCON0 register has CLKSEL bit.
  84 * @has_fixvclk: Set if VIDCON1 register has FIXVCLK bits.
  85 */
  86struct s3c_fb_variant {
  87        unsigned int    is_2443:1;
  88        unsigned short  nr_windows;
  89        unsigned int    vidtcon;
  90        unsigned short  wincon;
  91        unsigned short  winmap;
  92        unsigned short  keycon;
  93        unsigned short  buf_start;
  94        unsigned short  buf_end;
  95        unsigned short  buf_size;
  96        unsigned short  osd;
  97        unsigned short  osd_stride;
  98        unsigned short  palette[S3C_FB_MAX_WIN];
  99
 100        unsigned int    has_prtcon:1;
 101        unsigned int    has_shadowcon:1;
 102        unsigned int    has_blendcon:1;
 103        unsigned int    has_clksel:1;
 104        unsigned int    has_fixvclk:1;
 105};
 106
 107/**
 108 * struct s3c_fb_win_variant
 109 * @has_osd_c: Set if has OSD C register.
 110 * @has_osd_d: Set if has OSD D register.
 111 * @has_osd_alpha: Set if can change alpha transparency for a window.
 112 * @palette_sz: Size of palette in entries.
 113 * @palette_16bpp: Set if palette is 16bits wide.
 114 * @osd_size_off: If != 0, supports setting up OSD for a window; the appropriate
 115 *                register is located at the given offset from OSD_BASE.
 116 * @valid_bpp: 1 bit per BPP setting to show valid bits-per-pixel.
 117 *
 118 * valid_bpp bit x is set if (x+1)BPP is supported.
 119 */
 120struct s3c_fb_win_variant {
 121        unsigned int    has_osd_c:1;
 122        unsigned int    has_osd_d:1;
 123        unsigned int    has_osd_alpha:1;
 124        unsigned int    palette_16bpp:1;
 125        unsigned short  osd_size_off;
 126        unsigned short  palette_sz;
 127        u32             valid_bpp;
 128};
 129
 130/**
 131 * struct s3c_fb_driverdata - per-device type driver data for init time.
 132 * @variant: The variant information for this driver.
 133 * @win: The window information for each window.
 134 */
 135struct s3c_fb_driverdata {
 136        struct s3c_fb_variant   variant;
 137        struct s3c_fb_win_variant *win[S3C_FB_MAX_WIN];
 138};
 139
 140/**
 141 * struct s3c_fb_palette - palette information
 142 * @r: Red bitfield.
 143 * @g: Green bitfield.
 144 * @b: Blue bitfield.
 145 * @a: Alpha bitfield.
 146 */
 147struct s3c_fb_palette {
 148        struct fb_bitfield      r;
 149        struct fb_bitfield      g;
 150        struct fb_bitfield      b;
 151        struct fb_bitfield      a;
 152};
 153
 154/**
 155 * struct s3c_fb_win - per window private data for each framebuffer.
 156 * @windata: The platform data supplied for the window configuration.
 157 * @parent: The hardware that this window is part of.
 158 * @fbinfo: Pointer pack to the framebuffer info for this window.
 159 * @variant: The variant information for this window.
 160 * @palette_buffer: Buffer/cache to hold palette entries.
 161 * @pseudo_palette: For use in TRUECOLOUR modes for entries 0..15/
 162 * @index: The window number of this window.
 163 * @palette: The bitfields for changing r/g/b into a hardware palette entry.
 164 */
 165struct s3c_fb_win {
 166        struct s3c_fb_pd_win    *windata;
 167        struct s3c_fb           *parent;
 168        struct fb_info          *fbinfo;
 169        struct s3c_fb_palette    palette;
 170        struct s3c_fb_win_variant variant;
 171
 172        u32                     *palette_buffer;
 173        u32                      pseudo_palette[16];
 174        unsigned int             index;
 175};
 176
 177/**
 178 * struct s3c_fb_vsync - vsync information
 179 * @wait:       a queue for processes waiting for vsync
 180 * @count:      vsync interrupt count
 181 */
 182struct s3c_fb_vsync {
 183        wait_queue_head_t       wait;
 184        unsigned int            count;
 185};
 186
 187/**
 188 * struct s3c_fb - overall hardware state of the hardware
 189 * @slock: The spinlock protection for this data structure.
 190 * @dev: The device that we bound to, for printing, etc.
 191 * @bus_clk: The clk (hclk) feeding our interface and possibly pixclk.
 192 * @lcd_clk: The clk (sclk) feeding pixclk.
 193 * @regs: The mapped hardware registers.
 194 * @variant: Variant information for this hardware.
 195 * @enabled: A bitmask of enabled hardware windows.
 196 * @output_on: Flag if the physical output is enabled.
 197 * @pdata: The platform configuration data passed with the device.
 198 * @windows: The hardware windows that have been claimed.
 199 * @irq_no: IRQ line number
 200 * @irq_flags: irq flags
 201 * @vsync_info: VSYNC-related information (count, queues...)
 202 */
 203struct s3c_fb {
 204        spinlock_t              slock;
 205        struct device           *dev;
 206        struct clk              *bus_clk;
 207        struct clk              *lcd_clk;
 208        void __iomem            *regs;
 209        struct s3c_fb_variant    variant;
 210
 211        unsigned char            enabled;
 212        bool                     output_on;
 213
 214        struct s3c_fb_platdata  *pdata;
 215        struct s3c_fb_win       *windows[S3C_FB_MAX_WIN];
 216
 217        int                      irq_no;
 218        unsigned long            irq_flags;
 219        struct s3c_fb_vsync      vsync_info;
 220};
 221
 222/**
 223 * s3c_fb_validate_win_bpp - validate the bits-per-pixel for this mode.
 224 * @win: The device window.
 225 * @bpp: The bit depth.
 226 */
 227static bool s3c_fb_validate_win_bpp(struct s3c_fb_win *win, unsigned int bpp)
 228{
 229        return win->variant.valid_bpp & VALID_BPP(bpp);
 230}
 231
 232/**
 233 * s3c_fb_check_var() - framebuffer layer request to verify a given mode.
 234 * @var: The screen information to verify.
 235 * @info: The framebuffer device.
 236 *
 237 * Framebuffer layer call to verify the given information and allow us to
 238 * update various information depending on the hardware capabilities.
 239 */
 240static int s3c_fb_check_var(struct fb_var_screeninfo *var,
 241                            struct fb_info *info)
 242{
 243        struct s3c_fb_win *win = info->par;
 244        struct s3c_fb *sfb = win->parent;
 245
 246        dev_dbg(sfb->dev, "checking parameters\n");
 247
 248        var->xres_virtual = max(var->xres_virtual, var->xres);
 249        var->yres_virtual = max(var->yres_virtual, var->yres);
 250
 251        if (!s3c_fb_validate_win_bpp(win, var->bits_per_pixel)) {
 252                dev_dbg(sfb->dev, "win %d: unsupported bpp %d\n",
 253                        win->index, var->bits_per_pixel);
 254                return -EINVAL;
 255        }
 256
 257        /* always ensure these are zero, for drop through cases below */
 258        var->transp.offset = 0;
 259        var->transp.length = 0;
 260
 261        switch (var->bits_per_pixel) {
 262        case 1:
 263        case 2:
 264        case 4:
 265        case 8:
 266                if (sfb->variant.palette[win->index] != 0) {
 267                        /* non palletised, A:1,R:2,G:3,B:2 mode */
 268                        var->red.offset         = 5;
 269                        var->green.offset       = 2;
 270                        var->blue.offset        = 0;
 271                        var->red.length         = 2;
 272                        var->green.length       = 3;
 273                        var->blue.length        = 2;
 274                        var->transp.offset      = 7;
 275                        var->transp.length      = 1;
 276                } else {
 277                        var->red.offset = 0;
 278                        var->red.length = var->bits_per_pixel;
 279                        var->green      = var->red;
 280                        var->blue       = var->red;
 281                }
 282                break;
 283
 284        case 19:
 285                /* 666 with one bit alpha/transparency */
 286                var->transp.offset      = 18;
 287                var->transp.length      = 1;
 288                fallthrough;
 289        case 18:
 290                var->bits_per_pixel     = 32;
 291
 292                /* 666 format */
 293                var->red.offset         = 12;
 294                var->green.offset       = 6;
 295                var->blue.offset        = 0;
 296                var->red.length         = 6;
 297                var->green.length       = 6;
 298                var->blue.length        = 6;
 299                break;
 300
 301        case 16:
 302                /* 16 bpp, 565 format */
 303                var->red.offset         = 11;
 304                var->green.offset       = 5;
 305                var->blue.offset        = 0;
 306                var->red.length         = 5;
 307                var->green.length       = 6;
 308                var->blue.length        = 5;
 309                break;
 310
 311        case 32:
 312        case 28:
 313        case 25:
 314                var->transp.length      = var->bits_per_pixel - 24;
 315                var->transp.offset      = 24;
 316                fallthrough;
 317        case 24:
 318                /* our 24bpp is unpacked, so 32bpp */
 319                var->bits_per_pixel     = 32;
 320                var->red.offset         = 16;
 321                var->red.length         = 8;
 322                var->green.offset       = 8;
 323                var->green.length       = 8;
 324                var->blue.offset        = 0;
 325                var->blue.length        = 8;
 326                break;
 327
 328        default:
 329                dev_err(sfb->dev, "invalid bpp\n");
 330                return -EINVAL;
 331        }
 332
 333        dev_dbg(sfb->dev, "%s: verified parameters\n", __func__);
 334        return 0;
 335}
 336
 337/**
 338 * s3c_fb_calc_pixclk() - calculate the divider to create the pixel clock.
 339 * @sfb: The hardware state.
 340 * @pixclk: The pixel clock wanted, in picoseconds.
 341 *
 342 * Given the specified pixel clock, work out the necessary divider to get
 343 * close to the output frequency.
 344 */
 345static int s3c_fb_calc_pixclk(struct s3c_fb *sfb, unsigned int pixclk)
 346{
 347        unsigned long clk;
 348        unsigned long long tmp;
 349        unsigned int result;
 350
 351        if (sfb->variant.has_clksel)
 352                clk = clk_get_rate(sfb->bus_clk);
 353        else
 354                clk = clk_get_rate(sfb->lcd_clk);
 355
 356        tmp = (unsigned long long)clk;
 357        tmp *= pixclk;
 358
 359        do_div(tmp, 1000000000UL);
 360        result = (unsigned int)tmp / 1000;
 361
 362        dev_dbg(sfb->dev, "pixclk=%u, clk=%lu, div=%d (%lu)\n",
 363                pixclk, clk, result, result ? clk / result : clk);
 364
 365        return result;
 366}
 367
 368/**
 369 * s3c_fb_align_word() - align pixel count to word boundary
 370 * @bpp: The number of bits per pixel
 371 * @pix: The value to be aligned.
 372 *
 373 * Align the given pixel count so that it will start on an 32bit word
 374 * boundary.
 375 */
 376static int s3c_fb_align_word(unsigned int bpp, unsigned int pix)
 377{
 378        int pix_per_word;
 379
 380        if (bpp > 16)
 381                return pix;
 382
 383        pix_per_word = (8 * 32) / bpp;
 384        return ALIGN(pix, pix_per_word);
 385}
 386
 387/**
 388 * vidosd_set_size() - set OSD size for a window
 389 *
 390 * @win: the window to set OSD size for
 391 * @size: OSD size register value
 392 */
 393static void vidosd_set_size(struct s3c_fb_win *win, u32 size)
 394{
 395        struct s3c_fb *sfb = win->parent;
 396
 397        /* OSD can be set up if osd_size_off != 0 for this window */
 398        if (win->variant.osd_size_off)
 399                writel(size, sfb->regs + OSD_BASE(win->index, sfb->variant)
 400                                + win->variant.osd_size_off);
 401}
 402
 403/**
 404 * vidosd_set_alpha() - set alpha transparency for a window
 405 *
 406 * @win: the window to set OSD size for
 407 * @alpha: alpha register value
 408 */
 409static void vidosd_set_alpha(struct s3c_fb_win *win, u32 alpha)
 410{
 411        struct s3c_fb *sfb = win->parent;
 412
 413        if (win->variant.has_osd_alpha)
 414                writel(alpha, sfb->regs + VIDOSD_C(win->index, sfb->variant));
 415}
 416
 417/**
 418 * shadow_protect_win() - disable updating values from shadow registers at vsync
 419 *
 420 * @win: window to protect registers for
 421 * @protect: 1 to protect (disable updates)
 422 */
 423static void shadow_protect_win(struct s3c_fb_win *win, bool protect)
 424{
 425        struct s3c_fb *sfb = win->parent;
 426        u32 reg;
 427
 428        if (protect) {
 429                if (sfb->variant.has_prtcon) {
 430                        writel(PRTCON_PROTECT, sfb->regs + PRTCON);
 431                } else if (sfb->variant.has_shadowcon) {
 432                        reg = readl(sfb->regs + SHADOWCON);
 433                        writel(reg | SHADOWCON_WINx_PROTECT(win->index),
 434                                sfb->regs + SHADOWCON);
 435                }
 436        } else {
 437                if (sfb->variant.has_prtcon) {
 438                        writel(0, sfb->regs + PRTCON);
 439                } else if (sfb->variant.has_shadowcon) {
 440                        reg = readl(sfb->regs + SHADOWCON);
 441                        writel(reg & ~SHADOWCON_WINx_PROTECT(win->index),
 442                                sfb->regs + SHADOWCON);
 443                }
 444        }
 445}
 446
 447/**
 448 * s3c_fb_enable() - Set the state of the main LCD output
 449 * @sfb: The main framebuffer state.
 450 * @enable: The state to set.
 451 */
 452static void s3c_fb_enable(struct s3c_fb *sfb, int enable)
 453{
 454        u32 vidcon0 = readl(sfb->regs + VIDCON0);
 455
 456        if (enable && !sfb->output_on)
 457                pm_runtime_get_sync(sfb->dev);
 458
 459        if (enable) {
 460                vidcon0 |= VIDCON0_ENVID | VIDCON0_ENVID_F;
 461        } else {
 462                /* see the note in the framebuffer datasheet about
 463                 * why you cannot take both of these bits down at the
 464                 * same time. */
 465
 466                if (vidcon0 & VIDCON0_ENVID) {
 467                        vidcon0 |= VIDCON0_ENVID;
 468                        vidcon0 &= ~VIDCON0_ENVID_F;
 469                }
 470        }
 471
 472        writel(vidcon0, sfb->regs + VIDCON0);
 473
 474        if (!enable && sfb->output_on)
 475                pm_runtime_put_sync(sfb->dev);
 476
 477        sfb->output_on = enable;
 478}
 479
 480/**
 481 * s3c_fb_set_par() - framebuffer request to set new framebuffer state.
 482 * @info: The framebuffer to change.
 483 *
 484 * Framebuffer layer request to set a new mode for the specified framebuffer
 485 */
 486static int s3c_fb_set_par(struct fb_info *info)
 487{
 488        struct fb_var_screeninfo *var = &info->var;
 489        struct s3c_fb_win *win = info->par;
 490        struct s3c_fb *sfb = win->parent;
 491        void __iomem *regs = sfb->regs;
 492        void __iomem *buf = regs;
 493        int win_no = win->index;
 494        u32 alpha = 0;
 495        u32 data;
 496        u32 pagewidth;
 497
 498        dev_dbg(sfb->dev, "setting framebuffer parameters\n");
 499
 500        pm_runtime_get_sync(sfb->dev);
 501
 502        shadow_protect_win(win, 1);
 503
 504        switch (var->bits_per_pixel) {
 505        case 32:
 506        case 24:
 507        case 16:
 508        case 12:
 509                info->fix.visual = FB_VISUAL_TRUECOLOR;
 510                break;
 511        case 8:
 512                if (win->variant.palette_sz >= 256)
 513                        info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 514                else
 515                        info->fix.visual = FB_VISUAL_TRUECOLOR;
 516                break;
 517        case 1:
 518                info->fix.visual = FB_VISUAL_MONO01;
 519                break;
 520        default:
 521                info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 522                break;
 523        }
 524
 525        info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 526
 527        info->fix.xpanstep = info->var.xres_virtual > info->var.xres ? 1 : 0;
 528        info->fix.ypanstep = info->var.yres_virtual > info->var.yres ? 1 : 0;
 529
 530        /* disable the window whilst we update it */
 531        writel(0, regs + WINCON(win_no));
 532
 533        if (!sfb->output_on)
 534                s3c_fb_enable(sfb, 1);
 535
 536        /* write the buffer address */
 537
 538        /* start and end registers stride is 8 */
 539        buf = regs + win_no * 8;
 540
 541        writel(info->fix.smem_start, buf + sfb->variant.buf_start);
 542
 543        data = info->fix.smem_start + info->fix.line_length * var->yres;
 544        writel(data, buf + sfb->variant.buf_end);
 545
 546        pagewidth = (var->xres * var->bits_per_pixel) >> 3;
 547        data = VIDW_BUF_SIZE_OFFSET(info->fix.line_length - pagewidth) |
 548               VIDW_BUF_SIZE_PAGEWIDTH(pagewidth) |
 549               VIDW_BUF_SIZE_OFFSET_E(info->fix.line_length - pagewidth) |
 550               VIDW_BUF_SIZE_PAGEWIDTH_E(pagewidth);
 551        writel(data, regs + sfb->variant.buf_size + (win_no * 4));
 552
 553        /* write 'OSD' registers to control position of framebuffer */
 554
 555        data = VIDOSDxA_TOPLEFT_X(0) | VIDOSDxA_TOPLEFT_Y(0) |
 556               VIDOSDxA_TOPLEFT_X_E(0) | VIDOSDxA_TOPLEFT_Y_E(0);
 557        writel(data, regs + VIDOSD_A(win_no, sfb->variant));
 558
 559        data = VIDOSDxB_BOTRIGHT_X(s3c_fb_align_word(var->bits_per_pixel,
 560                                                     var->xres - 1)) |
 561               VIDOSDxB_BOTRIGHT_Y(var->yres - 1) |
 562               VIDOSDxB_BOTRIGHT_X_E(s3c_fb_align_word(var->bits_per_pixel,
 563                                                     var->xres - 1)) |
 564               VIDOSDxB_BOTRIGHT_Y_E(var->yres - 1);
 565
 566        writel(data, regs + VIDOSD_B(win_no, sfb->variant));
 567
 568        data = var->xres * var->yres;
 569
 570        alpha = VIDISD14C_ALPHA1_R(0xf) |
 571                VIDISD14C_ALPHA1_G(0xf) |
 572                VIDISD14C_ALPHA1_B(0xf);
 573
 574        vidosd_set_alpha(win, alpha);
 575        vidosd_set_size(win, data);
 576
 577        /* Enable DMA channel for this window */
 578        if (sfb->variant.has_shadowcon) {
 579                data = readl(sfb->regs + SHADOWCON);
 580                data |= SHADOWCON_CHx_ENABLE(win_no);
 581                writel(data, sfb->regs + SHADOWCON);
 582        }
 583
 584        data = WINCONx_ENWIN;
 585        sfb->enabled |= (1 << win->index);
 586
 587        /* note, since we have to round up the bits-per-pixel, we end up
 588         * relying on the bitfield information for r/g/b/a to work out
 589         * exactly which mode of operation is intended. */
 590
 591        switch (var->bits_per_pixel) {
 592        case 1:
 593                data |= WINCON0_BPPMODE_1BPP;
 594                data |= WINCONx_BITSWP;
 595                data |= WINCONx_BURSTLEN_4WORD;
 596                break;
 597        case 2:
 598                data |= WINCON0_BPPMODE_2BPP;
 599                data |= WINCONx_BITSWP;
 600                data |= WINCONx_BURSTLEN_8WORD;
 601                break;
 602        case 4:
 603                data |= WINCON0_BPPMODE_4BPP;
 604                data |= WINCONx_BITSWP;
 605                data |= WINCONx_BURSTLEN_8WORD;
 606                break;
 607        case 8:
 608                if (var->transp.length != 0)
 609                        data |= WINCON1_BPPMODE_8BPP_1232;
 610                else
 611                        data |= WINCON0_BPPMODE_8BPP_PALETTE;
 612                data |= WINCONx_BURSTLEN_8WORD;
 613                data |= WINCONx_BYTSWP;
 614                break;
 615        case 16:
 616                if (var->transp.length != 0)
 617                        data |= WINCON1_BPPMODE_16BPP_A1555;
 618                else
 619                        data |= WINCON0_BPPMODE_16BPP_565;
 620                data |= WINCONx_HAWSWP;
 621                data |= WINCONx_BURSTLEN_16WORD;
 622                break;
 623        case 24:
 624        case 32:
 625                if (var->red.length == 6) {
 626                        if (var->transp.length != 0)
 627                                data |= WINCON1_BPPMODE_19BPP_A1666;
 628                        else
 629                                data |= WINCON1_BPPMODE_18BPP_666;
 630                } else if (var->transp.length == 1)
 631                        data |= WINCON1_BPPMODE_25BPP_A1888
 632                                | WINCON1_BLD_PIX;
 633                else if ((var->transp.length == 4) ||
 634                        (var->transp.length == 8))
 635                        data |= WINCON1_BPPMODE_28BPP_A4888
 636                                | WINCON1_BLD_PIX | WINCON1_ALPHA_SEL;
 637                else
 638                        data |= WINCON0_BPPMODE_24BPP_888;
 639
 640                data |= WINCONx_WSWP;
 641                data |= WINCONx_BURSTLEN_16WORD;
 642                break;
 643        }
 644
 645        /* Enable the colour keying for the window below this one */
 646        if (win_no > 0) {
 647                u32 keycon0_data = 0, keycon1_data = 0;
 648                void __iomem *keycon = regs + sfb->variant.keycon;
 649
 650                keycon0_data = ~(WxKEYCON0_KEYBL_EN |
 651                                WxKEYCON0_KEYEN_F |
 652                                WxKEYCON0_DIRCON) | WxKEYCON0_COMPKEY(0);
 653
 654                keycon1_data = WxKEYCON1_COLVAL(0xffffff);
 655
 656                keycon += (win_no - 1) * 8;
 657
 658                writel(keycon0_data, keycon + WKEYCON0);
 659                writel(keycon1_data, keycon + WKEYCON1);
 660        }
 661
 662        writel(data, regs + sfb->variant.wincon + (win_no * 4));
 663        writel(0x0, regs + sfb->variant.winmap + (win_no * 4));
 664
 665        /* Set alpha value width */
 666        if (sfb->variant.has_blendcon) {
 667                data = readl(sfb->regs + BLENDCON);
 668                data &= ~BLENDCON_NEW_MASK;
 669                if (var->transp.length > 4)
 670                        data |= BLENDCON_NEW_8BIT_ALPHA_VALUE;
 671                else
 672                        data |= BLENDCON_NEW_4BIT_ALPHA_VALUE;
 673                writel(data, sfb->regs + BLENDCON);
 674        }
 675
 676        shadow_protect_win(win, 0);
 677
 678        pm_runtime_put_sync(sfb->dev);
 679
 680        return 0;
 681}
 682
 683/**
 684 * s3c_fb_update_palette() - set or schedule a palette update.
 685 * @sfb: The hardware information.
 686 * @win: The window being updated.
 687 * @reg: The palette index being changed.
 688 * @value: The computed palette value.
 689 *
 690 * Change the value of a palette register, either by directly writing to
 691 * the palette (this requires the palette RAM to be disconnected from the
 692 * hardware whilst this is in progress) or schedule the update for later.
 693 *
 694 * At the moment, since we have no VSYNC interrupt support, we simply set
 695 * the palette entry directly.
 696 */
 697static void s3c_fb_update_palette(struct s3c_fb *sfb,
 698                                  struct s3c_fb_win *win,
 699                                  unsigned int reg,
 700                                  u32 value)
 701{
 702        void __iomem *palreg;
 703        u32 palcon;
 704
 705        palreg = sfb->regs + sfb->variant.palette[win->index];
 706
 707        dev_dbg(sfb->dev, "%s: win %d, reg %d (%p): %08x\n",
 708                __func__, win->index, reg, palreg, value);
 709
 710        win->palette_buffer[reg] = value;
 711
 712        palcon = readl(sfb->regs + WPALCON);
 713        writel(palcon | WPALCON_PAL_UPDATE, sfb->regs + WPALCON);
 714
 715        if (win->variant.palette_16bpp)
 716                writew(value, palreg + (reg * 2));
 717        else
 718                writel(value, palreg + (reg * 4));
 719
 720        writel(palcon, sfb->regs + WPALCON);
 721}
 722
 723static inline unsigned int chan_to_field(unsigned int chan,
 724                                         struct fb_bitfield *bf)
 725{
 726        chan &= 0xffff;
 727        chan >>= 16 - bf->length;
 728        return chan << bf->offset;
 729}
 730
 731/**
 732 * s3c_fb_setcolreg() - framebuffer layer request to change palette.
 733 * @regno: The palette index to change.
 734 * @red: The red field for the palette data.
 735 * @green: The green field for the palette data.
 736 * @blue: The blue field for the palette data.
 737 * @transp: The transparency (alpha) field for the palette data.
 738 * @info: The framebuffer being changed.
 739 */
 740static int s3c_fb_setcolreg(unsigned regno,
 741                            unsigned red, unsigned green, unsigned blue,
 742                            unsigned transp, struct fb_info *info)
 743{
 744        struct s3c_fb_win *win = info->par;
 745        struct s3c_fb *sfb = win->parent;
 746        unsigned int val;
 747
 748        dev_dbg(sfb->dev, "%s: win %d: %d => rgb=%d/%d/%d\n",
 749                __func__, win->index, regno, red, green, blue);
 750
 751        pm_runtime_get_sync(sfb->dev);
 752
 753        switch (info->fix.visual) {
 754        case FB_VISUAL_TRUECOLOR:
 755                /* true-colour, use pseudo-palette */
 756
 757                if (regno < 16) {
 758                        u32 *pal = info->pseudo_palette;
 759
 760                        val  = chan_to_field(red,   &info->var.red);
 761                        val |= chan_to_field(green, &info->var.green);
 762                        val |= chan_to_field(blue,  &info->var.blue);
 763
 764                        pal[regno] = val;
 765                }
 766                break;
 767
 768        case FB_VISUAL_PSEUDOCOLOR:
 769                if (regno < win->variant.palette_sz) {
 770                        val  = chan_to_field(red, &win->palette.r);
 771                        val |= chan_to_field(green, &win->palette.g);
 772                        val |= chan_to_field(blue, &win->palette.b);
 773
 774                        s3c_fb_update_palette(sfb, win, regno, val);
 775                }
 776
 777                break;
 778
 779        default:
 780                pm_runtime_put_sync(sfb->dev);
 781                return 1;       /* unknown type */
 782        }
 783
 784        pm_runtime_put_sync(sfb->dev);
 785        return 0;
 786}
 787
 788/**
 789 * s3c_fb_blank() - blank or unblank the given window
 790 * @blank_mode: The blank state from FB_BLANK_*
 791 * @info: The framebuffer to blank.
 792 *
 793 * Framebuffer layer request to change the power state.
 794 */
 795static int s3c_fb_blank(int blank_mode, struct fb_info *info)
 796{
 797        struct s3c_fb_win *win = info->par;
 798        struct s3c_fb *sfb = win->parent;
 799        unsigned int index = win->index;
 800        u32 wincon;
 801        u32 output_on = sfb->output_on;
 802
 803        dev_dbg(sfb->dev, "blank mode %d\n", blank_mode);
 804
 805        pm_runtime_get_sync(sfb->dev);
 806
 807        wincon = readl(sfb->regs + sfb->variant.wincon + (index * 4));
 808
 809        switch (blank_mode) {
 810        case FB_BLANK_POWERDOWN:
 811                wincon &= ~WINCONx_ENWIN;
 812                sfb->enabled &= ~(1 << index);
 813                fallthrough;    /* to FB_BLANK_NORMAL */
 814
 815        case FB_BLANK_NORMAL:
 816                /* disable the DMA and display 0x0 (black) */
 817                shadow_protect_win(win, 1);
 818                writel(WINxMAP_MAP | WINxMAP_MAP_COLOUR(0x0),
 819                       sfb->regs + sfb->variant.winmap + (index * 4));
 820                shadow_protect_win(win, 0);
 821                break;
 822
 823        case FB_BLANK_UNBLANK:
 824                shadow_protect_win(win, 1);
 825                writel(0x0, sfb->regs + sfb->variant.winmap + (index * 4));
 826                shadow_protect_win(win, 0);
 827                wincon |= WINCONx_ENWIN;
 828                sfb->enabled |= (1 << index);
 829                break;
 830
 831        case FB_BLANK_VSYNC_SUSPEND:
 832        case FB_BLANK_HSYNC_SUSPEND:
 833        default:
 834                pm_runtime_put_sync(sfb->dev);
 835                return 1;
 836        }
 837
 838        shadow_protect_win(win, 1);
 839        writel(wincon, sfb->regs + sfb->variant.wincon + (index * 4));
 840
 841        /* Check the enabled state to see if we need to be running the
 842         * main LCD interface, as if there are no active windows then
 843         * it is highly likely that we also do not need to output
 844         * anything.
 845         */
 846        s3c_fb_enable(sfb, sfb->enabled ? 1 : 0);
 847        shadow_protect_win(win, 0);
 848
 849        pm_runtime_put_sync(sfb->dev);
 850
 851        return output_on == sfb->output_on;
 852}
 853
 854/**
 855 * s3c_fb_pan_display() - Pan the display.
 856 *
 857 * Note that the offsets can be written to the device at any time, as their
 858 * values are latched at each vsync automatically. This also means that only
 859 * the last call to this function will have any effect on next vsync, but
 860 * there is no need to sleep waiting for it to prevent tearing.
 861 *
 862 * @var: The screen information to verify.
 863 * @info: The framebuffer device.
 864 */
 865static int s3c_fb_pan_display(struct fb_var_screeninfo *var,
 866                              struct fb_info *info)
 867{
 868        struct s3c_fb_win *win  = info->par;
 869        struct s3c_fb *sfb      = win->parent;
 870        void __iomem *buf       = sfb->regs + win->index * 8;
 871        unsigned int start_boff, end_boff;
 872
 873        pm_runtime_get_sync(sfb->dev);
 874
 875        /* Offset in bytes to the start of the displayed area */
 876        start_boff = var->yoffset * info->fix.line_length;
 877        /* X offset depends on the current bpp */
 878        if (info->var.bits_per_pixel >= 8) {
 879                start_boff += var->xoffset * (info->var.bits_per_pixel >> 3);
 880        } else {
 881                switch (info->var.bits_per_pixel) {
 882                case 4:
 883                        start_boff += var->xoffset >> 1;
 884                        break;
 885                case 2:
 886                        start_boff += var->xoffset >> 2;
 887                        break;
 888                case 1:
 889                        start_boff += var->xoffset >> 3;
 890                        break;
 891                default:
 892                        dev_err(sfb->dev, "invalid bpp\n");
 893                        pm_runtime_put_sync(sfb->dev);
 894                        return -EINVAL;
 895                }
 896        }
 897        /* Offset in bytes to the end of the displayed area */
 898        end_boff = start_boff + info->var.yres * info->fix.line_length;
 899
 900        /* Temporarily turn off per-vsync update from shadow registers until
 901         * both start and end addresses are updated to prevent corruption */
 902        shadow_protect_win(win, 1);
 903
 904        writel(info->fix.smem_start + start_boff, buf + sfb->variant.buf_start);
 905        writel(info->fix.smem_start + end_boff, buf + sfb->variant.buf_end);
 906
 907        shadow_protect_win(win, 0);
 908
 909        pm_runtime_put_sync(sfb->dev);
 910        return 0;
 911}
 912
 913/**
 914 * s3c_fb_enable_irq() - enable framebuffer interrupts
 915 * @sfb: main hardware state
 916 */
 917static void s3c_fb_enable_irq(struct s3c_fb *sfb)
 918{
 919        void __iomem *regs = sfb->regs;
 920        u32 irq_ctrl_reg;
 921
 922        if (!test_and_set_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
 923                /* IRQ disabled, enable it */
 924                irq_ctrl_reg = readl(regs + VIDINTCON0);
 925
 926                irq_ctrl_reg |= VIDINTCON0_INT_ENABLE;
 927                irq_ctrl_reg |= VIDINTCON0_INT_FRAME;
 928
 929                irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL0_MASK;
 930                irq_ctrl_reg |= VIDINTCON0_FRAMESEL0_VSYNC;
 931                irq_ctrl_reg &= ~VIDINTCON0_FRAMESEL1_MASK;
 932                irq_ctrl_reg |= VIDINTCON0_FRAMESEL1_NONE;
 933
 934                writel(irq_ctrl_reg, regs + VIDINTCON0);
 935        }
 936}
 937
 938/**
 939 * s3c_fb_disable_irq() - disable framebuffer interrupts
 940 * @sfb: main hardware state
 941 */
 942static void s3c_fb_disable_irq(struct s3c_fb *sfb)
 943{
 944        void __iomem *regs = sfb->regs;
 945        u32 irq_ctrl_reg;
 946
 947        if (test_and_clear_bit(S3C_FB_VSYNC_IRQ_EN, &sfb->irq_flags)) {
 948                /* IRQ enabled, disable it */
 949                irq_ctrl_reg = readl(regs + VIDINTCON0);
 950
 951                irq_ctrl_reg &= ~VIDINTCON0_INT_FRAME;
 952                irq_ctrl_reg &= ~VIDINTCON0_INT_ENABLE;
 953
 954                writel(irq_ctrl_reg, regs + VIDINTCON0);
 955        }
 956}
 957
 958static irqreturn_t s3c_fb_irq(int irq, void *dev_id)
 959{
 960        struct s3c_fb *sfb = dev_id;
 961        void __iomem  *regs = sfb->regs;
 962        u32 irq_sts_reg;
 963
 964        spin_lock(&sfb->slock);
 965
 966        irq_sts_reg = readl(regs + VIDINTCON1);
 967
 968        if (irq_sts_reg & VIDINTCON1_INT_FRAME) {
 969
 970                /* VSYNC interrupt, accept it */
 971                writel(VIDINTCON1_INT_FRAME, regs + VIDINTCON1);
 972
 973                sfb->vsync_info.count++;
 974                wake_up_interruptible(&sfb->vsync_info.wait);
 975        }
 976
 977        /* We only support waiting for VSYNC for now, so it's safe
 978         * to always disable irqs here.
 979         */
 980        s3c_fb_disable_irq(sfb);
 981
 982        spin_unlock(&sfb->slock);
 983        return IRQ_HANDLED;
 984}
 985
 986/**
 987 * s3c_fb_wait_for_vsync() - sleep until next VSYNC interrupt or timeout
 988 * @sfb: main hardware state
 989 * @crtc: head index.
 990 */
 991static int s3c_fb_wait_for_vsync(struct s3c_fb *sfb, u32 crtc)
 992{
 993        unsigned long count;
 994        int ret;
 995
 996        if (crtc != 0)
 997                return -ENODEV;
 998
 999        pm_runtime_get_sync(sfb->dev);
1000
1001        count = sfb->vsync_info.count;
1002        s3c_fb_enable_irq(sfb);
1003        ret = wait_event_interruptible_timeout(sfb->vsync_info.wait,
1004                                       count != sfb->vsync_info.count,
1005                                       msecs_to_jiffies(VSYNC_TIMEOUT_MSEC));
1006
1007        pm_runtime_put_sync(sfb->dev);
1008
1009        if (ret == 0)
1010                return -ETIMEDOUT;
1011
1012        return 0;
1013}
1014
1015static int s3c_fb_ioctl(struct fb_info *info, unsigned int cmd,
1016                        unsigned long arg)
1017{
1018        struct s3c_fb_win *win = info->par;
1019        struct s3c_fb *sfb = win->parent;
1020        int ret;
1021        u32 crtc;
1022
1023        switch (cmd) {
1024        case FBIO_WAITFORVSYNC:
1025                if (get_user(crtc, (u32 __user *)arg)) {
1026                        ret = -EFAULT;
1027                        break;
1028                }
1029
1030                ret = s3c_fb_wait_for_vsync(sfb, crtc);
1031                break;
1032        default:
1033                ret = -ENOTTY;
1034        }
1035
1036        return ret;
1037}
1038
1039static const struct fb_ops s3c_fb_ops = {
1040        .owner          = THIS_MODULE,
1041        .fb_check_var   = s3c_fb_check_var,
1042        .fb_set_par     = s3c_fb_set_par,
1043        .fb_blank       = s3c_fb_blank,
1044        .fb_setcolreg   = s3c_fb_setcolreg,
1045        .fb_fillrect    = cfb_fillrect,
1046        .fb_copyarea    = cfb_copyarea,
1047        .fb_imageblit   = cfb_imageblit,
1048        .fb_pan_display = s3c_fb_pan_display,
1049        .fb_ioctl       = s3c_fb_ioctl,
1050};
1051
1052/**
1053 * s3c_fb_missing_pixclock() - calculates pixel clock
1054 * @mode: The video mode to change.
1055 *
1056 * Calculate the pixel clock when none has been given through platform data.
1057 */
1058static void s3c_fb_missing_pixclock(struct fb_videomode *mode)
1059{
1060        u64 pixclk = 1000000000000ULL;
1061        u32 div;
1062
1063        div  = mode->left_margin + mode->hsync_len + mode->right_margin +
1064               mode->xres;
1065        div *= mode->upper_margin + mode->vsync_len + mode->lower_margin +
1066               mode->yres;
1067        div *= mode->refresh ? : 60;
1068
1069        do_div(pixclk, div);
1070
1071        mode->pixclock = pixclk;
1072}
1073
1074/**
1075 * s3c_fb_alloc_memory() - allocate display memory for framebuffer window
1076 * @sfb: The base resources for the hardware.
1077 * @win: The window to initialise memory for.
1078 *
1079 * Allocate memory for the given framebuffer.
1080 */
1081static int s3c_fb_alloc_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1082{
1083        struct s3c_fb_pd_win *windata = win->windata;
1084        unsigned int real_size, virt_size, size;
1085        struct fb_info *fbi = win->fbinfo;
1086        dma_addr_t map_dma;
1087
1088        dev_dbg(sfb->dev, "allocating memory for display\n");
1089
1090        real_size = windata->xres * windata->yres;
1091        virt_size = windata->virtual_x * windata->virtual_y;
1092
1093        dev_dbg(sfb->dev, "real_size=%u (%u.%u), virt_size=%u (%u.%u)\n",
1094                real_size, windata->xres, windata->yres,
1095                virt_size, windata->virtual_x, windata->virtual_y);
1096
1097        size = (real_size > virt_size) ? real_size : virt_size;
1098        size *= (windata->max_bpp > 16) ? 32 : windata->max_bpp;
1099        size /= 8;
1100
1101        fbi->fix.smem_len = size;
1102        size = PAGE_ALIGN(size);
1103
1104        dev_dbg(sfb->dev, "want %u bytes for window\n", size);
1105
1106        fbi->screen_buffer = dma_alloc_wc(sfb->dev, size, &map_dma, GFP_KERNEL);
1107        if (!fbi->screen_buffer)
1108                return -ENOMEM;
1109
1110        dev_dbg(sfb->dev, "mapped %x to %p\n",
1111                (unsigned int)map_dma, fbi->screen_buffer);
1112
1113        memset(fbi->screen_buffer, 0x0, size);
1114        fbi->fix.smem_start = map_dma;
1115
1116        return 0;
1117}
1118
1119/**
1120 * s3c_fb_free_memory() - free the display memory for the given window
1121 * @sfb: The base resources for the hardware.
1122 * @win: The window to free the display memory for.
1123 *
1124 * Free the display memory allocated by s3c_fb_alloc_memory().
1125 */
1126static void s3c_fb_free_memory(struct s3c_fb *sfb, struct s3c_fb_win *win)
1127{
1128        struct fb_info *fbi = win->fbinfo;
1129
1130        if (fbi->screen_buffer)
1131                dma_free_wc(sfb->dev, PAGE_ALIGN(fbi->fix.smem_len),
1132                            fbi->screen_buffer, fbi->fix.smem_start);
1133}
1134
1135/**
1136 * s3c_fb_release_win() - release resources for a framebuffer window.
1137 * @sfb: The base resources for the hardware.
1138 * @win: The window to cleanup the resources for.
1139 *
1140 * Release the resources that where claimed for the hardware window,
1141 * such as the framebuffer instance and any memory claimed for it.
1142 */
1143static void s3c_fb_release_win(struct s3c_fb *sfb, struct s3c_fb_win *win)
1144{
1145        u32 data;
1146
1147        if (win->fbinfo) {
1148                if (sfb->variant.has_shadowcon) {
1149                        data = readl(sfb->regs + SHADOWCON);
1150                        data &= ~SHADOWCON_CHx_ENABLE(win->index);
1151                        data &= ~SHADOWCON_CHx_LOCAL_ENABLE(win->index);
1152                        writel(data, sfb->regs + SHADOWCON);
1153                }
1154                unregister_framebuffer(win->fbinfo);
1155                if (win->fbinfo->cmap.len)
1156                        fb_dealloc_cmap(&win->fbinfo->cmap);
1157                s3c_fb_free_memory(sfb, win);
1158                framebuffer_release(win->fbinfo);
1159        }
1160}
1161
1162/**
1163 * s3c_fb_probe_win() - register an hardware window
1164 * @sfb: The base resources for the hardware
1165 * @win_no: The window number
1166 * @variant: The variant information for this window.
1167 * @res: Pointer to where to place the resultant window.
1168 *
1169 * Allocate and do the basic initialisation for one of the hardware's graphics
1170 * windows.
1171 */
1172static int s3c_fb_probe_win(struct s3c_fb *sfb, unsigned int win_no,
1173                            struct s3c_fb_win_variant *variant,
1174                            struct s3c_fb_win **res)
1175{
1176        struct fb_videomode initmode;
1177        struct s3c_fb_pd_win *windata;
1178        struct s3c_fb_win *win;
1179        struct fb_info *fbinfo;
1180        int palette_size;
1181        int ret;
1182
1183        dev_dbg(sfb->dev, "probing window %d, variant %p\n", win_no, variant);
1184
1185        init_waitqueue_head(&sfb->vsync_info.wait);
1186
1187        palette_size = variant->palette_sz * 4;
1188
1189        fbinfo = framebuffer_alloc(sizeof(struct s3c_fb_win) +
1190                                   palette_size * sizeof(u32), sfb->dev);
1191        if (!fbinfo)
1192                return -ENOMEM;
1193
1194        windata = sfb->pdata->win[win_no];
1195        initmode = *sfb->pdata->vtiming;
1196
1197        WARN_ON(windata->max_bpp == 0);
1198        WARN_ON(windata->xres == 0);
1199        WARN_ON(windata->yres == 0);
1200
1201        win = fbinfo->par;
1202        *res = win;
1203        win->variant = *variant;
1204        win->fbinfo = fbinfo;
1205        win->parent = sfb;
1206        win->windata = windata;
1207        win->index = win_no;
1208        win->palette_buffer = (u32 *)(win + 1);
1209
1210        ret = s3c_fb_alloc_memory(sfb, win);
1211        if (ret) {
1212                dev_err(sfb->dev, "failed to allocate display memory\n");
1213                return ret;
1214        }
1215
1216        /* setup the r/b/g positions for the window's palette */
1217        if (win->variant.palette_16bpp) {
1218                /* Set RGB 5:6:5 as default */
1219                win->palette.r.offset = 11;
1220                win->palette.r.length = 5;
1221                win->palette.g.offset = 5;
1222                win->palette.g.length = 6;
1223                win->palette.b.offset = 0;
1224                win->palette.b.length = 5;
1225
1226        } else {
1227                /* Set 8bpp or 8bpp and 1bit alpha */
1228                win->palette.r.offset = 16;
1229                win->palette.r.length = 8;
1230                win->palette.g.offset = 8;
1231                win->palette.g.length = 8;
1232                win->palette.b.offset = 0;
1233                win->palette.b.length = 8;
1234        }
1235
1236        /* setup the initial video mode from the window */
1237        initmode.xres = windata->xres;
1238        initmode.yres = windata->yres;
1239        fb_videomode_to_var(&fbinfo->var, &initmode);
1240
1241        fbinfo->fix.type        = FB_TYPE_PACKED_PIXELS;
1242        fbinfo->fix.accel       = FB_ACCEL_NONE;
1243        fbinfo->var.activate    = FB_ACTIVATE_NOW;
1244        fbinfo->var.vmode       = FB_VMODE_NONINTERLACED;
1245        fbinfo->var.bits_per_pixel = windata->default_bpp;
1246        fbinfo->fbops           = &s3c_fb_ops;
1247        fbinfo->flags           = FBINFO_FLAG_DEFAULT;
1248        fbinfo->pseudo_palette  = &win->pseudo_palette;
1249
1250        /* prepare to actually start the framebuffer */
1251
1252        ret = s3c_fb_check_var(&fbinfo->var, fbinfo);
1253        if (ret < 0) {
1254                dev_err(sfb->dev, "check_var failed on initial video params\n");
1255                return ret;
1256        }
1257
1258        /* create initial colour map */
1259
1260        ret = fb_alloc_cmap(&fbinfo->cmap, win->variant.palette_sz, 1);
1261        if (ret == 0)
1262                fb_set_cmap(&fbinfo->cmap, fbinfo);
1263        else
1264                dev_err(sfb->dev, "failed to allocate fb cmap\n");
1265
1266        s3c_fb_set_par(fbinfo);
1267
1268        dev_dbg(sfb->dev, "about to register framebuffer\n");
1269
1270        /* run the check_var and set_par on our configuration. */
1271
1272        ret = register_framebuffer(fbinfo);
1273        if (ret < 0) {
1274                dev_err(sfb->dev, "failed to register framebuffer\n");
1275                return ret;
1276        }
1277
1278        dev_info(sfb->dev, "window %d: fb %s\n", win_no, fbinfo->fix.id);
1279
1280        return 0;
1281}
1282
1283/**
1284 * s3c_fb_set_rgb_timing() - set video timing for rgb interface.
1285 * @sfb: The base resources for the hardware.
1286 *
1287 * Set horizontal and vertical lcd rgb interface timing.
1288 */
1289static void s3c_fb_set_rgb_timing(struct s3c_fb *sfb)
1290{
1291        struct fb_videomode *vmode = sfb->pdata->vtiming;
1292        void __iomem *regs = sfb->regs;
1293        int clkdiv;
1294        u32 data;
1295
1296        if (!vmode->pixclock)
1297                s3c_fb_missing_pixclock(vmode);
1298
1299        clkdiv = s3c_fb_calc_pixclk(sfb, vmode->pixclock);
1300
1301        data = sfb->pdata->vidcon0;
1302        data &= ~(VIDCON0_CLKVAL_F_MASK | VIDCON0_CLKDIR);
1303
1304        if (clkdiv > 1)
1305                data |= VIDCON0_CLKVAL_F(clkdiv-1) | VIDCON0_CLKDIR;
1306        else
1307                data &= ~VIDCON0_CLKDIR;        /* 1:1 clock */
1308
1309        if (sfb->variant.is_2443)
1310                data |= (1 << 5);
1311        writel(data, regs + VIDCON0);
1312
1313        data = VIDTCON0_VBPD(vmode->upper_margin - 1) |
1314               VIDTCON0_VFPD(vmode->lower_margin - 1) |
1315               VIDTCON0_VSPW(vmode->vsync_len - 1);
1316        writel(data, regs + sfb->variant.vidtcon);
1317
1318        data = VIDTCON1_HBPD(vmode->left_margin - 1) |
1319               VIDTCON1_HFPD(vmode->right_margin - 1) |
1320               VIDTCON1_HSPW(vmode->hsync_len - 1);
1321        writel(data, regs + sfb->variant.vidtcon + 4);
1322
1323        data = VIDTCON2_LINEVAL(vmode->yres - 1) |
1324               VIDTCON2_HOZVAL(vmode->xres - 1) |
1325               VIDTCON2_LINEVAL_E(vmode->yres - 1) |
1326               VIDTCON2_HOZVAL_E(vmode->xres - 1);
1327        writel(data, regs + sfb->variant.vidtcon + 8);
1328}
1329
1330/**
1331 * s3c_fb_clear_win() - clear hardware window registers.
1332 * @sfb: The base resources for the hardware.
1333 * @win: The window to process.
1334 *
1335 * Reset the specific window registers to a known state.
1336 */
1337static void s3c_fb_clear_win(struct s3c_fb *sfb, int win)
1338{
1339        void __iomem *regs = sfb->regs;
1340        u32 reg;
1341
1342        writel(0, regs + sfb->variant.wincon + (win * 4));
1343        writel(0, regs + VIDOSD_A(win, sfb->variant));
1344        writel(0, regs + VIDOSD_B(win, sfb->variant));
1345        writel(0, regs + VIDOSD_C(win, sfb->variant));
1346
1347        if (sfb->variant.has_shadowcon) {
1348                reg = readl(sfb->regs + SHADOWCON);
1349                reg &= ~(SHADOWCON_WINx_PROTECT(win) |
1350                        SHADOWCON_CHx_ENABLE(win) |
1351                        SHADOWCON_CHx_LOCAL_ENABLE(win));
1352                writel(reg, sfb->regs + SHADOWCON);
1353        }
1354}
1355
1356static int s3c_fb_probe(struct platform_device *pdev)
1357{
1358        const struct platform_device_id *platid;
1359        struct s3c_fb_driverdata *fbdrv;
1360        struct device *dev = &pdev->dev;
1361        struct s3c_fb_platdata *pd;
1362        struct s3c_fb *sfb;
1363        struct resource *res;
1364        int win;
1365        int ret = 0;
1366        u32 reg;
1367
1368        platid = platform_get_device_id(pdev);
1369        fbdrv = (struct s3c_fb_driverdata *)platid->driver_data;
1370
1371        if (fbdrv->variant.nr_windows > S3C_FB_MAX_WIN) {
1372                dev_err(dev, "too many windows, cannot attach\n");
1373                return -EINVAL;
1374        }
1375
1376        pd = dev_get_platdata(&pdev->dev);
1377        if (!pd) {
1378                dev_err(dev, "no platform data specified\n");
1379                return -EINVAL;
1380        }
1381
1382        sfb = devm_kzalloc(dev, sizeof(*sfb), GFP_KERNEL);
1383        if (!sfb)
1384                return -ENOMEM;
1385
1386        dev_dbg(dev, "allocate new framebuffer %p\n", sfb);
1387
1388        sfb->dev = dev;
1389        sfb->pdata = pd;
1390        sfb->variant = fbdrv->variant;
1391
1392        spin_lock_init(&sfb->slock);
1393
1394        sfb->bus_clk = devm_clk_get(dev, "lcd");
1395        if (IS_ERR(sfb->bus_clk)) {
1396                dev_err(dev, "failed to get bus clock\n");
1397                return PTR_ERR(sfb->bus_clk);
1398        }
1399
1400        clk_prepare_enable(sfb->bus_clk);
1401
1402        if (!sfb->variant.has_clksel) {
1403                sfb->lcd_clk = devm_clk_get(dev, "sclk_fimd");
1404                if (IS_ERR(sfb->lcd_clk)) {
1405                        dev_err(dev, "failed to get lcd clock\n");
1406                        ret = PTR_ERR(sfb->lcd_clk);
1407                        goto err_bus_clk;
1408                }
1409
1410                clk_prepare_enable(sfb->lcd_clk);
1411        }
1412
1413        pm_runtime_enable(sfb->dev);
1414
1415        sfb->regs = devm_platform_ioremap_resource(pdev, 0);
1416        if (IS_ERR(sfb->regs)) {
1417                ret = PTR_ERR(sfb->regs);
1418                goto err_lcd_clk;
1419        }
1420
1421        res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1422        if (!res) {
1423                dev_err(dev, "failed to acquire irq resource\n");
1424                ret = -ENOENT;
1425                goto err_lcd_clk;
1426        }
1427        sfb->irq_no = res->start;
1428        ret = devm_request_irq(dev, sfb->irq_no, s3c_fb_irq,
1429                          0, "s3c_fb", sfb);
1430        if (ret) {
1431                dev_err(dev, "irq request failed\n");
1432                goto err_lcd_clk;
1433        }
1434
1435        dev_dbg(dev, "got resources (regs %p), probing windows\n", sfb->regs);
1436
1437        platform_set_drvdata(pdev, sfb);
1438        pm_runtime_get_sync(sfb->dev);
1439
1440        /* setup gpio and output polarity controls */
1441
1442        pd->setup_gpio();
1443
1444        writel(pd->vidcon1, sfb->regs + VIDCON1);
1445
1446        /* set video clock running at under-run */
1447        if (sfb->variant.has_fixvclk) {
1448                reg = readl(sfb->regs + VIDCON1);
1449                reg &= ~VIDCON1_VCLK_MASK;
1450                reg |= VIDCON1_VCLK_RUN;
1451                writel(reg, sfb->regs + VIDCON1);
1452        }
1453
1454        /* zero all windows before we do anything */
1455
1456        for (win = 0; win < fbdrv->variant.nr_windows; win++)
1457                s3c_fb_clear_win(sfb, win);
1458
1459        /* initialise colour key controls */
1460        for (win = 0; win < (fbdrv->variant.nr_windows - 1); win++) {
1461                void __iomem *regs = sfb->regs + sfb->variant.keycon;
1462
1463                regs += (win * 8);
1464                writel(0xffffff, regs + WKEYCON0);
1465                writel(0xffffff, regs + WKEYCON1);
1466        }
1467
1468        s3c_fb_set_rgb_timing(sfb);
1469
1470        /* we have the register setup, start allocating framebuffers */
1471
1472        for (win = 0; win < fbdrv->variant.nr_windows; win++) {
1473                if (!pd->win[win])
1474                        continue;
1475
1476                ret = s3c_fb_probe_win(sfb, win, fbdrv->win[win],
1477                                       &sfb->windows[win]);
1478                if (ret < 0) {
1479                        dev_err(dev, "failed to create window %d\n", win);
1480                        for (; win >= 0; win--)
1481                                s3c_fb_release_win(sfb, sfb->windows[win]);
1482                        goto err_pm_runtime;
1483                }
1484        }
1485
1486        platform_set_drvdata(pdev, sfb);
1487        pm_runtime_put_sync(sfb->dev);
1488
1489        return 0;
1490
1491err_pm_runtime:
1492        pm_runtime_put_sync(sfb->dev);
1493
1494err_lcd_clk:
1495        pm_runtime_disable(sfb->dev);
1496
1497        if (!sfb->variant.has_clksel)
1498                clk_disable_unprepare(sfb->lcd_clk);
1499
1500err_bus_clk:
1501        clk_disable_unprepare(sfb->bus_clk);
1502
1503        return ret;
1504}
1505
1506/**
1507 * s3c_fb_remove() - Cleanup on module finalisation
1508 * @pdev: The platform device we are bound to.
1509 *
1510 * Shutdown and then release all the resources that the driver allocated
1511 * on initialisation.
1512 */
1513static int s3c_fb_remove(struct platform_device *pdev)
1514{
1515        struct s3c_fb *sfb = platform_get_drvdata(pdev);
1516        int win;
1517
1518        pm_runtime_get_sync(sfb->dev);
1519
1520        for (win = 0; win < S3C_FB_MAX_WIN; win++)
1521                if (sfb->windows[win])
1522                        s3c_fb_release_win(sfb, sfb->windows[win]);
1523
1524        if (!sfb->variant.has_clksel)
1525                clk_disable_unprepare(sfb->lcd_clk);
1526
1527        clk_disable_unprepare(sfb->bus_clk);
1528
1529        pm_runtime_put_sync(sfb->dev);
1530        pm_runtime_disable(sfb->dev);
1531
1532        return 0;
1533}
1534
1535#ifdef CONFIG_PM_SLEEP
1536static int s3c_fb_suspend(struct device *dev)
1537{
1538        struct s3c_fb *sfb = dev_get_drvdata(dev);
1539        struct s3c_fb_win *win;
1540        int win_no;
1541
1542        pm_runtime_get_sync(sfb->dev);
1543
1544        for (win_no = S3C_FB_MAX_WIN - 1; win_no >= 0; win_no--) {
1545                win = sfb->windows[win_no];
1546                if (!win)
1547                        continue;
1548
1549                /* use the blank function to push into power-down */
1550                s3c_fb_blank(FB_BLANK_POWERDOWN, win->fbinfo);
1551        }
1552
1553        if (!sfb->variant.has_clksel)
1554                clk_disable_unprepare(sfb->lcd_clk);
1555
1556        clk_disable_unprepare(sfb->bus_clk);
1557
1558        pm_runtime_put_sync(sfb->dev);
1559
1560        return 0;
1561}
1562
1563static int s3c_fb_resume(struct device *dev)
1564{
1565        struct s3c_fb *sfb = dev_get_drvdata(dev);
1566        struct s3c_fb_platdata *pd = sfb->pdata;
1567        struct s3c_fb_win *win;
1568        int win_no;
1569        u32 reg;
1570
1571        pm_runtime_get_sync(sfb->dev);
1572
1573        clk_prepare_enable(sfb->bus_clk);
1574
1575        if (!sfb->variant.has_clksel)
1576                clk_prepare_enable(sfb->lcd_clk);
1577
1578        /* setup gpio and output polarity controls */
1579        pd->setup_gpio();
1580        writel(pd->vidcon1, sfb->regs + VIDCON1);
1581
1582        /* set video clock running at under-run */
1583        if (sfb->variant.has_fixvclk) {
1584                reg = readl(sfb->regs + VIDCON1);
1585                reg &= ~VIDCON1_VCLK_MASK;
1586                reg |= VIDCON1_VCLK_RUN;
1587                writel(reg, sfb->regs + VIDCON1);
1588        }
1589
1590        /* zero all windows before we do anything */
1591        for (win_no = 0; win_no < sfb->variant.nr_windows; win_no++)
1592                s3c_fb_clear_win(sfb, win_no);
1593
1594        for (win_no = 0; win_no < sfb->variant.nr_windows - 1; win_no++) {
1595                void __iomem *regs = sfb->regs + sfb->variant.keycon;
1596                win = sfb->windows[win_no];
1597                if (!win)
1598                        continue;
1599
1600                shadow_protect_win(win, 1);
1601                regs += (win_no * 8);
1602                writel(0xffffff, regs + WKEYCON0);
1603                writel(0xffffff, regs + WKEYCON1);
1604                shadow_protect_win(win, 0);
1605        }
1606
1607        s3c_fb_set_rgb_timing(sfb);
1608
1609        /* restore framebuffers */
1610        for (win_no = 0; win_no < S3C_FB_MAX_WIN; win_no++) {
1611                win = sfb->windows[win_no];
1612                if (!win)
1613                        continue;
1614
1615                dev_dbg(dev, "resuming window %d\n", win_no);
1616                s3c_fb_set_par(win->fbinfo);
1617        }
1618
1619        pm_runtime_put_sync(sfb->dev);
1620
1621        return 0;
1622}
1623#endif
1624
1625#ifdef CONFIG_PM
1626static int s3c_fb_runtime_suspend(struct device *dev)
1627{
1628        struct s3c_fb *sfb = dev_get_drvdata(dev);
1629
1630        if (!sfb->variant.has_clksel)
1631                clk_disable_unprepare(sfb->lcd_clk);
1632
1633        clk_disable_unprepare(sfb->bus_clk);
1634
1635        return 0;
1636}
1637
1638static int s3c_fb_runtime_resume(struct device *dev)
1639{
1640        struct s3c_fb *sfb = dev_get_drvdata(dev);
1641        struct s3c_fb_platdata *pd = sfb->pdata;
1642
1643        clk_prepare_enable(sfb->bus_clk);
1644
1645        if (!sfb->variant.has_clksel)
1646                clk_prepare_enable(sfb->lcd_clk);
1647
1648        /* setup gpio and output polarity controls */
1649        pd->setup_gpio();
1650        writel(pd->vidcon1, sfb->regs + VIDCON1);
1651
1652        return 0;
1653}
1654#endif
1655
1656#define VALID_BPP124 (VALID_BPP(1) | VALID_BPP(2) | VALID_BPP(4))
1657#define VALID_BPP1248 (VALID_BPP124 | VALID_BPP(8))
1658
1659static struct s3c_fb_win_variant s3c_fb_data_64xx_wins[] = {
1660        [0] = {
1661                .has_osd_c      = 1,
1662                .osd_size_off   = 0x8,
1663                .palette_sz     = 256,
1664                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1665                                   VALID_BPP(18) | VALID_BPP(24)),
1666        },
1667        [1] = {
1668                .has_osd_c      = 1,
1669                .has_osd_d      = 1,
1670                .osd_size_off   = 0xc,
1671                .has_osd_alpha  = 1,
1672                .palette_sz     = 256,
1673                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1674                                   VALID_BPP(18) | VALID_BPP(19) |
1675                                   VALID_BPP(24) | VALID_BPP(25) |
1676                                   VALID_BPP(28)),
1677        },
1678        [2] = {
1679                .has_osd_c      = 1,
1680                .has_osd_d      = 1,
1681                .osd_size_off   = 0xc,
1682                .has_osd_alpha  = 1,
1683                .palette_sz     = 16,
1684                .palette_16bpp  = 1,
1685                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1686                                   VALID_BPP(18) | VALID_BPP(19) |
1687                                   VALID_BPP(24) | VALID_BPP(25) |
1688                                   VALID_BPP(28)),
1689        },
1690        [3] = {
1691                .has_osd_c      = 1,
1692                .has_osd_alpha  = 1,
1693                .palette_sz     = 16,
1694                .palette_16bpp  = 1,
1695                .valid_bpp      = (VALID_BPP124  | VALID_BPP(16) |
1696                                   VALID_BPP(18) | VALID_BPP(19) |
1697                                   VALID_BPP(24) | VALID_BPP(25) |
1698                                   VALID_BPP(28)),
1699        },
1700        [4] = {
1701                .has_osd_c      = 1,
1702                .has_osd_alpha  = 1,
1703                .palette_sz     = 4,
1704                .palette_16bpp  = 1,
1705                .valid_bpp      = (VALID_BPP(1) | VALID_BPP(2) |
1706                                   VALID_BPP(16) | VALID_BPP(18) |
1707                                   VALID_BPP(19) | VALID_BPP(24) |
1708                                   VALID_BPP(25) | VALID_BPP(28)),
1709        },
1710};
1711
1712static struct s3c_fb_driverdata s3c_fb_data_64xx = {
1713        .variant = {
1714                .nr_windows     = 5,
1715                .vidtcon        = VIDTCON0,
1716                .wincon         = WINCON(0),
1717                .winmap         = WINxMAP(0),
1718                .keycon         = WKEYCON,
1719                .osd            = VIDOSD_BASE,
1720                .osd_stride     = 16,
1721                .buf_start      = VIDW_BUF_START(0),
1722                .buf_size       = VIDW_BUF_SIZE(0),
1723                .buf_end        = VIDW_BUF_END(0),
1724
1725                .palette = {
1726                        [0] = 0x400,
1727                        [1] = 0x800,
1728                        [2] = 0x300,
1729                        [3] = 0x320,
1730                        [4] = 0x340,
1731                },
1732
1733                .has_prtcon     = 1,
1734                .has_clksel     = 1,
1735        },
1736        .win[0] = &s3c_fb_data_64xx_wins[0],
1737        .win[1] = &s3c_fb_data_64xx_wins[1],
1738        .win[2] = &s3c_fb_data_64xx_wins[2],
1739        .win[3] = &s3c_fb_data_64xx_wins[3],
1740        .win[4] = &s3c_fb_data_64xx_wins[4],
1741};
1742
1743/* S3C2443/S3C2416 style hardware */
1744static struct s3c_fb_driverdata s3c_fb_data_s3c2443 = {
1745        .variant = {
1746                .nr_windows     = 2,
1747                .is_2443        = 1,
1748
1749                .vidtcon        = 0x08,
1750                .wincon         = 0x14,
1751                .winmap         = 0xd0,
1752                .keycon         = 0xb0,
1753                .osd            = 0x28,
1754                .osd_stride     = 12,
1755                .buf_start      = 0x64,
1756                .buf_size       = 0x94,
1757                .buf_end        = 0x7c,
1758
1759                .palette = {
1760                        [0] = 0x400,
1761                        [1] = 0x800,
1762                },
1763                .has_clksel     = 1,
1764        },
1765        .win[0] = &(struct s3c_fb_win_variant) {
1766                .palette_sz     = 256,
1767                .valid_bpp      = VALID_BPP1248 | VALID_BPP(16) | VALID_BPP(24),
1768        },
1769        .win[1] = &(struct s3c_fb_win_variant) {
1770                .has_osd_c      = 1,
1771                .has_osd_alpha  = 1,
1772                .palette_sz     = 256,
1773                .valid_bpp      = (VALID_BPP1248 | VALID_BPP(16) |
1774                                   VALID_BPP(18) | VALID_BPP(19) |
1775                                   VALID_BPP(24) | VALID_BPP(25) |
1776                                   VALID_BPP(28)),
1777        },
1778};
1779
1780static const struct platform_device_id s3c_fb_driver_ids[] = {
1781        {
1782                .name           = "s3c-fb",
1783                .driver_data    = (unsigned long)&s3c_fb_data_64xx,
1784        }, {
1785                .name           = "s3c2443-fb",
1786                .driver_data    = (unsigned long)&s3c_fb_data_s3c2443,
1787        },
1788        {},
1789};
1790MODULE_DEVICE_TABLE(platform, s3c_fb_driver_ids);
1791
1792static const struct dev_pm_ops s3cfb_pm_ops = {
1793        SET_SYSTEM_SLEEP_PM_OPS(s3c_fb_suspend, s3c_fb_resume)
1794        SET_RUNTIME_PM_OPS(s3c_fb_runtime_suspend, s3c_fb_runtime_resume,
1795                           NULL)
1796};
1797
1798static struct platform_driver s3c_fb_driver = {
1799        .probe          = s3c_fb_probe,
1800        .remove         = s3c_fb_remove,
1801        .id_table       = s3c_fb_driver_ids,
1802        .driver         = {
1803                .name   = "s3c-fb",
1804                .pm     = &s3cfb_pm_ops,
1805        },
1806};
1807
1808module_platform_driver(s3c_fb_driver);
1809
1810MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>");
1811MODULE_DESCRIPTION("Samsung S3C SoC Framebuffer driver");
1812MODULE_LICENSE("GPL");
1813MODULE_ALIAS("platform:s3c-fb");
1814