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12#ifndef __LINUX_XHCI_HCD_H
13#define __LINUX_XHCI_HCD_H
14
15#include <linux/usb.h>
16#include <linux/timer.h>
17#include <linux/kernel.h>
18#include <linux/usb/hcd.h>
19#include <linux/io-64-nonatomic-lo-hi.h>
20
21
22#include "xhci-ext-caps.h"
23#include "pci-quirks.h"
24
25
26#define XHCI_SBRN_OFFSET (0x60)
27
28
29#define MAX_HC_SLOTS 256
30
31#define MAX_HC_PORTS 127
32
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49
50struct xhci_cap_regs {
51 __le32 hc_capbase;
52 __le32 hcs_params1;
53 __le32 hcs_params2;
54 __le32 hcs_params3;
55 __le32 hcc_params;
56 __le32 db_off;
57 __le32 run_regs_off;
58 __le32 hcc_params2;
59
60};
61
62
63
64#define HC_LENGTH(p) XHCI_HC_LENGTH(p)
65
66#define HC_VERSION(p) (((p) >> 16) & 0xffff)
67
68
69
70#define HCS_MAX_SLOTS(p) (((p) >> 0) & 0xff)
71#define HCS_SLOTS_MASK 0xff
72
73#define HCS_MAX_INTRS(p) (((p) >> 8) & 0x7ff)
74
75#define HCS_MAX_PORTS(p) (((p) >> 24) & 0x7f)
76
77
78
79
80#define HCS_IST(p) (((p) >> 0) & 0xf)
81
82#define HCS_ERST_MAX(p) (((p) >> 4) & 0xf)
83
84
85
86#define HCS_MAX_SCRATCHPAD(p) ((((p) >> 16) & 0x3e0) | (((p) >> 27) & 0x1f))
87
88
89
90#define HCS_U1_LATENCY(p) (((p) >> 0) & 0xff)
91
92#define HCS_U2_LATENCY(p) (((p) >> 16) & 0xffff)
93
94
95
96#define HCC_64BIT_ADDR(p) ((p) & (1 << 0))
97
98#define HCC_BANDWIDTH_NEG(p) ((p) & (1 << 1))
99
100
101
102#define HCC_64BYTE_CONTEXT(p) ((p) & (1 << 2))
103
104#define HCC_PPC(p) ((p) & (1 << 3))
105
106#define HCS_INDICATOR(p) ((p) & (1 << 4))
107
108#define HCC_LIGHT_RESET(p) ((p) & (1 << 5))
109
110#define HCC_LTC(p) ((p) & (1 << 6))
111
112#define HCC_NSS(p) ((p) & (1 << 7))
113
114#define HCC_SPC(p) ((p) & (1 << 9))
115
116#define HCC_CFC(p) ((p) & (1 << 11))
117
118#define HCC_MAX_PSA(p) (1 << ((((p) >> 12) & 0xf) + 1))
119
120#define HCC_EXT_CAPS(p) XHCI_HCC_EXT_CAPS(p)
121
122#define CTX_SIZE(_hcc) (HCC_64BYTE_CONTEXT(_hcc) ? 64 : 32)
123
124
125#define DBOFF_MASK (~0x3)
126
127
128#define RTSOFF_MASK (~0x1f)
129
130
131
132#define HCC2_U3C(p) ((p) & (1 << 0))
133
134#define HCC2_CMC(p) ((p) & (1 << 1))
135
136#define HCC2_FSC(p) ((p) & (1 << 2))
137
138#define HCC2_CTC(p) ((p) & (1 << 3))
139
140#define HCC2_LEC(p) ((p) & (1 << 4))
141
142#define HCC2_CIC(p) ((p) & (1 << 5))
143
144#define HCC2_ETC(p) ((p) & (1 << 6))
145
146
147#define NUM_PORT_REGS 4
148
149#define PORTSC 0
150#define PORTPMSC 1
151#define PORTLI 2
152#define PORTHLPMC 3
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176struct xhci_op_regs {
177 __le32 command;
178 __le32 status;
179 __le32 page_size;
180 __le32 reserved1;
181 __le32 reserved2;
182 __le32 dev_notification;
183 __le64 cmd_ring;
184
185 __le32 reserved3[4];
186 __le64 dcbaa_ptr;
187 __le32 config_reg;
188
189 __le32 reserved4[241];
190
191 __le32 port_status_base;
192 __le32 port_power_base;
193 __le32 port_link_base;
194 __le32 reserved5;
195
196 __le32 reserved6[NUM_PORT_REGS*254];
197};
198
199
200
201#define CMD_RUN XHCI_CMD_RUN
202
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204
205
206#define CMD_RESET (1 << 1)
207
208#define CMD_EIE XHCI_CMD_EIE
209
210#define CMD_HSEIE XHCI_CMD_HSEIE
211
212
213#define CMD_LRESET (1 << 7)
214
215#define CMD_CSS (1 << 8)
216#define CMD_CRS (1 << 9)
217
218#define CMD_EWE XHCI_CMD_EWE
219
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222
223
224#define CMD_PM_INDEX (1 << 11)
225
226#define CMD_ETE (1 << 14)
227
228
229
230#define IMAN_IE (1 << 1)
231#define IMAN_IP (1 << 0)
232
233
234
235#define STS_HALT XHCI_STS_HALT
236
237#define STS_FATAL (1 << 2)
238
239#define STS_EINT (1 << 3)
240
241#define STS_PORT (1 << 4)
242
243
244#define STS_SAVE (1 << 8)
245
246#define STS_RESTORE (1 << 9)
247
248#define STS_SRE (1 << 10)
249
250#define STS_CNR XHCI_STS_CNR
251
252#define STS_HCE (1 << 12)
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259
260#define DEV_NOTE_MASK (0xffff)
261#define ENABLE_DEV_NOTE(x) (1 << (x))
262
263
264
265#define DEV_NOTE_FWAKE ENABLE_DEV_NOTE(1)
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269
270#define CMD_RING_PAUSE (1 << 1)
271
272#define CMD_RING_ABORT (1 << 2)
273
274#define CMD_RING_RUNNING (1 << 3)
275
276
277#define CMD_RING_RSVD_BITS (0x3f)
278
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280
281#define MAX_DEVS(p) ((p) & 0xff)
282
283#define CONFIG_U3E (1 << 8)
284
285#define CONFIG_CIE (1 << 9)
286
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289
290#define PORT_CONNECT (1 << 0)
291
292#define PORT_PE (1 << 1)
293
294
295#define PORT_OC (1 << 3)
296
297#define PORT_RESET (1 << 4)
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301
302#define PORT_PLS_MASK (0xf << 5)
303#define XDEV_U0 (0x0 << 5)
304#define XDEV_U1 (0x1 << 5)
305#define XDEV_U2 (0x2 << 5)
306#define XDEV_U3 (0x3 << 5)
307#define XDEV_DISABLED (0x4 << 5)
308#define XDEV_RXDETECT (0x5 << 5)
309#define XDEV_INACTIVE (0x6 << 5)
310#define XDEV_POLLING (0x7 << 5)
311#define XDEV_RECOVERY (0x8 << 5)
312#define XDEV_HOT_RESET (0x9 << 5)
313#define XDEV_COMP_MODE (0xa << 5)
314#define XDEV_TEST_MODE (0xb << 5)
315#define XDEV_RESUME (0xf << 5)
316
317
318#define PORT_POWER (1 << 9)
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327#define DEV_SPEED_MASK (0xf << 10)
328#define XDEV_FS (0x1 << 10)
329#define XDEV_LS (0x2 << 10)
330#define XDEV_HS (0x3 << 10)
331#define XDEV_SS (0x4 << 10)
332#define XDEV_SSP (0x5 << 10)
333#define DEV_UNDEFSPEED(p) (((p) & DEV_SPEED_MASK) == (0x0<<10))
334#define DEV_FULLSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_FS)
335#define DEV_LOWSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_LS)
336#define DEV_HIGHSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_HS)
337#define DEV_SUPERSPEED(p) (((p) & DEV_SPEED_MASK) == XDEV_SS)
338#define DEV_SUPERSPEEDPLUS(p) (((p) & DEV_SPEED_MASK) == XDEV_SSP)
339#define DEV_SUPERSPEED_ANY(p) (((p) & DEV_SPEED_MASK) >= XDEV_SS)
340#define DEV_PORT_SPEED(p) (((p) >> 10) & 0x0f)
341
342
343#define SLOT_SPEED_FS (XDEV_FS << 10)
344#define SLOT_SPEED_LS (XDEV_LS << 10)
345#define SLOT_SPEED_HS (XDEV_HS << 10)
346#define SLOT_SPEED_SS (XDEV_SS << 10)
347#define SLOT_SPEED_SSP (XDEV_SSP << 10)
348
349#define PORT_LED_OFF (0 << 14)
350#define PORT_LED_AMBER (1 << 14)
351#define PORT_LED_GREEN (2 << 14)
352#define PORT_LED_MASK (3 << 14)
353
354#define PORT_LINK_STROBE (1 << 16)
355
356#define PORT_CSC (1 << 17)
357
358#define PORT_PEC (1 << 18)
359
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363
364#define PORT_WRC (1 << 19)
365
366#define PORT_OCC (1 << 20)
367
368#define PORT_RC (1 << 21)
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382#define PORT_PLC (1 << 22)
383
384#define PORT_CEC (1 << 23)
385#define PORT_CHANGE_MASK (PORT_CSC | PORT_PEC | PORT_WRC | PORT_OCC | \
386 PORT_RC | PORT_PLC | PORT_CEC)
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393#define PORT_CAS (1 << 24)
394
395#define PORT_WKCONN_E (1 << 25)
396
397#define PORT_WKDISC_E (1 << 26)
398
399#define PORT_WKOC_E (1 << 27)
400
401
402#define PORT_DEV_REMOVE (1 << 30)
403
404#define PORT_WR (1 << 31)
405
406
407#define DUPLICATE_ENTRY ((u8)(-1))
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412
413#define PORT_U1_TIMEOUT(p) ((p) & 0xff)
414#define PORT_U1_TIMEOUT_MASK 0xff
415
416#define PORT_U2_TIMEOUT(p) (((p) & 0xff) << 8)
417#define PORT_U2_TIMEOUT_MASK (0xff << 8)
418
419
420
421#define PORT_L1S_MASK 7
422#define PORT_L1S_SUCCESS 1
423#define PORT_RWE (1 << 3)
424#define PORT_HIRD(p) (((p) & 0xf) << 4)
425#define PORT_HIRD_MASK (0xf << 4)
426#define PORT_L1DS_MASK (0xff << 8)
427#define PORT_L1DS(p) (((p) & 0xff) << 8)
428#define PORT_HLE (1 << 16)
429#define PORT_TEST_MODE_SHIFT 28
430
431
432#define PORT_RX_LANES(p) (((p) >> 16) & 0xf)
433#define PORT_TX_LANES(p) (((p) >> 20) & 0xf)
434
435
436#define PORT_HIRDM(p)((p) & 3)
437#define PORT_L1_TIMEOUT(p)(((p) & 0xff) << 2)
438#define PORT_BESLD(p)(((p) & 0xf) << 10)
439
440
441#define XHCI_L1_TIMEOUT 512
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452
453#define XHCI_DEFAULT_BESL 4
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461#define XHCI_PORT_POLLING_LFPS_TIME 36
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480struct xhci_intr_reg {
481 __le32 irq_pending;
482 __le32 irq_control;
483 __le32 erst_size;
484 __le32 rsvd;
485 __le64 erst_base;
486 __le64 erst_dequeue;
487};
488
489
490#define ER_IRQ_PENDING(p) ((p) & 0x1)
491
492
493#define ER_IRQ_CLEAR(p) ((p) & 0xfffffffe)
494#define ER_IRQ_ENABLE(p) ((ER_IRQ_CLEAR(p)) | 0x2)
495#define ER_IRQ_DISABLE(p) ((ER_IRQ_CLEAR(p)) & ~(0x2))
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501
502#define ER_IRQ_INTERVAL_MASK (0xffff)
503
504#define ER_IRQ_COUNTER_MASK (0xffff << 16)
505
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508#define ERST_SIZE_MASK (0xffff << 16)
509
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514#define ERST_DESI_MASK (0x7)
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518#define ERST_EHB (1 << 3)
519#define ERST_PTR_MASK (0xf)
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530struct xhci_run_regs {
531 __le32 microframe_index;
532 __le32 rsvd[7];
533 struct xhci_intr_reg ir_set[128];
534};
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545struct xhci_doorbell_array {
546 __le32 doorbell[256];
547};
548
549#define DB_VALUE(ep, stream) ((((ep) + 1) & 0xff) | ((stream) << 16))
550#define DB_VALUE_HOST 0x00000000
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560struct xhci_protocol_caps {
561 u32 revision;
562 u32 name_string;
563 u32 port_info;
564};
565
566#define XHCI_EXT_PORT_MAJOR(x) (((x) >> 24) & 0xff)
567#define XHCI_EXT_PORT_MINOR(x) (((x) >> 16) & 0xff)
568#define XHCI_EXT_PORT_PSIC(x) (((x) >> 28) & 0x0f)
569#define XHCI_EXT_PORT_OFF(x) ((x) & 0xff)
570#define XHCI_EXT_PORT_COUNT(x) (((x) >> 8) & 0xff)
571
572#define XHCI_EXT_PORT_PSIV(x) (((x) >> 0) & 0x0f)
573#define XHCI_EXT_PORT_PSIE(x) (((x) >> 4) & 0x03)
574#define XHCI_EXT_PORT_PLT(x) (((x) >> 6) & 0x03)
575#define XHCI_EXT_PORT_PFD(x) (((x) >> 8) & 0x01)
576#define XHCI_EXT_PORT_LP(x) (((x) >> 14) & 0x03)
577#define XHCI_EXT_PORT_PSIM(x) (((x) >> 16) & 0xffff)
578
579#define PLT_MASK (0x03 << 6)
580#define PLT_SYM (0x00 << 6)
581#define PLT_ASYM_RX (0x02 << 6)
582#define PLT_ASYM_TX (0x03 << 6)
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594struct xhci_container_ctx {
595 unsigned type;
596#define XHCI_CTX_TYPE_DEVICE 0x1
597#define XHCI_CTX_TYPE_INPUT 0x2
598
599 int size;
600
601 u8 *bytes;
602 dma_addr_t dma;
603};
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616struct xhci_slot_ctx {
617 __le32 dev_info;
618 __le32 dev_info2;
619 __le32 tt_info;
620 __le32 dev_state;
621
622 __le32 reserved[4];
623};
624
625
626
627#define ROUTE_STRING_MASK (0xfffff)
628
629#define DEV_SPEED (0xf << 20)
630#define GET_DEV_SPEED(n) (((n) & DEV_SPEED) >> 20)
631
632
633#define DEV_MTT (0x1 << 25)
634
635#define DEV_HUB (0x1 << 26)
636
637#define LAST_CTX_MASK (0x1f << 27)
638#define LAST_CTX(p) ((p) << 27)
639#define LAST_CTX_TO_EP_NUM(p) (((p) >> 27) - 1)
640#define SLOT_FLAG (1 << 0)
641#define EP0_FLAG (1 << 1)
642
643
644
645#define MAX_EXIT (0xffff)
646
647#define ROOT_HUB_PORT(p) (((p) & 0xff) << 16)
648#define DEVINFO_TO_ROOT_HUB_PORT(p) (((p) >> 16) & 0xff)
649
650#define XHCI_MAX_PORTS(p) (((p) & 0xff) << 24)
651#define DEVINFO_TO_MAX_PORTS(p) (((p) & (0xff << 24)) >> 24)
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657
658
659#define TT_SLOT (0xff)
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664#define TT_PORT (0xff << 8)
665#define TT_THINK_TIME(p) (((p) & 0x3) << 16)
666#define GET_TT_THINK_TIME(p) (((p) & (0x3 << 16)) >> 16)
667
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669
670#define DEV_ADDR_MASK (0xff)
671
672
673#define SLOT_STATE (0x1f << 27)
674#define GET_SLOT_STATE(p) (((p) & (0x1f << 27)) >> 27)
675
676#define SLOT_STATE_DISABLED 0
677#define SLOT_STATE_ENABLED SLOT_STATE_DISABLED
678#define SLOT_STATE_DEFAULT 1
679#define SLOT_STATE_ADDRESSED 2
680#define SLOT_STATE_CONFIGURED 3
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700struct xhci_ep_ctx {
701 __le32 ep_info;
702 __le32 ep_info2;
703 __le64 deq;
704 __le32 tx_info;
705
706 __le32 reserved[3];
707};
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718
719#define EP_STATE_MASK (0x7)
720#define EP_STATE_DISABLED 0
721#define EP_STATE_RUNNING 1
722#define EP_STATE_HALTED 2
723#define EP_STATE_STOPPED 3
724#define EP_STATE_ERROR 4
725#define GET_EP_CTX_STATE(ctx) (le32_to_cpu((ctx)->ep_info) & EP_STATE_MASK)
726
727
728#define EP_MULT(p) (((p) & 0x3) << 8)
729#define CTX_TO_EP_MULT(p) (((p) >> 8) & 0x3)
730
731
732
733#define EP_INTERVAL(p) (((p) & 0xff) << 16)
734#define EP_INTERVAL_TO_UFRAMES(p) (1 << (((p) >> 16) & 0xff))
735#define CTX_TO_EP_INTERVAL(p) (((p) >> 16) & 0xff)
736#define EP_MAXPSTREAMS_MASK (0x1f << 10)
737#define EP_MAXPSTREAMS(p) (((p) << 10) & EP_MAXPSTREAMS_MASK)
738#define CTX_TO_EP_MAXPSTREAMS(p) (((p) & EP_MAXPSTREAMS_MASK) >> 10)
739
740#define EP_HAS_LSA (1 << 15)
741
742#define CTX_TO_MAX_ESIT_PAYLOAD_HI(p) (((p) >> 24) & 0xff)
743
744
745
746
747
748
749#define FORCE_EVENT (0x1)
750#define ERROR_COUNT(p) (((p) & 0x3) << 1)
751#define CTX_TO_EP_TYPE(p) (((p) >> 3) & 0x7)
752#define EP_TYPE(p) ((p) << 3)
753#define ISOC_OUT_EP 1
754#define BULK_OUT_EP 2
755#define INT_OUT_EP 3
756#define CTRL_EP 4
757#define ISOC_IN_EP 5
758#define BULK_IN_EP 6
759#define INT_IN_EP 7
760
761
762#define MAX_BURST(p) (((p)&0xff) << 8)
763#define CTX_TO_MAX_BURST(p) (((p) >> 8) & 0xff)
764#define MAX_PACKET(p) (((p)&0xffff) << 16)
765#define MAX_PACKET_MASK (0xffff << 16)
766#define MAX_PACKET_DECODED(p) (((p) >> 16) & 0xffff)
767
768
769#define EP_AVG_TRB_LENGTH(p) ((p) & 0xffff)
770#define EP_MAX_ESIT_PAYLOAD_LO(p) (((p) & 0xffff) << 16)
771#define EP_MAX_ESIT_PAYLOAD_HI(p) ((((p) >> 16) & 0xff) << 24)
772#define CTX_TO_MAX_ESIT_PAYLOAD(p) (((p) >> 16) & 0xffff)
773
774
775#define EP_CTX_CYCLE_MASK (1 << 0)
776#define SCTX_DEQ_MASK (~0xfL)
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785
786struct xhci_input_control_ctx {
787 __le32 drop_flags;
788 __le32 add_flags;
789 __le32 rsvd2[6];
790};
791
792#define EP_IS_ADDED(ctrl_ctx, i) \
793 (le32_to_cpu(ctrl_ctx->add_flags) & (1 << (i + 1)))
794#define EP_IS_DROPPED(ctrl_ctx, i) \
795 (le32_to_cpu(ctrl_ctx->drop_flags) & (1 << (i + 1)))
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799
800
801struct xhci_command {
802
803 struct xhci_container_ctx *in_ctx;
804 u32 status;
805 int slot_id;
806
807
808
809 struct completion *completion;
810 union xhci_trb *command_trb;
811 struct list_head cmd_list;
812};
813
814
815#define DROP_EP(x) (0x1 << x)
816
817#define ADD_EP(x) (0x1 << x)
818
819struct xhci_stream_ctx {
820
821 __le64 stream_ring;
822
823 __le32 reserved[2];
824};
825
826
827#define SCT_FOR_CTX(p) (((p) & 0x7) << 1)
828
829#define SCT_SEC_TR 0
830
831#define SCT_PRI_TR 1
832
833#define SCT_SSA_8 2
834#define SCT_SSA_16 3
835#define SCT_SSA_32 4
836#define SCT_SSA_64 5
837#define SCT_SSA_128 6
838#define SCT_SSA_256 7
839
840
841struct xhci_stream_info {
842 struct xhci_ring **stream_rings;
843
844 unsigned int num_streams;
845
846
847
848 struct xhci_stream_ctx *stream_ctx_array;
849 unsigned int num_stream_ctxs;
850 dma_addr_t ctx_array_dma;
851
852 struct radix_tree_root trb_address_map;
853 struct xhci_command *free_streams_command;
854};
855
856#define SMALL_STREAM_ARRAY_SIZE 256
857#define MEDIUM_STREAM_ARRAY_SIZE 1024
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864
865struct xhci_bw_info {
866
867 unsigned int ep_interval;
868
869 unsigned int mult;
870 unsigned int num_packets;
871 unsigned int max_packet_size;
872 unsigned int max_esit_payload;
873 unsigned int type;
874};
875
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879
880
881#define FS_BLOCK 1
882#define HS_BLOCK 4
883#define SS_BLOCK 16
884#define DMI_BLOCK 32
885
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890
891#define DMI_OVERHEAD 8
892#define DMI_OVERHEAD_BURST 4
893#define SS_OVERHEAD 8
894#define SS_OVERHEAD_BURST 32
895#define HS_OVERHEAD 26
896#define FS_OVERHEAD 20
897#define LS_OVERHEAD 128
898
899
900
901
902
903#define TT_HS_OVERHEAD (31 + 94)
904#define TT_DMI_OVERHEAD (25 + 12)
905
906
907#define FS_BW_LIMIT 1285
908#define TT_BW_LIMIT 1320
909#define HS_BW_LIMIT 1607
910#define SS_BW_LIMIT_IN 3906
911#define DMI_BW_LIMIT_IN 3906
912#define SS_BW_LIMIT_OUT 3906
913#define DMI_BW_LIMIT_OUT 3906
914
915
916#define FS_BW_RESERVED 10
917#define HS_BW_RESERVED 20
918#define SS_BW_RESERVED 10
919
920struct xhci_virt_ep {
921 struct xhci_virt_device *vdev;
922 unsigned int ep_index;
923 struct xhci_ring *ring;
924
925 struct xhci_stream_info *stream_info;
926
927
928
929 struct xhci_ring *new_ring;
930 unsigned int ep_state;
931#define SET_DEQ_PENDING (1 << 0)
932#define EP_HALTED (1 << 1)
933#define EP_STOP_CMD_PENDING (1 << 2)
934
935#define EP_GETTING_STREAMS (1 << 3)
936#define EP_HAS_STREAMS (1 << 4)
937
938#define EP_GETTING_NO_STREAMS (1 << 5)
939#define EP_HARD_CLEAR_TOGGLE (1 << 6)
940#define EP_SOFT_CLEAR_TOGGLE (1 << 7)
941
942#define EP_CLEARING_TT (1 << 8)
943
944 struct list_head cancelled_td_list;
945
946 struct timer_list stop_cmd_timer;
947 struct xhci_hcd *xhci;
948
949
950
951
952 struct xhci_segment *queued_deq_seg;
953 union xhci_trb *queued_deq_ptr;
954
955
956
957
958
959
960
961 bool skip;
962
963 struct xhci_bw_info bw_info;
964 struct list_head bw_endpoint_list;
965
966 int next_frame_id;
967
968 bool use_extended_tbc;
969};
970
971enum xhci_overhead_type {
972 LS_OVERHEAD_TYPE = 0,
973 FS_OVERHEAD_TYPE,
974 HS_OVERHEAD_TYPE,
975};
976
977struct xhci_interval_bw {
978 unsigned int num_packets;
979
980
981
982 struct list_head endpoints;
983
984 unsigned int overhead[3];
985};
986
987#define XHCI_MAX_INTERVAL 16
988
989struct xhci_interval_bw_table {
990 unsigned int interval0_esit_payload;
991 struct xhci_interval_bw interval_bw[XHCI_MAX_INTERVAL];
992
993 unsigned int bw_used;
994 unsigned int ss_bw_in;
995 unsigned int ss_bw_out;
996};
997
998#define EP_CTX_PER_DEV 31
999
1000struct xhci_virt_device {
1001 int slot_id;
1002 struct usb_device *udev;
1003
1004
1005
1006
1007
1008
1009
1010
1011 struct xhci_container_ctx *out_ctx;
1012
1013 struct xhci_container_ctx *in_ctx;
1014 struct xhci_virt_ep eps[EP_CTX_PER_DEV];
1015 u8 fake_port;
1016 u8 real_port;
1017 struct xhci_interval_bw_table *bw_table;
1018 struct xhci_tt_bw_info *tt_info;
1019
1020
1021
1022
1023
1024
1025 unsigned long flags;
1026#define VDEV_PORT_ERROR BIT(0)
1027
1028
1029 u16 current_mel;
1030
1031 void *debugfs_private;
1032};
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042struct xhci_root_port_bw_info {
1043 struct list_head tts;
1044 unsigned int num_active_tts;
1045 struct xhci_interval_bw_table bw_table;
1046};
1047
1048struct xhci_tt_bw_info {
1049 struct list_head tt_list;
1050 int slot_id;
1051 int ttport;
1052 struct xhci_interval_bw_table bw_table;
1053 int active_eps;
1054};
1055
1056
1057
1058
1059
1060
1061struct xhci_device_context_array {
1062
1063 __le64 dev_context_ptrs[MAX_HC_SLOTS];
1064
1065 dma_addr_t dma;
1066};
1067
1068
1069
1070
1071
1072
1073
1074struct xhci_transfer_event {
1075
1076 __le64 buffer;
1077 __le32 transfer_len;
1078
1079 __le32 flags;
1080};
1081
1082
1083
1084#define EVENT_TRB_LEN(p) ((p) & 0xffffff)
1085
1086
1087#define TRB_TO_EP_ID(p) (((p) >> 16) & 0x1f)
1088
1089
1090#define COMP_CODE_MASK (0xff << 24)
1091#define GET_COMP_CODE(p) (((p) & COMP_CODE_MASK) >> 24)
1092#define COMP_INVALID 0
1093#define COMP_SUCCESS 1
1094#define COMP_DATA_BUFFER_ERROR 2
1095#define COMP_BABBLE_DETECTED_ERROR 3
1096#define COMP_USB_TRANSACTION_ERROR 4
1097#define COMP_TRB_ERROR 5
1098#define COMP_STALL_ERROR 6
1099#define COMP_RESOURCE_ERROR 7
1100#define COMP_BANDWIDTH_ERROR 8
1101#define COMP_NO_SLOTS_AVAILABLE_ERROR 9
1102#define COMP_INVALID_STREAM_TYPE_ERROR 10
1103#define COMP_SLOT_NOT_ENABLED_ERROR 11
1104#define COMP_ENDPOINT_NOT_ENABLED_ERROR 12
1105#define COMP_SHORT_PACKET 13
1106#define COMP_RING_UNDERRUN 14
1107#define COMP_RING_OVERRUN 15
1108#define COMP_VF_EVENT_RING_FULL_ERROR 16
1109#define COMP_PARAMETER_ERROR 17
1110#define COMP_BANDWIDTH_OVERRUN_ERROR 18
1111#define COMP_CONTEXT_STATE_ERROR 19
1112#define COMP_NO_PING_RESPONSE_ERROR 20
1113#define COMP_EVENT_RING_FULL_ERROR 21
1114#define COMP_INCOMPATIBLE_DEVICE_ERROR 22
1115#define COMP_MISSED_SERVICE_ERROR 23
1116#define COMP_COMMAND_RING_STOPPED 24
1117#define COMP_COMMAND_ABORTED 25
1118#define COMP_STOPPED 26
1119#define COMP_STOPPED_LENGTH_INVALID 27
1120#define COMP_STOPPED_SHORT_PACKET 28
1121#define COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR 29
1122#define COMP_ISOCH_BUFFER_OVERRUN 31
1123#define COMP_EVENT_LOST_ERROR 32
1124#define COMP_UNDEFINED_ERROR 33
1125#define COMP_INVALID_STREAM_ID_ERROR 34
1126#define COMP_SECONDARY_BANDWIDTH_ERROR 35
1127#define COMP_SPLIT_TRANSACTION_ERROR 36
1128
1129static inline const char *xhci_trb_comp_code_string(u8 status)
1130{
1131 switch (status) {
1132 case COMP_INVALID:
1133 return "Invalid";
1134 case COMP_SUCCESS:
1135 return "Success";
1136 case COMP_DATA_BUFFER_ERROR:
1137 return "Data Buffer Error";
1138 case COMP_BABBLE_DETECTED_ERROR:
1139 return "Babble Detected";
1140 case COMP_USB_TRANSACTION_ERROR:
1141 return "USB Transaction Error";
1142 case COMP_TRB_ERROR:
1143 return "TRB Error";
1144 case COMP_STALL_ERROR:
1145 return "Stall Error";
1146 case COMP_RESOURCE_ERROR:
1147 return "Resource Error";
1148 case COMP_BANDWIDTH_ERROR:
1149 return "Bandwidth Error";
1150 case COMP_NO_SLOTS_AVAILABLE_ERROR:
1151 return "No Slots Available Error";
1152 case COMP_INVALID_STREAM_TYPE_ERROR:
1153 return "Invalid Stream Type Error";
1154 case COMP_SLOT_NOT_ENABLED_ERROR:
1155 return "Slot Not Enabled Error";
1156 case COMP_ENDPOINT_NOT_ENABLED_ERROR:
1157 return "Endpoint Not Enabled Error";
1158 case COMP_SHORT_PACKET:
1159 return "Short Packet";
1160 case COMP_RING_UNDERRUN:
1161 return "Ring Underrun";
1162 case COMP_RING_OVERRUN:
1163 return "Ring Overrun";
1164 case COMP_VF_EVENT_RING_FULL_ERROR:
1165 return "VF Event Ring Full Error";
1166 case COMP_PARAMETER_ERROR:
1167 return "Parameter Error";
1168 case COMP_BANDWIDTH_OVERRUN_ERROR:
1169 return "Bandwidth Overrun Error";
1170 case COMP_CONTEXT_STATE_ERROR:
1171 return "Context State Error";
1172 case COMP_NO_PING_RESPONSE_ERROR:
1173 return "No Ping Response Error";
1174 case COMP_EVENT_RING_FULL_ERROR:
1175 return "Event Ring Full Error";
1176 case COMP_INCOMPATIBLE_DEVICE_ERROR:
1177 return "Incompatible Device Error";
1178 case COMP_MISSED_SERVICE_ERROR:
1179 return "Missed Service Error";
1180 case COMP_COMMAND_RING_STOPPED:
1181 return "Command Ring Stopped";
1182 case COMP_COMMAND_ABORTED:
1183 return "Command Aborted";
1184 case COMP_STOPPED:
1185 return "Stopped";
1186 case COMP_STOPPED_LENGTH_INVALID:
1187 return "Stopped - Length Invalid";
1188 case COMP_STOPPED_SHORT_PACKET:
1189 return "Stopped - Short Packet";
1190 case COMP_MAX_EXIT_LATENCY_TOO_LARGE_ERROR:
1191 return "Max Exit Latency Too Large Error";
1192 case COMP_ISOCH_BUFFER_OVERRUN:
1193 return "Isoch Buffer Overrun";
1194 case COMP_EVENT_LOST_ERROR:
1195 return "Event Lost Error";
1196 case COMP_UNDEFINED_ERROR:
1197 return "Undefined Error";
1198 case COMP_INVALID_STREAM_ID_ERROR:
1199 return "Invalid Stream ID Error";
1200 case COMP_SECONDARY_BANDWIDTH_ERROR:
1201 return "Secondary Bandwidth Error";
1202 case COMP_SPLIT_TRANSACTION_ERROR:
1203 return "Split Transaction Error";
1204 default:
1205 return "Unknown!!";
1206 }
1207}
1208
1209struct xhci_link_trb {
1210
1211 __le64 segment_ptr;
1212 __le32 intr_target;
1213 __le32 control;
1214};
1215
1216
1217#define LINK_TOGGLE (0x1<<1)
1218
1219
1220struct xhci_event_cmd {
1221
1222 __le64 cmd_trb;
1223 __le32 status;
1224 __le32 flags;
1225};
1226
1227
1228
1229
1230#define TRB_BSR (1<<9)
1231
1232
1233#define TRB_DC (1<<9)
1234
1235
1236#define TRB_TSP (1<<9)
1237
1238enum xhci_ep_reset_type {
1239 EP_HARD_RESET,
1240 EP_SOFT_RESET,
1241};
1242
1243
1244#define TRB_TO_VF_INTR_TARGET(p) (((p) & (0x3ff << 22)) >> 22)
1245#define TRB_TO_VF_ID(p) (((p) & (0xff << 16)) >> 16)
1246
1247
1248#define TRB_TO_BELT(p) (((p) & (0xfff << 16)) >> 16)
1249
1250
1251#define TRB_TO_DEV_SPEED(p) (((p) & (0xf << 16)) >> 16)
1252
1253
1254#define TRB_TO_PACKET_TYPE(p) ((p) & 0x1f)
1255#define TRB_TO_ROOTHUB_PORT(p) (((p) & (0xff << 24)) >> 24)
1256
1257enum xhci_setup_dev {
1258 SETUP_CONTEXT_ONLY,
1259 SETUP_CONTEXT_ADDRESS,
1260};
1261
1262
1263
1264#define TRB_TO_SLOT_ID(p) (((p) & (0xff<<24)) >> 24)
1265#define SLOT_ID_FOR_TRB(p) (((p) & 0xff) << 24)
1266
1267
1268#define TRB_TO_EP_INDEX(p) ((((p) & (0x1f << 16)) >> 16) - 1)
1269#define EP_ID_FOR_TRB(p) ((((p) + 1) & 0x1f) << 16)
1270
1271#define SUSPEND_PORT_FOR_TRB(p) (((p) & 1) << 23)
1272#define TRB_TO_SUSPEND_PORT(p) (((p) & (1 << 23)) >> 23)
1273#define LAST_EP_INDEX 30
1274
1275
1276#define TRB_TO_STREAM_ID(p) ((((p) & (0xffff << 16)) >> 16))
1277#define STREAM_ID_FOR_TRB(p) ((((p)) & 0xffff) << 16)
1278#define SCT_FOR_TRB(p) (((p) << 1) & 0x7)
1279
1280
1281#define TRB_TC (1<<1)
1282
1283
1284
1285#define GET_PORT_ID(p) (((p) & (0xff << 24)) >> 24)
1286
1287#define EVENT_DATA (1 << 2)
1288
1289
1290
1291#define TRB_LEN(p) ((p) & 0x1ffff)
1292
1293#define TRB_TD_SIZE(p) (min((p), (u32)31) << 17)
1294#define GET_TD_SIZE(p) (((p) & 0x3e0000) >> 17)
1295
1296#define TRB_TD_SIZE_TBC(p) (min((p), (u32)31) << 17)
1297
1298#define TRB_INTR_TARGET(p) (((p) & 0x3ff) << 22)
1299#define GET_INTR_TARGET(p) (((p) >> 22) & 0x3ff)
1300
1301#define TRB_TBC(p) (((p) & 0x3) << 7)
1302#define TRB_TLBPC(p) (((p) & 0xf) << 16)
1303
1304
1305#define TRB_CYCLE (1<<0)
1306
1307
1308
1309
1310#define TRB_ENT (1<<1)
1311
1312#define TRB_ISP (1<<2)
1313
1314#define TRB_NO_SNOOP (1<<3)
1315
1316#define TRB_CHAIN (1<<4)
1317
1318#define TRB_IOC (1<<5)
1319
1320#define TRB_IDT (1<<6)
1321
1322#define TRB_IDT_MAX_SIZE 8
1323
1324
1325#define TRB_BEI (1<<9)
1326
1327
1328#define TRB_DIR_IN (1<<16)
1329#define TRB_TX_TYPE(p) ((p) << 16)
1330#define TRB_DATA_OUT 2
1331#define TRB_DATA_IN 3
1332
1333
1334#define TRB_SIA (1<<31)
1335#define TRB_FRAME_ID(p) (((p) & 0x7ff) << 20)
1336
1337
1338#define TRB_CACHE_SIZE_HS 8
1339#define TRB_CACHE_SIZE_SS 16
1340
1341struct xhci_generic_trb {
1342 __le32 field[4];
1343};
1344
1345union xhci_trb {
1346 struct xhci_link_trb link;
1347 struct xhci_transfer_event trans_event;
1348 struct xhci_event_cmd event_cmd;
1349 struct xhci_generic_trb generic;
1350};
1351
1352
1353#define TRB_TYPE_BITMASK (0xfc00)
1354#define TRB_TYPE(p) ((p) << 10)
1355#define TRB_FIELD_TO_TYPE(p) (((p) & TRB_TYPE_BITMASK) >> 10)
1356
1357
1358#define TRB_NORMAL 1
1359
1360#define TRB_SETUP 2
1361
1362#define TRB_DATA 3
1363
1364#define TRB_STATUS 4
1365
1366#define TRB_ISOC 5
1367
1368#define TRB_LINK 6
1369#define TRB_EVENT_DATA 7
1370
1371#define TRB_TR_NOOP 8
1372
1373
1374#define TRB_ENABLE_SLOT 9
1375
1376#define TRB_DISABLE_SLOT 10
1377
1378#define TRB_ADDR_DEV 11
1379
1380#define TRB_CONFIG_EP 12
1381
1382#define TRB_EVAL_CONTEXT 13
1383
1384#define TRB_RESET_EP 14
1385
1386#define TRB_STOP_RING 15
1387
1388#define TRB_SET_DEQ 16
1389
1390#define TRB_RESET_DEV 17
1391
1392#define TRB_FORCE_EVENT 18
1393
1394#define TRB_NEG_BANDWIDTH 19
1395
1396#define TRB_SET_LT 20
1397
1398#define TRB_GET_BW 21
1399
1400#define TRB_FORCE_HEADER 22
1401
1402#define TRB_CMD_NOOP 23
1403
1404
1405
1406#define TRB_TRANSFER 32
1407
1408#define TRB_COMPLETION 33
1409
1410#define TRB_PORT_STATUS 34
1411
1412#define TRB_BANDWIDTH_EVENT 35
1413
1414#define TRB_DOORBELL 36
1415
1416#define TRB_HC_EVENT 37
1417
1418#define TRB_DEV_NOTE 38
1419
1420#define TRB_MFINDEX_WRAP 39
1421
1422#define TRB_VENDOR_DEFINED_LOW 48
1423
1424#define TRB_NEC_CMD_COMP 48
1425
1426#define TRB_NEC_GET_FW 49
1427
1428static inline const char *xhci_trb_type_string(u8 type)
1429{
1430 switch (type) {
1431 case TRB_NORMAL:
1432 return "Normal";
1433 case TRB_SETUP:
1434 return "Setup Stage";
1435 case TRB_DATA:
1436 return "Data Stage";
1437 case TRB_STATUS:
1438 return "Status Stage";
1439 case TRB_ISOC:
1440 return "Isoch";
1441 case TRB_LINK:
1442 return "Link";
1443 case TRB_EVENT_DATA:
1444 return "Event Data";
1445 case TRB_TR_NOOP:
1446 return "No-Op";
1447 case TRB_ENABLE_SLOT:
1448 return "Enable Slot Command";
1449 case TRB_DISABLE_SLOT:
1450 return "Disable Slot Command";
1451 case TRB_ADDR_DEV:
1452 return "Address Device Command";
1453 case TRB_CONFIG_EP:
1454 return "Configure Endpoint Command";
1455 case TRB_EVAL_CONTEXT:
1456 return "Evaluate Context Command";
1457 case TRB_RESET_EP:
1458 return "Reset Endpoint Command";
1459 case TRB_STOP_RING:
1460 return "Stop Ring Command";
1461 case TRB_SET_DEQ:
1462 return "Set TR Dequeue Pointer Command";
1463 case TRB_RESET_DEV:
1464 return "Reset Device Command";
1465 case TRB_FORCE_EVENT:
1466 return "Force Event Command";
1467 case TRB_NEG_BANDWIDTH:
1468 return "Negotiate Bandwidth Command";
1469 case TRB_SET_LT:
1470 return "Set Latency Tolerance Value Command";
1471 case TRB_GET_BW:
1472 return "Get Port Bandwidth Command";
1473 case TRB_FORCE_HEADER:
1474 return "Force Header Command";
1475 case TRB_CMD_NOOP:
1476 return "No-Op Command";
1477 case TRB_TRANSFER:
1478 return "Transfer Event";
1479 case TRB_COMPLETION:
1480 return "Command Completion Event";
1481 case TRB_PORT_STATUS:
1482 return "Port Status Change Event";
1483 case TRB_BANDWIDTH_EVENT:
1484 return "Bandwidth Request Event";
1485 case TRB_DOORBELL:
1486 return "Doorbell Event";
1487 case TRB_HC_EVENT:
1488 return "Host Controller Event";
1489 case TRB_DEV_NOTE:
1490 return "Device Notification Event";
1491 case TRB_MFINDEX_WRAP:
1492 return "MFINDEX Wrap Event";
1493 case TRB_NEC_CMD_COMP:
1494 return "NEC Command Completion Event";
1495 case TRB_NEC_GET_FW:
1496 return "NET Get Firmware Revision Command";
1497 default:
1498 return "UNKNOWN";
1499 }
1500}
1501
1502#define TRB_TYPE_LINK(x) (((x) & TRB_TYPE_BITMASK) == TRB_TYPE(TRB_LINK))
1503
1504#define TRB_TYPE_LINK_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1505 cpu_to_le32(TRB_TYPE(TRB_LINK)))
1506#define TRB_TYPE_NOOP_LE32(x) (((x) & cpu_to_le32(TRB_TYPE_BITMASK)) == \
1507 cpu_to_le32(TRB_TYPE(TRB_TR_NOOP)))
1508
1509#define NEC_FW_MINOR(p) (((p) >> 0) & 0xff)
1510#define NEC_FW_MAJOR(p) (((p) >> 8) & 0xff)
1511
1512
1513
1514
1515
1516
1517#define TRBS_PER_SEGMENT 256
1518
1519#define MAX_RSVD_CMD_TRBS (TRBS_PER_SEGMENT - 3)
1520#define TRB_SEGMENT_SIZE (TRBS_PER_SEGMENT*16)
1521#define TRB_SEGMENT_SHIFT (ilog2(TRB_SEGMENT_SIZE))
1522
1523#define TRB_MAX_BUFF_SHIFT 16
1524#define TRB_MAX_BUFF_SIZE (1 << TRB_MAX_BUFF_SHIFT)
1525
1526#define TRB_BUFF_LEN_UP_TO_BOUNDARY(addr) (TRB_MAX_BUFF_SIZE - \
1527 (addr & (TRB_MAX_BUFF_SIZE - 1)))
1528#define MAX_SOFT_RETRY 3
1529
1530
1531
1532
1533#define AVOID_BEI_INTERVAL_MIN 8
1534#define AVOID_BEI_INTERVAL_MAX 32
1535
1536struct xhci_segment {
1537 union xhci_trb *trbs;
1538
1539 struct xhci_segment *next;
1540 dma_addr_t dma;
1541
1542 dma_addr_t bounce_dma;
1543 void *bounce_buf;
1544 unsigned int bounce_offs;
1545 unsigned int bounce_len;
1546};
1547
1548enum xhci_cancelled_td_status {
1549 TD_DIRTY = 0,
1550 TD_HALTED,
1551 TD_CLEARING_CACHE,
1552 TD_CLEARED,
1553};
1554
1555struct xhci_td {
1556 struct list_head td_list;
1557 struct list_head cancelled_td_list;
1558 int status;
1559 enum xhci_cancelled_td_status cancel_status;
1560 struct urb *urb;
1561 struct xhci_segment *start_seg;
1562 union xhci_trb *first_trb;
1563 union xhci_trb *last_trb;
1564 struct xhci_segment *last_trb_seg;
1565 struct xhci_segment *bounce_seg;
1566
1567 bool urb_length_set;
1568 unsigned int num_trbs;
1569};
1570
1571
1572#define XHCI_CMD_DEFAULT_TIMEOUT (5 * HZ)
1573
1574
1575struct xhci_cd {
1576 struct xhci_command *command;
1577 union xhci_trb *cmd_trb;
1578};
1579
1580enum xhci_ring_type {
1581 TYPE_CTRL = 0,
1582 TYPE_ISOC,
1583 TYPE_BULK,
1584 TYPE_INTR,
1585 TYPE_STREAM,
1586 TYPE_COMMAND,
1587 TYPE_EVENT,
1588};
1589
1590static inline const char *xhci_ring_type_string(enum xhci_ring_type type)
1591{
1592 switch (type) {
1593 case TYPE_CTRL:
1594 return "CTRL";
1595 case TYPE_ISOC:
1596 return "ISOC";
1597 case TYPE_BULK:
1598 return "BULK";
1599 case TYPE_INTR:
1600 return "INTR";
1601 case TYPE_STREAM:
1602 return "STREAM";
1603 case TYPE_COMMAND:
1604 return "CMD";
1605 case TYPE_EVENT:
1606 return "EVENT";
1607 }
1608
1609 return "UNKNOWN";
1610}
1611
1612struct xhci_ring {
1613 struct xhci_segment *first_seg;
1614 struct xhci_segment *last_seg;
1615 union xhci_trb *enqueue;
1616 struct xhci_segment *enq_seg;
1617 union xhci_trb *dequeue;
1618 struct xhci_segment *deq_seg;
1619 struct list_head td_list;
1620
1621
1622
1623
1624
1625 u32 cycle_state;
1626 unsigned int err_count;
1627 unsigned int stream_id;
1628 unsigned int num_segs;
1629 unsigned int num_trbs_free;
1630 unsigned int num_trbs_free_temp;
1631 unsigned int bounce_buf_len;
1632 enum xhci_ring_type type;
1633 bool last_td_was_short;
1634 struct radix_tree_root *trb_address_map;
1635};
1636
1637struct xhci_erst_entry {
1638
1639 __le64 seg_addr;
1640 __le32 seg_size;
1641
1642 __le32 rsvd;
1643};
1644
1645struct xhci_erst {
1646 struct xhci_erst_entry *entries;
1647 unsigned int num_entries;
1648
1649 dma_addr_t erst_dma_addr;
1650
1651 unsigned int erst_size;
1652};
1653
1654struct xhci_scratchpad {
1655 u64 *sp_array;
1656 dma_addr_t sp_dma;
1657 void **sp_buffers;
1658};
1659
1660struct urb_priv {
1661 int num_tds;
1662 int num_tds_done;
1663 struct xhci_td td[];
1664};
1665
1666
1667
1668
1669
1670
1671#define ERST_NUM_SEGS 1
1672
1673#define POLL_TIMEOUT 60
1674
1675#define XHCI_STOP_EP_CMD_TIMEOUT 5
1676
1677
1678struct s3_save {
1679 u32 command;
1680 u32 dev_nt;
1681 u64 dcbaa_ptr;
1682 u32 config_reg;
1683 u32 irq_pending;
1684 u32 irq_control;
1685 u32 erst_size;
1686 u64 erst_base;
1687 u64 erst_dequeue;
1688};
1689
1690
1691struct dev_info {
1692 u32 dev_id;
1693 struct list_head list;
1694};
1695
1696struct xhci_bus_state {
1697 unsigned long bus_suspended;
1698 unsigned long next_statechange;
1699
1700
1701
1702 u32 port_c_suspend;
1703 u32 suspended_ports;
1704 u32 port_remote_wakeup;
1705 unsigned long resume_done[USB_MAXCHILDREN];
1706
1707 unsigned long resuming_ports;
1708
1709 unsigned long rexit_ports;
1710 struct completion rexit_done[USB_MAXCHILDREN];
1711 struct completion u3exit_done[USB_MAXCHILDREN];
1712};
1713
1714
1715
1716
1717
1718
1719#define XHCI_MAX_REXIT_TIMEOUT_MS 20
1720struct xhci_port_cap {
1721 u32 *psi;
1722 u8 psi_count;
1723 u8 psi_uid_count;
1724 u8 maj_rev;
1725 u8 min_rev;
1726};
1727
1728struct xhci_port {
1729 __le32 __iomem *addr;
1730 int hw_portnum;
1731 int hcd_portnum;
1732 struct xhci_hub *rhub;
1733 struct xhci_port_cap *port_cap;
1734};
1735
1736struct xhci_hub {
1737 struct xhci_port **ports;
1738 unsigned int num_ports;
1739 struct usb_hcd *hcd;
1740
1741 struct xhci_bus_state bus_state;
1742
1743 u8 maj_rev;
1744 u8 min_rev;
1745};
1746
1747
1748struct xhci_hcd {
1749 struct usb_hcd *main_hcd;
1750 struct usb_hcd *shared_hcd;
1751
1752 struct xhci_cap_regs __iomem *cap_regs;
1753 struct xhci_op_regs __iomem *op_regs;
1754 struct xhci_run_regs __iomem *run_regs;
1755 struct xhci_doorbell_array __iomem *dba;
1756
1757 struct xhci_intr_reg __iomem *ir_set;
1758
1759
1760 __u32 hcs_params1;
1761 __u32 hcs_params2;
1762 __u32 hcs_params3;
1763 __u32 hcc_params;
1764 __u32 hcc_params2;
1765
1766 spinlock_t lock;
1767
1768
1769 u8 sbrn;
1770 u16 hci_version;
1771 u8 max_slots;
1772 u8 max_interrupters;
1773 u8 max_ports;
1774 u8 isoc_threshold;
1775
1776 u32 imod_interval;
1777 u32 isoc_bei_interval;
1778 int event_ring_max;
1779
1780 int page_size;
1781
1782 int page_shift;
1783
1784 int msix_count;
1785
1786 struct clk *clk;
1787 struct clk *reg_clk;
1788
1789 struct reset_control *reset;
1790
1791 struct xhci_device_context_array *dcbaa;
1792 struct xhci_ring *cmd_ring;
1793 unsigned int cmd_ring_state;
1794#define CMD_RING_STATE_RUNNING (1 << 0)
1795#define CMD_RING_STATE_ABORTED (1 << 1)
1796#define CMD_RING_STATE_STOPPED (1 << 2)
1797 struct list_head cmd_list;
1798 unsigned int cmd_ring_reserved_trbs;
1799 struct delayed_work cmd_timer;
1800 struct completion cmd_ring_stop_completion;
1801 struct xhci_command *current_cmd;
1802 struct xhci_ring *event_ring;
1803 struct xhci_erst erst;
1804
1805 struct xhci_scratchpad *scratchpad;
1806
1807 struct list_head lpm_failed_devs;
1808
1809
1810
1811 struct mutex mutex;
1812
1813 struct xhci_command *lpm_command;
1814
1815 struct xhci_virt_device *devs[MAX_HC_SLOTS];
1816
1817 struct xhci_root_port_bw_info *rh_bw;
1818
1819
1820 struct dma_pool *device_pool;
1821 struct dma_pool *segment_pool;
1822 struct dma_pool *small_streams_pool;
1823 struct dma_pool *medium_streams_pool;
1824
1825
1826 unsigned int xhc_state;
1827
1828 u32 command;
1829 struct s3_save s3;
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842#define XHCI_STATE_DYING (1 << 0)
1843#define XHCI_STATE_HALTED (1 << 1)
1844#define XHCI_STATE_REMOVING (1 << 2)
1845 unsigned long long quirks;
1846#define XHCI_LINK_TRB_QUIRK BIT_ULL(0)
1847#define XHCI_RESET_EP_QUIRK BIT_ULL(1)
1848#define XHCI_NEC_HOST BIT_ULL(2)
1849#define XHCI_AMD_PLL_FIX BIT_ULL(3)
1850#define XHCI_SPURIOUS_SUCCESS BIT_ULL(4)
1851
1852
1853
1854
1855
1856
1857
1858
1859
1860#define XHCI_EP_LIMIT_QUIRK BIT_ULL(5)
1861#define XHCI_BROKEN_MSI BIT_ULL(6)
1862#define XHCI_RESET_ON_RESUME BIT_ULL(7)
1863#define XHCI_SW_BW_CHECKING BIT_ULL(8)
1864#define XHCI_AMD_0x96_HOST BIT_ULL(9)
1865#define XHCI_TRUST_TX_LENGTH BIT_ULL(10)
1866#define XHCI_LPM_SUPPORT BIT_ULL(11)
1867#define XHCI_INTEL_HOST BIT_ULL(12)
1868#define XHCI_SPURIOUS_REBOOT BIT_ULL(13)
1869#define XHCI_COMP_MODE_QUIRK BIT_ULL(14)
1870#define XHCI_AVOID_BEI BIT_ULL(15)
1871#define XHCI_PLAT BIT_ULL(16)
1872#define XHCI_SLOW_SUSPEND BIT_ULL(17)
1873#define XHCI_SPURIOUS_WAKEUP BIT_ULL(18)
1874
1875#define XHCI_BROKEN_STREAMS BIT_ULL(19)
1876#define XHCI_PME_STUCK_QUIRK BIT_ULL(20)
1877#define XHCI_MTK_HOST BIT_ULL(21)
1878#define XHCI_SSIC_PORT_UNUSED BIT_ULL(22)
1879#define XHCI_NO_64BIT_SUPPORT BIT_ULL(23)
1880#define XHCI_MISSING_CAS BIT_ULL(24)
1881
1882#define XHCI_BROKEN_PORT_PED BIT_ULL(25)
1883#define XHCI_LIMIT_ENDPOINT_INTERVAL_7 BIT_ULL(26)
1884#define XHCI_U2_DISABLE_WAKE BIT_ULL(27)
1885#define XHCI_ASMEDIA_MODIFY_FLOWCONTROL BIT_ULL(28)
1886#define XHCI_HW_LPM_DISABLE BIT_ULL(29)
1887#define XHCI_SUSPEND_DELAY BIT_ULL(30)
1888#define XHCI_INTEL_USB_ROLE_SW BIT_ULL(31)
1889#define XHCI_ZERO_64B_REGS BIT_ULL(32)
1890#define XHCI_DEFAULT_PM_RUNTIME_ALLOW BIT_ULL(33)
1891#define XHCI_RESET_PLL_ON_DISCONNECT BIT_ULL(34)
1892#define XHCI_SNPS_BROKEN_SUSPEND BIT_ULL(35)
1893#define XHCI_RENESAS_FW_QUIRK BIT_ULL(36)
1894#define XHCI_SKIP_PHY_INIT BIT_ULL(37)
1895#define XHCI_DISABLE_SPARSE BIT_ULL(38)
1896#define XHCI_SG_TRB_CACHE_SIZE_QUIRK BIT_ULL(39)
1897#define XHCI_NO_SOFT_RETRY BIT_ULL(40)
1898#define XHCI_BROKEN_D3COLD BIT_ULL(41)
1899
1900 unsigned int num_active_eps;
1901 unsigned int limit_active_eps;
1902 struct xhci_port *hw_ports;
1903 struct xhci_hub usb2_rhub;
1904 struct xhci_hub usb3_rhub;
1905
1906 unsigned hw_lpm_support:1;
1907
1908 unsigned broken_suspend:1;
1909
1910 u32 *ext_caps;
1911 unsigned int num_ext_caps;
1912
1913 struct xhci_port_cap *port_caps;
1914 unsigned int num_port_caps;
1915
1916 struct timer_list comp_mode_recovery_timer;
1917 u32 port_status_u0;
1918 u16 test_mode;
1919
1920#define COMP_MODE_RCVRY_MSECS 2000
1921
1922 struct dentry *debugfs_root;
1923 struct dentry *debugfs_slots;
1924 struct list_head regset_list;
1925
1926 void *dbc;
1927
1928 unsigned long priv[] __aligned(sizeof(s64));
1929};
1930
1931
1932struct xhci_driver_overrides {
1933 size_t extra_priv_size;
1934 int (*reset)(struct usb_hcd *hcd);
1935 int (*start)(struct usb_hcd *hcd);
1936 int (*add_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1937 struct usb_host_endpoint *ep);
1938 int (*drop_endpoint)(struct usb_hcd *hcd, struct usb_device *udev,
1939 struct usb_host_endpoint *ep);
1940 int (*check_bandwidth)(struct usb_hcd *, struct usb_device *);
1941 void (*reset_bandwidth)(struct usb_hcd *, struct usb_device *);
1942};
1943
1944#define XHCI_CFC_DELAY 10
1945
1946
1947static inline struct xhci_hcd *hcd_to_xhci(struct usb_hcd *hcd)
1948{
1949 struct usb_hcd *primary_hcd;
1950
1951 if (usb_hcd_is_primary_hcd(hcd))
1952 primary_hcd = hcd;
1953 else
1954 primary_hcd = hcd->primary_hcd;
1955
1956 return (struct xhci_hcd *) (primary_hcd->hcd_priv);
1957}
1958
1959static inline struct usb_hcd *xhci_to_hcd(struct xhci_hcd *xhci)
1960{
1961 return xhci->main_hcd;
1962}
1963
1964#define xhci_dbg(xhci, fmt, args...) \
1965 dev_dbg(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1966#define xhci_err(xhci, fmt, args...) \
1967 dev_err(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1968#define xhci_warn(xhci, fmt, args...) \
1969 dev_warn(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1970#define xhci_warn_ratelimited(xhci, fmt, args...) \
1971 dev_warn_ratelimited(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1972#define xhci_info(xhci, fmt, args...) \
1973 dev_info(xhci_to_hcd(xhci)->self.controller , fmt , ## args)
1974
1975
1976
1977
1978
1979
1980
1981
1982
1983
1984static inline u64 xhci_read_64(const struct xhci_hcd *xhci,
1985 __le64 __iomem *regs)
1986{
1987 return lo_hi_readq(regs);
1988}
1989static inline void xhci_write_64(struct xhci_hcd *xhci,
1990 const u64 val, __le64 __iomem *regs)
1991{
1992 lo_hi_writeq(val, regs);
1993}
1994
1995static inline int xhci_link_trb_quirk(struct xhci_hcd *xhci)
1996{
1997 return xhci->quirks & XHCI_LINK_TRB_QUIRK;
1998}
1999
2000
2001char *xhci_get_slot_state(struct xhci_hcd *xhci,
2002 struct xhci_container_ctx *ctx);
2003void xhci_dbg_trace(struct xhci_hcd *xhci, void (*trace)(struct va_format *),
2004 const char *fmt, ...);
2005
2006
2007void xhci_mem_cleanup(struct xhci_hcd *xhci);
2008int xhci_mem_init(struct xhci_hcd *xhci, gfp_t flags);
2009void xhci_free_virt_device(struct xhci_hcd *xhci, int slot_id);
2010int xhci_alloc_virt_device(struct xhci_hcd *xhci, int slot_id, struct usb_device *udev, gfp_t flags);
2011int xhci_setup_addressable_virt_dev(struct xhci_hcd *xhci, struct usb_device *udev);
2012void xhci_copy_ep0_dequeue_into_input_ctx(struct xhci_hcd *xhci,
2013 struct usb_device *udev);
2014unsigned int xhci_get_endpoint_index(struct usb_endpoint_descriptor *desc);
2015unsigned int xhci_get_endpoint_address(unsigned int ep_index);
2016unsigned int xhci_last_valid_endpoint(u32 added_ctxs);
2017void xhci_endpoint_zero(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev, struct usb_host_endpoint *ep);
2018void xhci_update_tt_active_eps(struct xhci_hcd *xhci,
2019 struct xhci_virt_device *virt_dev,
2020 int old_active_eps);
2021void xhci_clear_endpoint_bw_info(struct xhci_bw_info *bw_info);
2022void xhci_update_bw_info(struct xhci_hcd *xhci,
2023 struct xhci_container_ctx *in_ctx,
2024 struct xhci_input_control_ctx *ctrl_ctx,
2025 struct xhci_virt_device *virt_dev);
2026void xhci_endpoint_copy(struct xhci_hcd *xhci,
2027 struct xhci_container_ctx *in_ctx,
2028 struct xhci_container_ctx *out_ctx,
2029 unsigned int ep_index);
2030void xhci_slot_copy(struct xhci_hcd *xhci,
2031 struct xhci_container_ctx *in_ctx,
2032 struct xhci_container_ctx *out_ctx);
2033int xhci_endpoint_init(struct xhci_hcd *xhci, struct xhci_virt_device *virt_dev,
2034 struct usb_device *udev, struct usb_host_endpoint *ep,
2035 gfp_t mem_flags);
2036struct xhci_ring *xhci_ring_alloc(struct xhci_hcd *xhci,
2037 unsigned int num_segs, unsigned int cycle_state,
2038 enum xhci_ring_type type, unsigned int max_packet, gfp_t flags);
2039void xhci_ring_free(struct xhci_hcd *xhci, struct xhci_ring *ring);
2040int xhci_ring_expansion(struct xhci_hcd *xhci, struct xhci_ring *ring,
2041 unsigned int num_trbs, gfp_t flags);
2042int xhci_alloc_erst(struct xhci_hcd *xhci,
2043 struct xhci_ring *evt_ring,
2044 struct xhci_erst *erst,
2045 gfp_t flags);
2046void xhci_initialize_ring_info(struct xhci_ring *ring,
2047 unsigned int cycle_state);
2048void xhci_free_erst(struct xhci_hcd *xhci, struct xhci_erst *erst);
2049void xhci_free_endpoint_ring(struct xhci_hcd *xhci,
2050 struct xhci_virt_device *virt_dev,
2051 unsigned int ep_index);
2052struct xhci_stream_info *xhci_alloc_stream_info(struct xhci_hcd *xhci,
2053 unsigned int num_stream_ctxs,
2054 unsigned int num_streams,
2055 unsigned int max_packet, gfp_t flags);
2056void xhci_free_stream_info(struct xhci_hcd *xhci,
2057 struct xhci_stream_info *stream_info);
2058void xhci_setup_streams_ep_input_ctx(struct xhci_hcd *xhci,
2059 struct xhci_ep_ctx *ep_ctx,
2060 struct xhci_stream_info *stream_info);
2061void xhci_setup_no_streams_ep_input_ctx(struct xhci_ep_ctx *ep_ctx,
2062 struct xhci_virt_ep *ep);
2063void xhci_free_device_endpoint_resources(struct xhci_hcd *xhci,
2064 struct xhci_virt_device *virt_dev, bool drop_control_ep);
2065struct xhci_ring *xhci_dma_to_transfer_ring(
2066 struct xhci_virt_ep *ep,
2067 u64 address);
2068struct xhci_command *xhci_alloc_command(struct xhci_hcd *xhci,
2069 bool allocate_completion, gfp_t mem_flags);
2070struct xhci_command *xhci_alloc_command_with_ctx(struct xhci_hcd *xhci,
2071 bool allocate_completion, gfp_t mem_flags);
2072void xhci_urb_free_priv(struct urb_priv *urb_priv);
2073void xhci_free_command(struct xhci_hcd *xhci,
2074 struct xhci_command *command);
2075struct xhci_container_ctx *xhci_alloc_container_ctx(struct xhci_hcd *xhci,
2076 int type, gfp_t flags);
2077void xhci_free_container_ctx(struct xhci_hcd *xhci,
2078 struct xhci_container_ctx *ctx);
2079
2080
2081typedef void (*xhci_get_quirks_t)(struct device *, struct xhci_hcd *);
2082int xhci_handshake(void __iomem *ptr, u32 mask, u32 done, int usec);
2083void xhci_quiesce(struct xhci_hcd *xhci);
2084int xhci_halt(struct xhci_hcd *xhci);
2085int xhci_start(struct xhci_hcd *xhci);
2086int xhci_reset(struct xhci_hcd *xhci);
2087int xhci_run(struct usb_hcd *hcd);
2088int xhci_gen_setup(struct usb_hcd *hcd, xhci_get_quirks_t get_quirks);
2089void xhci_shutdown(struct usb_hcd *hcd);
2090void xhci_init_driver(struct hc_driver *drv,
2091 const struct xhci_driver_overrides *over);
2092int xhci_add_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2093 struct usb_host_endpoint *ep);
2094int xhci_drop_endpoint(struct usb_hcd *hcd, struct usb_device *udev,
2095 struct usb_host_endpoint *ep);
2096int xhci_check_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2097void xhci_reset_bandwidth(struct usb_hcd *hcd, struct usb_device *udev);
2098int xhci_disable_slot(struct xhci_hcd *xhci, u32 slot_id);
2099int xhci_ext_cap_init(struct xhci_hcd *xhci);
2100
2101int xhci_suspend(struct xhci_hcd *xhci, bool do_wakeup);
2102int xhci_resume(struct xhci_hcd *xhci, bool hibernated);
2103
2104irqreturn_t xhci_irq(struct usb_hcd *hcd);
2105irqreturn_t xhci_msi_irq(int irq, void *hcd);
2106int xhci_alloc_dev(struct usb_hcd *hcd, struct usb_device *udev);
2107int xhci_alloc_tt_info(struct xhci_hcd *xhci,
2108 struct xhci_virt_device *virt_dev,
2109 struct usb_device *hdev,
2110 struct usb_tt *tt, gfp_t mem_flags);
2111
2112
2113dma_addr_t xhci_trb_virt_to_dma(struct xhci_segment *seg, union xhci_trb *trb);
2114struct xhci_segment *trb_in_td(struct xhci_hcd *xhci,
2115 struct xhci_segment *start_seg, union xhci_trb *start_trb,
2116 union xhci_trb *end_trb, dma_addr_t suspect_dma, bool debug);
2117int xhci_is_vendor_info_code(struct xhci_hcd *xhci, unsigned int trb_comp_code);
2118void xhci_ring_cmd_db(struct xhci_hcd *xhci);
2119int xhci_queue_slot_control(struct xhci_hcd *xhci, struct xhci_command *cmd,
2120 u32 trb_type, u32 slot_id);
2121int xhci_queue_address_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2122 dma_addr_t in_ctx_ptr, u32 slot_id, enum xhci_setup_dev);
2123int xhci_queue_vendor_command(struct xhci_hcd *xhci, struct xhci_command *cmd,
2124 u32 field1, u32 field2, u32 field3, u32 field4);
2125int xhci_queue_stop_endpoint(struct xhci_hcd *xhci, struct xhci_command *cmd,
2126 int slot_id, unsigned int ep_index, int suspend);
2127int xhci_queue_ctrl_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2128 int slot_id, unsigned int ep_index);
2129int xhci_queue_bulk_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2130 int slot_id, unsigned int ep_index);
2131int xhci_queue_intr_tx(struct xhci_hcd *xhci, gfp_t mem_flags, struct urb *urb,
2132 int slot_id, unsigned int ep_index);
2133int xhci_queue_isoc_tx_prepare(struct xhci_hcd *xhci, gfp_t mem_flags,
2134 struct urb *urb, int slot_id, unsigned int ep_index);
2135int xhci_queue_configure_endpoint(struct xhci_hcd *xhci,
2136 struct xhci_command *cmd, dma_addr_t in_ctx_ptr, u32 slot_id,
2137 bool command_must_succeed);
2138int xhci_queue_evaluate_context(struct xhci_hcd *xhci, struct xhci_command *cmd,
2139 dma_addr_t in_ctx_ptr, u32 slot_id, bool command_must_succeed);
2140int xhci_queue_reset_ep(struct xhci_hcd *xhci, struct xhci_command *cmd,
2141 int slot_id, unsigned int ep_index,
2142 enum xhci_ep_reset_type reset_type);
2143int xhci_queue_reset_device(struct xhci_hcd *xhci, struct xhci_command *cmd,
2144 u32 slot_id);
2145void xhci_cleanup_stalled_ring(struct xhci_hcd *xhci, unsigned int slot_id,
2146 unsigned int ep_index, unsigned int stream_id,
2147 struct xhci_td *td);
2148void xhci_stop_endpoint_command_watchdog(struct timer_list *t);
2149void xhci_handle_command_timeout(struct work_struct *work);
2150
2151void xhci_ring_ep_doorbell(struct xhci_hcd *xhci, unsigned int slot_id,
2152 unsigned int ep_index, unsigned int stream_id);
2153void xhci_ring_doorbell_for_active_rings(struct xhci_hcd *xhci,
2154 unsigned int slot_id,
2155 unsigned int ep_index);
2156void xhci_cleanup_command_queue(struct xhci_hcd *xhci);
2157void inc_deq(struct xhci_hcd *xhci, struct xhci_ring *ring);
2158unsigned int count_trbs(u64 addr, u64 len);
2159
2160
2161void xhci_set_link_state(struct xhci_hcd *xhci, struct xhci_port *port,
2162 u32 link_state);
2163void xhci_test_and_clear_bit(struct xhci_hcd *xhci, struct xhci_port *port,
2164 u32 port_bit);
2165int xhci_hub_control(struct usb_hcd *hcd, u16 typeReq, u16 wValue, u16 wIndex,
2166 char *buf, u16 wLength);
2167int xhci_hub_status_data(struct usb_hcd *hcd, char *buf);
2168int xhci_find_raw_port_number(struct usb_hcd *hcd, int port1);
2169struct xhci_hub *xhci_get_rhub(struct usb_hcd *hcd);
2170
2171void xhci_hc_died(struct xhci_hcd *xhci);
2172
2173#ifdef CONFIG_PM
2174int xhci_bus_suspend(struct usb_hcd *hcd);
2175int xhci_bus_resume(struct usb_hcd *hcd);
2176unsigned long xhci_get_resuming_ports(struct usb_hcd *hcd);
2177#else
2178#define xhci_bus_suspend NULL
2179#define xhci_bus_resume NULL
2180#define xhci_get_resuming_ports NULL
2181#endif
2182
2183u32 xhci_port_state_to_neutral(u32 state);
2184int xhci_find_slot_id_by_port(struct usb_hcd *hcd, struct xhci_hcd *xhci,
2185 u16 port);
2186void xhci_ring_device(struct xhci_hcd *xhci, int slot_id);
2187
2188
2189struct xhci_input_control_ctx *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx);
2190struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx);
2191struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_hcd *xhci, struct xhci_container_ctx *ctx, unsigned int ep_index);
2192
2193struct xhci_ring *xhci_triad_to_transfer_ring(struct xhci_hcd *xhci,
2194 unsigned int slot_id, unsigned int ep_index,
2195 unsigned int stream_id);
2196
2197static inline struct xhci_ring *xhci_urb_to_transfer_ring(struct xhci_hcd *xhci,
2198 struct urb *urb)
2199{
2200 return xhci_triad_to_transfer_ring(xhci, urb->dev->slot_id,
2201 xhci_get_endpoint_index(&urb->ep->desc),
2202 urb->stream_id);
2203}
2204
2205
2206
2207
2208
2209
2210static inline bool xhci_urb_suitable_for_idt(struct urb *urb)
2211{
2212 if (!usb_endpoint_xfer_isoc(&urb->ep->desc) && usb_urb_dir_out(urb) &&
2213 usb_endpoint_maxp(&urb->ep->desc) >= TRB_IDT_MAX_SIZE &&
2214 urb->transfer_buffer_length <= TRB_IDT_MAX_SIZE &&
2215 !(urb->transfer_flags & URB_NO_TRANSFER_DMA_MAP) &&
2216 !urb->num_sgs)
2217 return true;
2218
2219 return false;
2220}
2221
2222static inline char *xhci_slot_state_string(u32 state)
2223{
2224 switch (state) {
2225 case SLOT_STATE_ENABLED:
2226 return "enabled/disabled";
2227 case SLOT_STATE_DEFAULT:
2228 return "default";
2229 case SLOT_STATE_ADDRESSED:
2230 return "addressed";
2231 case SLOT_STATE_CONFIGURED:
2232 return "configured";
2233 default:
2234 return "reserved";
2235 }
2236}
2237
2238static inline const char *xhci_decode_trb(u32 field0, u32 field1, u32 field2,
2239 u32 field3)
2240{
2241 static char str[256];
2242 int type = TRB_FIELD_TO_TYPE(field3);
2243
2244 switch (type) {
2245 case TRB_LINK:
2246 sprintf(str,
2247 "LINK %08x%08x intr %d type '%s' flags %c:%c:%c:%c",
2248 field1, field0, GET_INTR_TARGET(field2),
2249 xhci_trb_type_string(type),
2250 field3 & TRB_IOC ? 'I' : 'i',
2251 field3 & TRB_CHAIN ? 'C' : 'c',
2252 field3 & TRB_TC ? 'T' : 't',
2253 field3 & TRB_CYCLE ? 'C' : 'c');
2254 break;
2255 case TRB_TRANSFER:
2256 case TRB_COMPLETION:
2257 case TRB_PORT_STATUS:
2258 case TRB_BANDWIDTH_EVENT:
2259 case TRB_DOORBELL:
2260 case TRB_HC_EVENT:
2261 case TRB_DEV_NOTE:
2262 case TRB_MFINDEX_WRAP:
2263 sprintf(str,
2264 "TRB %08x%08x status '%s' len %d slot %d ep %d type '%s' flags %c:%c",
2265 field1, field0,
2266 xhci_trb_comp_code_string(GET_COMP_CODE(field2)),
2267 EVENT_TRB_LEN(field2), TRB_TO_SLOT_ID(field3),
2268
2269 TRB_TO_EP_INDEX(field3) + 1,
2270 xhci_trb_type_string(type),
2271 field3 & EVENT_DATA ? 'E' : 'e',
2272 field3 & TRB_CYCLE ? 'C' : 'c');
2273
2274 break;
2275 case TRB_SETUP:
2276 sprintf(str, "bRequestType %02x bRequest %02x wValue %02x%02x wIndex %02x%02x wLength %d length %d TD size %d intr %d type '%s' flags %c:%c:%c",
2277 field0 & 0xff,
2278 (field0 & 0xff00) >> 8,
2279 (field0 & 0xff000000) >> 24,
2280 (field0 & 0xff0000) >> 16,
2281 (field1 & 0xff00) >> 8,
2282 field1 & 0xff,
2283 (field1 & 0xff000000) >> 16 |
2284 (field1 & 0xff0000) >> 16,
2285 TRB_LEN(field2), GET_TD_SIZE(field2),
2286 GET_INTR_TARGET(field2),
2287 xhci_trb_type_string(type),
2288 field3 & TRB_IDT ? 'I' : 'i',
2289 field3 & TRB_IOC ? 'I' : 'i',
2290 field3 & TRB_CYCLE ? 'C' : 'c');
2291 break;
2292 case TRB_DATA:
2293 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c",
2294 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2295 GET_INTR_TARGET(field2),
2296 xhci_trb_type_string(type),
2297 field3 & TRB_IDT ? 'I' : 'i',
2298 field3 & TRB_IOC ? 'I' : 'i',
2299 field3 & TRB_CHAIN ? 'C' : 'c',
2300 field3 & TRB_NO_SNOOP ? 'S' : 's',
2301 field3 & TRB_ISP ? 'I' : 'i',
2302 field3 & TRB_ENT ? 'E' : 'e',
2303 field3 & TRB_CYCLE ? 'C' : 'c');
2304 break;
2305 case TRB_STATUS:
2306 sprintf(str, "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c",
2307 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2308 GET_INTR_TARGET(field2),
2309 xhci_trb_type_string(type),
2310 field3 & TRB_IOC ? 'I' : 'i',
2311 field3 & TRB_CHAIN ? 'C' : 'c',
2312 field3 & TRB_ENT ? 'E' : 'e',
2313 field3 & TRB_CYCLE ? 'C' : 'c');
2314 break;
2315 case TRB_NORMAL:
2316 case TRB_ISOC:
2317 case TRB_EVENT_DATA:
2318 case TRB_TR_NOOP:
2319 sprintf(str,
2320 "Buffer %08x%08x length %d TD size %d intr %d type '%s' flags %c:%c:%c:%c:%c:%c:%c:%c",
2321 field1, field0, TRB_LEN(field2), GET_TD_SIZE(field2),
2322 GET_INTR_TARGET(field2),
2323 xhci_trb_type_string(type),
2324 field3 & TRB_BEI ? 'B' : 'b',
2325 field3 & TRB_IDT ? 'I' : 'i',
2326 field3 & TRB_IOC ? 'I' : 'i',
2327 field3 & TRB_CHAIN ? 'C' : 'c',
2328 field3 & TRB_NO_SNOOP ? 'S' : 's',
2329 field3 & TRB_ISP ? 'I' : 'i',
2330 field3 & TRB_ENT ? 'E' : 'e',
2331 field3 & TRB_CYCLE ? 'C' : 'c');
2332 break;
2333
2334 case TRB_CMD_NOOP:
2335 case TRB_ENABLE_SLOT:
2336 sprintf(str,
2337 "%s: flags %c",
2338 xhci_trb_type_string(type),
2339 field3 & TRB_CYCLE ? 'C' : 'c');
2340 break;
2341 case TRB_DISABLE_SLOT:
2342 case TRB_NEG_BANDWIDTH:
2343 sprintf(str,
2344 "%s: slot %d flags %c",
2345 xhci_trb_type_string(type),
2346 TRB_TO_SLOT_ID(field3),
2347 field3 & TRB_CYCLE ? 'C' : 'c');
2348 break;
2349 case TRB_ADDR_DEV:
2350 sprintf(str,
2351 "%s: ctx %08x%08x slot %d flags %c:%c",
2352 xhci_trb_type_string(type),
2353 field1, field0,
2354 TRB_TO_SLOT_ID(field3),
2355 field3 & TRB_BSR ? 'B' : 'b',
2356 field3 & TRB_CYCLE ? 'C' : 'c');
2357 break;
2358 case TRB_CONFIG_EP:
2359 sprintf(str,
2360 "%s: ctx %08x%08x slot %d flags %c:%c",
2361 xhci_trb_type_string(type),
2362 field1, field0,
2363 TRB_TO_SLOT_ID(field3),
2364 field3 & TRB_DC ? 'D' : 'd',
2365 field3 & TRB_CYCLE ? 'C' : 'c');
2366 break;
2367 case TRB_EVAL_CONTEXT:
2368 sprintf(str,
2369 "%s: ctx %08x%08x slot %d flags %c",
2370 xhci_trb_type_string(type),
2371 field1, field0,
2372 TRB_TO_SLOT_ID(field3),
2373 field3 & TRB_CYCLE ? 'C' : 'c');
2374 break;
2375 case TRB_RESET_EP:
2376 sprintf(str,
2377 "%s: ctx %08x%08x slot %d ep %d flags %c:%c",
2378 xhci_trb_type_string(type),
2379 field1, field0,
2380 TRB_TO_SLOT_ID(field3),
2381
2382 TRB_TO_EP_INDEX(field3) + 1,
2383 field3 & TRB_TSP ? 'T' : 't',
2384 field3 & TRB_CYCLE ? 'C' : 'c');
2385 break;
2386 case TRB_STOP_RING:
2387 sprintf(str,
2388 "%s: slot %d sp %d ep %d flags %c",
2389 xhci_trb_type_string(type),
2390 TRB_TO_SLOT_ID(field3),
2391 TRB_TO_SUSPEND_PORT(field3),
2392
2393 TRB_TO_EP_INDEX(field3) + 1,
2394 field3 & TRB_CYCLE ? 'C' : 'c');
2395 break;
2396 case TRB_SET_DEQ:
2397 sprintf(str,
2398 "%s: deq %08x%08x stream %d slot %d ep %d flags %c",
2399 xhci_trb_type_string(type),
2400 field1, field0,
2401 TRB_TO_STREAM_ID(field2),
2402 TRB_TO_SLOT_ID(field3),
2403
2404 TRB_TO_EP_INDEX(field3) + 1,
2405 field3 & TRB_CYCLE ? 'C' : 'c');
2406 break;
2407 case TRB_RESET_DEV:
2408 sprintf(str,
2409 "%s: slot %d flags %c",
2410 xhci_trb_type_string(type),
2411 TRB_TO_SLOT_ID(field3),
2412 field3 & TRB_CYCLE ? 'C' : 'c');
2413 break;
2414 case TRB_FORCE_EVENT:
2415 sprintf(str,
2416 "%s: event %08x%08x vf intr %d vf id %d flags %c",
2417 xhci_trb_type_string(type),
2418 field1, field0,
2419 TRB_TO_VF_INTR_TARGET(field2),
2420 TRB_TO_VF_ID(field3),
2421 field3 & TRB_CYCLE ? 'C' : 'c');
2422 break;
2423 case TRB_SET_LT:
2424 sprintf(str,
2425 "%s: belt %d flags %c",
2426 xhci_trb_type_string(type),
2427 TRB_TO_BELT(field3),
2428 field3 & TRB_CYCLE ? 'C' : 'c');
2429 break;
2430 case TRB_GET_BW:
2431 sprintf(str,
2432 "%s: ctx %08x%08x slot %d speed %d flags %c",
2433 xhci_trb_type_string(type),
2434 field1, field0,
2435 TRB_TO_SLOT_ID(field3),
2436 TRB_TO_DEV_SPEED(field3),
2437 field3 & TRB_CYCLE ? 'C' : 'c');
2438 break;
2439 case TRB_FORCE_HEADER:
2440 sprintf(str,
2441 "%s: info %08x%08x%08x pkt type %d roothub port %d flags %c",
2442 xhci_trb_type_string(type),
2443 field2, field1, field0 & 0xffffffe0,
2444 TRB_TO_PACKET_TYPE(field0),
2445 TRB_TO_ROOTHUB_PORT(field3),
2446 field3 & TRB_CYCLE ? 'C' : 'c');
2447 break;
2448 default:
2449 sprintf(str,
2450 "type '%s' -> raw %08x %08x %08x %08x",
2451 xhci_trb_type_string(type),
2452 field0, field1, field2, field3);
2453 }
2454
2455 return str;
2456}
2457
2458static inline const char *xhci_decode_ctrl_ctx(unsigned long drop,
2459 unsigned long add)
2460{
2461 static char str[1024];
2462 unsigned int bit;
2463 int ret = 0;
2464
2465 if (drop) {
2466 ret = sprintf(str, "Drop:");
2467 for_each_set_bit(bit, &drop, 32)
2468 ret += sprintf(str + ret, " %d%s",
2469 bit / 2,
2470 bit % 2 ? "in":"out");
2471 ret += sprintf(str + ret, ", ");
2472 }
2473
2474 if (add) {
2475 ret += sprintf(str + ret, "Add:%s%s",
2476 (add & SLOT_FLAG) ? " slot":"",
2477 (add & EP0_FLAG) ? " ep0":"");
2478 add &= ~(SLOT_FLAG | EP0_FLAG);
2479 for_each_set_bit(bit, &add, 32)
2480 ret += sprintf(str + ret, " %d%s",
2481 bit / 2,
2482 bit % 2 ? "in":"out");
2483 }
2484 return str;
2485}
2486
2487static inline const char *xhci_decode_slot_context(u32 info, u32 info2,
2488 u32 tt_info, u32 state)
2489{
2490 static char str[1024];
2491 u32 speed;
2492 u32 hub;
2493 u32 mtt;
2494 int ret = 0;
2495
2496 speed = info & DEV_SPEED;
2497 hub = info & DEV_HUB;
2498 mtt = info & DEV_MTT;
2499
2500 ret = sprintf(str, "RS %05x %s%s%s Ctx Entries %d MEL %d us Port# %d/%d",
2501 info & ROUTE_STRING_MASK,
2502 ({ char *s;
2503 switch (speed) {
2504 case SLOT_SPEED_FS:
2505 s = "full-speed";
2506 break;
2507 case SLOT_SPEED_LS:
2508 s = "low-speed";
2509 break;
2510 case SLOT_SPEED_HS:
2511 s = "high-speed";
2512 break;
2513 case SLOT_SPEED_SS:
2514 s = "super-speed";
2515 break;
2516 case SLOT_SPEED_SSP:
2517 s = "super-speed plus";
2518 break;
2519 default:
2520 s = "UNKNOWN speed";
2521 } s; }),
2522 mtt ? " multi-TT" : "",
2523 hub ? " Hub" : "",
2524 (info & LAST_CTX_MASK) >> 27,
2525 info2 & MAX_EXIT,
2526 DEVINFO_TO_ROOT_HUB_PORT(info2),
2527 DEVINFO_TO_MAX_PORTS(info2));
2528
2529 ret += sprintf(str + ret, " [TT Slot %d Port# %d TTT %d Intr %d] Addr %d State %s",
2530 tt_info & TT_SLOT, (tt_info & TT_PORT) >> 8,
2531 GET_TT_THINK_TIME(tt_info), GET_INTR_TARGET(tt_info),
2532 state & DEV_ADDR_MASK,
2533 xhci_slot_state_string(GET_SLOT_STATE(state)));
2534
2535 return str;
2536}
2537
2538
2539static inline const char *xhci_portsc_link_state_string(u32 portsc)
2540{
2541 switch (portsc & PORT_PLS_MASK) {
2542 case XDEV_U0:
2543 return "U0";
2544 case XDEV_U1:
2545 return "U1";
2546 case XDEV_U2:
2547 return "U2";
2548 case XDEV_U3:
2549 return "U3";
2550 case XDEV_DISABLED:
2551 return "Disabled";
2552 case XDEV_RXDETECT:
2553 return "RxDetect";
2554 case XDEV_INACTIVE:
2555 return "Inactive";
2556 case XDEV_POLLING:
2557 return "Polling";
2558 case XDEV_RECOVERY:
2559 return "Recovery";
2560 case XDEV_HOT_RESET:
2561 return "Hot Reset";
2562 case XDEV_COMP_MODE:
2563 return "Compliance mode";
2564 case XDEV_TEST_MODE:
2565 return "Test mode";
2566 case XDEV_RESUME:
2567 return "Resume";
2568 default:
2569 break;
2570 }
2571 return "Unknown";
2572}
2573
2574static inline const char *xhci_decode_portsc(u32 portsc)
2575{
2576 static char str[256];
2577 int ret;
2578
2579 ret = sprintf(str, "%s %s %s Link:%s PortSpeed:%d ",
2580 portsc & PORT_POWER ? "Powered" : "Powered-off",
2581 portsc & PORT_CONNECT ? "Connected" : "Not-connected",
2582 portsc & PORT_PE ? "Enabled" : "Disabled",
2583 xhci_portsc_link_state_string(portsc),
2584 DEV_PORT_SPEED(portsc));
2585
2586 if (portsc & PORT_OC)
2587 ret += sprintf(str + ret, "OverCurrent ");
2588 if (portsc & PORT_RESET)
2589 ret += sprintf(str + ret, "In-Reset ");
2590
2591 ret += sprintf(str + ret, "Change: ");
2592 if (portsc & PORT_CSC)
2593 ret += sprintf(str + ret, "CSC ");
2594 if (portsc & PORT_PEC)
2595 ret += sprintf(str + ret, "PEC ");
2596 if (portsc & PORT_WRC)
2597 ret += sprintf(str + ret, "WRC ");
2598 if (portsc & PORT_OCC)
2599 ret += sprintf(str + ret, "OCC ");
2600 if (portsc & PORT_RC)
2601 ret += sprintf(str + ret, "PRC ");
2602 if (portsc & PORT_PLC)
2603 ret += sprintf(str + ret, "PLC ");
2604 if (portsc & PORT_CEC)
2605 ret += sprintf(str + ret, "CEC ");
2606 if (portsc & PORT_CAS)
2607 ret += sprintf(str + ret, "CAS ");
2608
2609 ret += sprintf(str + ret, "Wake: ");
2610 if (portsc & PORT_WKCONN_E)
2611 ret += sprintf(str + ret, "WCE ");
2612 if (portsc & PORT_WKDISC_E)
2613 ret += sprintf(str + ret, "WDE ");
2614 if (portsc & PORT_WKOC_E)
2615 ret += sprintf(str + ret, "WOE ");
2616
2617 return str;
2618}
2619
2620static inline const char *xhci_decode_usbsts(u32 usbsts)
2621{
2622 static char str[256];
2623 int ret = 0;
2624
2625 if (usbsts == ~(u32)0)
2626 return " 0xffffffff";
2627 if (usbsts & STS_HALT)
2628 ret += sprintf(str + ret, " HCHalted");
2629 if (usbsts & STS_FATAL)
2630 ret += sprintf(str + ret, " HSE");
2631 if (usbsts & STS_EINT)
2632 ret += sprintf(str + ret, " EINT");
2633 if (usbsts & STS_PORT)
2634 ret += sprintf(str + ret, " PCD");
2635 if (usbsts & STS_SAVE)
2636 ret += sprintf(str + ret, " SSS");
2637 if (usbsts & STS_RESTORE)
2638 ret += sprintf(str + ret, " RSS");
2639 if (usbsts & STS_SRE)
2640 ret += sprintf(str + ret, " SRE");
2641 if (usbsts & STS_CNR)
2642 ret += sprintf(str + ret, " CNR");
2643 if (usbsts & STS_HCE)
2644 ret += sprintf(str + ret, " HCE");
2645
2646 return str;
2647}
2648
2649static inline const char *xhci_decode_doorbell(u32 slot, u32 doorbell)
2650{
2651 static char str[256];
2652 u8 ep;
2653 u16 stream;
2654 int ret;
2655
2656 ep = (doorbell & 0xff);
2657 stream = doorbell >> 16;
2658
2659 if (slot == 0) {
2660 sprintf(str, "Command Ring %d", doorbell);
2661 return str;
2662 }
2663 ret = sprintf(str, "Slot %d ", slot);
2664 if (ep > 0 && ep < 32)
2665 ret = sprintf(str + ret, "ep%d%s",
2666 ep / 2,
2667 ep % 2 ? "in" : "out");
2668 else if (ep == 0 || ep < 248)
2669 ret = sprintf(str + ret, "Reserved %d", ep);
2670 else
2671 ret = sprintf(str + ret, "Vendor Defined %d", ep);
2672 if (stream)
2673 ret = sprintf(str + ret, " Stream %d", stream);
2674
2675 return str;
2676}
2677
2678static inline const char *xhci_ep_state_string(u8 state)
2679{
2680 switch (state) {
2681 case EP_STATE_DISABLED:
2682 return "disabled";
2683 case EP_STATE_RUNNING:
2684 return "running";
2685 case EP_STATE_HALTED:
2686 return "halted";
2687 case EP_STATE_STOPPED:
2688 return "stopped";
2689 case EP_STATE_ERROR:
2690 return "error";
2691 default:
2692 return "INVALID";
2693 }
2694}
2695
2696static inline const char *xhci_ep_type_string(u8 type)
2697{
2698 switch (type) {
2699 case ISOC_OUT_EP:
2700 return "Isoc OUT";
2701 case BULK_OUT_EP:
2702 return "Bulk OUT";
2703 case INT_OUT_EP:
2704 return "Int OUT";
2705 case CTRL_EP:
2706 return "Ctrl";
2707 case ISOC_IN_EP:
2708 return "Isoc IN";
2709 case BULK_IN_EP:
2710 return "Bulk IN";
2711 case INT_IN_EP:
2712 return "Int IN";
2713 default:
2714 return "INVALID";
2715 }
2716}
2717
2718static inline const char *xhci_decode_ep_context(u32 info, u32 info2, u64 deq,
2719 u32 tx_info)
2720{
2721 static char str[1024];
2722 int ret;
2723
2724 u32 esit;
2725 u16 maxp;
2726 u16 avg;
2727
2728 u8 max_pstr;
2729 u8 ep_state;
2730 u8 interval;
2731 u8 ep_type;
2732 u8 burst;
2733 u8 cerr;
2734 u8 mult;
2735
2736 bool lsa;
2737 bool hid;
2738
2739 esit = CTX_TO_MAX_ESIT_PAYLOAD_HI(info) << 16 |
2740 CTX_TO_MAX_ESIT_PAYLOAD(tx_info);
2741
2742 ep_state = info & EP_STATE_MASK;
2743 max_pstr = CTX_TO_EP_MAXPSTREAMS(info);
2744 interval = CTX_TO_EP_INTERVAL(info);
2745 mult = CTX_TO_EP_MULT(info) + 1;
2746 lsa = !!(info & EP_HAS_LSA);
2747
2748 cerr = (info2 & (3 << 1)) >> 1;
2749 ep_type = CTX_TO_EP_TYPE(info2);
2750 hid = !!(info2 & (1 << 7));
2751 burst = CTX_TO_MAX_BURST(info2);
2752 maxp = MAX_PACKET_DECODED(info2);
2753
2754 avg = EP_AVG_TRB_LENGTH(tx_info);
2755
2756 ret = sprintf(str, "State %s mult %d max P. Streams %d %s",
2757 xhci_ep_state_string(ep_state), mult,
2758 max_pstr, lsa ? "LSA " : "");
2759
2760 ret += sprintf(str + ret, "interval %d us max ESIT payload %d CErr %d ",
2761 (1 << interval) * 125, esit, cerr);
2762
2763 ret += sprintf(str + ret, "Type %s %sburst %d maxp %d deq %016llx ",
2764 xhci_ep_type_string(ep_type), hid ? "HID" : "",
2765 burst, maxp, deq);
2766
2767 ret += sprintf(str + ret, "avg trb len %d", avg);
2768
2769 return str;
2770}
2771
2772#endif
2773