// SPDX-License-Identifier: GPL-2.0
/*
 *  Probe module for 8250/16550-type PCI serial ports.
 *
 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
 *
 *  Copyright (C) 2001 Russell King, All Rights Reserved.
 */
#undef DEBUG
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/string.h>
#include <linux/kernel.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/tty.h>
#include <linux/serial_reg.h>
#include <linux/serial_core.h>
#include <linux/8250_pci.h>
#include <linux/bitops.h>

#include <asm/byteorder.h>
#include <asm/io.h>

#include "8250.h"

/*
 * init function returns:
 *  > 0 - number of ports
 *  = 0 - use board->num_ports
 *  < 0 - error
 */
struct pci_serial_quirk {
        u32     vendor;
        u32     device;
        u32     subvendor;
        u32     subdevice;
        int     (*probe)(struct pci_dev *dev);
        int     (*init)(struct pci_dev *dev);
        int     (*setup)(struct serial_private *,
                         const struct pciserial_board *,
                         struct uart_8250_port *, int);
        void    (*exit)(struct pci_dev *dev);
};

struct f815xxa_data {
        spinlock_t lock;
        int idx;
};

struct serial_private {
        struct pci_dev          *dev;
        unsigned int            nr;
        struct pci_serial_quirk *quirk;
        const struct pciserial_board *board;
        int                     line[];
};

#define PCI_DEVICE_ID_HPE_PCI_SERIAL    0x37e

static const struct pci_device_id pci_use_msi[] = {
        { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
                         0xA000, 0x1000) },
        { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
                         0xA000, 0x1000) },
        { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
                         0xA000, 0x1000) },
        { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
                         PCI_ANY_ID, PCI_ANY_ID) },
        { }
};

static int pci_default_setup(struct serial_private*,
          const struct pciserial_board*, struct uart_8250_port *, int);

static void moan_device(const char *str, struct pci_dev *dev)
{
        dev_err(&dev->dev,
               "%s: %s\n"
               "Please send the output of lspci -vv, this\n"
               "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
               "manufacturer and name of serial board or\n"
               "modem board to <linux-serial@vger.kernel.org>.\n",
               pci_name(dev), str, dev->vendor, dev->device,
               dev->subsystem_vendor, dev->subsystem_device);
}

static int
setup_port(struct serial_private *priv, struct uart_8250_port *port,
           int bar, int offset, int regshift)
{
        struct pci_dev *dev = priv->dev;

        if (bar >= PCI_STD_NUM_BARS)
                return -EINVAL;

        if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
                if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
                        return -ENOMEM;

                port->port.iotype = UPIO_MEM;
                port->port.iobase = 0;
                port->port.mapbase = pci_resource_start(dev, bar) + offset;
                port->port.membase = pcim_iomap_table(dev)[bar] + offset;
                port->port.regshift = regshift;
        } else {
                port->port.iotype = UPIO_PORT;
                port->port.iobase = pci_resource_start(dev, bar) + offset;
                port->port.mapbase = 0;
                port->port.membase = NULL;
                port->port.regshift = 0;
        }
        return 0;
}

/*
 * ADDI-DATA GmbH communication cards <info@addi-data.com>
 */
static int addidata_apci7800_setup(struct serial_private *priv,
                                const struct pciserial_board *board,
                                struct uart_8250_port *port, int idx)
{
        unsigned int bar = 0, offset = board->first_offset;
        bar = FL_GET_BASE(board->flags);

        if (idx < 2) {
                offset += idx * board->uart_offset;
        } else if ((idx >= 2) && (idx < 4)) {
                bar += 1;
                offset += ((idx - 2) * board->uart_offset);
        } else if ((idx >= 4) && (idx < 6)) {
                bar += 2;
                offset += ((idx - 4) * board->uart_offset);
        } else if (idx >= 6) {
                bar += 3;
                offset += ((idx - 6) * board->uart_offset);
        }

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

/*
 * AFAVLAB uses a different mixture of BARs and offsets
 * Not that ugly ;) -- HW
 */
static int
afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
              struct uart_8250_port *port, int idx)
{
        unsigned int bar, offset = board->first_offset;

        bar = FL_GET_BASE(board->flags);
        if (idx < 4)
                bar += idx;
        else {
                bar = 4;
                offset += (idx - 4) * board->uart_offset;
        }

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

/*
 * HP's Remote Management Console.  The Diva chip came in several
 * different versions.  N-class, L2000 and A500 have two Diva chips, each
 * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 * one Diva chip, but it has been expanded to 5 UARTs.
 */
static int pci_hp_diva_init(struct pci_dev *dev)
{
        int rc = 0;

        switch (dev->subsystem_device) {
        case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
        case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
        case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
                rc = 3;
                break;
        case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
                rc = 2;
                break;
        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
                rc = 4;
                break;
        case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
        case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
                rc = 1;
                break;
        }

        return rc;
}

/*
 * HP's Diva chip puts the 4th/5th serial port further out, and
 * some serial ports are supposed to be hidden on certain models.
 */
static int
pci_hp_diva_setup(struct serial_private *priv,
                const struct pciserial_board *board,
                struct uart_8250_port *port, int idx)
{
        unsigned int offset = board->first_offset;
        unsigned int bar = FL_GET_BASE(board->flags);

        switch (priv->dev->subsystem_device) {
        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
                if (idx == 3)
                        idx++;
                break;
        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
                if (idx > 0)
                        idx++;
                if (idx > 2)
                        idx++;
                break;
        }
        if (idx > 2)
                offset = 0x18;

        offset += idx * board->uart_offset;

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

/*
 * Added for EKF Intel i960 serial boards
 */
static int pci_inteli960ni_init(struct pci_dev *dev)
{
        u32 oldval;

        if (!(dev->subsystem_device & 0x1000))
                return -ENODEV;

        /* is firmware started? */
        pci_read_config_dword(dev, 0x44, &oldval);
        if (oldval == 0x00001000L) { /* RESET value */
                dev_dbg(&dev->dev, "Local i960 firmware missing\n");
                return -ENODEV;
        }
        return 0;
}

/*
 * Some PCI serial cards using the PLX 9050 PCI interface chip require
 * that the card interrupt be explicitly enabled or disabled.  This
 * seems to be mainly needed on card using the PLX which also use I/O
 * mapped memory.
 */
static int pci_plx9050_init(struct pci_dev *dev)
{
        u8 irq_config;
        void __iomem *p;

        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
                moan_device("no memory in bar 0", dev);
                return 0;
        }

        irq_config = 0x41;
        if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
            dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
                irq_config = 0x43;

        if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
            (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
                /*
                 * As the megawolf cards have the int pins active
                 * high, and have 2 UART chips, both ints must be
                 * enabled on the 9050. Also, the UARTS are set in
                 * 16450 mode by default, so we have to enable the
                 * 16C950 'enhanced' mode so that we can use the
                 * deep FIFOs
                 */
                irq_config = 0x5b;
        /*
         * enable/disable interrupts
         */
        p = ioremap(pci_resource_start(dev, 0), 0x80);
        if (p == NULL)
                return -ENOMEM;
        writel(irq_config, p + 0x4c);

        /*
         * Read the register back to ensure that it took effect.
         */
        readl(p + 0x4c);
        iounmap(p);

        return 0;
}

static void pci_plx9050_exit(struct pci_dev *dev)
{
        u8 __iomem *p;

        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
                return;

        /*
         * disable interrupts
         */
        p = ioremap(pci_resource_start(dev, 0), 0x80);
        if (p != NULL) {
                writel(0, p + 0x4c);

                /*
                 * Read the register back to ensure that it took effect.
                 */
                readl(p + 0x4c);
                iounmap(p);
        }
}

#define NI8420_INT_ENABLE_REG   0x38
#define NI8420_INT_ENABLE_BIT   0x2000

static void pci_ni8420_exit(struct pci_dev *dev)
{
        void __iomem *p;
        unsigned int bar = 0;

        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
                moan_device("no memory in bar", dev);
                return;
        }

        p = pci_ioremap_bar(dev, bar);
        if (p == NULL)
                return;

        /* Disable the CPU Interrupt */
        writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
               p + NI8420_INT_ENABLE_REG);
        iounmap(p);
}


/* MITE registers */
#define MITE_IOWBSR1    0xc4
#define MITE_IOWCR1     0xf4
#define MITE_LCIMR1     0x08
#define MITE_LCIMR2     0x10

#define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)

static void pci_ni8430_exit(struct pci_dev *dev)
{
        void __iomem *p;
        unsigned int bar = 0;

        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
                moan_device("no memory in bar", dev);
                return;
        }

        p = pci_ioremap_bar(dev, bar);
        if (p == NULL)
                return;

        /* Disable the CPU Interrupt */
        writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
        iounmap(p);
}

/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
static int
sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
                struct uart_8250_port *port, int idx)
{
        unsigned int bar, offset = board->first_offset;

        bar = 0;

        if (idx < 4) {
                /* first four channels map to 0, 0x100, 0x200, 0x300 */
                offset += idx * board->uart_offset;
        } else if (idx < 8) {
                /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
                offset += idx * board->uart_offset + 0xC00;
        } else /* we have only 8 ports on PMC-OCTALPRO */
                return 1;

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

/*
* This does initialization for PMC OCTALPRO cards:
* maps the device memory, resets the UARTs (needed, bc
* if the module is removed and inserted again, the card
* is in the sleep mode) and enables global interrupt.
*/

/* global control register offset for SBS PMC-OctalPro */
#define OCT_REG_CR_OFF          0x500

static int sbs_init(struct pci_dev *dev)
{
        u8 __iomem *p;

        p = pci_ioremap_bar(dev, 0);

        if (p == NULL)
                return -ENOMEM;
        /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
        writeb(0x10, p + OCT_REG_CR_OFF);
        udelay(50);
        writeb(0x0, p + OCT_REG_CR_OFF);

        /* Set bit-2 (INTENABLE) of Control Register */
        writeb(0x4, p + OCT_REG_CR_OFF);
        iounmap(p);

        return 0;
}

/*
 * Disables the global interrupt of PMC-OctalPro
 */

static void sbs_exit(struct pci_dev *dev)
{
        u8 __iomem *p;

        p = pci_ioremap_bar(dev, 0);
        /* FIXME: What if resource_len < OCT_REG_CR_OFF */
        if (p != NULL)
                writeb(0, p + OCT_REG_CR_OFF);
        iounmap(p);
}

/*
 * SIIG serial cards have an PCI interface chip which also controls
 * the UART clocking frequency. Each UART can be clocked independently
 * (except cards equipped with 4 UARTs) and initial clocking settings
 * are stored in the EEPROM chip. It can cause problems because this
 * version of serial driver doesn't support differently clocked UART's
 * on single PCI card. To prevent this, initialization functions set
 * high frequency clocking for all UART's on given card. It is safe (I
 * hope) because it doesn't touch EEPROM settings to prevent conflicts
 * with other OSes (like M$ DOS).
 *
 *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 *
 * There is two family of SIIG serial cards with different PCI
 * interface chip and different configuration methods:
 *     - 10x cards have control registers in IO and/or memory space;
 *     - 20x cards have control registers in standard PCI configuration space.
 *
 * Note: all 10x cards have PCI device ids 0x10..
 *       all 20x cards have PCI device ids 0x20..
 *
 * There are also Quartet Serial cards which use Oxford Semiconductor
 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 *
 * Note: some SIIG cards are probed by the parport_serial object.
 */

#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)

static int pci_siig10x_init(struct pci_dev *dev)
{
        u16 data;
        void __iomem *p;

        switch (dev->device & 0xfff8) {
        case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
                data = 0xffdf;
                break;
        case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
                data = 0xf7ff;
                break;
        default:                        /* 1S1P, 4S */
                data = 0xfffb;
                break;
        }

        p = ioremap(pci_resource_start(dev, 0), 0x80);
        if (p == NULL)
                return -ENOMEM;

        writew(readw(p + 0x28) & data, p + 0x28);
        readw(p + 0x28);
        iounmap(p);
        return 0;
}

#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)

static int pci_siig20x_init(struct pci_dev *dev)
{
        u8 data;

        /* Change clock frequency for the first UART. */
        pci_read_config_byte(dev, 0x6f, &data);
        pci_write_config_byte(dev, 0x6f, data & 0xef);

        /* If this card has 2 UART, we have to do the same with second UART. */
        if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
            ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
                pci_read_config_byte(dev, 0x73, &data);
                pci_write_config_byte(dev, 0x73, data & 0xef);
        }
        return 0;
}

static int pci_siig_init(struct pci_dev *dev)
{
        unsigned int type = dev->device & 0xff00;

        if (type == 0x1000)
                return pci_siig10x_init(dev);
        else if (type == 0x2000)
                return pci_siig20x_init(dev);

        moan_device("Unknown SIIG card", dev);
        return -ENODEV;
}

static int pci_siig_setup(struct serial_private *priv,
                          const struct pciserial_board *board,
                          struct uart_8250_port *port, int idx)
{
        unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;

        if (idx > 3) {
                bar = 4;
                offset = (idx - 4) * 8;
        }

        return setup_port(priv, port, bar, offset, 0);
}

/*
 * Timedia has an explosion of boards, and to avoid the PCI table from
 * growing *huge*, we use this function to collapse some 70 entries
 * in the PCI table into one, for sanity's and compactness's sake.
 */
static const unsigned short timedia_single_port[] = {
        0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
};

static const unsigned short timedia_dual_port[] = {
        0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
        0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
        0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
        0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
        0xD079, 0
};

static const unsigned short timedia_quad_port[] = {
        0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
        0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
        0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
        0xB157, 0
};

static const unsigned short timedia_eight_port[] = {
        0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
        0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
};

static const struct timedia_struct {
        int num;
        const unsigned short *ids;
} timedia_data[] = {
        { 1, timedia_single_port },
        { 2, timedia_dual_port },
        { 4, timedia_quad_port },
        { 8, timedia_eight_port }
};

/*
 * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 * listing them individually, this driver merely grabs them all with
 * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 * and should be left free to be claimed by parport_serial instead.
 */
static int pci_timedia_probe(struct pci_dev *dev)
{
        /*
         * Check the third digit of the subdevice ID
         * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
         */
        if ((dev->subsystem_device & 0x00f0) >= 0x70) {
                dev_info(&dev->dev,
                        "ignoring Timedia subdevice %04x for parport_serial\n",
                        dev->subsystem_device);
                return -ENODEV;
        }

        return 0;
}

static int pci_timedia_init(struct pci_dev *dev)
{
        const unsigned short *ids;
        int i, j;

        for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
                ids = timedia_data[i].ids;
                for (j = 0; ids[j]; j++)
                        if (dev->subsystem_device == ids[j])
                                return timedia_data[i].num;
        }
        return 0;
}

/*
 * Timedia/SUNIX uses a mixture of BARs and offsets
 * Ugh, this is ugly as all hell --- TYT
 */
static int
pci_timedia_setup(struct serial_private *priv,
                  const struct pciserial_board *board,
                  struct uart_8250_port *port, int idx)
{
        unsigned int bar = 0, offset = board->first_offset;

        switch (idx) {
        case 0:
                bar = 0;
                break;
        case 1:
                offset = board->uart_offset;
                bar = 0;
                break;
        case 2:
                bar = 1;
                break;
        case 3:
                offset = board->uart_offset;
                fallthrough;
        case 4: /* BAR 2 */
        case 5: /* BAR 3 */
        case 6: /* BAR 4 */
        case 7: /* BAR 5 */
                bar = idx - 2;
        }

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

/*
 * Some Titan cards are also a little weird
 */
static int
titan_400l_800l_setup(struct serial_private *priv,
                      const struct pciserial_board *board,
                      struct uart_8250_port *port, int idx)
{
        unsigned int bar, offset = board->first_offset;

        switch (idx) {
        case 0:
                bar = 1;
                break;
        case 1:
                bar = 2;
                break;
        default:
                bar = 4;
                offset = (idx - 2) * board->uart_offset;
        }

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

static int pci_xircom_init(struct pci_dev *dev)
{
        msleep(100);
        return 0;
}

static int pci_ni8420_init(struct pci_dev *dev)
{
        void __iomem *p;
        unsigned int bar = 0;

        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
                moan_device("no memory in bar", dev);
                return 0;
        }

        p = pci_ioremap_bar(dev, bar);
        if (p == NULL)
                return -ENOMEM;

        /* Enable CPU Interrupt */
        writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
               p + NI8420_INT_ENABLE_REG);

        iounmap(p);
        return 0;
}

#define MITE_IOWBSR1_WSIZE      0xa
#define MITE_IOWBSR1_WIN_OFFSET 0x800
#define MITE_IOWBSR1_WENAB      (1 << 7)
#define MITE_LCIMR1_IO_IE_0     (1 << 24)
#define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe

static int pci_ni8430_init(struct pci_dev *dev)
{
        void __iomem *p;
        struct pci_bus_region region;
        u32 device_window;
        unsigned int bar = 0;

        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
                moan_device("no memory in bar", dev);
                return 0;
        }

        p = pci_ioremap_bar(dev, bar);
        if (p == NULL)
                return -ENOMEM;

        /*
         * Set device window address and size in BAR0, while acknowledging that
         * the resource structure may contain a translated address that differs
         * from the address the device responds to.
         */
        pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
        device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
                        | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
        writel(device_window, p + MITE_IOWBSR1);

        /* Set window access to go to RAMSEL IO address space */
        writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
               p + MITE_IOWCR1);

        /* Enable IO Bus Interrupt 0 */
        writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);

        /* Enable CPU Interrupt */
        writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);

        iounmap(p);
        return 0;
}

/* UART Port Control Register */
#define NI8430_PORTCON  0x0f
#define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)

static int
pci_ni8430_setup(struct serial_private *priv,
                 const struct pciserial_board *board,
                 struct uart_8250_port *port, int idx)
{
        struct pci_dev *dev = priv->dev;
        void __iomem *p;
        unsigned int bar, offset = board->first_offset;

        if (idx >= board->num_ports)
                return 1;

        bar = FL_GET_BASE(board->flags);
        offset += idx * board->uart_offset;

        p = pci_ioremap_bar(dev, bar);
        if (!p)
                return -ENOMEM;

        /* enable the transceiver */
        writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
               p + offset + NI8430_PORTCON);

        iounmap(p);

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

static int pci_netmos_9900_setup(struct serial_private *priv,
                                const struct pciserial_board *board,
                                struct uart_8250_port *port, int idx)
{
        unsigned int bar;

        if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
            (priv->dev->subsystem_device & 0xff00) == 0x3000) {
                /* netmos apparently orders BARs by datasheet layout, so serial
                 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
                 */
                bar = 3 * idx;

                return setup_port(priv, port, bar, 0, board->reg_shift);
        } else {
                return pci_default_setup(priv, board, port, idx);
        }
}

/* the 99xx series comes with a range of device IDs and a variety
 * of capabilities:
 *
 * 9900 has varying capabilities and can cascade to sub-controllers
 *   (cascading should be purely internal)
 * 9904 is hardwired with 4 serial ports
 * 9912 and 9922 are hardwired with 2 serial ports
 */
static int pci_netmos_9900_numports(struct pci_dev *dev)
{
        unsigned int c = dev->class;
        unsigned int pi;
        unsigned short sub_serports;

        pi = c & 0xff;

        if (pi == 2)
                return 1;

        if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
                /* two possibilities: 0x30ps encodes number of parallel and
                 * serial ports, or 0x1000 indicates *something*. This is not
                 * immediately obvious, since the 2s1p+4s configuration seems
                 * to offer all functionality on functions 0..2, while still
                 * advertising the same function 3 as the 4s+2s1p config.
                 */
                sub_serports = dev->subsystem_device & 0xf;
                if (sub_serports > 0)
                        return sub_serports;

                dev_err(&dev->dev,
                        "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
                return 0;
        }

        moan_device("unknown NetMos/Mostech program interface", dev);
        return 0;
}

static int pci_netmos_init(struct pci_dev *dev)
{
        /* subdevice 0x00PS means <P> parallel, <S> serial */
        unsigned int num_serial = dev->subsystem_device & 0xf;

        if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
                (dev->device == PCI_DEVICE_ID_NETMOS_9865))
                return 0;

        if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
                        dev->subsystem_device == 0x0299)
                return 0;

        switch (dev->device) { /* FALLTHROUGH on all */
        case PCI_DEVICE_ID_NETMOS_9904:
        case PCI_DEVICE_ID_NETMOS_9912:
        case PCI_DEVICE_ID_NETMOS_9922:
        case PCI_DEVICE_ID_NETMOS_9900:
                num_serial = pci_netmos_9900_numports(dev);
                break;

        default:
                break;
        }

        if (num_serial == 0) {
                moan_device("unknown NetMos/Mostech device", dev);
                return -ENODEV;
        }

        return num_serial;
}

/*
 * These chips are available with optionally one parallel port and up to
 * two serial ports. Unfortunately they all have the same product id.
 *
 * Basic configuration is done over a region of 32 I/O ports. The base
 * ioport is called INTA or INTC, depending on docs/other drivers.
 *
 * The region of the 32 I/O ports is configured in POSIO0R...
 */

/* registers */
#define ITE_887x_MISCR          0x9c
#define ITE_887x_INTCBAR        0x78
#define ITE_887x_UARTBAR        0x7c
#define ITE_887x_PS0BAR         0x10
#define ITE_887x_POSIO0         0x60

/* I/O space size */
#define ITE_887x_IOSIZE         32
/* I/O space size (bits 26-24; 8 bytes = 011b) */
#define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
/* I/O space size (bits 26-24; 32 bytes = 101b) */
#define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
#define ITE_887x_POSIO_SPEED            (3 << 29)
/* enable IO_Space bit */
#define ITE_887x_POSIO_ENABLE           (1 << 31)

static int pci_ite887x_init(struct pci_dev *dev)
{
        /* inta_addr are the configuration addresses of the ITE */
        static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
                                                        0x200, 0x280, 0 };
        int ret, i, type;
        struct resource *iobase = NULL;
        u32 miscr, uartbar, ioport;

        /* search for the base-ioport */
        i = 0;
        while (inta_addr[i] && iobase == NULL) {
                iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
                                                                "ite887x");
                if (iobase != NULL) {
                        /* write POSIO0R - speed | size | ioport */
                        pci_write_config_dword(dev, ITE_887x_POSIO0,
                                ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
                                ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
                        /* write INTCBAR - ioport */
                        pci_write_config_dword(dev, ITE_887x_INTCBAR,
                                                                inta_addr[i]);
                        ret = inb(inta_addr[i]);
                        if (ret != 0xff) {
                                /* ioport connected */
                                break;
                        }
                        release_region(iobase->start, ITE_887x_IOSIZE);
                        iobase = NULL;
                }
                i++;
        }

        if (!inta_addr[i]) {
                dev_err(&dev->dev, "ite887x: could not find iobase\n");
                return -ENODEV;
        }

        /* start of undocumented type checking (see parport_pc.c) */
        type = inb(iobase->start + 0x18) & 0x0f;

        switch (type) {
        case 0x2:       /* ITE8871 (1P) */
        case 0xa:       /* ITE8875 (1P) */
                ret = 0;
                break;
        case 0xe:       /* ITE8872 (2S1P) */
                ret = 2;
                break;
        case 0x6:       /* ITE8873 (1S) */
                ret = 1;
                break;
        case 0x8:       /* ITE8874 (2S) */
                ret = 2;
                break;
        default:
                moan_device("Unknown ITE887x", dev);
                ret = -ENODEV;
        }

        /* configure all serial ports */
        for (i = 0; i < ret; i++) {
                /* read the I/O port from the device */
                pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
                                                                &ioport);
                ioport &= 0x0000FF00;   /* the actual base address */
                pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
                        ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
                        ITE_887x_POSIO_IOSIZE_8 | ioport);

                /* write the ioport to the UARTBAR */
                pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
                uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
                uartbar |= (ioport << (16 * i));        /* set the ioport */
                pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);

                /* get current config */
                pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
                /* disable interrupts (UARTx_Routing[3:0]) */
                miscr &= ~(0xf << (12 - 4 * i));
                /* activate the UART (UARTx_En) */
                miscr |= 1 << (23 - i);
                /* write new config with activated UART */
                pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
        }

        if (ret <= 0) {
                /* the device has no UARTs if we get here */
                release_region(iobase->start, ITE_887x_IOSIZE);
        }

        return ret;
}

static void pci_ite887x_exit(struct pci_dev *dev)
{
        u32 ioport;
        /* the ioport is bit 0-15 in POSIO0R */
        pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
        ioport &= 0xffff;
        release_region(ioport, ITE_887x_IOSIZE);

}

/*
 * EndRun Technologies.
 * Determine the number of ports available on the device.
 */
#define PCI_VENDOR_ID_ENDRUN                    0x7401
#define PCI_DEVICE_ID_ENDRUN_1588       0xe100

static int pci_endrun_init(struct pci_dev *dev)
{
        u8 __iomem *p;
        unsigned long deviceID;
        unsigned int  number_uarts = 0;

        /* EndRun device is all 0xexxx */
        if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
                (dev->device & 0xf000) != 0xe000)
                return 0;

        p = pci_iomap(dev, 0, 5);
        if (p == NULL)
                return -ENOMEM;

        deviceID = ioread32(p);
        /* EndRun device */
        if (deviceID == 0x07000200) {
                number_uarts = ioread8(p + 4);
                dev_dbg(&dev->dev,
                        "%d ports detected on EndRun PCI Express device\n",
                        number_uarts);
        }
        pci_iounmap(dev, p);
        return number_uarts;
}

/*
 * Oxford Semiconductor Inc.
 * Check that device is part of the Tornado range of devices, then determine
 * the number of ports available on the device.
 */
static int pci_oxsemi_tornado_init(struct pci_dev *dev)
{
        u8 __iomem *p;
        unsigned long deviceID;
        unsigned int  number_uarts = 0;

        /* OxSemi Tornado devices are all 0xCxxx */
        if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
            (dev->device & 0xF000) != 0xC000)
                return 0;

        p = pci_iomap(dev, 0, 5);
        if (p == NULL)
                return -ENOMEM;

        deviceID = ioread32(p);
        /* Tornado device */
        if (deviceID == 0x07000200) {
                number_uarts = ioread8(p + 4);
                dev_dbg(&dev->dev,
                        "%d ports detected on Oxford PCI Express device\n",
                        number_uarts);
        }
        pci_iounmap(dev, p);
        return number_uarts;
}

static int pci_asix_setup(struct serial_private *priv,
                  const struct pciserial_board *board,
                  struct uart_8250_port *port, int idx)
{
        port->bugs |= UART_BUG_PARITY;
        return pci_default_setup(priv, board, port, idx);
}

/* Quatech devices have their own extra interface features */

struct quatech_feature {
        u16 devid;
        bool amcc;
};

#define QPCR_TEST_FOR1          0x3F
#define QPCR_TEST_GET1          0x00
#define QPCR_TEST_FOR2          0x40
#define QPCR_TEST_GET2          0x40
#define QPCR_TEST_FOR3          0x80
#define QPCR_TEST_GET3          0x40
#define QPCR_TEST_FOR4          0xC0
#define QPCR_TEST_GET4          0x80

#define QOPR_CLOCK_X1           0x0000
#define QOPR_CLOCK_X2           0x0001
#define QOPR_CLOCK_X4           0x0002
#define QOPR_CLOCK_X8           0x0003
#define QOPR_CLOCK_RATE_MASK    0x0003


static struct quatech_feature quatech_cards[] = {
        { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
        { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
        { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
        { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
        { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
        { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
        { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
        { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
        { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
        { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
        { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
        { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
        { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
        { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
        { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
        { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
        { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
        { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
        { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
        { 0, }
};

static int pci_quatech_amcc(u16 devid)
{
        struct quatech_feature *qf = &quatech_cards[0];
        while (qf->devid) {
                if (qf->devid == devid)
                        return qf->amcc;
                qf++;
        }
        pr_err("quatech: unknown port type '0x%04X'.\n", devid);
        return 0;
};

static int pci_quatech_rqopr(struct uart_8250_port *port)
{
        unsigned long base = port->port.iobase;
        u8 LCR, val;

        LCR = inb(base + UART_LCR);
        outb(0xBF, base + UART_LCR);
        val = inb(base + UART_SCR);
        outb(LCR, base + UART_LCR);
        return val;
}

static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
{
        unsigned long base = port->port.iobase;
        u8 LCR;

        LCR = inb(base + UART_LCR);
        outb(0xBF, base + UART_LCR);
        inb(base + UART_SCR);
        outb(qopr, base + UART_SCR);
        outb(LCR, base + UART_LCR);
}

static int pci_quatech_rqmcr(struct uart_8250_port *port)
{
        unsigned long base = port->port.iobase;
        u8 LCR, val, qmcr;

        LCR = inb(base + UART_LCR);
        outb(0xBF, base + UART_LCR);
        val = inb(base + UART_SCR);
        outb(val | 0x10, base + UART_SCR);
        qmcr = inb(base + UART_MCR);
        outb(val, base + UART_SCR);
        outb(LCR, base + UART_LCR);

        return qmcr;
}

static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
{
        unsigned long base = port->port.iobase;
        u8 LCR, val;

        LCR = inb(base + UART_LCR);
        outb(0xBF, base + UART_LCR);
        val = inb(base + UART_SCR);
        outb(val | 0x10, base + UART_SCR);
        outb(qmcr, base + UART_MCR);
        outb(val, base + UART_SCR);
        outb(LCR, base + UART_LCR);
}

static int pci_quatech_has_qmcr(struct uart_8250_port *port)
{
        unsigned long base = port->port.iobase;
        u8 LCR, val;

        LCR = inb(base + UART_LCR);
        outb(0xBF, base + UART_LCR);
        val = inb(base + UART_SCR);
        if (val & 0x20) {
                outb(0x80, UART_LCR);
                if (!(inb(UART_SCR) & 0x20)) {
                        outb(LCR, base + UART_LCR);
                        return 1;
                }
        }
        return 0;
}

static int pci_quatech_test(struct uart_8250_port *port)
{
        u8 reg, qopr;

        qopr = pci_quatech_rqopr(port);
        pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
        reg = pci_quatech_rqopr(port) & 0xC0;
        if (reg != QPCR_TEST_GET1)
                return -EINVAL;
        pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
        reg = pci_quatech_rqopr(port) & 0xC0;
        if (reg != QPCR_TEST_GET2)
                return -EINVAL;
        pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
        reg = pci_quatech_rqopr(port) & 0xC0;
        if (reg != QPCR_TEST_GET3)
                return -EINVAL;
        pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
        reg = pci_quatech_rqopr(port) & 0xC0;
        if (reg != QPCR_TEST_GET4)
                return -EINVAL;

        pci_quatech_wqopr(port, qopr);
        return 0;
}

static int pci_quatech_clock(struct uart_8250_port *port)
{
        u8 qopr, reg, set;
        unsigned long clock;

        if (pci_quatech_test(port) < 0)
                return 1843200;

        qopr = pci_quatech_rqopr(port);

        pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
        reg = pci_quatech_rqopr(port);
        if (reg & QOPR_CLOCK_X8) {
                clock = 1843200;
                goto out;
        }
        pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
        reg = pci_quatech_rqopr(port);
        if (!(reg & QOPR_CLOCK_X8)) {
                clock = 1843200;
                goto out;
        }
        reg &= QOPR_CLOCK_X8;
        if (reg == QOPR_CLOCK_X2) {
                clock =  3685400;
                set = QOPR_CLOCK_X2;
        } else if (reg == QOPR_CLOCK_X4) {
                clock = 7372800;
                set = QOPR_CLOCK_X4;
        } else if (reg == QOPR_CLOCK_X8) {
                clock = 14745600;
                set = QOPR_CLOCK_X8;
        } else {
                clock = 1843200;
                set = QOPR_CLOCK_X1;
        }
        qopr &= ~QOPR_CLOCK_RATE_MASK;
        qopr |= set;

out:
        pci_quatech_wqopr(port, qopr);
        return clock;
}

static int pci_quatech_rs422(struct uart_8250_port *port)
{
        u8 qmcr;
        int rs422 = 0;

        if (!pci_quatech_has_qmcr(port))
                return 0;
        qmcr = pci_quatech_rqmcr(port);
        pci_quatech_wqmcr(port, 0xFF);
        if (pci_quatech_rqmcr(port))
                rs422 = 1;
        pci_quatech_wqmcr(port, qmcr);
        return rs422;
}

static int pci_quatech_init(struct pci_dev *dev)
{
        if (pci_quatech_amcc(dev->device)) {
                unsigned long base = pci_resource_start(dev, 0);
                if (base) {
                        u32 tmp;

                        outl(inl(base + 0x38) | 0x00002000, base + 0x38);
                        tmp = inl(base + 0x3c);
                        outl(tmp | 0x01000000, base + 0x3c);
                        outl(tmp &= ~0x01000000, base + 0x3c);
                }
        }
        return 0;
}

static int pci_quatech_setup(struct serial_private *priv,
                  const struct pciserial_board *board,
                  struct uart_8250_port *port, int idx)
{
        /* Needed by pci_quatech calls below */
        port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
        /* Set up the clocking */
        port->port.uartclk = pci_quatech_clock(port);
        /* For now just warn about RS422 */
        if (pci_quatech_rs422(port))
                pr_warn("quatech: software control of RS422 features not currently supported.\n");
        return pci_default_setup(priv, board, port, idx);
}

static void pci_quatech_exit(struct pci_dev *dev)
{
}

static int pci_default_setup(struct serial_private *priv,
                  const struct pciserial_board *board,
                  struct uart_8250_port *port, int idx)
{
        unsigned int bar, offset = board->first_offset, maxnr;

        bar = FL_GET_BASE(board->flags);
        if (board->flags & FL_BASE_BARS)
                bar += idx;
        else
                offset += idx * board->uart_offset;

        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
                (board->reg_shift + 3);

        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
                return 1;

        return setup_port(priv, port, bar, offset, board->reg_shift);
}
static void
pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
                               unsigned int quot, unsigned int quot_frac)
{
        int scr;
        int lcr;
        int actual_baud;
        int tolerance;

        for (scr = 5 ; scr <= 15 ; scr++) {
                actual_baud = 921600 * 16 / scr;
                tolerance = actual_baud / 50;

                if ((baud < actual_baud + tolerance) &&
                        (baud > actual_baud - tolerance)) {

                        lcr = serial_port_in(port, UART_LCR);
                        serial_port_out(port, UART_LCR, lcr | 0x80);

                        serial_port_out(port, UART_DLL, 1);
                        serial_port_out(port, UART_DLM, 0);
                        serial_port_out(port, 2, 16 - scr);
                        serial_port_out(port, UART_LCR, lcr);
                        return;
                } else if (baud > actual_baud) {
                        break;
                }
        }
        serial8250_do_set_divisor(port, baud, quot, quot_frac);
}
static int pci_pericom_setup(struct serial_private *priv,
                  const struct pciserial_board *board,
                  struct uart_8250_port *port, int idx)
{
        unsigned int bar, offset = board->first_offset, maxnr;

        bar = FL_GET_BASE(board->flags);
        if (board->flags & FL_BASE_BARS)
                bar += idx;
        else
                offset += idx * board->uart_offset;


        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
                (board->reg_shift + 3);

        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
                return 1;

        port->port.set_divisor = pericom_do_set_divisor;

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
                  const struct pciserial_board *board,
                  struct uart_8250_port *port, int idx)
{
        unsigned int bar, offset = board->first_offset, maxnr;

        bar = FL_GET_BASE(board->flags);
        if (board->flags & FL_BASE_BARS)
                bar += idx;
        else
                offset += idx * board->uart_offset;

        if (idx==3)
                offset = 0x38;

        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
                (board->reg_shift + 3);

        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
                return 1;

        port->port.set_divisor = pericom_do_set_divisor;

        return setup_port(priv, port, bar, offset, board->reg_shift);
}

static int
ce4100_serial_setup(struct serial_private *priv,
                  const struct pciserial_board *board,
                  struct uart_8250_port *port, int idx)
{
        int ret;

        ret = setup_port(priv, port, idx, 0, board->reg_shift);
        port->port.iotype = UPIO_MEM32;
        port->port.type = PORT_XSCALE;
        port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
        port->port.regshift = 2;

        return ret;
}

static int
pci_omegapci_setup(struct serial_private *priv,
                      const struct pciserial_board *board,
                      struct uart_8250_port *port, int idx)
{
        return setup_port(priv, port, 2, idx * 8, 0);
}

static int
pci_brcm_trumanage_setup(struct serial_private *priv,
                         const struct pciserial_board *board,
                         struct uart_8250_port *port, int idx)
{
        int ret = pci_default_setup(priv, board, port, idx);

        port->port.type = PORT_BRCM_TRUMANAGE;
        port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
        return ret;
}

/* RTS will control by MCR if this bit is 0 */
#define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
/* only worked with FINTEK_RTS_CONTROL_BY_HW on */
#define FINTEK_RTS_INVERT               BIT(5)

/* We should do proper H/W transceiver setting before change to RS485 mode */
static int pci_fintek_rs485_config(struct uart_port *port,
                               struct serial_rs485 *rs485)
{
        struct pci_dev *pci_dev = to_pci_dev(port->dev);
        u8 setting;
        u8 *index = (u8 *) port->private_data;

        pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);

        if (!rs485)
                rs485 = &port->rs485;
        else if (rs485->flags & SER_RS485_ENABLED)
                memset(rs485->padding, 0, sizeof(rs485->padding));
        else
                memset(rs485, 0, sizeof(*rs485));

        /* F81504/508/512 not support RTS delay before or after send */
        rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;

        if (rs485->flags & SER_RS485_ENABLED) {
                /* Enable RTS H/W control mode */
                setting |= FINTEK_RTS_CONTROL_BY_HW;

                if (rs485->flags & SER_RS485_RTS_ON_SEND) {
                        /* RTS driving high on TX */
                        setting &= ~FINTEK_RTS_INVERT;
                } else {
                        /* RTS driving low on TX */
                        setting |= FINTEK_RTS_INVERT;
                }

                rs485->delay_rts_after_send = 0;
                rs485->delay_rts_before_send = 0;
        } else {
                /* Disable RTS H/W control mode */
                setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
        }

        pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);

        if (rs485 != &port->rs485)
                port->rs485 = *rs485;

        return 0;
}

static int pci_fintek_setup(struct serial_private *priv,
                            const struct pciserial_board *board,
                            struct uart_8250_port *port, int idx)
{
        struct pci_dev *pdev = priv->dev;
        u8 *data;
        u8 config_base;
        u16 iobase;

        config_base = 0x40 + 0x08 * idx;

        /* Get the io address from configuration space */
        pci_read_config_word(pdev, config_base + 4, &iobase);

        dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);

        port->port.iotype = UPIO_PORT;
        port->port.iobase = iobase;
        port->port.rs485_config = pci_fintek_rs485_config;

        data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
        if (!data)
                return -ENOMEM;

        /* preserve index in PCI configuration space */
        *data = idx;
        port->port.private_data = data;

        return 0;
}

static int pci_fintek_init(struct pci_dev *dev)
{
        unsigned long iobase;
        u32 max_port, i;
        resource_size_t bar_data[3];
        u8 config_base;
        struct serial_private *priv = pci_get_drvdata(dev);
        struct uart_8250_port *port;

        if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
                        !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
                        !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
                return -ENODEV;

        switch (dev->device) {
        case 0x1104: /* 4 ports */
        case 0x1108: /* 8 ports */
                max_port = dev->device & 0xff;
                break;
        case 0x1112: /* 12 ports */
                max_port = 12;
                break;
        default:
                return -EINVAL;
        }

        /* Get the io address dispatch from the BIOS */
        bar_data[0] = pci_resource_start(dev, 5);
        bar_data[1] = pci_resource_start(dev, 4);
        bar_data[2] = pci_resource_start(dev, 3);

        for (i = 0; i < max_port; ++i) {
                /* UART0 configuration offset start from 0x40 */
                config_base = 0x40 + 0x08 * i;

                /* Calculate Real IO Port */
                iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;

                /* Enable UART I/O port */
                pci_write_config_byte(dev, config_base + 0x00, 0x01);

                /* Select 128-byte FIFO and 8x FIFO threshold */
                pci_write_config_byte(dev, config_base + 0x01, 0x33);

                /* LSB UART */
                pci_write_config_byte(dev, config_base + 0x04,
                                (u8)(iobase & 0xff));

                /* MSB UART */
                pci_write_config_byte(dev, config_base + 0x05,
                                (u8)((iobase & 0xff00) >> 8));

                pci_write_config_byte(dev, config_base + 0x06, dev->irq);

                if (priv) {
                        /* re-apply RS232/485 mode when
                         * pciserial_resume_ports()
                         */
                        port = serial8250_get_port(priv->line[i]);
                        pci_fintek_rs485_config(&port->port, NULL);
                } else {
                        /* First init without port data
                         * force init to RS232 Mode
                         */
                        pci_write_config_byte(dev, config_base + 0x07, 0x01);
                }
        }

        return max_port;
}

static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
{
        struct f815xxa_data *data = p->private_data;
        unsigned long flags;

        spin_lock_irqsave(&data->lock, flags);
        writeb(value, p->membase + offset);
        readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
        spin_unlock_irqrestore(&data->lock, flags);
}

static int pci_fintek_f815xxa_setup(struct serial_private *priv,
                            const struct pciserial_board *board,
                            struct uart_8250_port *port, int idx)
{
        struct pci_dev *pdev = priv->dev;
        struct f815xxa_data *data;

        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
        if (!data)
                return -ENOMEM;

        data->idx = idx;
        spin_lock_init(&data->lock);

        port->port.private_data = data;
        port->port.iotype = UPIO_MEM;
        port->port.flags |= UPF_IOREMAP;
        port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
        port->port.serial_out = f815xxa_mem_serial_out;

        return 0;
}

static int pci_fintek_f815xxa_init(struct pci_dev *dev)
{
        u32 max_port, i;
        int config_base;

        if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
                return -ENODEV;

        switch (dev->device) {
        case 0x1204: /* 4 ports */
        case 0x1208: /* 8 ports */
                max_port = dev->device & 0xff;
                break;
        case 0x1212: /* 12 ports */
                max_port = 12;
                break;
        default:
                return -EINVAL;
        }

        /* Set to mmio decode */
        pci_write_config_byte(dev, 0x209, 0x40);

        for (i = 0; i < max_port; ++i) {
                /* UART0 configuration offset start from 0x2A0 */
                config_base = 0x2A0 + 0x08 * i;

                /* Select 128-byte FIFO and 8x FIFO threshold */
                pci_write_config_byte(dev, config_base + 0x01, 0x33);

                /* Enable UART I/O port */
                pci_write_config_byte(dev, config_base + 0, 0x01);
        }

        return max_port;
}

static int skip_tx_en_setup(struct serial_private *priv,
                        const struct pciserial_board *board,
                        struct uart_8250_port *port, int idx)
{
        port->port.quirks |= UPQ_NO_TXEN_TEST;
        dev_dbg(&priv->dev->dev,
                "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
                priv->dev->vendor, priv->dev->device,
                priv->dev->subsystem_vendor, priv->dev->subsystem_device);

        return pci_default_setup(priv, board, port, idx);
}

static void kt_handle_break(struct uart_port *p)
{
        struct uart_8250_port *up = up_to_u8250p(p);
        /*
         * On receipt of a BI, serial device in Intel ME (Intel
         * management engine) needs to have its fifos cleared for sane
         * SOL (Serial Over Lan) output.
         */
        serial8250_clear_and_reinit_fifos(up);
}

static unsigned int kt_serial_in(struct uart_port *p, int offset)
{
        struct uart_8250_port *up = up_to_u8250p(p);
        unsigned int val;

        /*
         * When the Intel ME (management engine) gets reset its serial
         * port registers could return 0 momentarily.  Functions like
         * serial8250_console_write, read and save the IER, perform
         * some operation and then restore it.  In order to avoid
         * setting IER register inadvertently to 0, if the value read
         * is 0, double check with ier value in uart_8250_port and use
         * that instead.  up->ier should be the same value as what is
         * currently configured.
         */
        val = inb(p->iobase + offset);
        if (offset == UART_IER) {
                if (val == 0)
                        val = up->ier;
        }
        return val;
}

static int kt_serial_setup(struct serial_private *priv,
                           const struct pciserial_board *board,
                           struct uart_8250_port *port, int idx)
{
        port->port.flags |= UPF_BUG_THRE;
        port->port.serial_in = kt_serial_in;
        port->port.handle_break = kt_handle_break;
        return skip_tx_en_setup(priv, board, port, idx);
}

static int pci_eg20t_init(struct pci_dev *dev)
{
#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
        return -ENODEV;
#else
        return 0;
#endif
}

static int
pci_wch_ch353_setup(struct serial_private *priv,
                    const struct pciserial_board *board,
                    struct uart_8250_port *port, int idx)
{
        port->port.flags |= UPF_FIXED_TYPE;
        port->port.type = PORT_16550A;
        return pci_default_setup(priv, board, port, idx);
}

static int
pci_wch_ch355_setup(struct serial_private *priv,
                const struct pciserial_board *board,
                struct uart_8250_port *port, int idx)
{
        port->port.flags |= UPF_FIXED_TYPE;
        port->port.type = PORT_16550A;
        return pci_default_setup(priv, board, port, idx);
}

static int
pci_wch_ch38x_setup(struct serial_private *priv,
                    const struct pciserial_board *board,
                    struct uart_8250_port *port, int idx)
{
        port->port.flags |= UPF_FIXED_TYPE;
        port->port.type = PORT_16850;
        return pci_default_setup(priv, board, port, idx);
}


#define CH384_XINT_ENABLE_REG   0xEB
#define CH384_XINT_ENABLE_BIT   0x02

static int pci_wch_ch38x_init(struct pci_dev *dev)
{
        int max_port;
        unsigned long iobase;


        switch (dev->device) {
        case 0x3853: /* 8 ports */
                max_port = 8;
                break;
        default:
                return -EINVAL;
        }

        iobase = pci_resource_start(dev, 0);
        outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);

        return max_port;
}

static void pci_wch_ch38x_exit(struct pci_dev *dev)
{
        unsigned long iobase;

        iobase = pci_resource_start(dev, 0);
        outb(0x0, iobase + CH384_XINT_ENABLE_REG);
}


static int
pci_sunix_setup(struct serial_private *priv,
                const struct pciserial_board *board,
                struct uart_8250_port *port, int idx)
{
        int bar;
        int offset;

        port->port.flags |= UPF_FIXED_TYPE;
        port->port.type = PORT_SUNIX;

        if (idx < 4) {
                bar = 0;
                offset = idx * board->uart_offset;
        } else {
                bar = 1;
                idx -= 4;
                idx = div_s64_rem(idx, 4, &offset);
                offset = idx * 64 + offset * board->uart_offset;
        }

        return setup_port(priv, port, bar, offset, 0);
}

static int
pci_moxa_setup(struct serial_private *priv,
                const struct pciserial_board *board,
                struct uart_8250_port *port, int idx)
{
        unsigned int bar = FL_GET_BASE(board->flags);
        int offset;

        if (board->num_ports == 4 && idx == 3)
                offset = 7 * board->uart_offset;
        else
                offset = idx * board->uart_offset;

        return setup_port(priv, port, bar, offset, 0);
}

#define PCI_VENDOR_ID_SBSMODULARIO      0x124B
#define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
#define PCI_DEVICE_ID_OCTPRO            0x0001
#define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
#define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
#define PCI_SUBDEVICE_ID_POCTAL232      0x0308
#define PCI_SUBDEVICE_ID_POCTAL422      0x0408
#define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
#define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
#define PCI_VENDOR_ID_ADVANTECH         0x13fe
#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
#define PCI_DEVICE_ID_TITAN_200I        0x8028
#define PCI_DEVICE_ID_TITAN_400I        0x8048
#define PCI_DEVICE_ID_TITAN_800I        0x8088
#define PCI_DEVICE_ID_TITAN_800EH       0xA007
#define PCI_DEVICE_ID_TITAN_800EHB      0xA008
#define PCI_DEVICE_ID_TITAN_400EH       0xA009
#define PCI_DEVICE_ID_TITAN_100E        0xA010
#define PCI_DEVICE_ID_TITAN_200E        0xA012
#define PCI_DEVICE_ID_TITAN_400E        0xA013
#define PCI_DEVICE_ID_TITAN_800E        0xA014
#define PCI_DEVICE_ID_TITAN_200EI       0xA016
#define PCI_DEVICE_ID_TITAN_200EISI     0xA017
#define PCI_DEVICE_ID_TITAN_200V3       0xA306
#define PCI_DEVICE_ID_TITAN_400V3       0xA310
#define PCI_DEVICE_ID_TITAN_410V3       0xA312
#define PCI_DEVICE_ID_TITAN_800V3       0xA314
#define PCI_DEVICE_ID_TITAN_800V3B      0xA315
#define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
#define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
#define PCI_VENDOR_ID_WCH               0x4348
#define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
#define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
#define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
#define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
#define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
#define PCI_DEVICE_ID_WCH_CH355_4S      0x7173
#define PCI_VENDOR_ID_AGESTAR           0x5372
#define PCI_DEVICE_ID_AGESTAR_9375      0x6872
#define PCI_VENDOR_ID_ASIX              0x9710
#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e

#define PCIE_VENDOR_ID_WCH              0x1c00
#define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
#define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
#define PCIE_DEVICE_ID_WCH_CH384_8S     0x3853
#define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253

#define PCI_VENDOR_ID_ACCESIO                   0x494f
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB     0x1051
#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S      0x1053
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB     0x105C
#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S      0x105E
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB   0x1091
#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2    0x1093
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB   0x1099
#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4    0x109B
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB    0x10D1
#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM     0x10D3
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB    0x10DA
#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM     0x10DC
#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1    0x1108
#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2    0x1110
#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2    0x1111
#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4    0x1118
#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4    0x1119
#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S       0x1152
#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S       0x115A
#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2     0x1190
#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2    0x1191
#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4     0x1198
#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4    0x1199
#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM      0x11D0
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4     0x105A
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4     0x105B
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8     0x106A
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8     0x106B
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4     0x1098
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8     0x10A9
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM      0x10D9
#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM      0x10E9
#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM      0x11D8


#define PCI_DEVICE_ID_MOXA_CP102E       0x1024
#define PCI_DEVICE_ID_MOXA_CP102EL      0x1025
#define PCI_DEVICE_ID_MOXA_CP104EL_A    0x1045
#define PCI_DEVICE_ID_MOXA_CP114EL      0x1144
#define PCI_DEVICE_ID_MOXA_CP116E_A_A   0x1160
#define PCI_DEVICE_ID_MOXA_CP116E_A_B   0x1161
#define PCI_DEVICE_ID_MOXA_CP118EL_A    0x1182
#define PCI_DEVICE_ID_MOXA_CP118E_A_I   0x1183
#define PCI_DEVICE_ID_MOXA_CP132EL      0x1322
#define PCI_DEVICE_ID_MOXA_CP134EL_A    0x1342
#define PCI_DEVICE_ID_MOXA_CP138E_A     0x1381
#define PCI_DEVICE_ID_MOXA_CP168EL_A    0x1683

/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588

/*
 * Master list of serial port init/setup/exit quirks.
 * This does not describe the general nature of the port.
 * (ie, baud base, number and location of ports, etc)
 *
 * This list is ordered alphabetically by vendor then device.
 * Specific entries must come before more generic entries.
 */
static struct pci_serial_quirk pci_serial_quirks[] = {
        /*
        * ADDI-DATA GmbH communication cards <info@addi-data.com>
        */
        {
                .vendor         = PCI_VENDOR_ID_AMCC,
                .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
                .subvendor      = PCI_ANY_ID,
                .subdevice      = PCI_ANY_ID,
                .setup          = addidata_apci7800_setup,
        },
        /*
         * AFAVLAB cards - these may be called via parport_serial
         *  It is not clear whether this applies to all products.
         */
        {
                .vendor         = PCI_VENDOR_ID_AFAVLAB,
                .device         = PCI_ANY_ID,
                .subvendor      = PCI_ANY_ID,
                .subdevice      = PCI_ANY_ID,
                .setup          = afavlab_setup,
        },
        /*
         * HP Diva
         */
        {
                .vendor         = PCI_VENDOR_ID_HP,
                .device         = PCI_DEVICE_ID_HP_DIVA,
                .subvendor      = PCI_ANY_ID,
                .subdevice      = PCI_ANY_ID,