linux/drivers/tty/serial/8250/8250_pci.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 *  Probe module for 8250/16550-type PCI serial ports.
   4 *
   5 *  Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
   6 *
   7 *  Copyright (C) 2001 Russell King, All Rights Reserved.
   8 */
   9#undef DEBUG
  10#include <linux/module.h>
  11#include <linux/pci.h>
  12#include <linux/string.h>
  13#include <linux/kernel.h>
  14#include <linux/slab.h>
  15#include <linux/delay.h>
  16#include <linux/tty.h>
  17#include <linux/serial_reg.h>
  18#include <linux/serial_core.h>
  19#include <linux/8250_pci.h>
  20#include <linux/bitops.h>
  21
  22#include <asm/byteorder.h>
  23#include <asm/io.h>
  24
  25#include "8250.h"
  26
  27/*
  28 * init function returns:
  29 *  > 0 - number of ports
  30 *  = 0 - use board->num_ports
  31 *  < 0 - error
  32 */
  33struct pci_serial_quirk {
  34        u32     vendor;
  35        u32     device;
  36        u32     subvendor;
  37        u32     subdevice;
  38        int     (*probe)(struct pci_dev *dev);
  39        int     (*init)(struct pci_dev *dev);
  40        int     (*setup)(struct serial_private *,
  41                         const struct pciserial_board *,
  42                         struct uart_8250_port *, int);
  43        void    (*exit)(struct pci_dev *dev);
  44};
  45
  46struct f815xxa_data {
  47        spinlock_t lock;
  48        int idx;
  49};
  50
  51struct serial_private {
  52        struct pci_dev          *dev;
  53        unsigned int            nr;
  54        struct pci_serial_quirk *quirk;
  55        const struct pciserial_board *board;
  56        int                     line[];
  57};
  58
  59#define PCI_DEVICE_ID_HPE_PCI_SERIAL    0x37e
  60
  61static const struct pci_device_id pci_use_msi[] = {
  62        { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9900,
  63                         0xA000, 0x1000) },
  64        { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9912,
  65                         0xA000, 0x1000) },
  66        { PCI_DEVICE_SUB(PCI_VENDOR_ID_NETMOS, PCI_DEVICE_ID_NETMOS_9922,
  67                         0xA000, 0x1000) },
  68        { PCI_DEVICE_SUB(PCI_VENDOR_ID_HP_3PAR, PCI_DEVICE_ID_HPE_PCI_SERIAL,
  69                         PCI_ANY_ID, PCI_ANY_ID) },
  70        { }
  71};
  72
  73static int pci_default_setup(struct serial_private*,
  74          const struct pciserial_board*, struct uart_8250_port *, int);
  75
  76static void moan_device(const char *str, struct pci_dev *dev)
  77{
  78        dev_err(&dev->dev,
  79               "%s: %s\n"
  80               "Please send the output of lspci -vv, this\n"
  81               "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
  82               "manufacturer and name of serial board or\n"
  83               "modem board to <linux-serial@vger.kernel.org>.\n",
  84               pci_name(dev), str, dev->vendor, dev->device,
  85               dev->subsystem_vendor, dev->subsystem_device);
  86}
  87
  88static int
  89setup_port(struct serial_private *priv, struct uart_8250_port *port,
  90           int bar, int offset, int regshift)
  91{
  92        struct pci_dev *dev = priv->dev;
  93
  94        if (bar >= PCI_STD_NUM_BARS)
  95                return -EINVAL;
  96
  97        if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
  98                if (!pcim_iomap(dev, bar, 0) && !pcim_iomap_table(dev))
  99                        return -ENOMEM;
 100
 101                port->port.iotype = UPIO_MEM;
 102                port->port.iobase = 0;
 103                port->port.mapbase = pci_resource_start(dev, bar) + offset;
 104                port->port.membase = pcim_iomap_table(dev)[bar] + offset;
 105                port->port.regshift = regshift;
 106        } else {
 107                port->port.iotype = UPIO_PORT;
 108                port->port.iobase = pci_resource_start(dev, bar) + offset;
 109                port->port.mapbase = 0;
 110                port->port.membase = NULL;
 111                port->port.regshift = 0;
 112        }
 113        return 0;
 114}
 115
 116/*
 117 * ADDI-DATA GmbH communication cards <info@addi-data.com>
 118 */
 119static int addidata_apci7800_setup(struct serial_private *priv,
 120                                const struct pciserial_board *board,
 121                                struct uart_8250_port *port, int idx)
 122{
 123        unsigned int bar = 0, offset = board->first_offset;
 124        bar = FL_GET_BASE(board->flags);
 125
 126        if (idx < 2) {
 127                offset += idx * board->uart_offset;
 128        } else if ((idx >= 2) && (idx < 4)) {
 129                bar += 1;
 130                offset += ((idx - 2) * board->uart_offset);
 131        } else if ((idx >= 4) && (idx < 6)) {
 132                bar += 2;
 133                offset += ((idx - 4) * board->uart_offset);
 134        } else if (idx >= 6) {
 135                bar += 3;
 136                offset += ((idx - 6) * board->uart_offset);
 137        }
 138
 139        return setup_port(priv, port, bar, offset, board->reg_shift);
 140}
 141
 142/*
 143 * AFAVLAB uses a different mixture of BARs and offsets
 144 * Not that ugly ;) -- HW
 145 */
 146static int
 147afavlab_setup(struct serial_private *priv, const struct pciserial_board *board,
 148              struct uart_8250_port *port, int idx)
 149{
 150        unsigned int bar, offset = board->first_offset;
 151
 152        bar = FL_GET_BASE(board->flags);
 153        if (idx < 4)
 154                bar += idx;
 155        else {
 156                bar = 4;
 157                offset += (idx - 4) * board->uart_offset;
 158        }
 159
 160        return setup_port(priv, port, bar, offset, board->reg_shift);
 161}
 162
 163/*
 164 * HP's Remote Management Console.  The Diva chip came in several
 165 * different versions.  N-class, L2000 and A500 have two Diva chips, each
 166 * with 3 UARTs (the third UART on the second chip is unused).  Superdome
 167 * and Keystone have one Diva chip with 3 UARTs.  Some later machines have
 168 * one Diva chip, but it has been expanded to 5 UARTs.
 169 */
 170static int pci_hp_diva_init(struct pci_dev *dev)
 171{
 172        int rc = 0;
 173
 174        switch (dev->subsystem_device) {
 175        case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
 176        case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
 177        case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
 178        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 179                rc = 3;
 180                break;
 181        case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
 182                rc = 2;
 183                break;
 184        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 185                rc = 4;
 186                break;
 187        case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
 188        case PCI_DEVICE_ID_HP_DIVA_HURRICANE:
 189                rc = 1;
 190                break;
 191        }
 192
 193        return rc;
 194}
 195
 196/*
 197 * HP's Diva chip puts the 4th/5th serial port further out, and
 198 * some serial ports are supposed to be hidden on certain models.
 199 */
 200static int
 201pci_hp_diva_setup(struct serial_private *priv,
 202                const struct pciserial_board *board,
 203                struct uart_8250_port *port, int idx)
 204{
 205        unsigned int offset = board->first_offset;
 206        unsigned int bar = FL_GET_BASE(board->flags);
 207
 208        switch (priv->dev->subsystem_device) {
 209        case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
 210                if (idx == 3)
 211                        idx++;
 212                break;
 213        case PCI_DEVICE_ID_HP_DIVA_EVEREST:
 214                if (idx > 0)
 215                        idx++;
 216                if (idx > 2)
 217                        idx++;
 218                break;
 219        }
 220        if (idx > 2)
 221                offset = 0x18;
 222
 223        offset += idx * board->uart_offset;
 224
 225        return setup_port(priv, port, bar, offset, board->reg_shift);
 226}
 227
 228/*
 229 * Added for EKF Intel i960 serial boards
 230 */
 231static int pci_inteli960ni_init(struct pci_dev *dev)
 232{
 233        u32 oldval;
 234
 235        if (!(dev->subsystem_device & 0x1000))
 236                return -ENODEV;
 237
 238        /* is firmware started? */
 239        pci_read_config_dword(dev, 0x44, &oldval);
 240        if (oldval == 0x00001000L) { /* RESET value */
 241                dev_dbg(&dev->dev, "Local i960 firmware missing\n");
 242                return -ENODEV;
 243        }
 244        return 0;
 245}
 246
 247/*
 248 * Some PCI serial cards using the PLX 9050 PCI interface chip require
 249 * that the card interrupt be explicitly enabled or disabled.  This
 250 * seems to be mainly needed on card using the PLX which also use I/O
 251 * mapped memory.
 252 */
 253static int pci_plx9050_init(struct pci_dev *dev)
 254{
 255        u8 irq_config;
 256        void __iomem *p;
 257
 258        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
 259                moan_device("no memory in bar 0", dev);
 260                return 0;
 261        }
 262
 263        irq_config = 0x41;
 264        if (dev->vendor == PCI_VENDOR_ID_PANACOM ||
 265            dev->subsystem_vendor == PCI_SUBVENDOR_ID_EXSYS)
 266                irq_config = 0x43;
 267
 268        if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
 269            (dev->device == PCI_DEVICE_ID_PLX_ROMULUS))
 270                /*
 271                 * As the megawolf cards have the int pins active
 272                 * high, and have 2 UART chips, both ints must be
 273                 * enabled on the 9050. Also, the UARTS are set in
 274                 * 16450 mode by default, so we have to enable the
 275                 * 16C950 'enhanced' mode so that we can use the
 276                 * deep FIFOs
 277                 */
 278                irq_config = 0x5b;
 279        /*
 280         * enable/disable interrupts
 281         */
 282        p = ioremap(pci_resource_start(dev, 0), 0x80);
 283        if (p == NULL)
 284                return -ENOMEM;
 285        writel(irq_config, p + 0x4c);
 286
 287        /*
 288         * Read the register back to ensure that it took effect.
 289         */
 290        readl(p + 0x4c);
 291        iounmap(p);
 292
 293        return 0;
 294}
 295
 296static void pci_plx9050_exit(struct pci_dev *dev)
 297{
 298        u8 __iomem *p;
 299
 300        if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
 301                return;
 302
 303        /*
 304         * disable interrupts
 305         */
 306        p = ioremap(pci_resource_start(dev, 0), 0x80);
 307        if (p != NULL) {
 308                writel(0, p + 0x4c);
 309
 310                /*
 311                 * Read the register back to ensure that it took effect.
 312                 */
 313                readl(p + 0x4c);
 314                iounmap(p);
 315        }
 316}
 317
 318#define NI8420_INT_ENABLE_REG   0x38
 319#define NI8420_INT_ENABLE_BIT   0x2000
 320
 321static void pci_ni8420_exit(struct pci_dev *dev)
 322{
 323        void __iomem *p;
 324        unsigned int bar = 0;
 325
 326        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 327                moan_device("no memory in bar", dev);
 328                return;
 329        }
 330
 331        p = pci_ioremap_bar(dev, bar);
 332        if (p == NULL)
 333                return;
 334
 335        /* Disable the CPU Interrupt */
 336        writel(readl(p + NI8420_INT_ENABLE_REG) & ~(NI8420_INT_ENABLE_BIT),
 337               p + NI8420_INT_ENABLE_REG);
 338        iounmap(p);
 339}
 340
 341
 342/* MITE registers */
 343#define MITE_IOWBSR1    0xc4
 344#define MITE_IOWCR1     0xf4
 345#define MITE_LCIMR1     0x08
 346#define MITE_LCIMR2     0x10
 347
 348#define MITE_LCIMR2_CLR_CPU_IE  (1 << 30)
 349
 350static void pci_ni8430_exit(struct pci_dev *dev)
 351{
 352        void __iomem *p;
 353        unsigned int bar = 0;
 354
 355        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 356                moan_device("no memory in bar", dev);
 357                return;
 358        }
 359
 360        p = pci_ioremap_bar(dev, bar);
 361        if (p == NULL)
 362                return;
 363
 364        /* Disable the CPU Interrupt */
 365        writel(MITE_LCIMR2_CLR_CPU_IE, p + MITE_LCIMR2);
 366        iounmap(p);
 367}
 368
 369/* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
 370static int
 371sbs_setup(struct serial_private *priv, const struct pciserial_board *board,
 372                struct uart_8250_port *port, int idx)
 373{
 374        unsigned int bar, offset = board->first_offset;
 375
 376        bar = 0;
 377
 378        if (idx < 4) {
 379                /* first four channels map to 0, 0x100, 0x200, 0x300 */
 380                offset += idx * board->uart_offset;
 381        } else if (idx < 8) {
 382                /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
 383                offset += idx * board->uart_offset + 0xC00;
 384        } else /* we have only 8 ports on PMC-OCTALPRO */
 385                return 1;
 386
 387        return setup_port(priv, port, bar, offset, board->reg_shift);
 388}
 389
 390/*
 391* This does initialization for PMC OCTALPRO cards:
 392* maps the device memory, resets the UARTs (needed, bc
 393* if the module is removed and inserted again, the card
 394* is in the sleep mode) and enables global interrupt.
 395*/
 396
 397/* global control register offset for SBS PMC-OctalPro */
 398#define OCT_REG_CR_OFF          0x500
 399
 400static int sbs_init(struct pci_dev *dev)
 401{
 402        u8 __iomem *p;
 403
 404        p = pci_ioremap_bar(dev, 0);
 405
 406        if (p == NULL)
 407                return -ENOMEM;
 408        /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
 409        writeb(0x10, p + OCT_REG_CR_OFF);
 410        udelay(50);
 411        writeb(0x0, p + OCT_REG_CR_OFF);
 412
 413        /* Set bit-2 (INTENABLE) of Control Register */
 414        writeb(0x4, p + OCT_REG_CR_OFF);
 415        iounmap(p);
 416
 417        return 0;
 418}
 419
 420/*
 421 * Disables the global interrupt of PMC-OctalPro
 422 */
 423
 424static void sbs_exit(struct pci_dev *dev)
 425{
 426        u8 __iomem *p;
 427
 428        p = pci_ioremap_bar(dev, 0);
 429        /* FIXME: What if resource_len < OCT_REG_CR_OFF */
 430        if (p != NULL)
 431                writeb(0, p + OCT_REG_CR_OFF);
 432        iounmap(p);
 433}
 434
 435/*
 436 * SIIG serial cards have an PCI interface chip which also controls
 437 * the UART clocking frequency. Each UART can be clocked independently
 438 * (except cards equipped with 4 UARTs) and initial clocking settings
 439 * are stored in the EEPROM chip. It can cause problems because this
 440 * version of serial driver doesn't support differently clocked UART's
 441 * on single PCI card. To prevent this, initialization functions set
 442 * high frequency clocking for all UART's on given card. It is safe (I
 443 * hope) because it doesn't touch EEPROM settings to prevent conflicts
 444 * with other OSes (like M$ DOS).
 445 *
 446 *  SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
 447 *
 448 * There is two family of SIIG serial cards with different PCI
 449 * interface chip and different configuration methods:
 450 *     - 10x cards have control registers in IO and/or memory space;
 451 *     - 20x cards have control registers in standard PCI configuration space.
 452 *
 453 * Note: all 10x cards have PCI device ids 0x10..
 454 *       all 20x cards have PCI device ids 0x20..
 455 *
 456 * There are also Quartet Serial cards which use Oxford Semiconductor
 457 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
 458 *
 459 * Note: some SIIG cards are probed by the parport_serial object.
 460 */
 461
 462#define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
 463#define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
 464
 465static int pci_siig10x_init(struct pci_dev *dev)
 466{
 467        u16 data;
 468        void __iomem *p;
 469
 470        switch (dev->device & 0xfff8) {
 471        case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
 472                data = 0xffdf;
 473                break;
 474        case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
 475                data = 0xf7ff;
 476                break;
 477        default:                        /* 1S1P, 4S */
 478                data = 0xfffb;
 479                break;
 480        }
 481
 482        p = ioremap(pci_resource_start(dev, 0), 0x80);
 483        if (p == NULL)
 484                return -ENOMEM;
 485
 486        writew(readw(p + 0x28) & data, p + 0x28);
 487        readw(p + 0x28);
 488        iounmap(p);
 489        return 0;
 490}
 491
 492#define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
 493#define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
 494
 495static int pci_siig20x_init(struct pci_dev *dev)
 496{
 497        u8 data;
 498
 499        /* Change clock frequency for the first UART. */
 500        pci_read_config_byte(dev, 0x6f, &data);
 501        pci_write_config_byte(dev, 0x6f, data & 0xef);
 502
 503        /* If this card has 2 UART, we have to do the same with second UART. */
 504        if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
 505            ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
 506                pci_read_config_byte(dev, 0x73, &data);
 507                pci_write_config_byte(dev, 0x73, data & 0xef);
 508        }
 509        return 0;
 510}
 511
 512static int pci_siig_init(struct pci_dev *dev)
 513{
 514        unsigned int type = dev->device & 0xff00;
 515
 516        if (type == 0x1000)
 517                return pci_siig10x_init(dev);
 518        else if (type == 0x2000)
 519                return pci_siig20x_init(dev);
 520
 521        moan_device("Unknown SIIG card", dev);
 522        return -ENODEV;
 523}
 524
 525static int pci_siig_setup(struct serial_private *priv,
 526                          const struct pciserial_board *board,
 527                          struct uart_8250_port *port, int idx)
 528{
 529        unsigned int bar = FL_GET_BASE(board->flags) + idx, offset = 0;
 530
 531        if (idx > 3) {
 532                bar = 4;
 533                offset = (idx - 4) * 8;
 534        }
 535
 536        return setup_port(priv, port, bar, offset, 0);
 537}
 538
 539/*
 540 * Timedia has an explosion of boards, and to avoid the PCI table from
 541 * growing *huge*, we use this function to collapse some 70 entries
 542 * in the PCI table into one, for sanity's and compactness's sake.
 543 */
 544static const unsigned short timedia_single_port[] = {
 545        0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
 546};
 547
 548static const unsigned short timedia_dual_port[] = {
 549        0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
 550        0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
 551        0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
 552        0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
 553        0xD079, 0
 554};
 555
 556static const unsigned short timedia_quad_port[] = {
 557        0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
 558        0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
 559        0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
 560        0xB157, 0
 561};
 562
 563static const unsigned short timedia_eight_port[] = {
 564        0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
 565        0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
 566};
 567
 568static const struct timedia_struct {
 569        int num;
 570        const unsigned short *ids;
 571} timedia_data[] = {
 572        { 1, timedia_single_port },
 573        { 2, timedia_dual_port },
 574        { 4, timedia_quad_port },
 575        { 8, timedia_eight_port }
 576};
 577
 578/*
 579 * There are nearly 70 different Timedia/SUNIX PCI serial devices.  Instead of
 580 * listing them individually, this driver merely grabs them all with
 581 * PCI_ANY_ID.  Some of these devices, however, also feature a parallel port,
 582 * and should be left free to be claimed by parport_serial instead.
 583 */
 584static int pci_timedia_probe(struct pci_dev *dev)
 585{
 586        /*
 587         * Check the third digit of the subdevice ID
 588         * (0,2,3,5,6: serial only -- 7,8,9: serial + parallel)
 589         */
 590        if ((dev->subsystem_device & 0x00f0) >= 0x70) {
 591                dev_info(&dev->dev,
 592                        "ignoring Timedia subdevice %04x for parport_serial\n",
 593                        dev->subsystem_device);
 594                return -ENODEV;
 595        }
 596
 597        return 0;
 598}
 599
 600static int pci_timedia_init(struct pci_dev *dev)
 601{
 602        const unsigned short *ids;
 603        int i, j;
 604
 605        for (i = 0; i < ARRAY_SIZE(timedia_data); i++) {
 606                ids = timedia_data[i].ids;
 607                for (j = 0; ids[j]; j++)
 608                        if (dev->subsystem_device == ids[j])
 609                                return timedia_data[i].num;
 610        }
 611        return 0;
 612}
 613
 614/*
 615 * Timedia/SUNIX uses a mixture of BARs and offsets
 616 * Ugh, this is ugly as all hell --- TYT
 617 */
 618static int
 619pci_timedia_setup(struct serial_private *priv,
 620                  const struct pciserial_board *board,
 621                  struct uart_8250_port *port, int idx)
 622{
 623        unsigned int bar = 0, offset = board->first_offset;
 624
 625        switch (idx) {
 626        case 0:
 627                bar = 0;
 628                break;
 629        case 1:
 630                offset = board->uart_offset;
 631                bar = 0;
 632                break;
 633        case 2:
 634                bar = 1;
 635                break;
 636        case 3:
 637                offset = board->uart_offset;
 638                fallthrough;
 639        case 4: /* BAR 2 */
 640        case 5: /* BAR 3 */
 641        case 6: /* BAR 4 */
 642        case 7: /* BAR 5 */
 643                bar = idx - 2;
 644        }
 645
 646        return setup_port(priv, port, bar, offset, board->reg_shift);
 647}
 648
 649/*
 650 * Some Titan cards are also a little weird
 651 */
 652static int
 653titan_400l_800l_setup(struct serial_private *priv,
 654                      const struct pciserial_board *board,
 655                      struct uart_8250_port *port, int idx)
 656{
 657        unsigned int bar, offset = board->first_offset;
 658
 659        switch (idx) {
 660        case 0:
 661                bar = 1;
 662                break;
 663        case 1:
 664                bar = 2;
 665                break;
 666        default:
 667                bar = 4;
 668                offset = (idx - 2) * board->uart_offset;
 669        }
 670
 671        return setup_port(priv, port, bar, offset, board->reg_shift);
 672}
 673
 674static int pci_xircom_init(struct pci_dev *dev)
 675{
 676        msleep(100);
 677        return 0;
 678}
 679
 680static int pci_ni8420_init(struct pci_dev *dev)
 681{
 682        void __iomem *p;
 683        unsigned int bar = 0;
 684
 685        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 686                moan_device("no memory in bar", dev);
 687                return 0;
 688        }
 689
 690        p = pci_ioremap_bar(dev, bar);
 691        if (p == NULL)
 692                return -ENOMEM;
 693
 694        /* Enable CPU Interrupt */
 695        writel(readl(p + NI8420_INT_ENABLE_REG) | NI8420_INT_ENABLE_BIT,
 696               p + NI8420_INT_ENABLE_REG);
 697
 698        iounmap(p);
 699        return 0;
 700}
 701
 702#define MITE_IOWBSR1_WSIZE      0xa
 703#define MITE_IOWBSR1_WIN_OFFSET 0x800
 704#define MITE_IOWBSR1_WENAB      (1 << 7)
 705#define MITE_LCIMR1_IO_IE_0     (1 << 24)
 706#define MITE_LCIMR2_SET_CPU_IE  (1 << 31)
 707#define MITE_IOWCR1_RAMSEL_MASK 0xfffffffe
 708
 709static int pci_ni8430_init(struct pci_dev *dev)
 710{
 711        void __iomem *p;
 712        struct pci_bus_region region;
 713        u32 device_window;
 714        unsigned int bar = 0;
 715
 716        if ((pci_resource_flags(dev, bar) & IORESOURCE_MEM) == 0) {
 717                moan_device("no memory in bar", dev);
 718                return 0;
 719        }
 720
 721        p = pci_ioremap_bar(dev, bar);
 722        if (p == NULL)
 723                return -ENOMEM;
 724
 725        /*
 726         * Set device window address and size in BAR0, while acknowledging that
 727         * the resource structure may contain a translated address that differs
 728         * from the address the device responds to.
 729         */
 730        pcibios_resource_to_bus(dev->bus, &region, &dev->resource[bar]);
 731        device_window = ((region.start + MITE_IOWBSR1_WIN_OFFSET) & 0xffffff00)
 732                        | MITE_IOWBSR1_WENAB | MITE_IOWBSR1_WSIZE;
 733        writel(device_window, p + MITE_IOWBSR1);
 734
 735        /* Set window access to go to RAMSEL IO address space */
 736        writel((readl(p + MITE_IOWCR1) & MITE_IOWCR1_RAMSEL_MASK),
 737               p + MITE_IOWCR1);
 738
 739        /* Enable IO Bus Interrupt 0 */
 740        writel(MITE_LCIMR1_IO_IE_0, p + MITE_LCIMR1);
 741
 742        /* Enable CPU Interrupt */
 743        writel(MITE_LCIMR2_SET_CPU_IE, p + MITE_LCIMR2);
 744
 745        iounmap(p);
 746        return 0;
 747}
 748
 749/* UART Port Control Register */
 750#define NI8430_PORTCON  0x0f
 751#define NI8430_PORTCON_TXVR_ENABLE      (1 << 3)
 752
 753static int
 754pci_ni8430_setup(struct serial_private *priv,
 755                 const struct pciserial_board *board,
 756                 struct uart_8250_port *port, int idx)
 757{
 758        struct pci_dev *dev = priv->dev;
 759        void __iomem *p;
 760        unsigned int bar, offset = board->first_offset;
 761
 762        if (idx >= board->num_ports)
 763                return 1;
 764
 765        bar = FL_GET_BASE(board->flags);
 766        offset += idx * board->uart_offset;
 767
 768        p = pci_ioremap_bar(dev, bar);
 769        if (!p)
 770                return -ENOMEM;
 771
 772        /* enable the transceiver */
 773        writeb(readb(p + offset + NI8430_PORTCON) | NI8430_PORTCON_TXVR_ENABLE,
 774               p + offset + NI8430_PORTCON);
 775
 776        iounmap(p);
 777
 778        return setup_port(priv, port, bar, offset, board->reg_shift);
 779}
 780
 781static int pci_netmos_9900_setup(struct serial_private *priv,
 782                                const struct pciserial_board *board,
 783                                struct uart_8250_port *port, int idx)
 784{
 785        unsigned int bar;
 786
 787        if ((priv->dev->device != PCI_DEVICE_ID_NETMOS_9865) &&
 788            (priv->dev->subsystem_device & 0xff00) == 0x3000) {
 789                /* netmos apparently orders BARs by datasheet layout, so serial
 790                 * ports get BARs 0 and 3 (or 1 and 4 for memmapped)
 791                 */
 792                bar = 3 * idx;
 793
 794                return setup_port(priv, port, bar, 0, board->reg_shift);
 795        } else {
 796                return pci_default_setup(priv, board, port, idx);
 797        }
 798}
 799
 800/* the 99xx series comes with a range of device IDs and a variety
 801 * of capabilities:
 802 *
 803 * 9900 has varying capabilities and can cascade to sub-controllers
 804 *   (cascading should be purely internal)
 805 * 9904 is hardwired with 4 serial ports
 806 * 9912 and 9922 are hardwired with 2 serial ports
 807 */
 808static int pci_netmos_9900_numports(struct pci_dev *dev)
 809{
 810        unsigned int c = dev->class;
 811        unsigned int pi;
 812        unsigned short sub_serports;
 813
 814        pi = c & 0xff;
 815
 816        if (pi == 2)
 817                return 1;
 818
 819        if ((pi == 0) && (dev->device == PCI_DEVICE_ID_NETMOS_9900)) {
 820                /* two possibilities: 0x30ps encodes number of parallel and
 821                 * serial ports, or 0x1000 indicates *something*. This is not
 822                 * immediately obvious, since the 2s1p+4s configuration seems
 823                 * to offer all functionality on functions 0..2, while still
 824                 * advertising the same function 3 as the 4s+2s1p config.
 825                 */
 826                sub_serports = dev->subsystem_device & 0xf;
 827                if (sub_serports > 0)
 828                        return sub_serports;
 829
 830                dev_err(&dev->dev,
 831                        "NetMos/Mostech serial driver ignoring port on ambiguous config.\n");
 832                return 0;
 833        }
 834
 835        moan_device("unknown NetMos/Mostech program interface", dev);
 836        return 0;
 837}
 838
 839static int pci_netmos_init(struct pci_dev *dev)
 840{
 841        /* subdevice 0x00PS means <P> parallel, <S> serial */
 842        unsigned int num_serial = dev->subsystem_device & 0xf;
 843
 844        if ((dev->device == PCI_DEVICE_ID_NETMOS_9901) ||
 845                (dev->device == PCI_DEVICE_ID_NETMOS_9865))
 846                return 0;
 847
 848        if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
 849                        dev->subsystem_device == 0x0299)
 850                return 0;
 851
 852        switch (dev->device) { /* FALLTHROUGH on all */
 853        case PCI_DEVICE_ID_NETMOS_9904:
 854        case PCI_DEVICE_ID_NETMOS_9912:
 855        case PCI_DEVICE_ID_NETMOS_9922:
 856        case PCI_DEVICE_ID_NETMOS_9900:
 857                num_serial = pci_netmos_9900_numports(dev);
 858                break;
 859
 860        default:
 861                break;
 862        }
 863
 864        if (num_serial == 0) {
 865                moan_device("unknown NetMos/Mostech device", dev);
 866                return -ENODEV;
 867        }
 868
 869        return num_serial;
 870}
 871
 872/*
 873 * These chips are available with optionally one parallel port and up to
 874 * two serial ports. Unfortunately they all have the same product id.
 875 *
 876 * Basic configuration is done over a region of 32 I/O ports. The base
 877 * ioport is called INTA or INTC, depending on docs/other drivers.
 878 *
 879 * The region of the 32 I/O ports is configured in POSIO0R...
 880 */
 881
 882/* registers */
 883#define ITE_887x_MISCR          0x9c
 884#define ITE_887x_INTCBAR        0x78
 885#define ITE_887x_UARTBAR        0x7c
 886#define ITE_887x_PS0BAR         0x10
 887#define ITE_887x_POSIO0         0x60
 888
 889/* I/O space size */
 890#define ITE_887x_IOSIZE         32
 891/* I/O space size (bits 26-24; 8 bytes = 011b) */
 892#define ITE_887x_POSIO_IOSIZE_8         (3 << 24)
 893/* I/O space size (bits 26-24; 32 bytes = 101b) */
 894#define ITE_887x_POSIO_IOSIZE_32        (5 << 24)
 895/* Decoding speed (1 = slow, 2 = medium, 3 = fast) */
 896#define ITE_887x_POSIO_SPEED            (3 << 29)
 897/* enable IO_Space bit */
 898#define ITE_887x_POSIO_ENABLE           (1 << 31)
 899
 900static int pci_ite887x_init(struct pci_dev *dev)
 901{
 902        /* inta_addr are the configuration addresses of the ITE */
 903        static const short inta_addr[] = { 0x2a0, 0x2c0, 0x220, 0x240, 0x1e0,
 904                                                        0x200, 0x280, 0 };
 905        int ret, i, type;
 906        struct resource *iobase = NULL;
 907        u32 miscr, uartbar, ioport;
 908
 909        /* search for the base-ioport */
 910        i = 0;
 911        while (inta_addr[i] && iobase == NULL) {
 912                iobase = request_region(inta_addr[i], ITE_887x_IOSIZE,
 913                                                                "ite887x");
 914                if (iobase != NULL) {
 915                        /* write POSIO0R - speed | size | ioport */
 916                        pci_write_config_dword(dev, ITE_887x_POSIO0,
 917                                ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 918                                ITE_887x_POSIO_IOSIZE_32 | inta_addr[i]);
 919                        /* write INTCBAR - ioport */
 920                        pci_write_config_dword(dev, ITE_887x_INTCBAR,
 921                                                                inta_addr[i]);
 922                        ret = inb(inta_addr[i]);
 923                        if (ret != 0xff) {
 924                                /* ioport connected */
 925                                break;
 926                        }
 927                        release_region(iobase->start, ITE_887x_IOSIZE);
 928                        iobase = NULL;
 929                }
 930                i++;
 931        }
 932
 933        if (!inta_addr[i]) {
 934                dev_err(&dev->dev, "ite887x: could not find iobase\n");
 935                return -ENODEV;
 936        }
 937
 938        /* start of undocumented type checking (see parport_pc.c) */
 939        type = inb(iobase->start + 0x18) & 0x0f;
 940
 941        switch (type) {
 942        case 0x2:       /* ITE8871 (1P) */
 943        case 0xa:       /* ITE8875 (1P) */
 944                ret = 0;
 945                break;
 946        case 0xe:       /* ITE8872 (2S1P) */
 947                ret = 2;
 948                break;
 949        case 0x6:       /* ITE8873 (1S) */
 950                ret = 1;
 951                break;
 952        case 0x8:       /* ITE8874 (2S) */
 953                ret = 2;
 954                break;
 955        default:
 956                moan_device("Unknown ITE887x", dev);
 957                ret = -ENODEV;
 958        }
 959
 960        /* configure all serial ports */
 961        for (i = 0; i < ret; i++) {
 962                /* read the I/O port from the device */
 963                pci_read_config_dword(dev, ITE_887x_PS0BAR + (0x4 * (i + 1)),
 964                                                                &ioport);
 965                ioport &= 0x0000FF00;   /* the actual base address */
 966                pci_write_config_dword(dev, ITE_887x_POSIO0 + (0x4 * (i + 1)),
 967                        ITE_887x_POSIO_ENABLE | ITE_887x_POSIO_SPEED |
 968                        ITE_887x_POSIO_IOSIZE_8 | ioport);
 969
 970                /* write the ioport to the UARTBAR */
 971                pci_read_config_dword(dev, ITE_887x_UARTBAR, &uartbar);
 972                uartbar &= ~(0xffff << (16 * i));       /* clear half the reg */
 973                uartbar |= (ioport << (16 * i));        /* set the ioport */
 974                pci_write_config_dword(dev, ITE_887x_UARTBAR, uartbar);
 975
 976                /* get current config */
 977                pci_read_config_dword(dev, ITE_887x_MISCR, &miscr);
 978                /* disable interrupts (UARTx_Routing[3:0]) */
 979                miscr &= ~(0xf << (12 - 4 * i));
 980                /* activate the UART (UARTx_En) */
 981                miscr |= 1 << (23 - i);
 982                /* write new config with activated UART */
 983                pci_write_config_dword(dev, ITE_887x_MISCR, miscr);
 984        }
 985
 986        if (ret <= 0) {
 987                /* the device has no UARTs if we get here */
 988                release_region(iobase->start, ITE_887x_IOSIZE);
 989        }
 990
 991        return ret;
 992}
 993
 994static void pci_ite887x_exit(struct pci_dev *dev)
 995{
 996        u32 ioport;
 997        /* the ioport is bit 0-15 in POSIO0R */
 998        pci_read_config_dword(dev, ITE_887x_POSIO0, &ioport);
 999        ioport &= 0xffff;
1000        release_region(ioport, ITE_887x_IOSIZE);
1001}
1002
1003/*
1004 * EndRun Technologies.
1005 * Determine the number of ports available on the device.
1006 */
1007#define PCI_VENDOR_ID_ENDRUN                    0x7401
1008#define PCI_DEVICE_ID_ENDRUN_1588       0xe100
1009
1010static int pci_endrun_init(struct pci_dev *dev)
1011{
1012        u8 __iomem *p;
1013        unsigned long deviceID;
1014        unsigned int  number_uarts = 0;
1015
1016        /* EndRun device is all 0xexxx */
1017        if (dev->vendor == PCI_VENDOR_ID_ENDRUN &&
1018                (dev->device & 0xf000) != 0xe000)
1019                return 0;
1020
1021        p = pci_iomap(dev, 0, 5);
1022        if (p == NULL)
1023                return -ENOMEM;
1024
1025        deviceID = ioread32(p);
1026        /* EndRun device */
1027        if (deviceID == 0x07000200) {
1028                number_uarts = ioread8(p + 4);
1029                dev_dbg(&dev->dev,
1030                        "%d ports detected on EndRun PCI Express device\n",
1031                        number_uarts);
1032        }
1033        pci_iounmap(dev, p);
1034        return number_uarts;
1035}
1036
1037/*
1038 * Oxford Semiconductor Inc.
1039 * Check that device is part of the Tornado range of devices, then determine
1040 * the number of ports available on the device.
1041 */
1042static int pci_oxsemi_tornado_init(struct pci_dev *dev)
1043{
1044        u8 __iomem *p;
1045        unsigned long deviceID;
1046        unsigned int  number_uarts = 0;
1047
1048        /* OxSemi Tornado devices are all 0xCxxx */
1049        if (dev->vendor == PCI_VENDOR_ID_OXSEMI &&
1050            (dev->device & 0xF000) != 0xC000)
1051                return 0;
1052
1053        p = pci_iomap(dev, 0, 5);
1054        if (p == NULL)
1055                return -ENOMEM;
1056
1057        deviceID = ioread32(p);
1058        /* Tornado device */
1059        if (deviceID == 0x07000200) {
1060                number_uarts = ioread8(p + 4);
1061                dev_dbg(&dev->dev,
1062                        "%d ports detected on Oxford PCI Express device\n",
1063                        number_uarts);
1064        }
1065        pci_iounmap(dev, p);
1066        return number_uarts;
1067}
1068
1069static int pci_asix_setup(struct serial_private *priv,
1070                  const struct pciserial_board *board,
1071                  struct uart_8250_port *port, int idx)
1072{
1073        port->bugs |= UART_BUG_PARITY;
1074        return pci_default_setup(priv, board, port, idx);
1075}
1076
1077/* Quatech devices have their own extra interface features */
1078
1079struct quatech_feature {
1080        u16 devid;
1081        bool amcc;
1082};
1083
1084#define QPCR_TEST_FOR1          0x3F
1085#define QPCR_TEST_GET1          0x00
1086#define QPCR_TEST_FOR2          0x40
1087#define QPCR_TEST_GET2          0x40
1088#define QPCR_TEST_FOR3          0x80
1089#define QPCR_TEST_GET3          0x40
1090#define QPCR_TEST_FOR4          0xC0
1091#define QPCR_TEST_GET4          0x80
1092
1093#define QOPR_CLOCK_X1           0x0000
1094#define QOPR_CLOCK_X2           0x0001
1095#define QOPR_CLOCK_X4           0x0002
1096#define QOPR_CLOCK_X8           0x0003
1097#define QOPR_CLOCK_RATE_MASK    0x0003
1098
1099
1100static struct quatech_feature quatech_cards[] = {
1101        { PCI_DEVICE_ID_QUATECH_QSC100,   1 },
1102        { PCI_DEVICE_ID_QUATECH_DSC100,   1 },
1103        { PCI_DEVICE_ID_QUATECH_DSC100E,  0 },
1104        { PCI_DEVICE_ID_QUATECH_DSC200,   1 },
1105        { PCI_DEVICE_ID_QUATECH_DSC200E,  0 },
1106        { PCI_DEVICE_ID_QUATECH_ESC100D,  1 },
1107        { PCI_DEVICE_ID_QUATECH_ESC100M,  1 },
1108        { PCI_DEVICE_ID_QUATECH_QSCP100,  1 },
1109        { PCI_DEVICE_ID_QUATECH_DSCP100,  1 },
1110        { PCI_DEVICE_ID_QUATECH_QSCP200,  1 },
1111        { PCI_DEVICE_ID_QUATECH_DSCP200,  1 },
1112        { PCI_DEVICE_ID_QUATECH_ESCLP100, 0 },
1113        { PCI_DEVICE_ID_QUATECH_QSCLP100, 0 },
1114        { PCI_DEVICE_ID_QUATECH_DSCLP100, 0 },
1115        { PCI_DEVICE_ID_QUATECH_SSCLP100, 0 },
1116        { PCI_DEVICE_ID_QUATECH_QSCLP200, 0 },
1117        { PCI_DEVICE_ID_QUATECH_DSCLP200, 0 },
1118        { PCI_DEVICE_ID_QUATECH_SSCLP200, 0 },
1119        { PCI_DEVICE_ID_QUATECH_SPPXP_100, 0 },
1120        { 0, }
1121};
1122
1123static int pci_quatech_amcc(u16 devid)
1124{
1125        struct quatech_feature *qf = &quatech_cards[0];
1126        while (qf->devid) {
1127                if (qf->devid == devid)
1128                        return qf->amcc;
1129                qf++;
1130        }
1131        pr_err("quatech: unknown port type '0x%04X'.\n", devid);
1132        return 0;
1133};
1134
1135static int pci_quatech_rqopr(struct uart_8250_port *port)
1136{
1137        unsigned long base = port->port.iobase;
1138        u8 LCR, val;
1139
1140        LCR = inb(base + UART_LCR);
1141        outb(0xBF, base + UART_LCR);
1142        val = inb(base + UART_SCR);
1143        outb(LCR, base + UART_LCR);
1144        return val;
1145}
1146
1147static void pci_quatech_wqopr(struct uart_8250_port *port, u8 qopr)
1148{
1149        unsigned long base = port->port.iobase;
1150        u8 LCR;
1151
1152        LCR = inb(base + UART_LCR);
1153        outb(0xBF, base + UART_LCR);
1154        inb(base + UART_SCR);
1155        outb(qopr, base + UART_SCR);
1156        outb(LCR, base + UART_LCR);
1157}
1158
1159static int pci_quatech_rqmcr(struct uart_8250_port *port)
1160{
1161        unsigned long base = port->port.iobase;
1162        u8 LCR, val, qmcr;
1163
1164        LCR = inb(base + UART_LCR);
1165        outb(0xBF, base + UART_LCR);
1166        val = inb(base + UART_SCR);
1167        outb(val | 0x10, base + UART_SCR);
1168        qmcr = inb(base + UART_MCR);
1169        outb(val, base + UART_SCR);
1170        outb(LCR, base + UART_LCR);
1171
1172        return qmcr;
1173}
1174
1175static void pci_quatech_wqmcr(struct uart_8250_port *port, u8 qmcr)
1176{
1177        unsigned long base = port->port.iobase;
1178        u8 LCR, val;
1179
1180        LCR = inb(base + UART_LCR);
1181        outb(0xBF, base + UART_LCR);
1182        val = inb(base + UART_SCR);
1183        outb(val | 0x10, base + UART_SCR);
1184        outb(qmcr, base + UART_MCR);
1185        outb(val, base + UART_SCR);
1186        outb(LCR, base + UART_LCR);
1187}
1188
1189static int pci_quatech_has_qmcr(struct uart_8250_port *port)
1190{
1191        unsigned long base = port->port.iobase;
1192        u8 LCR, val;
1193
1194        LCR = inb(base + UART_LCR);
1195        outb(0xBF, base + UART_LCR);
1196        val = inb(base + UART_SCR);
1197        if (val & 0x20) {
1198                outb(0x80, UART_LCR);
1199                if (!(inb(UART_SCR) & 0x20)) {
1200                        outb(LCR, base + UART_LCR);
1201                        return 1;
1202                }
1203        }
1204        return 0;
1205}
1206
1207static int pci_quatech_test(struct uart_8250_port *port)
1208{
1209        u8 reg, qopr;
1210
1211        qopr = pci_quatech_rqopr(port);
1212        pci_quatech_wqopr(port, qopr & QPCR_TEST_FOR1);
1213        reg = pci_quatech_rqopr(port) & 0xC0;
1214        if (reg != QPCR_TEST_GET1)
1215                return -EINVAL;
1216        pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR2);
1217        reg = pci_quatech_rqopr(port) & 0xC0;
1218        if (reg != QPCR_TEST_GET2)
1219                return -EINVAL;
1220        pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR3);
1221        reg = pci_quatech_rqopr(port) & 0xC0;
1222        if (reg != QPCR_TEST_GET3)
1223                return -EINVAL;
1224        pci_quatech_wqopr(port, (qopr & QPCR_TEST_FOR1)|QPCR_TEST_FOR4);
1225        reg = pci_quatech_rqopr(port) & 0xC0;
1226        if (reg != QPCR_TEST_GET4)
1227                return -EINVAL;
1228
1229        pci_quatech_wqopr(port, qopr);
1230        return 0;
1231}
1232
1233static int pci_quatech_clock(struct uart_8250_port *port)
1234{
1235        u8 qopr, reg, set;
1236        unsigned long clock;
1237
1238        if (pci_quatech_test(port) < 0)
1239                return 1843200;
1240
1241        qopr = pci_quatech_rqopr(port);
1242
1243        pci_quatech_wqopr(port, qopr & ~QOPR_CLOCK_X8);
1244        reg = pci_quatech_rqopr(port);
1245        if (reg & QOPR_CLOCK_X8) {
1246                clock = 1843200;
1247                goto out;
1248        }
1249        pci_quatech_wqopr(port, qopr | QOPR_CLOCK_X8);
1250        reg = pci_quatech_rqopr(port);
1251        if (!(reg & QOPR_CLOCK_X8)) {
1252                clock = 1843200;
1253                goto out;
1254        }
1255        reg &= QOPR_CLOCK_X8;
1256        if (reg == QOPR_CLOCK_X2) {
1257                clock =  3685400;
1258                set = QOPR_CLOCK_X2;
1259        } else if (reg == QOPR_CLOCK_X4) {
1260                clock = 7372800;
1261                set = QOPR_CLOCK_X4;
1262        } else if (reg == QOPR_CLOCK_X8) {
1263                clock = 14745600;
1264                set = QOPR_CLOCK_X8;
1265        } else {
1266                clock = 1843200;
1267                set = QOPR_CLOCK_X1;
1268        }
1269        qopr &= ~QOPR_CLOCK_RATE_MASK;
1270        qopr |= set;
1271
1272out:
1273        pci_quatech_wqopr(port, qopr);
1274        return clock;
1275}
1276
1277static int pci_quatech_rs422(struct uart_8250_port *port)
1278{
1279        u8 qmcr;
1280        int rs422 = 0;
1281
1282        if (!pci_quatech_has_qmcr(port))
1283                return 0;
1284        qmcr = pci_quatech_rqmcr(port);
1285        pci_quatech_wqmcr(port, 0xFF);
1286        if (pci_quatech_rqmcr(port))
1287                rs422 = 1;
1288        pci_quatech_wqmcr(port, qmcr);
1289        return rs422;
1290}
1291
1292static int pci_quatech_init(struct pci_dev *dev)
1293{
1294        if (pci_quatech_amcc(dev->device)) {
1295                unsigned long base = pci_resource_start(dev, 0);
1296                if (base) {
1297                        u32 tmp;
1298
1299                        outl(inl(base + 0x38) | 0x00002000, base + 0x38);
1300                        tmp = inl(base + 0x3c);
1301                        outl(tmp | 0x01000000, base + 0x3c);
1302                        outl(tmp &= ~0x01000000, base + 0x3c);
1303                }
1304        }
1305        return 0;
1306}
1307
1308static int pci_quatech_setup(struct serial_private *priv,
1309                  const struct pciserial_board *board,
1310                  struct uart_8250_port *port, int idx)
1311{
1312        /* Needed by pci_quatech calls below */
1313        port->port.iobase = pci_resource_start(priv->dev, FL_GET_BASE(board->flags));
1314        /* Set up the clocking */
1315        port->port.uartclk = pci_quatech_clock(port);
1316        /* For now just warn about RS422 */
1317        if (pci_quatech_rs422(port))
1318                pr_warn("quatech: software control of RS422 features not currently supported.\n");
1319        return pci_default_setup(priv, board, port, idx);
1320}
1321
1322static void pci_quatech_exit(struct pci_dev *dev)
1323{
1324}
1325
1326static int pci_default_setup(struct serial_private *priv,
1327                  const struct pciserial_board *board,
1328                  struct uart_8250_port *port, int idx)
1329{
1330        unsigned int bar, offset = board->first_offset, maxnr;
1331
1332        bar = FL_GET_BASE(board->flags);
1333        if (board->flags & FL_BASE_BARS)
1334                bar += idx;
1335        else
1336                offset += idx * board->uart_offset;
1337
1338        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1339                (board->reg_shift + 3);
1340
1341        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1342                return 1;
1343
1344        return setup_port(priv, port, bar, offset, board->reg_shift);
1345}
1346static void
1347pericom_do_set_divisor(struct uart_port *port, unsigned int baud,
1348                               unsigned int quot, unsigned int quot_frac)
1349{
1350        int scr;
1351        int lcr;
1352        int actual_baud;
1353        int tolerance;
1354
1355        for (scr = 5 ; scr <= 15 ; scr++) {
1356                actual_baud = 921600 * 16 / scr;
1357                tolerance = actual_baud / 50;
1358
1359                if ((baud < actual_baud + tolerance) &&
1360                        (baud > actual_baud - tolerance)) {
1361
1362                        lcr = serial_port_in(port, UART_LCR);
1363                        serial_port_out(port, UART_LCR, lcr | 0x80);
1364
1365                        serial_port_out(port, UART_DLL, 1);
1366                        serial_port_out(port, UART_DLM, 0);
1367                        serial_port_out(port, 2, 16 - scr);
1368                        serial_port_out(port, UART_LCR, lcr);
1369                        return;
1370                } else if (baud > actual_baud) {
1371                        break;
1372                }
1373        }
1374        serial8250_do_set_divisor(port, baud, quot, quot_frac);
1375}
1376static int pci_pericom_setup(struct serial_private *priv,
1377                  const struct pciserial_board *board,
1378                  struct uart_8250_port *port, int idx)
1379{
1380        unsigned int bar, offset = board->first_offset, maxnr;
1381
1382        bar = FL_GET_BASE(board->flags);
1383        if (board->flags & FL_BASE_BARS)
1384                bar += idx;
1385        else
1386                offset += idx * board->uart_offset;
1387
1388
1389        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1390                (board->reg_shift + 3);
1391
1392        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1393                return 1;
1394
1395        port->port.set_divisor = pericom_do_set_divisor;
1396
1397        return setup_port(priv, port, bar, offset, board->reg_shift);
1398}
1399
1400static int pci_pericom_setup_four_at_eight(struct serial_private *priv,
1401                  const struct pciserial_board *board,
1402                  struct uart_8250_port *port, int idx)
1403{
1404        unsigned int bar, offset = board->first_offset, maxnr;
1405
1406        bar = FL_GET_BASE(board->flags);
1407        if (board->flags & FL_BASE_BARS)
1408                bar += idx;
1409        else
1410                offset += idx * board->uart_offset;
1411
1412        if (idx==3)
1413                offset = 0x38;
1414
1415        maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) >>
1416                (board->reg_shift + 3);
1417
1418        if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
1419                return 1;
1420
1421        port->port.set_divisor = pericom_do_set_divisor;
1422
1423        return setup_port(priv, port, bar, offset, board->reg_shift);
1424}
1425
1426static int
1427ce4100_serial_setup(struct serial_private *priv,
1428                  const struct pciserial_board *board,
1429                  struct uart_8250_port *port, int idx)
1430{
1431        int ret;
1432
1433        ret = setup_port(priv, port, idx, 0, board->reg_shift);
1434        port->port.iotype = UPIO_MEM32;
1435        port->port.type = PORT_XSCALE;
1436        port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1437        port->port.regshift = 2;
1438
1439        return ret;
1440}
1441
1442static int
1443pci_omegapci_setup(struct serial_private *priv,
1444                      const struct pciserial_board *board,
1445                      struct uart_8250_port *port, int idx)
1446{
1447        return setup_port(priv, port, 2, idx * 8, 0);
1448}
1449
1450static int
1451pci_brcm_trumanage_setup(struct serial_private *priv,
1452                         const struct pciserial_board *board,
1453                         struct uart_8250_port *port, int idx)
1454{
1455        int ret = pci_default_setup(priv, board, port, idx);
1456
1457        port->port.type = PORT_BRCM_TRUMANAGE;
1458        port->port.flags = (port->port.flags | UPF_FIXED_PORT | UPF_FIXED_TYPE);
1459        return ret;
1460}
1461
1462/* RTS will control by MCR if this bit is 0 */
1463#define FINTEK_RTS_CONTROL_BY_HW        BIT(4)
1464/* only worked with FINTEK_RTS_CONTROL_BY_HW on */
1465#define FINTEK_RTS_INVERT               BIT(5)
1466
1467/* We should do proper H/W transceiver setting before change to RS485 mode */
1468static int pci_fintek_rs485_config(struct uart_port *port,
1469                               struct serial_rs485 *rs485)
1470{
1471        struct pci_dev *pci_dev = to_pci_dev(port->dev);
1472        u8 setting;
1473        u8 *index = (u8 *) port->private_data;
1474
1475        pci_read_config_byte(pci_dev, 0x40 + 8 * *index + 7, &setting);
1476
1477        if (!rs485)
1478                rs485 = &port->rs485;
1479        else if (rs485->flags & SER_RS485_ENABLED)
1480                memset(rs485->padding, 0, sizeof(rs485->padding));
1481        else
1482                memset(rs485, 0, sizeof(*rs485));
1483
1484        /* F81504/508/512 not support RTS delay before or after send */
1485        rs485->flags &= SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND;
1486
1487        if (rs485->flags & SER_RS485_ENABLED) {
1488                /* Enable RTS H/W control mode */
1489                setting |= FINTEK_RTS_CONTROL_BY_HW;
1490
1491                if (rs485->flags & SER_RS485_RTS_ON_SEND) {
1492                        /* RTS driving high on TX */
1493                        setting &= ~FINTEK_RTS_INVERT;
1494                } else {
1495                        /* RTS driving low on TX */
1496                        setting |= FINTEK_RTS_INVERT;
1497                }
1498
1499                rs485->delay_rts_after_send = 0;
1500                rs485->delay_rts_before_send = 0;
1501        } else {
1502                /* Disable RTS H/W control mode */
1503                setting &= ~(FINTEK_RTS_CONTROL_BY_HW | FINTEK_RTS_INVERT);
1504        }
1505
1506        pci_write_config_byte(pci_dev, 0x40 + 8 * *index + 7, setting);
1507
1508        if (rs485 != &port->rs485)
1509                port->rs485 = *rs485;
1510
1511        return 0;
1512}
1513
1514static int pci_fintek_setup(struct serial_private *priv,
1515                            const struct pciserial_board *board,
1516                            struct uart_8250_port *port, int idx)
1517{
1518        struct pci_dev *pdev = priv->dev;
1519        u8 *data;
1520        u8 config_base;
1521        u16 iobase;
1522
1523        config_base = 0x40 + 0x08 * idx;
1524
1525        /* Get the io address from configuration space */
1526        pci_read_config_word(pdev, config_base + 4, &iobase);
1527
1528        dev_dbg(&pdev->dev, "%s: idx=%d iobase=0x%x", __func__, idx, iobase);
1529
1530        port->port.iotype = UPIO_PORT;
1531        port->port.iobase = iobase;
1532        port->port.rs485_config = pci_fintek_rs485_config;
1533
1534        data = devm_kzalloc(&pdev->dev, sizeof(u8), GFP_KERNEL);
1535        if (!data)
1536                return -ENOMEM;
1537
1538        /* preserve index in PCI configuration space */
1539        *data = idx;
1540        port->port.private_data = data;
1541
1542        return 0;
1543}
1544
1545static int pci_fintek_init(struct pci_dev *dev)
1546{
1547        unsigned long iobase;
1548        u32 max_port, i;
1549        resource_size_t bar_data[3];
1550        u8 config_base;
1551        struct serial_private *priv = pci_get_drvdata(dev);
1552        struct uart_8250_port *port;
1553
1554        if (!(pci_resource_flags(dev, 5) & IORESOURCE_IO) ||
1555                        !(pci_resource_flags(dev, 4) & IORESOURCE_IO) ||
1556                        !(pci_resource_flags(dev, 3) & IORESOURCE_IO))
1557                return -ENODEV;
1558
1559        switch (dev->device) {
1560        case 0x1104: /* 4 ports */
1561        case 0x1108: /* 8 ports */
1562                max_port = dev->device & 0xff;
1563                break;
1564        case 0x1112: /* 12 ports */
1565                max_port = 12;
1566                break;
1567        default:
1568                return -EINVAL;
1569        }
1570
1571        /* Get the io address dispatch from the BIOS */
1572        bar_data[0] = pci_resource_start(dev, 5);
1573        bar_data[1] = pci_resource_start(dev, 4);
1574        bar_data[2] = pci_resource_start(dev, 3);
1575
1576        for (i = 0; i < max_port; ++i) {
1577                /* UART0 configuration offset start from 0x40 */
1578                config_base = 0x40 + 0x08 * i;
1579
1580                /* Calculate Real IO Port */
1581                iobase = (bar_data[i / 4] & 0xffffffe0) + (i % 4) * 8;
1582
1583                /* Enable UART I/O port */
1584                pci_write_config_byte(dev, config_base + 0x00, 0x01);
1585
1586                /* Select 128-byte FIFO and 8x FIFO threshold */
1587                pci_write_config_byte(dev, config_base + 0x01, 0x33);
1588
1589                /* LSB UART */
1590                pci_write_config_byte(dev, config_base + 0x04,
1591                                (u8)(iobase & 0xff));
1592
1593                /* MSB UART */
1594                pci_write_config_byte(dev, config_base + 0x05,
1595                                (u8)((iobase & 0xff00) >> 8));
1596
1597                pci_write_config_byte(dev, config_base + 0x06, dev->irq);
1598
1599                if (priv) {
1600                        /* re-apply RS232/485 mode when
1601                         * pciserial_resume_ports()
1602                         */
1603                        port = serial8250_get_port(priv->line[i]);
1604                        pci_fintek_rs485_config(&port->port, NULL);
1605                } else {
1606                        /* First init without port data
1607                         * force init to RS232 Mode
1608                         */
1609                        pci_write_config_byte(dev, config_base + 0x07, 0x01);
1610                }
1611        }
1612
1613        return max_port;
1614}
1615
1616static void f815xxa_mem_serial_out(struct uart_port *p, int offset, int value)
1617{
1618        struct f815xxa_data *data = p->private_data;
1619        unsigned long flags;
1620
1621        spin_lock_irqsave(&data->lock, flags);
1622        writeb(value, p->membase + offset);
1623        readb(p->membase + UART_SCR); /* Dummy read for flush pcie tx queue */
1624        spin_unlock_irqrestore(&data->lock, flags);
1625}
1626
1627static int pci_fintek_f815xxa_setup(struct serial_private *priv,
1628                            const struct pciserial_board *board,
1629                            struct uart_8250_port *port, int idx)
1630{
1631        struct pci_dev *pdev = priv->dev;
1632        struct f815xxa_data *data;
1633
1634        data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
1635        if (!data)
1636                return -ENOMEM;
1637
1638        data->idx = idx;
1639        spin_lock_init(&data->lock);
1640
1641        port->port.private_data = data;
1642        port->port.iotype = UPIO_MEM;
1643        port->port.flags |= UPF_IOREMAP;
1644        port->port.mapbase = pci_resource_start(pdev, 0) + 8 * idx;
1645        port->port.serial_out = f815xxa_mem_serial_out;
1646
1647        return 0;
1648}
1649
1650static int pci_fintek_f815xxa_init(struct pci_dev *dev)
1651{
1652        u32 max_port, i;
1653        int config_base;
1654
1655        if (!(pci_resource_flags(dev, 0) & IORESOURCE_MEM))
1656                return -ENODEV;
1657
1658        switch (dev->device) {
1659        case 0x1204: /* 4 ports */
1660        case 0x1208: /* 8 ports */
1661                max_port = dev->device & 0xff;
1662                break;
1663        case 0x1212: /* 12 ports */
1664                max_port = 12;
1665                break;
1666        default:
1667                return -EINVAL;
1668        }
1669
1670        /* Set to mmio decode */
1671        pci_write_config_byte(dev, 0x209, 0x40);
1672
1673        for (i = 0; i < max_port; ++i) {
1674                /* UART0 configuration offset start from 0x2A0 */
1675                config_base = 0x2A0 + 0x08 * i;
1676
1677                /* Select 128-byte FIFO and 8x FIFO threshold */
1678                pci_write_config_byte(dev, config_base + 0x01, 0x33);
1679
1680                /* Enable UART I/O port */
1681                pci_write_config_byte(dev, config_base + 0, 0x01);
1682        }
1683
1684        return max_port;
1685}
1686
1687static int skip_tx_en_setup(struct serial_private *priv,
1688                        const struct pciserial_board *board,
1689                        struct uart_8250_port *port, int idx)
1690{
1691        port->port.quirks |= UPQ_NO_TXEN_TEST;
1692        dev_dbg(&priv->dev->dev,
1693                "serial8250: skipping TxEn test for device [%04x:%04x] subsystem [%04x:%04x]\n",
1694                priv->dev->vendor, priv->dev->device,
1695                priv->dev->subsystem_vendor, priv->dev->subsystem_device);
1696
1697        return pci_default_setup(priv, board, port, idx);
1698}
1699
1700static void kt_handle_break(struct uart_port *p)
1701{
1702        struct uart_8250_port *up = up_to_u8250p(p);
1703        /*
1704         * On receipt of a BI, serial device in Intel ME (Intel
1705         * management engine) needs to have its fifos cleared for sane
1706         * SOL (Serial Over Lan) output.
1707         */
1708        serial8250_clear_and_reinit_fifos(up);
1709}
1710
1711static unsigned int kt_serial_in(struct uart_port *p, int offset)
1712{
1713        struct uart_8250_port *up = up_to_u8250p(p);
1714        unsigned int val;
1715
1716        /*
1717         * When the Intel ME (management engine) gets reset its serial
1718         * port registers could return 0 momentarily.  Functions like
1719         * serial8250_console_write, read and save the IER, perform
1720         * some operation and then restore it.  In order to avoid
1721         * setting IER register inadvertently to 0, if the value read
1722         * is 0, double check with ier value in uart_8250_port and use
1723         * that instead.  up->ier should be the same value as what is
1724         * currently configured.
1725         */
1726        val = inb(p->iobase + offset);
1727        if (offset == UART_IER) {
1728                if (val == 0)
1729                        val = up->ier;
1730        }
1731        return val;
1732}
1733
1734static int kt_serial_setup(struct serial_private *priv,
1735                           const struct pciserial_board *board,
1736                           struct uart_8250_port *port, int idx)
1737{
1738        port->port.flags |= UPF_BUG_THRE;
1739        port->port.serial_in = kt_serial_in;
1740        port->port.handle_break = kt_handle_break;
1741        return skip_tx_en_setup(priv, board, port, idx);
1742}
1743
1744static int pci_eg20t_init(struct pci_dev *dev)
1745{
1746#if defined(CONFIG_SERIAL_PCH_UART) || defined(CONFIG_SERIAL_PCH_UART_MODULE)
1747        return -ENODEV;
1748#else
1749        return 0;
1750#endif
1751}
1752
1753static int
1754pci_wch_ch353_setup(struct serial_private *priv,
1755                    const struct pciserial_board *board,
1756                    struct uart_8250_port *port, int idx)
1757{
1758        port->port.flags |= UPF_FIXED_TYPE;
1759        port->port.type = PORT_16550A;
1760        return pci_default_setup(priv, board, port, idx);
1761}
1762
1763static int
1764pci_wch_ch355_setup(struct serial_private *priv,
1765                const struct pciserial_board *board,
1766                struct uart_8250_port *port, int idx)
1767{
1768        port->port.flags |= UPF_FIXED_TYPE;
1769        port->port.type = PORT_16550A;
1770        return pci_default_setup(priv, board, port, idx);
1771}
1772
1773static int
1774pci_wch_ch38x_setup(struct serial_private *priv,
1775                    const struct pciserial_board *board,
1776                    struct uart_8250_port *port, int idx)
1777{
1778        port->port.flags |= UPF_FIXED_TYPE;
1779        port->port.type = PORT_16850;
1780        return pci_default_setup(priv, board, port, idx);
1781}
1782
1783
1784#define CH384_XINT_ENABLE_REG   0xEB
1785#define CH384_XINT_ENABLE_BIT   0x02
1786
1787static int pci_wch_ch38x_init(struct pci_dev *dev)
1788{
1789        int max_port;
1790        unsigned long iobase;
1791
1792
1793        switch (dev->device) {
1794        case 0x3853: /* 8 ports */
1795                max_port = 8;
1796                break;
1797        default:
1798                return -EINVAL;
1799        }
1800
1801        iobase = pci_resource_start(dev, 0);
1802        outb(CH384_XINT_ENABLE_BIT, iobase + CH384_XINT_ENABLE_REG);
1803
1804        return max_port;
1805}
1806
1807static void pci_wch_ch38x_exit(struct pci_dev *dev)
1808{
1809        unsigned long iobase;
1810
1811        iobase = pci_resource_start(dev, 0);
1812        outb(0x0, iobase + CH384_XINT_ENABLE_REG);
1813}
1814
1815
1816static int
1817pci_sunix_setup(struct serial_private *priv,
1818                const struct pciserial_board *board,
1819                struct uart_8250_port *port, int idx)
1820{
1821        int bar;
1822        int offset;
1823
1824        port->port.flags |= UPF_FIXED_TYPE;
1825        port->port.type = PORT_SUNIX;
1826
1827        if (idx < 4) {
1828                bar = 0;
1829                offset = idx * board->uart_offset;
1830        } else {
1831                bar = 1;
1832                idx -= 4;
1833                idx = div_s64_rem(idx, 4, &offset);
1834                offset = idx * 64 + offset * board->uart_offset;
1835        }
1836
1837        return setup_port(priv, port, bar, offset, 0);
1838}
1839
1840static int
1841pci_moxa_setup(struct serial_private *priv,
1842                const struct pciserial_board *board,
1843                struct uart_8250_port *port, int idx)
1844{
1845        unsigned int bar = FL_GET_BASE(board->flags);
1846        int offset;
1847
1848        if (board->num_ports == 4 && idx == 3)
1849                offset = 7 * board->uart_offset;
1850        else
1851                offset = idx * board->uart_offset;
1852
1853        return setup_port(priv, port, bar, offset, 0);
1854}
1855
1856#define PCI_VENDOR_ID_SBSMODULARIO      0x124B
1857#define PCI_SUBVENDOR_ID_SBSMODULARIO   0x124B
1858#define PCI_DEVICE_ID_OCTPRO            0x0001
1859#define PCI_SUBDEVICE_ID_OCTPRO232      0x0108
1860#define PCI_SUBDEVICE_ID_OCTPRO422      0x0208
1861#define PCI_SUBDEVICE_ID_POCTAL232      0x0308
1862#define PCI_SUBDEVICE_ID_POCTAL422      0x0408
1863#define PCI_SUBDEVICE_ID_SIIG_DUAL_00   0x2500
1864#define PCI_SUBDEVICE_ID_SIIG_DUAL_30   0x2530
1865#define PCI_VENDOR_ID_ADVANTECH         0x13fe
1866#define PCI_DEVICE_ID_INTEL_CE4100_UART 0x2e66
1867#define PCI_DEVICE_ID_ADVANTECH_PCI3620 0x3620
1868#define PCI_DEVICE_ID_ADVANTECH_PCI3618 0x3618
1869#define PCI_DEVICE_ID_ADVANTECH_PCIf618 0xf618
1870#define PCI_DEVICE_ID_TITAN_200I        0x8028
1871#define PCI_DEVICE_ID_TITAN_400I        0x8048
1872#define PCI_DEVICE_ID_TITAN_800I        0x8088
1873#define PCI_DEVICE_ID_TITAN_800EH       0xA007
1874#define PCI_DEVICE_ID_TITAN_800EHB      0xA008
1875#define PCI_DEVICE_ID_TITAN_400EH       0xA009
1876#define PCI_DEVICE_ID_TITAN_100E        0xA010
1877#define PCI_DEVICE_ID_TITAN_200E        0xA012
1878#define PCI_DEVICE_ID_TITAN_400E        0xA013
1879#define PCI_DEVICE_ID_TITAN_800E        0xA014
1880#define PCI_DEVICE_ID_TITAN_200EI       0xA016
1881#define PCI_DEVICE_ID_TITAN_200EISI     0xA017
1882#define PCI_DEVICE_ID_TITAN_200V3       0xA306
1883#define PCI_DEVICE_ID_TITAN_400V3       0xA310
1884#define PCI_DEVICE_ID_TITAN_410V3       0xA312
1885#define PCI_DEVICE_ID_TITAN_800V3       0xA314
1886#define PCI_DEVICE_ID_TITAN_800V3B      0xA315
1887#define PCI_DEVICE_ID_OXSEMI_16PCI958   0x9538
1888#define PCIE_DEVICE_ID_NEO_2_OX_IBM     0x00F6
1889#define PCI_DEVICE_ID_PLX_CRONYX_OMEGA  0xc001
1890#define PCI_DEVICE_ID_INTEL_PATSBURG_KT 0x1d3d
1891#define PCI_VENDOR_ID_WCH               0x4348
1892#define PCI_DEVICE_ID_WCH_CH352_2S      0x3253
1893#define PCI_DEVICE_ID_WCH_CH353_4S      0x3453
1894#define PCI_DEVICE_ID_WCH_CH353_2S1PF   0x5046
1895#define PCI_DEVICE_ID_WCH_CH353_1S1P    0x5053
1896#define PCI_DEVICE_ID_WCH_CH353_2S1P    0x7053
1897#define PCI_DEVICE_ID_WCH_CH355_4S      0x7173
1898#define PCI_VENDOR_ID_AGESTAR           0x5372
1899#define PCI_DEVICE_ID_AGESTAR_9375      0x6872
1900#define PCI_VENDOR_ID_ASIX              0x9710
1901#define PCI_DEVICE_ID_BROADCOM_TRUMANAGE 0x160a
1902#define PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800 0x818e
1903
1904#define PCIE_VENDOR_ID_WCH              0x1c00
1905#define PCIE_DEVICE_ID_WCH_CH382_2S1P   0x3250
1906#define PCIE_DEVICE_ID_WCH_CH384_4S     0x3470
1907#define PCIE_DEVICE_ID_WCH_CH384_8S     0x3853
1908#define PCIE_DEVICE_ID_WCH_CH382_2S     0x3253
1909
1910#define PCI_VENDOR_ID_ACCESIO                   0x494f
1911#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SDB     0x1051
1912#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2S      0x1053
1913#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB     0x105C
1914#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S      0x105E
1915#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_2DB   0x1091
1916#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_2    0x1093
1917#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB   0x1099
1918#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4    0x109B
1919#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_2SMDB    0x10D1
1920#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_2SM     0x10D3
1921#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB    0x10DA
1922#define PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM     0x10DC
1923#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_1    0x1108
1924#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_2    0x1110
1925#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_2    0x1111
1926#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4    0x1118
1927#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4    0x1119
1928#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2S       0x1152
1929#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S       0x115A
1930#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_2     0x1190
1931#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_2    0x1191
1932#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4     0x1198
1933#define PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4    0x1199
1934#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_2SM      0x11D0
1935#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4     0x105A
1936#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4     0x105B
1937#define PCI_DEVICE_ID_ACCESIO_PCIE_COM422_8     0x106A
1938#define PCI_DEVICE_ID_ACCESIO_PCIE_COM485_8     0x106B
1939#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4     0x1098
1940#define PCI_DEVICE_ID_ACCESIO_PCIE_COM232_8     0x10A9
1941#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM      0x10D9
1942#define PCI_DEVICE_ID_ACCESIO_PCIE_COM_8SM      0x10E9
1943#define PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM      0x11D8
1944
1945
1946#define PCI_DEVICE_ID_MOXA_CP102E       0x1024
1947#define PCI_DEVICE_ID_MOXA_CP102EL      0x1025
1948#define PCI_DEVICE_ID_MOXA_CP104EL_A    0x1045
1949#define PCI_DEVICE_ID_MOXA_CP114EL      0x1144
1950#define PCI_DEVICE_ID_MOXA_CP116E_A_A   0x1160
1951#define PCI_DEVICE_ID_MOXA_CP116E_A_B   0x1161
1952#define PCI_DEVICE_ID_MOXA_CP118EL_A    0x1182
1953#define PCI_DEVICE_ID_MOXA_CP118E_A_I   0x1183
1954#define PCI_DEVICE_ID_MOXA_CP132EL      0x1322
1955#define PCI_DEVICE_ID_MOXA_CP134EL_A    0x1342
1956#define PCI_DEVICE_ID_MOXA_CP138E_A     0x1381
1957#define PCI_DEVICE_ID_MOXA_CP168EL_A    0x1683
1958
1959/* Unknown vendors/cards - this should not be in linux/pci_ids.h */
1960#define PCI_SUBDEVICE_ID_UNKNOWN_0x1584 0x1584
1961#define PCI_SUBDEVICE_ID_UNKNOWN_0x1588 0x1588
1962
1963/*
1964 * Master list of serial port init/setup/exit quirks.
1965 * This does not describe the general nature of the port.
1966 * (ie, baud base, number and location of ports, etc)
1967 *
1968 * This list is ordered alphabetically by vendor then device.
1969 * Specific entries must come before more generic entries.
1970 */
1971static struct pci_serial_quirk pci_serial_quirks[] = {
1972        /*
1973        * ADDI-DATA GmbH communication cards <info@addi-data.com>
1974        */
1975        {
1976                .vendor         = PCI_VENDOR_ID_AMCC,
1977                .device         = PCI_DEVICE_ID_AMCC_ADDIDATA_APCI7800,
1978                .subvendor      = PCI_ANY_ID,
1979                .subdevice      = PCI_ANY_ID,
1980                .setup          = addidata_apci7800_setup,
1981        },
1982        /*
1983         * AFAVLAB cards - these may be called via parport_serial
1984         *  It is not clear whether this applies to all products.
1985         */
1986        {
1987                .vendor         = PCI_VENDOR_ID_AFAVLAB,
1988                .device         = PCI_ANY_ID,
1989                .subvendor      = PCI_ANY_ID,
1990                .subdevice      = PCI_ANY_ID,
1991                .setup          = afavlab_setup,
1992        },
1993        /*
1994         * HP Diva
1995         */
1996        {
1997                .vendor         = PCI_VENDOR_ID_HP,
1998                .device         = PCI_DEVICE_ID_HP_DIVA,
1999                .subvendor      = PCI_ANY_ID,
2000                .subdevice      = PCI_ANY_ID,
2001                .init           = pci_hp_diva_init,
2002                .setup          = pci_hp_diva_setup,
2003        },
2004        /*
2005         * HPE PCI serial device
2006         */
2007        {
2008                .vendor         = PCI_VENDOR_ID_HP_3PAR,
2009                .device         = PCI_DEVICE_ID_HPE_PCI_SERIAL,
2010                .subvendor      = PCI_ANY_ID,
2011                .subdevice      = PCI_ANY_ID,
2012                .setup          = pci_hp_diva_setup,
2013        },
2014        /*
2015         * Intel
2016         */
2017        {
2018                .vendor         = PCI_VENDOR_ID_INTEL,
2019                .device         = PCI_DEVICE_ID_INTEL_80960_RP,
2020                .subvendor      = 0xe4bf,
2021                .subdevice      = PCI_ANY_ID,
2022                .init           = pci_inteli960ni_init,
2023                .setup          = pci_default_setup,
2024        },
2025        {
2026                .vendor         = PCI_VENDOR_ID_INTEL,
2027                .device         = PCI_DEVICE_ID_INTEL_8257X_SOL,
2028                .subvendor      = PCI_ANY_ID,
2029                .subdevice      = PCI_ANY_ID,
2030                .setup          = skip_tx_en_setup,
2031        },
2032        {
2033                .vendor         = PCI_VENDOR_ID_INTEL,
2034                .device         = PCI_DEVICE_ID_INTEL_82573L_SOL,
2035                .subvendor      = PCI_ANY_ID,
2036                .subdevice      = PCI_ANY_ID,
2037                .setup          = skip_tx_en_setup,
2038        },
2039        {
2040                .vendor         = PCI_VENDOR_ID_INTEL,
2041                .device         = PCI_DEVICE_ID_INTEL_82573E_SOL,
2042                .subvendor      = PCI_ANY_ID,
2043                .subdevice      = PCI_ANY_ID,
2044                .setup          = skip_tx_en_setup,
2045        },
2046        {
2047                .vendor         = PCI_VENDOR_ID_INTEL,
2048                .device         = PCI_DEVICE_ID_INTEL_CE4100_UART,
2049                .subvendor      = PCI_ANY_ID,
2050                .subdevice      = PCI_ANY_ID,
2051                .setup          = ce4100_serial_setup,
2052        },
2053        {
2054                .vendor         = PCI_VENDOR_ID_INTEL,
2055                .device         = PCI_DEVICE_ID_INTEL_PATSBURG_KT,
2056                .subvendor      = PCI_ANY_ID,
2057                .subdevice      = PCI_ANY_ID,
2058                .setup          = kt_serial_setup,
2059        },
2060        /*
2061         * ITE
2062         */
2063        {
2064                .vendor         = PCI_VENDOR_ID_ITE,
2065                .device         = PCI_DEVICE_ID_ITE_8872,
2066                .subvendor      = PCI_ANY_ID,
2067                .subdevice      = PCI_ANY_ID,
2068                .init           = pci_ite887x_init,
2069                .setup          = pci_default_setup,
2070                .exit           = pci_ite887x_exit,
2071        },
2072        /*
2073         * National Instruments
2074         */
2075        {
2076                .vendor         = PCI_VENDOR_ID_NI,
2077                .device         = PCI_DEVICE_ID_NI_PCI23216,
2078                .subvendor      = PCI_ANY_ID,
2079                .subdevice      = PCI_ANY_ID,
2080                .init           = pci_ni8420_init,
2081                .setup          = pci_default_setup,
2082                .exit           = pci_ni8420_exit,
2083        },
2084        {
2085                .vendor         = PCI_VENDOR_ID_NI,
2086                .device         = PCI_DEVICE_ID_NI_PCI2328,
2087                .subvendor      = PCI_ANY_ID,
2088                .subdevice      = PCI_ANY_ID,
2089                .init           = pci_ni8420_init,
2090                .setup          = pci_default_setup,
2091                .exit           = pci_ni8420_exit,
2092        },
2093        {
2094                .vendor         = PCI_VENDOR_ID_NI,
2095                .device         = PCI_DEVICE_ID_NI_PCI2324,
2096                .subvendor      = PCI_ANY_ID,
2097                .subdevice      = PCI_ANY_ID,
2098                .init           = pci_ni8420_init,
2099                .setup          = pci_default_setup,
2100                .exit           = pci_ni8420_exit,
2101        },
2102        {
2103                .vendor         = PCI_VENDOR_ID_NI,
2104                .device         = PCI_DEVICE_ID_NI_PCI2322,
2105                .subvendor      = PCI_ANY_ID,
2106                .subdevice      = PCI_ANY_ID,
2107                .init           = pci_ni8420_init,
2108                .setup          = pci_default_setup,
2109                .exit           = pci_ni8420_exit,
2110        },
2111        {
2112                .vendor         = PCI_VENDOR_ID_NI,
2113                .device         = PCI_DEVICE_ID_NI_PCI2324I,
2114                .subvendor      = PCI_ANY_ID,
2115                .subdevice      = PCI_ANY_ID,
2116                .init           = pci_ni8420_init,
2117                .setup          = pci_default_setup,
2118                .exit           = pci_ni8420_exit,
2119        },
2120        {
2121                .vendor         = PCI_VENDOR_ID_NI,
2122                .device         = PCI_DEVICE_ID_NI_PCI2322I,
2123                .subvendor      = PCI_ANY_ID,
2124                .subdevice      = PCI_ANY_ID,
2125                .init           = pci_ni8420_init,
2126                .setup          = pci_default_setup,
2127                .exit           = pci_ni8420_exit,
2128        },
2129        {
2130                .vendor         = PCI_VENDOR_ID_NI,
2131                .device         = PCI_DEVICE_ID_NI_PXI8420_23216,
2132                .subvendor      = PCI_ANY_ID,
2133                .subdevice      = PCI_ANY_ID,
2134                .init           = pci_ni8420_init,
2135                .setup          = pci_default_setup,
2136                .exit           = pci_ni8420_exit,
2137        },
2138        {
2139                .vendor         = PCI_VENDOR_ID_NI,
2140                .device         = PCI_DEVICE_ID_NI_PXI8420_2328,
2141                .subvendor      = PCI_ANY_ID,
2142                .subdevice      = PCI_ANY_ID,
2143                .init           = pci_ni8420_init,
2144                .setup          = pci_default_setup,
2145                .exit           = pci_ni8420_exit,
2146        },
2147        {
2148                .vendor         = PCI_VENDOR_ID_NI,
2149                .device         = PCI_DEVICE_ID_NI_PXI8420_2324,
2150                .subvendor      = PCI_ANY_ID,
2151                .subdevice      = PCI_ANY_ID,
2152                .init           = pci_ni8420_init,
2153                .setup          = pci_default_setup,
2154                .exit           = pci_ni8420_exit,
2155        },
2156        {
2157                .vendor         = PCI_VENDOR_ID_NI,
2158                .device         = PCI_DEVICE_ID_NI_PXI8420_2322,
2159                .subvendor      = PCI_ANY_ID,
2160                .subdevice      = PCI_ANY_ID,
2161                .init           = pci_ni8420_init,
2162                .setup          = pci_default_setup,
2163                .exit           = pci_ni8420_exit,
2164        },
2165        {
2166                .vendor         = PCI_VENDOR_ID_NI,
2167                .device         = PCI_DEVICE_ID_NI_PXI8422_2324,
2168                .subvendor      = PCI_ANY_ID,
2169                .subdevice      = PCI_ANY_ID,
2170                .init           = pci_ni8420_init,
2171                .setup          = pci_default_setup,
2172                .exit           = pci_ni8420_exit,
2173        },
2174        {
2175                .vendor         = PCI_VENDOR_ID_NI,
2176                .device         = PCI_DEVICE_ID_NI_PXI8422_2322,
2177                .subvendor      = PCI_ANY_ID,
2178                .subdevice      = PCI_ANY_ID,
2179                .init           = pci_ni8420_init,
2180                .setup          = pci_default_setup,
2181                .exit           = pci_ni8420_exit,
2182        },
2183        {
2184                .vendor         = PCI_VENDOR_ID_NI,
2185                .device         = PCI_ANY_ID,
2186                .subvendor      = PCI_ANY_ID,
2187                .subdevice      = PCI_ANY_ID,
2188                .init           = pci_ni8430_init,
2189                .setup          = pci_ni8430_setup,
2190                .exit           = pci_ni8430_exit,
2191        },
2192        /* Quatech */
2193        {
2194                .vendor         = PCI_VENDOR_ID_QUATECH,
2195                .device         = PCI_ANY_ID,
2196                .subvendor      = PCI_ANY_ID,
2197                .subdevice      = PCI_ANY_ID,
2198                .init           = pci_quatech_init,
2199                .setup          = pci_quatech_setup,
2200                .exit           = pci_quatech_exit,
2201        },
2202        /*
2203         * Panacom
2204         */
2205        {
2206                .vendor         = PCI_VENDOR_ID_PANACOM,
2207                .device         = PCI_DEVICE_ID_PANACOM_QUADMODEM,
2208                .subvendor      = PCI_ANY_ID,
2209                .subdevice      = PCI_ANY_ID,
2210                .init           = pci_plx9050_init,
2211                .setup          = pci_default_setup,
2212                .exit           = pci_plx9050_exit,
2213        },
2214        {
2215                .vendor         = PCI_VENDOR_ID_PANACOM,
2216                .device         = PCI_DEVICE_ID_PANACOM_DUALMODEM,
2217                .subvendor      = PCI_ANY_ID,
2218                .subdevice      = PCI_ANY_ID,
2219                .init           = pci_plx9050_init,
2220                .setup          = pci_default_setup,
2221                .exit           = pci_plx9050_exit,
2222        },
2223        /*
2224         * Pericom (Only 7954 - It have a offset jump for port 4)
2225         */
2226        {
2227                .vendor         = PCI_VENDOR_ID_PERICOM,
2228                .device         = PCI_DEVICE_ID_PERICOM_PI7C9X7954,
2229                .subvendor      = PCI_ANY_ID,
2230                .subdevice      = PCI_ANY_ID,
2231                .setup          = pci_pericom_setup_four_at_eight,
2232        },
2233        /*
2234         * PLX
2235         */
2236        {
2237                .vendor         = PCI_VENDOR_ID_PLX,
2238                .device         = PCI_DEVICE_ID_PLX_9050,
2239                .subvendor      = PCI_SUBVENDOR_ID_EXSYS,
2240                .subdevice      = PCI_SUBDEVICE_ID_EXSYS_4055,
2241                .init           = pci_plx9050_init,
2242                .setup          = pci_default_setup,
2243                .exit           = pci_plx9050_exit,
2244        },
2245        {
2246                .vendor         = PCI_VENDOR_ID_PLX,
2247                .device         = PCI_DEVICE_ID_PLX_9050,
2248                .subvendor      = PCI_SUBVENDOR_ID_KEYSPAN,
2249                .subdevice      = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
2250                .init           = pci_plx9050_init,
2251                .setup          = pci_default_setup,
2252                .exit           = pci_plx9050_exit,
2253        },
2254        {
2255                .vendor         = PCI_VENDOR_ID_PLX,
2256                .device         = PCI_DEVICE_ID_PLX_ROMULUS,
2257                .subvendor      = PCI_VENDOR_ID_PLX,
2258                .subdevice      = PCI_DEVICE_ID_PLX_ROMULUS,
2259                .init           = pci_plx9050_init,
2260                .setup          = pci_default_setup,
2261                .exit           = pci_plx9050_exit,
2262        },
2263        {
2264                .vendor     = PCI_VENDOR_ID_ACCESIO,
2265                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SDB,
2266                .subvendor  = PCI_ANY_ID,
2267                .subdevice  = PCI_ANY_ID,
2268                .setup      = pci_pericom_setup_four_at_eight,
2269        },
2270        {
2271                .vendor     = PCI_VENDOR_ID_ACCESIO,
2272                .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4S,
2273                .subvendor  = PCI_ANY_ID,
2274                .subdevice  = PCI_ANY_ID,
2275                .setup      = pci_pericom_setup_four_at_eight,
2276        },
2277        {
2278                .vendor     = PCI_VENDOR_ID_ACCESIO,
2279                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4DB,
2280                .subvendor  = PCI_ANY_ID,
2281                .subdevice  = PCI_ANY_ID,
2282                .setup      = pci_pericom_setup_four_at_eight,
2283        },
2284        {
2285                .vendor     = PCI_VENDOR_ID_ACCESIO,
2286                .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM232_4,
2287                .subvendor  = PCI_ANY_ID,
2288                .subdevice  = PCI_ANY_ID,
2289                .setup      = pci_pericom_setup_four_at_eight,
2290        },
2291        {
2292                .vendor     = PCI_VENDOR_ID_ACCESIO,
2293                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SMDB,
2294                .subvendor  = PCI_ANY_ID,
2295                .subdevice  = PCI_ANY_ID,
2296                .setup      = pci_pericom_setup_four_at_eight,
2297        },
2298        {
2299                .vendor     = PCI_VENDOR_ID_ACCESIO,
2300                .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_COM_4SM,
2301                .subvendor  = PCI_ANY_ID,
2302                .subdevice  = PCI_ANY_ID,
2303                .setup      = pci_pericom_setup_four_at_eight,
2304        },
2305        {
2306                .vendor     = PCI_VENDOR_ID_ACCESIO,
2307                .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM422_4,
2308                .subvendor  = PCI_ANY_ID,
2309                .subdevice  = PCI_ANY_ID,
2310                .setup      = pci_pericom_setup_four_at_eight,
2311        },
2312        {
2313                .vendor     = PCI_VENDOR_ID_ACCESIO,
2314                .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM485_4,
2315                .subvendor  = PCI_ANY_ID,
2316                .subdevice  = PCI_ANY_ID,
2317                .setup      = pci_pericom_setup_four_at_eight,
2318        },
2319        {
2320                .vendor     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4S,
2321                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM232_4,
2322                .subvendor  = PCI_ANY_ID,
2323                .subdevice  = PCI_ANY_ID,
2324                .setup      = pci_pericom_setup_four_at_eight,
2325        },
2326        {
2327                .vendor     = PCI_VENDOR_ID_ACCESIO,
2328                .device     = PCI_DEVICE_ID_ACCESIO_MPCIE_ICM232_4,
2329                .subvendor  = PCI_ANY_ID,
2330                .subdevice  = PCI_ANY_ID,
2331                .setup      = pci_pericom_setup_four_at_eight,
2332        },
2333        {
2334                .vendor     = PCI_VENDOR_ID_ACCESIO,
2335                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM422_4,
2336                .subvendor  = PCI_ANY_ID,
2337                .subdevice  = PCI_ANY_ID,
2338                .setup      = pci_pericom_setup_four_at_eight,
2339        },
2340        {
2341                .vendor     = PCI_VENDOR_ID_ACCESIO,
2342                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM485_4,
2343                .subvendor  = PCI_ANY_ID,
2344                .subdevice  = PCI_ANY_ID,
2345                .setup      = pci_pericom_setup_four_at_eight,
2346        },
2347        {
2348                .vendor     = PCI_VENDOR_ID_ACCESIO,
2349                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM232_4,
2350                .subvendor  = PCI_ANY_ID,
2351                .subdevice  = PCI_ANY_ID,
2352                .setup      = pci_pericom_setup_four_at_eight,
2353        },
2354        {
2355                .vendor     = PCI_VENDOR_ID_ACCESIO,
2356                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_COM_4SM,
2357                .subvendor  = PCI_ANY_ID,
2358                .subdevice  = PCI_ANY_ID,
2359                .setup      = pci_pericom_setup_four_at_eight,
2360        },
2361        {
2362                .vendor     = PCI_VENDOR_ID_ACCESIO,
2363                .device     = PCI_DEVICE_ID_ACCESIO_PCIE_ICM_4SM,
2364                .subvendor  = PCI_ANY_ID,
2365                .subdevice  = PCI_ANY_ID,
2366                .setup      = pci_pericom_setup_four_at_eight,
2367        },
2368        {
2369                .vendor     = PCI_VENDOR_ID_ACCESIO,
2370                .device     = PCI_ANY_ID,
2371                .subvendor  = PCI_ANY_ID,
2372                .subdevice  = PCI_ANY_ID,
2373                .setup      = pci_pericom_setup,
2374        },      /*
2375         * SBS Technologies, Inc., PMC-OCTALPRO 232
2376         */
2377        {
2378                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2379                .device         = PCI_DEVICE_ID_OCTPRO,
2380                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2381                .subdevice      = PCI_SUBDEVICE_ID_OCTPRO232,
2382                .init           = sbs_init,
2383                .setup          = sbs_setup,
2384                .exit           = sbs_exit,
2385        },
2386        /*
2387         * SBS Technologies, Inc., PMC-OCTALPRO 422
2388         */
2389        {
2390                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2391                .device         = PCI_DEVICE_ID_OCTPRO,
2392                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2393                .subdevice      = PCI_SUBDEVICE_ID_OCTPRO422,
2394                .init           = sbs_init,
2395                .setup          = sbs_setup,
2396                .exit           = sbs_exit,
2397        },
2398        /*
2399         * SBS Technologies, Inc., P-Octal 232
2400         */
2401        {
2402                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2403                .device         = PCI_DEVICE_ID_OCTPRO,
2404                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2405                .subdevice      = PCI_SUBDEVICE_ID_POCTAL232,
2406                .init           = sbs_init,
2407                .setup          = sbs_setup,
2408                .exit           = sbs_exit,
2409        },
2410        /*
2411         * SBS Technologies, Inc., P-Octal 422
2412         */
2413        {
2414                .vendor         = PCI_VENDOR_ID_SBSMODULARIO,
2415                .device         = PCI_DEVICE_ID_OCTPRO,
2416                .subvendor      = PCI_SUBVENDOR_ID_SBSMODULARIO,
2417                .subdevice      = PCI_SUBDEVICE_ID_POCTAL422,
2418                .init           = sbs_init,
2419                .setup          = sbs_setup,
2420                .exit           = sbs_exit,
2421        },
2422        /*
2423         * SIIG cards - these may be called via parport_serial
2424         */
2425        {
2426                .vendor         = PCI_VENDOR_ID_SIIG,
2427                .device         = PCI_ANY_ID,
2428                .subvendor      = PCI_ANY_ID,
2429                .subdevice      = PCI_ANY_ID,
2430                .init           = pci_siig_init,
2431                .setup          = pci_siig_setup,
2432        },
2433        /*
2434         * Titan cards
2435         */
2436        {
2437                .vendor         = PCI_VENDOR_ID_TITAN,
2438                .device         = PCI_DEVICE_ID_TITAN_400L,
2439                .subvendor      = PCI_ANY_ID,
2440                .subdevice      = PCI_ANY_ID,
2441                .setup          = titan_400l_800l_setup,
2442        },
2443        {
2444                .vendor         = PCI_VENDOR_ID_TITAN,
2445                .device         = PCI_DEVICE_ID_TITAN_800L,
2446                .subvendor      = PCI_ANY_ID,
2447                .subdevice      = PCI_ANY_ID,
2448                .setup          = titan_400l_800l_setup,
2449        },
2450        /*
2451         * Timedia cards
2452         */
2453        {
2454                .vendor         = PCI_VENDOR_ID_TIMEDIA,
2455                .device         = PCI_DEVICE_ID_TIMEDIA_1889,
2456                .subvendor      = PCI_VENDOR_ID_TIMEDIA,
2457                .subdevice      = PCI_ANY_ID,
2458                .probe          = pci_timedia_probe,
2459                .init           = pci_timedia_init,
2460                .setup          = pci_timedia_setup,
2461        },
2462        {
2463                .vendor         = PCI_VENDOR_ID_TIMEDIA,
2464                .device         = PCI_ANY_ID,
2465                .subvendor      = PCI_ANY_ID,
2466                .subdevice      = PCI_ANY_ID,
2467                .setup          = pci_timedia_setup,
2468        },
2469        /*
2470         * Sunix PCI serial boards
2471         */
2472        {
2473                .vendor         = PCI_VENDOR_ID_SUNIX,
2474                .device         = PCI_DEVICE_ID_SUNIX_1999,
2475                .subvendor      = PCI_VENDOR_ID_SUNIX,
2476                .subdevice      = PCI_ANY_ID,
2477                .setup          = pci_sunix_setup,
2478        },
2479        /*
2480         * Xircom cards
2481         */
2482        {
2483                .vendor         = PCI_VENDOR_ID_XIRCOM,
2484                .device         = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2485                .subvendor      = PCI_ANY_ID,
2486                .subdevice      = PCI_ANY_ID,
2487                .init           = pci_xircom_init,
2488                .setup          = pci_default_setup,
2489        },
2490        /*
2491         * Netmos cards - these may be called via parport_serial
2492         */
2493        {
2494                .vendor         = PCI_VENDOR_ID_NETMOS,
2495                .device         = PCI_ANY_ID,
2496                .subvendor      = PCI_ANY_ID,
2497                .subdevice      = PCI_ANY_ID,
2498                .init           = pci_netmos_init,
2499                .setup          = pci_netmos_9900_setup,
2500        },
2501        /*
2502         * EndRun Technologies
2503        */
2504        {
2505                .vendor         = PCI_VENDOR_ID_ENDRUN,
2506                .device         = PCI_ANY_ID,
2507                .subvendor      = PCI_ANY_ID,
2508                .subdevice      = PCI_ANY_ID,
2509                .init           = pci_endrun_init,
2510                .setup          = pci_default_setup,
2511        },
2512        /*
2513         * For Oxford Semiconductor Tornado based devices
2514         */
2515        {
2516                .vendor         = PCI_VENDOR_ID_OXSEMI,
2517                .device         = PCI_ANY_ID,
2518                .subvendor      = PCI_ANY_ID,
2519                .subdevice      = PCI_ANY_ID,
2520                .init           = pci_oxsemi_tornado_init,
2521                .setup          = pci_default_setup,
2522        },
2523        {
2524                .vendor         = PCI_VENDOR_ID_MAINPINE,
2525                .device         = PCI_ANY_ID,
2526                .subvendor      = PCI_ANY_ID,
2527                .subdevice      = PCI_ANY_ID,
2528                .init           = pci_oxsemi_tornado_init,
2529                .setup          = pci_default_setup,
2530        },
2531        {
2532                .vendor         = PCI_VENDOR_ID_DIGI,
2533                .device         = PCIE_DEVICE_ID_NEO_2_OX_IBM,
2534                .subvendor              = PCI_SUBVENDOR_ID_IBM,
2535                .subdevice              = PCI_ANY_ID,
2536                .init                   = pci_oxsemi_tornado_init,
2537                .setup          = pci_default_setup,
2538        },
2539        {
2540                .vendor         = PCI_VENDOR_ID_INTEL,
2541                .device         = 0x8811,
2542                .subvendor      = PCI_ANY_ID,
2543                .subdevice      = PCI_ANY_ID,
2544                .init           = pci_eg20t_init,
2545                .setup          = pci_default_setup,
2546        },
2547        {
2548                .vendor         = PCI_VENDOR_ID_INTEL,
2549                .device         = 0x8812,
2550                .subvendor      = PCI_ANY_ID,
2551                .subdevice      = PCI_ANY_ID,
2552                .init           = pci_eg20t_init,
2553                .setup          = pci_default_setup,
2554        },
2555        {
2556                .vendor         = PCI_VENDOR_ID_INTEL,
2557                .device         = 0x8813,
2558                .subvendor      = PCI_ANY_ID,
2559                .subdevice      = PCI_ANY_ID,
2560                .init           = pci_eg20t_init,
2561                .setup          = pci_default_setup,
2562        },
2563        {
2564                .vendor         = PCI_VENDOR_ID_INTEL,
2565                .device         = 0x8814,
2566                .subvendor      = PCI_ANY_ID,
2567                .subdevice      = PCI_ANY_ID,
2568                .init           = pci_eg20t_init,
2569                .setup          = pci_default_setup,
2570        },
2571        {
2572                .vendor         = 0x10DB,
2573                .device         = 0x8027,
2574                .subvendor      = PCI_ANY_ID,
2575                .subdevice      = PCI_ANY_ID,
2576                .init           = pci_eg20t_init,
2577                .setup          = pci_default_setup,
2578        },
2579        {
2580                .vendor         = 0x10DB,
2581                .device         = 0x8028,
2582                .subvendor      = PCI_ANY_ID,
2583                .subdevice      = PCI_ANY_ID,
2584                .init           = pci_eg20t_init,
2585                .setup          = pci_default_setup,
2586        },
2587        {
2588                .vendor         = 0x10DB,
2589                .device         = 0x8029,
2590                .subvendor      = PCI_ANY_ID,
2591                .subdevice      = PCI_ANY_ID,
2592                .init           = pci_eg20t_init,
2593                .setup          = pci_default_setup,
2594        },
2595        {
2596                .vendor         = 0x10DB,
2597                .device         = 0x800C,
2598                .subvendor      = PCI_ANY_ID,
2599                .subdevice      = PCI_ANY_ID,
2600                .init           = pci_eg20t_init,
2601                .setup          = pci_default_setup,
2602        },
2603        {
2604                .vendor         = 0x10DB,
2605                .device         = 0x800D,
2606                .subvendor      = PCI_ANY_ID,
2607                .subdevice      = PCI_ANY_ID,
2608                .init           = pci_eg20t_init,
2609                .setup          = pci_default_setup,
2610        },
2611        /*
2612         * Cronyx Omega PCI (PLX-chip based)
2613         */
2614        {
2615                .vendor         = PCI_VENDOR_ID_PLX,
2616                .device         = PCI_DEVICE_ID_PLX_CRONYX_OMEGA,
2617                .subvendor      = PCI_ANY_ID,
2618                .subdevice      = PCI_ANY_ID,
2619                .setup          = pci_omegapci_setup,
2620        },
2621        /* WCH CH353 1S1P card (16550 clone) */
2622        {
2623                .vendor         = PCI_VENDOR_ID_WCH,
2624                .device         = PCI_DEVICE_ID_WCH_CH353_1S1P,
2625                .subvendor      = PCI_ANY_ID,
2626                .subdevice      = PCI_ANY_ID,
2627                .setup          = pci_wch_ch353_setup,
2628        },
2629        /* WCH CH353 2S1P card (16550 clone) */
2630        {
2631                .vendor         = PCI_VENDOR_ID_WCH,
2632                .device         = PCI_DEVICE_ID_WCH_CH353_2S1P,
2633                .subvendor      = PCI_ANY_ID,
2634                .subdevice      = PCI_ANY_ID,
2635                .setup          = pci_wch_ch353_setup,
2636        },
2637        /* WCH CH353 4S card (16550 clone) */
2638        {
2639                .vendor         = PCI_VENDOR_ID_WCH,
2640                .device         = PCI_DEVICE_ID_WCH_CH353_4S,
2641                .subvendor      = PCI_ANY_ID,
2642                .subdevice      = PCI_ANY_ID,
2643                .setup          = pci_wch_ch353_setup,
2644        },
2645        /* WCH CH353 2S1PF card (16550 clone) */
2646        {
2647                .vendor         = PCI_VENDOR_ID_WCH,
2648                .device         = PCI_DEVICE_ID_WCH_CH353_2S1PF,
2649                .subvendor      = PCI_ANY_ID,
2650                .subdevice      = PCI_ANY_ID,
2651                .setup          = pci_wch_ch353_setup,
2652        },
2653        /* WCH CH352 2S card (16550 clone) */
2654        {
2655                .vendor         = PCI_VENDOR_ID_WCH,
2656                .device         = PCI_DEVICE_ID_WCH_CH352_2S,
2657                .subvendor      = PCI_ANY_ID,
2658                .subdevice      = PCI_ANY_ID,
2659                .setup          = pci_wch_ch353_setup,
2660        },
2661        /* WCH CH355 4S card (16550 clone) */
2662        {
2663                .vendor         = PCI_VENDOR_ID_WCH,
2664                .device         = PCI_DEVICE_ID_WCH_CH355_4S,
2665                .subvendor      = PCI_ANY_ID,
2666                .subdevice      = PCI_ANY_ID,
2667                .setup          = pci_wch_ch355_setup,
2668        },
2669        /* WCH CH382 2S card (16850 clone) */
2670        {
2671                .vendor         = PCIE_VENDOR_ID_WCH,
2672                .device         = PCIE_DEVICE_ID_WCH_CH382_2S,
2673                .subvendor      = PCI_ANY_ID,
2674                .subdevice      = PCI_ANY_ID,
2675                .setup          = pci_wch_ch38x_setup,
2676        },
2677        /* WCH CH382 2S1P card (16850 clone) */
2678        {
2679                .vendor         = PCIE_VENDOR_ID_WCH,
2680                .device         = PCIE_DEVICE_ID_WCH_CH382_2S1P,
2681                .subvendor      = PCI_ANY_ID,
2682                .subdevice      = PCI_ANY_ID,
2683                .setup          = pci_wch_ch38x_setup,
2684        },
2685        /* WCH CH384 4S card (16850 clone) */
2686        {
2687                .vendor         = PCIE_VENDOR_ID_WCH,
2688                .device         = PCIE_DEVICE_ID_WCH_CH384_4S,
2689                .subvendor      = PCI_ANY_ID,
2690                .subdevice      = PCI_ANY_ID,
2691                .setup          = pci_wch_ch38x_setup,
2692        },
2693        /* WCH CH384 8S card (16850 clone) */
2694        {
2695                .vendor         = PCIE_VENDOR_ID_WCH,
2696                .device         = PCIE_DEVICE_ID_WCH_CH384_8S,
2697                .subvendor      = PCI_ANY_ID,
2698                .subdevice      = PCI_ANY_ID,
2699                .init           = pci_wch_ch38x_init,
2700                .exit           = pci_wch_ch38x_exit,
2701                .setup          = pci_wch_ch38x_setup,
2702        },
2703        /*
2704         * ASIX devices with FIFO bug
2705         */
2706        {
2707                .vendor         = PCI_VENDOR_ID_ASIX,
2708                .device         = PCI_ANY_ID,
2709                .subvendor      = PCI_ANY_ID,
2710                .subdevice      = PCI_ANY_ID,
2711                .setup          = pci_asix_setup,
2712        },
2713        /*
2714         * Broadcom TruManage (NetXtreme)
2715         */
2716        {
2717                .vendor         = PCI_VENDOR_ID_BROADCOM,
2718                .device         = PCI_DEVICE_ID_BROADCOM_TRUMANAGE,
2719                .subvendor      = PCI_ANY_ID,
2720                .subdevice      = PCI_ANY_ID,
2721                .setup          = pci_brcm_trumanage_setup,
2722        },
2723        {
2724                .vendor         = 0x1c29,
2725                .device         = 0x1104,
2726                .subvendor      = PCI_ANY_ID,
2727                .subdevice      = PCI_ANY_ID,
2728                .setup          = pci_fintek_setup,
2729                .init           = pci_fintek_init,
2730        },
2731        {
2732                .vendor         = 0x1c29,
2733                .device         = 0x1108,
2734                .subvendor      = PCI_ANY_ID,
2735                .subdevice      = PCI_ANY_ID,
2736                .setup          = pci_fintek_setup,
2737                .init           = pci_fintek_init,
2738        },
2739        {
2740                .vendor         = 0x1c29,
2741                .device         = 0x1112,
2742                .subvendor      = PCI_ANY_ID,
2743                .subdevice      = PCI_ANY_ID,
2744                .setup          = pci_fintek_setup,
2745                .init           = pci_fintek_init,
2746        },
2747        /*
2748         * MOXA
2749         */
2750        {
2751                .vendor         = PCI_VENDOR_ID_MOXA,
2752                .device         = PCI_ANY_ID,
2753                .subvendor      = PCI_ANY_ID,
2754                .subdevice      = PCI_ANY_ID,
2755                .setup          = pci_moxa_setup,
2756        },
2757        {
2758                .vendor         = 0x1c29,
2759                .device         = 0x1204,
2760                .subvendor      = PCI_ANY_ID,
2761                .subdevice      = PCI_ANY_ID,
2762                .setup          = pci_fintek_f815xxa_setup,
2763                .init           = pci_fintek_f815xxa_init,
2764        },
2765        {
2766                .vendor         = 0x1c29,
2767                .device         = 0x1208,
2768                .subvendor      = PCI_ANY_ID,
2769                .subdevice      = PCI_ANY_ID,
2770                .setup          = pci_fintek_f815xxa_setup,
2771                .init           = pci_fintek_f815xxa_init,
2772        },
2773        {
2774                .vendor         = 0x1c29,
2775                .device         = 0x1212,
2776                .subvendor      = PCI_ANY_ID,
2777                .subdevice      = PCI_ANY_ID,
2778                .setup          = pci_fintek_f815xxa_setup,
2779                .init           = pci_fintek_f815xxa_init,
2780        },
2781
2782        /*
2783         * Default "match everything" terminator entry
2784         */
2785        {
2786                .vendor         = PCI_ANY_ID,
2787                .device         = PCI_ANY_ID,
2788                .subvendor      = PCI_ANY_ID,
2789                .subdevice      = PCI_ANY_ID,
2790                .setup          = pci_default_setup,
2791        }
2792};
2793
2794static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
2795{
2796        return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
2797}
2798
2799static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
2800{
2801        struct pci_serial_quirk *quirk;
2802
2803        for (quirk = pci_serial_quirks; ; quirk++)
2804                if (quirk_id_matches(quirk->vendor, dev->vendor) &&
2805                    quirk_id_matches(quirk->device, dev->device) &&
2806                    quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
2807                    quirk_id_matches(quirk->subdevice, dev->subsystem_device))
2808                        break;
2809        return quirk;
2810}
2811
2812/*
2813 * This is the configuration table for all of the PCI serial boards
2814 * which we support.  It is directly indexed by the pci_board_num_t enum
2815 * value, which is encoded in the pci_device_id PCI probe table's
2816 * driver_data member.
2817 *
2818 * The makeup of these names are:
2819 *  pbn_bn{_bt}_n_baud{_offsetinhex}
2820 *
2821 *  bn          = PCI BAR number
2822 *  bt          = Index using PCI BARs
2823 *  n           = number of serial ports
2824 *  baud        = baud rate
2825 *  offsetinhex = offset for each sequential port (in hex)
2826 *
2827 * This table is sorted by (in order): bn, bt, baud, offsetindex, n.
2828 *
2829 * Please note: in theory if n = 1, _bt infix should make no difference.
2830 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
2831 */
2832enum pci_board_num_t {
2833        pbn_default = 0,
2834
2835        pbn_b0_1_115200,
2836        pbn_b0_2_115200,
2837        pbn_b0_4_115200,
2838        pbn_b0_5_115200,
2839        pbn_b0_8_115200,
2840
2841        pbn_b0_1_921600,
2842        pbn_b0_2_921600,
2843        pbn_b0_4_921600,
2844
2845        pbn_b0_2_1130000,
2846
2847        pbn_b0_4_1152000,
2848
2849        pbn_b0_4_1250000,
2850
2851        pbn_b0_2_1843200,
2852        pbn_b0_4_1843200,
2853
2854        pbn_b0_1_3906250,
2855
2856        pbn_b0_bt_1_115200,
2857        pbn_b0_bt_2_115200,
2858        pbn_b0_bt_4_115200,
2859        pbn_b0_bt_8_115200,
2860
2861        pbn_b0_bt_1_460800,
2862        pbn_b0_bt_2_460800,
2863        pbn_b0_bt_4_460800,
2864
2865        pbn_b0_bt_1_921600,
2866        pbn_b0_bt_2_921600,
2867        pbn_b0_bt_4_921600,
2868        pbn_b0_bt_8_921600,
2869
2870        pbn_b1_1_115200,
2871        pbn_b1_2_115200,
2872        pbn_b1_4_115200,
2873        pbn_b1_8_115200,
2874        pbn_b1_16_115200,
2875
2876        pbn_b1_1_921600,
2877        pbn_b1_2_921600,
2878        pbn_b1_4_921600,
2879        pbn_b1_8_921600,
2880
2881        pbn_b1_2_1250000,
2882
2883        pbn_b1_bt_1_115200,
2884        pbn_b1_bt_2_115200,
2885        pbn_b1_bt_4_115200,
2886
2887        pbn_b1_bt_2_921600,
2888
2889        pbn_b1_1_1382400,
2890        pbn_b1_2_1382400,
2891        pbn_b1_4_1382400,
2892        pbn_b1_8_1382400,
2893
2894        pbn_b2_1_115200,
2895        pbn_b2_2_115200,
2896        pbn_b2_4_115200,
2897        pbn_b2_8_115200,
2898
2899        pbn_b2_1_460800,
2900        pbn_b2_4_460800,
2901        pbn_b2_8_460800,
2902        pbn_b2_16_460800,
2903
2904        pbn_b2_1_921600,
2905        pbn_b2_4_921600,
2906        pbn_b2_8_921600,
2907
2908        pbn_b2_8_1152000,
2909
2910        pbn_b2_bt_1_115200,
2911        pbn_b2_bt_2_115200,
2912        pbn_b2_bt_4_115200,
2913
2914        pbn_b2_bt_2_921600,
2915        pbn_b2_bt_4_921600,
2916
2917        pbn_b3_2_115200,
2918        pbn_b3_4_115200,
2919        pbn_b3_8_115200,
2920
2921        pbn_b4_bt_2_921600,
2922        pbn_b4_bt_4_921600,
2923        pbn_b4_bt_8_921600,
2924
2925        /*
2926         * Board-specific versions.
2927         */
2928        pbn_panacom,
2929        pbn_panacom2,
2930        pbn_panacom4,
2931        pbn_plx_romulus,
2932        pbn_endrun_2_4000000,
2933        pbn_oxsemi,
2934        pbn_oxsemi_1_3906250,
2935        pbn_oxsemi_2_3906250,
2936        pbn_oxsemi_4_3906250,
2937        pbn_oxsemi_8_3906250,
2938        pbn_intel_i960,
2939        pbn_sgi_ioc3,
2940        pbn_computone_4,
2941        pbn_computone_6,
2942        pbn_computone_8,
2943        pbn_sbsxrsio,
2944        pbn_pasemi_1682M,
2945        pbn_ni8430_2,
2946        pbn_ni8430_4,
2947        pbn_ni8430_8,
2948        pbn_ni8430_16,
2949        pbn_ADDIDATA_PCIe_1_3906250,
2950        pbn_ADDIDATA_PCIe_2_3906250,
2951        pbn_ADDIDATA_PCIe_4_3906250,
2952        pbn_ADDIDATA_PCIe_8_3906250,
2953        pbn_ce4100_1_115200,
2954        pbn_omegapci,
2955        pbn_NETMOS9900_2s_115200,
2956        pbn_brcm_trumanage,
2957        pbn_fintek_4,
2958        pbn_fintek_8,
2959        pbn_fintek_12,
2960        pbn_fintek_F81504A,
2961        pbn_fintek_F81508A,
2962        pbn_fintek_F81512A,
2963        pbn_wch382_2,
2964        pbn_wch384_4,
2965        pbn_wch384_8,
2966        pbn_pericom_PI7C9X7951,
2967        pbn_pericom_PI7C9X7952,
2968        pbn_pericom_PI7C9X7954,
2969        pbn_pericom_PI7C9X7958,
2970        pbn_sunix_pci_1s,
2971        pbn_sunix_pci_2s,
2972        pbn_sunix_pci_4s,
2973        pbn_sunix_pci_8s,
2974        pbn_sunix_pci_16s,
2975        pbn_titan_1_4000000,
2976        pbn_titan_2_4000000,
2977        pbn_titan_4_4000000,
2978        pbn_titan_8_4000000,
2979        pbn_moxa8250_2p,
2980        pbn_moxa8250_4p,
2981        pbn_moxa8250_8p,
2982};
2983
2984/*
2985 * uart_offset - the space between channels
2986 * reg_shift   - describes how the UART registers are mapped
2987 *               to PCI memory by the card.
2988 * For example IER register on SBS, Inc. PMC-OctPro is located at
2989 * offset 0x10 from the UART base, while UART_IER is defined as 1
2990 * in include/linux/serial_reg.h,
2991 * see first lines of serial_in() and serial_out() in 8250.c
2992*/
2993
2994static struct pciserial_board pci_boards[] = {
2995        [pbn_default] = {
2996                .flags          = FL_BASE0,
2997                .num_ports      = 1,
2998                .base_baud      = 115200,
2999                .uart_offset    = 8,
3000        },
3001        [pbn_b0_1_115200] = {
3002                .flags          = FL_BASE0,
3003                .num_ports      = 1,
3004                .base_baud      = 115200,
3005                .uart_offset    = 8,
3006        },
3007        [pbn_b0_2_115200] = {
3008                .flags          = FL_BASE0,
3009                .num_ports      = 2,
3010                .base_baud      = 115200,
3011                .uart_offset    = 8,
3012        },
3013        [pbn_b0_4_115200] = {
3014                .flags          = FL_BASE0,
3015                .num_ports      = 4,
3016                .base_baud      = 115200,
3017                .uart_offset    = 8,
3018        },
3019        [pbn_b0_5_115200] = {
3020                .flags          = FL_BASE0,
3021                .num_ports      = 5,
3022                .base_baud      = 115200,
3023                .uart_offset    = 8,
3024        },
3025        [pbn_b0_8_115200] = {
3026                .flags          = FL_BASE0,
3027                .num_ports      = 8,
3028                .base_baud      = 115200,
3029                .uart_offset    = 8,
3030        },
3031        [pbn_b0_1_921600] = {
3032                .flags          = FL_BASE0,
3033                .num_ports      = 1,
3034                .base_baud      = 921600,
3035                .uart_offset    = 8,
3036        },
3037        [pbn_b0_2_921600] = {
3038                .flags          = FL_BASE0,
3039                .num_ports      = 2,
3040                .base_baud      = 921600,
3041                .uart_offset    = 8,
3042        },
3043        [pbn_b0_4_921600] = {
3044                .flags          = FL_BASE0,
3045                .num_ports      = 4,
3046                .base_baud      = 921600,
3047                .uart_offset    = 8,
3048        },
3049
3050        [pbn_b0_2_1130000] = {
3051                .flags          = FL_BASE0,
3052                .num_ports      = 2,
3053                .base_baud      = 1130000,
3054                .uart_offset    = 8,
3055        },
3056
3057        [pbn_b0_4_1152000] = {
3058                .flags          = FL_BASE0,
3059                .num_ports      = 4,
3060                .base_baud      = 1152000,
3061                .uart_offset    = 8,
3062        },
3063
3064        [pbn_b0_4_1250000] = {
3065                .flags          = FL_BASE0,
3066                .num_ports      = 4,
3067                .base_baud      = 1250000,
3068                .uart_offset    = 8,
3069        },
3070
3071        [pbn_b0_2_1843200] = {
3072                .flags          = FL_BASE0,
3073                .num_ports      = 2,
3074                .base_baud      = 1843200,
3075                .uart_offset    = 8,
3076        },
3077        [pbn_b0_4_1843200] = {
3078                .flags          = FL_BASE0,
3079                .num_ports      = 4,
3080                .base_baud      = 1843200,
3081                .uart_offset    = 8,
3082        },
3083
3084        [pbn_b0_1_3906250] = {
3085                .flags          = FL_BASE0,
3086                .num_ports      = 1,
3087                .base_baud      = 3906250,
3088                .uart_offset    = 8,
3089        },
3090
3091        [pbn_b0_bt_1_115200] = {
3092                .flags          = FL_BASE0|FL_BASE_BARS,
3093                .num_ports      = 1,
3094                .base_baud      = 115200,
3095                .uart_offset    = 8,
3096        },
3097        [pbn_b0_bt_2_115200] = {
3098                .flags          = FL_BASE0|FL_BASE_BARS,
3099                .num_ports      = 2,
3100                .base_baud      = 115200,
3101                .uart_offset    = 8,
3102        },
3103        [pbn_b0_bt_4_115200] = {
3104                .flags          = FL_BASE0|FL_BASE_BARS,
3105                .num_ports      = 4,
3106                .base_baud      = 115200,
3107                .uart_offset    = 8,
3108        },
3109        [pbn_b0_bt_8_115200] = {
3110                .flags          = FL_BASE0|FL_BASE_BARS,
3111                .num_ports      = 8,
3112                .base_baud      = 115200,
3113                .uart_offset    = 8,
3114        },
3115
3116        [pbn_b0_bt_1_460800] = {
3117                .flags          = FL_BASE0|FL_BASE_BARS,
3118                .num_ports      = 1,
3119                .base_baud      = 460800,
3120                .uart_offset    = 8,
3121        },
3122        [pbn_b0_bt_2_460800] = {
3123                .flags          = FL_BASE0|FL_BASE_BARS,
3124                .num_ports      = 2,
3125                .base_baud      = 460800,
3126                .uart_offset    = 8,
3127        },
3128        [pbn_b0_bt_4_460800] = {
3129                .flags          = FL_BASE0|FL_BASE_BARS,
3130                .num_ports      = 4,
3131                .base_baud      = 460800,
3132                .uart_offset    = 8,
3133        },
3134
3135        [pbn_b0_bt_1_921600] = {
3136                .flags          = FL_BASE0|FL_BASE_BARS,
3137                .num_ports      = 1,
3138                .base_baud      = 921600,
3139                .uart_offset    = 8,
3140        },
3141        [pbn_b0_bt_2_921600] = {
3142                .flags          = FL_BASE0|FL_BASE_BARS,
3143                .num_ports      = 2,
3144                .base_baud      = 921600,
3145                .uart_offset    = 8,
3146        },
3147        [pbn_b0_bt_4_921600] = {
3148                .flags          = FL_BASE0|FL_BASE_BARS,
3149                .num_ports      = 4,
3150                .base_baud      = 921600,
3151                .uart_offset    = 8,
3152        },
3153        [pbn_b0_bt_8_921600] = {
3154                .flags          = FL_BASE0|FL_BASE_BARS,
3155                .num_ports      = 8,
3156                .base_baud      = 921600,
3157                .uart_offset    = 8,
3158        },
3159
3160        [pbn_b1_1_115200] = {
3161                .flags          = FL_BASE1,
3162                .num_ports      = 1,
3163                .base_baud      = 115200,
3164                .uart_offset    = 8,
3165        },
3166        [pbn_b1_2_115200] = {
3167                .flags          = FL_BASE1,
3168                .num_ports      = 2,
3169                .base_baud      = 115200,
3170                .uart_offset    = 8,
3171        },
3172        [pbn_b1_4_115200] = {
3173                .flags          = FL_BASE1,
3174                .num_ports      = 4,
3175                .base_baud      = 115200,
3176                .uart_offset    = 8,
3177        },
3178        [pbn_b1_8_115200] = {
3179                .flags          = FL_BASE1,
3180                .num_ports      = 8,
3181                .base_baud      = 115200,
3182                .uart_offset    = 8,
3183        },
3184        [pbn_b1_16_115200] = {
3185                .flags          = FL_BASE1,
3186                .num_ports      = 16,
3187                .base_baud      = 115200,
3188                .uart_offset    = 8,
3189        },
3190
3191        [pbn_b1_1_921600] = {
3192                .flags          = FL_BASE1,
3193                .num_ports      = 1,
3194                .base_baud      = 921600,
3195                .uart_offset    = 8,
3196        },
3197        [pbn_b1_2_921600] = {
3198                .flags          = FL_BASE1,
3199                .num_ports      = 2,
3200                .base_baud      = 921600,
3201                .uart_offset    = 8,
3202        },
3203        [pbn_b1_4_921600] = {
3204                .flags          = FL_BASE1,
3205                .num_ports      = 4,
3206                .base_baud      = 921600,
3207                .uart_offset    = 8,
3208        },
3209        [pbn_b1_8_921600] = {
3210                .flags          = FL_BASE1,
3211                .num_ports      = 8,
3212                .base_baud      = 921600,
3213                .uart_offset    = 8,
3214        },
3215        [pbn_b1_2_1250000] = {
3216                .flags          = FL_BASE1,
3217                .num_ports      = 2,
3218                .base_baud      = 1250000,
3219                .uart_offset    = 8,
3220        },
3221
3222        [pbn_b1_bt_1_115200] = {
3223                .flags          = FL_BASE1|FL_BASE_BARS,
3224                .num_ports      = 1,
3225                .base_baud      = 115200,
3226                .uart_offset    = 8,
3227        },
3228        [pbn_b1_bt_2_115200] = {
3229                .flags          = FL_BASE1|FL_BASE_BARS,
3230                .num_ports      = 2,
3231                .base_baud      = 115200,
3232                .uart_offset    = 8,
3233        },
3234        [pbn_b1_bt_4_115200] = {
3235                .flags          = FL_BASE1|FL_BASE_BARS,
3236                .num_ports      = 4,
3237                .base_baud      = 115200,
3238                .uart_offset    = 8,
3239        },
3240
3241        [pbn_b1_bt_2_921600] = {
3242                .flags          = FL_BASE1|FL_BASE_BARS,
3243                .num_ports      = 2,
3244                .base_baud      = 921600,
3245                .uart_offset    = 8,
3246        },
3247
3248        [pbn_b1_1_1382400] = {
3249                .flags          = FL_BASE1,
3250                .num_ports      = 1,
3251                .base_baud      = 1382400,
3252                .uart_offset    = 8,
3253        },
3254        [pbn_b1_2_1382400] = {
3255                .flags          = FL_BASE1,
3256                .num_ports      = 2,
3257                .base_baud      = 1382400,
3258                .uart_offset    = 8,
3259        },
3260        [pbn_b1_4_1382400] = {
3261                .flags          = FL_BASE1,
3262                .num_ports      = 4,
3263                .base_baud      = 1382400,
3264                .uart_offset    = 8,
3265        },
3266        [pbn_b1_8_1382400] = {
3267                .flags          = FL_BASE1,
3268                .num_ports      = 8,
3269                .base_baud      = 1382400,
3270                .uart_offset    = 8,
3271        },
3272
3273        [pbn_b2_1_115200] = {
3274                .flags          = FL_BASE2,
3275                .num_ports      = 1,
3276                .base_baud      = 115200,
3277                .uart_offset    = 8,
3278        },
3279        [pbn_b2_2_115200] = {
3280                .flags          = FL_BASE2,
3281                .num_ports      = 2,
3282                .base_baud      = 115200,
3283                .uart_offset    = 8,
3284        },
3285        [pbn_b2_4_115200] = {
3286                .flags          = FL_BASE2,
3287                .num_ports      = 4,
3288                .base_baud      = 115200,
3289                .uart_offset    = 8,
3290        },
3291        [pbn_b2_8_115200] = {
3292                .flags          = FL_BASE2,
3293                .num_ports      = 8,
3294                .base_baud      = 115200,
3295                .uart_offset    = 8,
3296        },
3297
3298        [pbn_b2_1_460800] = {
3299                .flags          = FL_BASE2,
3300                .num_ports      = 1,
3301                .base_baud      = 460800,
3302                .uart_offset    = 8,
3303        },
3304        [pbn_b2_4_460800] = {
3305                .flags          = FL_BASE2,
3306                .num_ports      = 4,
3307                .base_baud      = 460800,
3308                .uart_offset    = 8,
3309        },
3310        [pbn_b2_8_460800] = {
3311                .flags          = FL_BASE2,
3312                .num_ports      = 8,
3313                .base_baud      = 460800,
3314                .uart_offset    = 8,
3315        },
3316        [pbn_b2_16_460800] = {
3317                .flags          = FL_BASE2,
3318                .num_ports      = 16,
3319                .base_baud      = 460800,
3320                .uart_offset    = 8,
3321         },
3322
3323        [pbn_b2_1_921600] = {
3324                .flags          = FL_BASE2,
3325                .num_ports      = 1,
3326                .base_baud      = 921600,
3327                .uart_offset    = 8,
3328        },
3329        [pbn_b2_4_921600] = {
3330                .flags          = FL_BASE2,
3331                .num_ports      = 4,
3332                .base_baud      = 921600,
3333                .uart_offset    = 8,
3334        },
3335        [pbn_b2_8_921600] = {
3336                .flags          = FL_BASE2,
3337                .num_ports      = 8,
3338                .base_baud      = 921600,
3339                .uart_offset    = 8,
3340        },
3341
3342        [pbn_b2_8_1152000] = {
3343                .flags          = FL_BASE2,
3344                .num_ports      = 8,
3345                .base_baud      = 1152000,
3346                .uart_offset    = 8,
3347        },
3348
3349        [pbn_b2_bt_1_115200] = {
3350                .flags          = FL_BASE2|FL_BASE_BARS,
3351                .num_ports      = 1,
3352                .base_baud      = 115200,
3353                .uart_offset    = 8,
3354        },
3355        [pbn_b2_bt_2_115200] = {
3356                .flags          = FL_BASE2|FL_BASE_BARS,
3357                .num_ports      = 2,
3358                .base_baud      = 115200,
3359                .uart_offset    = 8,
3360        },
3361        [pbn_b2_bt_4_115200] = {
3362                .flags          = FL_BASE2|FL_BASE_BARS,
3363                .num_ports      = 4,
3364                .base_baud      = 115200,
3365                .uart_offset    = 8,
3366        },
3367
3368        [pbn_b2_bt_2_921600] = {
3369                .flags          = FL_BASE2|FL_BASE_BARS,
3370                .num_ports      = 2,
3371                .base_baud      = 921600,
3372                .uart_offset    = 8,
3373        },
3374        [pbn_b2_bt_4_921600] = {
3375                .flags          = FL_BASE2|FL_BASE_BARS,
3376                .num_ports      = 4,
3377                .base_baud      = 921600,
3378                .uart_offset    = 8,
3379        },
3380
3381        [pbn_b3_2_115200] = {
3382                .flags          = FL_BASE3,
3383                .num_ports      = 2,
3384                .base_baud      = 115200,
3385                .uart_offset    = 8,
3386        },
3387        [pbn_b3_4_115200] = {
3388                .flags          = FL_BASE3,
3389                .num_ports      = 4,
3390                .base_baud      = 115200,
3391                .uart_offset    = 8,
3392        },
3393        [pbn_b3_8_115200] = {
3394                .flags          = FL_BASE3,
3395                .num_ports      = 8,
3396                .base_baud      = 115200,
3397                .uart_offset    = 8,
3398        },
3399
3400        [pbn_b4_bt_2_921600] = {
3401                .flags          = FL_BASE4,
3402                .num_ports      = 2,
3403                .base_baud      = 921600,
3404                .uart_offset    = 8,
3405        },
3406        [pbn_b4_bt_4_921600] = {
3407                .flags          = FL_BASE4,
3408                .num_ports      = 4,
3409                .base_baud      = 921600,
3410                .uart_offset    = 8,
3411        },
3412        [pbn_b4_bt_8_921600] = {
3413                .flags          = FL_BASE4,
3414                .num_ports      = 8,
3415                .base_baud      = 921600,
3416                .uart_offset    = 8,
3417        },
3418
3419        /*
3420         * Entries following this are board-specific.
3421         */
3422
3423        /*
3424         * Panacom - IOMEM
3425         */
3426        [pbn_panacom] = {
3427                .flags          = FL_BASE2,
3428                .num_ports      = 2,
3429                .base_baud      = 921600,
3430                .uart_offset    = 0x400,
3431                .reg_shift      = 7,
3432        },
3433        [pbn_panacom2] = {
3434                .flags          = FL_BASE2|FL_BASE_BARS,
3435                .num_ports      = 2,
3436                .base_baud      = 921600,
3437                .uart_offset    = 0x400,
3438                .reg_shift      = 7,
3439        },
3440        [pbn_panacom4] = {
3441                .flags          = FL_BASE2|FL_BASE_BARS,
3442                .num_ports      = 4,
3443                .base_baud      = 921600,
3444                .uart_offset    = 0x400,
3445                .reg_shift      = 7,
3446        },
3447
3448        /* I think this entry is broken - the first_offset looks wrong --rmk */
3449        [pbn_plx_romulus] = {
3450                .flags          = FL_BASE2,
3451                .num_ports      = 4,
3452                .base_baud      = 921600,
3453                .uart_offset    = 8 << 2,
3454                .reg_shift      = 2,
3455                .first_offset   = 0x03,
3456        },
3457
3458        /*
3459         * EndRun Technologies
3460        * Uses the size of PCI Base region 0 to
3461        * signal now many ports are available
3462        * 2 port 952 Uart support
3463        */
3464        [pbn_endrun_2_4000000] = {
3465                .flags          = FL_BASE0,
3466                .num_ports      = 2,
3467                .base_baud      = 4000000,
3468                .uart_offset    = 0x200,
3469                .first_offset   = 0x1000,
3470        },
3471
3472        /*
3473         * This board uses the size of PCI Base region 0 to
3474         * signal now many ports are available
3475         */
3476        [pbn_oxsemi] = {
3477                .flags          = FL_BASE0|FL_REGION_SZ_CAP,
3478                .num_ports      = 32,
3479                .base_baud      = 115200,
3480                .uart_offset    = 8,
3481        },
3482        [pbn_oxsemi_1_3906250] = {
3483                .flags          = FL_BASE0,
3484                .num_ports      = 1,
3485                .base_baud      = 3906250,
3486                .uart_offset    = 0x200,
3487                .first_offset   = 0x1000,
3488        },
3489        [pbn_oxsemi_2_3906250] = {
3490                .flags          = FL_BASE0,
3491                .num_ports      = 2,
3492                .base_baud      = 3906250,
3493                .uart_offset    = 0x200,
3494                .first_offset   = 0x1000,
3495        },
3496        [pbn_oxsemi_4_3906250] = {
3497                .flags          = FL_BASE0,
3498                .num_ports      = 4,
3499                .base_baud      = 3906250,
3500                .uart_offset    = 0x200,
3501                .first_offset   = 0x1000,
3502        },
3503        [pbn_oxsemi_8_3906250] = {
3504                .flags          = FL_BASE0,
3505                .num_ports      = 8,
3506                .base_baud      = 3906250,
3507                .uart_offset    = 0x200,
3508                .first_offset   = 0x1000,
3509        },
3510
3511
3512        /*
3513         * EKF addition for i960 Boards form EKF with serial port.
3514         * Max 256 ports.
3515         */
3516        [pbn_intel_i960] = {
3517                .flags          = FL_BASE0,
3518                .num_ports      = 32,
3519                .base_baud      = 921600,
3520                .uart_offset    = 8 << 2,
3521                .reg_shift      = 2,
3522                .first_offset   = 0x10000,
3523        },
3524        [pbn_sgi_ioc3] = {
3525                .flags          = FL_BASE0|FL_NOIRQ,
3526                .num_ports      = 1,
3527                .base_baud      = 458333,
3528                .uart_offset    = 8,
3529                .reg_shift      = 0,
3530                .first_offset   = 0x20178,
3531        },
3532
3533        /*
3534         * Computone - uses IOMEM.
3535         */
3536        [pbn_computone_4] = {
3537                .flags          = FL_BASE0,
3538                .num_ports      = 4,
3539                .base_baud      = 921600,
3540                .uart_offset    = 0x40,
3541                .reg_shift      = 2,
3542                .first_offset   = 0x200,
3543        },
3544        [pbn_computone_6] = {
3545                .flags          = FL_BASE0,
3546                .num_ports      = 6,
3547                .base_baud      = 921600,
3548                .uart_offset    = 0x40,
3549                .reg_shift      = 2,
3550                .first_offset   = 0x200,
3551        },
3552        [pbn_computone_8] = {
3553                .flags          = FL_BASE0,
3554                .num_ports      = 8,
3555                .base_baud      = 921600,
3556                .uart_offset    = 0x40,
3557                .reg_shift      = 2,
3558                .first_offset   = 0x200,
3559        },
3560        [pbn_sbsxrsio] = {
3561                .flags          = FL_BASE0,
3562                .num_ports      = 8,
3563                .base_baud      = 460800,
3564                .uart_offset    = 256,
3565                .reg_shift      = 4,
3566        },
3567        /*
3568         * PA Semi PWRficient PA6T-1682M on-chip UART
3569         */
3570        [pbn_pasemi_1682M] = {
3571                .flags          = FL_BASE0,
3572                .num_ports      = 1,
3573                .base_baud      = 8333333,
3574        },
3575        /*
3576         * National Instruments 843x
3577         */
3578        [pbn_ni8430_16] = {
3579                .flags          = FL_BASE0,
3580                .num_ports      = 16,
3581                .base_baud      = 3686400,
3582                .uart_offset    = 0x10,
3583                .first_offset   = 0x800,
3584        },
3585        [pbn_ni8430_8] = {
3586                .flags          = FL_BASE0,
3587                .num_ports      = 8,
3588                .base_baud      = 3686400,
3589                .uart_offset    = 0x10,
3590                .first_offset   = 0x800,
3591        },
3592        [pbn_ni8430_4] = {
3593                .flags          = FL_BASE0,
3594                .num_ports      = 4,
3595                .base_baud      = 3686400,
3596                .uart_offset    = 0x10,
3597                .first_offset   = 0x800,
3598        },
3599        [pbn_ni8430_2] = {
3600                .flags          = FL_BASE0,
3601                .num_ports      = 2,
3602                .base_baud      = 3686400,
3603                .uart_offset    = 0x10,
3604                .first_offset   = 0x800,
3605        },
3606        /*
3607         * ADDI-DATA GmbH PCI-Express communication cards <info@addi-data.com>
3608         */
3609        [pbn_ADDIDATA_PCIe_1_3906250] = {
3610                .flags          = FL_BASE0,
3611                .num_ports      = 1,
3612                .base_baud      = 3906250,
3613                .uart_offset    = 0x200,
3614                .first_offset   = 0x1000,
3615        },
3616        [pbn_ADDIDATA_PCIe_2_3906250] = {
3617                .flags          = FL_BASE0,
3618                .num_ports      = 2,
3619                .base_baud      = 3906250,
3620                .uart_offset    = 0x200,
3621                .first_offset   = 0x1000,
3622        },
3623        [pbn_ADDIDATA_PCIe_4_3906250] = {
3624                .flags          = FL_BASE0,
3625                .num_ports      = 4,
3626                .base_baud      = 3906250,
3627                .uart_offset    = 0x200,
3628                .first_offset   = 0x1000,
3629        },
3630        [pbn_ADDIDATA_PCIe_8_3906250] = {
3631                .flags          = FL_BASE0,
3632                .num_ports      = 8,
3633                .base_baud      = 3906250,
3634                .uart_offset    = 0x200,
3635                .first_offset   = 0x1000,
3636        },
3637        [pbn_ce4100_1_115200] = {
3638                .flags          = FL_BASE_BARS,
3639                .num_ports      = 2,
3640                .base_baud      = 921600,
3641                .reg_shift      = 2,
3642        },
3643        [pbn_omegapci] = {
3644                .flags          = FL_BASE0,
3645                .num_ports      = 8,
3646                .base_baud      = 115200,
3647                .uart_offset    = 0x200,
3648        },
3649        [pbn_NETMOS9900_2s_115200] = {
3650                .flags          = FL_BASE0,
3651                .num_ports      = 2,
3652                .base_baud      = 115200,
3653        },
3654        [pbn_brcm_trumanage] = {
3655                .flags          = FL_BASE0,
3656                .num_ports      = 1,
3657                .reg_shift      = 2,
3658                .base_baud      = 115200,
3659        },
3660        [pbn_fintek_4] = {
3661                .num_ports      = 4,
3662                .uart_offset    = 8,
3663                .base_baud      = 115200,
3664                .first_offset   = 0x40,
3665        },
3666        [pbn_fintek_8] = {
3667                .num_ports      = 8,
3668                .uart_offset    = 8,
3669                .base_baud      = 115200,
3670                .first_offset   = 0x40,
3671        },
3672        [pbn_fintek_12] = {
3673                .num_ports      = 12,
3674                .uart_offset    = 8,
3675                .base_baud      = 115200,
3676                .first_offset   = 0x40,
3677        },
3678        [pbn_fintek_F81504A] = {
3679                .num_ports      = 4,
3680                .uart_offset    = 8,
3681                .base_baud      = 115200,
3682        },
3683        [pbn_fintek_F81508A] = {
3684                .num_ports      = 8,
3685                .uart_offset    = 8,
3686                .base_baud      = 115200,
3687        },
3688        [pbn_fintek_F81512A] = {
3689                .num_ports      = 12,
3690                .uart_offset    = 8,
3691                .base_baud      = 115200,
3692        },
3693        [pbn_wch382_2] = {
3694                .flags          = FL_BASE0,
3695                .num_ports      = 2,
3696                .base_baud      = 115200,
3697                .uart_offset    = 8,
3698                .first_offset   = 0xC0,
3699        },
3700        [pbn_wch384_4] = {
3701                .flags          = FL_BASE0,
3702                .num_ports      = 4,
3703                .base_baud      = 115200,
3704                .uart_offset    = 8,
3705                .first_offset   = 0xC0,
3706        },
3707        [pbn_wch384_8] = {
3708                .flags          = FL_BASE0,
3709                .num_ports      = 8,
3710                .base_baud      = 115200,
3711                .uart_offset    = 8,
3712                .first_offset   = 0x00,
3713        },
3714        /*
3715         * Pericom PI7C9X795[1248] Uno/Dual/Quad/Octal UART
3716         */
3717        [pbn_pericom_PI7C9X7951] = {
3718                .flags          = FL_BASE0,
3719                .num_ports      = 1,
3720                .base_baud      = 921600,
3721                .uart_offset    = 0x8,
3722        },
3723        [pbn_pericom_PI7C9X7952] = {
3724                .flags          = FL_BASE0,
3725                .num_ports      = 2,
3726                .base_baud      = 921600,
3727                .uart_offset    = 0x8,
3728        },
3729        [pbn_pericom_PI7C9X7954] = {
3730                .flags          = FL_BASE0,
3731                .num_ports      = 4,
3732                .base_baud      = 921600,
3733                .uart_offset    = 0x8,
3734        },
3735        [pbn_pericom_PI7C9X7958] = {
3736                .flags          = FL_BASE0,
3737                .num_ports      = 8,
3738                .base_baud      = 921600,
3739                .uart_offset    = 0x8,
3740        },
3741        [pbn_sunix_pci_1s] = {
3742                .num_ports      = 1,
3743                .base_baud      = 921600,
3744                .uart_offset    = 0x8,
3745        },
3746        [pbn_sunix_pci_2s] = {
3747                .num_ports      = 2,
3748                .base_baud      = 921600,
3749                .uart_offset    = 0x8,
3750        },
3751        [pbn_sunix_pci_4s] = {
3752                .num_ports      = 4,
3753                .base_baud      = 921600,
3754                .uart_offset    = 0x8,
3755        },
3756        [pbn_sunix_pci_8s] = {
3757                .num_ports      = 8,
3758                .base_baud      = 921600,
3759                .uart_offset    = 0x8,
3760        },
3761        [pbn_sunix_pci_16s] = {
3762                .num_ports      = 16,
3763                .base_baud      = 921600,
3764                .uart_offset    = 0x8,
3765        },
3766        [pbn_titan_1_4000000] = {
3767                .flags          = FL_BASE0,
3768                .num_ports      = 1,
3769                .base_baud      = 4000000,
3770                .uart_offset    = 0x200,
3771                .first_offset   = 0x1000,
3772        },
3773        [pbn_titan_2_4000000] = {
3774                .flags          = FL_BASE0,
3775                .num_ports      = 2,
3776                .base_baud      = 4000000,
3777                .uart_offset    = 0x200,
3778                .first_offset   = 0x1000,
3779        },
3780        [pbn_titan_4_4000000] = {
3781                .flags          = FL_BASE0,
3782                .num_ports      = 4,
3783                .base_baud      = 4000000,
3784                .uart_offset    = 0x200,
3785                .first_offset   = 0x1000,
3786        },
3787        [pbn_titan_8_4000000] = {
3788                .flags          = FL_BASE0,
3789                .num_ports      = 8,
3790                .base_baud      = 4000000,
3791                .uart_offset    = 0x200,
3792                .first_offset   = 0x1000,
3793        },
3794        [pbn_moxa8250_2p] = {
3795                .flags          = FL_BASE1,
3796                .num_ports      = 2,
3797                .base_baud      = 921600,
3798                .uart_offset    = 0x200,
3799        },
3800        [pbn_moxa8250_4p] = {
3801                .flags          = FL_BASE1,
3802                .num_ports      = 4,
3803                .base_baud      = 921600,
3804                .uart_offset    = 0x200,
3805        },
3806        [pbn_moxa8250_8p] = {
3807                .flags          = FL_BASE1,
3808                .num_ports      = 8,
3809                .base_baud      = 921600,
3810                .uart_offset    = 0x200,
3811        },
3812};
3813
3814static const struct pci_device_id blacklist[] = {
3815        /* softmodems */
3816        { PCI_VDEVICE(AL, 0x5457), }, /* ALi Corporation M5457 AC'97 Modem */
3817        { PCI_VDEVICE(MOTOROLA, 0x3052), }, /* Motorola Si3052-based modem */
3818        { PCI_DEVICE(0x1543, 0x3052), }, /* Si3052-based modem, default IDs */
3819
3820        /* multi-io cards handled by parport_serial */
3821        { PCI_DEVICE(0x4348, 0x7053), }, /* WCH CH353 2S1P */
3822        { PCI_DEVICE(0x4348, 0x5053), }, /* WCH CH353 1S1P */
3823        { PCI_DEVICE(0x1c00, 0x3250), }, /* WCH CH382 2S1P */
3824
3825        /* Intel platforms with MID UART */
3826        { PCI_VDEVICE(INTEL, 0x081b), },
3827        { PCI_VDEVICE(INTEL, 0x081c), },
3828        { PCI_VDEVICE(INTEL, 0x081d), },
3829        { PCI_VDEVICE(INTEL, 0x1191), },
3830        { PCI_VDEVICE(INTEL, 0x18d8), },
3831        { PCI_VDEVICE(INTEL, 0x19d8), },
3832
3833        /* Intel platforms with DesignWare UART */
3834        { PCI_VDEVICE(INTEL, 0x0936), },
3835        { PCI_VDEVICE(INTEL, 0x0f0a), },
3836        { PCI_VDEVICE(INTEL, 0x0f0c), },
3837        { PCI_VDEVICE(INTEL, 0x228a), },
3838        { PCI_VDEVICE(INTEL, 0x228c), },
3839        { PCI_VDEVICE(INTEL, 0x4b96), },
3840        { PCI_VDEVICE(INTEL, 0x4b97), },
3841        { PCI_VDEVICE(INTEL, 0x4b98), },
3842        { PCI_VDEVICE(INTEL, 0x4b99), },
3843        { PCI_VDEVICE(INTEL, 0x4b9a), },
3844        { PCI_VDEVICE(INTEL, 0x4b9b), },
3845        { PCI_VDEVICE(INTEL, 0x9ce3), },
3846        { PCI_VDEVICE(INTEL, 0x9ce4), },
3847
3848        /* Exar devices */
3849        { PCI_VDEVICE(EXAR, PCI_ANY_ID), },
3850        { PCI_VDEVICE(COMMTECH, PCI_ANY_ID), },
3851
3852        /* End of the black list */
3853        { }
3854};
3855
3856static int serial_pci_is_class_communication(struct pci_dev *dev)
3857{
3858        /*
3859         * If it is not a communications device or the programming
3860         * interface is greater than 6, give up.
3861         */
3862        if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
3863             ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MULTISERIAL) &&
3864             ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
3865            (dev->class & 0xff) > 6)
3866                return -ENODEV;
3867
3868        return 0;
3869}
3870
3871/*
3872 * Given a complete unknown PCI device, try to use some heuristics to
3873 * guess what the configuration might be, based on the pitiful PCI
3874 * serial specs.  Returns 0 on success, -ENODEV on failure.
3875 */
3876static int
3877serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
3878{
3879        int num_iomem, num_port, first_port = -1, i;
3880        int rc;
3881
3882        rc = serial_pci_is_class_communication(dev);
3883        if (rc)
3884                return rc;
3885
3886        /*
3887         * Should we try to make guesses for multiport serial devices later?
3888         */
3889        if ((dev->class >> 8) == PCI_CLASS_COMMUNICATION_MULTISERIAL)
3890                return -ENODEV;
3891
3892        num_iomem = num_port = 0;
3893        for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3894                if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
3895                        num_port++;
3896                        if (first_port == -1)
3897                                first_port = i;
3898                }
3899                if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
3900                        num_iomem++;
3901        }
3902
3903        /*
3904         * If there is 1 or 0 iomem regions, and exactly one port,
3905         * use it.  We guess the number of ports based on the IO
3906         * region size.
3907         */
3908        if (num_iomem <= 1 && num_port == 1) {
3909                board->flags = first_port;
3910                board->num_ports = pci_resource_len(dev, first_port) / 8;
3911                return 0;
3912        }
3913
3914        /*
3915         * Now guess if we've got a board which indexes by BARs.
3916         * Each IO BAR should be 8 bytes, and they should follow
3917         * consecutively.
3918         */
3919        first_port = -1;
3920        num_port = 0;
3921        for (i = 0; i < PCI_STD_NUM_BARS; i++) {
3922                if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
3923                    pci_resource_len(dev, i) == 8 &&
3924                    (first_port == -1 || (first_port + num_port) == i)) {
3925                        num_port++;
3926                        if (first_port == -1)
3927                                first_port = i;
3928                }
3929        }
3930
3931        if (num_port > 1) {
3932                board->flags = first_port | FL_BASE_BARS;
3933                board->num_ports = num_port;
3934                return 0;
3935        }
3936
3937        return -ENODEV;
3938}
3939
3940static inline int
3941serial_pci_matches(const struct pciserial_board *board,
3942                   const struct pciserial_board *guessed)
3943{
3944        return
3945            board->num_ports == guessed->num_ports &&
3946            board->base_baud == guessed->base_baud &&
3947            board->uart_offset == guessed->uart_offset &&
3948            board->reg_shift == guessed->reg_shift &&
3949            board->first_offset == guessed->first_offset;
3950}
3951
3952struct serial_private *
3953pciserial_init_ports(struct pci_dev *dev, const struct pciserial_board *board)
3954{
3955        struct uart_8250_port uart;
3956        struct serial_private *priv;
3957        struct pci_serial_quirk *quirk;
3958        int rc, nr_ports, i;
3959
3960        nr_ports = board->num_ports;
3961
3962        /*
3963         * Find an init and setup quirks.
3964         */
3965        quirk = find_quirk(dev);
3966
3967        /*
3968         * Run the new-style initialization function.
3969         * The initialization function returns:
3970         *  <0  - error
3971         *   0  - use board->num_ports
3972         *  >0  - number of ports
3973         */
3974        if (quirk->init) {
3975                rc = quirk->init(dev);
3976                if (rc < 0) {
3977                        priv = ERR_PTR(rc);
3978                        goto err_out;
3979                }
3980                if (rc)
3981                        nr_ports = rc;
3982        }
3983
3984        priv = kzalloc(sizeof(struct serial_private) +
3985                       sizeof(unsigned int) * nr_ports,
3986                       GFP_KERNEL);
3987        if (!priv) {
3988                priv = ERR_PTR(-ENOMEM);
3989                goto err_deinit;
3990        }
3991
3992        priv->dev = dev;
3993        priv->quirk = quirk;
3994
3995        memset(&uart, 0, sizeof(uart));
3996        uart.port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
3997        uart.port.uartclk = board->base_baud * 16;
3998
3999        if (board->flags & FL_NOIRQ) {
4000                uart.port.irq = 0;
4001        } else {
4002                if (pci_match_id(pci_use_msi, dev)) {
4003                        dev_dbg(&dev->dev, "Using MSI(-X) interrupts\n");
4004                        pci_set_master(dev);
4005                        uart.port.flags &= ~UPF_SHARE_IRQ;
4006                        rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_ALL_TYPES);
4007                } else {
4008                        dev_dbg(&dev->dev, "Using legacy interrupts\n");
4009                        rc = pci_alloc_irq_vectors(dev, 1, 1, PCI_IRQ_LEGACY);
4010                }
4011                if (rc < 0) {
4012                        kfree(priv);
4013                        priv = ERR_PTR(rc);
4014                        goto err_deinit;
4015                }
4016
4017                uart.port.irq = pci_irq_vector(dev, 0);
4018        }
4019
4020        uart.port.dev = &dev->dev;
4021
4022        for (i = 0; i < nr_ports; i++) {
4023                if (quirk->setup(priv, board, &uart, i))
4024                        break;
4025
4026                dev_dbg(&dev->dev, "Setup PCI port: port %lx, irq %d, type %d\n",
4027                        uart.port.iobase, uart.port.irq, uart.port.iotype);
4028
4029                priv->line[i] = serial8250_register_8250_port(&uart);
4030                if (priv->line[i] < 0) {
4031                        dev_err(&dev->dev,
4032                                "Couldn't register serial port %lx, irq %d, type %d, error %d\n",
4033                                uart.port.iobase, uart.port.irq,
4034                                uart.port.iotype, priv->line[i]);
4035                        break;
4036                }
4037        }
4038        priv->nr = i;
4039        priv->board = board;
4040        return priv;
4041
4042err_deinit:
4043        if (quirk->exit)
4044                quirk->exit(dev);
4045err_out:
4046        return priv;
4047}
4048EXPORT_SYMBOL_GPL(pciserial_init_ports);
4049
4050static void pciserial_detach_ports(struct serial_private *priv)
4051{
4052        struct pci_serial_quirk *quirk;
4053        int i;
4054
4055        for (i = 0; i < priv->nr; i++)
4056                serial8250_unregister_port(priv->line[i]);
4057
4058        /*
4059         * Find the exit quirks.
4060         */
4061        quirk = find_quirk(priv->dev);
4062        if (quirk->exit)
4063                quirk->exit(priv->dev);
4064}
4065
4066void pciserial_remove_ports(struct serial_private *priv)
4067{
4068        pciserial_detach_ports(priv);
4069        kfree(priv);
4070}
4071EXPORT_SYMBOL_GPL(pciserial_remove_ports);
4072
4073void pciserial_suspend_ports(struct serial_private *priv)
4074{
4075        int i;
4076
4077        for (i = 0; i < priv->nr; i++)
4078                if (priv->line[i] >= 0)
4079                        serial8250_suspend_port(priv->line[i]);
4080
4081        /*
4082         * Ensure that every init quirk is properly torn down
4083         */
4084        if (priv->quirk->exit)
4085                priv->quirk->exit(priv->dev);
4086}
4087EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
4088
4089void pciserial_resume_ports(struct serial_private *priv)
4090{
4091        int i;
4092
4093        /*
4094         * Ensure that the board is correctly configured.
4095         */
4096        if (priv->quirk->init)
4097                priv->quirk->init(priv->dev);
4098
4099        for (i = 0; i < priv->nr; i++)
4100                if (priv->line[i] >= 0)
4101                        serial8250_resume_port(priv->line[i]);
4102}
4103EXPORT_SYMBOL_GPL(pciserial_resume_ports);
4104
4105/*
4106 * Probe one serial board.  Unfortunately, there is no rhyme nor reason
4107 * to the arrangement of serial ports on a PCI card.
4108 */
4109static int
4110pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
4111{
4112        struct pci_serial_quirk *quirk;
4113        struct serial_private *priv;
4114        const struct pciserial_board *board;
4115        const struct pci_device_id *exclude;
4116        struct pciserial_board tmp;
4117        int rc;
4118
4119        quirk = find_quirk(dev);
4120        if (quirk->probe) {
4121                rc = quirk->probe(dev);
4122                if (rc)
4123                        return rc;
4124        }
4125
4126        if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
4127                dev_err(&dev->dev, "invalid driver_data: %ld\n",
4128                        ent->driver_data);
4129                return -EINVAL;
4130        }
4131
4132        board = &pci_boards[ent->driver_data];
4133
4134        exclude = pci_match_id(blacklist, dev);
4135        if (exclude)
4136                return -ENODEV;
4137
4138        rc = pcim_enable_device(dev);
4139        pci_save_state(dev);
4140        if (rc)
4141                return rc;
4142
4143        if (ent->driver_data == pbn_default) {
4144                /*
4145                 * Use a copy of the pci_board entry for this;
4146                 * avoid changing entries in the table.
4147                 */
4148                memcpy(&tmp, board, sizeof(struct pciserial_board));
4149                board = &tmp;
4150
4151                /*
4152                 * We matched one of our class entries.  Try to
4153                 * determine the parameters of this board.
4154                 */
4155                rc = serial_pci_guess_board(dev, &tmp);
4156                if (rc)
4157                        return rc;
4158        } else {
4159                /*
4160                 * We matched an explicit entry.  If we are able to
4161                 * detect this boards settings with our heuristic,
4162                 * then we no longer need this entry.
4163                 */
4164                memcpy(&tmp, &pci_boards[pbn_default],
4165                       sizeof(struct pciserial_board));
4166                rc = serial_pci_guess_board(dev, &tmp);
4167                if (rc == 0 && serial_pci_matches(board, &tmp))
4168                        moan_device("Redundant entry in serial pci_table.",
4169                                    dev);
4170        }
4171
4172        priv = pciserial_init_ports(dev, board);
4173        if (IS_ERR(priv))
4174                return PTR_ERR(priv);
4175
4176        pci_set_drvdata(dev, priv);
4177        return 0;
4178}
4179
4180static void pciserial_remove_one(struct pci_dev *dev)
4181{
4182        struct serial_private *priv = pci_get_drvdata(dev);
4183
4184        pciserial_remove_ports(priv);
4185}
4186
4187#ifdef CONFIG_PM_SLEEP
4188static int pciserial_suspend_one(struct device *dev)
4189{
4190        struct serial_private *priv = dev_get_drvdata(dev);
4191
4192        if (priv)
4193                pciserial_suspend_ports(priv);
4194
4195        return 0;
4196}
4197
4198static int pciserial_resume_one(struct device *dev)
4199{
4200        struct pci_dev *pdev = to_pci_dev(dev);
4201        struct serial_private *priv = pci_get_drvdata(pdev);
4202        int err;
4203
4204        if (priv) {
4205                /*
4206                 * The device may have been disabled.  Re-enable it.
4207                 */
4208                err = pci_enable_device(pdev);
4209                /* FIXME: We cannot simply error out here */
4210                if (err)
4211                        dev_err(dev, "Unable to re-enable ports, trying to continue.\n");
4212                pciserial_resume_ports(priv);
4213        }
4214        return 0;
4215}
4216#endif
4217
4218static SIMPLE_DEV_PM_OPS(pciserial_pm_ops, pciserial_suspend_one,
4219                         pciserial_resume_one);
4220
4221static const struct pci_device_id serial_pci_tbl[] = {
4222        /* Advantech use PCI_DEVICE_ID_ADVANTECH_PCI3620 (0x3620) as 'PCI_SUBVENDOR_ID' */
4223        {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3620,
4224                PCI_DEVICE_ID_ADVANTECH_PCI3620, 0x0001, 0, 0,
4225                pbn_b2_8_921600 },
4226        /* Advantech also use 0x3618 and 0xf618 */
4227        {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCI3618,
4228                PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4229                pbn_b0_4_921600 },
4230        {       PCI_VENDOR_ID_ADVANTECH, PCI_DEVICE_ID_ADVANTECH_PCIf618,
4231                PCI_DEVICE_ID_ADVANTECH_PCI3618, PCI_ANY_ID, 0, 0,
4232                pbn_b0_4_921600 },
4233        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4234                PCI_SUBVENDOR_ID_CONNECT_TECH,
4235                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4236                pbn_b1_8_1382400 },
4237        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4238                PCI_SUBVENDOR_ID_CONNECT_TECH,
4239                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4240                pbn_b1_4_1382400 },
4241        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
4242                PCI_SUBVENDOR_ID_CONNECT_TECH,
4243                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4244                pbn_b1_2_1382400 },
4245        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4246                PCI_SUBVENDOR_ID_CONNECT_TECH,
4247                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
4248                pbn_b1_8_1382400 },
4249        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4250                PCI_SUBVENDOR_ID_CONNECT_TECH,
4251                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
4252                pbn_b1_4_1382400 },
4253        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4254                PCI_SUBVENDOR_ID_CONNECT_TECH,
4255                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
4256                pbn_b1_2_1382400 },
4257        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4258                PCI_SUBVENDOR_ID_CONNECT_TECH,
4259                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
4260                pbn_b1_8_921600 },
4261        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4262                PCI_SUBVENDOR_ID_CONNECT_TECH,
4263                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
4264                pbn_b1_8_921600 },
4265        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4266                PCI_SUBVENDOR_ID_CONNECT_TECH,
4267                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
4268                pbn_b1_4_921600 },
4269        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4270                PCI_SUBVENDOR_ID_CONNECT_TECH,
4271                PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
4272                pbn_b1_4_921600 },
4273        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4274                PCI_SUBVENDOR_ID_CONNECT_TECH,
4275                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
4276                pbn_b1_2_921600 },
4277        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4278                PCI_SUBVENDOR_ID_CONNECT_TECH,
4279                PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
4280                pbn_b1_8_921600 },
4281        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4282                PCI_SUBVENDOR_ID_CONNECT_TECH,
4283                PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
4284                pbn_b1_8_921600 },
4285        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4286                PCI_SUBVENDOR_ID_CONNECT_TECH,
4287                PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
4288                pbn_b1_4_921600 },
4289        {       PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
4290                PCI_SUBVENDOR_ID_CONNECT_TECH,
4291                PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_20MHZ, 0, 0,
4292                pbn_b1_2_1250000 },
4293        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4294                PCI_SUBVENDOR_ID_CONNECT_TECH,
4295                PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_2, 0, 0,
4296                pbn_b0_2_1843200 },
4297        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4298                PCI_SUBVENDOR_ID_CONNECT_TECH,
4299                PCI_SUBDEVICE_ID_CONNECT_TECH_TITAN_4, 0, 0,
4300                pbn_b0_4_1843200 },
4301        {       PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
4302                PCI_VENDOR_ID_AFAVLAB,
4303                PCI_SUBDEVICE_ID_AFAVLAB_P061, 0, 0,
4304                pbn_b0_4_1152000 },
4305        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
4306                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4307                pbn_b2_bt_1_115200 },
4308        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
4309                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4310                pbn_b2_bt_2_115200 },
4311        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
4312                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4313                pbn_b2_bt_4_115200 },
4314        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
4315                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4316                pbn_b2_bt_2_115200 },
4317        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
4318                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4319                pbn_b2_bt_4_115200 },
4320        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
4321                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4322                pbn_b2_8_115200 },
4323        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_7803,
4324                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4325                pbn_b2_8_460800 },
4326        {       PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
4327                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4328                pbn_b2_8_115200 },
4329
4330        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
4331                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4332                pbn_b2_bt_2_115200 },
4333        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
4334                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4335                pbn_b2_bt_2_921600 },
4336        /*
4337         * VScom SPCOM800, from sl@s.pl
4338         */
4339        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
4340                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4341                pbn_b2_8_921600 },
4342        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
4343                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4344                pbn_b2_4_921600 },
4345        /* Unknown card - subdevice 0x1584 */
4346        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4347                PCI_VENDOR_ID_PLX,
4348                PCI_SUBDEVICE_ID_UNKNOWN_0x1584, 0, 0,
4349                pbn_b2_4_115200 },
4350        /* Unknown card - subdevice 0x1588 */
4351        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4352                PCI_VENDOR_ID_PLX,
4353                PCI_SUBDEVICE_ID_UNKNOWN_0x1588, 0, 0,
4354                pbn_b2_8_115200 },
4355        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4356                PCI_SUBVENDOR_ID_KEYSPAN,
4357                PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
4358                pbn_panacom },
4359        {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
4360                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4361                pbn_panacom4 },
4362        {       PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
4363                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4364                pbn_panacom2 },
4365        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9030,
4366                PCI_VENDOR_ID_ESDGMBH,
4367                PCI_DEVICE_ID_ESDGMBH_CPCIASIO4, 0, 0,
4368                pbn_b2_4_115200 },
4369        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4370                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4371                PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
4372                pbn_b2_4_460800 },
4373        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4374                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4375                PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
4376                pbn_b2_8_460800 },
4377        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4378                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4379                PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
4380                pbn_b2_16_460800 },
4381        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4382                PCI_SUBVENDOR_ID_CHASE_PCIFAST,
4383                PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
4384                pbn_b2_16_460800 },
4385        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4386                PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4387                PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
4388                pbn_b2_4_460800 },
4389        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4390                PCI_SUBVENDOR_ID_CHASE_PCIRAS,
4391                PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
4392                pbn_b2_8_460800 },
4393        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
4394                PCI_SUBVENDOR_ID_EXSYS,
4395                PCI_SUBDEVICE_ID_EXSYS_4055, 0, 0,
4396                pbn_b2_4_115200 },
4397        /*
4398         * Megawolf Romulus PCI Serial Card, from Mike Hudson
4399         * (Exoray@isys.ca)
4400         */
4401        {       PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
4402                0x10b5, 0x106a, 0, 0,
4403                pbn_plx_romulus },
4404        /*
4405        * EndRun Technologies. PCI express device range.
4406        *    EndRun PTP/1588 has 2 Native UARTs.
4407        */
4408        {       PCI_VENDOR_ID_ENDRUN, PCI_DEVICE_ID_ENDRUN_1588,
4409                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4410                pbn_endrun_2_4000000 },
4411        /*
4412         * Quatech cards. These actually have configurable clocks but for
4413         * now we just use the default.
4414         *
4415         * 100 series are RS232, 200 series RS422,
4416         */
4417        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
4418                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4419                pbn_b1_4_115200 },
4420        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
4421                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4422                pbn_b1_2_115200 },
4423        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100E,
4424                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4425                pbn_b2_2_115200 },
4426        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200,
4427                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4428                pbn_b1_2_115200 },
4429        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC200E,
4430                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4431                pbn_b2_2_115200 },
4432        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC200,
4433                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4434                pbn_b1_4_115200 },
4435        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
4436                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4437                pbn_b1_8_115200 },
4438        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
4439                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4440                pbn_b1_8_115200 },
4441        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP100,
4442                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4443                pbn_b1_4_115200 },
4444        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP100,
4445                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4446                pbn_b1_2_115200 },
4447        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCP200,
4448                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4449                pbn_b1_4_115200 },
4450        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSCP200,
4451                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4452                pbn_b1_2_115200 },
4453        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSCLP100,
4454                PCI_ANY_ID, PCI_ANY_ID, 0, 0,
4455                pbn_b2_4_115200 },
4456        {       PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QU