linux/drivers/thermal/rockchip_thermal.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2014-2016, Fuzhou Rockchip Electronics Co., Ltd
   4 * Caesar Wang <wxt@rock-chips.com>
   5 */
   6
   7#include <linux/clk.h>
   8#include <linux/delay.h>
   9#include <linux/interrupt.h>
  10#include <linux/io.h>
  11#include <linux/module.h>
  12#include <linux/of.h>
  13#include <linux/of_address.h>
  14#include <linux/of_irq.h>
  15#include <linux/platform_device.h>
  16#include <linux/regmap.h>
  17#include <linux/reset.h>
  18#include <linux/thermal.h>
  19#include <linux/mfd/syscon.h>
  20#include <linux/pinctrl/consumer.h>
  21
  22/*
  23 * If the temperature over a period of time High,
  24 * the resulting TSHUT gave CRU module,let it reset the entire chip,
  25 * or via GPIO give PMIC.
  26 */
  27enum tshut_mode {
  28        TSHUT_MODE_CRU = 0,
  29        TSHUT_MODE_GPIO,
  30};
  31
  32/*
  33 * The system Temperature Sensors tshut(tshut) polarity
  34 * the bit 8 is tshut polarity.
  35 * 0: low active, 1: high active
  36 */
  37enum tshut_polarity {
  38        TSHUT_LOW_ACTIVE = 0,
  39        TSHUT_HIGH_ACTIVE,
  40};
  41
  42/*
  43 * The system has two Temperature Sensors.
  44 * sensor0 is for CPU, and sensor1 is for GPU.
  45 */
  46enum sensor_id {
  47        SENSOR_CPU = 0,
  48        SENSOR_GPU,
  49};
  50
  51/*
  52 * The conversion table has the adc value and temperature.
  53 * ADC_DECREMENT: the adc value is of diminishing.(e.g. rk3288_code_table)
  54 * ADC_INCREMENT: the adc value is incremental.(e.g. rk3368_code_table)
  55 */
  56enum adc_sort_mode {
  57        ADC_DECREMENT = 0,
  58        ADC_INCREMENT,
  59};
  60
  61#include "thermal_hwmon.h"
  62
  63/**
  64 * The max sensors is two in rockchip SoCs.
  65 * Two sensors: CPU and GPU sensor.
  66 */
  67#define SOC_MAX_SENSORS 2
  68
  69/**
  70 * struct chip_tsadc_table - hold information about chip-specific differences
  71 * @id: conversion table
  72 * @length: size of conversion table
  73 * @data_mask: mask to apply on data inputs
  74 * @mode: sort mode of this adc variant (incrementing or decrementing)
  75 */
  76struct chip_tsadc_table {
  77        const struct tsadc_table *id;
  78        unsigned int length;
  79        u32 data_mask;
  80        enum adc_sort_mode mode;
  81};
  82
  83/**
  84 * struct rockchip_tsadc_chip - hold the private data of tsadc chip
  85 * @chn_id: array of sensor ids of chip corresponding to the channel
  86 * @chn_num: the channel number of tsadc chip
  87 * @tshut_temp: the hardware-controlled shutdown temperature value
  88 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
  89 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
  90 * @initialize: SoC special initialize tsadc controller method
  91 * @irq_ack: clear the interrupt
  92 * @control: enable/disable method for the tsadc controller
  93 * @get_temp: get the temperature
  94 * @set_alarm_temp: set the high temperature interrupt
  95 * @set_tshut_temp: set the hardware-controlled shutdown temperature
  96 * @set_tshut_mode: set the hardware-controlled shutdown mode
  97 * @table: the chip-specific conversion table
  98 */
  99struct rockchip_tsadc_chip {
 100        /* The sensor id of chip correspond to the ADC channel */
 101        int chn_id[SOC_MAX_SENSORS];
 102        int chn_num;
 103
 104        /* The hardware-controlled tshut property */
 105        int tshut_temp;
 106        enum tshut_mode tshut_mode;
 107        enum tshut_polarity tshut_polarity;
 108
 109        /* Chip-wide methods */
 110        void (*initialize)(struct regmap *grf,
 111                           void __iomem *reg, enum tshut_polarity p);
 112        void (*irq_ack)(void __iomem *reg);
 113        void (*control)(void __iomem *reg, bool on);
 114
 115        /* Per-sensor methods */
 116        int (*get_temp)(const struct chip_tsadc_table *table,
 117                        int chn, void __iomem *reg, int *temp);
 118        int (*set_alarm_temp)(const struct chip_tsadc_table *table,
 119                              int chn, void __iomem *reg, int temp);
 120        int (*set_tshut_temp)(const struct chip_tsadc_table *table,
 121                              int chn, void __iomem *reg, int temp);
 122        void (*set_tshut_mode)(int chn, void __iomem *reg, enum tshut_mode m);
 123
 124        /* Per-table methods */
 125        struct chip_tsadc_table table;
 126};
 127
 128/**
 129 * struct rockchip_thermal_sensor - hold the information of thermal sensor
 130 * @thermal:  pointer to the platform/configuration data
 131 * @tzd: pointer to a thermal zone
 132 * @id: identifier of the thermal sensor
 133 */
 134struct rockchip_thermal_sensor {
 135        struct rockchip_thermal_data *thermal;
 136        struct thermal_zone_device *tzd;
 137        int id;
 138};
 139
 140/**
 141 * struct rockchip_thermal_data - hold the private data of thermal driver
 142 * @chip: pointer to the platform/configuration data
 143 * @pdev: platform device of thermal
 144 * @reset: the reset controller of tsadc
 145 * @sensors: array of thermal sensors
 146 * @clk: the controller clock is divided by the exteral 24MHz
 147 * @pclk: the advanced peripherals bus clock
 148 * @grf: the general register file will be used to do static set by software
 149 * @regs: the base address of tsadc controller
 150 * @tshut_temp: the hardware-controlled shutdown temperature value
 151 * @tshut_mode: the hardware-controlled shutdown mode (0:CRU 1:GPIO)
 152 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
 153 */
 154struct rockchip_thermal_data {
 155        const struct rockchip_tsadc_chip *chip;
 156        struct platform_device *pdev;
 157        struct reset_control *reset;
 158
 159        struct rockchip_thermal_sensor sensors[SOC_MAX_SENSORS];
 160
 161        struct clk *clk;
 162        struct clk *pclk;
 163
 164        struct regmap *grf;
 165        void __iomem *regs;
 166
 167        int tshut_temp;
 168        enum tshut_mode tshut_mode;
 169        enum tshut_polarity tshut_polarity;
 170};
 171
 172/**
 173 * TSADC Sensor Register description:
 174 *
 175 * TSADCV2_* are used for RK3288 SoCs, the other chips can reuse it.
 176 * TSADCV3_* are used for newer SoCs than RK3288. (e.g: RK3228, RK3399)
 177 *
 178 */
 179#define TSADCV2_USER_CON                        0x00
 180#define TSADCV2_AUTO_CON                        0x04
 181#define TSADCV2_INT_EN                          0x08
 182#define TSADCV2_INT_PD                          0x0c
 183#define TSADCV2_DATA(chn)                       (0x20 + (chn) * 0x04)
 184#define TSADCV2_COMP_INT(chn)                   (0x30 + (chn) * 0x04)
 185#define TSADCV2_COMP_SHUT(chn)                  (0x40 + (chn) * 0x04)
 186#define TSADCV2_HIGHT_INT_DEBOUNCE              0x60
 187#define TSADCV2_HIGHT_TSHUT_DEBOUNCE            0x64
 188#define TSADCV2_AUTO_PERIOD                     0x68
 189#define TSADCV2_AUTO_PERIOD_HT                  0x6c
 190
 191#define TSADCV2_AUTO_EN                         BIT(0)
 192#define TSADCV2_AUTO_SRC_EN(chn)                BIT(4 + (chn))
 193#define TSADCV2_AUTO_TSHUT_POLARITY_HIGH        BIT(8)
 194
 195#define TSADCV3_AUTO_Q_SEL_EN                   BIT(1)
 196
 197#define TSADCV2_INT_SRC_EN(chn)                 BIT(chn)
 198#define TSADCV2_SHUT_2GPIO_SRC_EN(chn)          BIT(4 + (chn))
 199#define TSADCV2_SHUT_2CRU_SRC_EN(chn)           BIT(8 + (chn))
 200
 201#define TSADCV2_INT_PD_CLEAR_MASK               ~BIT(8)
 202#define TSADCV3_INT_PD_CLEAR_MASK               ~BIT(16)
 203
 204#define TSADCV2_DATA_MASK                       0xfff
 205#define TSADCV3_DATA_MASK                       0x3ff
 206
 207#define TSADCV2_HIGHT_INT_DEBOUNCE_COUNT        4
 208#define TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT      4
 209#define TSADCV2_AUTO_PERIOD_TIME                250 /* 250ms */
 210#define TSADCV2_AUTO_PERIOD_HT_TIME             50  /* 50ms */
 211#define TSADCV3_AUTO_PERIOD_TIME                1875 /* 2.5ms */
 212#define TSADCV3_AUTO_PERIOD_HT_TIME             1875 /* 2.5ms */
 213
 214#define TSADCV5_AUTO_PERIOD_TIME                1622 /* 2.5ms */
 215#define TSADCV5_AUTO_PERIOD_HT_TIME             1622 /* 2.5ms */
 216
 217#define TSADCV2_USER_INTER_PD_SOC               0x340 /* 13 clocks */
 218#define TSADCV5_USER_INTER_PD_SOC               0xfc0 /* 97us, at least 90us */
 219
 220#define GRF_SARADC_TESTBIT                      0x0e644
 221#define GRF_TSADC_TESTBIT_L                     0x0e648
 222#define GRF_TSADC_TESTBIT_H                     0x0e64c
 223
 224#define PX30_GRF_SOC_CON2                       0x0408
 225
 226#define RK3568_GRF_TSADC_CON                    0x0600
 227#define RK3568_GRF_TSADC_ANA_REG0               (0x10001 << 0)
 228#define RK3568_GRF_TSADC_ANA_REG1               (0x10001 << 1)
 229#define RK3568_GRF_TSADC_ANA_REG2               (0x10001 << 2)
 230#define RK3568_GRF_TSADC_TSEN                   (0x10001 << 8)
 231
 232#define GRF_SARADC_TESTBIT_ON                   (0x10001 << 2)
 233#define GRF_TSADC_TESTBIT_H_ON                  (0x10001 << 2)
 234#define GRF_TSADC_VCM_EN_L                      (0x10001 << 7)
 235#define GRF_TSADC_VCM_EN_H                      (0x10001 << 7)
 236
 237#define GRF_CON_TSADC_CH_INV                    (0x10001 << 1)
 238
 239/**
 240 * struct tsadc_table - code to temperature conversion table
 241 * @code: the value of adc channel
 242 * @temp: the temperature
 243 * Note:
 244 * code to temperature mapping of the temperature sensor is a piece wise linear
 245 * curve.Any temperature, code faling between to 2 give temperatures can be
 246 * linearly interpolated.
 247 * Code to Temperature mapping should be updated based on manufacturer results.
 248 */
 249struct tsadc_table {
 250        u32 code;
 251        int temp;
 252};
 253
 254static const struct tsadc_table rv1108_table[] = {
 255        {0, -40000},
 256        {374, -40000},
 257        {382, -35000},
 258        {389, -30000},
 259        {397, -25000},
 260        {405, -20000},
 261        {413, -15000},
 262        {421, -10000},
 263        {429, -5000},
 264        {436, 0},
 265        {444, 5000},
 266        {452, 10000},
 267        {460, 15000},
 268        {468, 20000},
 269        {476, 25000},
 270        {483, 30000},
 271        {491, 35000},
 272        {499, 40000},
 273        {507, 45000},
 274        {515, 50000},
 275        {523, 55000},
 276        {531, 60000},
 277        {539, 65000},
 278        {547, 70000},
 279        {555, 75000},
 280        {562, 80000},
 281        {570, 85000},
 282        {578, 90000},
 283        {586, 95000},
 284        {594, 100000},
 285        {602, 105000},
 286        {610, 110000},
 287        {618, 115000},
 288        {626, 120000},
 289        {634, 125000},
 290        {TSADCV2_DATA_MASK, 125000},
 291};
 292
 293static const struct tsadc_table rk3228_code_table[] = {
 294        {0, -40000},
 295        {588, -40000},
 296        {593, -35000},
 297        {598, -30000},
 298        {603, -25000},
 299        {608, -20000},
 300        {613, -15000},
 301        {618, -10000},
 302        {623, -5000},
 303        {629, 0},
 304        {634, 5000},
 305        {639, 10000},
 306        {644, 15000},
 307        {649, 20000},
 308        {654, 25000},
 309        {660, 30000},
 310        {665, 35000},
 311        {670, 40000},
 312        {675, 45000},
 313        {681, 50000},
 314        {686, 55000},
 315        {691, 60000},
 316        {696, 65000},
 317        {702, 70000},
 318        {707, 75000},
 319        {712, 80000},
 320        {717, 85000},
 321        {723, 90000},
 322        {728, 95000},
 323        {733, 100000},
 324        {738, 105000},
 325        {744, 110000},
 326        {749, 115000},
 327        {754, 120000},
 328        {760, 125000},
 329        {TSADCV2_DATA_MASK, 125000},
 330};
 331
 332static const struct tsadc_table rk3288_code_table[] = {
 333        {TSADCV2_DATA_MASK, -40000},
 334        {3800, -40000},
 335        {3792, -35000},
 336        {3783, -30000},
 337        {3774, -25000},
 338        {3765, -20000},
 339        {3756, -15000},
 340        {3747, -10000},
 341        {3737, -5000},
 342        {3728, 0},
 343        {3718, 5000},
 344        {3708, 10000},
 345        {3698, 15000},
 346        {3688, 20000},
 347        {3678, 25000},
 348        {3667, 30000},
 349        {3656, 35000},
 350        {3645, 40000},
 351        {3634, 45000},
 352        {3623, 50000},
 353        {3611, 55000},
 354        {3600, 60000},
 355        {3588, 65000},
 356        {3575, 70000},
 357        {3563, 75000},
 358        {3550, 80000},
 359        {3537, 85000},
 360        {3524, 90000},
 361        {3510, 95000},
 362        {3496, 100000},
 363        {3482, 105000},
 364        {3467, 110000},
 365        {3452, 115000},
 366        {3437, 120000},
 367        {3421, 125000},
 368        {0, 125000},
 369};
 370
 371static const struct tsadc_table rk3328_code_table[] = {
 372        {0, -40000},
 373        {296, -40000},
 374        {304, -35000},
 375        {313, -30000},
 376        {331, -20000},
 377        {340, -15000},
 378        {349, -10000},
 379        {359, -5000},
 380        {368, 0},
 381        {378, 5000},
 382        {388, 10000},
 383        {398, 15000},
 384        {408, 20000},
 385        {418, 25000},
 386        {429, 30000},
 387        {440, 35000},
 388        {451, 40000},
 389        {462, 45000},
 390        {473, 50000},
 391        {485, 55000},
 392        {496, 60000},
 393        {508, 65000},
 394        {521, 70000},
 395        {533, 75000},
 396        {546, 80000},
 397        {559, 85000},
 398        {572, 90000},
 399        {586, 95000},
 400        {600, 100000},
 401        {614, 105000},
 402        {629, 110000},
 403        {644, 115000},
 404        {659, 120000},
 405        {675, 125000},
 406        {TSADCV2_DATA_MASK, 125000},
 407};
 408
 409static const struct tsadc_table rk3368_code_table[] = {
 410        {0, -40000},
 411        {106, -40000},
 412        {108, -35000},
 413        {110, -30000},
 414        {112, -25000},
 415        {114, -20000},
 416        {116, -15000},
 417        {118, -10000},
 418        {120, -5000},
 419        {122, 0},
 420        {124, 5000},
 421        {126, 10000},
 422        {128, 15000},
 423        {130, 20000},
 424        {132, 25000},
 425        {134, 30000},
 426        {136, 35000},
 427        {138, 40000},
 428        {140, 45000},
 429        {142, 50000},
 430        {144, 55000},
 431        {146, 60000},
 432        {148, 65000},
 433        {150, 70000},
 434        {152, 75000},
 435        {154, 80000},
 436        {156, 85000},
 437        {158, 90000},
 438        {160, 95000},
 439        {162, 100000},
 440        {163, 105000},
 441        {165, 110000},
 442        {167, 115000},
 443        {169, 120000},
 444        {171, 125000},
 445        {TSADCV3_DATA_MASK, 125000},
 446};
 447
 448static const struct tsadc_table rk3399_code_table[] = {
 449        {0, -40000},
 450        {402, -40000},
 451        {410, -35000},
 452        {419, -30000},
 453        {427, -25000},
 454        {436, -20000},
 455        {444, -15000},
 456        {453, -10000},
 457        {461, -5000},
 458        {470, 0},
 459        {478, 5000},
 460        {487, 10000},
 461        {496, 15000},
 462        {504, 20000},
 463        {513, 25000},
 464        {521, 30000},
 465        {530, 35000},
 466        {538, 40000},
 467        {547, 45000},
 468        {555, 50000},
 469        {564, 55000},
 470        {573, 60000},
 471        {581, 65000},
 472        {590, 70000},
 473        {599, 75000},
 474        {607, 80000},
 475        {616, 85000},
 476        {624, 90000},
 477        {633, 95000},
 478        {642, 100000},
 479        {650, 105000},
 480        {659, 110000},
 481        {668, 115000},
 482        {677, 120000},
 483        {685, 125000},
 484        {TSADCV3_DATA_MASK, 125000},
 485};
 486
 487static const struct tsadc_table rk3568_code_table[] = {
 488        {0, -40000},
 489        {1584, -40000},
 490        {1620, -35000},
 491        {1652, -30000},
 492        {1688, -25000},
 493        {1720, -20000},
 494        {1756, -15000},
 495        {1788, -10000},
 496        {1824, -5000},
 497        {1856, 0},
 498        {1892, 5000},
 499        {1924, 10000},
 500        {1956, 15000},
 501        {1992, 20000},
 502        {2024, 25000},
 503        {2060, 30000},
 504        {2092, 35000},
 505        {2128, 40000},
 506        {2160, 45000},
 507        {2196, 50000},
 508        {2228, 55000},
 509        {2264, 60000},
 510        {2300, 65000},
 511        {2332, 70000},
 512        {2368, 75000},
 513        {2400, 80000},
 514        {2436, 85000},
 515        {2468, 90000},
 516        {2500, 95000},
 517        {2536, 100000},
 518        {2572, 105000},
 519        {2604, 110000},
 520        {2636, 115000},
 521        {2672, 120000},
 522        {2704, 125000},
 523        {TSADCV2_DATA_MASK, 125000},
 524};
 525
 526static u32 rk_tsadcv2_temp_to_code(const struct chip_tsadc_table *table,
 527                                   int temp)
 528{
 529        int high, low, mid;
 530        unsigned long num;
 531        unsigned int denom;
 532        u32 error = table->data_mask;
 533
 534        low = 0;
 535        high = (table->length - 1) - 1; /* ignore the last check for table */
 536        mid = (high + low) / 2;
 537
 538        /* Return mask code data when the temp is over table range */
 539        if (temp < table->id[low].temp || temp > table->id[high].temp)
 540                goto exit;
 541
 542        while (low <= high) {
 543                if (temp == table->id[mid].temp)
 544                        return table->id[mid].code;
 545                else if (temp < table->id[mid].temp)
 546                        high = mid - 1;
 547                else
 548                        low = mid + 1;
 549                mid = (low + high) / 2;
 550        }
 551
 552        /*
 553         * The conversion code granularity provided by the table. Let's
 554         * assume that the relationship between temperature and
 555         * analog value between 2 table entries is linear and interpolate
 556         * to produce less granular result.
 557         */
 558        num = abs(table->id[mid + 1].code - table->id[mid].code);
 559        num *= temp - table->id[mid].temp;
 560        denom = table->id[mid + 1].temp - table->id[mid].temp;
 561
 562        switch (table->mode) {
 563        case ADC_DECREMENT:
 564                return table->id[mid].code - (num / denom);
 565        case ADC_INCREMENT:
 566                return table->id[mid].code + (num / denom);
 567        default:
 568                pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
 569                return error;
 570        }
 571
 572exit:
 573        pr_err("%s: invalid temperature, temp=%d error=%d\n",
 574               __func__, temp, error);
 575        return error;
 576}
 577
 578static int rk_tsadcv2_code_to_temp(const struct chip_tsadc_table *table,
 579                                   u32 code, int *temp)
 580{
 581        unsigned int low = 1;
 582        unsigned int high = table->length - 1;
 583        unsigned int mid = (low + high) / 2;
 584        unsigned int num;
 585        unsigned long denom;
 586
 587        WARN_ON(table->length < 2);
 588
 589        switch (table->mode) {
 590        case ADC_DECREMENT:
 591                code &= table->data_mask;
 592                if (code <= table->id[high].code)
 593                        return -EAGAIN;         /* Incorrect reading */
 594
 595                while (low <= high) {
 596                        if (code >= table->id[mid].code &&
 597                            code < table->id[mid - 1].code)
 598                                break;
 599                        else if (code < table->id[mid].code)
 600                                low = mid + 1;
 601                        else
 602                                high = mid - 1;
 603
 604                        mid = (low + high) / 2;
 605                }
 606                break;
 607        case ADC_INCREMENT:
 608                code &= table->data_mask;
 609                if (code < table->id[low].code)
 610                        return -EAGAIN;         /* Incorrect reading */
 611
 612                while (low <= high) {
 613                        if (code <= table->id[mid].code &&
 614                            code > table->id[mid - 1].code)
 615                                break;
 616                        else if (code > table->id[mid].code)
 617                                low = mid + 1;
 618                        else
 619                                high = mid - 1;
 620
 621                        mid = (low + high) / 2;
 622                }
 623                break;
 624        default:
 625                pr_err("%s: unknown table mode: %d\n", __func__, table->mode);
 626                return -EINVAL;
 627        }
 628
 629        /*
 630         * The 5C granularity provided by the table is too much. Let's
 631         * assume that the relationship between sensor readings and
 632         * temperature between 2 table entries is linear and interpolate
 633         * to produce less granular result.
 634         */
 635        num = table->id[mid].temp - table->id[mid - 1].temp;
 636        num *= abs(table->id[mid - 1].code - code);
 637        denom = abs(table->id[mid - 1].code - table->id[mid].code);
 638        *temp = table->id[mid - 1].temp + (num / denom);
 639
 640        return 0;
 641}
 642
 643/**
 644 * rk_tsadcv2_initialize - initialize TASDC Controller.
 645 * @grf: the general register file will be used to do static set by software
 646 * @regs: the base address of tsadc controller
 647 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
 648 *
 649 * (1) Set TSADC_V2_AUTO_PERIOD:
 650 *     Configure the interleave between every two accessing of
 651 *     TSADC in normal operation.
 652 *
 653 * (2) Set TSADCV2_AUTO_PERIOD_HT:
 654 *     Configure the interleave between every two accessing of
 655 *     TSADC after the temperature is higher than COM_SHUT or COM_INT.
 656 *
 657 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
 658 *     If the temperature is higher than COMP_INT or COMP_SHUT for
 659 *     "debounce" times, TSADC controller will generate interrupt or TSHUT.
 660 */
 661static void rk_tsadcv2_initialize(struct regmap *grf, void __iomem *regs,
 662                                  enum tshut_polarity tshut_polarity)
 663{
 664        if (tshut_polarity == TSHUT_HIGH_ACTIVE)
 665                writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 666                               regs + TSADCV2_AUTO_CON);
 667        else
 668                writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 669                               regs + TSADCV2_AUTO_CON);
 670
 671        writel_relaxed(TSADCV2_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
 672        writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 673                       regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 674        writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
 675                       regs + TSADCV2_AUTO_PERIOD_HT);
 676        writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 677                       regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 678}
 679
 680/**
 681 * rk_tsadcv3_initialize - initialize TASDC Controller.
 682 * @grf: the general register file will be used to do static set by software
 683 * @regs: the base address of tsadc controller
 684 * @tshut_polarity: the hardware-controlled active polarity (0:LOW 1:HIGH)
 685 *
 686 * (1) The tsadc control power sequence.
 687 *
 688 * (2) Set TSADC_V2_AUTO_PERIOD:
 689 *     Configure the interleave between every two accessing of
 690 *     TSADC in normal operation.
 691 *
 692 * (2) Set TSADCV2_AUTO_PERIOD_HT:
 693 *     Configure the interleave between every two accessing of
 694 *     TSADC after the temperature is higher than COM_SHUT or COM_INT.
 695 *
 696 * (3) Set TSADCV2_HIGH_INT_DEBOUNCE and TSADC_HIGHT_TSHUT_DEBOUNCE:
 697 *     If the temperature is higher than COMP_INT or COMP_SHUT for
 698 *     "debounce" times, TSADC controller will generate interrupt or TSHUT.
 699 */
 700static void rk_tsadcv3_initialize(struct regmap *grf, void __iomem *regs,
 701                                  enum tshut_polarity tshut_polarity)
 702{
 703        /* The tsadc control power sequence */
 704        if (IS_ERR(grf)) {
 705                /* Set interleave value to workround ic time sync issue */
 706                writel_relaxed(TSADCV2_USER_INTER_PD_SOC, regs +
 707                               TSADCV2_USER_CON);
 708
 709                writel_relaxed(TSADCV2_AUTO_PERIOD_TIME,
 710                               regs + TSADCV2_AUTO_PERIOD);
 711                writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 712                               regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 713                writel_relaxed(TSADCV2_AUTO_PERIOD_HT_TIME,
 714                               regs + TSADCV2_AUTO_PERIOD_HT);
 715                writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 716                               regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 717
 718        } else {
 719                /* Enable the voltage common mode feature */
 720                regmap_write(grf, GRF_TSADC_TESTBIT_L, GRF_TSADC_VCM_EN_L);
 721                regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_VCM_EN_H);
 722
 723                usleep_range(15, 100); /* The spec note says at least 15 us */
 724                regmap_write(grf, GRF_SARADC_TESTBIT, GRF_SARADC_TESTBIT_ON);
 725                regmap_write(grf, GRF_TSADC_TESTBIT_H, GRF_TSADC_TESTBIT_H_ON);
 726                usleep_range(90, 200); /* The spec note says at least 90 us */
 727
 728                writel_relaxed(TSADCV3_AUTO_PERIOD_TIME,
 729                               regs + TSADCV2_AUTO_PERIOD);
 730                writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 731                               regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 732                writel_relaxed(TSADCV3_AUTO_PERIOD_HT_TIME,
 733                               regs + TSADCV2_AUTO_PERIOD_HT);
 734                writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 735                               regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 736        }
 737
 738        if (tshut_polarity == TSHUT_HIGH_ACTIVE)
 739                writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 740                               regs + TSADCV2_AUTO_CON);
 741        else
 742                writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 743                               regs + TSADCV2_AUTO_CON);
 744}
 745
 746static void rk_tsadcv4_initialize(struct regmap *grf, void __iomem *regs,
 747                                  enum tshut_polarity tshut_polarity)
 748{
 749        rk_tsadcv2_initialize(grf, regs, tshut_polarity);
 750        regmap_write(grf, PX30_GRF_SOC_CON2, GRF_CON_TSADC_CH_INV);
 751}
 752
 753static void rk_tsadcv7_initialize(struct regmap *grf, void __iomem *regs,
 754                                  enum tshut_polarity tshut_polarity)
 755{
 756        writel_relaxed(TSADCV5_USER_INTER_PD_SOC, regs + TSADCV2_USER_CON);
 757        writel_relaxed(TSADCV5_AUTO_PERIOD_TIME, regs + TSADCV2_AUTO_PERIOD);
 758        writel_relaxed(TSADCV2_HIGHT_INT_DEBOUNCE_COUNT,
 759                       regs + TSADCV2_HIGHT_INT_DEBOUNCE);
 760        writel_relaxed(TSADCV5_AUTO_PERIOD_HT_TIME,
 761                       regs + TSADCV2_AUTO_PERIOD_HT);
 762        writel_relaxed(TSADCV2_HIGHT_TSHUT_DEBOUNCE_COUNT,
 763                       regs + TSADCV2_HIGHT_TSHUT_DEBOUNCE);
 764
 765        if (tshut_polarity == TSHUT_HIGH_ACTIVE)
 766                writel_relaxed(0U | TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 767                               regs + TSADCV2_AUTO_CON);
 768        else
 769                writel_relaxed(0U & ~TSADCV2_AUTO_TSHUT_POLARITY_HIGH,
 770                               regs + TSADCV2_AUTO_CON);
 771
 772        /*
 773         * The general register file will is optional
 774         * and might not be available.
 775         */
 776        if (!IS_ERR(grf)) {
 777                regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_TSEN);
 778                /*
 779                 * RK3568 TRM, section 18.5. requires a delay no less
 780                 * than 10us between the rising edge of tsadc_tsen_en
 781                 * and the rising edge of tsadc_ana_reg_0/1/2.
 782                 */
 783                udelay(15);
 784                regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG0);
 785                regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG1);
 786                regmap_write(grf, RK3568_GRF_TSADC_CON, RK3568_GRF_TSADC_ANA_REG2);
 787
 788                /*
 789                 * RK3568 TRM, section 18.5. requires a delay no less
 790                 * than 90us after the rising edge of tsadc_ana_reg_0/1/2.
 791                 */
 792                usleep_range(100, 200);
 793        }
 794}
 795
 796static void rk_tsadcv2_irq_ack(void __iomem *regs)
 797{
 798        u32 val;
 799
 800        val = readl_relaxed(regs + TSADCV2_INT_PD);
 801        writel_relaxed(val & TSADCV2_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
 802}
 803
 804static void rk_tsadcv3_irq_ack(void __iomem *regs)
 805{
 806        u32 val;
 807
 808        val = readl_relaxed(regs + TSADCV2_INT_PD);
 809        writel_relaxed(val & TSADCV3_INT_PD_CLEAR_MASK, regs + TSADCV2_INT_PD);
 810}
 811
 812static void rk_tsadcv2_control(void __iomem *regs, bool enable)
 813{
 814        u32 val;
 815
 816        val = readl_relaxed(regs + TSADCV2_AUTO_CON);
 817        if (enable)
 818                val |= TSADCV2_AUTO_EN;
 819        else
 820                val &= ~TSADCV2_AUTO_EN;
 821
 822        writel_relaxed(val, regs + TSADCV2_AUTO_CON);
 823}
 824
 825/**
 826 * rk_tsadcv3_control - the tsadc controller is enabled or disabled.
 827 * @regs: the base address of tsadc controller
 828 * @enable: boolean flag to enable the controller
 829 *
 830 * NOTE: TSADC controller works at auto mode, and some SoCs need set the
 831 * tsadc_q_sel bit on TSADCV2_AUTO_CON[1]. The (1024 - tsadc_q) as output
 832 * adc value if setting this bit to enable.
 833 */
 834static void rk_tsadcv3_control(void __iomem *regs, bool enable)
 835{
 836        u32 val;
 837
 838        val = readl_relaxed(regs + TSADCV2_AUTO_CON);
 839        if (enable)
 840                val |= TSADCV2_AUTO_EN | TSADCV3_AUTO_Q_SEL_EN;
 841        else
 842                val &= ~TSADCV2_AUTO_EN;
 843
 844        writel_relaxed(val, regs + TSADCV2_AUTO_CON);
 845}
 846
 847static int rk_tsadcv2_get_temp(const struct chip_tsadc_table *table,
 848                               int chn, void __iomem *regs, int *temp)
 849{
 850        u32 val;
 851
 852        val = readl_relaxed(regs + TSADCV2_DATA(chn));
 853
 854        return rk_tsadcv2_code_to_temp(table, val, temp);
 855}
 856
 857static int rk_tsadcv2_alarm_temp(const struct chip_tsadc_table *table,
 858                                 int chn, void __iomem *regs, int temp)
 859{
 860        u32 alarm_value;
 861        u32 int_en, int_clr;
 862
 863        /*
 864         * In some cases, some sensors didn't need the trip points, the
 865         * set_trips will pass {-INT_MAX, INT_MAX} to trigger tsadc alarm
 866         * in the end, ignore this case and disable the high temperature
 867         * interrupt.
 868         */
 869        if (temp == INT_MAX) {
 870                int_clr = readl_relaxed(regs + TSADCV2_INT_EN);
 871                int_clr &= ~TSADCV2_INT_SRC_EN(chn);
 872                writel_relaxed(int_clr, regs + TSADCV2_INT_EN);
 873                return 0;
 874        }
 875
 876        /* Make sure the value is valid */
 877        alarm_value = rk_tsadcv2_temp_to_code(table, temp);
 878        if (alarm_value == table->data_mask)
 879                return -ERANGE;
 880
 881        writel_relaxed(alarm_value & table->data_mask,
 882                       regs + TSADCV2_COMP_INT(chn));
 883
 884        int_en = readl_relaxed(regs + TSADCV2_INT_EN);
 885        int_en |= TSADCV2_INT_SRC_EN(chn);
 886        writel_relaxed(int_en, regs + TSADCV2_INT_EN);
 887
 888        return 0;
 889}
 890
 891static int rk_tsadcv2_tshut_temp(const struct chip_tsadc_table *table,
 892                                 int chn, void __iomem *regs, int temp)
 893{
 894        u32 tshut_value, val;
 895
 896        /* Make sure the value is valid */
 897        tshut_value = rk_tsadcv2_temp_to_code(table, temp);
 898        if (tshut_value == table->data_mask)
 899                return -ERANGE;
 900
 901        writel_relaxed(tshut_value, regs + TSADCV2_COMP_SHUT(chn));
 902
 903        /* TSHUT will be valid */
 904        val = readl_relaxed(regs + TSADCV2_AUTO_CON);
 905        writel_relaxed(val | TSADCV2_AUTO_SRC_EN(chn), regs + TSADCV2_AUTO_CON);
 906
 907        return 0;
 908}
 909
 910static void rk_tsadcv2_tshut_mode(int chn, void __iomem *regs,
 911                                  enum tshut_mode mode)
 912{
 913        u32 val;
 914
 915        val = readl_relaxed(regs + TSADCV2_INT_EN);
 916        if (mode == TSHUT_MODE_GPIO) {
 917                val &= ~TSADCV2_SHUT_2CRU_SRC_EN(chn);
 918                val |= TSADCV2_SHUT_2GPIO_SRC_EN(chn);
 919        } else {
 920                val &= ~TSADCV2_SHUT_2GPIO_SRC_EN(chn);
 921                val |= TSADCV2_SHUT_2CRU_SRC_EN(chn);
 922        }
 923
 924        writel_relaxed(val, regs + TSADCV2_INT_EN);
 925}
 926
 927static const struct rockchip_tsadc_chip px30_tsadc_data = {
 928        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
 929        .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
 930        .chn_num = 2, /* 2 channels for tsadc */
 931
 932        .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
 933        .tshut_temp = 95000,
 934
 935        .initialize = rk_tsadcv4_initialize,
 936        .irq_ack = rk_tsadcv3_irq_ack,
 937        .control = rk_tsadcv3_control,
 938        .get_temp = rk_tsadcv2_get_temp,
 939        .set_alarm_temp = rk_tsadcv2_alarm_temp,
 940        .set_tshut_temp = rk_tsadcv2_tshut_temp,
 941        .set_tshut_mode = rk_tsadcv2_tshut_mode,
 942
 943        .table = {
 944                .id = rk3328_code_table,
 945                .length = ARRAY_SIZE(rk3328_code_table),
 946                .data_mask = TSADCV2_DATA_MASK,
 947                .mode = ADC_INCREMENT,
 948        },
 949};
 950
 951static const struct rockchip_tsadc_chip rv1108_tsadc_data = {
 952        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
 953        .chn_num = 1, /* one channel for tsadc */
 954
 955        .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
 956        .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
 957        .tshut_temp = 95000,
 958
 959        .initialize = rk_tsadcv2_initialize,
 960        .irq_ack = rk_tsadcv3_irq_ack,
 961        .control = rk_tsadcv3_control,
 962        .get_temp = rk_tsadcv2_get_temp,
 963        .set_alarm_temp = rk_tsadcv2_alarm_temp,
 964        .set_tshut_temp = rk_tsadcv2_tshut_temp,
 965        .set_tshut_mode = rk_tsadcv2_tshut_mode,
 966
 967        .table = {
 968                .id = rv1108_table,
 969                .length = ARRAY_SIZE(rv1108_table),
 970                .data_mask = TSADCV2_DATA_MASK,
 971                .mode = ADC_INCREMENT,
 972        },
 973};
 974
 975static const struct rockchip_tsadc_chip rk3228_tsadc_data = {
 976        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
 977        .chn_num = 1, /* one channel for tsadc */
 978
 979        .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
 980        .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
 981        .tshut_temp = 95000,
 982
 983        .initialize = rk_tsadcv2_initialize,
 984        .irq_ack = rk_tsadcv3_irq_ack,
 985        .control = rk_tsadcv3_control,
 986        .get_temp = rk_tsadcv2_get_temp,
 987        .set_alarm_temp = rk_tsadcv2_alarm_temp,
 988        .set_tshut_temp = rk_tsadcv2_tshut_temp,
 989        .set_tshut_mode = rk_tsadcv2_tshut_mode,
 990
 991        .table = {
 992                .id = rk3228_code_table,
 993                .length = ARRAY_SIZE(rk3228_code_table),
 994                .data_mask = TSADCV3_DATA_MASK,
 995                .mode = ADC_INCREMENT,
 996        },
 997};
 998
 999static const struct rockchip_tsadc_chip rk3288_tsadc_data = {
1000        .chn_id[SENSOR_CPU] = 1, /* cpu sensor is channel 1 */
1001        .chn_id[SENSOR_GPU] = 2, /* gpu sensor is channel 2 */
1002        .chn_num = 2, /* two channels for tsadc */
1003
1004        .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1005        .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1006        .tshut_temp = 95000,
1007
1008        .initialize = rk_tsadcv2_initialize,
1009        .irq_ack = rk_tsadcv2_irq_ack,
1010        .control = rk_tsadcv2_control,
1011        .get_temp = rk_tsadcv2_get_temp,
1012        .set_alarm_temp = rk_tsadcv2_alarm_temp,
1013        .set_tshut_temp = rk_tsadcv2_tshut_temp,
1014        .set_tshut_mode = rk_tsadcv2_tshut_mode,
1015
1016        .table = {
1017                .id = rk3288_code_table,
1018                .length = ARRAY_SIZE(rk3288_code_table),
1019                .data_mask = TSADCV2_DATA_MASK,
1020                .mode = ADC_DECREMENT,
1021        },
1022};
1023
1024static const struct rockchip_tsadc_chip rk3328_tsadc_data = {
1025        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1026        .chn_num = 1, /* one channels for tsadc */
1027
1028        .tshut_mode = TSHUT_MODE_CRU, /* default TSHUT via CRU */
1029        .tshut_temp = 95000,
1030
1031        .initialize = rk_tsadcv2_initialize,
1032        .irq_ack = rk_tsadcv3_irq_ack,
1033        .control = rk_tsadcv3_control,
1034        .get_temp = rk_tsadcv2_get_temp,
1035        .set_alarm_temp = rk_tsadcv2_alarm_temp,
1036        .set_tshut_temp = rk_tsadcv2_tshut_temp,
1037        .set_tshut_mode = rk_tsadcv2_tshut_mode,
1038
1039        .table = {
1040                .id = rk3328_code_table,
1041                .length = ARRAY_SIZE(rk3328_code_table),
1042                .data_mask = TSADCV2_DATA_MASK,
1043                .mode = ADC_INCREMENT,
1044        },
1045};
1046
1047static const struct rockchip_tsadc_chip rk3366_tsadc_data = {
1048        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1049        .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1050        .chn_num = 2, /* two channels for tsadc */
1051
1052        .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1053        .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1054        .tshut_temp = 95000,
1055
1056        .initialize = rk_tsadcv3_initialize,
1057        .irq_ack = rk_tsadcv3_irq_ack,
1058        .control = rk_tsadcv3_control,
1059        .get_temp = rk_tsadcv2_get_temp,
1060        .set_alarm_temp = rk_tsadcv2_alarm_temp,
1061        .set_tshut_temp = rk_tsadcv2_tshut_temp,
1062        .set_tshut_mode = rk_tsadcv2_tshut_mode,
1063
1064        .table = {
1065                .id = rk3228_code_table,
1066                .length = ARRAY_SIZE(rk3228_code_table),
1067                .data_mask = TSADCV3_DATA_MASK,
1068                .mode = ADC_INCREMENT,
1069        },
1070};
1071
1072static const struct rockchip_tsadc_chip rk3368_tsadc_data = {
1073        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1074        .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1075        .chn_num = 2, /* two channels for tsadc */
1076
1077        .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1078        .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1079        .tshut_temp = 95000,
1080
1081        .initialize = rk_tsadcv2_initialize,
1082        .irq_ack = rk_tsadcv2_irq_ack,
1083        .control = rk_tsadcv2_control,
1084        .get_temp = rk_tsadcv2_get_temp,
1085        .set_alarm_temp = rk_tsadcv2_alarm_temp,
1086        .set_tshut_temp = rk_tsadcv2_tshut_temp,
1087        .set_tshut_mode = rk_tsadcv2_tshut_mode,
1088
1089        .table = {
1090                .id = rk3368_code_table,
1091                .length = ARRAY_SIZE(rk3368_code_table),
1092                .data_mask = TSADCV3_DATA_MASK,
1093                .mode = ADC_INCREMENT,
1094        },
1095};
1096
1097static const struct rockchip_tsadc_chip rk3399_tsadc_data = {
1098        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1099        .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1100        .chn_num = 2, /* two channels for tsadc */
1101
1102        .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1103        .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1104        .tshut_temp = 95000,
1105
1106        .initialize = rk_tsadcv3_initialize,
1107        .irq_ack = rk_tsadcv3_irq_ack,
1108        .control = rk_tsadcv3_control,
1109        .get_temp = rk_tsadcv2_get_temp,
1110        .set_alarm_temp = rk_tsadcv2_alarm_temp,
1111        .set_tshut_temp = rk_tsadcv2_tshut_temp,
1112        .set_tshut_mode = rk_tsadcv2_tshut_mode,
1113
1114        .table = {
1115                .id = rk3399_code_table,
1116                .length = ARRAY_SIZE(rk3399_code_table),
1117                .data_mask = TSADCV3_DATA_MASK,
1118                .mode = ADC_INCREMENT,
1119        },
1120};
1121
1122static const struct rockchip_tsadc_chip rk3568_tsadc_data = {
1123        .chn_id[SENSOR_CPU] = 0, /* cpu sensor is channel 0 */
1124        .chn_id[SENSOR_GPU] = 1, /* gpu sensor is channel 1 */
1125        .chn_num = 2, /* two channels for tsadc */
1126
1127        .tshut_mode = TSHUT_MODE_GPIO, /* default TSHUT via GPIO give PMIC */
1128        .tshut_polarity = TSHUT_LOW_ACTIVE, /* default TSHUT LOW ACTIVE */
1129        .tshut_temp = 95000,
1130
1131        .initialize = rk_tsadcv7_initialize,
1132        .irq_ack = rk_tsadcv3_irq_ack,
1133        .control = rk_tsadcv3_control,
1134        .get_temp = rk_tsadcv2_get_temp,
1135        .set_alarm_temp = rk_tsadcv2_alarm_temp,
1136        .set_tshut_temp = rk_tsadcv2_tshut_temp,
1137        .set_tshut_mode = rk_tsadcv2_tshut_mode,
1138
1139        .table = {
1140                .id = rk3568_code_table,
1141                .length = ARRAY_SIZE(rk3568_code_table),
1142                .data_mask = TSADCV2_DATA_MASK,
1143                .mode = ADC_INCREMENT,
1144        },
1145};
1146
1147static const struct of_device_id of_rockchip_thermal_match[] = {
1148        {       .compatible = "rockchip,px30-tsadc",
1149                .data = (void *)&px30_tsadc_data,
1150        },
1151        {
1152                .compatible = "rockchip,rv1108-tsadc",
1153                .data = (void *)&rv1108_tsadc_data,
1154        },
1155        {
1156                .compatible = "rockchip,rk3228-tsadc",
1157                .data = (void *)&rk3228_tsadc_data,
1158        },
1159        {
1160                .compatible = "rockchip,rk3288-tsadc",
1161                .data = (void *)&rk3288_tsadc_data,
1162        },
1163        {
1164                .compatible = "rockchip,rk3328-tsadc",
1165                .data = (void *)&rk3328_tsadc_data,
1166        },
1167        {
1168                .compatible = "rockchip,rk3366-tsadc",
1169                .data = (void *)&rk3366_tsadc_data,
1170        },
1171        {
1172                .compatible = "rockchip,rk3368-tsadc",
1173                .data = (void *)&rk3368_tsadc_data,
1174        },
1175        {
1176                .compatible = "rockchip,rk3399-tsadc",
1177                .data = (void *)&rk3399_tsadc_data,
1178        },
1179        {
1180                .compatible = "rockchip,rk3568-tsadc",
1181                .data = (void *)&rk3568_tsadc_data,
1182        },
1183        { /* end */ },
1184};
1185MODULE_DEVICE_TABLE(of, of_rockchip_thermal_match);
1186
1187static void
1188rockchip_thermal_toggle_sensor(struct rockchip_thermal_sensor *sensor, bool on)
1189{
1190        struct thermal_zone_device *tzd = sensor->tzd;
1191
1192        if (on)
1193                thermal_zone_device_enable(tzd);
1194        else
1195                thermal_zone_device_disable(tzd);
1196}
1197
1198static irqreturn_t rockchip_thermal_alarm_irq_thread(int irq, void *dev)
1199{
1200        struct rockchip_thermal_data *thermal = dev;
1201        int i;
1202
1203        dev_dbg(&thermal->pdev->dev, "thermal alarm\n");
1204
1205        thermal->chip->irq_ack(thermal->regs);
1206
1207        for (i = 0; i < thermal->chip->chn_num; i++)
1208                thermal_zone_device_update(thermal->sensors[i].tzd,
1209                                           THERMAL_EVENT_UNSPECIFIED);
1210
1211        return IRQ_HANDLED;
1212}
1213
1214static int rockchip_thermal_set_trips(void *_sensor, int low, int high)
1215{
1216        struct rockchip_thermal_sensor *sensor = _sensor;
1217        struct rockchip_thermal_data *thermal = sensor->thermal;
1218        const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1219
1220        dev_dbg(&thermal->pdev->dev, "%s: sensor %d: low: %d, high %d\n",
1221                __func__, sensor->id, low, high);
1222
1223        return tsadc->set_alarm_temp(&tsadc->table,
1224                                     sensor->id, thermal->regs, high);
1225}
1226
1227static int rockchip_thermal_get_temp(void *_sensor, int *out_temp)
1228{
1229        struct rockchip_thermal_sensor *sensor = _sensor;
1230        struct rockchip_thermal_data *thermal = sensor->thermal;
1231        const struct rockchip_tsadc_chip *tsadc = sensor->thermal->chip;
1232        int retval;
1233
1234        retval = tsadc->get_temp(&tsadc->table,
1235                                 sensor->id, thermal->regs, out_temp);
1236        dev_dbg(&thermal->pdev->dev, "sensor %d - temp: %d, retval: %d\n",
1237                sensor->id, *out_temp, retval);
1238
1239        return retval;
1240}
1241
1242static const struct thermal_zone_of_device_ops rockchip_of_thermal_ops = {
1243        .get_temp = rockchip_thermal_get_temp,
1244        .set_trips = rockchip_thermal_set_trips,
1245};
1246
1247static int rockchip_configure_from_dt(struct device *dev,
1248                                      struct device_node *np,
1249                                      struct rockchip_thermal_data *thermal)
1250{
1251        u32 shut_temp, tshut_mode, tshut_polarity;
1252
1253        if (of_property_read_u32(np, "rockchip,hw-tshut-temp", &shut_temp)) {
1254                dev_warn(dev,
1255                         "Missing tshut temp property, using default %d\n",
1256                         thermal->chip->tshut_temp);
1257                thermal->tshut_temp = thermal->chip->tshut_temp;
1258        } else {
1259                if (shut_temp > INT_MAX) {
1260                        dev_err(dev, "Invalid tshut temperature specified: %d\n",
1261                                shut_temp);
1262                        return -ERANGE;
1263                }
1264                thermal->tshut_temp = shut_temp;
1265        }
1266
1267        if (of_property_read_u32(np, "rockchip,hw-tshut-mode", &tshut_mode)) {
1268                dev_warn(dev,
1269                         "Missing tshut mode property, using default (%s)\n",
1270                         thermal->chip->tshut_mode == TSHUT_MODE_GPIO ?
1271                                "gpio" : "cru");
1272                thermal->tshut_mode = thermal->chip->tshut_mode;
1273        } else {
1274                thermal->tshut_mode = tshut_mode;
1275        }
1276
1277        if (thermal->tshut_mode > 1) {
1278                dev_err(dev, "Invalid tshut mode specified: %d\n",
1279                        thermal->tshut_mode);
1280                return -EINVAL;
1281        }
1282
1283        if (of_property_read_u32(np, "rockchip,hw-tshut-polarity",
1284                                 &tshut_polarity)) {
1285                dev_warn(dev,
1286                         "Missing tshut-polarity property, using default (%s)\n",
1287                         thermal->chip->tshut_polarity == TSHUT_LOW_ACTIVE ?
1288                                "low" : "high");
1289                thermal->tshut_polarity = thermal->chip->tshut_polarity;
1290        } else {
1291                thermal->tshut_polarity = tshut_polarity;
1292        }
1293
1294        if (thermal->tshut_polarity > 1) {
1295                dev_err(dev, "Invalid tshut-polarity specified: %d\n",
1296                        thermal->tshut_polarity);
1297                return -EINVAL;
1298        }
1299
1300        /* The tsadc wont to handle the error in here since some SoCs didn't
1301         * need this property.
1302         */
1303        thermal->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
1304        if (IS_ERR(thermal->grf))
1305                dev_warn(dev, "Missing rockchip,grf property\n");
1306
1307        return 0;
1308}
1309
1310static int
1311rockchip_thermal_register_sensor(struct platform_device *pdev,
1312                                 struct rockchip_thermal_data *thermal,
1313                                 struct rockchip_thermal_sensor *sensor,
1314                                 int id)
1315{
1316        const struct rockchip_tsadc_chip *tsadc = thermal->chip;
1317        int error;
1318
1319        tsadc->set_tshut_mode(id, thermal->regs, thermal->tshut_mode);
1320
1321        error = tsadc->set_tshut_temp(&tsadc->table, id, thermal->regs,
1322                              thermal->tshut_temp);
1323        if (error)
1324                dev_err(&pdev->dev, "%s: invalid tshut=%d, error=%d\n",
1325                        __func__, thermal->tshut_temp, error);
1326
1327        sensor->thermal = thermal;
1328        sensor->id = id;
1329        sensor->tzd = devm_thermal_zone_of_sensor_register(&pdev->dev, id,
1330                                        sensor, &rockchip_of_thermal_ops);
1331        if (IS_ERR(sensor->tzd)) {
1332                error = PTR_ERR(sensor->tzd);
1333                dev_err(&pdev->dev, "failed to register sensor %d: %d\n",
1334                        id, error);
1335                return error;
1336        }
1337
1338        return 0;
1339}
1340
1341/**
1342 * Reset TSADC Controller, reset all tsadc registers.
1343 * @reset: the reset controller of tsadc
1344 */
1345static void rockchip_thermal_reset_controller(struct reset_control *reset)
1346{
1347        reset_control_assert(reset);
1348        usleep_range(10, 20);
1349        reset_control_deassert(reset);
1350}
1351
1352static int rockchip_thermal_probe(struct platform_device *pdev)
1353{
1354        struct device_node *np = pdev->dev.of_node;
1355        struct rockchip_thermal_data *thermal;
1356        const struct of_device_id *match;
1357        struct resource *res;
1358        int irq;
1359        int i;
1360        int error;
1361
1362        match = of_match_node(of_rockchip_thermal_match, np);
1363        if (!match)
1364                return -ENXIO;
1365
1366        irq = platform_get_irq(pdev, 0);
1367        if (irq < 0)
1368                return -EINVAL;
1369
1370        thermal = devm_kzalloc(&pdev->dev, sizeof(struct rockchip_thermal_data),
1371                               GFP_KERNEL);
1372        if (!thermal)
1373                return -ENOMEM;
1374
1375        thermal->pdev = pdev;
1376
1377        thermal->chip = (const struct rockchip_tsadc_chip *)match->data;
1378        if (!thermal->chip)
1379                return -EINVAL;
1380
1381        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1382        thermal->regs = devm_ioremap_resource(&pdev->dev, res);
1383        if (IS_ERR(thermal->regs))
1384                return PTR_ERR(thermal->regs);
1385
1386        thermal->reset = devm_reset_control_get(&pdev->dev, "tsadc-apb");
1387        if (IS_ERR(thermal->reset)) {
1388                error = PTR_ERR(thermal->reset);
1389                dev_err(&pdev->dev, "failed to get tsadc reset: %d\n", error);
1390                return error;
1391        }
1392
1393        thermal->clk = devm_clk_get(&pdev->dev, "tsadc");
1394        if (IS_ERR(thermal->clk)) {
1395                error = PTR_ERR(thermal->clk);
1396                dev_err(&pdev->dev, "failed to get tsadc clock: %d\n", error);
1397                return error;
1398        }
1399
1400        thermal->pclk = devm_clk_get(&pdev->dev, "apb_pclk");
1401        if (IS_ERR(thermal->pclk)) {
1402                error = PTR_ERR(thermal->pclk);
1403                dev_err(&pdev->dev, "failed to get apb_pclk clock: %d\n",
1404                        error);
1405                return error;
1406        }
1407
1408        error = clk_prepare_enable(thermal->clk);
1409        if (error) {
1410                dev_err(&pdev->dev, "failed to enable converter clock: %d\n",
1411                        error);
1412                return error;
1413        }
1414
1415        error = clk_prepare_enable(thermal->pclk);
1416        if (error) {
1417                dev_err(&pdev->dev, "failed to enable pclk: %d\n", error);
1418                goto err_disable_clk;
1419        }
1420
1421        rockchip_thermal_reset_controller(thermal->reset);
1422
1423        error = rockchip_configure_from_dt(&pdev->dev, np, thermal);
1424        if (error) {
1425                dev_err(&pdev->dev, "failed to parse device tree data: %d\n",
1426                        error);
1427                goto err_disable_pclk;
1428        }
1429
1430        thermal->chip->initialize(thermal->grf, thermal->regs,
1431                                  thermal->tshut_polarity);
1432
1433        for (i = 0; i < thermal->chip->chn_num; i++) {
1434                error = rockchip_thermal_register_sensor(pdev, thermal,
1435                                                &thermal->sensors[i],
1436                                                thermal->chip->chn_id[i]);
1437                if (error) {
1438                        dev_err(&pdev->dev,
1439                                "failed to register sensor[%d] : error = %d\n",
1440                                i, error);
1441                        goto err_disable_pclk;
1442                }
1443        }
1444
1445        error = devm_request_threaded_irq(&pdev->dev, irq, NULL,
1446                                          &rockchip_thermal_alarm_irq_thread,
1447                                          IRQF_ONESHOT,
1448                                          "rockchip_thermal", thermal);
1449        if (error) {
1450                dev_err(&pdev->dev,
1451                        "failed to request tsadc irq: %d\n", error);
1452                goto err_disable_pclk;
1453        }
1454
1455        thermal->chip->control(thermal->regs, true);
1456
1457        for (i = 0; i < thermal->chip->chn_num; i++) {
1458                rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1459                thermal->sensors[i].tzd->tzp->no_hwmon = false;
1460                error = thermal_add_hwmon_sysfs(thermal->sensors[i].tzd);
1461                if (error)
1462                        dev_warn(&pdev->dev,
1463                                 "failed to register sensor %d with hwmon: %d\n",
1464                                 i, error);
1465        }
1466
1467        platform_set_drvdata(pdev, thermal);
1468
1469        return 0;
1470
1471err_disable_pclk:
1472        clk_disable_unprepare(thermal->pclk);
1473err_disable_clk:
1474        clk_disable_unprepare(thermal->clk);
1475
1476        return error;
1477}
1478
1479static int rockchip_thermal_remove(struct platform_device *pdev)
1480{
1481        struct rockchip_thermal_data *thermal = platform_get_drvdata(pdev);
1482        int i;
1483
1484        for (i = 0; i < thermal->chip->chn_num; i++) {
1485                struct rockchip_thermal_sensor *sensor = &thermal->sensors[i];
1486
1487                thermal_remove_hwmon_sysfs(sensor->tzd);
1488                rockchip_thermal_toggle_sensor(sensor, false);
1489        }
1490
1491        thermal->chip->control(thermal->regs, false);
1492
1493        clk_disable_unprepare(thermal->pclk);
1494        clk_disable_unprepare(thermal->clk);
1495
1496        return 0;
1497}
1498
1499static int __maybe_unused rockchip_thermal_suspend(struct device *dev)
1500{
1501        struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1502        int i;
1503
1504        for (i = 0; i < thermal->chip->chn_num; i++)
1505                rockchip_thermal_toggle_sensor(&thermal->sensors[i], false);
1506
1507        thermal->chip->control(thermal->regs, false);
1508
1509        clk_disable(thermal->pclk);
1510        clk_disable(thermal->clk);
1511
1512        pinctrl_pm_select_sleep_state(dev);
1513
1514        return 0;
1515}
1516
1517static int __maybe_unused rockchip_thermal_resume(struct device *dev)
1518{
1519        struct rockchip_thermal_data *thermal = dev_get_drvdata(dev);
1520        int i;
1521        int error;
1522
1523        error = clk_enable(thermal->clk);
1524        if (error)
1525                return error;
1526
1527        error = clk_enable(thermal->pclk);
1528        if (error) {
1529                clk_disable(thermal->clk);
1530                return error;
1531        }
1532
1533        rockchip_thermal_reset_controller(thermal->reset);
1534
1535        thermal->chip->initialize(thermal->grf, thermal->regs,
1536                                  thermal->tshut_polarity);
1537
1538        for (i = 0; i < thermal->chip->chn_num; i++) {
1539                int id = thermal->sensors[i].id;
1540
1541                thermal->chip->set_tshut_mode(id, thermal->regs,
1542                                              thermal->tshut_mode);
1543
1544                error = thermal->chip->set_tshut_temp(&thermal->chip->table,
1545                                              id, thermal->regs,
1546                                              thermal->tshut_temp);
1547                if (error)
1548                        dev_err(dev, "%s: invalid tshut=%d, error=%d\n",
1549                                __func__, thermal->tshut_temp, error);
1550        }
1551
1552        thermal->chip->control(thermal->regs, true);
1553
1554        for (i = 0; i < thermal->chip->chn_num; i++)
1555                rockchip_thermal_toggle_sensor(&thermal->sensors[i], true);
1556
1557        pinctrl_pm_select_default_state(dev);
1558
1559        return 0;
1560}
1561
1562static SIMPLE_DEV_PM_OPS(rockchip_thermal_pm_ops,
1563                         rockchip_thermal_suspend, rockchip_thermal_resume);
1564
1565static struct platform_driver rockchip_thermal_driver = {
1566        .driver = {
1567                .name = "rockchip-thermal",
1568                .pm = &rockchip_thermal_pm_ops,
1569                .of_match_table = of_rockchip_thermal_match,
1570        },
1571        .probe = rockchip_thermal_probe,
1572        .remove = rockchip_thermal_remove,
1573};
1574
1575module_platform_driver(rockchip_thermal_driver);
1576
1577MODULE_DESCRIPTION("ROCKCHIP THERMAL Driver");
1578MODULE_AUTHOR("Rockchip, Inc.");
1579MODULE_LICENSE("GPL v2");
1580MODULE_ALIAS("platform:rockchip-thermal");
1581