linux/drivers/staging/media/imx/imx7-mipi-csis.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Freescale i.MX7 SoC series MIPI-CSI V3.3 receiver driver
   4 *
   5 * Copyright (C) 2019 Linaro Ltd
   6 * Copyright (C) 2015-2016 Freescale Semiconductor, Inc. All Rights Reserved.
   7 * Copyright (C) 2011 - 2013 Samsung Electronics Co., Ltd.
   8 *
   9 */
  10
  11#include <linux/clk.h>
  12#include <linux/debugfs.h>
  13#include <linux/delay.h>
  14#include <linux/errno.h>
  15#include <linux/interrupt.h>
  16#include <linux/io.h>
  17#include <linux/kernel.h>
  18#include <linux/module.h>
  19#include <linux/mutex.h>
  20#include <linux/of.h>
  21#include <linux/of_device.h>
  22#include <linux/platform_device.h>
  23#include <linux/pm_runtime.h>
  24#include <linux/regulator/consumer.h>
  25#include <linux/reset.h>
  26#include <linux/spinlock.h>
  27
  28#include <media/v4l2-common.h>
  29#include <media/v4l2-device.h>
  30#include <media/v4l2-fwnode.h>
  31#include <media/v4l2-mc.h>
  32#include <media/v4l2-subdev.h>
  33
  34#define CSIS_DRIVER_NAME                        "imx7-mipi-csis"
  35#define CSIS_SUBDEV_NAME                        CSIS_DRIVER_NAME
  36
  37#define CSIS_PAD_SINK                           0
  38#define CSIS_PAD_SOURCE                         1
  39#define CSIS_PADS_NUM                           2
  40
  41#define MIPI_CSIS_DEF_PIX_WIDTH                 640
  42#define MIPI_CSIS_DEF_PIX_HEIGHT                480
  43
  44/* Register map definition */
  45
  46/* CSIS common control */
  47#define MIPI_CSIS_CMN_CTRL                      0x04
  48#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW        BIT(16)
  49#define MIPI_CSIS_CMN_CTRL_INTER_MODE           BIT(10)
  50#define MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL   BIT(2)
  51#define MIPI_CSIS_CMN_CTRL_RESET                BIT(1)
  52#define MIPI_CSIS_CMN_CTRL_ENABLE               BIT(0)
  53
  54#define MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET       8
  55#define MIPI_CSIS_CMN_CTRL_LANE_NR_MASK         (3 << 8)
  56
  57/* CSIS clock control */
  58#define MIPI_CSIS_CLK_CTRL                      0x08
  59#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH3(x) ((x) << 28)
  60#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH2(x) ((x) << 24)
  61#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH1(x) ((x) << 20)
  62#define MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(x) ((x) << 16)
  63#define MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK       (0xf << 4)
  64#define MIPI_CSIS_CLK_CTRL_WCLK_SRC             BIT(0)
  65
  66/* CSIS Interrupt mask */
  67#define MIPI_CSIS_INT_MSK                       0x10
  68#define MIPI_CSIS_INT_MSK_EVEN_BEFORE           BIT(31)
  69#define MIPI_CSIS_INT_MSK_EVEN_AFTER            BIT(30)
  70#define MIPI_CSIS_INT_MSK_ODD_BEFORE            BIT(29)
  71#define MIPI_CSIS_INT_MSK_ODD_AFTER             BIT(28)
  72#define MIPI_CSIS_INT_MSK_FRAME_START           BIT(24)
  73#define MIPI_CSIS_INT_MSK_FRAME_END             BIT(20)
  74#define MIPI_CSIS_INT_MSK_ERR_SOT_HS            BIT(16)
  75#define MIPI_CSIS_INT_MSK_ERR_LOST_FS           BIT(12)
  76#define MIPI_CSIS_INT_MSK_ERR_LOST_FE           BIT(8)
  77#define MIPI_CSIS_INT_MSK_ERR_OVER              BIT(4)
  78#define MIPI_CSIS_INT_MSK_ERR_WRONG_CFG         BIT(3)
  79#define MIPI_CSIS_INT_MSK_ERR_ECC               BIT(2)
  80#define MIPI_CSIS_INT_MSK_ERR_CRC               BIT(1)
  81#define MIPI_CSIS_INT_MSK_ERR_UNKNOWN           BIT(0)
  82
  83/* CSIS Interrupt source */
  84#define MIPI_CSIS_INT_SRC                       0x14
  85#define MIPI_CSIS_INT_SRC_EVEN_BEFORE           BIT(31)
  86#define MIPI_CSIS_INT_SRC_EVEN_AFTER            BIT(30)
  87#define MIPI_CSIS_INT_SRC_EVEN                  BIT(30)
  88#define MIPI_CSIS_INT_SRC_ODD_BEFORE            BIT(29)
  89#define MIPI_CSIS_INT_SRC_ODD_AFTER             BIT(28)
  90#define MIPI_CSIS_INT_SRC_ODD                   (0x3 << 28)
  91#define MIPI_CSIS_INT_SRC_NON_IMAGE_DATA        (0xf << 28)
  92#define MIPI_CSIS_INT_SRC_FRAME_START           BIT(24)
  93#define MIPI_CSIS_INT_SRC_FRAME_END             BIT(20)
  94#define MIPI_CSIS_INT_SRC_ERR_SOT_HS            BIT(16)
  95#define MIPI_CSIS_INT_SRC_ERR_LOST_FS           BIT(12)
  96#define MIPI_CSIS_INT_SRC_ERR_LOST_FE           BIT(8)
  97#define MIPI_CSIS_INT_SRC_ERR_OVER              BIT(4)
  98#define MIPI_CSIS_INT_SRC_ERR_WRONG_CFG         BIT(3)
  99#define MIPI_CSIS_INT_SRC_ERR_ECC               BIT(2)
 100#define MIPI_CSIS_INT_SRC_ERR_CRC               BIT(1)
 101#define MIPI_CSIS_INT_SRC_ERR_UNKNOWN           BIT(0)
 102#define MIPI_CSIS_INT_SRC_ERRORS                0xfffff
 103
 104/* D-PHY status control */
 105#define MIPI_CSIS_DPHY_STATUS                   0x20
 106#define MIPI_CSIS_DPHY_STATUS_ULPS_DAT          BIT(8)
 107#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_DAT     BIT(4)
 108#define MIPI_CSIS_DPHY_STATUS_ULPS_CLK          BIT(1)
 109#define MIPI_CSIS_DPHY_STATUS_STOPSTATE_CLK     BIT(0)
 110
 111/* D-PHY common control */
 112#define MIPI_CSIS_DPHY_CMN_CTRL                 0x24
 113#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(n)     ((n) << 24)
 114#define MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE_MASK   GENMASK(31, 24)
 115#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(n)    ((n) << 22)
 116#define MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE_MASK  GENMASK(23, 22)
 117#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_CLK   BIT(6)
 118#define MIPI_CSIS_DPHY_CMN_CTRL_DPDN_SWAP_DAT   BIT(5)
 119#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_DAT      BIT(1)
 120#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE_CLK      BIT(0)
 121#define MIPI_CSIS_DPHY_CMN_CTRL_ENABLE          (0x1f << 0)
 122
 123/* D-PHY Master and Slave Control register Low */
 124#define MIPI_CSIS_DPHY_BCTRL_L                  0x30
 125#define MIPI_CSIS_DPHY_BCTRL_L_USER_DATA_PATTERN_LOW(n)         (((n) & 3U) << 30)
 126#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV              (0 << 28)
 127#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_724MV              (1 << 28)
 128#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_733MV              (2 << 28)
 129#define MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_706MV              (3 << 28)
 130#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ            (0 << 27)
 131#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_1_5MHZ          (1 << 27)
 132#define MIPI_CSIS_DPHY_BCTRL_L_VREG12_EXTPWR_EN_CTL             BIT(26)
 133#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V             (0 << 24)
 134#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_23V            (1 << 24)
 135#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_17V            (2 << 24)
 136#define MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_26V            (3 << 24)
 137#define MIPI_CSIS_DPHY_BCTRL_L_REG_1P2_LVL_SEL                  BIT(23)
 138#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV               (0 << 21)
 139#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_100MV              (1 << 21)
 140#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_120MV              (2 << 21)
 141#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_140MV              (3 << 21)
 142#define MIPI_CSIS_DPHY_BCTRL_L_VREF_SRC_SEL                     BIT(20)
 143#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV             (0 << 18)
 144#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_743MV             (1 << 18)
 145#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_650MV             (2 << 18)
 146#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_682MV             (3 << 18)
 147#define MIPI_CSIS_DPHY_BCTRL_L_LP_RX_PULSE_REJECT               BIT(17)
 148#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_0      (0 << 15)
 149#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_15P    (1 << 15)
 150#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_DOWN_30P    (3 << 15)
 151#define MIPI_CSIS_DPHY_BCTRL_L_MSTRCLK_LP_SLEW_RATE_UP          BIT(14)
 152#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV                   (0 << 13)
 153#define MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_70MV                   (1 << 13)
 154#define MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_EN                   BIT(12)
 155#define MIPI_CSIS_DPHY_BCTRL_L_ERRCONTENTION_LP_EN              BIT(11)
 156#define MIPI_CSIS_DPHY_BCTRL_L_TXTRIGGER_CLK_EN                 BIT(10)
 157#define MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(n)                    (((n) * 25 / 1000000) << 0)
 158
 159/* D-PHY Master and Slave Control register High */
 160#define MIPI_CSIS_DPHY_BCTRL_H                  0x34
 161/* D-PHY Slave Control register Low */
 162#define MIPI_CSIS_DPHY_SCTRL_L                  0x38
 163/* D-PHY Slave Control register High */
 164#define MIPI_CSIS_DPHY_SCTRL_H                  0x3c
 165
 166/* ISP Configuration register */
 167#define MIPI_CSIS_ISP_CONFIG_CH(n)              (0x40 + (n) * 0x10)
 168#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP_MSK       (0xff << 24)
 169#define MIPI_CSIS_ISPCFG_MEM_FULL_GAP(x)        ((x) << 24)
 170#define MIPI_CSIS_ISPCFG_PIXEL_MODE_SINGLE      (0 << 12)
 171#define MIPI_CSIS_ISPCFG_PIXEL_MODE_DUAL        (1 << 12)
 172#define MIPI_CSIS_ISPCFG_PIXEL_MODE_QUAD        (2 << 12)       /* i.MX8M[MNP] only */
 173#define MIPI_CSIS_ISPCFG_ALIGN_32BIT            BIT(11)
 174#define MIPI_CSIS_ISPCFG_FMT(fmt)               ((fmt) << 2)
 175#define MIPI_CSIS_ISPCFG_FMT_MASK               (0x3f << 2)
 176
 177/* ISP Image Resolution register */
 178#define MIPI_CSIS_ISP_RESOL_CH(n)               (0x44 + (n) * 0x10)
 179#define CSIS_MAX_PIX_WIDTH                      0xffff
 180#define CSIS_MAX_PIX_HEIGHT                     0xffff
 181
 182/* ISP SYNC register */
 183#define MIPI_CSIS_ISP_SYNC_CH(n)                (0x48 + (n) * 0x10)
 184#define MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET   18
 185#define MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET   12
 186#define MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET   0
 187
 188/* ISP shadow registers */
 189#define MIPI_CSIS_SDW_CONFIG_CH(n)              (0x80 + (n) * 0x10)
 190#define MIPI_CSIS_SDW_RESOL_CH(n)               (0x84 + (n) * 0x10)
 191#define MIPI_CSIS_SDW_SYNC_CH(n)                (0x88 + (n) * 0x10)
 192
 193/* Debug control register */
 194#define MIPI_CSIS_DBG_CTRL                      0xc0
 195#define MIPI_CSIS_DBG_INTR_MSK                  0xc4
 196#define MIPI_CSIS_DBG_INTR_MSK_DT_NOT_SUPPORT   BIT(25)
 197#define MIPI_CSIS_DBG_INTR_MSK_DT_IGNORE        BIT(24)
 198#define MIPI_CSIS_DBG_INTR_MSK_ERR_FRAME_SIZE   BIT(20)
 199#define MIPI_CSIS_DBG_INTR_MSK_TRUNCATED_FRAME  BIT(16)
 200#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FE         BIT(12)
 201#define MIPI_CSIS_DBG_INTR_MSK_EARLY_FS         BIT(8)
 202#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_FALL   BIT(4)
 203#define MIPI_CSIS_DBG_INTR_MSK_CAM_VSYNC_RISE   BIT(0)
 204#define MIPI_CSIS_DBG_INTR_SRC                  0xc8
 205#define MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT   BIT(25)
 206#define MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE        BIT(24)
 207#define MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE   BIT(20)
 208#define MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME  BIT(16)
 209#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FE         BIT(12)
 210#define MIPI_CSIS_DBG_INTR_SRC_EARLY_FS         BIT(8)
 211#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL   BIT(4)
 212#define MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE   BIT(0)
 213
 214/* Non-image packet data buffers */
 215#define MIPI_CSIS_PKTDATA_ODD                   0x2000
 216#define MIPI_CSIS_PKTDATA_EVEN                  0x3000
 217#define MIPI_CSIS_PKTDATA_SIZE                  SZ_4K
 218
 219#define DEFAULT_SCLK_CSIS_FREQ                  166000000UL
 220
 221/* MIPI CSI-2 Data Types */
 222#define MIPI_CSI2_DATA_TYPE_YUV420_8            0x18
 223#define MIPI_CSI2_DATA_TYPE_YUV420_10           0x19
 224#define MIPI_CSI2_DATA_TYPE_LE_YUV420_8         0x1a
 225#define MIPI_CSI2_DATA_TYPE_CS_YUV420_8         0x1c
 226#define MIPI_CSI2_DATA_TYPE_CS_YUV420_10        0x1d
 227#define MIPI_CSI2_DATA_TYPE_YUV422_8            0x1e
 228#define MIPI_CSI2_DATA_TYPE_YUV422_10           0x1f
 229#define MIPI_CSI2_DATA_TYPE_RGB565              0x22
 230#define MIPI_CSI2_DATA_TYPE_RGB666              0x23
 231#define MIPI_CSI2_DATA_TYPE_RGB888              0x24
 232#define MIPI_CSI2_DATA_TYPE_RAW6                0x28
 233#define MIPI_CSI2_DATA_TYPE_RAW7                0x29
 234#define MIPI_CSI2_DATA_TYPE_RAW8                0x2a
 235#define MIPI_CSI2_DATA_TYPE_RAW10               0x2b
 236#define MIPI_CSI2_DATA_TYPE_RAW12               0x2c
 237#define MIPI_CSI2_DATA_TYPE_RAW14               0x2d
 238#define MIPI_CSI2_DATA_TYPE_USER(x)             (0x30 + (x))
 239
 240enum {
 241        ST_POWERED      = 1,
 242        ST_STREAMING    = 2,
 243        ST_SUSPENDED    = 4,
 244};
 245
 246struct mipi_csis_event {
 247        bool debug;
 248        u32 mask;
 249        const char * const name;
 250        unsigned int counter;
 251};
 252
 253static const struct mipi_csis_event mipi_csis_events[] = {
 254        /* Errors */
 255        { false, MIPI_CSIS_INT_SRC_ERR_SOT_HS,          "SOT Error" },
 256        { false, MIPI_CSIS_INT_SRC_ERR_LOST_FS,         "Lost Frame Start Error" },
 257        { false, MIPI_CSIS_INT_SRC_ERR_LOST_FE,         "Lost Frame End Error" },
 258        { false, MIPI_CSIS_INT_SRC_ERR_OVER,            "FIFO Overflow Error" },
 259        { false, MIPI_CSIS_INT_SRC_ERR_WRONG_CFG,       "Wrong Configuration Error" },
 260        { false, MIPI_CSIS_INT_SRC_ERR_ECC,             "ECC Error" },
 261        { false, MIPI_CSIS_INT_SRC_ERR_CRC,             "CRC Error" },
 262        { false, MIPI_CSIS_INT_SRC_ERR_UNKNOWN,         "Unknown Error" },
 263        { true, MIPI_CSIS_DBG_INTR_SRC_DT_NOT_SUPPORT,  "Data Type Not Supported" },
 264        { true, MIPI_CSIS_DBG_INTR_SRC_DT_IGNORE,       "Data Type Ignored" },
 265        { true, MIPI_CSIS_DBG_INTR_SRC_ERR_FRAME_SIZE,  "Frame Size Error" },
 266        { true, MIPI_CSIS_DBG_INTR_SRC_TRUNCATED_FRAME, "Truncated Frame" },
 267        { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FE,        "Early Frame End" },
 268        { true, MIPI_CSIS_DBG_INTR_SRC_EARLY_FS,        "Early Frame Start" },
 269        /* Non-image data receive events */
 270        { false, MIPI_CSIS_INT_SRC_EVEN_BEFORE,         "Non-image data before even frame" },
 271        { false, MIPI_CSIS_INT_SRC_EVEN_AFTER,          "Non-image data after even frame" },
 272        { false, MIPI_CSIS_INT_SRC_ODD_BEFORE,          "Non-image data before odd frame" },
 273        { false, MIPI_CSIS_INT_SRC_ODD_AFTER,           "Non-image data after odd frame" },
 274        /* Frame start/end */
 275        { false, MIPI_CSIS_INT_SRC_FRAME_START,         "Frame Start" },
 276        { false, MIPI_CSIS_INT_SRC_FRAME_END,           "Frame End" },
 277        { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_FALL,  "VSYNC Falling Edge" },
 278        { true, MIPI_CSIS_DBG_INTR_SRC_CAM_VSYNC_RISE,  "VSYNC Rising Edge" },
 279};
 280
 281#define MIPI_CSIS_NUM_EVENTS ARRAY_SIZE(mipi_csis_events)
 282
 283enum mipi_csis_clk {
 284        MIPI_CSIS_CLK_PCLK,
 285        MIPI_CSIS_CLK_WRAP,
 286        MIPI_CSIS_CLK_PHY,
 287        MIPI_CSIS_CLK_AXI,
 288};
 289
 290static const char * const mipi_csis_clk_id[] = {
 291        "pclk",
 292        "wrap",
 293        "phy",
 294        "axi",
 295};
 296
 297enum mipi_csis_version {
 298        MIPI_CSIS_V3_3,
 299        MIPI_CSIS_V3_6_3,
 300};
 301
 302struct mipi_csis_info {
 303        enum mipi_csis_version version;
 304        unsigned int num_clocks;
 305};
 306
 307struct csi_state {
 308        struct device *dev;
 309        void __iomem *regs;
 310        struct clk_bulk_data *clks;
 311        struct reset_control *mrst;
 312        struct regulator *mipi_phy_regulator;
 313        const struct mipi_csis_info *info;
 314        u8 index;
 315
 316        struct v4l2_subdev sd;
 317        struct media_pad pads[CSIS_PADS_NUM];
 318        struct v4l2_async_notifier notifier;
 319        struct v4l2_subdev *src_sd;
 320
 321        struct v4l2_fwnode_bus_mipi_csi2 bus;
 322        u32 clk_frequency;
 323        u32 hs_settle;
 324        u32 clk_settle;
 325
 326        struct mutex lock;      /* Protect csis_fmt, format_mbus and state */
 327        const struct csis_pix_format *csis_fmt;
 328        struct v4l2_mbus_framefmt format_mbus;
 329        u32 state;
 330
 331        spinlock_t slock;       /* Protect events */
 332        struct mipi_csis_event events[MIPI_CSIS_NUM_EVENTS];
 333        struct dentry *debugfs_root;
 334        bool debug;
 335};
 336
 337/* -----------------------------------------------------------------------------
 338 * Format helpers
 339 */
 340
 341struct csis_pix_format {
 342        u32 code;
 343        u32 data_type;
 344        u8 width;
 345};
 346
 347static const struct csis_pix_format mipi_csis_formats[] = {
 348        /* YUV formats. */
 349        {
 350                .code = MEDIA_BUS_FMT_UYVY8_1X16,
 351                .data_type = MIPI_CSI2_DATA_TYPE_YUV422_8,
 352                .width = 16,
 353        },
 354        /* RAW (Bayer and greyscale) formats. */
 355        {
 356                .code = MEDIA_BUS_FMT_SBGGR8_1X8,
 357                .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
 358                .width = 8,
 359        }, {
 360                .code = MEDIA_BUS_FMT_SGBRG8_1X8,
 361                .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
 362                .width = 8,
 363        }, {
 364                .code = MEDIA_BUS_FMT_SGRBG8_1X8,
 365                .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
 366                .width = 8,
 367        }, {
 368                .code = MEDIA_BUS_FMT_SRGGB8_1X8,
 369                .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
 370                .width = 8,
 371        }, {
 372                .code = MEDIA_BUS_FMT_Y8_1X8,
 373                .data_type = MIPI_CSI2_DATA_TYPE_RAW8,
 374                .width = 8,
 375        }, {
 376                .code = MEDIA_BUS_FMT_SBGGR10_1X10,
 377                .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
 378                .width = 10,
 379        }, {
 380                .code = MEDIA_BUS_FMT_SGBRG10_1X10,
 381                .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
 382                .width = 10,
 383        }, {
 384                .code = MEDIA_BUS_FMT_SGRBG10_1X10,
 385                .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
 386                .width = 10,
 387        }, {
 388                .code = MEDIA_BUS_FMT_SRGGB10_1X10,
 389                .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
 390                .width = 10,
 391        }, {
 392                .code = MEDIA_BUS_FMT_Y10_1X10,
 393                .data_type = MIPI_CSI2_DATA_TYPE_RAW10,
 394                .width = 10,
 395        }, {
 396                .code = MEDIA_BUS_FMT_SBGGR12_1X12,
 397                .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
 398                .width = 12,
 399        }, {
 400                .code = MEDIA_BUS_FMT_SGBRG12_1X12,
 401                .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
 402                .width = 12,
 403        }, {
 404                .code = MEDIA_BUS_FMT_SGRBG12_1X12,
 405                .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
 406                .width = 12,
 407        }, {
 408                .code = MEDIA_BUS_FMT_SRGGB12_1X12,
 409                .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
 410                .width = 12,
 411        }, {
 412                .code = MEDIA_BUS_FMT_Y12_1X12,
 413                .data_type = MIPI_CSI2_DATA_TYPE_RAW12,
 414                .width = 12,
 415        }, {
 416                .code = MEDIA_BUS_FMT_SBGGR14_1X14,
 417                .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
 418                .width = 14,
 419        }, {
 420                .code = MEDIA_BUS_FMT_SGBRG14_1X14,
 421                .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
 422                .width = 14,
 423        }, {
 424                .code = MEDIA_BUS_FMT_SGRBG14_1X14,
 425                .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
 426                .width = 14,
 427        }, {
 428                .code = MEDIA_BUS_FMT_SRGGB14_1X14,
 429                .data_type = MIPI_CSI2_DATA_TYPE_RAW14,
 430                .width = 14,
 431        }
 432};
 433
 434static const struct csis_pix_format *find_csis_format(u32 code)
 435{
 436        unsigned int i;
 437
 438        for (i = 0; i < ARRAY_SIZE(mipi_csis_formats); i++)
 439                if (code == mipi_csis_formats[i].code)
 440                        return &mipi_csis_formats[i];
 441        return NULL;
 442}
 443
 444/* -----------------------------------------------------------------------------
 445 * Hardware configuration
 446 */
 447
 448static inline u32 mipi_csis_read(struct csi_state *state, u32 reg)
 449{
 450        return readl(state->regs + reg);
 451}
 452
 453static inline void mipi_csis_write(struct csi_state *state, u32 reg, u32 val)
 454{
 455        writel(val, state->regs + reg);
 456}
 457
 458static void mipi_csis_enable_interrupts(struct csi_state *state, bool on)
 459{
 460        mipi_csis_write(state, MIPI_CSIS_INT_MSK, on ? 0xffffffff : 0);
 461        mipi_csis_write(state, MIPI_CSIS_DBG_INTR_MSK, on ? 0xffffffff : 0);
 462}
 463
 464static void mipi_csis_sw_reset(struct csi_state *state)
 465{
 466        u32 val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 467
 468        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
 469                        val | MIPI_CSIS_CMN_CTRL_RESET);
 470        usleep_range(10, 20);
 471}
 472
 473static void mipi_csis_system_enable(struct csi_state *state, int on)
 474{
 475        u32 val, mask;
 476
 477        val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 478        if (on)
 479                val |= MIPI_CSIS_CMN_CTRL_ENABLE;
 480        else
 481                val &= ~MIPI_CSIS_CMN_CTRL_ENABLE;
 482        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
 483
 484        val = mipi_csis_read(state, MIPI_CSIS_DPHY_CMN_CTRL);
 485        val &= ~MIPI_CSIS_DPHY_CMN_CTRL_ENABLE;
 486        if (on) {
 487                mask = (1 << (state->bus.num_data_lanes + 1)) - 1;
 488                val |= (mask & MIPI_CSIS_DPHY_CMN_CTRL_ENABLE);
 489        }
 490        mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL, val);
 491}
 492
 493/* Called with the state.lock mutex held */
 494static void __mipi_csis_set_format(struct csi_state *state)
 495{
 496        struct v4l2_mbus_framefmt *mf = &state->format_mbus;
 497        u32 val;
 498
 499        /* Color format */
 500        val = mipi_csis_read(state, MIPI_CSIS_ISP_CONFIG_CH(0));
 501        val &= ~(MIPI_CSIS_ISPCFG_ALIGN_32BIT | MIPI_CSIS_ISPCFG_FMT_MASK);
 502        val |= MIPI_CSIS_ISPCFG_FMT(state->csis_fmt->data_type);
 503        mipi_csis_write(state, MIPI_CSIS_ISP_CONFIG_CH(0), val);
 504
 505        /* Pixel resolution */
 506        val = mf->width | (mf->height << 16);
 507        mipi_csis_write(state, MIPI_CSIS_ISP_RESOL_CH(0), val);
 508}
 509
 510static int mipi_csis_calculate_params(struct csi_state *state)
 511{
 512        s64 link_freq;
 513        u32 lane_rate;
 514
 515        /* Calculate the line rate from the pixel rate. */
 516        link_freq = v4l2_get_link_freq(state->src_sd->ctrl_handler,
 517                                       state->csis_fmt->width,
 518                                       state->bus.num_data_lanes * 2);
 519        if (link_freq < 0) {
 520                dev_err(state->dev, "Unable to obtain link frequency: %d\n",
 521                        (int)link_freq);
 522                return link_freq;
 523        }
 524
 525        lane_rate = link_freq * 2;
 526
 527        if (lane_rate < 80000000 || lane_rate > 1500000000) {
 528                dev_dbg(state->dev, "Out-of-bound lane rate %u\n", lane_rate);
 529                return -EINVAL;
 530        }
 531
 532        /*
 533         * The HSSETTLE counter value is document in a table, but can also
 534         * easily be calculated. Hardcode the CLKSETTLE value to 0 for now
 535         * (which is documented as corresponding to CSI-2 v0.87 to v1.00) until
 536         * we figure out how to compute it correctly.
 537         */
 538        state->hs_settle = (lane_rate - 5000000) / 45000000;
 539        state->clk_settle = 0;
 540
 541        dev_dbg(state->dev, "lane rate %u, Tclk_settle %u, Ths_settle %u\n",
 542                lane_rate, state->clk_settle, state->hs_settle);
 543
 544        return 0;
 545}
 546
 547static void mipi_csis_set_params(struct csi_state *state)
 548{
 549        int lanes = state->bus.num_data_lanes;
 550        u32 val;
 551
 552        val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 553        val &= ~MIPI_CSIS_CMN_CTRL_LANE_NR_MASK;
 554        val |= (lanes - 1) << MIPI_CSIS_CMN_CTRL_LANE_NR_OFFSET;
 555        if (state->info->version == MIPI_CSIS_V3_3)
 556                val |= MIPI_CSIS_CMN_CTRL_INTER_MODE;
 557        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL, val);
 558
 559        __mipi_csis_set_format(state);
 560
 561        mipi_csis_write(state, MIPI_CSIS_DPHY_CMN_CTRL,
 562                        MIPI_CSIS_DPHY_CMN_CTRL_HSSETTLE(state->hs_settle) |
 563                        MIPI_CSIS_DPHY_CMN_CTRL_CLKSETTLE(state->clk_settle));
 564
 565        val = (0 << MIPI_CSIS_ISP_SYNC_HSYNC_LINTV_OFFSET)
 566            | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_SINTV_OFFSET)
 567            | (0 << MIPI_CSIS_ISP_SYNC_VSYNC_EINTV_OFFSET);
 568        mipi_csis_write(state, MIPI_CSIS_ISP_SYNC_CH(0), val);
 569
 570        val = mipi_csis_read(state, MIPI_CSIS_CLK_CTRL);
 571        val |= MIPI_CSIS_CLK_CTRL_WCLK_SRC;
 572        val |= MIPI_CSIS_CLK_CTRL_CLKGATE_TRAIL_CH0(15);
 573        val &= ~MIPI_CSIS_CLK_CTRL_CLKGATE_EN_MSK;
 574        mipi_csis_write(state, MIPI_CSIS_CLK_CTRL, val);
 575
 576        mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_L,
 577                        MIPI_CSIS_DPHY_BCTRL_L_BIAS_REF_VOLT_715MV |
 578                        MIPI_CSIS_DPHY_BCTRL_L_BGR_CHOPPER_FREQ_3MHZ |
 579                        MIPI_CSIS_DPHY_BCTRL_L_REG_12P_LVL_CTL_1_2V |
 580                        MIPI_CSIS_DPHY_BCTRL_L_LP_RX_HYS_LVL_80MV |
 581                        MIPI_CSIS_DPHY_BCTRL_L_LP_RX_VREF_LVL_715MV |
 582                        MIPI_CSIS_DPHY_BCTRL_L_LP_CD_HYS_60MV |
 583                        MIPI_CSIS_DPHY_BCTRL_L_B_DPHYCTRL(20000000));
 584        mipi_csis_write(state, MIPI_CSIS_DPHY_BCTRL_H, 0);
 585
 586        /* Update the shadow register. */
 587        val = mipi_csis_read(state, MIPI_CSIS_CMN_CTRL);
 588        mipi_csis_write(state, MIPI_CSIS_CMN_CTRL,
 589                        val | MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW |
 590                        MIPI_CSIS_CMN_CTRL_UPDATE_SHADOW_CTRL);
 591}
 592
 593static int mipi_csis_clk_enable(struct csi_state *state)
 594{
 595        return clk_bulk_prepare_enable(state->info->num_clocks, state->clks);
 596}
 597
 598static void mipi_csis_clk_disable(struct csi_state *state)
 599{
 600        clk_bulk_disable_unprepare(state->info->num_clocks, state->clks);
 601}
 602
 603static int mipi_csis_clk_get(struct csi_state *state)
 604{
 605        unsigned int i;
 606        int ret;
 607
 608        state->clks = devm_kcalloc(state->dev, state->info->num_clocks,
 609                                   sizeof(*state->clks), GFP_KERNEL);
 610
 611        if (!state->clks)
 612                return -ENOMEM;
 613
 614        for (i = 0; i < state->info->num_clocks; i++)
 615                state->clks[i].id = mipi_csis_clk_id[i];
 616
 617        ret = devm_clk_bulk_get(state->dev, state->info->num_clocks,
 618                                state->clks);
 619        if (ret < 0)
 620                return ret;
 621
 622        /* Set clock rate */
 623        ret = clk_set_rate(state->clks[MIPI_CSIS_CLK_WRAP].clk,
 624                           state->clk_frequency);
 625        if (ret < 0)
 626                dev_err(state->dev, "set rate=%d failed: %d\n",
 627                        state->clk_frequency, ret);
 628
 629        return ret;
 630}
 631
 632static void mipi_csis_start_stream(struct csi_state *state)
 633{
 634        mipi_csis_sw_reset(state);
 635        mipi_csis_set_params(state);
 636        mipi_csis_system_enable(state, true);
 637        mipi_csis_enable_interrupts(state, true);
 638}
 639
 640static void mipi_csis_stop_stream(struct csi_state *state)
 641{
 642        mipi_csis_enable_interrupts(state, false);
 643        mipi_csis_system_enable(state, false);
 644}
 645
 646static irqreturn_t mipi_csis_irq_handler(int irq, void *dev_id)
 647{
 648        struct csi_state *state = dev_id;
 649        unsigned long flags;
 650        unsigned int i;
 651        u32 status;
 652        u32 dbg_status;
 653
 654        status = mipi_csis_read(state, MIPI_CSIS_INT_SRC);
 655        dbg_status = mipi_csis_read(state, MIPI_CSIS_DBG_INTR_SRC);
 656
 657        spin_lock_irqsave(&state->slock, flags);
 658
 659        /* Update the event/error counters */
 660        if ((status & MIPI_CSIS_INT_SRC_ERRORS) || state->debug) {
 661                for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++) {
 662                        struct mipi_csis_event *event = &state->events[i];
 663
 664                        if ((!event->debug && (status & event->mask)) ||
 665                            (event->debug && (dbg_status & event->mask)))
 666                                event->counter++;
 667                }
 668        }
 669        spin_unlock_irqrestore(&state->slock, flags);
 670
 671        mipi_csis_write(state, MIPI_CSIS_INT_SRC, status);
 672        mipi_csis_write(state, MIPI_CSIS_DBG_INTR_SRC, dbg_status);
 673
 674        return IRQ_HANDLED;
 675}
 676
 677/* -----------------------------------------------------------------------------
 678 * PHY regulator and reset
 679 */
 680
 681static int mipi_csis_phy_enable(struct csi_state *state)
 682{
 683        if (state->info->version != MIPI_CSIS_V3_3)
 684                return 0;
 685
 686        return regulator_enable(state->mipi_phy_regulator);
 687}
 688
 689static int mipi_csis_phy_disable(struct csi_state *state)
 690{
 691        if (state->info->version != MIPI_CSIS_V3_3)
 692                return 0;
 693
 694        return regulator_disable(state->mipi_phy_regulator);
 695}
 696
 697static void mipi_csis_phy_reset(struct csi_state *state)
 698{
 699        if (state->info->version != MIPI_CSIS_V3_3)
 700                return;
 701
 702        reset_control_assert(state->mrst);
 703        msleep(20);
 704        reset_control_deassert(state->mrst);
 705}
 706
 707static int mipi_csis_phy_init(struct csi_state *state)
 708{
 709        if (state->info->version != MIPI_CSIS_V3_3)
 710                return 0;
 711
 712        /* Get MIPI PHY reset and regulator. */
 713        state->mrst = devm_reset_control_get_exclusive(state->dev, NULL);
 714        if (IS_ERR(state->mrst))
 715                return PTR_ERR(state->mrst);
 716
 717        state->mipi_phy_regulator = devm_regulator_get(state->dev, "phy");
 718        if (IS_ERR(state->mipi_phy_regulator))
 719                return PTR_ERR(state->mipi_phy_regulator);
 720
 721        return regulator_set_voltage(state->mipi_phy_regulator, 1000000,
 722                                     1000000);
 723}
 724
 725/* -----------------------------------------------------------------------------
 726 * Debug
 727 */
 728
 729static void mipi_csis_clear_counters(struct csi_state *state)
 730{
 731        unsigned long flags;
 732        unsigned int i;
 733
 734        spin_lock_irqsave(&state->slock, flags);
 735        for (i = 0; i < MIPI_CSIS_NUM_EVENTS; i++)
 736                state->events[i].counter = 0;
 737        spin_unlock_irqrestore(&state->slock, flags);
 738}
 739
 740static void mipi_csis_log_counters(struct csi_state *state, bool non_errors)
 741{
 742        unsigned int num_events = non_errors ? MIPI_CSIS_NUM_EVENTS
 743                                : MIPI_CSIS_NUM_EVENTS - 8;
 744        unsigned long flags;
 745        unsigned int i;
 746
 747        spin_lock_irqsave(&state->slock, flags);
 748
 749        for (i = 0; i < num_events; ++i) {
 750                if (state->events[i].counter > 0 || state->debug)
 751                        dev_info(state->dev, "%s events: %d\n",
 752                                 state->events[i].name,
 753                                 state->events[i].counter);
 754        }
 755        spin_unlock_irqrestore(&state->slock, flags);
 756}
 757
 758static int mipi_csis_dump_regs(struct csi_state *state)
 759{
 760        static const struct {
 761                u32 offset;
 762                const char * const name;
 763        } registers[] = {
 764                { MIPI_CSIS_CMN_CTRL, "CMN_CTRL" },
 765                { MIPI_CSIS_CLK_CTRL, "CLK_CTRL" },
 766                { MIPI_CSIS_INT_MSK, "INT_MSK" },
 767                { MIPI_CSIS_DPHY_STATUS, "DPHY_STATUS" },
 768                { MIPI_CSIS_DPHY_CMN_CTRL, "DPHY_CMN_CTRL" },
 769                { MIPI_CSIS_DPHY_SCTRL_L, "DPHY_SCTRL_L" },
 770                { MIPI_CSIS_DPHY_SCTRL_H, "DPHY_SCTRL_H" },
 771                { MIPI_CSIS_ISP_CONFIG_CH(0), "ISP_CONFIG_CH0" },
 772                { MIPI_CSIS_ISP_RESOL_CH(0), "ISP_RESOL_CH0" },
 773                { MIPI_CSIS_SDW_CONFIG_CH(0), "SDW_CONFIG_CH0" },
 774                { MIPI_CSIS_SDW_RESOL_CH(0), "SDW_RESOL_CH0" },
 775                { MIPI_CSIS_DBG_CTRL, "DBG_CTRL" },
 776        };
 777
 778        unsigned int i;
 779        u32 cfg;
 780
 781        dev_info(state->dev, "--- REGISTERS ---\n");
 782
 783        for (i = 0; i < ARRAY_SIZE(registers); i++) {
 784                cfg = mipi_csis_read(state, registers[i].offset);
 785                dev_info(state->dev, "%14s: 0x%08x\n", registers[i].name, cfg);
 786        }
 787
 788        return 0;
 789}
 790
 791static int mipi_csis_dump_regs_show(struct seq_file *m, void *private)
 792{
 793        struct csi_state *state = m->private;
 794
 795        return mipi_csis_dump_regs(state);
 796}
 797DEFINE_SHOW_ATTRIBUTE(mipi_csis_dump_regs);
 798
 799static void mipi_csis_debugfs_init(struct csi_state *state)
 800{
 801        state->debugfs_root = debugfs_create_dir(dev_name(state->dev), NULL);
 802
 803        debugfs_create_bool("debug_enable", 0600, state->debugfs_root,
 804                            &state->debug);
 805        debugfs_create_file("dump_regs", 0600, state->debugfs_root, state,
 806                            &mipi_csis_dump_regs_fops);
 807}
 808
 809static void mipi_csis_debugfs_exit(struct csi_state *state)
 810{
 811        debugfs_remove_recursive(state->debugfs_root);
 812}
 813
 814/* -----------------------------------------------------------------------------
 815 * V4L2 subdev operations
 816 */
 817
 818static struct csi_state *mipi_sd_to_csis_state(struct v4l2_subdev *sdev)
 819{
 820        return container_of(sdev, struct csi_state, sd);
 821}
 822
 823static int mipi_csis_s_stream(struct v4l2_subdev *sd, int enable)
 824{
 825        struct csi_state *state = mipi_sd_to_csis_state(sd);
 826        int ret;
 827
 828        if (enable) {
 829                ret = mipi_csis_calculate_params(state);
 830                if (ret < 0)
 831                        return ret;
 832
 833                mipi_csis_clear_counters(state);
 834
 835                ret = pm_runtime_resume_and_get(state->dev);
 836                if (ret < 0)
 837                        return ret;
 838
 839                ret = v4l2_subdev_call(state->src_sd, core, s_power, 1);
 840                if (ret < 0 && ret != -ENOIOCTLCMD)
 841                        goto done;
 842        }
 843
 844        mutex_lock(&state->lock);
 845
 846        if (enable) {
 847                if (state->state & ST_SUSPENDED) {
 848                        ret = -EBUSY;
 849                        goto unlock;
 850                }
 851
 852                mipi_csis_start_stream(state);
 853                ret = v4l2_subdev_call(state->src_sd, video, s_stream, 1);
 854                if (ret < 0)
 855                        goto unlock;
 856
 857                mipi_csis_log_counters(state, true);
 858
 859                state->state |= ST_STREAMING;
 860        } else {
 861                v4l2_subdev_call(state->src_sd, video, s_stream, 0);
 862                ret = v4l2_subdev_call(state->src_sd, core, s_power, 0);
 863                if (ret == -ENOIOCTLCMD)
 864                        ret = 0;
 865                mipi_csis_stop_stream(state);
 866                state->state &= ~ST_STREAMING;
 867                if (state->debug)
 868                        mipi_csis_log_counters(state, true);
 869        }
 870
 871unlock:
 872        mutex_unlock(&state->lock);
 873
 874done:
 875        if (!enable || ret < 0)
 876                pm_runtime_put(state->dev);
 877
 878        return ret;
 879}
 880
 881static struct v4l2_mbus_framefmt *
 882mipi_csis_get_format(struct csi_state *state,
 883                     struct v4l2_subdev_state *sd_state,
 884                     enum v4l2_subdev_format_whence which,
 885                     unsigned int pad)
 886{
 887        if (which == V4L2_SUBDEV_FORMAT_TRY)
 888                return v4l2_subdev_get_try_format(&state->sd, sd_state, pad);
 889
 890        return &state->format_mbus;
 891}
 892
 893static int mipi_csis_init_cfg(struct v4l2_subdev *sd,
 894                              struct v4l2_subdev_state *sd_state)
 895{
 896        struct csi_state *state = mipi_sd_to_csis_state(sd);
 897        struct v4l2_mbus_framefmt *fmt_sink;
 898        struct v4l2_mbus_framefmt *fmt_source;
 899        enum v4l2_subdev_format_whence which;
 900
 901        which = sd_state ? V4L2_SUBDEV_FORMAT_TRY : V4L2_SUBDEV_FORMAT_ACTIVE;
 902        fmt_sink = mipi_csis_get_format(state, sd_state, which, CSIS_PAD_SINK);
 903
 904        fmt_sink->code = MEDIA_BUS_FMT_UYVY8_1X16;
 905        fmt_sink->width = MIPI_CSIS_DEF_PIX_WIDTH;
 906        fmt_sink->height = MIPI_CSIS_DEF_PIX_HEIGHT;
 907        fmt_sink->field = V4L2_FIELD_NONE;
 908
 909        fmt_sink->colorspace = V4L2_COLORSPACE_SMPTE170M;
 910        fmt_sink->xfer_func = V4L2_MAP_XFER_FUNC_DEFAULT(fmt_sink->colorspace);
 911        fmt_sink->ycbcr_enc = V4L2_MAP_YCBCR_ENC_DEFAULT(fmt_sink->colorspace);
 912        fmt_sink->quantization =
 913                V4L2_MAP_QUANTIZATION_DEFAULT(false, fmt_sink->colorspace,
 914                                              fmt_sink->ycbcr_enc);
 915
 916        /*
 917         * When called from mipi_csis_subdev_init() to initialize the active
 918         * configuration, cfg is NULL, which indicates there's no source pad
 919         * configuration to set.
 920         */
 921        if (!sd_state)
 922                return 0;
 923
 924        fmt_source = mipi_csis_get_format(state, sd_state, which,
 925                                          CSIS_PAD_SOURCE);
 926        *fmt_source = *fmt_sink;
 927
 928        return 0;
 929}
 930
 931static int mipi_csis_get_fmt(struct v4l2_subdev *sd,
 932                             struct v4l2_subdev_state *sd_state,
 933                             struct v4l2_subdev_format *sdformat)
 934{
 935        struct csi_state *state = mipi_sd_to_csis_state(sd);
 936        struct v4l2_mbus_framefmt *fmt;
 937
 938        fmt = mipi_csis_get_format(state, sd_state, sdformat->which,
 939                                   sdformat->pad);
 940
 941        mutex_lock(&state->lock);
 942        sdformat->format = *fmt;
 943        mutex_unlock(&state->lock);
 944
 945        return 0;
 946}
 947
 948static int mipi_csis_enum_mbus_code(struct v4l2_subdev *sd,
 949                                    struct v4l2_subdev_state *sd_state,
 950                                    struct v4l2_subdev_mbus_code_enum *code)
 951{
 952        struct csi_state *state = mipi_sd_to_csis_state(sd);
 953
 954        /*
 955         * The CSIS can't transcode in any way, the source format is identical
 956         * to the sink format.
 957         */
 958        if (code->pad == CSIS_PAD_SOURCE) {
 959                struct v4l2_mbus_framefmt *fmt;
 960
 961                if (code->index > 0)
 962                        return -EINVAL;
 963
 964                fmt = mipi_csis_get_format(state, sd_state, code->which,
 965                                           code->pad);
 966                code->code = fmt->code;
 967                return 0;
 968        }
 969
 970        if (code->pad != CSIS_PAD_SINK)
 971                return -EINVAL;
 972
 973        if (code->index >= ARRAY_SIZE(mipi_csis_formats))
 974                return -EINVAL;
 975
 976        code->code = mipi_csis_formats[code->index].code;
 977
 978        return 0;
 979}
 980
 981static int mipi_csis_set_fmt(struct v4l2_subdev *sd,
 982                             struct v4l2_subdev_state *sd_state,
 983                             struct v4l2_subdev_format *sdformat)
 984{
 985        struct csi_state *state = mipi_sd_to_csis_state(sd);
 986        struct csis_pix_format const *csis_fmt;
 987        struct v4l2_mbus_framefmt *fmt;
 988        unsigned int align;
 989
 990        /*
 991         * The CSIS can't transcode in any way, the source format can't be
 992         * modified.
 993         */
 994        if (sdformat->pad == CSIS_PAD_SOURCE)
 995                return mipi_csis_get_fmt(sd, sd_state, sdformat);
 996
 997        if (sdformat->pad != CSIS_PAD_SINK)
 998                return -EINVAL;
 999
1000        /*
1001         * Validate the media bus code and clamp and align the size.
1002         *
1003         * The total number of bits per line must be a multiple of 8. We thus
1004         * need to align the width for formats that are not multiples of 8
1005         * bits.
1006         */
1007        csis_fmt = find_csis_format(sdformat->format.code);
1008        if (!csis_fmt)
1009                csis_fmt = &mipi_csis_formats[0];
1010
1011        switch (csis_fmt->width % 8) {
1012        case 0:
1013                align = 0;
1014                break;
1015        case 4:
1016                align = 1;
1017                break;
1018        case 2:
1019        case 6:
1020                align = 2;
1021                break;
1022        case 1:
1023        case 3:
1024        case 5:
1025        case 7:
1026                align = 3;
1027                break;
1028        }
1029
1030        v4l_bound_align_image(&sdformat->format.width, 1,
1031                              CSIS_MAX_PIX_WIDTH, align,
1032                              &sdformat->format.height, 1,
1033                              CSIS_MAX_PIX_HEIGHT, 0, 0);
1034
1035        fmt = mipi_csis_get_format(state, sd_state, sdformat->which,
1036                                   sdformat->pad);
1037
1038        mutex_lock(&state->lock);
1039
1040        fmt->code = csis_fmt->code;
1041        fmt->width = sdformat->format.width;
1042        fmt->height = sdformat->format.height;
1043
1044        sdformat->format = *fmt;
1045
1046        /* Propagate the format from sink to source. */
1047        fmt = mipi_csis_get_format(state, sd_state, sdformat->which,
1048                                   CSIS_PAD_SOURCE);
1049        *fmt = sdformat->format;
1050
1051        /* Store the CSIS format descriptor for active formats. */
1052        if (sdformat->which == V4L2_SUBDEV_FORMAT_ACTIVE)
1053                state->csis_fmt = csis_fmt;
1054
1055        mutex_unlock(&state->lock);
1056
1057        return 0;
1058}
1059
1060static int mipi_csis_log_status(struct v4l2_subdev *sd)
1061{
1062        struct csi_state *state = mipi_sd_to_csis_state(sd);
1063
1064        mutex_lock(&state->lock);
1065        mipi_csis_log_counters(state, true);
1066        if (state->debug && (state->state & ST_POWERED))
1067                mipi_csis_dump_regs(state);
1068        mutex_unlock(&state->lock);
1069
1070        return 0;
1071}
1072
1073static const struct v4l2_subdev_core_ops mipi_csis_core_ops = {
1074        .log_status     = mipi_csis_log_status,
1075};
1076
1077static const struct v4l2_subdev_video_ops mipi_csis_video_ops = {
1078        .s_stream       = mipi_csis_s_stream,
1079};
1080
1081static const struct v4l2_subdev_pad_ops mipi_csis_pad_ops = {
1082        .init_cfg               = mipi_csis_init_cfg,
1083        .enum_mbus_code         = mipi_csis_enum_mbus_code,
1084        .get_fmt                = mipi_csis_get_fmt,
1085        .set_fmt                = mipi_csis_set_fmt,
1086};
1087
1088static const struct v4l2_subdev_ops mipi_csis_subdev_ops = {
1089        .core   = &mipi_csis_core_ops,
1090        .video  = &mipi_csis_video_ops,
1091        .pad    = &mipi_csis_pad_ops,
1092};
1093
1094/* -----------------------------------------------------------------------------
1095 * Media entity operations
1096 */
1097
1098static int mipi_csis_link_setup(struct media_entity *entity,
1099                                const struct media_pad *local_pad,
1100                                const struct media_pad *remote_pad, u32 flags)
1101{
1102        struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
1103        struct csi_state *state = mipi_sd_to_csis_state(sd);
1104        struct v4l2_subdev *remote_sd;
1105
1106        dev_dbg(state->dev, "link setup %s -> %s", remote_pad->entity->name,
1107                local_pad->entity->name);
1108
1109        /* We only care about the link to the source. */
1110        if (!(local_pad->flags & MEDIA_PAD_FL_SINK))
1111                return 0;
1112
1113        remote_sd = media_entity_to_v4l2_subdev(remote_pad->entity);
1114
1115        if (flags & MEDIA_LNK_FL_ENABLED) {
1116                if (state->src_sd)
1117                        return -EBUSY;
1118
1119                state->src_sd = remote_sd;
1120        } else {
1121                state->src_sd = NULL;
1122        }
1123
1124        return 0;
1125}
1126
1127static const struct media_entity_operations mipi_csis_entity_ops = {
1128        .link_setup     = mipi_csis_link_setup,
1129        .link_validate  = v4l2_subdev_link_validate,
1130        .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1131};
1132
1133/* -----------------------------------------------------------------------------
1134 * Async subdev notifier
1135 */
1136
1137static struct csi_state *
1138mipi_notifier_to_csis_state(struct v4l2_async_notifier *n)
1139{
1140        return container_of(n, struct csi_state, notifier);
1141}
1142
1143static int mipi_csis_notify_bound(struct v4l2_async_notifier *notifier,
1144                                  struct v4l2_subdev *sd,
1145                                  struct v4l2_async_subdev *asd)
1146{
1147        struct csi_state *state = mipi_notifier_to_csis_state(notifier);
1148        struct media_pad *sink = &state->sd.entity.pads[CSIS_PAD_SINK];
1149
1150        return v4l2_create_fwnode_links_to_pad(sd, sink, 0);
1151}
1152
1153static const struct v4l2_async_notifier_operations mipi_csis_notify_ops = {
1154        .bound = mipi_csis_notify_bound,
1155};
1156
1157static int mipi_csis_async_register(struct csi_state *state)
1158{
1159        struct v4l2_fwnode_endpoint vep = {
1160                .bus_type = V4L2_MBUS_CSI2_DPHY,
1161        };
1162        struct v4l2_async_subdev *asd;
1163        struct fwnode_handle *ep;
1164        unsigned int i;
1165        int ret;
1166
1167        v4l2_async_notifier_init(&state->notifier);
1168
1169        ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(state->dev), 0, 0,
1170                                             FWNODE_GRAPH_ENDPOINT_NEXT);
1171        if (!ep)
1172                return -ENOTCONN;
1173
1174        ret = v4l2_fwnode_endpoint_parse(ep, &vep);
1175        if (ret)
1176                goto err_parse;
1177
1178        for (i = 0; i < vep.bus.mipi_csi2.num_data_lanes; ++i) {
1179                if (vep.bus.mipi_csi2.data_lanes[i] != i + 1) {
1180                        dev_err(state->dev,
1181                                "data lanes reordering is not supported");
1182                        ret = -EINVAL;
1183                        goto err_parse;
1184                }
1185        }
1186
1187        state->bus = vep.bus.mipi_csi2;
1188
1189        dev_dbg(state->dev, "data lanes: %d\n", state->bus.num_data_lanes);
1190        dev_dbg(state->dev, "flags: 0x%08x\n", state->bus.flags);
1191
1192        asd = v4l2_async_notifier_add_fwnode_remote_subdev(
1193                &state->notifier, ep, struct v4l2_async_subdev);
1194        if (IS_ERR(asd)) {
1195                ret = PTR_ERR(asd);
1196                goto err_parse;
1197        }
1198
1199        fwnode_handle_put(ep);
1200
1201        state->notifier.ops = &mipi_csis_notify_ops;
1202
1203        ret = v4l2_async_subdev_notifier_register(&state->sd, &state->notifier);
1204        if (ret)
1205                return ret;
1206
1207        return v4l2_async_register_subdev(&state->sd);
1208
1209err_parse:
1210        fwnode_handle_put(ep);
1211
1212        return ret;
1213}
1214
1215/* -----------------------------------------------------------------------------
1216 * Suspend/resume
1217 */
1218
1219static int mipi_csis_pm_suspend(struct device *dev, bool runtime)
1220{
1221        struct v4l2_subdev *sd = dev_get_drvdata(dev);
1222        struct csi_state *state = mipi_sd_to_csis_state(sd);
1223        int ret = 0;
1224
1225        mutex_lock(&state->lock);
1226        if (state->state & ST_POWERED) {
1227                mipi_csis_stop_stream(state);
1228                ret = mipi_csis_phy_disable(state);
1229                if (ret)
1230                        goto unlock;
1231                mipi_csis_clk_disable(state);
1232                state->state &= ~ST_POWERED;
1233                if (!runtime)
1234                        state->state |= ST_SUSPENDED;
1235        }
1236
1237unlock:
1238        mutex_unlock(&state->lock);
1239
1240        return ret ? -EAGAIN : 0;
1241}
1242
1243static int mipi_csis_pm_resume(struct device *dev, bool runtime)
1244{
1245        struct v4l2_subdev *sd = dev_get_drvdata(dev);
1246        struct csi_state *state = mipi_sd_to_csis_state(sd);
1247        int ret = 0;
1248
1249        mutex_lock(&state->lock);
1250        if (!runtime && !(state->state & ST_SUSPENDED))
1251                goto unlock;
1252
1253        if (!(state->state & ST_POWERED)) {
1254                ret = mipi_csis_phy_enable(state);
1255                if (ret)
1256                        goto unlock;
1257
1258                state->state |= ST_POWERED;
1259                mipi_csis_clk_enable(state);
1260        }
1261        if (state->state & ST_STREAMING)
1262                mipi_csis_start_stream(state);
1263
1264        state->state &= ~ST_SUSPENDED;
1265
1266unlock:
1267        mutex_unlock(&state->lock);
1268
1269        return ret ? -EAGAIN : 0;
1270}
1271
1272static int __maybe_unused mipi_csis_suspend(struct device *dev)
1273{
1274        return mipi_csis_pm_suspend(dev, false);
1275}
1276
1277static int __maybe_unused mipi_csis_resume(struct device *dev)
1278{
1279        return mipi_csis_pm_resume(dev, false);
1280}
1281
1282static int __maybe_unused mipi_csis_runtime_suspend(struct device *dev)
1283{
1284        return mipi_csis_pm_suspend(dev, true);
1285}
1286
1287static int __maybe_unused mipi_csis_runtime_resume(struct device *dev)
1288{
1289        return mipi_csis_pm_resume(dev, true);
1290}
1291
1292static const struct dev_pm_ops mipi_csis_pm_ops = {
1293        SET_RUNTIME_PM_OPS(mipi_csis_runtime_suspend, mipi_csis_runtime_resume,
1294                           NULL)
1295        SET_SYSTEM_SLEEP_PM_OPS(mipi_csis_suspend, mipi_csis_resume)
1296};
1297
1298/* -----------------------------------------------------------------------------
1299 * Probe/remove & platform driver
1300 */
1301
1302static int mipi_csis_subdev_init(struct csi_state *state)
1303{
1304        struct v4l2_subdev *sd = &state->sd;
1305
1306        v4l2_subdev_init(sd, &mipi_csis_subdev_ops);
1307        sd->owner = THIS_MODULE;
1308        snprintf(sd->name, sizeof(sd->name), "%s.%d",
1309                 CSIS_SUBDEV_NAME, state->index);
1310
1311        sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1312        sd->ctrl_handler = NULL;
1313
1314        sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1315        sd->entity.ops = &mipi_csis_entity_ops;
1316
1317        sd->dev = state->dev;
1318
1319        state->csis_fmt = &mipi_csis_formats[0];
1320        mipi_csis_init_cfg(sd, NULL);
1321
1322        state->pads[CSIS_PAD_SINK].flags = MEDIA_PAD_FL_SINK
1323                                         | MEDIA_PAD_FL_MUST_CONNECT;
1324        state->pads[CSIS_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE
1325                                           | MEDIA_PAD_FL_MUST_CONNECT;
1326        return media_entity_pads_init(&sd->entity, CSIS_PADS_NUM,
1327                                      state->pads);
1328}
1329
1330static int mipi_csis_parse_dt(struct csi_state *state)
1331{
1332        struct device_node *node = state->dev->of_node;
1333
1334        if (of_property_read_u32(node, "clock-frequency",
1335                                 &state->clk_frequency))
1336                state->clk_frequency = DEFAULT_SCLK_CSIS_FREQ;
1337
1338        return 0;
1339}
1340
1341static int mipi_csis_probe(struct platform_device *pdev)
1342{
1343        struct device *dev = &pdev->dev;
1344        struct csi_state *state;
1345        int irq;
1346        int ret;
1347
1348        state = devm_kzalloc(dev, sizeof(*state), GFP_KERNEL);
1349        if (!state)
1350                return -ENOMEM;
1351
1352        mutex_init(&state->lock);
1353        spin_lock_init(&state->slock);
1354
1355        state->dev = dev;
1356        state->info = of_device_get_match_data(dev);
1357
1358        memcpy(state->events, mipi_csis_events, sizeof(state->events));
1359
1360        /* Parse DT properties. */
1361        ret = mipi_csis_parse_dt(state);
1362        if (ret < 0) {
1363                dev_err(dev, "Failed to parse device tree: %d\n", ret);
1364                return ret;
1365        }
1366
1367        /* Acquire resources. */
1368        state->regs = devm_platform_ioremap_resource(pdev, 0);
1369        if (IS_ERR(state->regs))
1370                return PTR_ERR(state->regs);
1371
1372        irq = platform_get_irq(pdev, 0);
1373        if (irq < 0)
1374                return irq;
1375
1376        ret = mipi_csis_phy_init(state);
1377        if (ret < 0)
1378                return ret;
1379
1380        ret = mipi_csis_clk_get(state);
1381        if (ret < 0)
1382                return ret;
1383
1384        /* Reset PHY and enable the clocks. */
1385        mipi_csis_phy_reset(state);
1386
1387        ret = mipi_csis_clk_enable(state);
1388        if (ret < 0) {
1389                dev_err(state->dev, "failed to enable clocks: %d\n", ret);
1390                return ret;
1391        }
1392
1393        /* Now that the hardware is initialized, request the interrupt. */
1394        ret = devm_request_irq(dev, irq, mipi_csis_irq_handler, 0,
1395                               dev_name(dev), state);
1396        if (ret) {
1397                dev_err(dev, "Interrupt request failed\n");
1398                goto disable_clock;
1399        }
1400
1401        /* Initialize and register the subdev. */
1402        ret = mipi_csis_subdev_init(state);
1403        if (ret < 0)
1404                goto disable_clock;
1405
1406        platform_set_drvdata(pdev, &state->sd);
1407
1408        ret = mipi_csis_async_register(state);
1409        if (ret < 0) {
1410                dev_err(dev, "async register failed: %d\n", ret);
1411                goto cleanup;
1412        }
1413
1414        /* Initialize debugfs. */
1415        mipi_csis_debugfs_init(state);
1416
1417        /* Enable runtime PM. */
1418        pm_runtime_enable(dev);
1419        if (!pm_runtime_enabled(dev)) {
1420                ret = mipi_csis_pm_resume(dev, true);
1421                if (ret < 0)
1422                        goto unregister_all;
1423        }
1424
1425        dev_info(dev, "lanes: %d, freq: %u\n",
1426                 state->bus.num_data_lanes, state->clk_frequency);
1427
1428        return 0;
1429
1430unregister_all:
1431        mipi_csis_debugfs_exit(state);
1432cleanup:
1433        media_entity_cleanup(&state->sd.entity);
1434        v4l2_async_notifier_unregister(&state->notifier);
1435        v4l2_async_notifier_cleanup(&state->notifier);
1436        v4l2_async_unregister_subdev(&state->sd);
1437disable_clock:
1438        mipi_csis_clk_disable(state);
1439        mutex_destroy(&state->lock);
1440
1441        return ret;
1442}
1443
1444static int mipi_csis_remove(struct platform_device *pdev)
1445{
1446        struct v4l2_subdev *sd = platform_get_drvdata(pdev);
1447        struct csi_state *state = mipi_sd_to_csis_state(sd);
1448
1449        mipi_csis_debugfs_exit(state);
1450        v4l2_async_notifier_unregister(&state->notifier);
1451        v4l2_async_notifier_cleanup(&state->notifier);
1452        v4l2_async_unregister_subdev(&state->sd);
1453
1454        pm_runtime_disable(&pdev->dev);
1455        mipi_csis_pm_suspend(&pdev->dev, true);
1456        mipi_csis_clk_disable(state);
1457        media_entity_cleanup(&state->sd.entity);
1458        mutex_destroy(&state->lock);
1459        pm_runtime_set_suspended(&pdev->dev);
1460
1461        return 0;
1462}
1463
1464static const struct of_device_id mipi_csis_of_match[] = {
1465        {
1466                .compatible = "fsl,imx7-mipi-csi2",
1467                .data = &(const struct mipi_csis_info){
1468                        .version = MIPI_CSIS_V3_3,
1469                        .num_clocks = 3,
1470                },
1471        }, {
1472                .compatible = "fsl,imx8mm-mipi-csi2",
1473                .data = &(const struct mipi_csis_info){
1474                        .version = MIPI_CSIS_V3_6_3,
1475                        .num_clocks = 4,
1476                },
1477        },
1478        { /* sentinel */ },
1479};
1480MODULE_DEVICE_TABLE(of, mipi_csis_of_match);
1481
1482static struct platform_driver mipi_csis_driver = {
1483        .probe          = mipi_csis_probe,
1484        .remove         = mipi_csis_remove,
1485        .driver         = {
1486                .of_match_table = mipi_csis_of_match,
1487                .name           = CSIS_DRIVER_NAME,
1488                .pm             = &mipi_csis_pm_ops,
1489        },
1490};
1491
1492module_platform_driver(mipi_csis_driver);
1493
1494MODULE_DESCRIPTION("i.MX7 & i.MX8 MIPI CSI-2 receiver driver");
1495MODULE_LICENSE("GPL v2");
1496MODULE_ALIAS("platform:imx7-mipi-csi2");
1497