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16#ifndef __DMA_LOCAL_H_INCLUDED__
17#define __DMA_LOCAL_H_INCLUDED__
18
19#include <type_support.h>
20#include "dma_global.h"
21
22#include <defs.h>
23#include <bits.h>
24#include <hive_isp_css_defs.h>
25#include <dma_v2_defs.h>
26
27#define _DMA_FSM_GROUP_CMD_IDX _DMA_V2_FSM_GROUP_CMD_IDX
28#define _DMA_FSM_GROUP_ADDR_A_IDX _DMA_V2_FSM_GROUP_ADDR_SRC_IDX
29#define _DMA_FSM_GROUP_ADDR_B_IDX _DMA_V2_FSM_GROUP_ADDR_DEST_IDX
30
31#define _DMA_FSM_GROUP_CMD_CTRL_IDX _DMA_V2_FSM_GROUP_CMD_CTRL_IDX
32
33#define _DMA_FSM_GROUP_FSM_CTRL_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_IDX
34#define _DMA_FSM_GROUP_FSM_CTRL_STATE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_STATE_IDX
35#define _DMA_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_DEV_IDX
36#define _DMA_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_ADDR_IDX
37#define _DMA_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_STRIDE_IDX
38#define _DMA_FSM_GROUP_FSM_CTRL_REQ_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_XB_IDX
39#define _DMA_FSM_GROUP_FSM_CTRL_REQ_YB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_REQ_YB_IDX
40#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_DEV_IDX
41#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_DEV_IDX
42#define _DMA_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_WR_ADDR_IDX
43#define _DMA_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_WR_STRIDE_IDX
44#define _DMA_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_REQ_XB_IDX
45#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_YB_IDX
46#define _DMA_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_WR_XB_IDX
47#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_REQ_IDX
48#define _DMA_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_ELEM_WR_IDX
49#define _DMA_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX _DMA_V2_FSM_GROUP_FSM_CTRL_PACK_S_Z_IDX
50
51#define _DMA_FSM_GROUP_FSM_PACK_IDX _DMA_V2_FSM_GROUP_FSM_PACK_IDX
52#define _DMA_FSM_GROUP_FSM_PACK_STATE_IDX _DMA_V2_FSM_GROUP_FSM_PACK_STATE_IDX
53#define _DMA_FSM_GROUP_FSM_PACK_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_YB_IDX
54#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_REQ_IDX
55#define _DMA_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX _DMA_V2_FSM_GROUP_FSM_PACK_CNT_XB_WR_IDX
56
57#define _DMA_FSM_GROUP_FSM_REQ_IDX _DMA_V2_FSM_GROUP_FSM_REQ_IDX
58#define _DMA_FSM_GROUP_FSM_REQ_STATE_IDX _DMA_V2_FSM_GROUP_FSM_REQ_STATE_IDX
59#define _DMA_FSM_GROUP_FSM_REQ_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_REQ_CNT_YB_IDX
60#define _DMA_FSM_GROUP_FSM_REQ_CNT_XB_IDX _DMA_V2_FSM_GROUP_FSM_REQ_CNT_XB_IDX
61
62#define _DMA_FSM_GROUP_FSM_WR_IDX _DMA_V2_FSM_GROUP_FSM_WR_IDX
63#define _DMA_FSM_GROUP_FSM_WR_STATE_IDX _DMA_V2_FSM_GROUP_FSM_WR_STATE_IDX
64#define _DMA_FSM_GROUP_FSM_WR_CNT_YB_IDX _DMA_V2_FSM_GROUP_FSM_WR_CNT_YB_IDX
65#define _DMA_FSM_GROUP_FSM_WR_CNT_XB_IDX _DMA_V2_FSM_GROUP_FSM_WR_CNT_XB_IDX
66
67#define _DMA_DEV_INTERF_MAX_BURST_IDX _DMA_V2_DEV_INTERF_MAX_BURST_IDX
68
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71
72#define DMA_SEL_COMP(comp) (((comp) & _hrt_ones(_DMA_V2_ADDR_SEL_COMP_BITS)) << _DMA_V2_ADDR_SEL_COMP_IDX)
73#define DMA_SEL_CH(ch) (((ch) & _hrt_ones(_DMA_V2_ADDR_SEL_CH_REG_BITS)) << _DMA_V2_ADDR_SEL_CH_REG_IDX)
74#define DMA_SEL_PARAM(param) (((param) & _hrt_ones(_DMA_V2_ADDR_SEL_PARAM_BITS)) << _DMA_V2_ADDR_SEL_PARAM_IDX)
75
76#define DMA_SEL_CG_INFO(info) (((info) & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_INFO_BITS)) << _DMA_V2_ADDR_SEL_GROUP_COMP_INFO_IDX)
77#define DMA_SEL_CG_COMP(comp) (((comp) & _hrt_ones(_DMA_V2_ADDR_SEL_GROUP_COMP_BITS)) << _DMA_V2_ADDR_SEL_GROUP_COMP_IDX)
78#define DMA_SEL_DEV_INFO(info) (((info) & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_INFO_BITS)) << _DMA_V2_ADDR_SEL_DEV_INTERF_INFO_IDX)
79#define DMA_SEL_DEV_ID(dev) (((dev) & _hrt_ones(_DMA_V2_ADDR_SEL_DEV_INTERF_IDX_BITS)) << _DMA_V2_ADDR_SEL_DEV_INTERF_IDX_IDX)
80
81#define DMA_COMMAND_FSM_REG_IDX (DMA_SEL_COMP(_DMA_V2_SEL_FSM_CMD) >> 2)
82#define DMA_CHANNEL_PARAM_REG_IDX(ch, param) ((DMA_SEL_COMP(_DMA_V2_SEL_CH_REG) | DMA_SEL_CH(ch) | DMA_SEL_PARAM(param)) >> 2)
83#define DMA_CG_INFO_REG_IDX(info_id, comp_id) ((DMA_SEL_COMP(_DMA_V2_SEL_CONN_GROUP) | DMA_SEL_CG_INFO(info_id) | DMA_SEL_CG_COMP(comp_id)) >> 2)
84#define DMA_DEV_INFO_REG_IDX(info_id, dev_id) ((DMA_SEL_COMP(_DMA_V2_SEL_DEV_INTERF) | DMA_SEL_DEV_INFO(info_id) | DMA_SEL_DEV_ID(dev_id)) >> 2)
85#define DMA_RST_REG_IDX (DMA_SEL_COMP(_DMA_V2_SEL_RESET) >> 2)
86
87#define DMA_GET_CONNECTION(val) _hrt_get_bits(val, _DMA_V2_CONNECTION_IDX, _DMA_V2_CONNECTION_BITS)
88#define DMA_GET_EXTENSION(val) _hrt_get_bits(val, _DMA_V2_EXTENSION_IDX, _DMA_V2_EXTENSION_BITS)
89#define DMA_GET_ELEMENTS(val) _hrt_get_bits(val, _DMA_V2_ELEMENTS_IDX, _DMA_V2_ELEMENTS_BITS)
90#define DMA_GET_CROPPING(val) _hrt_get_bits(val, _DMA_V2_LEFT_CROPPING_IDX, _DMA_V2_LEFT_CROPPING_BITS)
91
92typedef enum {
93 DMA_CTRL_STATE_IDLE,
94 DMA_CTRL_STATE_REQ_RCV,
95 DMA_CTRL_STATE_RCV,
96 DMA_CTRL_STATE_RCV_REQ,
97 DMA_CTRL_STATE_INIT,
98 N_DMA_CTRL_STATES
99} dma_ctrl_states_t;
100
101typedef enum {
102 DMA_COMMAND_READ,
103 DMA_COMMAND_WRITE,
104 DMA_COMMAND_SET_CHANNEL,
105 DMA_COMMAND_SET_PARAM,
106 DMA_COMMAND_READ_SPECIFIC,
107 DMA_COMMAND_WRITE_SPECIFIC,
108 DMA_COMMAND_INIT,
109 DMA_COMMAND_INIT_SPECIFIC,
110 DMA_COMMAND_RST,
111 N_DMA_COMMANDS
112} dma_commands_t;
113
114typedef enum {
115 DMA_RW_STATE_IDLE,
116 DMA_RW_STATE_REQ,
117 DMA_RW_STATE_NEXT_LINE,
118 DMA_RW_STATE_UNLOCK_CHANNEL,
119 N_DMA_RW_STATES
120} dma_rw_states_t;
121
122typedef enum {
123 DMA_FIFO_STATE_WILL_BE_FULL,
124 DMA_FIFO_STATE_FULL,
125 DMA_FIFO_STATE_EMPTY,
126 N_DMA_FIFO_STATES
127} dma_fifo_states_t;
128
129
130typedef struct dma_channel_state_s dma_channel_state_t;
131typedef struct dma_port_state_s dma_port_state_t;
132
133struct dma_port_state_s {
134 bool req_cs;
135 bool req_we_n;
136 bool req_run;
137 bool req_ack;
138 bool send_cs;
139 bool send_we_n;
140 bool send_run;
141 bool send_ack;
142 dma_fifo_states_t fifo_state;
143 int fifo_counter;
144};
145
146struct dma_channel_state_s {
147 int connection;
148 bool sign_extend;
149 int height;
150 int stride_a;
151 int elems_a;
152 int cropping_a;
153 int width_a;
154 int stride_b;
155 int elems_b;
156 int cropping_b;
157 int width_b;
158};
159
160struct dma_state_s {
161 bool fsm_command_idle;
162 bool fsm_command_run;
163 bool fsm_command_stalling;
164 bool fsm_command_error;
165 dma_commands_t last_command;
166 int last_command_channel;
167 int last_command_param;
168 dma_commands_t current_command;
169 int current_addr_a;
170 int current_addr_b;
171 bool fsm_ctrl_idle;
172 bool fsm_ctrl_run;
173 bool fsm_ctrl_stalling;
174 bool fsm_ctrl_error;
175 dma_ctrl_states_t fsm_ctrl_state;
176 int fsm_ctrl_source_dev;
177 int fsm_ctrl_source_addr;
178 int fsm_ctrl_source_stride;
179 int fsm_ctrl_source_width;
180 int fsm_ctrl_source_height;
181 int fsm_ctrl_pack_source_dev;
182 int fsm_ctrl_pack_dest_dev;
183 int fsm_ctrl_dest_addr;
184 int fsm_ctrl_dest_stride;
185 int fsm_ctrl_pack_source_width;
186 int fsm_ctrl_pack_dest_height;
187 int fsm_ctrl_pack_dest_width;
188 int fsm_ctrl_pack_source_elems;
189 int fsm_ctrl_pack_dest_elems;
190 int fsm_ctrl_pack_extension;
191 int pack_idle;
192 int pack_run;
193 int pack_stalling;
194 int pack_error;
195 int pack_cnt_height;
196 int pack_src_cnt_width;
197 int pack_dest_cnt_width;
198 dma_rw_states_t read_state;
199 int read_cnt_height;
200 int read_cnt_width;
201 dma_rw_states_t write_state;
202 int write_height;
203 int write_width;
204 dma_port_state_t port_states[HIVE_ISP_NUM_DMA_CONNS];
205 dma_channel_state_t channel_states[HIVE_DMA_NUM_CHANNELS];
206};
207
208#endif
209
