linux/drivers/spmi/spmi-pmic-arb.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved.
   4 */
   5#include <linux/bitmap.h>
   6#include <linux/delay.h>
   7#include <linux/err.h>
   8#include <linux/interrupt.h>
   9#include <linux/io.h>
  10#include <linux/irqchip/chained_irq.h>
  11#include <linux/irqdomain.h>
  12#include <linux/irq.h>
  13#include <linux/kernel.h>
  14#include <linux/module.h>
  15#include <linux/of.h>
  16#include <linux/platform_device.h>
  17#include <linux/slab.h>
  18#include <linux/spmi.h>
  19
  20/* PMIC Arbiter configuration registers */
  21#define PMIC_ARB_VERSION                0x0000
  22#define PMIC_ARB_VERSION_V2_MIN         0x20010000
  23#define PMIC_ARB_VERSION_V3_MIN         0x30000000
  24#define PMIC_ARB_VERSION_V5_MIN         0x50000000
  25#define PMIC_ARB_INT_EN                 0x0004
  26
  27/* PMIC Arbiter channel registers offsets */
  28#define PMIC_ARB_CMD                    0x00
  29#define PMIC_ARB_CONFIG                 0x04
  30#define PMIC_ARB_STATUS                 0x08
  31#define PMIC_ARB_WDATA0                 0x10
  32#define PMIC_ARB_WDATA1                 0x14
  33#define PMIC_ARB_RDATA0                 0x18
  34#define PMIC_ARB_RDATA1                 0x1C
  35
  36/* Mapping Table */
  37#define SPMI_MAPPING_TABLE_REG(N)       (0x0B00 + (4 * (N)))
  38#define SPMI_MAPPING_BIT_INDEX(X)       (((X) >> 18) & 0xF)
  39#define SPMI_MAPPING_BIT_IS_0_FLAG(X)   (((X) >> 17) & 0x1)
  40#define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF)
  41#define SPMI_MAPPING_BIT_IS_1_FLAG(X)   (((X) >> 8) & 0x1)
  42#define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF)
  43
  44#define SPMI_MAPPING_TABLE_TREE_DEPTH   16      /* Maximum of 16-bits */
  45#define PMIC_ARB_MAX_PPID               BIT(12) /* PPID is 12bit */
  46#define PMIC_ARB_APID_VALID             BIT(15)
  47#define PMIC_ARB_CHAN_IS_IRQ_OWNER(reg) ((reg) & BIT(24))
  48#define INVALID_EE                              0xFF
  49
  50/* Ownership Table */
  51#define SPMI_OWNERSHIP_TABLE_REG(N)     (0x0700 + (4 * (N)))
  52#define SPMI_OWNERSHIP_PERIPH2OWNER(X)  ((X) & 0x7)
  53
  54/* Channel Status fields */
  55enum pmic_arb_chnl_status {
  56        PMIC_ARB_STATUS_DONE    = BIT(0),
  57        PMIC_ARB_STATUS_FAILURE = BIT(1),
  58        PMIC_ARB_STATUS_DENIED  = BIT(2),
  59        PMIC_ARB_STATUS_DROPPED = BIT(3),
  60};
  61
  62/* Command register fields */
  63#define PMIC_ARB_CMD_MAX_BYTE_COUNT     8
  64
  65/* Command Opcodes */
  66enum pmic_arb_cmd_op_code {
  67        PMIC_ARB_OP_EXT_WRITEL = 0,
  68        PMIC_ARB_OP_EXT_READL = 1,
  69        PMIC_ARB_OP_EXT_WRITE = 2,
  70        PMIC_ARB_OP_RESET = 3,
  71        PMIC_ARB_OP_SLEEP = 4,
  72        PMIC_ARB_OP_SHUTDOWN = 5,
  73        PMIC_ARB_OP_WAKEUP = 6,
  74        PMIC_ARB_OP_AUTHENTICATE = 7,
  75        PMIC_ARB_OP_MSTR_READ = 8,
  76        PMIC_ARB_OP_MSTR_WRITE = 9,
  77        PMIC_ARB_OP_EXT_READ = 13,
  78        PMIC_ARB_OP_WRITE = 14,
  79        PMIC_ARB_OP_READ = 15,
  80        PMIC_ARB_OP_ZERO_WRITE = 16,
  81};
  82
  83/*
  84 * PMIC arbiter version 5 uses different register offsets for read/write vs
  85 * observer channels.
  86 */
  87enum pmic_arb_channel {
  88        PMIC_ARB_CHANNEL_RW,
  89        PMIC_ARB_CHANNEL_OBS,
  90};
  91
  92/* Maximum number of support PMIC peripherals */
  93#define PMIC_ARB_MAX_PERIPHS            512
  94#define PMIC_ARB_TIMEOUT_US             100
  95#define PMIC_ARB_MAX_TRANS_BYTES        (8)
  96
  97#define PMIC_ARB_APID_MASK              0xFF
  98#define PMIC_ARB_PPID_MASK              0xFFF
  99
 100/* interrupt enable bit */
 101#define SPMI_PIC_ACC_ENABLE_BIT         BIT(0)
 102
 103#define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \
 104        ((((slave_id) & 0xF)   << 28) | \
 105        (((periph_id) & 0xFF)  << 20) | \
 106        (((irq_id)    & 0x7)   << 16) | \
 107        (((apid)      & 0x1FF) << 0))
 108
 109#define hwirq_to_sid(hwirq)  (((hwirq) >> 28) & 0xF)
 110#define hwirq_to_per(hwirq)  (((hwirq) >> 20) & 0xFF)
 111#define hwirq_to_irq(hwirq)  (((hwirq) >> 16) & 0x7)
 112#define hwirq_to_apid(hwirq) (((hwirq) >> 0)  & 0x1FF)
 113
 114struct pmic_arb_ver_ops;
 115
 116struct apid_data {
 117        u16             ppid;
 118        u8              write_ee;
 119        u8              irq_ee;
 120};
 121
 122/**
 123 * spmi_pmic_arb - SPMI PMIC Arbiter object
 124 *
 125 * @rd_base:            on v1 "core", on v2 "observer" register base off DT.
 126 * @wr_base:            on v1 "core", on v2 "chnls"    register base off DT.
 127 * @intr:               address of the SPMI interrupt control registers.
 128 * @cnfg:               address of the PMIC Arbiter configuration registers.
 129 * @lock:               lock to synchronize accesses.
 130 * @channel:            execution environment channel to use for accesses.
 131 * @irq:                PMIC ARB interrupt.
 132 * @ee:                 the current Execution Environment
 133 * @min_apid:           minimum APID (used for bounding IRQ search)
 134 * @max_apid:           maximum APID
 135 * @mapping_table:      in-memory copy of PPID -> APID mapping table.
 136 * @domain:             irq domain object for PMIC IRQ domain
 137 * @spmic:              SPMI controller object
 138 * @ver_ops:            version dependent operations.
 139 * @ppid_to_apid        in-memory copy of PPID -> APID mapping table.
 140 */
 141struct spmi_pmic_arb {
 142        void __iomem            *rd_base;
 143        void __iomem            *wr_base;
 144        void __iomem            *intr;
 145        void __iomem            *cnfg;
 146        void __iomem            *core;
 147        resource_size_t         core_size;
 148        raw_spinlock_t          lock;
 149        u8                      channel;
 150        int                     irq;
 151        u8                      ee;
 152        u16                     min_apid;
 153        u16                     max_apid;
 154        u32                     *mapping_table;
 155        DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS);
 156        struct irq_domain       *domain;
 157        struct spmi_controller  *spmic;
 158        const struct pmic_arb_ver_ops *ver_ops;
 159        u16                     *ppid_to_apid;
 160        u16                     last_apid;
 161        struct apid_data        apid_data[PMIC_ARB_MAX_PERIPHS];
 162};
 163
 164/**
 165 * pmic_arb_ver: version dependent functionality.
 166 *
 167 * @ver_str:            version string.
 168 * @ppid_to_apid:       finds the apid for a given ppid.
 169 * @non_data_cmd:       on v1 issues an spmi non-data command.
 170 *                      on v2 no HW support, returns -EOPNOTSUPP.
 171 * @offset:             on v1 offset of per-ee channel.
 172 *                      on v2 offset of per-ee and per-ppid channel.
 173 * @fmt_cmd:            formats a GENI/SPMI command.
 174 * @owner_acc_status:   on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn
 175 *                      on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn.
 176 * @acc_enable:         on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn
 177 *                      on v2 address of SPMI_PIC_ACC_ENABLEn.
 178 * @irq_status:         on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn
 179 *                      on v2 address of SPMI_PIC_IRQ_STATUSn.
 180 * @irq_clear:          on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn
 181 *                      on v2 address of SPMI_PIC_IRQ_CLEARn.
 182 * @apid_map_offset:    offset of PMIC_ARB_REG_CHNLn
 183 */
 184struct pmic_arb_ver_ops {
 185        const char *ver_str;
 186        int (*ppid_to_apid)(struct spmi_pmic_arb *pmic_arb, u16 ppid);
 187        /* spmi commands (read_cmd, write_cmd, cmd) functionality */
 188        int (*offset)(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 189                        enum pmic_arb_channel ch_type);
 190        u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc);
 191        int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid);
 192        /* Interrupts controller functionality (offset of PIC registers) */
 193        void __iomem *(*owner_acc_status)(struct spmi_pmic_arb *pmic_arb, u8 m,
 194                                          u16 n);
 195        void __iomem *(*acc_enable)(struct spmi_pmic_arb *pmic_arb, u16 n);
 196        void __iomem *(*irq_status)(struct spmi_pmic_arb *pmic_arb, u16 n);
 197        void __iomem *(*irq_clear)(struct spmi_pmic_arb *pmic_arb, u16 n);
 198        u32 (*apid_map_offset)(u16 n);
 199};
 200
 201static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb,
 202                                       u32 offset, u32 val)
 203{
 204        writel_relaxed(val, pmic_arb->wr_base + offset);
 205}
 206
 207static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb,
 208                                       u32 offset, u32 val)
 209{
 210        writel_relaxed(val, pmic_arb->rd_base + offset);
 211}
 212
 213/**
 214 * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf
 215 * @bc:         byte count -1. range: 0..3
 216 * @reg:        register's address
 217 * @buf:        output parameter, length must be bc + 1
 218 */
 219static void
 220pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc)
 221{
 222        u32 data = __raw_readl(pmic_arb->rd_base + reg);
 223
 224        memcpy(buf, &data, (bc & 3) + 1);
 225}
 226
 227/**
 228 * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register
 229 * @bc:         byte-count -1. range: 0..3.
 230 * @reg:        register's address.
 231 * @buf:        buffer to write. length must be bc + 1.
 232 */
 233static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf,
 234                                u32 reg, u8 bc)
 235{
 236        u32 data = 0;
 237
 238        memcpy(&data, buf, (bc & 3) + 1);
 239        __raw_writel(data, pmic_arb->wr_base + reg);
 240}
 241
 242static int pmic_arb_wait_for_done(struct spmi_controller *ctrl,
 243                                  void __iomem *base, u8 sid, u16 addr,
 244                                  enum pmic_arb_channel ch_type)
 245{
 246        struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 247        u32 status = 0;
 248        u32 timeout = PMIC_ARB_TIMEOUT_US;
 249        u32 offset;
 250        int rc;
 251
 252        rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr, ch_type);
 253        if (rc < 0)
 254                return rc;
 255
 256        offset = rc;
 257        offset += PMIC_ARB_STATUS;
 258
 259        while (timeout--) {
 260                status = readl_relaxed(base + offset);
 261
 262                if (status & PMIC_ARB_STATUS_DONE) {
 263                        if (status & PMIC_ARB_STATUS_DENIED) {
 264                                dev_err(&ctrl->dev, "%s: transaction denied (0x%x)\n",
 265                                        __func__, status);
 266                                return -EPERM;
 267                        }
 268
 269                        if (status & PMIC_ARB_STATUS_FAILURE) {
 270                                dev_err(&ctrl->dev, "%s: transaction failed (0x%x)\n",
 271                                        __func__, status);
 272                                return -EIO;
 273                        }
 274
 275                        if (status & PMIC_ARB_STATUS_DROPPED) {
 276                                dev_err(&ctrl->dev, "%s: transaction dropped (0x%x)\n",
 277                                        __func__, status);
 278                                return -EIO;
 279                        }
 280
 281                        return 0;
 282                }
 283                udelay(1);
 284        }
 285
 286        dev_err(&ctrl->dev, "%s: timeout, status 0x%x\n",
 287                __func__, status);
 288        return -ETIMEDOUT;
 289}
 290
 291static int
 292pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid)
 293{
 294        struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 295        unsigned long flags;
 296        u32 cmd;
 297        int rc;
 298        u32 offset;
 299
 300        rc = pmic_arb->ver_ops->offset(pmic_arb, sid, 0, PMIC_ARB_CHANNEL_RW);
 301        if (rc < 0)
 302                return rc;
 303
 304        offset = rc;
 305        cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20);
 306
 307        raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 308        pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 309        rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0,
 310                                    PMIC_ARB_CHANNEL_RW);
 311        raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 312
 313        return rc;
 314}
 315
 316static int
 317pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid)
 318{
 319        return -EOPNOTSUPP;
 320}
 321
 322/* Non-data command */
 323static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid)
 324{
 325        struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 326
 327        dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid);
 328
 329        /* Check for valid non-data command */
 330        if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP)
 331                return -EINVAL;
 332
 333        return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid);
 334}
 335
 336static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 337                             u16 addr, u8 *buf, size_t len)
 338{
 339        struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 340        unsigned long flags;
 341        u8 bc = len - 1;
 342        u32 cmd;
 343        int rc;
 344        u32 offset;
 345
 346        rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
 347                                       PMIC_ARB_CHANNEL_OBS);
 348        if (rc < 0)
 349                return rc;
 350
 351        offset = rc;
 352        if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 353                dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 354                        PMIC_ARB_MAX_TRANS_BYTES, len);
 355                return  -EINVAL;
 356        }
 357
 358        /* Check the opcode */
 359        if (opc >= 0x60 && opc <= 0x7F)
 360                opc = PMIC_ARB_OP_READ;
 361        else if (opc >= 0x20 && opc <= 0x2F)
 362                opc = PMIC_ARB_OP_EXT_READ;
 363        else if (opc >= 0x38 && opc <= 0x3F)
 364                opc = PMIC_ARB_OP_EXT_READL;
 365        else
 366                return -EINVAL;
 367
 368        cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 369
 370        raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 371        pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 372        rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr,
 373                                    PMIC_ARB_CHANNEL_OBS);
 374        if (rc)
 375                goto done;
 376
 377        pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0,
 378                     min_t(u8, bc, 3));
 379
 380        if (bc > 3)
 381                pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1,
 382                                        bc - 4);
 383
 384done:
 385        raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 386        return rc;
 387}
 388
 389static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid,
 390                        u16 addr, const u8 *buf, size_t len)
 391{
 392        struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
 393        unsigned long flags;
 394        u8 bc = len - 1;
 395        u32 cmd;
 396        int rc;
 397        u32 offset;
 398
 399        rc = pmic_arb->ver_ops->offset(pmic_arb, sid, addr,
 400                                        PMIC_ARB_CHANNEL_RW);
 401        if (rc < 0)
 402                return rc;
 403
 404        offset = rc;
 405        if (bc >= PMIC_ARB_MAX_TRANS_BYTES) {
 406                dev_err(&ctrl->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested",
 407                        PMIC_ARB_MAX_TRANS_BYTES, len);
 408                return  -EINVAL;
 409        }
 410
 411        /* Check the opcode */
 412        if (opc >= 0x40 && opc <= 0x5F)
 413                opc = PMIC_ARB_OP_WRITE;
 414        else if (opc <= 0x0F)
 415                opc = PMIC_ARB_OP_EXT_WRITE;
 416        else if (opc >= 0x30 && opc <= 0x37)
 417                opc = PMIC_ARB_OP_EXT_WRITEL;
 418        else if (opc >= 0x80)
 419                opc = PMIC_ARB_OP_ZERO_WRITE;
 420        else
 421                return -EINVAL;
 422
 423        cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc);
 424
 425        /* Write data to FIFOs */
 426        raw_spin_lock_irqsave(&pmic_arb->lock, flags);
 427        pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0,
 428                                min_t(u8, bc, 3));
 429        if (bc > 3)
 430                pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1,
 431                                        bc - 4);
 432
 433        /* Start the transaction */
 434        pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd);
 435        rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr,
 436                                    PMIC_ARB_CHANNEL_RW);
 437        raw_spin_unlock_irqrestore(&pmic_arb->lock, flags);
 438
 439        return rc;
 440}
 441
 442enum qpnpint_regs {
 443        QPNPINT_REG_RT_STS              = 0x10,
 444        QPNPINT_REG_SET_TYPE            = 0x11,
 445        QPNPINT_REG_POLARITY_HIGH       = 0x12,
 446        QPNPINT_REG_POLARITY_LOW        = 0x13,
 447        QPNPINT_REG_LATCHED_CLR         = 0x14,
 448        QPNPINT_REG_EN_SET              = 0x15,
 449        QPNPINT_REG_EN_CLR              = 0x16,
 450        QPNPINT_REG_LATCHED_STS         = 0x18,
 451};
 452
 453struct spmi_pmic_arb_qpnpint_type {
 454        u8 type; /* 1 -> edge */
 455        u8 polarity_high;
 456        u8 polarity_low;
 457} __packed;
 458
 459/* Simplified accessor functions for irqchip callbacks */
 460static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf,
 461                               size_t len)
 462{
 463        struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 464        u8 sid = hwirq_to_sid(d->hwirq);
 465        u8 per = hwirq_to_per(d->hwirq);
 466
 467        if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
 468                               (per << 8) + reg, buf, len))
 469                dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
 470                                    d->irq);
 471}
 472
 473static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len)
 474{
 475        struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 476        u8 sid = hwirq_to_sid(d->hwirq);
 477        u8 per = hwirq_to_per(d->hwirq);
 478
 479        if (pmic_arb_read_cmd(pmic_arb->spmic, SPMI_CMD_EXT_READL, sid,
 480                              (per << 8) + reg, buf, len))
 481                dev_err_ratelimited(&pmic_arb->spmic->dev, "failed irqchip transaction on %x\n",
 482                                    d->irq);
 483}
 484
 485static void cleanup_irq(struct spmi_pmic_arb *pmic_arb, u16 apid, int id)
 486{
 487        u16 ppid = pmic_arb->apid_data[apid].ppid;
 488        u8 sid = ppid >> 8;
 489        u8 per = ppid & 0xFF;
 490        u8 irq_mask = BIT(id);
 491
 492        writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
 493
 494        if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
 495                        (per << 8) + QPNPINT_REG_LATCHED_CLR, &irq_mask, 1))
 496                dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
 497                                irq_mask, ppid);
 498
 499        if (pmic_arb_write_cmd(pmic_arb->spmic, SPMI_CMD_EXT_WRITEL, sid,
 500                               (per << 8) + QPNPINT_REG_EN_CLR, &irq_mask, 1))
 501                dev_err_ratelimited(&pmic_arb->spmic->dev, "failed to ack irq_mask = 0x%x for ppid = %x\n",
 502                                irq_mask, ppid);
 503}
 504
 505static void periph_interrupt(struct spmi_pmic_arb *pmic_arb, u16 apid)
 506{
 507        unsigned int irq;
 508        u32 status, id;
 509        u8 sid = (pmic_arb->apid_data[apid].ppid >> 8) & 0xF;
 510        u8 per = pmic_arb->apid_data[apid].ppid & 0xFF;
 511
 512        status = readl_relaxed(pmic_arb->ver_ops->irq_status(pmic_arb, apid));
 513        while (status) {
 514                id = ffs(status) - 1;
 515                status &= ~BIT(id);
 516                irq = irq_find_mapping(pmic_arb->domain,
 517                                        spec_to_hwirq(sid, per, id, apid));
 518                if (irq == 0) {
 519                        cleanup_irq(pmic_arb, apid, id);
 520                        continue;
 521                }
 522                generic_handle_irq(irq);
 523        }
 524}
 525
 526static void pmic_arb_chained_irq(struct irq_desc *desc)
 527{
 528        struct spmi_pmic_arb *pmic_arb = irq_desc_get_handler_data(desc);
 529        const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
 530        struct irq_chip *chip = irq_desc_get_chip(desc);
 531        int first = pmic_arb->min_apid >> 5;
 532        int last = pmic_arb->max_apid >> 5;
 533        u8 ee = pmic_arb->ee;
 534        u32 status, enable;
 535        int i, id, apid;
 536
 537        chained_irq_enter(chip, desc);
 538
 539        for (i = first; i <= last; ++i) {
 540                status = readl_relaxed(
 541                                ver_ops->owner_acc_status(pmic_arb, ee, i));
 542                while (status) {
 543                        id = ffs(status) - 1;
 544                        status &= ~BIT(id);
 545                        apid = id + i * 32;
 546                        enable = readl_relaxed(
 547                                        ver_ops->acc_enable(pmic_arb, apid));
 548                        if (enable & SPMI_PIC_ACC_ENABLE_BIT)
 549                                periph_interrupt(pmic_arb, apid);
 550                }
 551        }
 552
 553        chained_irq_exit(chip, desc);
 554}
 555
 556static void qpnpint_irq_ack(struct irq_data *d)
 557{
 558        struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 559        u8 irq = hwirq_to_irq(d->hwirq);
 560        u16 apid = hwirq_to_apid(d->hwirq);
 561        u8 data;
 562
 563        writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(pmic_arb, apid));
 564
 565        data = BIT(irq);
 566        qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1);
 567}
 568
 569static void qpnpint_irq_mask(struct irq_data *d)
 570{
 571        u8 irq = hwirq_to_irq(d->hwirq);
 572        u8 data = BIT(irq);
 573
 574        qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1);
 575}
 576
 577static void qpnpint_irq_unmask(struct irq_data *d)
 578{
 579        struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 580        const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops;
 581        u8 irq = hwirq_to_irq(d->hwirq);
 582        u16 apid = hwirq_to_apid(d->hwirq);
 583        u8 buf[2];
 584
 585        writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT,
 586                        ver_ops->acc_enable(pmic_arb, apid));
 587
 588        qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1);
 589        if (!(buf[0] & BIT(irq))) {
 590                /*
 591                 * Since the interrupt is currently disabled, write to both the
 592                 * LATCHED_CLR and EN_SET registers so that a spurious interrupt
 593                 * cannot be triggered when the interrupt is enabled
 594                 */
 595                buf[0] = BIT(irq);
 596                buf[1] = BIT(irq);
 597                qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2);
 598        }
 599}
 600
 601static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type)
 602{
 603        struct spmi_pmic_arb_qpnpint_type type;
 604        irq_flow_handler_t flow_handler;
 605        u8 irq = hwirq_to_irq(d->hwirq);
 606
 607        qpnpint_spmi_read(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
 608
 609        if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
 610                type.type |= BIT(irq);
 611                if (flow_type & IRQF_TRIGGER_RISING)
 612                        type.polarity_high |= BIT(irq);
 613                if (flow_type & IRQF_TRIGGER_FALLING)
 614                        type.polarity_low  |= BIT(irq);
 615
 616                flow_handler = handle_edge_irq;
 617        } else {
 618                if ((flow_type & (IRQF_TRIGGER_HIGH)) &&
 619                    (flow_type & (IRQF_TRIGGER_LOW)))
 620                        return -EINVAL;
 621
 622                type.type &= ~BIT(irq); /* level trig */
 623                if (flow_type & IRQF_TRIGGER_HIGH)
 624                        type.polarity_high |= BIT(irq);
 625                else
 626                        type.polarity_low  |= BIT(irq);
 627
 628                flow_handler = handle_level_irq;
 629        }
 630
 631        qpnpint_spmi_write(d, QPNPINT_REG_SET_TYPE, &type, sizeof(type));
 632        irq_set_handler_locked(d, flow_handler);
 633
 634        return 0;
 635}
 636
 637static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on)
 638{
 639        struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 640
 641        return irq_set_irq_wake(pmic_arb->irq, on);
 642}
 643
 644static int qpnpint_get_irqchip_state(struct irq_data *d,
 645                                     enum irqchip_irq_state which,
 646                                     bool *state)
 647{
 648        u8 irq = hwirq_to_irq(d->hwirq);
 649        u8 status = 0;
 650
 651        if (which != IRQCHIP_STATE_LINE_LEVEL)
 652                return -EINVAL;
 653
 654        qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1);
 655        *state = !!(status & BIT(irq));
 656
 657        return 0;
 658}
 659
 660static int qpnpint_irq_domain_activate(struct irq_domain *domain,
 661                                       struct irq_data *d, bool reserve)
 662{
 663        struct spmi_pmic_arb *pmic_arb = irq_data_get_irq_chip_data(d);
 664        u16 periph = hwirq_to_per(d->hwirq);
 665        u16 apid = hwirq_to_apid(d->hwirq);
 666        u16 sid = hwirq_to_sid(d->hwirq);
 667        u16 irq = hwirq_to_irq(d->hwirq);
 668
 669        if (pmic_arb->apid_data[apid].irq_ee != pmic_arb->ee) {
 670                dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n",
 671                        sid, periph, irq, pmic_arb->ee,
 672                        pmic_arb->apid_data[apid].irq_ee);
 673                return -ENODEV;
 674        }
 675
 676        return 0;
 677}
 678
 679static struct irq_chip pmic_arb_irqchip = {
 680        .name           = "pmic_arb",
 681        .irq_ack        = qpnpint_irq_ack,
 682        .irq_mask       = qpnpint_irq_mask,
 683        .irq_unmask     = qpnpint_irq_unmask,
 684        .irq_set_type   = qpnpint_irq_set_type,
 685        .irq_set_wake   = qpnpint_irq_set_wake,
 686        .irq_get_irqchip_state  = qpnpint_get_irqchip_state,
 687        .flags          = IRQCHIP_MASK_ON_SUSPEND,
 688};
 689
 690static int qpnpint_irq_domain_translate(struct irq_domain *d,
 691                                        struct irq_fwspec *fwspec,
 692                                        unsigned long *out_hwirq,
 693                                        unsigned int *out_type)
 694{
 695        struct spmi_pmic_arb *pmic_arb = d->host_data;
 696        u32 *intspec = fwspec->param;
 697        u16 apid, ppid;
 698        int rc;
 699
 700        dev_dbg(&pmic_arb->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n",
 701                intspec[0], intspec[1], intspec[2]);
 702
 703        if (irq_domain_get_of_node(d) != pmic_arb->spmic->dev.of_node)
 704                return -EINVAL;
 705        if (fwspec->param_count != 4)
 706                return -EINVAL;
 707        if (intspec[0] > 0xF || intspec[1] > 0xFF || intspec[2] > 0x7)
 708                return -EINVAL;
 709
 710        ppid = intspec[0] << 8 | intspec[1];
 711        rc = pmic_arb->ver_ops->ppid_to_apid(pmic_arb, ppid);
 712        if (rc < 0) {
 713                dev_err(&pmic_arb->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n",
 714                intspec[0], intspec[1], intspec[2], rc);
 715                return rc;
 716        }
 717
 718        apid = rc;
 719        /* Keep track of {max,min}_apid for bounding search during interrupt */
 720        if (apid > pmic_arb->max_apid)
 721                pmic_arb->max_apid = apid;
 722        if (apid < pmic_arb->min_apid)
 723                pmic_arb->min_apid = apid;
 724
 725        *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid);
 726        *out_type  = intspec[3] & IRQ_TYPE_SENSE_MASK;
 727
 728        dev_dbg(&pmic_arb->spmic->dev, "out_hwirq = %lu\n", *out_hwirq);
 729
 730        return 0;
 731}
 732
 733static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class;
 734
 735static void qpnpint_irq_domain_map(struct spmi_pmic_arb *pmic_arb,
 736                                   struct irq_domain *domain, unsigned int virq,
 737                                   irq_hw_number_t hwirq, unsigned int type)
 738{
 739        irq_flow_handler_t handler;
 740
 741        dev_dbg(&pmic_arb->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n",
 742                virq, hwirq, type);
 743
 744        if (type & IRQ_TYPE_EDGE_BOTH)
 745                handler = handle_edge_irq;
 746        else
 747                handler = handle_level_irq;
 748
 749
 750        irq_set_lockdep_class(virq, &qpnpint_irq_lock_class,
 751                              &qpnpint_irq_request_class);
 752        irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, pmic_arb,
 753                            handler, NULL, NULL);
 754}
 755
 756static int qpnpint_irq_domain_alloc(struct irq_domain *domain,
 757                                    unsigned int virq, unsigned int nr_irqs,
 758                                    void *data)
 759{
 760        struct spmi_pmic_arb *pmic_arb = domain->host_data;
 761        struct irq_fwspec *fwspec = data;
 762        irq_hw_number_t hwirq;
 763        unsigned int type;
 764        int ret, i;
 765
 766        ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type);
 767        if (ret)
 768                return ret;
 769
 770        for (i = 0; i < nr_irqs; i++)
 771                qpnpint_irq_domain_map(pmic_arb, domain, virq + i, hwirq + i,
 772                                       type);
 773
 774        return 0;
 775}
 776
 777static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 778{
 779        u32 *mapping_table = pmic_arb->mapping_table;
 780        int index = 0, i;
 781        u16 apid_valid;
 782        u16 apid;
 783        u32 data;
 784
 785        apid_valid = pmic_arb->ppid_to_apid[ppid];
 786        if (apid_valid & PMIC_ARB_APID_VALID) {
 787                apid = apid_valid & ~PMIC_ARB_APID_VALID;
 788                return apid;
 789        }
 790
 791        for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) {
 792                if (!test_and_set_bit(index, pmic_arb->mapping_table_valid))
 793                        mapping_table[index] = readl_relaxed(pmic_arb->cnfg +
 794                                                SPMI_MAPPING_TABLE_REG(index));
 795
 796                data = mapping_table[index];
 797
 798                if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) {
 799                        if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) {
 800                                index = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 801                        } else {
 802                                apid = SPMI_MAPPING_BIT_IS_1_RESULT(data);
 803                                pmic_arb->ppid_to_apid[ppid]
 804                                        = apid | PMIC_ARB_APID_VALID;
 805                                pmic_arb->apid_data[apid].ppid = ppid;
 806                                return apid;
 807                        }
 808                } else {
 809                        if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) {
 810                                index = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 811                        } else {
 812                                apid = SPMI_MAPPING_BIT_IS_0_RESULT(data);
 813                                pmic_arb->ppid_to_apid[ppid]
 814                                        = apid | PMIC_ARB_APID_VALID;
 815                                pmic_arb->apid_data[apid].ppid = ppid;
 816                                return apid;
 817                        }
 818                }
 819        }
 820
 821        return -ENODEV;
 822}
 823
 824/* v1 offset per ee */
 825static int pmic_arb_offset_v1(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 826                        enum pmic_arb_channel ch_type)
 827{
 828        return 0x800 + 0x80 * pmic_arb->channel;
 829}
 830
 831static u16 pmic_arb_find_apid(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 832{
 833        struct apid_data *apidd = &pmic_arb->apid_data[pmic_arb->last_apid];
 834        u32 regval, offset;
 835        u16 id, apid;
 836
 837        for (apid = pmic_arb->last_apid; ; apid++, apidd++) {
 838                offset = pmic_arb->ver_ops->apid_map_offset(apid);
 839                if (offset >= pmic_arb->core_size)
 840                        break;
 841
 842                regval = readl_relaxed(pmic_arb->cnfg +
 843                                      SPMI_OWNERSHIP_TABLE_REG(apid));
 844                apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
 845                apidd->write_ee = apidd->irq_ee;
 846
 847                regval = readl_relaxed(pmic_arb->core + offset);
 848                if (!regval)
 849                        continue;
 850
 851                id = (regval >> 8) & PMIC_ARB_PPID_MASK;
 852                pmic_arb->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID;
 853                apidd->ppid = id;
 854                if (id == ppid) {
 855                        apid |= PMIC_ARB_APID_VALID;
 856                        break;
 857                }
 858        }
 859        pmic_arb->last_apid = apid & ~PMIC_ARB_APID_VALID;
 860
 861        return apid;
 862}
 863
 864static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 865{
 866        u16 apid_valid;
 867
 868        apid_valid = pmic_arb->ppid_to_apid[ppid];
 869        if (!(apid_valid & PMIC_ARB_APID_VALID))
 870                apid_valid = pmic_arb_find_apid(pmic_arb, ppid);
 871        if (!(apid_valid & PMIC_ARB_APID_VALID))
 872                return -ENODEV;
 873
 874        return apid_valid & ~PMIC_ARB_APID_VALID;
 875}
 876
 877static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb *pmic_arb)
 878{
 879        struct apid_data *apidd = pmic_arb->apid_data;
 880        struct apid_data *prev_apidd;
 881        u16 i, apid, ppid;
 882        bool valid, is_irq_ee;
 883        u32 regval, offset;
 884
 885        /*
 886         * In order to allow multiple EEs to write to a single PPID in arbiter
 887         * version 5, there is more than one APID mapped to each PPID.
 888         * The owner field for each of these mappings specifies the EE which is
 889         * allowed to write to the APID.  The owner of the last (highest) APID
 890         * for a given PPID will receive interrupts from the PPID.
 891         */
 892        for (i = 0; ; i++, apidd++) {
 893                offset = pmic_arb->ver_ops->apid_map_offset(i);
 894                if (offset >= pmic_arb->core_size)
 895                        break;
 896
 897                regval = readl_relaxed(pmic_arb->core + offset);
 898                if (!regval)
 899                        continue;
 900                ppid = (regval >> 8) & PMIC_ARB_PPID_MASK;
 901                is_irq_ee = PMIC_ARB_CHAN_IS_IRQ_OWNER(regval);
 902
 903                regval = readl_relaxed(pmic_arb->cnfg +
 904                                      SPMI_OWNERSHIP_TABLE_REG(i));
 905                apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval);
 906
 907                apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE;
 908
 909                valid = pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID;
 910                apid = pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
 911                prev_apidd = &pmic_arb->apid_data[apid];
 912
 913                if (valid && is_irq_ee &&
 914                                prev_apidd->write_ee == pmic_arb->ee) {
 915                        /*
 916                         * Duplicate PPID mapping after the one for this EE;
 917                         * override the irq owner
 918                         */
 919                        prev_apidd->irq_ee = apidd->irq_ee;
 920                } else if (!valid || is_irq_ee) {
 921                        /* First PPID mapping or duplicate for another EE */
 922                        pmic_arb->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID;
 923                }
 924
 925                apidd->ppid = ppid;
 926                pmic_arb->last_apid = i;
 927        }
 928
 929        /* Dump the mapping table for debug purposes. */
 930        dev_dbg(&pmic_arb->spmic->dev, "PPID APID Write-EE IRQ-EE\n");
 931        for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) {
 932                apid = pmic_arb->ppid_to_apid[ppid];
 933                if (apid & PMIC_ARB_APID_VALID) {
 934                        apid &= ~PMIC_ARB_APID_VALID;
 935                        apidd = &pmic_arb->apid_data[apid];
 936                        dev_dbg(&pmic_arb->spmic->dev, "%#03X %3u %2u %2u\n",
 937                              ppid, apid, apidd->write_ee, apidd->irq_ee);
 938                }
 939        }
 940
 941        return 0;
 942}
 943
 944static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb *pmic_arb, u16 ppid)
 945{
 946        if (!(pmic_arb->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID))
 947                return -ENODEV;
 948
 949        return pmic_arb->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID;
 950}
 951
 952/* v2 offset per ppid and per ee */
 953static int pmic_arb_offset_v2(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 954                           enum pmic_arb_channel ch_type)
 955{
 956        u16 apid;
 957        u16 ppid;
 958        int rc;
 959
 960        ppid = sid << 8 | ((addr >> 8) & 0xFF);
 961        rc = pmic_arb_ppid_to_apid_v2(pmic_arb, ppid);
 962        if (rc < 0)
 963                return rc;
 964
 965        apid = rc;
 966        return 0x1000 * pmic_arb->ee + 0x8000 * apid;
 967}
 968
 969/*
 970 * v5 offset per ee and per apid for observer channels and per apid for
 971 * read/write channels.
 972 */
 973static int pmic_arb_offset_v5(struct spmi_pmic_arb *pmic_arb, u8 sid, u16 addr,
 974                           enum pmic_arb_channel ch_type)
 975{
 976        u16 apid;
 977        int rc;
 978        u32 offset = 0;
 979        u16 ppid = (sid << 8) | (addr >> 8);
 980
 981        rc = pmic_arb_ppid_to_apid_v5(pmic_arb, ppid);
 982        if (rc < 0)
 983                return rc;
 984
 985        apid = rc;
 986        switch (ch_type) {
 987        case PMIC_ARB_CHANNEL_OBS:
 988                offset = 0x10000 * pmic_arb->ee + 0x80 * apid;
 989                break;
 990        case PMIC_ARB_CHANNEL_RW:
 991                offset = 0x10000 * apid;
 992                break;
 993        }
 994
 995        return offset;
 996}
 997
 998static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc)
 999{
1000        return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7);
1001}
1002
1003static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc)
1004{
1005        return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7);
1006}
1007
1008static void __iomem *
1009pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1010{
1011        return pmic_arb->intr + 0x20 * m + 0x4 * n;
1012}
1013
1014static void __iomem *
1015pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1016{
1017        return pmic_arb->intr + 0x100000 + 0x1000 * m + 0x4 * n;
1018}
1019
1020static void __iomem *
1021pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1022{
1023        return pmic_arb->intr + 0x200000 + 0x1000 * m + 0x4 * n;
1024}
1025
1026static void __iomem *
1027pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb *pmic_arb, u8 m, u16 n)
1028{
1029        return pmic_arb->intr + 0x10000 * m + 0x4 * n;
1030}
1031
1032static void __iomem *
1033pmic_arb_acc_enable_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1034{
1035        return pmic_arb->intr + 0x200 + 0x4 * n;
1036}
1037
1038static void __iomem *
1039pmic_arb_acc_enable_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1040{
1041        return pmic_arb->intr + 0x1000 * n;
1042}
1043
1044static void __iomem *
1045pmic_arb_acc_enable_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1046{
1047        return pmic_arb->wr_base + 0x100 + 0x10000 * n;
1048}
1049
1050static void __iomem *
1051pmic_arb_irq_status_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1052{
1053        return pmic_arb->intr + 0x600 + 0x4 * n;
1054}
1055
1056static void __iomem *
1057pmic_arb_irq_status_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1058{
1059        return pmic_arb->intr + 0x4 + 0x1000 * n;
1060}
1061
1062static void __iomem *
1063pmic_arb_irq_status_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1064{
1065        return pmic_arb->wr_base + 0x104 + 0x10000 * n;
1066}
1067
1068static void __iomem *
1069pmic_arb_irq_clear_v1(struct spmi_pmic_arb *pmic_arb, u16 n)
1070{
1071        return pmic_arb->intr + 0xA00 + 0x4 * n;
1072}
1073
1074static void __iomem *
1075pmic_arb_irq_clear_v2(struct spmi_pmic_arb *pmic_arb, u16 n)
1076{
1077        return pmic_arb->intr + 0x8 + 0x1000 * n;
1078}
1079
1080static void __iomem *
1081pmic_arb_irq_clear_v5(struct spmi_pmic_arb *pmic_arb, u16 n)
1082{
1083        return pmic_arb->wr_base + 0x108 + 0x10000 * n;
1084}
1085
1086static u32 pmic_arb_apid_map_offset_v2(u16 n)
1087{
1088        return 0x800 + 0x4 * n;
1089}
1090
1091static u32 pmic_arb_apid_map_offset_v5(u16 n)
1092{
1093        return 0x900 + 0x4 * n;
1094}
1095
1096static const struct pmic_arb_ver_ops pmic_arb_v1 = {
1097        .ver_str                = "v1",
1098        .ppid_to_apid           = pmic_arb_ppid_to_apid_v1,
1099        .non_data_cmd           = pmic_arb_non_data_cmd_v1,
1100        .offset                 = pmic_arb_offset_v1,
1101        .fmt_cmd                = pmic_arb_fmt_cmd_v1,
1102        .owner_acc_status       = pmic_arb_owner_acc_status_v1,
1103        .acc_enable             = pmic_arb_acc_enable_v1,
1104        .irq_status             = pmic_arb_irq_status_v1,
1105        .irq_clear              = pmic_arb_irq_clear_v1,
1106        .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1107};
1108
1109static const struct pmic_arb_ver_ops pmic_arb_v2 = {
1110        .ver_str                = "v2",
1111        .ppid_to_apid           = pmic_arb_ppid_to_apid_v2,
1112        .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1113        .offset                 = pmic_arb_offset_v2,
1114        .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1115        .owner_acc_status       = pmic_arb_owner_acc_status_v2,
1116        .acc_enable             = pmic_arb_acc_enable_v2,
1117        .irq_status             = pmic_arb_irq_status_v2,
1118        .irq_clear              = pmic_arb_irq_clear_v2,
1119        .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1120};
1121
1122static const struct pmic_arb_ver_ops pmic_arb_v3 = {
1123        .ver_str                = "v3",
1124        .ppid_to_apid           = pmic_arb_ppid_to_apid_v2,
1125        .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1126        .offset                 = pmic_arb_offset_v2,
1127        .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1128        .owner_acc_status       = pmic_arb_owner_acc_status_v3,
1129        .acc_enable             = pmic_arb_acc_enable_v2,
1130        .irq_status             = pmic_arb_irq_status_v2,
1131        .irq_clear              = pmic_arb_irq_clear_v2,
1132        .apid_map_offset        = pmic_arb_apid_map_offset_v2,
1133};
1134
1135static const struct pmic_arb_ver_ops pmic_arb_v5 = {
1136        .ver_str                = "v5",
1137        .ppid_to_apid           = pmic_arb_ppid_to_apid_v5,
1138        .non_data_cmd           = pmic_arb_non_data_cmd_v2,
1139        .offset                 = pmic_arb_offset_v5,
1140        .fmt_cmd                = pmic_arb_fmt_cmd_v2,
1141        .owner_acc_status       = pmic_arb_owner_acc_status_v5,
1142        .acc_enable             = pmic_arb_acc_enable_v5,
1143        .irq_status             = pmic_arb_irq_status_v5,
1144        .irq_clear              = pmic_arb_irq_clear_v5,
1145        .apid_map_offset        = pmic_arb_apid_map_offset_v5,
1146};
1147
1148static const struct irq_domain_ops pmic_arb_irq_domain_ops = {
1149        .activate = qpnpint_irq_domain_activate,
1150        .alloc = qpnpint_irq_domain_alloc,
1151        .free = irq_domain_free_irqs_common,
1152        .translate = qpnpint_irq_domain_translate,
1153};
1154
1155static int spmi_pmic_arb_probe(struct platform_device *pdev)
1156{
1157        struct spmi_pmic_arb *pmic_arb;
1158        struct spmi_controller *ctrl;
1159        struct resource *res;
1160        void __iomem *core;
1161        u32 *mapping_table;
1162        u32 channel, ee, hw_ver;
1163        int err;
1164
1165        ctrl = spmi_controller_alloc(&pdev->dev, sizeof(*pmic_arb));
1166        if (!ctrl)
1167                return -ENOMEM;
1168
1169        pmic_arb = spmi_controller_get_drvdata(ctrl);
1170        pmic_arb->spmic = ctrl;
1171
1172        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core");
1173        core = devm_ioremap_resource(&ctrl->dev, res);
1174        if (IS_ERR(core)) {
1175                err = PTR_ERR(core);
1176                goto err_put_ctrl;
1177        }
1178
1179        pmic_arb->core_size = resource_size(res);
1180
1181        pmic_arb->ppid_to_apid = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PPID,
1182                                              sizeof(*pmic_arb->ppid_to_apid),
1183                                              GFP_KERNEL);
1184        if (!pmic_arb->ppid_to_apid) {
1185                err = -ENOMEM;
1186                goto err_put_ctrl;
1187        }
1188
1189        hw_ver = readl_relaxed(core + PMIC_ARB_VERSION);
1190
1191        if (hw_ver < PMIC_ARB_VERSION_V2_MIN) {
1192                pmic_arb->ver_ops = &pmic_arb_v1;
1193                pmic_arb->wr_base = core;
1194                pmic_arb->rd_base = core;
1195        } else {
1196                pmic_arb->core = core;
1197
1198                if (hw_ver < PMIC_ARB_VERSION_V3_MIN)
1199                        pmic_arb->ver_ops = &pmic_arb_v2;
1200                else if (hw_ver < PMIC_ARB_VERSION_V5_MIN)
1201                        pmic_arb->ver_ops = &pmic_arb_v3;
1202                else
1203                        pmic_arb->ver_ops = &pmic_arb_v5;
1204
1205                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1206                                                   "obsrvr");
1207                pmic_arb->rd_base = devm_ioremap_resource(&ctrl->dev, res);
1208                if (IS_ERR(pmic_arb->rd_base)) {
1209                        err = PTR_ERR(pmic_arb->rd_base);
1210                        goto err_put_ctrl;
1211                }
1212
1213                res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1214                                                   "chnls");
1215                pmic_arb->wr_base = devm_ioremap_resource(&ctrl->dev, res);
1216                if (IS_ERR(pmic_arb->wr_base)) {
1217                        err = PTR_ERR(pmic_arb->wr_base);
1218                        goto err_put_ctrl;
1219                }
1220        }
1221
1222        dev_info(&ctrl->dev, "PMIC arbiter version %s (0x%x)\n",
1223                 pmic_arb->ver_ops->ver_str, hw_ver);
1224
1225        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "intr");
1226        pmic_arb->intr = devm_ioremap_resource(&ctrl->dev, res);
1227        if (IS_ERR(pmic_arb->intr)) {
1228                err = PTR_ERR(pmic_arb->intr);
1229                goto err_put_ctrl;
1230        }
1231
1232        res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "cnfg");
1233        pmic_arb->cnfg = devm_ioremap_resource(&ctrl->dev, res);
1234        if (IS_ERR(pmic_arb->cnfg)) {
1235                err = PTR_ERR(pmic_arb->cnfg);
1236                goto err_put_ctrl;
1237        }
1238
1239        pmic_arb->irq = platform_get_irq_byname(pdev, "periph_irq");
1240        if (pmic_arb->irq < 0) {
1241                err = pmic_arb->irq;
1242                goto err_put_ctrl;
1243        }
1244
1245        err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel);
1246        if (err) {
1247                dev_err(&pdev->dev, "channel unspecified.\n");
1248                goto err_put_ctrl;
1249        }
1250
1251        if (channel > 5) {
1252                dev_err(&pdev->dev, "invalid channel (%u) specified.\n",
1253                        channel);
1254                err = -EINVAL;
1255                goto err_put_ctrl;
1256        }
1257
1258        pmic_arb->channel = channel;
1259
1260        err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee);
1261        if (err) {
1262                dev_err(&pdev->dev, "EE unspecified.\n");
1263                goto err_put_ctrl;
1264        }
1265
1266        if (ee > 5) {
1267                dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee);
1268                err = -EINVAL;
1269                goto err_put_ctrl;
1270        }
1271
1272        pmic_arb->ee = ee;
1273        mapping_table = devm_kcalloc(&ctrl->dev, PMIC_ARB_MAX_PERIPHS,
1274                                        sizeof(*mapping_table), GFP_KERNEL);
1275        if (!mapping_table) {
1276                err = -ENOMEM;
1277                goto err_put_ctrl;
1278        }
1279
1280        pmic_arb->mapping_table = mapping_table;
1281        /* Initialize max_apid/min_apid to the opposite bounds, during
1282         * the irq domain translation, we are sure to update these */
1283        pmic_arb->max_apid = 0;
1284        pmic_arb->min_apid = PMIC_ARB_MAX_PERIPHS - 1;
1285
1286        platform_set_drvdata(pdev, ctrl);
1287        raw_spin_lock_init(&pmic_arb->lock);
1288
1289        ctrl->cmd = pmic_arb_cmd;
1290        ctrl->read_cmd = pmic_arb_read_cmd;
1291        ctrl->write_cmd = pmic_arb_write_cmd;
1292
1293        if (hw_ver >= PMIC_ARB_VERSION_V5_MIN) {
1294                err = pmic_arb_read_apid_map_v5(pmic_arb);
1295                if (err) {
1296                        dev_err(&pdev->dev, "could not read APID->PPID mapping table, rc= %d\n",
1297                                err);
1298                        goto err_put_ctrl;
1299                }
1300        }
1301
1302        dev_dbg(&pdev->dev, "adding irq domain\n");
1303        pmic_arb->domain = irq_domain_add_tree(pdev->dev.of_node,
1304                                         &pmic_arb_irq_domain_ops, pmic_arb);
1305        if (!pmic_arb->domain) {
1306                dev_err(&pdev->dev, "unable to create irq_domain\n");
1307                err = -ENOMEM;
1308                goto err_put_ctrl;
1309        }
1310
1311        irq_set_chained_handler_and_data(pmic_arb->irq, pmic_arb_chained_irq,
1312                                        pmic_arb);
1313        err = spmi_controller_add(ctrl);
1314        if (err)
1315                goto err_domain_remove;
1316
1317        return 0;
1318
1319err_domain_remove:
1320        irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1321        irq_domain_remove(pmic_arb->domain);
1322err_put_ctrl:
1323        spmi_controller_put(ctrl);
1324        return err;
1325}
1326
1327static int spmi_pmic_arb_remove(struct platform_device *pdev)
1328{
1329        struct spmi_controller *ctrl = platform_get_drvdata(pdev);
1330        struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl);
1331        spmi_controller_remove(ctrl);
1332        irq_set_chained_handler_and_data(pmic_arb->irq, NULL, NULL);
1333        irq_domain_remove(pmic_arb->domain);
1334        spmi_controller_put(ctrl);
1335        return 0;
1336}
1337
1338static const struct of_device_id spmi_pmic_arb_match_table[] = {
1339        { .compatible = "qcom,spmi-pmic-arb", },
1340        {},
1341};
1342MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table);
1343
1344static struct platform_driver spmi_pmic_arb_driver = {
1345        .probe          = spmi_pmic_arb_probe,
1346        .remove         = spmi_pmic_arb_remove,
1347        .driver         = {
1348                .name   = "spmi_pmic_arb",
1349                .of_match_table = spmi_pmic_arb_match_table,
1350        },
1351};
1352module_platform_driver(spmi_pmic_arb_driver);
1353
1354MODULE_LICENSE("GPL v2");
1355MODULE_ALIAS("platform:spmi_pmic_arb");
1356