linux/drivers/spi/spi-s3c64xx.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2//
   3// Copyright (c) 2009 Samsung Electronics Co., Ltd.
   4//      Jaswinder Singh <jassi.brar@samsung.com>
   5
   6#include <linux/init.h>
   7#include <linux/module.h>
   8#include <linux/interrupt.h>
   9#include <linux/delay.h>
  10#include <linux/clk.h>
  11#include <linux/dma-mapping.h>
  12#include <linux/dmaengine.h>
  13#include <linux/platform_device.h>
  14#include <linux/pm_runtime.h>
  15#include <linux/spi/spi.h>
  16#include <linux/gpio.h>
  17#include <linux/of.h>
  18#include <linux/of_device.h>
  19#include <linux/of_gpio.h>
  20
  21#include <linux/platform_data/spi-s3c64xx.h>
  22
  23#define MAX_SPI_PORTS           6
  24#define S3C64XX_SPI_QUIRK_POLL          (1 << 0)
  25#define S3C64XX_SPI_QUIRK_CS_AUTO       (1 << 1)
  26#define AUTOSUSPEND_TIMEOUT     2000
  27
  28/* Registers and bit-fields */
  29
  30#define S3C64XX_SPI_CH_CFG              0x00
  31#define S3C64XX_SPI_CLK_CFG             0x04
  32#define S3C64XX_SPI_MODE_CFG            0x08
  33#define S3C64XX_SPI_CS_REG              0x0C
  34#define S3C64XX_SPI_INT_EN              0x10
  35#define S3C64XX_SPI_STATUS              0x14
  36#define S3C64XX_SPI_TX_DATA             0x18
  37#define S3C64XX_SPI_RX_DATA             0x1C
  38#define S3C64XX_SPI_PACKET_CNT          0x20
  39#define S3C64XX_SPI_PENDING_CLR         0x24
  40#define S3C64XX_SPI_SWAP_CFG            0x28
  41#define S3C64XX_SPI_FB_CLK              0x2C
  42
  43#define S3C64XX_SPI_CH_HS_EN            (1<<6)  /* High Speed Enable */
  44#define S3C64XX_SPI_CH_SW_RST           (1<<5)
  45#define S3C64XX_SPI_CH_SLAVE            (1<<4)
  46#define S3C64XX_SPI_CPOL_L              (1<<3)
  47#define S3C64XX_SPI_CPHA_B              (1<<2)
  48#define S3C64XX_SPI_CH_RXCH_ON          (1<<1)
  49#define S3C64XX_SPI_CH_TXCH_ON          (1<<0)
  50
  51#define S3C64XX_SPI_CLKSEL_SRCMSK       (3<<9)
  52#define S3C64XX_SPI_CLKSEL_SRCSHFT      9
  53#define S3C64XX_SPI_ENCLK_ENABLE        (1<<8)
  54#define S3C64XX_SPI_PSR_MASK            0xff
  55
  56#define S3C64XX_SPI_MODE_CH_TSZ_BYTE            (0<<29)
  57#define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD        (1<<29)
  58#define S3C64XX_SPI_MODE_CH_TSZ_WORD            (2<<29)
  59#define S3C64XX_SPI_MODE_CH_TSZ_MASK            (3<<29)
  60#define S3C64XX_SPI_MODE_BUS_TSZ_BYTE           (0<<17)
  61#define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD       (1<<17)
  62#define S3C64XX_SPI_MODE_BUS_TSZ_WORD           (2<<17)
  63#define S3C64XX_SPI_MODE_BUS_TSZ_MASK           (3<<17)
  64#define S3C64XX_SPI_MODE_RXDMA_ON               (1<<2)
  65#define S3C64XX_SPI_MODE_TXDMA_ON               (1<<1)
  66#define S3C64XX_SPI_MODE_4BURST                 (1<<0)
  67
  68#define S3C64XX_SPI_CS_NSC_CNT_2                (2<<4)
  69#define S3C64XX_SPI_CS_AUTO                     (1<<1)
  70#define S3C64XX_SPI_CS_SIG_INACT                (1<<0)
  71
  72#define S3C64XX_SPI_INT_TRAILING_EN             (1<<6)
  73#define S3C64XX_SPI_INT_RX_OVERRUN_EN           (1<<5)
  74#define S3C64XX_SPI_INT_RX_UNDERRUN_EN          (1<<4)
  75#define S3C64XX_SPI_INT_TX_OVERRUN_EN           (1<<3)
  76#define S3C64XX_SPI_INT_TX_UNDERRUN_EN          (1<<2)
  77#define S3C64XX_SPI_INT_RX_FIFORDY_EN           (1<<1)
  78#define S3C64XX_SPI_INT_TX_FIFORDY_EN           (1<<0)
  79
  80#define S3C64XX_SPI_ST_RX_OVERRUN_ERR           (1<<5)
  81#define S3C64XX_SPI_ST_RX_UNDERRUN_ERR          (1<<4)
  82#define S3C64XX_SPI_ST_TX_OVERRUN_ERR           (1<<3)
  83#define S3C64XX_SPI_ST_TX_UNDERRUN_ERR          (1<<2)
  84#define S3C64XX_SPI_ST_RX_FIFORDY               (1<<1)
  85#define S3C64XX_SPI_ST_TX_FIFORDY               (1<<0)
  86
  87#define S3C64XX_SPI_PACKET_CNT_EN               (1<<16)
  88
  89#define S3C64XX_SPI_PND_TX_UNDERRUN_CLR         (1<<4)
  90#define S3C64XX_SPI_PND_TX_OVERRUN_CLR          (1<<3)
  91#define S3C64XX_SPI_PND_RX_UNDERRUN_CLR         (1<<2)
  92#define S3C64XX_SPI_PND_RX_OVERRUN_CLR          (1<<1)
  93#define S3C64XX_SPI_PND_TRAILING_CLR            (1<<0)
  94
  95#define S3C64XX_SPI_SWAP_RX_HALF_WORD           (1<<7)
  96#define S3C64XX_SPI_SWAP_RX_BYTE                (1<<6)
  97#define S3C64XX_SPI_SWAP_RX_BIT                 (1<<5)
  98#define S3C64XX_SPI_SWAP_RX_EN                  (1<<4)
  99#define S3C64XX_SPI_SWAP_TX_HALF_WORD           (1<<3)
 100#define S3C64XX_SPI_SWAP_TX_BYTE                (1<<2)
 101#define S3C64XX_SPI_SWAP_TX_BIT                 (1<<1)
 102#define S3C64XX_SPI_SWAP_TX_EN                  (1<<0)
 103
 104#define S3C64XX_SPI_FBCLK_MSK                   (3<<0)
 105
 106#define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id])
 107#define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \
 108                                (1 << (i)->port_conf->tx_st_done)) ? 1 : 0)
 109#define TX_FIFO_LVL(v, i) (((v) >> 6) & FIFO_LVL_MASK(i))
 110#define RX_FIFO_LVL(v, i) (((v) >> (i)->port_conf->rx_lvl_offset) & \
 111                                        FIFO_LVL_MASK(i))
 112
 113#define S3C64XX_SPI_MAX_TRAILCNT        0x3ff
 114#define S3C64XX_SPI_TRAILCNT_OFF        19
 115
 116#define S3C64XX_SPI_TRAILCNT            S3C64XX_SPI_MAX_TRAILCNT
 117
 118#define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t)
 119#define is_polling(x)   (x->port_conf->quirks & S3C64XX_SPI_QUIRK_POLL)
 120
 121#define RXBUSY    (1<<2)
 122#define TXBUSY    (1<<3)
 123
 124struct s3c64xx_spi_dma_data {
 125        struct dma_chan *ch;
 126        dma_cookie_t cookie;
 127        enum dma_transfer_direction direction;
 128};
 129
 130/**
 131 * struct s3c64xx_spi_port_config - SPI Controller hardware info
 132 * @fifo_lvl_mask: Bit-mask for {TX|RX}_FIFO_LVL bits in SPI_STATUS register.
 133 * @rx_lvl_offset: Bit offset of RX_FIFO_LVL bits in SPI_STATUS regiter.
 134 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter.
 135 * @quirks: Bitmask of known quirks
 136 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit.
 137 * @clk_from_cmu: True, if the controller does not include a clock mux and
 138 *      prescaler unit.
 139 * @clk_ioclk: True if clock is present on this device
 140 *
 141 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but
 142 * differ in some aspects such as the size of the fifo and spi bus clock
 143 * setup. Such differences are specified to the driver using this structure
 144 * which is provided as driver data to the driver.
 145 */
 146struct s3c64xx_spi_port_config {
 147        int     fifo_lvl_mask[MAX_SPI_PORTS];
 148        int     rx_lvl_offset;
 149        int     tx_st_done;
 150        int     quirks;
 151        bool    high_speed;
 152        bool    clk_from_cmu;
 153        bool    clk_ioclk;
 154};
 155
 156/**
 157 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver.
 158 * @clk: Pointer to the spi clock.
 159 * @src_clk: Pointer to the clock used to generate SPI signals.
 160 * @ioclk: Pointer to the i/o clock between master and slave
 161 * @pdev: Pointer to device's platform device data
 162 * @master: Pointer to the SPI Protocol master.
 163 * @cntrlr_info: Platform specific data for the controller this driver manages.
 164 * @lock: Controller specific lock.
 165 * @state: Set of FLAGS to indicate status.
 166 * @sfr_start: BUS address of SPI controller regs.
 167 * @regs: Pointer to ioremap'ed controller registers.
 168 * @xfer_completion: To indicate completion of xfer task.
 169 * @cur_mode: Stores the active configuration of the controller.
 170 * @cur_bpw: Stores the active bits per word settings.
 171 * @cur_speed: Current clock speed
 172 * @rx_dma: Local receive DMA data (e.g. chan and direction)
 173 * @tx_dma: Local transmit DMA data (e.g. chan and direction)
 174 * @port_conf: Local SPI port configuartion data
 175 * @port_id: Port identification number
 176 */
 177struct s3c64xx_spi_driver_data {
 178        void __iomem                    *regs;
 179        struct clk                      *clk;
 180        struct clk                      *src_clk;
 181        struct clk                      *ioclk;
 182        struct platform_device          *pdev;
 183        struct spi_master               *master;
 184        struct s3c64xx_spi_info         *cntrlr_info;
 185        spinlock_t                      lock;
 186        unsigned long                   sfr_start;
 187        struct completion               xfer_completion;
 188        unsigned                        state;
 189        unsigned                        cur_mode, cur_bpw;
 190        unsigned                        cur_speed;
 191        struct s3c64xx_spi_dma_data     rx_dma;
 192        struct s3c64xx_spi_dma_data     tx_dma;
 193        const struct s3c64xx_spi_port_config    *port_conf;
 194        unsigned int                    port_id;
 195};
 196
 197static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd)
 198{
 199        void __iomem *regs = sdd->regs;
 200        unsigned long loops;
 201        u32 val;
 202
 203        writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 204
 205        val = readl(regs + S3C64XX_SPI_CH_CFG);
 206        val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON);
 207        writel(val, regs + S3C64XX_SPI_CH_CFG);
 208
 209        val = readl(regs + S3C64XX_SPI_CH_CFG);
 210        val |= S3C64XX_SPI_CH_SW_RST;
 211        val &= ~S3C64XX_SPI_CH_HS_EN;
 212        writel(val, regs + S3C64XX_SPI_CH_CFG);
 213
 214        /* Flush TxFIFO*/
 215        loops = msecs_to_loops(1);
 216        do {
 217                val = readl(regs + S3C64XX_SPI_STATUS);
 218        } while (TX_FIFO_LVL(val, sdd) && loops--);
 219
 220        if (loops == 0)
 221                dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n");
 222
 223        /* Flush RxFIFO*/
 224        loops = msecs_to_loops(1);
 225        do {
 226                val = readl(regs + S3C64XX_SPI_STATUS);
 227                if (RX_FIFO_LVL(val, sdd))
 228                        readl(regs + S3C64XX_SPI_RX_DATA);
 229                else
 230                        break;
 231        } while (loops--);
 232
 233        if (loops == 0)
 234                dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n");
 235
 236        val = readl(regs + S3C64XX_SPI_CH_CFG);
 237        val &= ~S3C64XX_SPI_CH_SW_RST;
 238        writel(val, regs + S3C64XX_SPI_CH_CFG);
 239
 240        val = readl(regs + S3C64XX_SPI_MODE_CFG);
 241        val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 242        writel(val, regs + S3C64XX_SPI_MODE_CFG);
 243}
 244
 245static void s3c64xx_spi_dmacb(void *data)
 246{
 247        struct s3c64xx_spi_driver_data *sdd;
 248        struct s3c64xx_spi_dma_data *dma = data;
 249        unsigned long flags;
 250
 251        if (dma->direction == DMA_DEV_TO_MEM)
 252                sdd = container_of(data,
 253                        struct s3c64xx_spi_driver_data, rx_dma);
 254        else
 255                sdd = container_of(data,
 256                        struct s3c64xx_spi_driver_data, tx_dma);
 257
 258        spin_lock_irqsave(&sdd->lock, flags);
 259
 260        if (dma->direction == DMA_DEV_TO_MEM) {
 261                sdd->state &= ~RXBUSY;
 262                if (!(sdd->state & TXBUSY))
 263                        complete(&sdd->xfer_completion);
 264        } else {
 265                sdd->state &= ~TXBUSY;
 266                if (!(sdd->state & RXBUSY))
 267                        complete(&sdd->xfer_completion);
 268        }
 269
 270        spin_unlock_irqrestore(&sdd->lock, flags);
 271}
 272
 273static int prepare_dma(struct s3c64xx_spi_dma_data *dma,
 274                        struct sg_table *sgt)
 275{
 276        struct s3c64xx_spi_driver_data *sdd;
 277        struct dma_slave_config config;
 278        struct dma_async_tx_descriptor *desc;
 279        int ret;
 280
 281        memset(&config, 0, sizeof(config));
 282
 283        if (dma->direction == DMA_DEV_TO_MEM) {
 284                sdd = container_of((void *)dma,
 285                        struct s3c64xx_spi_driver_data, rx_dma);
 286                config.direction = dma->direction;
 287                config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA;
 288                config.src_addr_width = sdd->cur_bpw / 8;
 289                config.src_maxburst = 1;
 290                dmaengine_slave_config(dma->ch, &config);
 291        } else {
 292                sdd = container_of((void *)dma,
 293                        struct s3c64xx_spi_driver_data, tx_dma);
 294                config.direction = dma->direction;
 295                config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA;
 296                config.dst_addr_width = sdd->cur_bpw / 8;
 297                config.dst_maxburst = 1;
 298                dmaengine_slave_config(dma->ch, &config);
 299        }
 300
 301        desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents,
 302                                       dma->direction, DMA_PREP_INTERRUPT);
 303        if (!desc) {
 304                dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist",
 305                        dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx");
 306                return -ENOMEM;
 307        }
 308
 309        desc->callback = s3c64xx_spi_dmacb;
 310        desc->callback_param = dma;
 311
 312        dma->cookie = dmaengine_submit(desc);
 313        ret = dma_submit_error(dma->cookie);
 314        if (ret) {
 315                dev_err(&sdd->pdev->dev, "DMA submission failed");
 316                return -EIO;
 317        }
 318
 319        dma_async_issue_pending(dma->ch);
 320        return 0;
 321}
 322
 323static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable)
 324{
 325        struct s3c64xx_spi_driver_data *sdd =
 326                                        spi_master_get_devdata(spi->master);
 327
 328        if (sdd->cntrlr_info->no_cs)
 329                return;
 330
 331        if (enable) {
 332                if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) {
 333                        writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
 334                } else {
 335                        u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG);
 336
 337                        ssel |= (S3C64XX_SPI_CS_AUTO |
 338                                                S3C64XX_SPI_CS_NSC_CNT_2);
 339                        writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG);
 340                }
 341        } else {
 342                if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 343                        writel(S3C64XX_SPI_CS_SIG_INACT,
 344                               sdd->regs + S3C64XX_SPI_CS_REG);
 345        }
 346}
 347
 348static int s3c64xx_spi_prepare_transfer(struct spi_master *spi)
 349{
 350        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(spi);
 351
 352        if (is_polling(sdd))
 353                return 0;
 354
 355        spi->dma_rx = sdd->rx_dma.ch;
 356        spi->dma_tx = sdd->tx_dma.ch;
 357
 358        return 0;
 359}
 360
 361static bool s3c64xx_spi_can_dma(struct spi_master *master,
 362                                struct spi_device *spi,
 363                                struct spi_transfer *xfer)
 364{
 365        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 366
 367        return xfer->len > (FIFO_LVL_MASK(sdd) >> 1) + 1;
 368}
 369
 370static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd,
 371                                    struct spi_transfer *xfer, int dma_mode)
 372{
 373        void __iomem *regs = sdd->regs;
 374        u32 modecfg, chcfg;
 375        int ret = 0;
 376
 377        modecfg = readl(regs + S3C64XX_SPI_MODE_CFG);
 378        modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON);
 379
 380        chcfg = readl(regs + S3C64XX_SPI_CH_CFG);
 381        chcfg &= ~S3C64XX_SPI_CH_TXCH_ON;
 382
 383        if (dma_mode) {
 384                chcfg &= ~S3C64XX_SPI_CH_RXCH_ON;
 385        } else {
 386                /* Always shift in data in FIFO, even if xfer is Tx only,
 387                 * this helps setting PCKT_CNT value for generating clocks
 388                 * as exactly needed.
 389                 */
 390                chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 391                writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 392                                        | S3C64XX_SPI_PACKET_CNT_EN,
 393                                        regs + S3C64XX_SPI_PACKET_CNT);
 394        }
 395
 396        if (xfer->tx_buf != NULL) {
 397                sdd->state |= TXBUSY;
 398                chcfg |= S3C64XX_SPI_CH_TXCH_ON;
 399                if (dma_mode) {
 400                        modecfg |= S3C64XX_SPI_MODE_TXDMA_ON;
 401                        ret = prepare_dma(&sdd->tx_dma, &xfer->tx_sg);
 402                } else {
 403                        switch (sdd->cur_bpw) {
 404                        case 32:
 405                                iowrite32_rep(regs + S3C64XX_SPI_TX_DATA,
 406                                        xfer->tx_buf, xfer->len / 4);
 407                                break;
 408                        case 16:
 409                                iowrite16_rep(regs + S3C64XX_SPI_TX_DATA,
 410                                        xfer->tx_buf, xfer->len / 2);
 411                                break;
 412                        default:
 413                                iowrite8_rep(regs + S3C64XX_SPI_TX_DATA,
 414                                        xfer->tx_buf, xfer->len);
 415                                break;
 416                        }
 417                }
 418        }
 419
 420        if (xfer->rx_buf != NULL) {
 421                sdd->state |= RXBUSY;
 422
 423                if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL
 424                                        && !(sdd->cur_mode & SPI_CPHA))
 425                        chcfg |= S3C64XX_SPI_CH_HS_EN;
 426
 427                if (dma_mode) {
 428                        modecfg |= S3C64XX_SPI_MODE_RXDMA_ON;
 429                        chcfg |= S3C64XX_SPI_CH_RXCH_ON;
 430                        writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff)
 431                                        | S3C64XX_SPI_PACKET_CNT_EN,
 432                                        regs + S3C64XX_SPI_PACKET_CNT);
 433                        ret = prepare_dma(&sdd->rx_dma, &xfer->rx_sg);
 434                }
 435        }
 436
 437        if (ret)
 438                return ret;
 439
 440        writel(modecfg, regs + S3C64XX_SPI_MODE_CFG);
 441        writel(chcfg, regs + S3C64XX_SPI_CH_CFG);
 442
 443        return 0;
 444}
 445
 446static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd,
 447                                        int timeout_ms)
 448{
 449        void __iomem *regs = sdd->regs;
 450        unsigned long val = 1;
 451        u32 status;
 452
 453        /* max fifo depth available */
 454        u32 max_fifo = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 455
 456        if (timeout_ms)
 457                val = msecs_to_loops(timeout_ms);
 458
 459        do {
 460                status = readl(regs + S3C64XX_SPI_STATUS);
 461        } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val);
 462
 463        /* return the actual received data length */
 464        return RX_FIFO_LVL(status, sdd);
 465}
 466
 467static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd,
 468                                struct spi_transfer *xfer)
 469{
 470        void __iomem *regs = sdd->regs;
 471        unsigned long val;
 472        u32 status;
 473        int ms;
 474
 475        /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 476        ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 477        ms += 30;               /* some tolerance */
 478        ms = max(ms, 100);      /* minimum timeout */
 479
 480        val = msecs_to_jiffies(ms) + 10;
 481        val = wait_for_completion_timeout(&sdd->xfer_completion, val);
 482
 483        /*
 484         * If the previous xfer was completed within timeout, then
 485         * proceed further else return -EIO.
 486         * DmaTx returns after simply writing data in the FIFO,
 487         * w/o waiting for real transmission on the bus to finish.
 488         * DmaRx returns only after Dma read data from FIFO which
 489         * needs bus transmission to finish, so we don't worry if
 490         * Xfer involved Rx(with or without Tx).
 491         */
 492        if (val && !xfer->rx_buf) {
 493                val = msecs_to_loops(10);
 494                status = readl(regs + S3C64XX_SPI_STATUS);
 495                while ((TX_FIFO_LVL(status, sdd)
 496                        || !S3C64XX_SPI_ST_TX_DONE(status, sdd))
 497                       && --val) {
 498                        cpu_relax();
 499                        status = readl(regs + S3C64XX_SPI_STATUS);
 500                }
 501
 502        }
 503
 504        /* If timed out while checking rx/tx status return error */
 505        if (!val)
 506                return -EIO;
 507
 508        return 0;
 509}
 510
 511static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd,
 512                                struct spi_transfer *xfer)
 513{
 514        void __iomem *regs = sdd->regs;
 515        unsigned long val;
 516        u32 status;
 517        int loops;
 518        u32 cpy_len;
 519        u8 *buf;
 520        int ms;
 521
 522        /* millisecs to xfer 'len' bytes @ 'cur_speed' */
 523        ms = xfer->len * 8 * 1000 / sdd->cur_speed;
 524        ms += 10; /* some tolerance */
 525
 526        val = msecs_to_loops(ms);
 527        do {
 528                status = readl(regs + S3C64XX_SPI_STATUS);
 529        } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val);
 530
 531        if (!val)
 532                return -EIO;
 533
 534        /* If it was only Tx */
 535        if (!xfer->rx_buf) {
 536                sdd->state &= ~TXBUSY;
 537                return 0;
 538        }
 539
 540        /*
 541         * If the receive length is bigger than the controller fifo
 542         * size, calculate the loops and read the fifo as many times.
 543         * loops = length / max fifo size (calculated by using the
 544         * fifo mask).
 545         * For any size less than the fifo size the below code is
 546         * executed atleast once.
 547         */
 548        loops = xfer->len / ((FIFO_LVL_MASK(sdd) >> 1) + 1);
 549        buf = xfer->rx_buf;
 550        do {
 551                /* wait for data to be received in the fifo */
 552                cpy_len = s3c64xx_spi_wait_for_timeout(sdd,
 553                                                       (loops ? ms : 0));
 554
 555                switch (sdd->cur_bpw) {
 556                case 32:
 557                        ioread32_rep(regs + S3C64XX_SPI_RX_DATA,
 558                                     buf, cpy_len / 4);
 559                        break;
 560                case 16:
 561                        ioread16_rep(regs + S3C64XX_SPI_RX_DATA,
 562                                     buf, cpy_len / 2);
 563                        break;
 564                default:
 565                        ioread8_rep(regs + S3C64XX_SPI_RX_DATA,
 566                                    buf, cpy_len);
 567                        break;
 568                }
 569
 570                buf = buf + cpy_len;
 571        } while (loops--);
 572        sdd->state &= ~RXBUSY;
 573
 574        return 0;
 575}
 576
 577static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
 578{
 579        void __iomem *regs = sdd->regs;
 580        int ret;
 581        u32 val;
 582
 583        /* Disable Clock */
 584        if (!sdd->port_conf->clk_from_cmu) {
 585                val = readl(regs + S3C64XX_SPI_CLK_CFG);
 586                val &= ~S3C64XX_SPI_ENCLK_ENABLE;
 587                writel(val, regs + S3C64XX_SPI_CLK_CFG);
 588        }
 589
 590        /* Set Polarity and Phase */
 591        val = readl(regs + S3C64XX_SPI_CH_CFG);
 592        val &= ~(S3C64XX_SPI_CH_SLAVE |
 593                        S3C64XX_SPI_CPOL_L |
 594                        S3C64XX_SPI_CPHA_B);
 595
 596        if (sdd->cur_mode & SPI_CPOL)
 597                val |= S3C64XX_SPI_CPOL_L;
 598
 599        if (sdd->cur_mode & SPI_CPHA)
 600                val |= S3C64XX_SPI_CPHA_B;
 601
 602        writel(val, regs + S3C64XX_SPI_CH_CFG);
 603
 604        /* Set Channel & DMA Mode */
 605        val = readl(regs + S3C64XX_SPI_MODE_CFG);
 606        val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK
 607                        | S3C64XX_SPI_MODE_CH_TSZ_MASK);
 608
 609        switch (sdd->cur_bpw) {
 610        case 32:
 611                val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD;
 612                val |= S3C64XX_SPI_MODE_CH_TSZ_WORD;
 613                break;
 614        case 16:
 615                val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD;
 616                val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD;
 617                break;
 618        default:
 619                val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE;
 620                val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE;
 621                break;
 622        }
 623
 624        writel(val, regs + S3C64XX_SPI_MODE_CFG);
 625
 626        if (sdd->port_conf->clk_from_cmu) {
 627                /* The src_clk clock is divided internally by 2 */
 628                ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
 629                if (ret)
 630                        return ret;
 631                sdd->cur_speed = clk_get_rate(sdd->src_clk) / 2;
 632        } else {
 633                /* Configure Clock */
 634                val = readl(regs + S3C64XX_SPI_CLK_CFG);
 635                val &= ~S3C64XX_SPI_PSR_MASK;
 636                val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1)
 637                                & S3C64XX_SPI_PSR_MASK);
 638                writel(val, regs + S3C64XX_SPI_CLK_CFG);
 639
 640                /* Enable Clock */
 641                val = readl(regs + S3C64XX_SPI_CLK_CFG);
 642                val |= S3C64XX_SPI_ENCLK_ENABLE;
 643                writel(val, regs + S3C64XX_SPI_CLK_CFG);
 644        }
 645
 646        return 0;
 647}
 648
 649#define XFER_DMAADDR_INVALID DMA_BIT_MASK(32)
 650
 651static int s3c64xx_spi_prepare_message(struct spi_master *master,
 652                                       struct spi_message *msg)
 653{
 654        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 655        struct spi_device *spi = msg->spi;
 656        struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 657
 658        /* Configure feedback delay */
 659        writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK);
 660
 661        return 0;
 662}
 663
 664static int s3c64xx_spi_transfer_one(struct spi_master *master,
 665                                    struct spi_device *spi,
 666                                    struct spi_transfer *xfer)
 667{
 668        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
 669        const unsigned int fifo_len = (FIFO_LVL_MASK(sdd) >> 1) + 1;
 670        const void *tx_buf = NULL;
 671        void *rx_buf = NULL;
 672        int target_len = 0, origin_len = 0;
 673        int use_dma = 0;
 674        int status;
 675        u32 speed;
 676        u8 bpw;
 677        unsigned long flags;
 678
 679        reinit_completion(&sdd->xfer_completion);
 680
 681        /* Only BPW and Speed may change across transfers */
 682        bpw = xfer->bits_per_word;
 683        speed = xfer->speed_hz;
 684
 685        if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) {
 686                sdd->cur_bpw = bpw;
 687                sdd->cur_speed = speed;
 688                sdd->cur_mode = spi->mode;
 689                status = s3c64xx_spi_config(sdd);
 690                if (status)
 691                        return status;
 692        }
 693
 694        if (!is_polling(sdd) && (xfer->len > fifo_len) &&
 695            sdd->rx_dma.ch && sdd->tx_dma.ch) {
 696                use_dma = 1;
 697
 698        } else if (is_polling(sdd) && xfer->len > fifo_len) {
 699                tx_buf = xfer->tx_buf;
 700                rx_buf = xfer->rx_buf;
 701                origin_len = xfer->len;
 702
 703                target_len = xfer->len;
 704                if (xfer->len > fifo_len)
 705                        xfer->len = fifo_len;
 706        }
 707
 708        do {
 709                spin_lock_irqsave(&sdd->lock, flags);
 710
 711                /* Pending only which is to be done */
 712                sdd->state &= ~RXBUSY;
 713                sdd->state &= ~TXBUSY;
 714
 715                /* Start the signals */
 716                s3c64xx_spi_set_cs(spi, true);
 717
 718                status = s3c64xx_enable_datapath(sdd, xfer, use_dma);
 719
 720                spin_unlock_irqrestore(&sdd->lock, flags);
 721
 722                if (status) {
 723                        dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status);
 724                        break;
 725                }
 726
 727                if (use_dma)
 728                        status = s3c64xx_wait_for_dma(sdd, xfer);
 729                else
 730                        status = s3c64xx_wait_for_pio(sdd, xfer);
 731
 732                if (status) {
 733                        dev_err(&spi->dev,
 734                                "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n",
 735                                xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0,
 736                                (sdd->state & RXBUSY) ? 'f' : 'p',
 737                                (sdd->state & TXBUSY) ? 'f' : 'p',
 738                                xfer->len, use_dma ? 1 : 0, status);
 739
 740                        if (use_dma) {
 741                                struct dma_tx_state s;
 742
 743                                if (xfer->tx_buf && (sdd->state & TXBUSY)) {
 744                                        dmaengine_pause(sdd->tx_dma.ch);
 745                                        dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s);
 746                                        dmaengine_terminate_all(sdd->tx_dma.ch);
 747                                        dev_err(&spi->dev, "TX residue: %d\n", s.residue);
 748
 749                                }
 750                                if (xfer->rx_buf && (sdd->state & RXBUSY)) {
 751                                        dmaengine_pause(sdd->rx_dma.ch);
 752                                        dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s);
 753                                        dmaengine_terminate_all(sdd->rx_dma.ch);
 754                                        dev_err(&spi->dev, "RX residue: %d\n", s.residue);
 755                                }
 756                        }
 757                } else {
 758                        s3c64xx_flush_fifo(sdd);
 759                }
 760                if (target_len > 0) {
 761                        target_len -= xfer->len;
 762
 763                        if (xfer->tx_buf)
 764                                xfer->tx_buf += xfer->len;
 765
 766                        if (xfer->rx_buf)
 767                                xfer->rx_buf += xfer->len;
 768
 769                        if (target_len > fifo_len)
 770                                xfer->len = fifo_len;
 771                        else
 772                                xfer->len = target_len;
 773                }
 774        } while (target_len > 0);
 775
 776        if (origin_len) {
 777                /* Restore original xfer buffers and length */
 778                xfer->tx_buf = tx_buf;
 779                xfer->rx_buf = rx_buf;
 780                xfer->len = origin_len;
 781        }
 782
 783        return status;
 784}
 785
 786static struct s3c64xx_spi_csinfo *s3c64xx_get_slave_ctrldata(
 787                                struct spi_device *spi)
 788{
 789        struct s3c64xx_spi_csinfo *cs;
 790        struct device_node *slave_np, *data_np = NULL;
 791        u32 fb_delay = 0;
 792
 793        slave_np = spi->dev.of_node;
 794        if (!slave_np) {
 795                dev_err(&spi->dev, "device node not found\n");
 796                return ERR_PTR(-EINVAL);
 797        }
 798
 799        data_np = of_get_child_by_name(slave_np, "controller-data");
 800        if (!data_np) {
 801                dev_err(&spi->dev, "child node 'controller-data' not found\n");
 802                return ERR_PTR(-EINVAL);
 803        }
 804
 805        cs = kzalloc(sizeof(*cs), GFP_KERNEL);
 806        if (!cs) {
 807                of_node_put(data_np);
 808                return ERR_PTR(-ENOMEM);
 809        }
 810
 811        of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay);
 812        cs->fb_delay = fb_delay;
 813        of_node_put(data_np);
 814        return cs;
 815}
 816
 817/*
 818 * Here we only check the validity of requested configuration
 819 * and save the configuration in a local data-structure.
 820 * The controller is actually configured only just before we
 821 * get a message to transfer.
 822 */
 823static int s3c64xx_spi_setup(struct spi_device *spi)
 824{
 825        struct s3c64xx_spi_csinfo *cs = spi->controller_data;
 826        struct s3c64xx_spi_driver_data *sdd;
 827        int err;
 828
 829        sdd = spi_master_get_devdata(spi->master);
 830        if (spi->dev.of_node) {
 831                cs = s3c64xx_get_slave_ctrldata(spi);
 832                spi->controller_data = cs;
 833        } else if (cs) {
 834                /* On non-DT platforms the SPI core will set spi->cs_gpio
 835                 * to -ENOENT. The GPIO pin used to drive the chip select
 836                 * is defined by using platform data so spi->cs_gpio value
 837                 * has to be override to have the proper GPIO pin number.
 838                 */
 839                spi->cs_gpio = cs->line;
 840        }
 841
 842        if (IS_ERR_OR_NULL(cs)) {
 843                dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select);
 844                return -ENODEV;
 845        }
 846
 847        if (!spi_get_ctldata(spi)) {
 848                if (gpio_is_valid(spi->cs_gpio)) {
 849                        err = gpio_request_one(spi->cs_gpio, GPIOF_OUT_INIT_HIGH,
 850                                               dev_name(&spi->dev));
 851                        if (err) {
 852                                dev_err(&spi->dev,
 853                                        "Failed to get /CS gpio [%d]: %d\n",
 854                                        spi->cs_gpio, err);
 855                                goto err_gpio_req;
 856                        }
 857                }
 858
 859                spi_set_ctldata(spi, cs);
 860        }
 861
 862        pm_runtime_get_sync(&sdd->pdev->dev);
 863
 864        /* Check if we can provide the requested rate */
 865        if (!sdd->port_conf->clk_from_cmu) {
 866                u32 psr, speed;
 867
 868                /* Max possible */
 869                speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1);
 870
 871                if (spi->max_speed_hz > speed)
 872                        spi->max_speed_hz = speed;
 873
 874                psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1;
 875                psr &= S3C64XX_SPI_PSR_MASK;
 876                if (psr == S3C64XX_SPI_PSR_MASK)
 877                        psr--;
 878
 879                speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 880                if (spi->max_speed_hz < speed) {
 881                        if (psr+1 < S3C64XX_SPI_PSR_MASK) {
 882                                psr++;
 883                        } else {
 884                                err = -EINVAL;
 885                                goto setup_exit;
 886                        }
 887                }
 888
 889                speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1);
 890                if (spi->max_speed_hz >= speed) {
 891                        spi->max_speed_hz = speed;
 892                } else {
 893                        dev_err(&spi->dev, "Can't set %dHz transfer speed\n",
 894                                spi->max_speed_hz);
 895                        err = -EINVAL;
 896                        goto setup_exit;
 897                }
 898        }
 899
 900        pm_runtime_mark_last_busy(&sdd->pdev->dev);
 901        pm_runtime_put_autosuspend(&sdd->pdev->dev);
 902        s3c64xx_spi_set_cs(spi, false);
 903
 904        return 0;
 905
 906setup_exit:
 907        pm_runtime_mark_last_busy(&sdd->pdev->dev);
 908        pm_runtime_put_autosuspend(&sdd->pdev->dev);
 909        /* setup() returns with device de-selected */
 910        s3c64xx_spi_set_cs(spi, false);
 911
 912        if (gpio_is_valid(spi->cs_gpio))
 913                gpio_free(spi->cs_gpio);
 914        spi_set_ctldata(spi, NULL);
 915
 916err_gpio_req:
 917        if (spi->dev.of_node)
 918                kfree(cs);
 919
 920        return err;
 921}
 922
 923static void s3c64xx_spi_cleanup(struct spi_device *spi)
 924{
 925        struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi);
 926
 927        if (gpio_is_valid(spi->cs_gpio)) {
 928                gpio_free(spi->cs_gpio);
 929                if (spi->dev.of_node)
 930                        kfree(cs);
 931                else {
 932                        /* On non-DT platforms, the SPI core sets
 933                         * spi->cs_gpio to -ENOENT and .setup()
 934                         * overrides it with the GPIO pin value
 935                         * passed using platform data.
 936                         */
 937                        spi->cs_gpio = -ENOENT;
 938                }
 939        }
 940
 941        spi_set_ctldata(spi, NULL);
 942}
 943
 944static irqreturn_t s3c64xx_spi_irq(int irq, void *data)
 945{
 946        struct s3c64xx_spi_driver_data *sdd = data;
 947        struct spi_master *spi = sdd->master;
 948        unsigned int val, clr = 0;
 949
 950        val = readl(sdd->regs + S3C64XX_SPI_STATUS);
 951
 952        if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) {
 953                clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR;
 954                dev_err(&spi->dev, "RX overrun\n");
 955        }
 956        if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) {
 957                clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR;
 958                dev_err(&spi->dev, "RX underrun\n");
 959        }
 960        if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) {
 961                clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR;
 962                dev_err(&spi->dev, "TX overrun\n");
 963        }
 964        if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) {
 965                clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
 966                dev_err(&spi->dev, "TX underrun\n");
 967        }
 968
 969        /* Clear the pending irq by setting and then clearing it */
 970        writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 971        writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR);
 972
 973        return IRQ_HANDLED;
 974}
 975
 976static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd)
 977{
 978        struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
 979        void __iomem *regs = sdd->regs;
 980        unsigned int val;
 981
 982        sdd->cur_speed = 0;
 983
 984        if (sci->no_cs)
 985                writel(0, sdd->regs + S3C64XX_SPI_CS_REG);
 986        else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO))
 987                writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG);
 988
 989        /* Disable Interrupts - we use Polling if not DMA mode */
 990        writel(0, regs + S3C64XX_SPI_INT_EN);
 991
 992        if (!sdd->port_conf->clk_from_cmu)
 993                writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT,
 994                                regs + S3C64XX_SPI_CLK_CFG);
 995        writel(0, regs + S3C64XX_SPI_MODE_CFG);
 996        writel(0, regs + S3C64XX_SPI_PACKET_CNT);
 997
 998        /* Clear any irq pending bits, should set and clear the bits */
 999        val = S3C64XX_SPI_PND_RX_OVERRUN_CLR |
1000                S3C64XX_SPI_PND_RX_UNDERRUN_CLR |
1001                S3C64XX_SPI_PND_TX_OVERRUN_CLR |
1002                S3C64XX_SPI_PND_TX_UNDERRUN_CLR;
1003        writel(val, regs + S3C64XX_SPI_PENDING_CLR);
1004        writel(0, regs + S3C64XX_SPI_PENDING_CLR);
1005
1006        writel(0, regs + S3C64XX_SPI_SWAP_CFG);
1007
1008        val = readl(regs + S3C64XX_SPI_MODE_CFG);
1009        val &= ~S3C64XX_SPI_MODE_4BURST;
1010        val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1011        val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF);
1012        writel(val, regs + S3C64XX_SPI_MODE_CFG);
1013
1014        s3c64xx_flush_fifo(sdd);
1015}
1016
1017#ifdef CONFIG_OF
1018static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1019{
1020        struct s3c64xx_spi_info *sci;
1021        u32 temp;
1022
1023        sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL);
1024        if (!sci)
1025                return ERR_PTR(-ENOMEM);
1026
1027        if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) {
1028                dev_warn(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n");
1029                sci->src_clk_nr = 0;
1030        } else {
1031                sci->src_clk_nr = temp;
1032        }
1033
1034        if (of_property_read_u32(dev->of_node, "num-cs", &temp)) {
1035                dev_warn(dev, "number of chip select lines not specified, assuming 1 chip select line\n");
1036                sci->num_cs = 1;
1037        } else {
1038                sci->num_cs = temp;
1039        }
1040
1041        sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback");
1042
1043        return sci;
1044}
1045#else
1046static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev)
1047{
1048        return dev_get_platdata(dev);
1049}
1050#endif
1051
1052static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config(
1053                                                struct platform_device *pdev)
1054{
1055#ifdef CONFIG_OF
1056        if (pdev->dev.of_node)
1057                return of_device_get_match_data(&pdev->dev);
1058#endif
1059        return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data;
1060}
1061
1062static int s3c64xx_spi_probe(struct platform_device *pdev)
1063{
1064        struct resource *mem_res;
1065        struct s3c64xx_spi_driver_data *sdd;
1066        struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev);
1067        struct spi_master *master;
1068        int ret, irq;
1069        char clk_name[16];
1070
1071        if (!sci && pdev->dev.of_node) {
1072                sci = s3c64xx_spi_parse_dt(&pdev->dev);
1073                if (IS_ERR(sci))
1074                        return PTR_ERR(sci);
1075        }
1076
1077        if (!sci) {
1078                dev_err(&pdev->dev, "platform_data missing!\n");
1079                return -ENODEV;
1080        }
1081
1082        mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1083        if (mem_res == NULL) {
1084                dev_err(&pdev->dev, "Unable to get SPI MEM resource\n");
1085                return -ENXIO;
1086        }
1087
1088        irq = platform_get_irq(pdev, 0);
1089        if (irq < 0) {
1090                dev_warn(&pdev->dev, "Failed to get IRQ: %d\n", irq);
1091                return irq;
1092        }
1093
1094        master = spi_alloc_master(&pdev->dev,
1095                                sizeof(struct s3c64xx_spi_driver_data));
1096        if (master == NULL) {
1097                dev_err(&pdev->dev, "Unable to allocate SPI Master\n");
1098                return -ENOMEM;
1099        }
1100
1101        platform_set_drvdata(pdev, master);
1102
1103        sdd = spi_master_get_devdata(master);
1104        sdd->port_conf = s3c64xx_spi_get_port_config(pdev);
1105        sdd->master = master;
1106        sdd->cntrlr_info = sci;
1107        sdd->pdev = pdev;
1108        sdd->sfr_start = mem_res->start;
1109        if (pdev->dev.of_node) {
1110                ret = of_alias_get_id(pdev->dev.of_node, "spi");
1111                if (ret < 0) {
1112                        dev_err(&pdev->dev, "failed to get alias id, errno %d\n",
1113                                ret);
1114                        goto err_deref_master;
1115                }
1116                sdd->port_id = ret;
1117        } else {
1118                sdd->port_id = pdev->id;
1119        }
1120
1121        sdd->cur_bpw = 8;
1122
1123        sdd->tx_dma.direction = DMA_MEM_TO_DEV;
1124        sdd->rx_dma.direction = DMA_DEV_TO_MEM;
1125
1126        master->dev.of_node = pdev->dev.of_node;
1127        master->bus_num = sdd->port_id;
1128        master->setup = s3c64xx_spi_setup;
1129        master->cleanup = s3c64xx_spi_cleanup;
1130        master->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer;
1131        master->prepare_message = s3c64xx_spi_prepare_message;
1132        master->transfer_one = s3c64xx_spi_transfer_one;
1133        master->num_chipselect = sci->num_cs;
1134        master->dma_alignment = 8;
1135        master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) |
1136                                        SPI_BPW_MASK(8);
1137        /* the spi->mode bits understood by this driver: */
1138        master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH;
1139        master->auto_runtime_pm = true;
1140        if (!is_polling(sdd))
1141                master->can_dma = s3c64xx_spi_can_dma;
1142
1143        sdd->regs = devm_ioremap_resource(&pdev->dev, mem_res);
1144        if (IS_ERR(sdd->regs)) {
1145                ret = PTR_ERR(sdd->regs);
1146                goto err_deref_master;
1147        }
1148
1149        if (sci->cfg_gpio && sci->cfg_gpio()) {
1150                dev_err(&pdev->dev, "Unable to config gpio\n");
1151                ret = -EBUSY;
1152                goto err_deref_master;
1153        }
1154
1155        /* Setup clocks */
1156        sdd->clk = devm_clk_get(&pdev->dev, "spi");
1157        if (IS_ERR(sdd->clk)) {
1158                dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n");
1159                ret = PTR_ERR(sdd->clk);
1160                goto err_deref_master;
1161        }
1162
1163        ret = clk_prepare_enable(sdd->clk);
1164        if (ret) {
1165                dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n");
1166                goto err_deref_master;
1167        }
1168
1169        sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr);
1170        sdd->src_clk = devm_clk_get(&pdev->dev, clk_name);
1171        if (IS_ERR(sdd->src_clk)) {
1172                dev_err(&pdev->dev,
1173                        "Unable to acquire clock '%s'\n", clk_name);
1174                ret = PTR_ERR(sdd->src_clk);
1175                goto err_disable_clk;
1176        }
1177
1178        ret = clk_prepare_enable(sdd->src_clk);
1179        if (ret) {
1180                dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name);
1181                goto err_disable_clk;
1182        }
1183
1184        if (sdd->port_conf->clk_ioclk) {
1185                sdd->ioclk = devm_clk_get(&pdev->dev, "spi_ioclk");
1186                if (IS_ERR(sdd->ioclk)) {
1187                        dev_err(&pdev->dev, "Unable to acquire 'ioclk'\n");
1188                        ret = PTR_ERR(sdd->ioclk);
1189                        goto err_disable_src_clk;
1190                }
1191
1192                ret = clk_prepare_enable(sdd->ioclk);
1193                if (ret) {
1194                        dev_err(&pdev->dev, "Couldn't enable clock 'ioclk'\n");
1195                        goto err_disable_src_clk;
1196                }
1197        }
1198
1199        if (!is_polling(sdd)) {
1200                /* Acquire DMA channels */
1201                sdd->rx_dma.ch = dma_request_chan(&pdev->dev, "rx");
1202                if (IS_ERR(sdd->rx_dma.ch)) {
1203                        dev_err(&pdev->dev, "Failed to get RX DMA channel\n");
1204                        ret = PTR_ERR(sdd->rx_dma.ch);
1205                        goto err_disable_io_clk;
1206                }
1207                sdd->tx_dma.ch = dma_request_chan(&pdev->dev, "tx");
1208                if (IS_ERR(sdd->tx_dma.ch)) {
1209                        dev_err(&pdev->dev, "Failed to get TX DMA channel\n");
1210                        ret = PTR_ERR(sdd->tx_dma.ch);
1211                        goto err_release_rx_dma;
1212                }
1213        }
1214
1215        pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT);
1216        pm_runtime_use_autosuspend(&pdev->dev);
1217        pm_runtime_set_active(&pdev->dev);
1218        pm_runtime_enable(&pdev->dev);
1219        pm_runtime_get_sync(&pdev->dev);
1220
1221        /* Setup Deufult Mode */
1222        s3c64xx_spi_hwinit(sdd);
1223
1224        spin_lock_init(&sdd->lock);
1225        init_completion(&sdd->xfer_completion);
1226
1227        ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0,
1228                                "spi-s3c64xx", sdd);
1229        if (ret != 0) {
1230                dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n",
1231                        irq, ret);
1232                goto err_pm_put;
1233        }
1234
1235        writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1236               S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1237               sdd->regs + S3C64XX_SPI_INT_EN);
1238
1239        ret = devm_spi_register_master(&pdev->dev, master);
1240        if (ret != 0) {
1241                dev_err(&pdev->dev, "cannot register SPI master: %d\n", ret);
1242                goto err_pm_put;
1243        }
1244
1245        dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Slaves attached\n",
1246                                        sdd->port_id, master->num_chipselect);
1247        dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n",
1248                                        mem_res, (FIFO_LVL_MASK(sdd) >> 1) + 1);
1249
1250        pm_runtime_mark_last_busy(&pdev->dev);
1251        pm_runtime_put_autosuspend(&pdev->dev);
1252
1253        return 0;
1254
1255err_pm_put:
1256        pm_runtime_put_noidle(&pdev->dev);
1257        pm_runtime_disable(&pdev->dev);
1258        pm_runtime_set_suspended(&pdev->dev);
1259
1260        if (!is_polling(sdd))
1261                dma_release_channel(sdd->tx_dma.ch);
1262err_release_rx_dma:
1263        if (!is_polling(sdd))
1264                dma_release_channel(sdd->rx_dma.ch);
1265err_disable_io_clk:
1266        clk_disable_unprepare(sdd->ioclk);
1267err_disable_src_clk:
1268        clk_disable_unprepare(sdd->src_clk);
1269err_disable_clk:
1270        clk_disable_unprepare(sdd->clk);
1271err_deref_master:
1272        spi_master_put(master);
1273
1274        return ret;
1275}
1276
1277static int s3c64xx_spi_remove(struct platform_device *pdev)
1278{
1279        struct spi_master *master = platform_get_drvdata(pdev);
1280        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1281
1282        pm_runtime_get_sync(&pdev->dev);
1283
1284        writel(0, sdd->regs + S3C64XX_SPI_INT_EN);
1285
1286        if (!is_polling(sdd)) {
1287                dma_release_channel(sdd->rx_dma.ch);
1288                dma_release_channel(sdd->tx_dma.ch);
1289        }
1290
1291        clk_disable_unprepare(sdd->ioclk);
1292
1293        clk_disable_unprepare(sdd->src_clk);
1294
1295        clk_disable_unprepare(sdd->clk);
1296
1297        pm_runtime_put_noidle(&pdev->dev);
1298        pm_runtime_disable(&pdev->dev);
1299        pm_runtime_set_suspended(&pdev->dev);
1300
1301        return 0;
1302}
1303
1304#ifdef CONFIG_PM_SLEEP
1305static int s3c64xx_spi_suspend(struct device *dev)
1306{
1307        struct spi_master *master = dev_get_drvdata(dev);
1308        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1309
1310        int ret = spi_master_suspend(master);
1311        if (ret)
1312                return ret;
1313
1314        ret = pm_runtime_force_suspend(dev);
1315        if (ret < 0)
1316                return ret;
1317
1318        sdd->cur_speed = 0; /* Output Clock is stopped */
1319
1320        return 0;
1321}
1322
1323static int s3c64xx_spi_resume(struct device *dev)
1324{
1325        struct spi_master *master = dev_get_drvdata(dev);
1326        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1327        struct s3c64xx_spi_info *sci = sdd->cntrlr_info;
1328        int ret;
1329
1330        if (sci->cfg_gpio)
1331                sci->cfg_gpio();
1332
1333        ret = pm_runtime_force_resume(dev);
1334        if (ret < 0)
1335                return ret;
1336
1337        return spi_master_resume(master);
1338}
1339#endif /* CONFIG_PM_SLEEP */
1340
1341#ifdef CONFIG_PM
1342static int s3c64xx_spi_runtime_suspend(struct device *dev)
1343{
1344        struct spi_master *master = dev_get_drvdata(dev);
1345        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1346
1347        clk_disable_unprepare(sdd->clk);
1348        clk_disable_unprepare(sdd->src_clk);
1349        clk_disable_unprepare(sdd->ioclk);
1350
1351        return 0;
1352}
1353
1354static int s3c64xx_spi_runtime_resume(struct device *dev)
1355{
1356        struct spi_master *master = dev_get_drvdata(dev);
1357        struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master);
1358        int ret;
1359
1360        if (sdd->port_conf->clk_ioclk) {
1361                ret = clk_prepare_enable(sdd->ioclk);
1362                if (ret != 0)
1363                        return ret;
1364        }
1365
1366        ret = clk_prepare_enable(sdd->src_clk);
1367        if (ret != 0)
1368                goto err_disable_ioclk;
1369
1370        ret = clk_prepare_enable(sdd->clk);
1371        if (ret != 0)
1372                goto err_disable_src_clk;
1373
1374        s3c64xx_spi_hwinit(sdd);
1375
1376        writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN |
1377               S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN,
1378               sdd->regs + S3C64XX_SPI_INT_EN);
1379
1380        return 0;
1381
1382err_disable_src_clk:
1383        clk_disable_unprepare(sdd->src_clk);
1384err_disable_ioclk:
1385        clk_disable_unprepare(sdd->ioclk);
1386
1387        return ret;
1388}
1389#endif /* CONFIG_PM */
1390
1391static const struct dev_pm_ops s3c64xx_spi_pm = {
1392        SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume)
1393        SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend,
1394                           s3c64xx_spi_runtime_resume, NULL)
1395};
1396
1397static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = {
1398        .fifo_lvl_mask  = { 0x7f },
1399        .rx_lvl_offset  = 13,
1400        .tx_st_done     = 21,
1401        .high_speed     = true,
1402};
1403
1404static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = {
1405        .fifo_lvl_mask  = { 0x7f, 0x7F },
1406        .rx_lvl_offset  = 13,
1407        .tx_st_done     = 21,
1408};
1409
1410static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = {
1411        .fifo_lvl_mask  = { 0x1ff, 0x7F },
1412        .rx_lvl_offset  = 15,
1413        .tx_st_done     = 25,
1414        .high_speed     = true,
1415};
1416
1417static const struct s3c64xx_spi_port_config exynos4_spi_port_config = {
1418        .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F },
1419        .rx_lvl_offset  = 15,
1420        .tx_st_done     = 25,
1421        .high_speed     = true,
1422        .clk_from_cmu   = true,
1423        .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1424};
1425
1426static const struct s3c64xx_spi_port_config exynos7_spi_port_config = {
1427        .fifo_lvl_mask  = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff},
1428        .rx_lvl_offset  = 15,
1429        .tx_st_done     = 25,
1430        .high_speed     = true,
1431        .clk_from_cmu   = true,
1432        .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1433};
1434
1435static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = {
1436        .fifo_lvl_mask  = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff},
1437        .rx_lvl_offset  = 15,
1438        .tx_st_done     = 25,
1439        .high_speed     = true,
1440        .clk_from_cmu   = true,
1441        .clk_ioclk      = true,
1442        .quirks         = S3C64XX_SPI_QUIRK_CS_AUTO,
1443};
1444
1445static const struct platform_device_id s3c64xx_spi_driver_ids[] = {
1446        {
1447                .name           = "s3c2443-spi",
1448                .driver_data    = (kernel_ulong_t)&s3c2443_spi_port_config,
1449        }, {
1450                .name           = "s3c6410-spi",
1451                .driver_data    = (kernel_ulong_t)&s3c6410_spi_port_config,
1452        },
1453        { },
1454};
1455
1456static const struct of_device_id s3c64xx_spi_dt_match[] = {
1457        { .compatible = "samsung,s3c2443-spi",
1458                        .data = (void *)&s3c2443_spi_port_config,
1459        },
1460        { .compatible = "samsung,s3c6410-spi",
1461                        .data = (void *)&s3c6410_spi_port_config,
1462        },
1463        { .compatible = "samsung,s5pv210-spi",
1464                        .data = (void *)&s5pv210_spi_port_config,
1465        },
1466        { .compatible = "samsung,exynos4210-spi",
1467                        .data = (void *)&exynos4_spi_port_config,
1468        },
1469        { .compatible = "samsung,exynos7-spi",
1470                        .data = (void *)&exynos7_spi_port_config,
1471        },
1472        { .compatible = "samsung,exynos5433-spi",
1473                        .data = (void *)&exynos5433_spi_port_config,
1474        },
1475        { },
1476};
1477MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match);
1478
1479static struct platform_driver s3c64xx_spi_driver = {
1480        .driver = {
1481                .name   = "s3c64xx-spi",
1482                .pm = &s3c64xx_spi_pm,
1483                .of_match_table = of_match_ptr(s3c64xx_spi_dt_match),
1484        },
1485        .probe = s3c64xx_spi_probe,
1486        .remove = s3c64xx_spi_remove,
1487        .id_table = s3c64xx_spi_driver_ids,
1488};
1489MODULE_ALIAS("platform:s3c64xx-spi");
1490
1491module_platform_driver(s3c64xx_spi_driver);
1492
1493MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>");
1494MODULE_DESCRIPTION("S3C64XX SPI Controller Driver");
1495MODULE_LICENSE("GPL");
1496