1
2
3
4
5
6#include "qla_def.h"
7#include "qla_gbl.h"
8
9#include <linux/delay.h>
10#include <linux/slab.h>
11#include <linux/vmalloc.h>
12
13#include "qla_devtbl.h"
14
15#ifdef CONFIG_SPARC
16#include <asm/prom.h>
17#endif
18
19#include "qla_target.h"
20
21
22
23
24static int qla2x00_isp_firmware(scsi_qla_host_t *);
25static int qla2x00_setup_chip(scsi_qla_host_t *);
26static int qla2x00_fw_ready(scsi_qla_host_t *);
27static int qla2x00_configure_hba(scsi_qla_host_t *);
28static int qla2x00_configure_loop(scsi_qla_host_t *);
29static int qla2x00_configure_local_loop(scsi_qla_host_t *);
30static int qla2x00_configure_fabric(scsi_qla_host_t *);
31static int qla2x00_find_all_fabric_devs(scsi_qla_host_t *);
32static int qla2x00_restart_isp(scsi_qla_host_t *);
33
34static struct qla_chip_state_84xx *qla84xx_get_chip(struct scsi_qla_host *);
35static int qla84xx_init_chip(scsi_qla_host_t *);
36static int qla25xx_init_queues(struct qla_hw_data *);
37static int qla24xx_post_prli_work(struct scsi_qla_host*, fc_port_t *);
38static void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha,
39 struct event_arg *ea);
40static void qla24xx_handle_prli_done_event(struct scsi_qla_host *,
41 struct event_arg *);
42static void __qla24xx_handle_gpdb_event(scsi_qla_host_t *, struct event_arg *);
43
44
45
46void
47qla2x00_sp_timeout(struct timer_list *t)
48{
49 srb_t *sp = from_timer(sp, t, u.iocb_cmd.timer);
50 struct srb_iocb *iocb;
51
52 WARN_ON(irqs_disabled());
53 iocb = &sp->u.iocb_cmd;
54 iocb->timeout(sp);
55}
56
57void qla2x00_sp_free(srb_t *sp)
58{
59 struct srb_iocb *iocb = &sp->u.iocb_cmd;
60
61 del_timer(&iocb->timer);
62 qla2x00_rel_sp(sp);
63}
64
65void qla2xxx_rel_done_warning(srb_t *sp, int res)
66{
67 WARN_ONCE(1, "Calling done() of an already freed srb %p object\n", sp);
68}
69
70void qla2xxx_rel_free_warning(srb_t *sp)
71{
72 WARN_ONCE(1, "Calling free() of an already freed srb %p object\n", sp);
73}
74
75
76
77unsigned long
78qla2x00_get_async_timeout(struct scsi_qla_host *vha)
79{
80 unsigned long tmo;
81 struct qla_hw_data *ha = vha->hw;
82
83
84 tmo = ha->r_a_tov / 10 * 2;
85 if (IS_QLAFX00(ha)) {
86 tmo = FX00_DEF_RATOV * 2;
87 } else if (!IS_FWI2_CAPABLE(ha)) {
88
89
90
91
92 tmo = ha->login_timeout;
93 }
94 return tmo;
95}
96
97static void qla24xx_abort_iocb_timeout(void *data)
98{
99 srb_t *sp = data;
100 struct srb_iocb *abt = &sp->u.iocb_cmd;
101 struct qla_qpair *qpair = sp->qpair;
102 u32 handle;
103 unsigned long flags;
104
105 if (sp->cmd_sp)
106 ql_dbg(ql_dbg_async, sp->vha, 0x507c,
107 "Abort timeout - cmd hdl=%x, cmd type=%x hdl=%x, type=%x\n",
108 sp->cmd_sp->handle, sp->cmd_sp->type,
109 sp->handle, sp->type);
110 else
111 ql_dbg(ql_dbg_async, sp->vha, 0x507c,
112 "Abort timeout 2 - hdl=%x, type=%x\n",
113 sp->handle, sp->type);
114
115 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
116 for (handle = 1; handle < qpair->req->num_outstanding_cmds; handle++) {
117 if (sp->cmd_sp && (qpair->req->outstanding_cmds[handle] ==
118 sp->cmd_sp))
119 qpair->req->outstanding_cmds[handle] = NULL;
120
121
122 if (qpair->req->outstanding_cmds[handle] == sp) {
123 qpair->req->outstanding_cmds[handle] = NULL;
124 break;
125 }
126 }
127 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
128
129 if (sp->cmd_sp)
130 sp->cmd_sp->done(sp->cmd_sp, QLA_OS_TIMER_EXPIRED);
131
132 abt->u.abt.comp_status = cpu_to_le16(CS_TIMEOUT);
133 sp->done(sp, QLA_OS_TIMER_EXPIRED);
134}
135
136static void qla24xx_abort_sp_done(srb_t *sp, int res)
137{
138 struct srb_iocb *abt = &sp->u.iocb_cmd;
139 srb_t *orig_sp = sp->cmd_sp;
140
141 if (orig_sp)
142 qla_wait_nvme_release_cmd_kref(orig_sp);
143
144 del_timer(&sp->u.iocb_cmd.timer);
145 if (sp->flags & SRB_WAKEUP_ON_COMP)
146 complete(&abt->u.abt.comp);
147 else
148 sp->free(sp);
149}
150
151int qla24xx_async_abort_cmd(srb_t *cmd_sp, bool wait)
152{
153 scsi_qla_host_t *vha = cmd_sp->vha;
154 struct srb_iocb *abt_iocb;
155 srb_t *sp;
156 int rval = QLA_FUNCTION_FAILED;
157
158 sp = qla2xxx_get_qpair_sp(cmd_sp->vha, cmd_sp->qpair, cmd_sp->fcport,
159 GFP_ATOMIC);
160 if (!sp)
161 return rval;
162
163 abt_iocb = &sp->u.iocb_cmd;
164 sp->type = SRB_ABT_CMD;
165 sp->name = "abort";
166 sp->qpair = cmd_sp->qpair;
167 sp->cmd_sp = cmd_sp;
168 if (wait)
169 sp->flags = SRB_WAKEUP_ON_COMP;
170
171 abt_iocb->timeout = qla24xx_abort_iocb_timeout;
172 init_completion(&abt_iocb->u.abt.comp);
173
174 qla2x00_init_timer(sp, 42);
175
176 abt_iocb->u.abt.cmd_hndl = cmd_sp->handle;
177 abt_iocb->u.abt.req_que_no = cpu_to_le16(cmd_sp->qpair->req->id);
178
179 sp->done = qla24xx_abort_sp_done;
180
181 ql_dbg(ql_dbg_async, vha, 0x507c,
182 "Abort command issued - hdl=%x, type=%x\n", cmd_sp->handle,
183 cmd_sp->type);
184
185 rval = qla2x00_start_sp(sp);
186 if (rval != QLA_SUCCESS) {
187 sp->free(sp);
188 return rval;
189 }
190
191 if (wait) {
192 wait_for_completion(&abt_iocb->u.abt.comp);
193 rval = abt_iocb->u.abt.comp_status == CS_COMPLETE ?
194 QLA_SUCCESS : QLA_FUNCTION_FAILED;
195 sp->free(sp);
196 }
197
198 return rval;
199}
200
201void
202qla2x00_async_iocb_timeout(void *data)
203{
204 srb_t *sp = data;
205 fc_port_t *fcport = sp->fcport;
206 struct srb_iocb *lio = &sp->u.iocb_cmd;
207 int rc, h;
208 unsigned long flags;
209
210 if (fcport) {
211 ql_dbg(ql_dbg_disc, fcport->vha, 0x2071,
212 "Async-%s timeout - hdl=%x portid=%06x %8phC.\n",
213 sp->name, sp->handle, fcport->d_id.b24, fcport->port_name);
214
215 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
216 } else {
217 pr_info("Async-%s timeout - hdl=%x.\n",
218 sp->name, sp->handle);
219 }
220
221 switch (sp->type) {
222 case SRB_LOGIN_CMD:
223 rc = qla24xx_async_abort_cmd(sp, false);
224 if (rc) {
225
226 lio->u.logio.data[0] = MBS_COMMAND_ERROR;
227 lio->u.logio.data[1] =
228 lio->u.logio.flags & SRB_LOGIN_RETRIED ?
229 QLA_LOGIO_LOGIN_RETRIED : 0;
230 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
231 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
232 h++) {
233 if (sp->qpair->req->outstanding_cmds[h] ==
234 sp) {
235 sp->qpair->req->outstanding_cmds[h] =
236 NULL;
237 break;
238 }
239 }
240 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
241 sp->done(sp, QLA_FUNCTION_TIMEOUT);
242 }
243 break;
244 case SRB_LOGOUT_CMD:
245 case SRB_CT_PTHRU_CMD:
246 case SRB_MB_IOCB:
247 case SRB_NACK_PLOGI:
248 case SRB_NACK_PRLI:
249 case SRB_NACK_LOGO:
250 case SRB_CTRL_VP:
251 default:
252 rc = qla24xx_async_abort_cmd(sp, false);
253 if (rc) {
254 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
255 for (h = 1; h < sp->qpair->req->num_outstanding_cmds;
256 h++) {
257 if (sp->qpair->req->outstanding_cmds[h] ==
258 sp) {
259 sp->qpair->req->outstanding_cmds[h] =
260 NULL;
261 break;
262 }
263 }
264 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
265 sp->done(sp, QLA_FUNCTION_TIMEOUT);
266 }
267 break;
268 }
269}
270
271static void qla2x00_async_login_sp_done(srb_t *sp, int res)
272{
273 struct scsi_qla_host *vha = sp->vha;
274 struct srb_iocb *lio = &sp->u.iocb_cmd;
275 struct event_arg ea;
276
277 ql_dbg(ql_dbg_disc, vha, 0x20dd,
278 "%s %8phC res %d \n", __func__, sp->fcport->port_name, res);
279
280 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
281
282 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
283 memset(&ea, 0, sizeof(ea));
284 ea.fcport = sp->fcport;
285 ea.data[0] = lio->u.logio.data[0];
286 ea.data[1] = lio->u.logio.data[1];
287 ea.iop[0] = lio->u.logio.iop[0];
288 ea.iop[1] = lio->u.logio.iop[1];
289 ea.sp = sp;
290 qla24xx_handle_plogi_done_event(vha, &ea);
291 }
292
293 sp->free(sp);
294}
295
296static inline bool
297fcport_is_smaller(fc_port_t *fcport)
298{
299 if (wwn_to_u64(fcport->port_name) <
300 wwn_to_u64(fcport->vha->port_name))
301 return true;
302 else
303 return false;
304}
305
306static inline bool
307fcport_is_bigger(fc_port_t *fcport)
308{
309 return !fcport_is_smaller(fcport);
310}
311
312int
313qla2x00_async_login(struct scsi_qla_host *vha, fc_port_t *fcport,
314 uint16_t *data)
315{
316 srb_t *sp;
317 struct srb_iocb *lio;
318 int rval = QLA_FUNCTION_FAILED;
319
320 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
321 fcport->loop_id == FC_NO_LOOP_ID) {
322 ql_log(ql_log_warn, vha, 0xffff,
323 "%s: %8phC - not sending command.\n",
324 __func__, fcport->port_name);
325 return rval;
326 }
327
328 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
329 if (!sp)
330 goto done;
331
332 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND);
333 fcport->flags |= FCF_ASYNC_SENT;
334 fcport->logout_completed = 0;
335
336 sp->type = SRB_LOGIN_CMD;
337 sp->name = "login";
338 sp->gen1 = fcport->rscn_gen;
339 sp->gen2 = fcport->login_gen;
340
341 lio = &sp->u.iocb_cmd;
342 lio->timeout = qla2x00_async_iocb_timeout;
343 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
344
345 sp->done = qla2x00_async_login_sp_done;
346 if (N2N_TOPO(fcport->vha->hw) && fcport_is_bigger(fcport))
347 lio->u.logio.flags |= SRB_LOGIN_PRLI_ONLY;
348 else
349 lio->u.logio.flags |= SRB_LOGIN_COND_PLOGI;
350
351 if (NVME_TARGET(vha->hw, fcport))
352 lio->u.logio.flags |= SRB_LOGIN_SKIP_PRLI;
353
354 ql_log(ql_log_warn, vha, 0x2072,
355 "Async-login - %8phC hdl=%x, loopid=%x portid=%02x%02x%02x retries=%d.\n",
356 fcport->port_name, sp->handle, fcport->loop_id,
357 fcport->d_id.b.domain, fcport->d_id.b.area, fcport->d_id.b.al_pa,
358 fcport->login_retry);
359
360 rval = qla2x00_start_sp(sp);
361 if (rval != QLA_SUCCESS) {
362 fcport->flags |= FCF_LOGIN_NEEDED;
363 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
364 goto done_free_sp;
365 }
366
367 return rval;
368
369done_free_sp:
370 sp->free(sp);
371 fcport->flags &= ~FCF_ASYNC_SENT;
372done:
373 fcport->flags &= ~FCF_ASYNC_ACTIVE;
374 return rval;
375}
376
377static void qla2x00_async_logout_sp_done(srb_t *sp, int res)
378{
379 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
380 sp->fcport->login_gen++;
381 qlt_logo_completion_handler(sp->fcport, res);
382 sp->free(sp);
383}
384
385int
386qla2x00_async_logout(struct scsi_qla_host *vha, fc_port_t *fcport)
387{
388 srb_t *sp;
389 struct srb_iocb *lio;
390 int rval = QLA_FUNCTION_FAILED;
391
392 fcport->flags |= FCF_ASYNC_SENT;
393 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
394 if (!sp)
395 goto done;
396
397 sp->type = SRB_LOGOUT_CMD;
398 sp->name = "logout";
399
400 lio = &sp->u.iocb_cmd;
401 lio->timeout = qla2x00_async_iocb_timeout;
402 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
403
404 sp->done = qla2x00_async_logout_sp_done;
405
406 ql_dbg(ql_dbg_disc, vha, 0x2070,
407 "Async-logout - hdl=%x loop-id=%x portid=%02x%02x%02x %8phC.\n",
408 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
409 fcport->d_id.b.area, fcport->d_id.b.al_pa,
410 fcport->port_name);
411
412 rval = qla2x00_start_sp(sp);
413 if (rval != QLA_SUCCESS)
414 goto done_free_sp;
415 return rval;
416
417done_free_sp:
418 sp->free(sp);
419done:
420 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
421 return rval;
422}
423
424void
425qla2x00_async_prlo_done(struct scsi_qla_host *vha, fc_port_t *fcport,
426 uint16_t *data)
427{
428 fcport->flags &= ~FCF_ASYNC_ACTIVE;
429
430 if (!fcport->tgt_session)
431 qla2x00_mark_device_lost(vha, fcport, 1);
432 qlt_logo_completion_handler(fcport, data[0]);
433}
434
435static void qla2x00_async_prlo_sp_done(srb_t *sp, int res)
436{
437 struct srb_iocb *lio = &sp->u.iocb_cmd;
438 struct scsi_qla_host *vha = sp->vha;
439
440 sp->fcport->flags &= ~FCF_ASYNC_ACTIVE;
441 if (!test_bit(UNLOADING, &vha->dpc_flags))
442 qla2x00_post_async_prlo_done_work(sp->fcport->vha, sp->fcport,
443 lio->u.logio.data);
444 sp->free(sp);
445}
446
447int
448qla2x00_async_prlo(struct scsi_qla_host *vha, fc_port_t *fcport)
449{
450 srb_t *sp;
451 struct srb_iocb *lio;
452 int rval;
453
454 rval = QLA_FUNCTION_FAILED;
455 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
456 if (!sp)
457 goto done;
458
459 sp->type = SRB_PRLO_CMD;
460 sp->name = "prlo";
461
462 lio = &sp->u.iocb_cmd;
463 lio->timeout = qla2x00_async_iocb_timeout;
464 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
465
466 sp->done = qla2x00_async_prlo_sp_done;
467
468 ql_dbg(ql_dbg_disc, vha, 0x2070,
469 "Async-prlo - hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
470 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
471 fcport->d_id.b.area, fcport->d_id.b.al_pa);
472
473 rval = qla2x00_start_sp(sp);
474 if (rval != QLA_SUCCESS)
475 goto done_free_sp;
476
477 return rval;
478
479done_free_sp:
480 sp->free(sp);
481done:
482 fcport->flags &= ~FCF_ASYNC_ACTIVE;
483 return rval;
484}
485
486static
487void qla24xx_handle_adisc_event(scsi_qla_host_t *vha, struct event_arg *ea)
488{
489 struct fc_port *fcport = ea->fcport;
490
491 ql_dbg(ql_dbg_disc, vha, 0x20d2,
492 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d lid %d\n",
493 __func__, fcport->port_name, fcport->disc_state,
494 fcport->fw_login_state, ea->rc, fcport->login_gen, ea->sp->gen2,
495 fcport->rscn_gen, ea->sp->gen1, fcport->loop_id);
496
497 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
498 ea->data[0]);
499
500 if (ea->data[0] != MBS_COMMAND_COMPLETE) {
501 ql_dbg(ql_dbg_disc, vha, 0x2066,
502 "%s %8phC: adisc fail: post delete\n",
503 __func__, ea->fcport->port_name);
504
505 fcport->deleted = 0;
506 fcport->logout_on_delete = 1;
507 qlt_schedule_sess_for_deletion(ea->fcport);
508 return;
509 }
510
511 if (ea->fcport->disc_state == DSC_DELETE_PEND)
512 return;
513
514 if (ea->sp->gen2 != ea->fcport->login_gen) {
515
516 ql_dbg(ql_dbg_disc, vha, 0x20d3,
517 "%s %8phC generation changed\n",
518 __func__, ea->fcport->port_name);
519 return;
520 } else if (ea->sp->gen1 != ea->fcport->rscn_gen) {
521 qla_rscn_replay(fcport);
522 qlt_schedule_sess_for_deletion(fcport);
523 return;
524 }
525
526 __qla24xx_handle_gpdb_event(vha, ea);
527}
528
529static int qla_post_els_plogi_work(struct scsi_qla_host *vha, fc_port_t *fcport)
530{
531 struct qla_work_evt *e;
532
533 e = qla2x00_alloc_work(vha, QLA_EVT_ELS_PLOGI);
534 if (!e)
535 return QLA_FUNCTION_FAILED;
536
537 e->u.fcport.fcport = fcport;
538 fcport->flags |= FCF_ASYNC_ACTIVE;
539 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_PEND);
540 return qla2x00_post_work(vha, e);
541}
542
543static void qla2x00_async_adisc_sp_done(srb_t *sp, int res)
544{
545 struct scsi_qla_host *vha = sp->vha;
546 struct event_arg ea;
547 struct srb_iocb *lio = &sp->u.iocb_cmd;
548
549 ql_dbg(ql_dbg_disc, vha, 0x2066,
550 "Async done-%s res %x %8phC\n",
551 sp->name, res, sp->fcport->port_name);
552
553 sp->fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
554
555 memset(&ea, 0, sizeof(ea));
556 ea.rc = res;
557 ea.data[0] = lio->u.logio.data[0];
558 ea.data[1] = lio->u.logio.data[1];
559 ea.iop[0] = lio->u.logio.iop[0];
560 ea.iop[1] = lio->u.logio.iop[1];
561 ea.fcport = sp->fcport;
562 ea.sp = sp;
563
564 qla24xx_handle_adisc_event(vha, &ea);
565
566 sp->free(sp);
567}
568
569int
570qla2x00_async_adisc(struct scsi_qla_host *vha, fc_port_t *fcport,
571 uint16_t *data)
572{
573 srb_t *sp;
574 struct srb_iocb *lio;
575 int rval = QLA_FUNCTION_FAILED;
576
577 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
578 return rval;
579
580 fcport->flags |= FCF_ASYNC_SENT;
581 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
582 if (!sp)
583 goto done;
584
585 sp->type = SRB_ADISC_CMD;
586 sp->name = "adisc";
587
588 lio = &sp->u.iocb_cmd;
589 lio->timeout = qla2x00_async_iocb_timeout;
590 sp->gen1 = fcport->rscn_gen;
591 sp->gen2 = fcport->login_gen;
592 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
593
594 sp->done = qla2x00_async_adisc_sp_done;
595 if (data[1] & QLA_LOGIO_LOGIN_RETRIED)
596 lio->u.logio.flags |= SRB_LOGIN_RETRIED;
597
598 ql_dbg(ql_dbg_disc, vha, 0x206f,
599 "Async-adisc - hdl=%x loopid=%x portid=%06x %8phC.\n",
600 sp->handle, fcport->loop_id, fcport->d_id.b24, fcport->port_name);
601
602 rval = qla2x00_start_sp(sp);
603 if (rval != QLA_SUCCESS)
604 goto done_free_sp;
605
606 return rval;
607
608done_free_sp:
609 sp->free(sp);
610done:
611 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
612 qla2x00_post_async_adisc_work(vha, fcport, data);
613 return rval;
614}
615
616static bool qla2x00_is_reserved_id(scsi_qla_host_t *vha, uint16_t loop_id)
617{
618 struct qla_hw_data *ha = vha->hw;
619
620 if (IS_FWI2_CAPABLE(ha))
621 return loop_id > NPH_LAST_HANDLE;
622
623 return (loop_id > ha->max_loop_id && loop_id < SNS_FIRST_LOOP_ID) ||
624 loop_id == MANAGEMENT_SERVER || loop_id == BROADCAST;
625}
626
627
628
629
630
631
632
633
634
635
636
637
638static int qla2x00_find_new_loop_id(scsi_qla_host_t *vha, fc_port_t *dev)
639{
640 int rval;
641 struct qla_hw_data *ha = vha->hw;
642 unsigned long flags = 0;
643
644 rval = QLA_SUCCESS;
645
646 spin_lock_irqsave(&ha->vport_slock, flags);
647
648 dev->loop_id = find_first_zero_bit(ha->loop_id_map, LOOPID_MAP_SIZE);
649 if (dev->loop_id >= LOOPID_MAP_SIZE ||
650 qla2x00_is_reserved_id(vha, dev->loop_id)) {
651 dev->loop_id = FC_NO_LOOP_ID;
652 rval = QLA_FUNCTION_FAILED;
653 } else {
654 set_bit(dev->loop_id, ha->loop_id_map);
655 }
656 spin_unlock_irqrestore(&ha->vport_slock, flags);
657
658 if (rval == QLA_SUCCESS)
659 ql_dbg(ql_dbg_disc, dev->vha, 0x2086,
660 "Assigning new loopid=%x, portid=%x.\n",
661 dev->loop_id, dev->d_id.b24);
662 else
663 ql_log(ql_log_warn, dev->vha, 0x2087,
664 "No loop_id's available, portid=%x.\n",
665 dev->d_id.b24);
666
667 return rval;
668}
669
670void qla2x00_clear_loop_id(fc_port_t *fcport)
671{
672 struct qla_hw_data *ha = fcport->vha->hw;
673
674 if (fcport->loop_id == FC_NO_LOOP_ID ||
675 qla2x00_is_reserved_id(fcport->vha, fcport->loop_id))
676 return;
677
678 clear_bit(fcport->loop_id, ha->loop_id_map);
679 fcport->loop_id = FC_NO_LOOP_ID;
680}
681
682static void qla24xx_handle_gnl_done_event(scsi_qla_host_t *vha,
683 struct event_arg *ea)
684{
685 fc_port_t *fcport, *conflict_fcport;
686 struct get_name_list_extended *e;
687 u16 i, n, found = 0, loop_id;
688 port_id_t id;
689 u64 wwn;
690 u16 data[2];
691 u8 current_login_state, nvme_cls;
692
693 fcport = ea->fcport;
694 ql_dbg(ql_dbg_disc, vha, 0xffff,
695 "%s %8phC DS %d LS rc %d %d login %d|%d rscn %d|%d lid %d\n",
696 __func__, fcport->port_name, fcport->disc_state,
697 fcport->fw_login_state, ea->rc,
698 fcport->login_gen, fcport->last_login_gen,
699 fcport->rscn_gen, fcport->last_rscn_gen, vha->loop_id);
700
701 if (fcport->disc_state == DSC_DELETE_PEND)
702 return;
703
704 if (ea->rc) {
705 if (fcport->login_retry == 0) {
706 ql_dbg(ql_dbg_disc, vha, 0x20de,
707 "GNL failed Port login retry %8phN, retry cnt=%d.\n",
708 fcport->port_name, fcport->login_retry);
709 }
710 return;
711 }
712
713 if (fcport->last_rscn_gen != fcport->rscn_gen) {
714 qla_rscn_replay(fcport);
715 qlt_schedule_sess_for_deletion(fcport);
716 return;
717 } else if (fcport->last_login_gen != fcport->login_gen) {
718 ql_dbg(ql_dbg_disc, vha, 0x20e0,
719 "%s %8phC login gen changed\n",
720 __func__, fcport->port_name);
721 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
722 return;
723 }
724
725 n = ea->data[0] / sizeof(struct get_name_list_extended);
726
727 ql_dbg(ql_dbg_disc, vha, 0x20e1,
728 "%s %d %8phC n %d %02x%02x%02x lid %d \n",
729 __func__, __LINE__, fcport->port_name, n,
730 fcport->d_id.b.domain, fcport->d_id.b.area,
731 fcport->d_id.b.al_pa, fcport->loop_id);
732
733 for (i = 0; i < n; i++) {
734 e = &vha->gnl.l[i];
735 wwn = wwn_to_u64(e->port_name);
736 id.b.domain = e->port_id[2];
737 id.b.area = e->port_id[1];
738 id.b.al_pa = e->port_id[0];
739 id.b.rsvd_1 = 0;
740
741 if (memcmp((u8 *)&wwn, fcport->port_name, WWN_SIZE))
742 continue;
743
744 if (IS_SW_RESV_ADDR(id))
745 continue;
746
747 found = 1;
748
749 loop_id = le16_to_cpu(e->nport_handle);
750 loop_id = (loop_id & 0x7fff);
751 nvme_cls = e->current_login_state >> 4;
752 current_login_state = e->current_login_state & 0xf;
753
754 if (PRLI_PHASE(nvme_cls)) {
755 current_login_state = nvme_cls;
756 fcport->fc4_type &= ~FS_FC4TYPE_FCP;
757 fcport->fc4_type |= FS_FC4TYPE_NVME;
758 } else if (PRLI_PHASE(current_login_state)) {
759 fcport->fc4_type |= FS_FC4TYPE_FCP;
760 fcport->fc4_type &= ~FS_FC4TYPE_NVME;
761 }
762
763 ql_dbg(ql_dbg_disc, vha, 0x20e2,
764 "%s found %8phC CLS [%x|%x] fc4_type %d ID[%06x|%06x] lid[%d|%d]\n",
765 __func__, fcport->port_name,
766 e->current_login_state, fcport->fw_login_state,
767 fcport->fc4_type, id.b24, fcport->d_id.b24,
768 loop_id, fcport->loop_id);
769
770 switch (fcport->disc_state) {
771 case DSC_DELETE_PEND:
772 case DSC_DELETED:
773 break;
774 default:
775 if ((id.b24 != fcport->d_id.b24 &&
776 fcport->d_id.b24 &&
777 fcport->loop_id != FC_NO_LOOP_ID) ||
778 (fcport->loop_id != FC_NO_LOOP_ID &&
779 fcport->loop_id != loop_id)) {
780 ql_dbg(ql_dbg_disc, vha, 0x20e3,
781 "%s %d %8phC post del sess\n",
782 __func__, __LINE__, fcport->port_name);
783 if (fcport->n2n_flag)
784 fcport->d_id.b24 = 0;
785 qlt_schedule_sess_for_deletion(fcport);
786 return;
787 }
788 break;
789 }
790
791 fcport->loop_id = loop_id;
792 if (fcport->n2n_flag)
793 fcport->d_id.b24 = id.b24;
794
795 wwn = wwn_to_u64(fcport->port_name);
796 qlt_find_sess_invalidate_other(vha, wwn,
797 id, loop_id, &conflict_fcport);
798
799 if (conflict_fcport) {
800
801
802
803
804
805 conflict_fcport->conflict = fcport;
806 fcport->login_pause = 1;
807 }
808
809 switch (vha->hw->current_topology) {
810 default:
811 switch (current_login_state) {
812 case DSC_LS_PRLI_COMP:
813 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
814 vha, 0x20e4, "%s %d %8phC post gpdb\n",
815 __func__, __LINE__, fcport->port_name);
816
817 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
818 fcport->port_type = FCT_INITIATOR;
819 else
820 fcport->port_type = FCT_TARGET;
821 data[0] = data[1] = 0;
822 qla2x00_post_async_adisc_work(vha, fcport,
823 data);
824 break;
825 case DSC_LS_PORT_UNAVAIL:
826 default:
827 if (fcport->loop_id == FC_NO_LOOP_ID) {
828 qla2x00_find_new_loop_id(vha, fcport);
829 fcport->fw_login_state =
830 DSC_LS_PORT_UNAVAIL;
831 }
832 ql_dbg(ql_dbg_disc, vha, 0x20e5,
833 "%s %d %8phC\n", __func__, __LINE__,
834 fcport->port_name);
835 qla24xx_fcport_handle_login(vha, fcport);
836 break;
837 }
838 break;
839 case ISP_CFG_N:
840 fcport->fw_login_state = current_login_state;
841 fcport->d_id = id;
842 switch (current_login_state) {
843 case DSC_LS_PRLI_PEND:
844
845
846
847
848
849
850 qla2x00_set_fcport_disc_state(fcport,
851 DSC_DELETED);
852 break;
853 case DSC_LS_PRLI_COMP:
854 if ((e->prli_svc_param_word_3[0] & BIT_4) == 0)
855 fcport->port_type = FCT_INITIATOR;
856 else
857 fcport->port_type = FCT_TARGET;
858
859 data[0] = data[1] = 0;
860 qla2x00_post_async_adisc_work(vha, fcport,
861 data);
862 break;
863 case DSC_LS_PLOGI_COMP:
864 if (fcport_is_bigger(fcport)) {
865
866 if (fcport->loop_id != FC_NO_LOOP_ID)
867 qla2x00_clear_loop_id(fcport);
868
869 fcport->loop_id = loop_id;
870 qla24xx_fcport_handle_login(vha,
871 fcport);
872 break;
873 }
874 fallthrough;
875 default:
876 if (fcport_is_smaller(fcport)) {
877
878 if (fcport->loop_id != FC_NO_LOOP_ID)
879 qla2x00_clear_loop_id(fcport);
880
881 fcport->loop_id = loop_id;
882 qla24xx_fcport_handle_login(vha,
883 fcport);
884 }
885 break;
886 }
887 break;
888 }
889 }
890
891 if (!found) {
892 switch (vha->hw->current_topology) {
893 case ISP_CFG_F:
894 case ISP_CFG_FL:
895 for (i = 0; i < n; i++) {
896 e = &vha->gnl.l[i];
897 id.b.domain = e->port_id[0];
898 id.b.area = e->port_id[1];
899 id.b.al_pa = e->port_id[2];
900 id.b.rsvd_1 = 0;
901 loop_id = le16_to_cpu(e->nport_handle);
902
903 if (fcport->d_id.b24 == id.b24) {
904 conflict_fcport =
905 qla2x00_find_fcport_by_wwpn(vha,
906 e->port_name, 0);
907 if (conflict_fcport) {
908 ql_dbg(ql_dbg_disc + ql_dbg_verbose,
909 vha, 0x20e5,
910 "%s %d %8phC post del sess\n",
911 __func__, __LINE__,
912 conflict_fcport->port_name);
913 qlt_schedule_sess_for_deletion
914 (conflict_fcport);
915 }
916 }
917
918
919
920
921 if (fcport->loop_id == loop_id)
922 fcport->loop_id = FC_NO_LOOP_ID;
923 }
924 qla24xx_fcport_handle_login(vha, fcport);
925 break;
926 case ISP_CFG_N:
927 qla2x00_set_fcport_disc_state(fcport, DSC_DELETED);
928 if (time_after_eq(jiffies, fcport->dm_login_expire)) {
929 if (fcport->n2n_link_reset_cnt < 2) {
930 fcport->n2n_link_reset_cnt++;
931
932
933
934
935
936 set_bit(N2N_LINK_RESET,
937 &vha->dpc_flags);
938 } else {
939 if (fcport->n2n_chip_reset < 1) {
940 ql_log(ql_log_info, vha, 0x705d,
941 "Chip reset to bring laser down");
942 set_bit(ISP_ABORT_NEEDED,
943 &vha->dpc_flags);
944 fcport->n2n_chip_reset++;
945 } else {
946 ql_log(ql_log_info, vha, 0x705d,
947 "Remote port %8ph is not coming back\n",
948 fcport->port_name);
949 fcport->scan_state = 0;
950 }
951 }
952 qla2xxx_wake_dpc(vha);
953 } else {
954
955
956
957
958 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
959 }
960 break;
961 default:
962 break;
963 }
964 }
965}
966
967static void qla24xx_async_gnl_sp_done(srb_t *sp, int res)
968{
969 struct scsi_qla_host *vha = sp->vha;
970 unsigned long flags;
971 struct fc_port *fcport = NULL, *tf;
972 u16 i, n = 0, loop_id;
973 struct event_arg ea;
974 struct get_name_list_extended *e;
975 u64 wwn;
976 struct list_head h;
977 bool found = false;
978
979 ql_dbg(ql_dbg_disc, vha, 0x20e7,
980 "Async done-%s res %x mb[1]=%x mb[2]=%x \n",
981 sp->name, res, sp->u.iocb_cmd.u.mbx.in_mb[1],
982 sp->u.iocb_cmd.u.mbx.in_mb[2]);
983
984 if (res == QLA_FUNCTION_TIMEOUT)
985 return;
986
987 sp->fcport->flags &= ~(FCF_ASYNC_SENT|FCF_ASYNC_ACTIVE);
988 memset(&ea, 0, sizeof(ea));
989 ea.sp = sp;
990 ea.rc = res;
991
992 if (sp->u.iocb_cmd.u.mbx.in_mb[1] >=
993 sizeof(struct get_name_list_extended)) {
994 n = sp->u.iocb_cmd.u.mbx.in_mb[1] /
995 sizeof(struct get_name_list_extended);
996 ea.data[0] = sp->u.iocb_cmd.u.mbx.in_mb[1];
997 }
998
999 for (i = 0; i < n; i++) {
1000 e = &vha->gnl.l[i];
1001 loop_id = le16_to_cpu(e->nport_handle);
1002
1003 loop_id = (loop_id & 0x7fff);
1004 set_bit(loop_id, vha->hw->loop_id_map);
1005 wwn = wwn_to_u64(e->port_name);
1006
1007 ql_dbg(ql_dbg_disc, vha, 0x20e8,
1008 "%s %8phC %02x:%02x:%02x CLS %x/%x lid %x \n",
1009 __func__, &wwn, e->port_id[2], e->port_id[1],
1010 e->port_id[0], e->current_login_state, e->last_login_state,
1011 (loop_id & 0x7fff));
1012 }
1013
1014 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1015
1016 INIT_LIST_HEAD(&h);
1017 fcport = tf = NULL;
1018 if (!list_empty(&vha->gnl.fcports))
1019 list_splice_init(&vha->gnl.fcports, &h);
1020 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1021
1022 list_for_each_entry_safe(fcport, tf, &h, gnl_entry) {
1023 list_del_init(&fcport->gnl_entry);
1024 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1025 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1026 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1027 ea.fcport = fcport;
1028
1029 qla24xx_handle_gnl_done_event(vha, &ea);
1030 }
1031
1032
1033 for (i = 0; i < n; i++) {
1034 port_id_t id;
1035 u64 wwnn;
1036
1037 e = &vha->gnl.l[i];
1038 wwn = wwn_to_u64(e->port_name);
1039
1040 found = false;
1041 list_for_each_entry_safe(fcport, tf, &vha->vp_fcports, list) {
1042 if (!memcmp((u8 *)&wwn, fcport->port_name,
1043 WWN_SIZE)) {
1044 found = true;
1045 break;
1046 }
1047 }
1048
1049 id.b.domain = e->port_id[2];
1050 id.b.area = e->port_id[1];
1051 id.b.al_pa = e->port_id[0];
1052 id.b.rsvd_1 = 0;
1053
1054 if (!found && wwn && !IS_SW_RESV_ADDR(id)) {
1055 ql_dbg(ql_dbg_disc, vha, 0x2065,
1056 "%s %d %8phC %06x post new sess\n",
1057 __func__, __LINE__, (u8 *)&wwn, id.b24);
1058 wwnn = wwn_to_u64(e->node_name);
1059 qla24xx_post_newsess_work(vha, &id, (u8 *)&wwn,
1060 (u8 *)&wwnn, NULL, 0);
1061 }
1062 }
1063
1064 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1065 vha->gnl.sent = 0;
1066 if (!list_empty(&vha->gnl.fcports)) {
1067
1068 list_for_each_entry_safe(fcport, tf, &vha->gnl.fcports,
1069 gnl_entry) {
1070 list_del_init(&fcport->gnl_entry);
1071 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1072 if (qla24xx_post_gnl_work(vha, fcport) == QLA_SUCCESS)
1073 break;
1074 }
1075 }
1076 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1077
1078 sp->free(sp);
1079}
1080
1081int qla24xx_async_gnl(struct scsi_qla_host *vha, fc_port_t *fcport)
1082{
1083 srb_t *sp;
1084 struct srb_iocb *mbx;
1085 int rval = QLA_FUNCTION_FAILED;
1086 unsigned long flags;
1087 u16 *mb;
1088
1089 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT))
1090 return rval;
1091
1092 ql_dbg(ql_dbg_disc, vha, 0x20d9,
1093 "Async-gnlist WWPN %8phC \n", fcport->port_name);
1094
1095 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1096 fcport->flags |= FCF_ASYNC_SENT;
1097 qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
1098 fcport->last_rscn_gen = fcport->rscn_gen;
1099 fcport->last_login_gen = fcport->login_gen;
1100
1101 list_add_tail(&fcport->gnl_entry, &vha->gnl.fcports);
1102 if (vha->gnl.sent) {
1103 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1104 return QLA_SUCCESS;
1105 }
1106 vha->gnl.sent = 1;
1107 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1108
1109 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1110 if (!sp)
1111 goto done;
1112
1113 sp->type = SRB_MB_IOCB;
1114 sp->name = "gnlist";
1115 sp->gen1 = fcport->rscn_gen;
1116 sp->gen2 = fcport->login_gen;
1117
1118 mbx = &sp->u.iocb_cmd;
1119 mbx->timeout = qla2x00_async_iocb_timeout;
1120 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha)+2);
1121
1122 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1123 mb[0] = MBC_PORT_NODE_NAME_LIST;
1124 mb[1] = BIT_2 | BIT_3;
1125 mb[2] = MSW(vha->gnl.ldma);
1126 mb[3] = LSW(vha->gnl.ldma);
1127 mb[6] = MSW(MSD(vha->gnl.ldma));
1128 mb[7] = LSW(MSD(vha->gnl.ldma));
1129 mb[8] = vha->gnl.size;
1130 mb[9] = vha->vp_idx;
1131
1132 sp->done = qla24xx_async_gnl_sp_done;
1133
1134 ql_dbg(ql_dbg_disc, vha, 0x20da,
1135 "Async-%s - OUT WWPN %8phC hndl %x\n",
1136 sp->name, fcport->port_name, sp->handle);
1137
1138 rval = qla2x00_start_sp(sp);
1139 if (rval != QLA_SUCCESS)
1140 goto done_free_sp;
1141
1142 return rval;
1143
1144done_free_sp:
1145 sp->free(sp);
1146done:
1147 fcport->flags &= ~(FCF_ASYNC_ACTIVE | FCF_ASYNC_SENT);
1148 return rval;
1149}
1150
1151int qla24xx_post_gnl_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1152{
1153 struct qla_work_evt *e;
1154
1155 e = qla2x00_alloc_work(vha, QLA_EVT_GNL);
1156 if (!e)
1157 return QLA_FUNCTION_FAILED;
1158
1159 e->u.fcport.fcport = fcport;
1160 fcport->flags |= FCF_ASYNC_ACTIVE;
1161 return qla2x00_post_work(vha, e);
1162}
1163
1164static void qla24xx_async_gpdb_sp_done(srb_t *sp, int res)
1165{
1166 struct scsi_qla_host *vha = sp->vha;
1167 struct qla_hw_data *ha = vha->hw;
1168 fc_port_t *fcport = sp->fcport;
1169 u16 *mb = sp->u.iocb_cmd.u.mbx.in_mb;
1170 struct event_arg ea;
1171
1172 ql_dbg(ql_dbg_disc, vha, 0x20db,
1173 "Async done-%s res %x, WWPN %8phC mb[1]=%x mb[2]=%x \n",
1174 sp->name, res, fcport->port_name, mb[1], mb[2]);
1175
1176 fcport->flags &= ~(FCF_ASYNC_SENT | FCF_ASYNC_ACTIVE);
1177
1178 if (res == QLA_FUNCTION_TIMEOUT)
1179 goto done;
1180
1181 memset(&ea, 0, sizeof(ea));
1182 ea.fcport = fcport;
1183 ea.sp = sp;
1184
1185 qla24xx_handle_gpdb_event(vha, &ea);
1186
1187done:
1188 dma_pool_free(ha->s_dma_pool, sp->u.iocb_cmd.u.mbx.in,
1189 sp->u.iocb_cmd.u.mbx.in_dma);
1190
1191 sp->free(sp);
1192}
1193
1194static int qla24xx_post_prli_work(struct scsi_qla_host *vha, fc_port_t *fcport)
1195{
1196 struct qla_work_evt *e;
1197
1198 if (vha->host->active_mode == MODE_TARGET)
1199 return QLA_FUNCTION_FAILED;
1200
1201 e = qla2x00_alloc_work(vha, QLA_EVT_PRLI);
1202 if (!e)
1203 return QLA_FUNCTION_FAILED;
1204
1205 e->u.fcport.fcport = fcport;
1206
1207 return qla2x00_post_work(vha, e);
1208}
1209
1210static void qla2x00_async_prli_sp_done(srb_t *sp, int res)
1211{
1212 struct scsi_qla_host *vha = sp->vha;
1213 struct srb_iocb *lio = &sp->u.iocb_cmd;
1214 struct event_arg ea;
1215
1216 ql_dbg(ql_dbg_disc, vha, 0x2129,
1217 "%s %8phC res %d \n", __func__,
1218 sp->fcport->port_name, res);
1219
1220 sp->fcport->flags &= ~FCF_ASYNC_SENT;
1221
1222 if (!test_bit(UNLOADING, &vha->dpc_flags)) {
1223 memset(&ea, 0, sizeof(ea));
1224 ea.fcport = sp->fcport;
1225 ea.data[0] = lio->u.logio.data[0];
1226 ea.data[1] = lio->u.logio.data[1];
1227 ea.iop[0] = lio->u.logio.iop[0];
1228 ea.iop[1] = lio->u.logio.iop[1];
1229 ea.sp = sp;
1230
1231 qla24xx_handle_prli_done_event(vha, &ea);
1232 }
1233
1234 sp->free(sp);
1235}
1236
1237int
1238qla24xx_async_prli(struct scsi_qla_host *vha, fc_port_t *fcport)
1239{
1240 srb_t *sp;
1241 struct srb_iocb *lio;
1242 int rval = QLA_FUNCTION_FAILED;
1243
1244 if (!vha->flags.online) {
1245 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n",
1246 __func__, __LINE__, fcport->port_name);
1247 return rval;
1248 }
1249
1250 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND ||
1251 fcport->fw_login_state == DSC_LS_PRLI_PEND) &&
1252 qla_dual_mode_enabled(vha)) {
1253 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s %d %8phC exit\n",
1254 __func__, __LINE__, fcport->port_name);
1255 return rval;
1256 }
1257
1258 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1259 if (!sp)
1260 return rval;
1261
1262 fcport->flags |= FCF_ASYNC_SENT;
1263 fcport->logout_completed = 0;
1264
1265 sp->type = SRB_PRLI_CMD;
1266 sp->name = "prli";
1267
1268 lio = &sp->u.iocb_cmd;
1269 lio->timeout = qla2x00_async_iocb_timeout;
1270 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1271
1272 sp->done = qla2x00_async_prli_sp_done;
1273 lio->u.logio.flags = 0;
1274
1275 if (NVME_TARGET(vha->hw, fcport))
1276 lio->u.logio.flags |= SRB_LOGIN_NVME_PRLI;
1277
1278 ql_dbg(ql_dbg_disc, vha, 0x211b,
1279 "Async-prli - %8phC hdl=%x, loopid=%x portid=%06x retries=%d fc4type %x priority %x %s.\n",
1280 fcport->port_name, sp->handle, fcport->loop_id, fcport->d_id.b24,
1281 fcport->login_retry, fcport->fc4_type, vha->hw->fc4_type_priority,
1282 NVME_TARGET(vha->hw, fcport) ? "nvme" : "fcp");
1283
1284 rval = qla2x00_start_sp(sp);
1285 if (rval != QLA_SUCCESS) {
1286 fcport->flags |= FCF_LOGIN_NEEDED;
1287 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1288 goto done_free_sp;
1289 }
1290
1291 return rval;
1292
1293done_free_sp:
1294 sp->free(sp);
1295 fcport->flags &= ~FCF_ASYNC_SENT;
1296 return rval;
1297}
1298
1299int qla24xx_post_gpdb_work(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1300{
1301 struct qla_work_evt *e;
1302
1303 e = qla2x00_alloc_work(vha, QLA_EVT_GPDB);
1304 if (!e)
1305 return QLA_FUNCTION_FAILED;
1306
1307 e->u.fcport.fcport = fcport;
1308 e->u.fcport.opt = opt;
1309 fcport->flags |= FCF_ASYNC_ACTIVE;
1310 return qla2x00_post_work(vha, e);
1311}
1312
1313int qla24xx_async_gpdb(struct scsi_qla_host *vha, fc_port_t *fcport, u8 opt)
1314{
1315 srb_t *sp;
1316 struct srb_iocb *mbx;
1317 int rval = QLA_FUNCTION_FAILED;
1318 u16 *mb;
1319 dma_addr_t pd_dma;
1320 struct port_database_24xx *pd;
1321 struct qla_hw_data *ha = vha->hw;
1322
1323 if (!vha->flags.online || (fcport->flags & FCF_ASYNC_SENT) ||
1324 fcport->loop_id == FC_NO_LOOP_ID) {
1325 ql_log(ql_log_warn, vha, 0xffff,
1326 "%s: %8phC - not sending command.\n",
1327 __func__, fcport->port_name);
1328 return rval;
1329 }
1330
1331 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1332 if (!sp)
1333 goto done;
1334
1335 qla2x00_set_fcport_disc_state(fcport, DSC_GPDB);
1336
1337 fcport->flags |= FCF_ASYNC_SENT;
1338 sp->type = SRB_MB_IOCB;
1339 sp->name = "gpdb";
1340 sp->gen1 = fcport->rscn_gen;
1341 sp->gen2 = fcport->login_gen;
1342
1343 mbx = &sp->u.iocb_cmd;
1344 mbx->timeout = qla2x00_async_iocb_timeout;
1345 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha) + 2);
1346
1347 pd = dma_pool_zalloc(ha->s_dma_pool, GFP_KERNEL, &pd_dma);
1348 if (pd == NULL) {
1349 ql_log(ql_log_warn, vha, 0xd043,
1350 "Failed to allocate port database structure.\n");
1351 goto done_free_sp;
1352 }
1353
1354 mb = sp->u.iocb_cmd.u.mbx.out_mb;
1355 mb[0] = MBC_GET_PORT_DATABASE;
1356 mb[1] = fcport->loop_id;
1357 mb[2] = MSW(pd_dma);
1358 mb[3] = LSW(pd_dma);
1359 mb[6] = MSW(MSD(pd_dma));
1360 mb[7] = LSW(MSD(pd_dma));
1361 mb[9] = vha->vp_idx;
1362 mb[10] = opt;
1363
1364 mbx->u.mbx.in = pd;
1365 mbx->u.mbx.in_dma = pd_dma;
1366
1367 sp->done = qla24xx_async_gpdb_sp_done;
1368
1369 ql_dbg(ql_dbg_disc, vha, 0x20dc,
1370 "Async-%s %8phC hndl %x opt %x\n",
1371 sp->name, fcport->port_name, sp->handle, opt);
1372
1373 rval = qla2x00_start_sp(sp);
1374 if (rval != QLA_SUCCESS)
1375 goto done_free_sp;
1376 return rval;
1377
1378done_free_sp:
1379 if (pd)
1380 dma_pool_free(ha->s_dma_pool, pd, pd_dma);
1381
1382 sp->free(sp);
1383 fcport->flags &= ~FCF_ASYNC_SENT;
1384done:
1385 fcport->flags &= ~FCF_ASYNC_ACTIVE;
1386 qla24xx_post_gpdb_work(vha, fcport, opt);
1387 return rval;
1388}
1389
1390static
1391void __qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1392{
1393 unsigned long flags;
1394
1395 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1396 ea->fcport->login_gen++;
1397 ea->fcport->deleted = 0;
1398 ea->fcport->logout_on_delete = 1;
1399
1400 if (!ea->fcport->login_succ && !IS_SW_RESV_ADDR(ea->fcport->d_id)) {
1401 vha->fcport_count++;
1402 ea->fcport->login_succ = 1;
1403
1404 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1405 qla24xx_sched_upd_fcport(ea->fcport);
1406 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
1407 } else if (ea->fcport->login_succ) {
1408
1409
1410
1411
1412
1413 ql_dbg(ql_dbg_disc, vha, 0x20d6,
1414 "%s %d %8phC session revalidate success\n",
1415 __func__, __LINE__, ea->fcport->port_name);
1416 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_COMPLETE);
1417 }
1418 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
1419}
1420
1421static
1422void qla24xx_handle_gpdb_event(scsi_qla_host_t *vha, struct event_arg *ea)
1423{
1424 fc_port_t *fcport = ea->fcport;
1425 struct port_database_24xx *pd;
1426 struct srb *sp = ea->sp;
1427 uint8_t ls;
1428
1429 pd = (struct port_database_24xx *)sp->u.iocb_cmd.u.mbx.in;
1430
1431 fcport->flags &= ~FCF_ASYNC_SENT;
1432
1433 ql_dbg(ql_dbg_disc, vha, 0x20d2,
1434 "%s %8phC DS %d LS %d fc4_type %x rc %d\n", __func__,
1435 fcport->port_name, fcport->disc_state, pd->current_login_state,
1436 fcport->fc4_type, ea->rc);
1437
1438 if (fcport->disc_state == DSC_DELETE_PEND)
1439 return;
1440
1441 if (NVME_TARGET(vha->hw, fcport))
1442 ls = pd->current_login_state >> 4;
1443 else
1444 ls = pd->current_login_state & 0xf;
1445
1446 if (ea->sp->gen2 != fcport->login_gen) {
1447
1448
1449 ql_dbg(ql_dbg_disc, vha, 0x20d3,
1450 "%s %8phC generation changed\n",
1451 __func__, fcport->port_name);
1452 return;
1453 } else if (ea->sp->gen1 != fcport->rscn_gen) {
1454 qla_rscn_replay(fcport);
1455 qlt_schedule_sess_for_deletion(fcport);
1456 return;
1457 }
1458
1459 switch (ls) {
1460 case PDS_PRLI_COMPLETE:
1461 __qla24xx_parse_gpdb(vha, fcport, pd);
1462 break;
1463 case PDS_PLOGI_PENDING:
1464 case PDS_PLOGI_COMPLETE:
1465 case PDS_PRLI_PENDING:
1466 case PDS_PRLI2_PENDING:
1467
1468 if (qla_dual_mode_enabled(vha) ||
1469 qla_ini_mode_enabled(vha)) {
1470 qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
1471 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1472 }
1473 return;
1474 case PDS_LOGO_PENDING:
1475 case PDS_PORT_UNAVAILABLE:
1476 default:
1477 ql_dbg(ql_dbg_disc, vha, 0x20d5, "%s %d %8phC post del sess\n",
1478 __func__, __LINE__, fcport->port_name);
1479 qlt_schedule_sess_for_deletion(fcport);
1480 return;
1481 }
1482 __qla24xx_handle_gpdb_event(vha, ea);
1483}
1484
1485static void qla_chk_n2n_b4_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1486{
1487 u8 login = 0;
1488 int rc;
1489
1490 if (qla_tgt_mode_enabled(vha))
1491 return;
1492
1493 if (qla_dual_mode_enabled(vha)) {
1494 if (N2N_TOPO(vha->hw)) {
1495 u64 mywwn, wwn;
1496
1497 mywwn = wwn_to_u64(vha->port_name);
1498 wwn = wwn_to_u64(fcport->port_name);
1499 if (mywwn > wwn)
1500 login = 1;
1501 else if ((fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1502 && time_after_eq(jiffies,
1503 fcport->plogi_nack_done_deadline))
1504 login = 1;
1505 } else {
1506 login = 1;
1507 }
1508 } else {
1509
1510 login = 1;
1511 }
1512
1513 if (login && fcport->login_retry) {
1514 fcport->login_retry--;
1515 if (fcport->loop_id == FC_NO_LOOP_ID) {
1516 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
1517 rc = qla2x00_find_new_loop_id(vha, fcport);
1518 if (rc) {
1519 ql_dbg(ql_dbg_disc, vha, 0x20e6,
1520 "%s %d %8phC post del sess - out of loopid\n",
1521 __func__, __LINE__, fcport->port_name);
1522 fcport->scan_state = 0;
1523 qlt_schedule_sess_for_deletion(fcport);
1524 return;
1525 }
1526 }
1527 ql_dbg(ql_dbg_disc, vha, 0x20bf,
1528 "%s %d %8phC post login\n",
1529 __func__, __LINE__, fcport->port_name);
1530 qla2x00_post_async_login_work(vha, fcport, NULL);
1531 }
1532}
1533
1534int qla24xx_fcport_handle_login(struct scsi_qla_host *vha, fc_port_t *fcport)
1535{
1536 u16 data[2];
1537 u64 wwn;
1538 u16 sec;
1539
1540 ql_dbg(ql_dbg_disc, vha, 0x20d8,
1541 "%s %8phC DS %d LS %d P %d fl %x confl %p rscn %d|%d login %d lid %d scan %d\n",
1542 __func__, fcport->port_name, fcport->disc_state,
1543 fcport->fw_login_state, fcport->login_pause, fcport->flags,
1544 fcport->conflict, fcport->last_rscn_gen, fcport->rscn_gen,
1545 fcport->login_gen, fcport->loop_id, fcport->scan_state);
1546
1547 if (fcport->scan_state != QLA_FCPORT_FOUND)
1548 return 0;
1549
1550 if ((fcport->loop_id != FC_NO_LOOP_ID) &&
1551 qla_dual_mode_enabled(vha) &&
1552 ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
1553 (fcport->fw_login_state == DSC_LS_PRLI_PEND)))
1554 return 0;
1555
1556 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP &&
1557 !N2N_TOPO(vha->hw)) {
1558 if (time_before_eq(jiffies, fcport->plogi_nack_done_deadline)) {
1559 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1560 return 0;
1561 }
1562 }
1563
1564
1565 if (vha->host->active_mode == MODE_TARGET && !N2N_TOPO(vha->hw))
1566 return 0;
1567
1568 if (fcport->flags & FCF_ASYNC_SENT) {
1569 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1570 return 0;
1571 }
1572
1573 switch (fcport->disc_state) {
1574 case DSC_DELETED:
1575 wwn = wwn_to_u64(fcport->node_name);
1576 switch (vha->hw->current_topology) {
1577 case ISP_CFG_N:
1578 if (fcport_is_smaller(fcport)) {
1579
1580 if (fcport->login_retry) {
1581 if (fcport->loop_id == FC_NO_LOOP_ID) {
1582 qla2x00_find_new_loop_id(vha,
1583 fcport);
1584 fcport->fw_login_state =
1585 DSC_LS_PORT_UNAVAIL;
1586 }
1587 fcport->login_retry--;
1588 qla_post_els_plogi_work(vha, fcport);
1589 } else {
1590 ql_log(ql_log_info, vha, 0x705d,
1591 "Unable to reach remote port %8phC",
1592 fcport->port_name);
1593 }
1594 } else {
1595 qla24xx_post_gnl_work(vha, fcport);
1596 }
1597 break;
1598 default:
1599 if (wwn == 0) {
1600 ql_dbg(ql_dbg_disc, vha, 0xffff,
1601 "%s %d %8phC post GNNID\n",
1602 __func__, __LINE__, fcport->port_name);
1603 qla24xx_post_gnnid_work(vha, fcport);
1604 } else if (fcport->loop_id == FC_NO_LOOP_ID) {
1605 ql_dbg(ql_dbg_disc, vha, 0x20bd,
1606 "%s %d %8phC post gnl\n",
1607 __func__, __LINE__, fcport->port_name);
1608 qla24xx_post_gnl_work(vha, fcport);
1609 } else {
1610 qla_chk_n2n_b4_login(vha, fcport);
1611 }
1612 break;
1613 }
1614 break;
1615
1616 case DSC_GNL:
1617 switch (vha->hw->current_topology) {
1618 case ISP_CFG_N:
1619 if ((fcport->current_login_state & 0xf) == 0x6) {
1620 ql_dbg(ql_dbg_disc, vha, 0x2118,
1621 "%s %d %8phC post GPDB work\n",
1622 __func__, __LINE__, fcport->port_name);
1623 fcport->chip_reset =
1624 vha->hw->base_qpair->chip_reset;
1625 qla24xx_post_gpdb_work(vha, fcport, 0);
1626 } else {
1627 ql_dbg(ql_dbg_disc, vha, 0x2118,
1628 "%s %d %8phC post %s PRLI\n",
1629 __func__, __LINE__, fcport->port_name,
1630 NVME_TARGET(vha->hw, fcport) ? "NVME" :
1631 "FC");
1632 qla24xx_post_prli_work(vha, fcport);
1633 }
1634 break;
1635 default:
1636 if (fcport->login_pause) {
1637 ql_dbg(ql_dbg_disc, vha, 0x20d8,
1638 "%s %d %8phC exit\n",
1639 __func__, __LINE__,
1640 fcport->port_name);
1641 fcport->last_rscn_gen = fcport->rscn_gen;
1642 fcport->last_login_gen = fcport->login_gen;
1643 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1644 break;
1645 }
1646 qla_chk_n2n_b4_login(vha, fcport);
1647 break;
1648 }
1649 break;
1650
1651 case DSC_LOGIN_FAILED:
1652 if (N2N_TOPO(vha->hw))
1653 qla_chk_n2n_b4_login(vha, fcport);
1654 else
1655 qlt_schedule_sess_for_deletion(fcport);
1656 break;
1657
1658 case DSC_LOGIN_COMPLETE:
1659
1660 data[0] = data[1] = 0;
1661 qla2x00_post_async_adisc_work(vha, fcport, data);
1662 break;
1663
1664 case DSC_LOGIN_PEND:
1665 if (fcport->fw_login_state == DSC_LS_PLOGI_COMP)
1666 qla24xx_post_prli_work(vha, fcport);
1667 break;
1668
1669 case DSC_UPD_FCPORT:
1670 sec = jiffies_to_msecs(jiffies -
1671 fcport->jiffies_at_registration)/1000;
1672 if (fcport->sec_since_registration < sec && sec &&
1673 !(sec % 60)) {
1674 fcport->sec_since_registration = sec;
1675 ql_dbg(ql_dbg_disc, fcport->vha, 0xffff,
1676 "%s %8phC - Slow Rport registration(%d Sec)\n",
1677 __func__, fcport->port_name, sec);
1678 }
1679
1680 if (fcport->next_disc_state != DSC_DELETE_PEND)
1681 fcport->next_disc_state = DSC_ADISC;
1682 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1683 break;
1684
1685 default:
1686 break;
1687 }
1688
1689 return 0;
1690}
1691
1692int qla24xx_post_newsess_work(struct scsi_qla_host *vha, port_id_t *id,
1693 u8 *port_name, u8 *node_name, void *pla, u8 fc4_type)
1694{
1695 struct qla_work_evt *e;
1696
1697 e = qla2x00_alloc_work(vha, QLA_EVT_NEW_SESS);
1698 if (!e)
1699 return QLA_FUNCTION_FAILED;
1700
1701 e->u.new_sess.id = *id;
1702 e->u.new_sess.pla = pla;
1703 e->u.new_sess.fc4_type = fc4_type;
1704 memcpy(e->u.new_sess.port_name, port_name, WWN_SIZE);
1705 if (node_name)
1706 memcpy(e->u.new_sess.node_name, node_name, WWN_SIZE);
1707
1708 return qla2x00_post_work(vha, e);
1709}
1710
1711void qla2x00_handle_rscn(scsi_qla_host_t *vha, struct event_arg *ea)
1712{
1713 fc_port_t *fcport;
1714 unsigned long flags;
1715
1716 fcport = qla2x00_find_fcport_by_nportid(vha, &ea->id, 1);
1717 if (fcport) {
1718 fcport->scan_needed = 1;
1719 fcport->rscn_gen++;
1720 }
1721
1722 spin_lock_irqsave(&vha->work_lock, flags);
1723 if (vha->scan.scan_flags == 0) {
1724 ql_dbg(ql_dbg_disc, vha, 0xffff, "%s: schedule\n", __func__);
1725 vha->scan.scan_flags |= SF_QUEUED;
1726 schedule_delayed_work(&vha->scan.scan_work, 5);
1727 }
1728 spin_unlock_irqrestore(&vha->work_lock, flags);
1729}
1730
1731void qla24xx_handle_relogin_event(scsi_qla_host_t *vha,
1732 struct event_arg *ea)
1733{
1734 fc_port_t *fcport = ea->fcport;
1735
1736 if (test_bit(UNLOADING, &vha->dpc_flags))
1737 return;
1738
1739 ql_dbg(ql_dbg_disc, vha, 0x2102,
1740 "%s %8phC DS %d LS %d P %d del %d cnfl %p rscn %d|%d login %d|%d fl %x\n",
1741 __func__, fcport->port_name, fcport->disc_state,
1742 fcport->fw_login_state, fcport->login_pause,
1743 fcport->deleted, fcport->conflict,
1744 fcport->last_rscn_gen, fcport->rscn_gen,
1745 fcport->last_login_gen, fcport->login_gen,
1746 fcport->flags);
1747
1748 if (fcport->last_rscn_gen != fcport->rscn_gen) {
1749 ql_dbg(ql_dbg_disc, vha, 0x20e9, "%s %d %8phC post gnl\n",
1750 __func__, __LINE__, fcport->port_name);
1751 qla24xx_post_gnl_work(vha, fcport);
1752 return;
1753 }
1754
1755 qla24xx_fcport_handle_login(vha, fcport);
1756}
1757
1758void qla_handle_els_plogi_done(scsi_qla_host_t *vha,
1759 struct event_arg *ea)
1760{
1761
1762 if (vha->host->active_mode == MODE_TARGET)
1763 return;
1764
1765 ql_dbg(ql_dbg_disc, vha, 0x2118,
1766 "%s %d %8phC post PRLI\n",
1767 __func__, __LINE__, ea->fcport->port_name);
1768 qla24xx_post_prli_work(vha, ea->fcport);
1769}
1770
1771
1772
1773
1774
1775void qla_rscn_replay(fc_port_t *fcport)
1776{
1777 struct event_arg ea;
1778
1779 switch (fcport->disc_state) {
1780 case DSC_DELETE_PEND:
1781 return;
1782 default:
1783 break;
1784 }
1785
1786 if (fcport->scan_needed) {
1787 memset(&ea, 0, sizeof(ea));
1788 ea.id = fcport->d_id;
1789 ea.id.b.rsvd_1 = RSCN_PORT_ADDR;
1790 qla2x00_handle_rscn(fcport->vha, &ea);
1791 }
1792}
1793
1794static void
1795qla2x00_tmf_iocb_timeout(void *data)
1796{
1797 srb_t *sp = data;
1798 struct srb_iocb *tmf = &sp->u.iocb_cmd;
1799 int rc, h;
1800 unsigned long flags;
1801
1802 rc = qla24xx_async_abort_cmd(sp, false);
1803 if (rc) {
1804 spin_lock_irqsave(sp->qpair->qp_lock_ptr, flags);
1805 for (h = 1; h < sp->qpair->req->num_outstanding_cmds; h++) {
1806 if (sp->qpair->req->outstanding_cmds[h] == sp) {
1807 sp->qpair->req->outstanding_cmds[h] = NULL;
1808 break;
1809 }
1810 }
1811 spin_unlock_irqrestore(sp->qpair->qp_lock_ptr, flags);
1812 tmf->u.tmf.comp_status = cpu_to_le16(CS_TIMEOUT);
1813 tmf->u.tmf.data = QLA_FUNCTION_FAILED;
1814 complete(&tmf->u.tmf.comp);
1815 }
1816}
1817
1818static void qla2x00_tmf_sp_done(srb_t *sp, int res)
1819{
1820 struct srb_iocb *tmf = &sp->u.iocb_cmd;
1821
1822 complete(&tmf->u.tmf.comp);
1823}
1824
1825int
1826qla2x00_async_tm_cmd(fc_port_t *fcport, uint32_t flags, uint32_t lun,
1827 uint32_t tag)
1828{
1829 struct scsi_qla_host *vha = fcport->vha;
1830 struct srb_iocb *tm_iocb;
1831 srb_t *sp;
1832 int rval = QLA_FUNCTION_FAILED;
1833
1834 sp = qla2x00_get_sp(vha, fcport, GFP_KERNEL);
1835 if (!sp)
1836 goto done;
1837
1838 tm_iocb = &sp->u.iocb_cmd;
1839 sp->type = SRB_TM_CMD;
1840 sp->name = "tmf";
1841
1842 tm_iocb->timeout = qla2x00_tmf_iocb_timeout;
1843 init_completion(&tm_iocb->u.tmf.comp);
1844 qla2x00_init_timer(sp, qla2x00_get_async_timeout(vha));
1845
1846 tm_iocb->u.tmf.flags = flags;
1847 tm_iocb->u.tmf.lun = lun;
1848 tm_iocb->u.tmf.data = tag;
1849 sp->done = qla2x00_tmf_sp_done;
1850
1851 ql_dbg(ql_dbg_taskm, vha, 0x802f,
1852 "Async-tmf hdl=%x loop-id=%x portid=%02x%02x%02x.\n",
1853 sp->handle, fcport->loop_id, fcport->d_id.b.domain,
1854 fcport->d_id.b.area, fcport->d_id.b.al_pa);
1855
1856 rval = qla2x00_start_sp(sp);
1857 if (rval != QLA_SUCCESS)
1858 goto done_free_sp;
1859 wait_for_completion(&tm_iocb->u.tmf.comp);
1860
1861 rval = tm_iocb->u.tmf.data;
1862
1863 if (rval != QLA_SUCCESS) {
1864 ql_log(ql_log_warn, vha, 0x8030,
1865 "TM IOCB failed (%x).\n", rval);
1866 }
1867
1868 if (!test_bit(UNLOADING, &vha->dpc_flags) && !IS_QLAFX00(vha->hw)) {
1869 flags = tm_iocb->u.tmf.flags;
1870 lun = (uint16_t)tm_iocb->u.tmf.lun;
1871
1872
1873 qla2x00_marker(vha, vha->hw->base_qpair,
1874 fcport->loop_id, lun,
1875 flags == TCF_LUN_RESET ? MK_SYNC_ID_LUN : MK_SYNC_ID);
1876 }
1877
1878done_free_sp:
1879 sp->free(sp);
1880 fcport->flags &= ~FCF_ASYNC_SENT;
1881done:
1882 return rval;
1883}
1884
1885int
1886qla24xx_async_abort_command(srb_t *sp)
1887{
1888 unsigned long flags = 0;
1889
1890 uint32_t handle;
1891 fc_port_t *fcport = sp->fcport;
1892 struct qla_qpair *qpair = sp->qpair;
1893 struct scsi_qla_host *vha = fcport->vha;
1894 struct req_que *req = qpair->req;
1895
1896 spin_lock_irqsave(qpair->qp_lock_ptr, flags);
1897 for (handle = 1; handle < req->num_outstanding_cmds; handle++) {
1898 if (req->outstanding_cmds[handle] == sp)
1899 break;
1900 }
1901 spin_unlock_irqrestore(qpair->qp_lock_ptr, flags);
1902
1903 if (handle == req->num_outstanding_cmds) {
1904
1905 return QLA_FUNCTION_FAILED;
1906 }
1907 if (sp->type == SRB_FXIOCB_DCMD)
1908 return qlafx00_fx_disc(vha, &vha->hw->mr.fcport,
1909 FXDISC_ABORT_IOCTL);
1910
1911 return qla24xx_async_abort_cmd(sp, true);
1912}
1913
1914static void
1915qla24xx_handle_prli_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
1916{
1917 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
1918 ea->data[0]);
1919
1920 switch (ea->data[0]) {
1921 case MBS_COMMAND_COMPLETE:
1922 ql_dbg(ql_dbg_disc, vha, 0x2118,
1923 "%s %d %8phC post gpdb\n",
1924 __func__, __LINE__, ea->fcport->port_name);
1925
1926 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
1927 ea->fcport->logout_on_delete = 1;
1928 ea->fcport->nvme_prli_service_param = ea->iop[0];
1929 if (ea->iop[0] & NVME_PRLI_SP_FIRST_BURST)
1930 ea->fcport->nvme_first_burst_size =
1931 (ea->iop[1] & 0xffff) * 512;
1932 else
1933 ea->fcport->nvme_first_burst_size = 0;
1934 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
1935 break;
1936 default:
1937 if ((ea->iop[0] == LSC_SCODE_ELS_REJECT) &&
1938 (ea->iop[1] == 0x50000)) {
1939 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
1940 ea->fcport->fw_login_state = DSC_LS_PLOGI_COMP;
1941 break;
1942 }
1943
1944 ql_dbg(ql_dbg_disc, vha, 0x2118,
1945 "%s %d %8phC priority %s, fc4type %x\n",
1946 __func__, __LINE__, ea->fcport->port_name,
1947 vha->hw->fc4_type_priority == FC4_PRIORITY_FCP ?
1948 "FCP" : "NVMe", ea->fcport->fc4_type);
1949
1950 if (N2N_TOPO(vha->hw)) {
1951 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME) {
1952 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME;
1953 ea->fcport->fc4_type |= FS_FC4TYPE_FCP;
1954 } else {
1955 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP;
1956 ea->fcport->fc4_type |= FS_FC4TYPE_NVME;
1957 }
1958
1959 if (ea->fcport->n2n_link_reset_cnt < 3) {
1960 ea->fcport->n2n_link_reset_cnt++;
1961 vha->relogin_jif = jiffies + 2 * HZ;
1962
1963
1964
1965
1966 set_bit(N2N_LINK_RESET, &vha->dpc_flags);
1967 } else {
1968 ql_log(ql_log_warn, vha, 0x2119,
1969 "%s %d %8phC Unable to reconnect\n",
1970 __func__, __LINE__,
1971 ea->fcport->port_name);
1972 }
1973 } else {
1974
1975
1976
1977
1978 if (NVME_FCP_TARGET(ea->fcport)) {
1979 ql_dbg(ql_dbg_disc, vha, 0x2118,
1980 "%s %d %8phC post %s prli\n",
1981 __func__, __LINE__,
1982 ea->fcport->port_name,
1983 (ea->fcport->fc4_type & FS_FC4TYPE_NVME)
1984 ? "NVMe" : "FCP");
1985 if (vha->hw->fc4_type_priority == FC4_PRIORITY_NVME)
1986 ea->fcport->fc4_type &= ~FS_FC4TYPE_NVME;
1987 else
1988 ea->fcport->fc4_type &= ~FS_FC4TYPE_FCP;
1989 }
1990
1991 ea->fcport->flags &= ~FCF_ASYNC_SENT;
1992 ea->fcport->keep_nport_handle = 0;
1993 ea->fcport->logout_on_delete = 1;
1994 qlt_schedule_sess_for_deletion(ea->fcport);
1995 }
1996 break;
1997 }
1998}
1999
2000void
2001qla24xx_handle_plogi_done_event(struct scsi_qla_host *vha, struct event_arg *ea)
2002{
2003 port_id_t cid;
2004 u16 lid;
2005 struct fc_port *conflict_fcport;
2006 unsigned long flags;
2007 struct fc_port *fcport = ea->fcport;
2008
2009 ql_dbg(ql_dbg_disc, vha, 0xffff,
2010 "%s %8phC DS %d LS %d rc %d login %d|%d rscn %d|%d data %x|%x iop %x|%x\n",
2011 __func__, fcport->port_name, fcport->disc_state,
2012 fcport->fw_login_state, ea->rc, ea->sp->gen2, fcport->login_gen,
2013 ea->sp->gen1, fcport->rscn_gen,
2014 ea->data[0], ea->data[1], ea->iop[0], ea->iop[1]);
2015
2016 if ((fcport->fw_login_state == DSC_LS_PLOGI_PEND) ||
2017 (fcport->fw_login_state == DSC_LS_PRLI_PEND)) {
2018 ql_dbg(ql_dbg_disc, vha, 0x20ea,
2019 "%s %d %8phC Remote is trying to login\n",
2020 __func__, __LINE__, fcport->port_name);
2021 return;
2022 }
2023
2024 if ((fcport->disc_state == DSC_DELETE_PEND) ||
2025 (fcport->disc_state == DSC_DELETED)) {
2026 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2027 return;
2028 }
2029
2030 if (ea->sp->gen2 != fcport->login_gen) {
2031
2032 ql_dbg(ql_dbg_disc, vha, 0x20d3,
2033 "%s %8phC generation changed\n",
2034 __func__, fcport->port_name);
2035 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2036 return;
2037 } else if (ea->sp->gen1 != fcport->rscn_gen) {
2038 ql_dbg(ql_dbg_disc, vha, 0x20d3,
2039 "%s %8phC RSCN generation changed\n",
2040 __func__, fcport->port_name);
2041 qla_rscn_replay(fcport);
2042 qlt_schedule_sess_for_deletion(fcport);
2043 return;
2044 }
2045
2046 WARN_ONCE(!qla2xxx_is_valid_mbs(ea->data[0]), "mbs: %#x\n",
2047 ea->data[0]);
2048
2049 switch (ea->data[0]) {
2050 case MBS_COMMAND_COMPLETE:
2051
2052
2053
2054
2055
2056 if (NVME_TARGET(vha->hw, ea->fcport)) {
2057 ql_dbg(ql_dbg_disc, vha, 0x2117,
2058 "%s %d %8phC post prli\n",
2059 __func__, __LINE__, ea->fcport->port_name);
2060 qla24xx_post_prli_work(vha, ea->fcport);
2061 } else {
2062 ql_dbg(ql_dbg_disc, vha, 0x20ea,
2063 "%s %d %8phC LoopID 0x%x in use with %06x. post gpdb\n",
2064 __func__, __LINE__, ea->fcport->port_name,
2065 ea->fcport->loop_id, ea->fcport->d_id.b24);
2066
2067 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2068 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
2069 ea->fcport->chip_reset = vha->hw->base_qpair->chip_reset;
2070 ea->fcport->logout_on_delete = 1;
2071 ea->fcport->send_els_logo = 0;
2072 ea->fcport->fw_login_state = DSC_LS_PRLI_COMP;
2073 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
2074
2075 qla24xx_post_gpdb_work(vha, ea->fcport, 0);
2076 }
2077 break;
2078 case MBS_COMMAND_ERROR:
2079 ql_dbg(ql_dbg_disc, vha, 0x20eb, "%s %d %8phC cmd error %x\n",
2080 __func__, __LINE__, ea->fcport->port_name, ea->data[1]);
2081
2082 ea->fcport->flags &= ~FCF_ASYNC_SENT;
2083 qla2x00_set_fcport_disc_state(ea->fcport, DSC_LOGIN_FAILED);
2084 if (ea->data[1] & QLA_LOGIO_LOGIN_RETRIED)
2085 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
2086 else
2087 qla2x00_mark_device_lost(vha, ea->fcport, 1);
2088 break;
2089 case MBS_LOOP_ID_USED:
2090
2091 cid.b.domain = (ea->iop[1] >> 16) & 0xff;
2092 cid.b.area = (ea->iop[1] >> 8) & 0xff;
2093 cid.b.al_pa = ea->iop[1] & 0xff;
2094 cid.b.rsvd_1 = 0;
2095
2096 ql_dbg(ql_dbg_disc, vha, 0x20ec,
2097 "%s %d %8phC lid %#x in use with pid %06x post gnl\n",
2098 __func__, __LINE__, ea->fcport->port_name,
2099 ea->fcport->loop_id, cid.b24);
2100
2101 set_bit(ea->fcport->loop_id, vha->hw->loop_id_map);
2102 ea->fcport->loop_id = FC_NO_LOOP_ID;
2103 qla24xx_post_gnl_work(vha, ea->fcport);
2104 break;
2105 case MBS_PORT_ID_USED:
2106 lid = ea->iop[1] & 0xffff;
2107 qlt_find_sess_invalidate_other(vha,
2108 wwn_to_u64(ea->fcport->port_name),
2109 ea->fcport->d_id, lid, &conflict_fcport);
2110
2111 if (conflict_fcport) {
2112
2113
2114
2115
2116
2117 conflict_fcport->conflict = ea->fcport;
2118 ea->fcport->login_pause = 1;
2119
2120 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2121 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. post gidpn\n",
2122 __func__, __LINE__, ea->fcport->port_name,
2123 ea->fcport->d_id.b24, lid);
2124 } else {
2125 ql_dbg(ql_dbg_disc, vha, 0x20ed,
2126 "%s %d %8phC NPortId %06x inuse with loopid 0x%x. sched delete\n",
2127 __func__, __LINE__, ea->fcport->port_name,
2128 ea->fcport->d_id.b24, lid);
2129
2130 qla2x00_clear_loop_id(ea->fcport);
2131 set_bit(lid, vha->hw->loop_id_map);
2132 ea->fcport->loop_id = lid;
2133 ea->fcport->keep_nport_handle = 0;
2134 ea->fcport->logout_on_delete = 1;
2135 qlt_schedule_sess_for_deletion(ea->fcport);
2136 }
2137 break;
2138 }
2139 return;
2140}
2141
2142
2143
2144
2145
2146static int
2147qla83xx_nic_core_fw_load(scsi_qla_host_t *vha)
2148{
2149 int rval = QLA_SUCCESS;
2150 struct qla_hw_data *ha = vha->hw;
2151 uint32_t idc_major_ver, idc_minor_ver;
2152 uint16_t config[4];
2153
2154 qla83xx_idc_lock(vha, 0);
2155
2156
2157
2158
2159 ha->fcoe_dev_init_timeout = QLA83XX_IDC_INITIALIZATION_TIMEOUT;
2160 ha->fcoe_reset_timeout = QLA83XX_IDC_RESET_ACK_TIMEOUT;
2161
2162
2163 if (__qla83xx_set_drv_presence(vha) != QLA_SUCCESS) {
2164 ql_dbg(ql_dbg_p3p, vha, 0xb077,
2165 "Error while setting DRV-Presence.\n");
2166 rval = QLA_FUNCTION_FAILED;
2167 goto exit;
2168 }
2169
2170
2171 qla83xx_reset_ownership(vha);
2172
2173
2174
2175
2176
2177
2178
2179 qla83xx_rd_reg(vha, QLA83XX_IDC_MAJOR_VERSION, &idc_major_ver);
2180 if (ha->flags.nic_core_reset_owner) {
2181
2182 idc_major_ver = QLA83XX_SUPP_IDC_MAJOR_VERSION;
2183 qla83xx_wr_reg(vha, QLA83XX_IDC_MAJOR_VERSION, idc_major_ver);
2184
2185
2186 qla83xx_wr_reg(vha, QLA83XX_IDC_LOCK_RECOVERY, 0);
2187 } else if (idc_major_ver != QLA83XX_SUPP_IDC_MAJOR_VERSION) {
2188
2189
2190
2191
2192 ql_log(ql_log_warn, vha, 0xb07d,
2193 "Failing load, idc_major_ver=%d, expected_major_ver=%d.\n",
2194 idc_major_ver, QLA83XX_SUPP_IDC_MAJOR_VERSION);
2195 __qla83xx_clear_drv_presence(vha);
2196 rval = QLA_FUNCTION_FAILED;
2197 goto exit;
2198 }
2199
2200 qla83xx_rd_reg(vha, QLA83XX_IDC_MINOR_VERSION, &idc_minor_ver);
2201 idc_minor_ver |= (QLA83XX_SUPP_IDC_MINOR_VERSION << (ha->portnum * 2));
2202 qla83xx_wr_reg(vha, QLA83XX_IDC_MINOR_VERSION, idc_minor_ver);
2203
2204 if (ha->flags.nic_core_reset_owner) {
2205 memset(config, 0, sizeof(config));
2206 if (!qla81xx_get_port_config(vha, config))
2207 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
2208 QLA8XXX_DEV_READY);
2209 }
2210
2211 rval = qla83xx_idc_state_handler(vha);
2212
2213exit:
2214 qla83xx_idc_unlock(vha, 0);
2215
2216 return rval;
2217}
2218
2219
2220
2221
2222
2223
2224
2225
2226
2227
2228
2229int
2230qla2x00_initialize_adapter(scsi_qla_host_t *vha)
2231{
2232 int rval;
2233 struct qla_hw_data *ha = vha->hw;
2234 struct req_que *req = ha->req_q_map[0];
2235 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2236
2237 memset(&vha->qla_stats, 0, sizeof(vha->qla_stats));
2238 memset(&vha->fc_host_stat, 0, sizeof(vha->fc_host_stat));
2239
2240
2241 vha->flags.online = 0;
2242 ha->flags.chip_reset_done = 0;
2243 vha->flags.reset_active = 0;
2244 ha->flags.pci_channel_io_perm_failure = 0;
2245 ha->flags.eeh_busy = 0;
2246 vha->qla_stats.jiffies_at_last_reset = get_jiffies_64();
2247 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
2248 atomic_set(&vha->loop_state, LOOP_DOWN);
2249 vha->device_flags = DFLG_NO_CABLE;
2250 vha->dpc_flags = 0;
2251 vha->flags.management_server_logged_in = 0;
2252 vha->marker_needed = 0;
2253 ha->isp_abort_cnt = 0;
2254 ha->beacon_blink_led = 0;
2255
2256 set_bit(0, ha->req_qid_map);
2257 set_bit(0, ha->rsp_qid_map);
2258
2259 ql_dbg(ql_dbg_init, vha, 0x0040,
2260 "Configuring PCI space...\n");
2261 rval = ha->isp_ops->pci_config(vha);
2262 if (rval) {
2263 ql_log(ql_log_warn, vha, 0x0044,
2264 "Unable to configure PCI space.\n");
2265 return (rval);
2266 }
2267
2268 ha->isp_ops->reset_chip(vha);
2269
2270
2271 if (IS_QLA28XX(ha)) {
2272 if (rd_reg_word(®->mailbox12) & BIT_0)
2273 ha->flags.secure_adapter = 1;
2274 ql_log(ql_log_info, vha, 0xffff, "Secure Adapter: %s\n",
2275 (ha->flags.secure_adapter) ? "Yes" : "No");
2276 }
2277
2278
2279 rval = qla2xxx_get_flash_info(vha);
2280 if (rval) {
2281 ql_log(ql_log_fatal, vha, 0x004f,
2282 "Unable to validate FLASH data.\n");
2283 return rval;
2284 }
2285
2286 if (IS_QLA8044(ha)) {
2287 qla8044_read_reset_template(vha);
2288
2289
2290
2291
2292
2293 if (ql2xdontresethba == 1)
2294 qla8044_set_idc_dontreset(vha);
2295 }
2296
2297 ha->isp_ops->get_flash_version(vha, req->ring);
2298 ql_dbg(ql_dbg_init, vha, 0x0061,
2299 "Configure NVRAM parameters...\n");
2300
2301
2302 ha->fc4_type_priority = FC4_PRIORITY_FCP;
2303
2304 ha->isp_ops->nvram_config(vha);
2305
2306 if (ha->fc4_type_priority != FC4_PRIORITY_FCP &&
2307 ha->fc4_type_priority != FC4_PRIORITY_NVME)
2308 ha->fc4_type_priority = FC4_PRIORITY_FCP;
2309
2310 ql_log(ql_log_info, vha, 0xffff, "FC4 priority set to %s\n",
2311 ha->fc4_type_priority == FC4_PRIORITY_FCP ? "FCP" : "NVMe");
2312
2313 if (ha->flags.disable_serdes) {
2314
2315 ql_log(ql_log_info, vha, 0x0077,
2316 "Masking HBA WWPN %8phN (via NVRAM).\n", vha->port_name);
2317 return QLA_FUNCTION_FAILED;
2318 }
2319
2320 ql_dbg(ql_dbg_init, vha, 0x0078,
2321 "Verifying loaded RISC code...\n");
2322
2323
2324 if (ql2xsmartsan) {
2325 ql2xfdmienable = 1;
2326 ql2xrdpenable = 1;
2327 }
2328
2329 if (qla2x00_isp_firmware(vha) != QLA_SUCCESS) {
2330 rval = ha->isp_ops->chip_diag(vha);
2331 if (rval)
2332 return (rval);
2333 rval = qla2x00_setup_chip(vha);
2334 if (rval)
2335 return (rval);
2336 }
2337
2338 if (IS_QLA84XX(ha)) {
2339 ha->cs84xx = qla84xx_get_chip(vha);
2340 if (!ha->cs84xx) {
2341 ql_log(ql_log_warn, vha, 0x00d0,
2342 "Unable to configure ISP84XX.\n");
2343 return QLA_FUNCTION_FAILED;
2344 }
2345 }
2346
2347 if (qla_ini_mode_enabled(vha) || qla_dual_mode_enabled(vha))
2348 rval = qla2x00_init_rings(vha);
2349
2350
2351 if (rval != QLA_SUCCESS)
2352 return rval;
2353
2354 ha->flags.chip_reset_done = 1;
2355
2356 if (rval == QLA_SUCCESS && IS_QLA84XX(ha)) {
2357
2358 rval = qla84xx_init_chip(vha);
2359 if (rval != QLA_SUCCESS) {
2360 ql_log(ql_log_warn, vha, 0x00d4,
2361 "Unable to initialize ISP84XX.\n");
2362 qla84xx_put_chip(vha);
2363 }
2364 }
2365
2366
2367 if (IS_QLA8031(ha)) {
2368 rval = qla83xx_nic_core_fw_load(vha);
2369 if (rval)
2370 ql_log(ql_log_warn, vha, 0x0124,
2371 "Error in initializing NIC Core f/w.\n");
2372 }
2373
2374 if (IS_QLA24XX_TYPE(ha) || IS_QLA25XX(ha))
2375 qla24xx_read_fcp_prio_cfg(vha);
2376
2377 if (IS_P3P_TYPE(ha))
2378 qla82xx_set_driver_version(vha, QLA2XXX_VERSION);
2379 else
2380 qla25xx_set_driver_version(vha, QLA2XXX_VERSION);
2381
2382 return (rval);
2383}
2384
2385
2386
2387
2388
2389
2390
2391int
2392qla2100_pci_config(scsi_qla_host_t *vha)
2393{
2394 uint16_t w;
2395 unsigned long flags;
2396 struct qla_hw_data *ha = vha->hw;
2397 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2398
2399 pci_set_master(ha->pdev);
2400 pci_try_set_mwi(ha->pdev);
2401
2402 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2403 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2404 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2405
2406 pci_disable_rom(ha->pdev);
2407
2408
2409 spin_lock_irqsave(&ha->hardware_lock, flags);
2410 ha->pci_attr = rd_reg_word(®->ctrl_status);
2411 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2412
2413 return QLA_SUCCESS;
2414}
2415
2416
2417
2418
2419
2420
2421
2422int
2423qla2300_pci_config(scsi_qla_host_t *vha)
2424{
2425 uint16_t w;
2426 unsigned long flags = 0;
2427 uint32_t cnt;
2428 struct qla_hw_data *ha = vha->hw;
2429 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2430
2431 pci_set_master(ha->pdev);
2432 pci_try_set_mwi(ha->pdev);
2433
2434 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2435 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2436
2437 if (IS_QLA2322(ha) || IS_QLA6322(ha))
2438 w &= ~PCI_COMMAND_INTX_DISABLE;
2439 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2440
2441
2442
2443
2444
2445
2446
2447
2448 if (IS_QLA2300(ha)) {
2449 spin_lock_irqsave(&ha->hardware_lock, flags);
2450
2451
2452 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
2453 for (cnt = 0; cnt < 30000; cnt++) {
2454 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) != 0)
2455 break;
2456
2457 udelay(10);
2458 }
2459
2460
2461 wrt_reg_word(®->ctrl_status, 0x20);
2462 rd_reg_word(®->ctrl_status);
2463
2464
2465 ha->fb_rev = RD_FB_CMD_REG(ha, reg);
2466
2467 if (ha->fb_rev == FPM_2300)
2468 pci_clear_mwi(ha->pdev);
2469
2470
2471 wrt_reg_word(®->ctrl_status, 0x0);
2472 rd_reg_word(®->ctrl_status);
2473
2474
2475 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
2476 for (cnt = 0; cnt < 30000; cnt++) {
2477 if ((rd_reg_word(®->hccr) & HCCR_RISC_PAUSE) == 0)
2478 break;
2479
2480 udelay(10);
2481 }
2482
2483 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2484 }
2485
2486 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2487
2488 pci_disable_rom(ha->pdev);
2489
2490
2491 spin_lock_irqsave(&ha->hardware_lock, flags);
2492 ha->pci_attr = rd_reg_word(®->ctrl_status);
2493 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2494
2495 return QLA_SUCCESS;
2496}
2497
2498
2499
2500
2501
2502
2503
2504int
2505qla24xx_pci_config(scsi_qla_host_t *vha)
2506{
2507 uint16_t w;
2508 unsigned long flags = 0;
2509 struct qla_hw_data *ha = vha->hw;
2510 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2511
2512 pci_set_master(ha->pdev);
2513 pci_try_set_mwi(ha->pdev);
2514
2515 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2516 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2517 w &= ~PCI_COMMAND_INTX_DISABLE;
2518 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2519
2520 pci_write_config_byte(ha->pdev, PCI_LATENCY_TIMER, 0x80);
2521
2522
2523 if (pci_find_capability(ha->pdev, PCI_CAP_ID_PCIX))
2524 pcix_set_mmrbc(ha->pdev, 2048);
2525
2526
2527 if (pci_is_pcie(ha->pdev))
2528 pcie_set_readrq(ha->pdev, 4096);
2529
2530 pci_disable_rom(ha->pdev);
2531
2532 ha->chip_revision = ha->pdev->revision;
2533
2534
2535 spin_lock_irqsave(&ha->hardware_lock, flags);
2536 ha->pci_attr = rd_reg_dword(®->ctrl_status);
2537 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2538
2539 return QLA_SUCCESS;
2540}
2541
2542
2543
2544
2545
2546
2547
2548int
2549qla25xx_pci_config(scsi_qla_host_t *vha)
2550{
2551 uint16_t w;
2552 struct qla_hw_data *ha = vha->hw;
2553
2554 pci_set_master(ha->pdev);
2555 pci_try_set_mwi(ha->pdev);
2556
2557 pci_read_config_word(ha->pdev, PCI_COMMAND, &w);
2558 w |= (PCI_COMMAND_PARITY | PCI_COMMAND_SERR);
2559 w &= ~PCI_COMMAND_INTX_DISABLE;
2560 pci_write_config_word(ha->pdev, PCI_COMMAND, w);
2561
2562
2563 if (pci_is_pcie(ha->pdev))
2564 pcie_set_readrq(ha->pdev, 4096);
2565
2566 pci_disable_rom(ha->pdev);
2567
2568 ha->chip_revision = ha->pdev->revision;
2569
2570 return QLA_SUCCESS;
2571}
2572
2573
2574
2575
2576
2577
2578
2579static int
2580qla2x00_isp_firmware(scsi_qla_host_t *vha)
2581{
2582 int rval;
2583 uint16_t loop_id, topo, sw_cap;
2584 uint8_t domain, area, al_pa;
2585 struct qla_hw_data *ha = vha->hw;
2586
2587
2588 rval = QLA_FUNCTION_FAILED;
2589
2590 if (ha->flags.disable_risc_code_load) {
2591 ql_log(ql_log_info, vha, 0x0079, "RISC CODE NOT loaded.\n");
2592
2593
2594 rval = qla2x00_verify_checksum(vha, ha->fw_srisc_address);
2595 if (rval == QLA_SUCCESS) {
2596
2597 rval = qla2x00_get_adapter_id(vha, &loop_id, &al_pa,
2598 &area, &domain, &topo, &sw_cap);
2599 }
2600 }
2601
2602 if (rval)
2603 ql_dbg(ql_dbg_init, vha, 0x007a,
2604 "**** Load RISC code ****.\n");
2605
2606 return (rval);
2607}
2608
2609
2610
2611
2612
2613
2614
2615int
2616qla2x00_reset_chip(scsi_qla_host_t *vha)
2617{
2618 unsigned long flags = 0;
2619 struct qla_hw_data *ha = vha->hw;
2620 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
2621 uint32_t cnt;
2622 uint16_t cmd;
2623 int rval = QLA_FUNCTION_FAILED;
2624
2625 if (unlikely(pci_channel_offline(ha->pdev)))
2626 return rval;
2627
2628 ha->isp_ops->disable_intrs(ha);
2629
2630 spin_lock_irqsave(&ha->hardware_lock, flags);
2631
2632
2633 cmd = 0;
2634 pci_read_config_word(ha->pdev, PCI_COMMAND, &cmd);
2635 cmd &= ~PCI_COMMAND_MASTER;
2636 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2637
2638 if (!IS_QLA2100(ha)) {
2639
2640 wrt_reg_word(®->hccr, HCCR_PAUSE_RISC);
2641 if (IS_QLA2200(ha) || IS_QLA2300(ha)) {
2642 for (cnt = 0; cnt < 30000; cnt++) {
2643 if ((rd_reg_word(®->hccr) &
2644 HCCR_RISC_PAUSE) != 0)
2645 break;
2646 udelay(100);
2647 }
2648 } else {
2649 rd_reg_word(®->hccr);
2650 udelay(10);
2651 }
2652
2653
2654 wrt_reg_word(®->ctrl_status, 0x20);
2655 rd_reg_word(®->ctrl_status);
2656
2657
2658 wrt_reg_word(®->fpm_diag_config, 0x100);
2659 rd_reg_word(®->fpm_diag_config);
2660
2661
2662 if (!IS_QLA2200(ha)) {
2663 wrt_reg_word(®->fpm_diag_config, 0x0);
2664 rd_reg_word(®->fpm_diag_config);
2665 }
2666
2667
2668 wrt_reg_word(®->ctrl_status, 0x10);
2669 rd_reg_word(®->ctrl_status);
2670
2671
2672 if (IS_QLA2200(ha)) {
2673 WRT_FB_CMD_REG(ha, reg, 0xa000);
2674 RD_FB_CMD_REG(ha, reg);
2675 } else {
2676 WRT_FB_CMD_REG(ha, reg, 0x00fc);
2677
2678
2679 for (cnt = 0; cnt < 3000; cnt++) {
2680 if ((RD_FB_CMD_REG(ha, reg) & 0xff) == 0)
2681 break;
2682 udelay(100);
2683 }
2684 }
2685
2686
2687 wrt_reg_word(®->ctrl_status, 0);
2688 rd_reg_word(®->ctrl_status);
2689
2690
2691 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
2692 rd_reg_word(®->hccr);
2693
2694
2695 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
2696 rd_reg_word(®->hccr);
2697 }
2698
2699 wrt_reg_word(®->hccr, HCCR_CLR_RISC_INT);
2700 wrt_reg_word(®->hccr, HCCR_CLR_HOST_INT);
2701
2702
2703 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
2704
2705
2706 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2707
2708
2709
2710
2711
2712 udelay(20);
2713 for (cnt = 30000; cnt; cnt--) {
2714 if ((rd_reg_word(®->ctrl_status) &
2715 CSR_ISP_SOFT_RESET) == 0)
2716 break;
2717 udelay(100);
2718 }
2719 } else
2720 udelay(10);
2721
2722
2723 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
2724
2725 wrt_reg_word(®->semaphore, 0);
2726
2727
2728 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
2729 rd_reg_word(®->hccr);
2730
2731 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
2732 for (cnt = 0; cnt < 30000; cnt++) {
2733 if (RD_MAILBOX_REG(ha, reg, 0) != MBS_BUSY)
2734 break;
2735
2736 udelay(100);
2737 }
2738 } else
2739 udelay(100);
2740
2741
2742 cmd |= PCI_COMMAND_MASTER;
2743 pci_write_config_word(ha->pdev, PCI_COMMAND, cmd);
2744
2745
2746 if (!IS_QLA2100(ha)) {
2747 wrt_reg_word(®->hccr, HCCR_DISABLE_PARITY_PAUSE);
2748 rd_reg_word(®->hccr);
2749 }
2750
2751 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2752
2753 return QLA_SUCCESS;
2754}
2755
2756
2757
2758
2759
2760
2761
2762static int
2763qla81xx_reset_mpi(scsi_qla_host_t *vha)
2764{
2765 uint16_t mb[4] = {0x1010, 0, 1, 0};
2766
2767 if (!IS_QLA81XX(vha->hw))
2768 return QLA_SUCCESS;
2769
2770 return qla81xx_write_mpi_register(vha, mb);
2771}
2772
2773static int
2774qla_chk_risc_recovery(scsi_qla_host_t *vha)
2775{
2776 struct qla_hw_data *ha = vha->hw;
2777 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2778 __le16 __iomem *mbptr = ®->mailbox0;
2779 int i;
2780 u16 mb[32];
2781 int rc = QLA_SUCCESS;
2782
2783 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
2784 return rc;
2785
2786
2787 mb[0] = rd_reg_word(mbptr);
2788 mbptr++;
2789 if (mb[0] == 0xf) {
2790 rc = QLA_FUNCTION_FAILED;
2791
2792 for (i = 1; i < 32; i++) {
2793 mb[i] = rd_reg_word(mbptr);
2794 mbptr++;
2795 }
2796
2797 ql_log(ql_log_warn, vha, 0x1015,
2798 "RISC reset failed. mb[0-7] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
2799 mb[0], mb[1], mb[2], mb[3], mb[4], mb[5], mb[6], mb[7]);
2800 ql_log(ql_log_warn, vha, 0x1015,
2801 "RISC reset failed. mb[8-15] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
2802 mb[8], mb[9], mb[10], mb[11], mb[12], mb[13], mb[14],
2803 mb[15]);
2804 ql_log(ql_log_warn, vha, 0x1015,
2805 "RISC reset failed. mb[16-23] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
2806 mb[16], mb[17], mb[18], mb[19], mb[20], mb[21], mb[22],
2807 mb[23]);
2808 ql_log(ql_log_warn, vha, 0x1015,
2809 "RISC reset failed. mb[24-31] %04xh %04xh %04xh %04xh %04xh %04xh %04xh %04xh\n",
2810 mb[24], mb[25], mb[26], mb[27], mb[28], mb[29], mb[30],
2811 mb[31]);
2812 }
2813 return rc;
2814}
2815
2816
2817
2818
2819
2820
2821
2822static inline int
2823qla24xx_reset_risc(scsi_qla_host_t *vha)
2824{
2825 unsigned long flags = 0;
2826 struct qla_hw_data *ha = vha->hw;
2827 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
2828 uint32_t cnt;
2829 uint16_t wd;
2830 static int abts_cnt;
2831 int rval = QLA_SUCCESS;
2832 int print = 1;
2833
2834 spin_lock_irqsave(&ha->hardware_lock, flags);
2835
2836
2837 wrt_reg_dword(®->ctrl_status, CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2838 for (cnt = 0; cnt < 30000; cnt++) {
2839 if ((rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE) == 0)
2840 break;
2841
2842 udelay(10);
2843 }
2844
2845 if (!(rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE))
2846 set_bit(DMA_SHUTDOWN_CMPL, &ha->fw_dump_cap_flags);
2847
2848 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017e,
2849 "HCCR: 0x%x, Control Status %x, DMA active status:0x%x\n",
2850 rd_reg_dword(®->hccr),
2851 rd_reg_dword(®->ctrl_status),
2852 (rd_reg_dword(®->ctrl_status) & CSRX_DMA_ACTIVE));
2853
2854 wrt_reg_dword(®->ctrl_status,
2855 CSRX_ISP_SOFT_RESET|CSRX_DMA_SHUTDOWN|MWB_4096_BYTES);
2856 pci_read_config_word(ha->pdev, PCI_COMMAND, &wd);
2857
2858 udelay(100);
2859
2860
2861 rd_reg_word(®->mailbox0);
2862 for (cnt = 10000; rd_reg_word(®->mailbox0) != 0 &&
2863 rval == QLA_SUCCESS; cnt--) {
2864 barrier();
2865 if (cnt)
2866 udelay(5);
2867 else
2868 rval = QLA_FUNCTION_TIMEOUT;
2869 }
2870
2871 if (rval == QLA_SUCCESS)
2872 set_bit(ISP_MBX_RDY, &ha->fw_dump_cap_flags);
2873
2874 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x017f,
2875 "HCCR: 0x%x, MailBox0 Status 0x%x\n",
2876 rd_reg_dword(®->hccr),
2877 rd_reg_word(®->mailbox0));
2878
2879
2880 rd_reg_dword(®->ctrl_status);
2881 for (cnt = 0; cnt < 60; cnt++) {
2882 barrier();
2883 if ((rd_reg_dword(®->ctrl_status) &
2884 CSRX_ISP_SOFT_RESET) == 0)
2885 break;
2886
2887 udelay(5);
2888 }
2889 if (!(rd_reg_dword(®->ctrl_status) & CSRX_ISP_SOFT_RESET))
2890 set_bit(ISP_SOFT_RESET_CMPL, &ha->fw_dump_cap_flags);
2891
2892 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015d,
2893 "HCCR: 0x%x, Soft Reset status: 0x%x\n",
2894 rd_reg_dword(®->hccr),
2895 rd_reg_dword(®->ctrl_status));
2896
2897
2898 if (test_and_clear_bit(MPI_RESET_NEEDED, &vha->dpc_flags)) {
2899 if (qla81xx_reset_mpi(vha) != QLA_SUCCESS) {
2900 if (++abts_cnt < 5) {
2901 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
2902 set_bit(MPI_RESET_NEEDED, &vha->dpc_flags);
2903 } else {
2904
2905
2906
2907
2908 abts_cnt = 0;
2909 vha->flags.online = 0;
2910 }
2911 }
2912 }
2913
2914 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET);
2915 rd_reg_dword(®->hccr);
2916
2917 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE);
2918 rd_reg_dword(®->hccr);
2919
2920 wrt_reg_dword(®->hccr, HCCRX_CLR_RISC_RESET);
2921 mdelay(10);
2922 rd_reg_dword(®->hccr);
2923
2924 wd = rd_reg_word(®->mailbox0);
2925 for (cnt = 300; wd != 0 && rval == QLA_SUCCESS; cnt--) {
2926 barrier();
2927 if (cnt) {
2928 mdelay(1);
2929 if (print && qla_chk_risc_recovery(vha))
2930 print = 0;
2931
2932 wd = rd_reg_word(®->mailbox0);
2933 } else {
2934 rval = QLA_FUNCTION_TIMEOUT;
2935
2936 ql_log(ql_log_warn, vha, 0x015e,
2937 "RISC reset timeout\n");
2938 }
2939 }
2940
2941 if (rval == QLA_SUCCESS)
2942 set_bit(RISC_RDY_AFT_RESET, &ha->fw_dump_cap_flags);
2943
2944 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015e,
2945 "Host Risc 0x%x, mailbox0 0x%x\n",
2946 rd_reg_dword(®->hccr),
2947 rd_reg_word(®->mailbox0));
2948
2949 spin_unlock_irqrestore(&ha->hardware_lock, flags);
2950
2951 ql_dbg(ql_dbg_init + ql_dbg_verbose, vha, 0x015f,
2952 "Driver in %s mode\n",
2953 IS_NOPOLLING_TYPE(ha) ? "Interrupt" : "Polling");
2954
2955 if (IS_NOPOLLING_TYPE(ha))
2956 ha->isp_ops->enable_intrs(ha);
2957
2958 return rval;
2959}
2960
2961static void
2962qla25xx_read_risc_sema_reg(scsi_qla_host_t *vha, uint32_t *data)
2963{
2964 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2965
2966 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2967 *data = rd_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET);
2968}
2969
2970static void
2971qla25xx_write_risc_sema_reg(scsi_qla_host_t *vha, uint32_t data)
2972{
2973 struct device_reg_24xx __iomem *reg = &vha->hw->iobase->isp24;
2974
2975 wrt_reg_dword(®->iobase_addr, RISC_REGISTER_BASE_OFFSET);
2976 wrt_reg_dword(®->iobase_window + RISC_REGISTER_WINDOW_OFFSET, data);
2977}
2978
2979static void
2980qla25xx_manipulate_risc_semaphore(scsi_qla_host_t *vha)
2981{
2982 uint32_t wd32 = 0;
2983 uint delta_msec = 100;
2984 uint elapsed_msec = 0;
2985 uint timeout_msec;
2986 ulong n;
2987
2988 if (vha->hw->pdev->subsystem_device != 0x0175 &&
2989 vha->hw->pdev->subsystem_device != 0x0240)
2990 return;
2991
2992 wrt_reg_dword(&vha->hw->iobase->isp24.hccr, HCCRX_SET_RISC_PAUSE);
2993 udelay(100);
2994
2995attempt:
2996 timeout_msec = TIMEOUT_SEMAPHORE;
2997 n = timeout_msec / delta_msec;
2998 while (n--) {
2999 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_SET);
3000 qla25xx_read_risc_sema_reg(vha, &wd32);
3001 if (wd32 & RISC_SEMAPHORE)
3002 break;
3003 msleep(delta_msec);
3004 elapsed_msec += delta_msec;
3005 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
3006 goto force;
3007 }
3008
3009 if (!(wd32 & RISC_SEMAPHORE))
3010 goto force;
3011
3012 if (!(wd32 & RISC_SEMAPHORE_FORCE))
3013 goto acquired;
3014
3015 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_CLR);
3016 timeout_msec = TIMEOUT_SEMAPHORE_FORCE;
3017 n = timeout_msec / delta_msec;
3018 while (n--) {
3019 qla25xx_read_risc_sema_reg(vha, &wd32);
3020 if (!(wd32 & RISC_SEMAPHORE_FORCE))
3021 break;
3022 msleep(delta_msec);
3023 elapsed_msec += delta_msec;
3024 if (elapsed_msec > TIMEOUT_TOTAL_ELAPSED)
3025 goto force;
3026 }
3027
3028 if (wd32 & RISC_SEMAPHORE_FORCE)
3029 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_CLR);
3030
3031 goto attempt;
3032
3033force:
3034 qla25xx_write_risc_sema_reg(vha, RISC_SEMAPHORE_FORCE_SET);
3035
3036acquired:
3037 return;
3038}
3039
3040
3041
3042
3043
3044
3045
3046int
3047qla24xx_reset_chip(scsi_qla_host_t *vha)
3048{
3049 struct qla_hw_data *ha = vha->hw;
3050 int rval = QLA_FUNCTION_FAILED;
3051
3052 if (pci_channel_offline(ha->pdev) &&
3053 ha->flags.pci_channel_io_perm_failure) {
3054 return rval;
3055 }
3056
3057 ha->isp_ops->disable_intrs(ha);
3058
3059 qla25xx_manipulate_risc_semaphore(vha);
3060
3061
3062 rval = qla24xx_reset_risc(vha);
3063
3064 return rval;
3065}
3066
3067
3068
3069
3070
3071
3072
3073int
3074qla2x00_chip_diag(scsi_qla_host_t *vha)
3075{
3076 int rval;
3077 struct qla_hw_data *ha = vha->hw;
3078 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3079 unsigned long flags = 0;
3080 uint16_t data;
3081 uint32_t cnt;
3082 uint16_t mb[5];
3083 struct req_que *req = ha->req_q_map[0];
3084
3085
3086 rval = QLA_FUNCTION_FAILED;
3087
3088 ql_dbg(ql_dbg_init, vha, 0x007b, "Testing device at %p.\n",
3089 ®->flash_address);
3090
3091 spin_lock_irqsave(&ha->hardware_lock, flags);
3092
3093
3094 wrt_reg_word(®->ctrl_status, CSR_ISP_SOFT_RESET);
3095
3096
3097
3098
3099
3100 udelay(20);
3101 data = qla2x00_debounce_register(®->ctrl_status);
3102 for (cnt = 6000000 ; cnt && (data & CSR_ISP_SOFT_RESET); cnt--) {
3103 udelay(5);
3104 data = rd_reg_word(®->ctrl_status);
3105 barrier();
3106 }
3107
3108 if (!cnt)
3109 goto chip_diag_failed;
3110
3111 ql_dbg(ql_dbg_init, vha, 0x007c,
3112 "Reset register cleared by chip reset.\n");
3113
3114
3115 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
3116 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
3117
3118
3119 if (IS_QLA2100(ha) || IS_QLA2200(ha) || IS_QLA2300(ha)) {
3120 data = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 0));
3121 for (cnt = 6000000; cnt && (data == MBS_BUSY); cnt--) {
3122 udelay(5);
3123 data = RD_MAILBOX_REG(ha, reg, 0);
3124 barrier();
3125 }
3126 } else
3127 udelay(10);
3128
3129 if (!cnt)
3130 goto chip_diag_failed;
3131
3132
3133 ql_dbg(ql_dbg_init, vha, 0x007d, "Checking product ID of chip.\n");
3134
3135 mb[1] = RD_MAILBOX_REG(ha, reg, 1);
3136 mb[2] = RD_MAILBOX_REG(ha, reg, 2);
3137 mb[3] = RD_MAILBOX_REG(ha, reg, 3);
3138 mb[4] = qla2x00_debounce_register(MAILBOX_REG(ha, reg, 4));
3139 if (mb[1] != PROD_ID_1 || (mb[2] != PROD_ID_2 && mb[2] != PROD_ID_2a) ||
3140 mb[3] != PROD_ID_3) {
3141 ql_log(ql_log_warn, vha, 0x0062,
3142 "Wrong product ID = 0x%x,0x%x,0x%x.\n",
3143 mb[1], mb[2], mb[3]);
3144
3145 goto chip_diag_failed;
3146 }
3147 ha->product_id[0] = mb[1];
3148 ha->product_id[1] = mb[2];
3149 ha->product_id[2] = mb[3];
3150 ha->product_id[3] = mb[4];
3151
3152
3153 if (req->length > 1024)
3154 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * 1024;
3155 else
3156 ha->fw_transfer_size = REQUEST_ENTRY_SIZE *
3157 req->length;
3158
3159 if (IS_QLA2200(ha) &&
3160 RD_MAILBOX_REG(ha, reg, 7) == QLA2200A_RISC_ROM_VER) {
3161
3162 ql_dbg(ql_dbg_init, vha, 0x007e, "Found QLA2200A Chip.\n");
3163
3164 ha->device_type |= DT_ISP2200A;
3165 ha->fw_transfer_size = 128;
3166 }
3167
3168
3169 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3170
3171 ql_dbg(ql_dbg_init, vha, 0x007f, "Checking mailboxes.\n");
3172 rval = qla2x00_mbx_reg_test(vha);
3173 if (rval)
3174 ql_log(ql_log_warn, vha, 0x0080,
3175 "Failed mailbox send register test.\n");
3176 else
3177
3178 rval = QLA_SUCCESS;
3179 spin_lock_irqsave(&ha->hardware_lock, flags);
3180
3181chip_diag_failed:
3182 if (rval)
3183 ql_log(ql_log_info, vha, 0x0081,
3184 "Chip diagnostics **** FAILED ****.\n");
3185
3186 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3187
3188 return (rval);
3189}
3190
3191
3192
3193
3194
3195
3196
3197int
3198qla24xx_chip_diag(scsi_qla_host_t *vha)
3199{
3200 int rval;
3201 struct qla_hw_data *ha = vha->hw;
3202 struct req_que *req = ha->req_q_map[0];
3203
3204 if (IS_P3P_TYPE(ha))
3205 return QLA_SUCCESS;
3206
3207 ha->fw_transfer_size = REQUEST_ENTRY_SIZE * req->length;
3208
3209 rval = qla2x00_mbx_reg_test(vha);
3210 if (rval) {
3211 ql_log(ql_log_warn, vha, 0x0082,
3212 "Failed mailbox send register test.\n");
3213 } else {
3214
3215 rval = QLA_SUCCESS;
3216 }
3217
3218 return rval;
3219}
3220
3221static void
3222qla2x00_init_fce_trace(scsi_qla_host_t *vha)
3223{
3224 int rval;
3225 dma_addr_t tc_dma;
3226 void *tc;
3227 struct qla_hw_data *ha = vha->hw;
3228
3229 if (!IS_FWI2_CAPABLE(ha))
3230 return;
3231
3232 if (!IS_QLA25XX(ha) && !IS_QLA81XX(ha) && !IS_QLA83XX(ha) &&
3233 !IS_QLA27XX(ha) && !IS_QLA28XX(ha))
3234 return;
3235
3236 if (ha->fce) {
3237 ql_dbg(ql_dbg_init, vha, 0x00bd,
3238 "%s: FCE Mem is already allocated.\n",
3239 __func__);
3240 return;
3241 }
3242
3243
3244 tc = dma_alloc_coherent(&ha->pdev->dev, FCE_SIZE, &tc_dma,
3245 GFP_KERNEL);
3246 if (!tc) {
3247 ql_log(ql_log_warn, vha, 0x00be,
3248 "Unable to allocate (%d KB) for FCE.\n",
3249 FCE_SIZE / 1024);
3250 return;
3251 }
3252
3253 rval = qla2x00_enable_fce_trace(vha, tc_dma, FCE_NUM_BUFFERS,
3254 ha->fce_mb, &ha->fce_bufs);
3255 if (rval) {
3256 ql_log(ql_log_warn, vha, 0x00bf,
3257 "Unable to initialize FCE (%d).\n", rval);
3258 dma_free_coherent(&ha->pdev->dev, FCE_SIZE, tc, tc_dma);
3259 return;
3260 }
3261
3262 ql_dbg(ql_dbg_init, vha, 0x00c0,
3263 "Allocated (%d KB) for FCE...\n", FCE_SIZE / 1024);
3264
3265 ha->flags.fce_enabled = 1;
3266 ha->fce_dma = tc_dma;
3267 ha->fce = tc;
3268}
3269
3270static void
3271qla2x00_init_eft_trace(scsi_qla_host_t *vha)
3272{
3273 int rval;
3274 dma_addr_t tc_dma;
3275 void *tc;
3276 struct qla_hw_data *ha = vha->hw;
3277
3278 if (!IS_FWI2_CAPABLE(ha))
3279 return;
3280
3281 if (ha->eft) {
3282 ql_dbg(ql_dbg_init, vha, 0x00bd,
3283 "%s: EFT Mem is already allocated.\n",
3284 __func__);
3285 return;
3286 }
3287
3288
3289 tc = dma_alloc_coherent(&ha->pdev->dev, EFT_SIZE, &tc_dma,
3290 GFP_KERNEL);
3291 if (!tc) {
3292 ql_log(ql_log_warn, vha, 0x00c1,
3293 "Unable to allocate (%d KB) for EFT.\n",
3294 EFT_SIZE / 1024);
3295 return;
3296 }
3297
3298 rval = qla2x00_enable_eft_trace(vha, tc_dma, EFT_NUM_BUFFERS);
3299 if (rval) {
3300 ql_log(ql_log_warn, vha, 0x00c2,
3301 "Unable to initialize EFT (%d).\n", rval);
3302 dma_free_coherent(&ha->pdev->dev, EFT_SIZE, tc, tc_dma);
3303 return;
3304 }
3305
3306 ql_dbg(ql_dbg_init, vha, 0x00c3,
3307 "Allocated (%d KB) EFT ...\n", EFT_SIZE / 1024);
3308
3309 ha->eft_dma = tc_dma;
3310 ha->eft = tc;
3311}
3312
3313static void
3314qla2x00_alloc_offload_mem(scsi_qla_host_t *vha)
3315{
3316 qla2x00_init_fce_trace(vha);
3317 qla2x00_init_eft_trace(vha);
3318}
3319
3320void
3321qla2x00_alloc_fw_dump(scsi_qla_host_t *vha)
3322{
3323 uint32_t dump_size, fixed_size, mem_size, req_q_size, rsp_q_size,
3324 eft_size, fce_size, mq_size;
3325 struct qla_hw_data *ha = vha->hw;
3326 struct req_que *req = ha->req_q_map[0];
3327 struct rsp_que *rsp = ha->rsp_q_map[0];
3328 struct qla2xxx_fw_dump *fw_dump;
3329
3330 dump_size = fixed_size = mem_size = eft_size = fce_size = mq_size = 0;
3331 req_q_size = rsp_q_size = 0;
3332
3333 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
3334 fixed_size = sizeof(struct qla2100_fw_dump);
3335 } else if (IS_QLA23XX(ha)) {
3336 fixed_size = offsetof(struct qla2300_fw_dump, data_ram);
3337 mem_size = (ha->fw_memory_size - 0x11000 + 1) *
3338 sizeof(uint16_t);
3339 } else if (IS_FWI2_CAPABLE(ha)) {
3340 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))
3341 fixed_size = offsetof(struct qla83xx_fw_dump, ext_mem);
3342 else if (IS_QLA81XX(ha))
3343 fixed_size = offsetof(struct qla81xx_fw_dump, ext_mem);
3344 else if (IS_QLA25XX(ha))
3345 fixed_size = offsetof(struct qla25xx_fw_dump, ext_mem);
3346 else
3347 fixed_size = offsetof(struct qla24xx_fw_dump, ext_mem);
3348
3349 mem_size = (ha->fw_memory_size - 0x100000 + 1) *
3350 sizeof(uint32_t);
3351 if (ha->mqenable) {
3352 if (!IS_QLA83XX(ha) && !IS_QLA27XX(ha) &&
3353 !IS_QLA28XX(ha))
3354 mq_size = sizeof(struct qla2xxx_mq_chain);
3355
3356
3357
3358
3359 mq_size += (ha->max_req_queues - 1) *
3360 (req->length * sizeof(request_t));
3361 mq_size += (ha->max_rsp_queues - 1) *
3362 (rsp->length * sizeof(response_t));
3363 }
3364 if (ha->tgt.atio_ring)
3365 mq_size += ha->tgt.atio_q_length * sizeof(request_t);
3366
3367 qla2x00_init_fce_trace(vha);
3368 if (ha->fce)
3369 fce_size = sizeof(struct qla2xxx_fce_chain) + FCE_SIZE;
3370 qla2x00_init_eft_trace(vha);
3371 if (ha->eft)
3372 eft_size = EFT_SIZE;
3373 }
3374
3375 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3376 struct fwdt *fwdt = ha->fwdt;
3377 uint j;
3378
3379 for (j = 0; j < 2; j++, fwdt++) {
3380 if (!fwdt->template) {
3381 ql_dbg(ql_dbg_init, vha, 0x00ba,
3382 "-> fwdt%u no template\n", j);
3383 continue;
3384 }
3385 ql_dbg(ql_dbg_init, vha, 0x00fa,
3386 "-> fwdt%u calculating fwdump size...\n", j);
3387 fwdt->dump_size = qla27xx_fwdt_calculate_dump_size(
3388 vha, fwdt->template);
3389 ql_dbg(ql_dbg_init, vha, 0x00fa,
3390 "-> fwdt%u calculated fwdump size = %#lx bytes\n",
3391 j, fwdt->dump_size);
3392 dump_size += fwdt->dump_size;
3393 }
3394
3395 dump_size += ha->fwdt[1].dump_size;
3396 } else {
3397 req_q_size = req->length * sizeof(request_t);
3398 rsp_q_size = rsp->length * sizeof(response_t);
3399 dump_size = offsetof(struct qla2xxx_fw_dump, isp);
3400 dump_size += fixed_size + mem_size + req_q_size + rsp_q_size
3401 + eft_size;
3402 ha->chain_offset = dump_size;
3403 dump_size += mq_size + fce_size;
3404 if (ha->exchoffld_buf)
3405 dump_size += sizeof(struct qla2xxx_offld_chain) +
3406 ha->exchoffld_size;
3407 if (ha->exlogin_buf)
3408 dump_size += sizeof(struct qla2xxx_offld_chain) +
3409 ha->exlogin_size;
3410 }
3411
3412 if (!ha->fw_dump_len || dump_size > ha->fw_dump_alloc_len) {
3413
3414 ql_dbg(ql_dbg_init, vha, 0x00c5,
3415 "%s dump_size %d fw_dump_len %d fw_dump_alloc_len %d\n",
3416 __func__, dump_size, ha->fw_dump_len,
3417 ha->fw_dump_alloc_len);
3418
3419 fw_dump = vmalloc(dump_size);
3420 if (!fw_dump) {
3421 ql_log(ql_log_warn, vha, 0x00c4,
3422 "Unable to allocate (%d KB) for firmware dump.\n",
3423 dump_size / 1024);
3424 } else {
3425 mutex_lock(&ha->optrom_mutex);
3426 if (ha->fw_dumped) {
3427 memcpy(fw_dump, ha->fw_dump, ha->fw_dump_len);
3428 vfree(ha->fw_dump);
3429 ha->fw_dump = fw_dump;
3430 ha->fw_dump_alloc_len = dump_size;
3431 ql_dbg(ql_dbg_init, vha, 0x00c5,
3432 "Re-Allocated (%d KB) and save firmware dump.\n",
3433 dump_size / 1024);
3434 } else {
3435 vfree(ha->fw_dump);
3436 ha->fw_dump = fw_dump;
3437
3438 ha->fw_dump_len = ha->fw_dump_alloc_len =
3439 dump_size;
3440 ql_dbg(ql_dbg_init, vha, 0x00c5,
3441 "Allocated (%d KB) for firmware dump.\n",
3442 dump_size / 1024);
3443
3444 if (IS_QLA27XX(ha) || IS_QLA28XX(ha)) {
3445 ha->mpi_fw_dump = (char *)fw_dump +
3446 ha->fwdt[1].dump_size;
3447 mutex_unlock(&ha->optrom_mutex);
3448 return;
3449 }
3450
3451 ha->fw_dump->signature[0] = 'Q';
3452 ha->fw_dump->signature[1] = 'L';
3453 ha->fw_dump->signature[2] = 'G';
3454 ha->fw_dump->signature[3] = 'C';
3455 ha->fw_dump->version = htonl(1);
3456
3457 ha->fw_dump->fixed_size = htonl(fixed_size);
3458 ha->fw_dump->mem_size = htonl(mem_size);
3459 ha->fw_dump->req_q_size = htonl(req_q_size);
3460 ha->fw_dump->rsp_q_size = htonl(rsp_q_size);
3461
3462 ha->fw_dump->eft_size = htonl(eft_size);
3463 ha->fw_dump->eft_addr_l =
3464 htonl(LSD(ha->eft_dma));
3465 ha->fw_dump->eft_addr_h =
3466 htonl(MSD(ha->eft_dma));
3467
3468 ha->fw_dump->header_size =
3469 htonl(offsetof
3470 (struct qla2xxx_fw_dump, isp));
3471 }
3472 mutex_unlock(&ha->optrom_mutex);
3473 }
3474 }
3475}
3476
3477static int
3478qla81xx_mpi_sync(scsi_qla_host_t *vha)
3479{
3480#define MPS_MASK 0xe0
3481 int rval;
3482 uint16_t dc;
3483 uint32_t dw;
3484
3485 if (!IS_QLA81XX(vha->hw))
3486 return QLA_SUCCESS;
3487
3488 rval = qla2x00_write_ram_word(vha, 0x7c00, 1);
3489 if (rval != QLA_SUCCESS) {
3490 ql_log(ql_log_warn, vha, 0x0105,
3491 "Unable to acquire semaphore.\n");
3492 goto done;
3493 }
3494
3495 pci_read_config_word(vha->hw->pdev, 0x54, &dc);
3496 rval = qla2x00_read_ram_word(vha, 0x7a15, &dw);
3497 if (rval != QLA_SUCCESS) {
3498 ql_log(ql_log_warn, vha, 0x0067, "Unable to read sync.\n");
3499 goto done_release;
3500 }
3501
3502 dc &= MPS_MASK;
3503 if (dc == (dw & MPS_MASK))
3504 goto done_release;
3505
3506 dw &= ~MPS_MASK;
3507 dw |= dc;
3508 rval = qla2x00_write_ram_word(vha, 0x7a15, dw);
3509 if (rval != QLA_SUCCESS) {
3510 ql_log(ql_log_warn, vha, 0x0114, "Unable to gain sync.\n");
3511 }
3512
3513done_release:
3514 rval = qla2x00_write_ram_word(vha, 0x7c00, 0);
3515 if (rval != QLA_SUCCESS) {
3516 ql_log(ql_log_warn, vha, 0x006d,
3517 "Unable to release semaphore.\n");
3518 }
3519
3520done:
3521 return rval;
3522}
3523
3524int
3525qla2x00_alloc_outstanding_cmds(struct qla_hw_data *ha, struct req_que *req)
3526{
3527
3528 if (req->outstanding_cmds)
3529 return QLA_SUCCESS;
3530
3531 if (!IS_FWI2_CAPABLE(ha))
3532 req->num_outstanding_cmds = DEFAULT_OUTSTANDING_COMMANDS;
3533 else {
3534 if (ha->cur_fw_xcb_count <= ha->cur_fw_iocb_count)
3535 req->num_outstanding_cmds = ha->cur_fw_xcb_count;
3536 else
3537 req->num_outstanding_cmds = ha->cur_fw_iocb_count;
3538 }
3539
3540 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3541 sizeof(srb_t *),
3542 GFP_KERNEL);
3543
3544 if (!req->outstanding_cmds) {
3545
3546
3547
3548
3549 req->num_outstanding_cmds = MIN_OUTSTANDING_COMMANDS;
3550 req->outstanding_cmds = kcalloc(req->num_outstanding_cmds,
3551 sizeof(srb_t *),
3552 GFP_KERNEL);
3553
3554 if (!req->outstanding_cmds) {
3555 ql_log(ql_log_fatal, NULL, 0x0126,
3556 "Failed to allocate memory for "
3557 "outstanding_cmds for req_que %p.\n", req);
3558 req->num_outstanding_cmds = 0;
3559 return QLA_FUNCTION_FAILED;
3560 }
3561 }
3562
3563 return QLA_SUCCESS;
3564}
3565
3566#define PRINT_FIELD(_field, _flag, _str) { \
3567 if (a0->_field & _flag) {\
3568 if (p) {\
3569 strcat(ptr, "|");\
3570 ptr++;\
3571 leftover--;\
3572 } \
3573 len = snprintf(ptr, leftover, "%s", _str); \
3574 p = 1;\
3575 leftover -= len;\
3576 ptr += len; \
3577 } \
3578}
3579
3580static void qla2xxx_print_sfp_info(struct scsi_qla_host *vha)
3581{
3582#define STR_LEN 64
3583 struct sff_8247_a0 *a0 = (struct sff_8247_a0 *)vha->hw->sfp_data;
3584 u8 str[STR_LEN], *ptr, p;
3585 int leftover, len;
3586
3587 memset(str, 0, STR_LEN);
3588 snprintf(str, SFF_VEN_NAME_LEN+1, a0->vendor_name);
3589 ql_dbg(ql_dbg_init, vha, 0x015a,
3590 "SFP MFG Name: %s\n", str);
3591
3592 memset(str, 0, STR_LEN);
3593 snprintf(str, SFF_PART_NAME_LEN+1, a0->vendor_pn);
3594 ql_dbg(ql_dbg_init, vha, 0x015c,
3595 "SFP Part Name: %s\n", str);
3596
3597
3598 memset(str, 0, STR_LEN);
3599 ptr = str;
3600 leftover = STR_LEN;
3601 p = len = 0;
3602 PRINT_FIELD(fc_med_cc9, FC_MED_TW, "Twin AX");
3603 PRINT_FIELD(fc_med_cc9, FC_MED_TP, "Twisted Pair");
3604 PRINT_FIELD(fc_med_cc9, FC_MED_MI, "Min Coax");
3605 PRINT_FIELD(fc_med_cc9, FC_MED_TV, "Video Coax");
3606 PRINT_FIELD(fc_med_cc9, FC_MED_M6, "MultiMode 62.5um");
3607 PRINT_FIELD(fc_med_cc9, FC_MED_M5, "MultiMode 50um");
3608 PRINT_FIELD(fc_med_cc9, FC_MED_SM, "SingleMode");
3609 ql_dbg(ql_dbg_init, vha, 0x0160,
3610 "SFP Media: %s\n", str);
3611
3612
3613 memset(str, 0, STR_LEN);
3614 ptr = str;
3615 leftover = STR_LEN;
3616 p = len = 0;
3617 PRINT_FIELD(fc_ll_cc7, FC_LL_VL, "Very Long");
3618 PRINT_FIELD(fc_ll_cc7, FC_LL_S, "Short");
3619 PRINT_FIELD(fc_ll_cc7, FC_LL_I, "Intermediate");
3620 PRINT_FIELD(fc_ll_cc7, FC_LL_L, "Long");
3621 PRINT_FIELD(fc_ll_cc7, FC_LL_M, "Medium");
3622 ql_dbg(ql_dbg_init, vha, 0x0196,
3623 "SFP Link Length: %s\n", str);
3624
3625 memset(str, 0, STR_LEN);
3626 ptr = str;
3627 leftover = STR_LEN;
3628 p = len = 0;
3629 PRINT_FIELD(fc_ll_cc7, FC_LL_SA, "Short Wave (SA)");
3630 PRINT_FIELD(fc_ll_cc7, FC_LL_LC, "Long Wave(LC)");
3631 PRINT_FIELD(fc_tec_cc8, FC_TEC_SN, "Short Wave (SN)");
3632 PRINT_FIELD(fc_tec_cc8, FC_TEC_SL, "Short Wave (SL)");
3633 PRINT_FIELD(fc_tec_cc8, FC_TEC_LL, "Long Wave (LL)");
3634 ql_dbg(ql_dbg_init, vha, 0x016e,
3635 "SFP FC Link Tech: %s\n", str);
3636
3637 if (a0->length_km)
3638 ql_dbg(ql_dbg_init, vha, 0x016f,
3639 "SFP Distant: %d km\n", a0->length_km);
3640 if (a0->length_100m)
3641 ql_dbg(ql_dbg_init, vha, 0x0170,
3642 "SFP Distant: %d m\n", a0->length_100m*100);
3643 if (a0->length_50um_10m)
3644 ql_dbg(ql_dbg_init, vha, 0x0189,
3645 "SFP Distant (WL=50um): %d m\n", a0->length_50um_10m * 10);
3646 if (a0->length_62um_10m)
3647 ql_dbg(ql_dbg_init, vha, 0x018a,
3648 "SFP Distant (WL=62.5um): %d m\n", a0->length_62um_10m * 10);
3649 if (a0->length_om4_10m)
3650 ql_dbg(ql_dbg_init, vha, 0x0194,
3651 "SFP Distant (OM4): %d m\n", a0->length_om4_10m * 10);
3652 if (a0->length_om3_10m)
3653 ql_dbg(ql_dbg_init, vha, 0x0195,
3654 "SFP Distant (OM3): %d m\n", a0->length_om3_10m * 10);
3655}
3656
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667
3668
3669
3670
3671
3672int
3673qla24xx_detect_sfp(scsi_qla_host_t *vha)
3674{
3675 int rc, used_nvram;
3676 struct sff_8247_a0 *a;
3677 struct qla_hw_data *ha = vha->hw;
3678 struct nvram_81xx *nv = ha->nvram;
3679#define LR_DISTANCE_UNKNOWN 2
3680 static const char * const types[] = { "Short", "Long" };
3681 static const char * const lengths[] = { "(10km)", "(5km)", "" };
3682 u8 ll = 0;
3683
3684
3685 used_nvram = 0;
3686 ha->flags.lr_detected = 0;
3687 if (IS_BPM_RANGE_CAPABLE(ha) &&
3688 (nv->enhanced_features & NEF_LR_DIST_ENABLE)) {
3689 used_nvram = 1;
3690 ha->flags.lr_detected = 1;
3691 ha->lr_distance =
3692 (nv->enhanced_features >> LR_DIST_NV_POS)
3693 & LR_DIST_NV_MASK;
3694 }
3695
3696 if (!IS_BPM_ENABLED(vha))
3697 goto out;
3698
3699 rc = qla2x00_read_sfp_dev(vha, NULL, 0);
3700 if (rc)
3701 goto out;
3702
3703 used_nvram = 0;
3704 a = (struct sff_8247_a0 *)vha->hw->sfp_data;
3705 qla2xxx_print_sfp_info(vha);
3706
3707 ha->flags.lr_detected = 0;
3708 ll = a->fc_ll_cc7;
3709 if (ll & FC_LL_VL || ll & FC_LL_L) {
3710
3711 ha->flags.lr_detected = 1;
3712
3713 if (a->length_km > 5 || a->length_100m > 50)
3714 ha->lr_distance = LR_DISTANCE_10K;
3715 else
3716 ha->lr_distance = LR_DISTANCE_5K;
3717 }
3718
3719out:
3720 ql_dbg(ql_dbg_async, vha, 0x507b,
3721 "SFP detect: %s-Range SFP %s (nvr=%x ll=%x lr=%x lrd=%x).\n",
3722 types[ha->flags.lr_detected],
3723 ha->flags.lr_detected ? lengths[ha->lr_distance] :
3724 lengths[LR_DISTANCE_UNKNOWN],
3725 used_nvram, ll, ha->flags.lr_detected, ha->lr_distance);
3726 return ha->flags.lr_detected;
3727}
3728
3729void qla_init_iocb_limit(scsi_qla_host_t *vha)
3730{
3731 u16 i, num_qps;
3732 u32 limit;
3733 struct qla_hw_data *ha = vha->hw;
3734
3735 num_qps = ha->num_qpairs + 1;
3736 limit = (ha->orig_fw_iocb_count * QLA_IOCB_PCT_LIMIT) / 100;
3737
3738 ha->base_qpair->fwres.iocbs_total = ha->orig_fw_iocb_count;
3739 ha->base_qpair->fwres.iocbs_limit = limit;
3740 ha->base_qpair->fwres.iocbs_qp_limit = limit / num_qps;
3741 ha->base_qpair->fwres.iocbs_used = 0;
3742 for (i = 0; i < ha->max_qpairs; i++) {
3743 if (ha->queue_pair_map[i]) {
3744 ha->queue_pair_map[i]->fwres.iocbs_total =
3745 ha->orig_fw_iocb_count;
3746 ha->queue_pair_map[i]->fwres.iocbs_limit = limit;
3747 ha->queue_pair_map[i]->fwres.iocbs_qp_limit =
3748 limit / num_qps;
3749 ha->queue_pair_map[i]->fwres.iocbs_used = 0;
3750 }
3751 }
3752}
3753
3754
3755
3756
3757
3758
3759
3760static int
3761qla2x00_setup_chip(scsi_qla_host_t *vha)
3762{
3763 int rval;
3764 uint32_t srisc_address = 0;
3765 struct qla_hw_data *ha = vha->hw;
3766 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
3767 unsigned long flags;
3768 uint16_t fw_major_version;
3769 int done_once = 0;
3770
3771 if (IS_P3P_TYPE(ha)) {
3772 rval = ha->isp_ops->load_risc(vha, &srisc_address);
3773 if (rval == QLA_SUCCESS) {
3774 qla2x00_stop_firmware(vha);
3775 goto enable_82xx_npiv;
3776 } else
3777 goto failed;
3778 }
3779
3780 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3781
3782 spin_lock_irqsave(&ha->hardware_lock, flags);
3783 wrt_reg_word(®->hccr, (HCCR_ENABLE_PARITY + 0x0));
3784 rd_reg_word(®->hccr);
3785 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3786 }
3787
3788 qla81xx_mpi_sync(vha);
3789
3790execute_fw_with_lr:
3791
3792 rval = ha->isp_ops->load_risc(vha, &srisc_address);
3793 if (rval == QLA_SUCCESS) {
3794 ql_dbg(ql_dbg_init, vha, 0x00c9,
3795 "Verifying Checksum of loaded RISC code.\n");
3796
3797 rval = qla2x00_verify_checksum(vha, srisc_address);
3798 if (rval == QLA_SUCCESS) {
3799
3800 ql_dbg(ql_dbg_init, vha, 0x00ca,
3801 "Starting firmware.\n");
3802
3803 if (ql2xexlogins)
3804 ha->flags.exlogins_enabled = 1;
3805
3806 if (qla_is_exch_offld_enabled(vha))
3807 ha->flags.exchoffld_enabled = 1;
3808
3809 rval = qla2x00_execute_fw(vha, srisc_address);
3810
3811 if (rval == QLA_SUCCESS) {
3812
3813 if (!done_once++ && qla24xx_detect_sfp(vha)) {
3814 ql_dbg(ql_dbg_init, vha, 0x00ca,
3815 "Re-starting firmware -- BPM.\n");
3816
3817 ha->isp_ops->reset_chip(vha);
3818 ha->isp_ops->chip_diag(vha);
3819 goto execute_fw_with_lr;
3820 }
3821
3822 if (IS_ZIO_THRESHOLD_CAPABLE(ha))
3823 qla27xx_set_zio_threshold(vha,
3824 ha->last_zio_threshold);
3825
3826 rval = qla2x00_set_exlogins_buffer(vha);
3827 if (rval != QLA_SUCCESS)
3828 goto failed;
3829
3830 rval = qla2x00_set_exchoffld_buffer(vha);
3831 if (rval != QLA_SUCCESS)
3832 goto failed;
3833
3834enable_82xx_npiv:
3835 fw_major_version = ha->fw_major_version;
3836 if (IS_P3P_TYPE(ha))
3837 qla82xx_check_md_needed(vha);
3838 else
3839 rval = qla2x00_get_fw_version(vha);
3840 if (rval != QLA_SUCCESS)
3841 goto failed;
3842 ha->flags.npiv_supported = 0;
3843 if (IS_QLA2XXX_MIDTYPE(ha) &&
3844 (ha->fw_attributes & BIT_2)) {
3845 ha->flags.npiv_supported = 1;
3846 if ((!ha->max_npiv_vports) ||
3847 ((ha->max_npiv_vports + 1) %
3848 MIN_MULTI_ID_FABRIC))
3849 ha->max_npiv_vports =
3850 MIN_MULTI_ID_FABRIC - 1;
3851 }
3852 qla2x00_get_resource_cnts(vha);
3853 qla_init_iocb_limit(vha);
3854
3855
3856
3857
3858
3859 rval = qla2x00_alloc_outstanding_cmds(ha,
3860 vha->req);
3861 if (rval != QLA_SUCCESS)
3862 goto failed;
3863
3864 if (!fw_major_version && !(IS_P3P_TYPE(ha)))
3865 qla2x00_alloc_offload_mem(vha);
3866
3867 if (ql2xallocfwdump && !(IS_P3P_TYPE(ha)))
3868 qla2x00_alloc_fw_dump(vha);
3869
3870 } else {
3871 goto failed;
3872 }
3873 } else {
3874 ql_log(ql_log_fatal, vha, 0x00cd,
3875 "ISP Firmware failed checksum.\n");
3876 goto failed;
3877 }
3878
3879
3880 if (ql2xrdpenable || ha->flags.scm_supported_f)
3881 qla25xx_set_els_cmds_supported(vha);
3882 } else
3883 goto failed;
3884
3885 if (!IS_FWI2_CAPABLE(ha) && !IS_QLA2100(ha) && !IS_QLA2200(ha)) {
3886
3887 spin_lock_irqsave(&ha->hardware_lock, flags);
3888 if (IS_QLA2300(ha))
3889
3890 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x1);
3891 else
3892
3893 wrt_reg_word(®->hccr, HCCR_ENABLE_PARITY + 0x7);
3894 rd_reg_word(®->hccr);
3895 spin_unlock_irqrestore(&ha->hardware_lock, flags);
3896 }
3897
3898 if (IS_QLA27XX(ha) || IS_QLA28XX(ha))
3899 ha->flags.fac_supported = 1;
3900 else if (rval == QLA_SUCCESS && IS_FAC_REQUIRED(ha)) {
3901 uint32_t size;
3902
3903 rval = qla81xx_fac_get_sector_size(vha, &size);
3904 if (rval == QLA_SUCCESS) {
3905 ha->flags.fac_supported = 1;
3906 ha->fdt_block_size = size << 2;
3907 } else {
3908 ql_log(ql_log_warn, vha, 0x00ce,
3909 "Unsupported FAC firmware (%d.%02d.%02d).\n",
3910 ha->fw_major_version, ha->fw_minor_version,
3911 ha->fw_subminor_version);
3912
3913 if (IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
3914 IS_QLA28XX(ha)) {
3915 ha->flags.fac_supported = 0;
3916 rval = QLA_SUCCESS;
3917 }
3918 }
3919 }
3920failed:
3921 if (rval) {
3922 ql_log(ql_log_fatal, vha, 0x00cf,
3923 "Setup chip ****FAILED****.\n");
3924 }
3925
3926 return (rval);
3927}
3928
3929
3930
3931
3932
3933
3934
3935
3936
3937
3938void
3939qla2x00_init_response_q_entries(struct rsp_que *rsp)
3940{
3941 uint16_t cnt;
3942 response_t *pkt;
3943
3944 rsp->ring_ptr = rsp->ring;
3945 rsp->ring_index = 0;
3946 rsp->status_srb = NULL;
3947 pkt = rsp->ring_ptr;
3948 for (cnt = 0; cnt < rsp->length; cnt++) {
3949 pkt->signature = RESPONSE_PROCESSED;
3950 pkt++;
3951 }
3952}
3953
3954
3955
3956
3957
3958
3959
3960void
3961qla2x00_update_fw_options(scsi_qla_host_t *vha)
3962{
3963 uint16_t swing, emphasis, tx_sens, rx_sens;
3964 struct qla_hw_data *ha = vha->hw;
3965
3966 memset(ha->fw_options, 0, sizeof(ha->fw_options));
3967 qla2x00_get_fw_options(vha, ha->fw_options);
3968
3969 if (IS_QLA2100(ha) || IS_QLA2200(ha))
3970 return;
3971
3972
3973 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0115,
3974 "Serial link options.\n");
3975 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0109,
3976 ha->fw_seriallink_options, sizeof(ha->fw_seriallink_options));
3977
3978 ha->fw_options[1] &= ~FO1_SET_EMPHASIS_SWING;
3979 if (ha->fw_seriallink_options[3] & BIT_2) {
3980 ha->fw_options[1] |= FO1_SET_EMPHASIS_SWING;
3981
3982
3983 swing = ha->fw_seriallink_options[2] & (BIT_2 | BIT_1 | BIT_0);
3984 emphasis = (ha->fw_seriallink_options[2] &
3985 (BIT_4 | BIT_3)) >> 3;
3986 tx_sens = ha->fw_seriallink_options[0] &
3987 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
3988 rx_sens = (ha->fw_seriallink_options[0] &
3989 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
3990 ha->fw_options[10] = (emphasis << 14) | (swing << 8);
3991 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
3992 if (rx_sens == 0x0)
3993 rx_sens = 0x3;
3994 ha->fw_options[10] |= (tx_sens << 4) | rx_sens;
3995 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
3996 ha->fw_options[10] |= BIT_5 |
3997 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
3998 (tx_sens & (BIT_1 | BIT_0));
3999
4000
4001 swing = (ha->fw_seriallink_options[2] &
4002 (BIT_7 | BIT_6 | BIT_5)) >> 5;
4003 emphasis = ha->fw_seriallink_options[3] & (BIT_1 | BIT_0);
4004 tx_sens = ha->fw_seriallink_options[1] &
4005 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4006 rx_sens = (ha->fw_seriallink_options[1] &
4007 (BIT_7 | BIT_6 | BIT_5 | BIT_4)) >> 4;
4008 ha->fw_options[11] = (emphasis << 14) | (swing << 8);
4009 if (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA6312(ha)) {
4010 if (rx_sens == 0x0)
4011 rx_sens = 0x3;
4012 ha->fw_options[11] |= (tx_sens << 4) | rx_sens;
4013 } else if (IS_QLA2322(ha) || IS_QLA6322(ha))
4014 ha->fw_options[11] |= BIT_5 |
4015 ((rx_sens & (BIT_1 | BIT_0)) << 2) |
4016 (tx_sens & (BIT_1 | BIT_0));
4017 }
4018
4019
4020
4021 ha->fw_options[3] |= BIT_13;
4022
4023
4024 if (ha->flags.enable_led_scheme)
4025 ha->fw_options[2] |= BIT_12;
4026
4027
4028 if (IS_QLA6312(ha))
4029 ha->fw_options[2] |= BIT_13;
4030
4031
4032 if (ha->operating_mode == P2P) {
4033 ha->fw_options[2] |= BIT_3;
4034 ql_dbg(ql_dbg_disc, vha, 0x2100,
4035 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
4036 __func__, ha->fw_options[2]);
4037 }
4038
4039
4040 qla2x00_set_fw_options(vha, ha->fw_options);
4041}
4042
4043void
4044qla24xx_update_fw_options(scsi_qla_host_t *vha)
4045{
4046 int rval;
4047 struct qla_hw_data *ha = vha->hw;
4048
4049 if (IS_P3P_TYPE(ha))
4050 return;
4051
4052
4053 if (ql2xfwholdabts)
4054 ha->fw_options[3] |= BIT_12;
4055
4056
4057 if (ha->operating_mode == P2P) {
4058 ha->fw_options[2] |= BIT_3;
4059 ql_dbg(ql_dbg_disc, vha, 0x2101,
4060 "(%s): Setting FLOGI retry BIT in fw_options[2]: 0x%x\n",
4061 __func__, ha->fw_options[2]);
4062 }
4063
4064
4065 if (ql2xmvasynctoatio &&
4066 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha))) {
4067 if (qla_tgt_mode_enabled(vha) ||
4068 qla_dual_mode_enabled(vha))
4069 ha->fw_options[2] |= BIT_11;
4070 else
4071 ha->fw_options[2] &= ~BIT_11;
4072 }
4073
4074 if (IS_QLA25XX(ha) || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4075 IS_QLA28XX(ha)) {
4076
4077
4078
4079
4080 if (qla_tgt_mode_enabled(vha) ||
4081 qla_dual_mode_enabled(vha))
4082 ha->fw_options[2] |= BIT_4;
4083 else
4084 ha->fw_options[2] &= ~BIT_4;
4085
4086
4087 if (qla2xuseresexchforels)
4088 ha->fw_options[2] |= BIT_8;
4089 else
4090 ha->fw_options[2] &= ~BIT_8;
4091 }
4092
4093 if (ql2xrdpenable || ha->flags.scm_supported_f)
4094 ha->fw_options[1] |= ADD_FO1_ENABLE_PUREX_IOCB;
4095
4096
4097 if (IS_BPM_RANGE_CAPABLE(ha))
4098 ha->fw_options[3] |= BIT_10;
4099
4100 ql_dbg(ql_dbg_init, vha, 0x00e8,
4101 "%s, add FW options 1-3 = 0x%04x 0x%04x 0x%04x mode %x\n",
4102 __func__, ha->fw_options[1], ha->fw_options[2],
4103 ha->fw_options[3], vha->host->active_mode);
4104
4105 if (ha->fw_options[1] || ha->fw_options[2] || ha->fw_options[3])
4106 qla2x00_set_fw_options(vha, ha->fw_options);
4107
4108
4109 if ((le16_to_cpu(ha->fw_seriallink_options24[0]) & BIT_0) == 0)
4110 return;
4111
4112 rval = qla2x00_set_serdes_params(vha,
4113 le16_to_cpu(ha->fw_seriallink_options24[1]),
4114 le16_to_cpu(ha->fw_seriallink_options24[2]),
4115 le16_to_cpu(ha->fw_seriallink_options24[3]));
4116 if (rval != QLA_SUCCESS) {
4117 ql_log(ql_log_warn, vha, 0x0104,
4118 "Unable to update Serial Link options (%x).\n", rval);
4119 }
4120}
4121
4122void
4123qla2x00_config_rings(struct scsi_qla_host *vha)
4124{
4125 struct qla_hw_data *ha = vha->hw;
4126 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4127 struct req_que *req = ha->req_q_map[0];
4128 struct rsp_que *rsp = ha->rsp_q_map[0];
4129
4130
4131 ha->init_cb->request_q_outpointer = cpu_to_le16(0);
4132 ha->init_cb->response_q_inpointer = cpu_to_le16(0);
4133 ha->init_cb->request_q_length = cpu_to_le16(req->length);
4134 ha->init_cb->response_q_length = cpu_to_le16(rsp->length);
4135 put_unaligned_le64(req->dma, &ha->init_cb->request_q_address);
4136 put_unaligned_le64(rsp->dma, &ha->init_cb->response_q_address);
4137
4138 wrt_reg_word(ISP_REQ_Q_IN(ha, reg), 0);
4139 wrt_reg_word(ISP_REQ_Q_OUT(ha, reg), 0);
4140 wrt_reg_word(ISP_RSP_Q_IN(ha, reg), 0);
4141 wrt_reg_word(ISP_RSP_Q_OUT(ha, reg), 0);
4142 rd_reg_word(ISP_RSP_Q_OUT(ha, reg));
4143}
4144
4145void
4146qla24xx_config_rings(struct scsi_qla_host *vha)
4147{
4148 struct qla_hw_data *ha = vha->hw;
4149 device_reg_t *reg = ISP_QUE_REG(ha, 0);
4150 struct device_reg_2xxx __iomem *ioreg = &ha->iobase->isp;
4151 struct qla_msix_entry *msix;
4152 struct init_cb_24xx *icb;
4153 uint16_t rid = 0;
4154 struct req_que *req = ha->req_q_map[0];
4155 struct rsp_que *rsp = ha->rsp_q_map[0];
4156
4157
4158 icb = (struct init_cb_24xx *)ha->init_cb;
4159 icb->request_q_outpointer = cpu_to_le16(0);
4160 icb->response_q_inpointer = cpu_to_le16(0);
4161 icb->request_q_length = cpu_to_le16(req->length);
4162 icb->response_q_length = cpu_to_le16(rsp->length);
4163 put_unaligned_le64(req->dma, &icb->request_q_address);
4164 put_unaligned_le64(rsp->dma, &icb->response_q_address);
4165
4166
4167 icb->atio_q_inpointer = cpu_to_le16(0);
4168 icb->atio_q_length = cpu_to_le16(ha->tgt.atio_q_length);
4169 put_unaligned_le64(ha->tgt.atio_dma, &icb->atio_q_address);
4170
4171 if (IS_SHADOW_REG_CAPABLE(ha))
4172 icb->firmware_options_2 |= cpu_to_le32(BIT_30|BIT_29);
4173
4174 if (ha->mqenable || IS_QLA83XX(ha) || IS_QLA27XX(ha) ||
4175 IS_QLA28XX(ha)) {
4176 icb->qos = cpu_to_le16(QLA_DEFAULT_QUE_QOS);
4177 icb->rid = cpu_to_le16(rid);
4178 if (ha->flags.msix_enabled) {
4179 msix = &ha->msix_entries[1];
4180 ql_dbg(ql_dbg_init, vha, 0x0019,
4181 "Registering vector 0x%x for base que.\n",
4182 msix->entry);
4183 icb->msix = cpu_to_le16(msix->entry);
4184 }
4185
4186 if (MSB(rid))
4187 icb->firmware_options_2 |= cpu_to_le32(BIT_19);
4188
4189 if (LSB(rid))
4190 icb->firmware_options_2 |= cpu_to_le32(BIT_18);
4191
4192
4193 if ((ha->fw_attributes & BIT_6) && (IS_MSIX_NACK_CAPABLE(ha)) &&
4194 (ha->flags.msix_enabled)) {
4195 icb->firmware_options_2 &= cpu_to_le32(~BIT_22);
4196 ha->flags.disable_msix_handshake = 1;
4197 ql_dbg(ql_dbg_init, vha, 0x00fe,
4198 "MSIX Handshake Disable Mode turned on.\n");
4199 } else {
4200 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
4201 }
4202 icb->firmware_options_2 |= cpu_to_le32(BIT_23);
4203
4204 wrt_reg_dword(®->isp25mq.req_q_in, 0);
4205 wrt_reg_dword(®->isp25mq.req_q_out, 0);
4206 wrt_reg_dword(®->isp25mq.rsp_q_in, 0);
4207 wrt_reg_dword(®->isp25mq.rsp_q_out, 0);
4208 } else {
4209 wrt_reg_dword(®->isp24.req_q_in, 0);
4210 wrt_reg_dword(®->isp24.req_q_out, 0);
4211 wrt_reg_dword(®->isp24.rsp_q_in, 0);
4212 wrt_reg_dword(®->isp24.rsp_q_out, 0);
4213 }
4214
4215 qlt_24xx_config_rings(vha);
4216
4217
4218 if (ha->set_data_rate) {
4219 ql_dbg(ql_dbg_init, vha, 0x00fd,
4220 "Speed set by user : %s Gbps \n",
4221 qla2x00_get_link_speed_str(ha, ha->set_data_rate));
4222 icb->firmware_options_3 = cpu_to_le32(ha->set_data_rate << 13);
4223 }
4224
4225
4226 rd_reg_word(&ioreg->hccr);
4227}
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238int
4239qla2x00_init_rings(scsi_qla_host_t *vha)
4240{
4241 int rval;
4242 unsigned long flags = 0;
4243 int cnt, que;
4244 struct qla_hw_data *ha = vha->hw;
4245 struct req_que *req;
4246 struct rsp_que *rsp;
4247 struct mid_init_cb_24xx *mid_init_cb =
4248 (struct mid_init_cb_24xx *) ha->init_cb;
4249
4250 spin_lock_irqsave(&ha->hardware_lock, flags);
4251
4252
4253 for (que = 0; que < ha->max_req_queues; que++) {
4254 req = ha->req_q_map[que];
4255 if (!req || !test_bit(que, ha->req_qid_map))
4256 continue;
4257 req->out_ptr = (uint16_t *)(req->ring + req->length);
4258 *req->out_ptr = 0;
4259 for (cnt = 1; cnt < req->num_outstanding_cmds; cnt++)
4260 req->outstanding_cmds[cnt] = NULL;
4261
4262 req->current_outstanding_cmd = 1;
4263
4264
4265 req->ring_ptr = req->ring;
4266 req->ring_index = 0;
4267 req->cnt = req->length;
4268 }
4269
4270 for (que = 0; que < ha->max_rsp_queues; que++) {
4271 rsp = ha->rsp_q_map[que];
4272 if (!rsp || !test_bit(que, ha->rsp_qid_map))
4273 continue;
4274 rsp->in_ptr = (uint16_t *)(rsp->ring + rsp->length);
4275 *rsp->in_ptr = 0;
4276
4277 if (IS_QLAFX00(ha))
4278 qlafx00_init_response_q_entries(rsp);
4279 else
4280 qla2x00_init_response_q_entries(rsp);
4281 }
4282
4283 ha->tgt.atio_ring_ptr = ha->tgt.atio_ring;
4284 ha->tgt.atio_ring_index = 0;
4285
4286 qlt_init_atio_q_entries(vha);
4287
4288 ha->isp_ops->config_rings(vha);
4289
4290 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4291
4292 ql_dbg(ql_dbg_init, vha, 0x00d1, "Issue init firmware.\n");
4293
4294 if (IS_QLAFX00(ha)) {
4295 rval = qlafx00_init_firmware(vha, ha->init_cb_size);
4296 goto next_check;
4297 }
4298
4299
4300 ha->isp_ops->update_fw_options(vha);
4301
4302 if (ha->flags.npiv_supported) {
4303 if (ha->operating_mode == LOOP && !IS_CNA_CAPABLE(ha))
4304 ha->max_npiv_vports = MIN_MULTI_ID_FABRIC - 1;
4305 mid_init_cb->count = cpu_to_le16(ha->max_npiv_vports);
4306 }
4307
4308 if (IS_FWI2_CAPABLE(ha)) {
4309 mid_init_cb->options = cpu_to_le16(BIT_1);
4310 mid_init_cb->init_cb.execution_throttle =
4311 cpu_to_le16(ha->cur_fw_xcb_count);
4312 ha->flags.dport_enabled =
4313 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) &
4314 BIT_7) != 0;
4315 ql_dbg(ql_dbg_init, vha, 0x0191, "DPORT Support: %s.\n",
4316 (ha->flags.dport_enabled) ? "enabled" : "disabled");
4317
4318 ha->flags.fawwpn_enabled =
4319 (le32_to_cpu(mid_init_cb->init_cb.firmware_options_1) &
4320 BIT_6) != 0;
4321 ql_dbg(ql_dbg_init, vha, 0x00bc, "FA-WWPN Support: %s.\n",
4322 (ha->flags.fawwpn_enabled) ? "enabled" : "disabled");
4323 }
4324
4325 rval = qla2x00_init_firmware(vha, ha->init_cb_size);
4326next_check:
4327 if (rval) {
4328 ql_log(ql_log_fatal, vha, 0x00d2,
4329 "Init Firmware **** FAILED ****.\n");
4330 } else {
4331 ql_dbg(ql_dbg_init, vha, 0x00d3,
4332 "Init Firmware -- success.\n");
4333 QLA_FW_STARTED(ha);
4334 vha->u_ql2xexchoffld = vha->u_ql2xiniexchg = 0;
4335 }
4336
4337 return (rval);
4338}
4339
4340
4341
4342
4343
4344
4345
4346static int
4347qla2x00_fw_ready(scsi_qla_host_t *vha)
4348{
4349 int rval;
4350 unsigned long wtime, mtime, cs84xx_time;
4351 uint16_t min_wait;
4352 uint16_t wait_time;
4353 uint16_t state[6];
4354 struct qla_hw_data *ha = vha->hw;
4355
4356 if (IS_QLAFX00(vha->hw))
4357 return qlafx00_fw_ready(vha);
4358
4359
4360 if (IS_P3P_TYPE(ha))
4361 min_wait = 30;
4362 else
4363 min_wait = 20;
4364
4365
4366
4367
4368
4369 if ((wait_time = (ha->retry_count*ha->login_timeout) + 5) < min_wait) {
4370 wait_time = min_wait;
4371 }
4372
4373
4374 mtime = jiffies + (min_wait * HZ);
4375
4376
4377 wtime = jiffies + (wait_time * HZ);
4378
4379
4380 if (!vha->flags.init_done)
4381 ql_log(ql_log_info, vha, 0x801e,
4382 "Waiting for LIP to complete.\n");
4383
4384 do {
4385 memset(state, -1, sizeof(state));
4386 rval = qla2x00_get_firmware_state(vha, state);
4387 if (rval == QLA_SUCCESS) {
4388 if (state[0] < FSTATE_LOSS_OF_SYNC) {
4389 vha->device_flags &= ~DFLG_NO_CABLE;
4390 }
4391 if (IS_QLA84XX(ha) && state[0] != FSTATE_READY) {
4392 ql_dbg(ql_dbg_taskm, vha, 0x801f,
4393 "fw_state=%x 84xx=%x.\n", state[0],
4394 state[2]);
4395 if ((state[2] & FSTATE_LOGGED_IN) &&
4396 (state[2] & FSTATE_WAITING_FOR_VERIFY)) {
4397 ql_dbg(ql_dbg_taskm, vha, 0x8028,
4398 "Sending verify iocb.\n");
4399
4400 cs84xx_time = jiffies;
4401 rval = qla84xx_init_chip(vha);
4402 if (rval != QLA_SUCCESS) {
4403 ql_log(ql_log_warn,
4404 vha, 0x8007,
4405 "Init chip failed.\n");
4406 break;
4407 }
4408
4409
4410 cs84xx_time = jiffies - cs84xx_time;
4411 wtime += cs84xx_time;
4412 mtime += cs84xx_time;
4413 ql_dbg(ql_dbg_taskm, vha, 0x8008,
4414 "Increasing wait time by %ld. "
4415 "New time %ld.\n", cs84xx_time,
4416 wtime);
4417 }
4418 } else if (state[0] == FSTATE_READY) {
4419 ql_dbg(ql_dbg_taskm, vha, 0x8037,
4420 "F/W Ready - OK.\n");
4421
4422 qla2x00_get_retry_cnt(vha, &ha->retry_count,
4423 &ha->login_timeout, &ha->r_a_tov);
4424
4425 rval = QLA_SUCCESS;
4426 break;
4427 }
4428
4429 rval = QLA_FUNCTION_FAILED;
4430
4431 if (atomic_read(&vha->loop_down_timer) &&
4432 state[0] != FSTATE_READY) {
4433
4434
4435
4436 if (time_after_eq(jiffies, mtime)) {
4437 ql_log(ql_log_info, vha, 0x8038,
4438 "Cable is unplugged...\n");
4439
4440 vha->device_flags |= DFLG_NO_CABLE;
4441 break;
4442 }
4443 }
4444 } else {
4445
4446 if (time_after_eq(jiffies, mtime) ||
4447 ha->flags.isp82xx_fw_hung)
4448 break;
4449 }
4450
4451 if (time_after_eq(jiffies, wtime))
4452 break;
4453
4454
4455 msleep(500);
4456 } while (1);
4457
4458 ql_dbg(ql_dbg_taskm, vha, 0x803a,
4459 "fw_state=%x (%x, %x, %x, %x %x) curr time=%lx.\n", state[0],
4460 state[1], state[2], state[3], state[4], state[5], jiffies);
4461
4462 if (rval && !(vha->device_flags & DFLG_NO_CABLE)) {
4463 ql_log(ql_log_warn, vha, 0x803b,
4464 "Firmware ready **** FAILED ****.\n");
4465 }
4466
4467 return (rval);
4468}
4469
4470
4471
4472
4473
4474
4475
4476
4477
4478
4479
4480
4481
4482
4483static int
4484qla2x00_configure_hba(scsi_qla_host_t *vha)
4485{
4486 int rval;
4487 uint16_t loop_id;
4488 uint16_t topo;
4489 uint16_t sw_cap;
4490 uint8_t al_pa;
4491 uint8_t area;
4492 uint8_t domain;
4493 char connect_type[22];
4494 struct qla_hw_data *ha = vha->hw;
4495 scsi_qla_host_t *base_vha = pci_get_drvdata(ha->pdev);
4496 port_id_t id;
4497 unsigned long flags;
4498
4499
4500 rval = qla2x00_get_adapter_id(vha,
4501 &loop_id, &al_pa, &area, &domain, &topo, &sw_cap);
4502 if (rval != QLA_SUCCESS) {
4503 if (LOOP_TRANSITION(vha) || atomic_read(&ha->loop_down_timer) ||
4504 IS_CNA_CAPABLE(ha) ||
4505 (rval == QLA_COMMAND_ERROR && loop_id == 0x7)) {
4506 ql_dbg(ql_dbg_disc, vha, 0x2008,
4507 "Loop is in a transition state.\n");
4508 } else {
4509 ql_log(ql_log_warn, vha, 0x2009,
4510 "Unable to get host loop ID.\n");
4511 if (IS_FWI2_CAPABLE(ha) && (vha == base_vha) &&
4512 (rval == QLA_COMMAND_ERROR && loop_id == 0x1b)) {
4513 ql_log(ql_log_warn, vha, 0x1151,
4514 "Doing link init.\n");
4515 if (qla24xx_link_initialize(vha) == QLA_SUCCESS)
4516 return rval;
4517 }
4518 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
4519 }
4520 return (rval);
4521 }
4522
4523 if (topo == 4) {
4524 ql_log(ql_log_info, vha, 0x200a,
4525 "Cannot get topology - retrying.\n");
4526 return (QLA_FUNCTION_FAILED);
4527 }
4528
4529 vha->loop_id = loop_id;
4530
4531
4532 ha->min_external_loopid = SNS_FIRST_LOOP_ID;
4533 ha->operating_mode = LOOP;
4534 ha->switch_cap = 0;
4535
4536 switch (topo) {
4537 case 0:
4538 ql_dbg(ql_dbg_disc, vha, 0x200b, "HBA in NL topology.\n");
4539 ha->current_topology = ISP_CFG_NL;
4540 strcpy(connect_type, "(Loop)");
4541 break;
4542
4543 case 1:
4544 ql_dbg(ql_dbg_disc, vha, 0x200c, "HBA in FL topology.\n");
4545 ha->switch_cap = sw_cap;
4546 ha->current_topology = ISP_CFG_FL;
4547 strcpy(connect_type, "(FL_Port)");
4548 break;
4549
4550 case 2:
4551 ql_dbg(ql_dbg_disc, vha, 0x200d, "HBA in N P2P topology.\n");
4552 ha->operating_mode = P2P;
4553 ha->current_topology = ISP_CFG_N;
4554 strcpy(connect_type, "(N_Port-to-N_Port)");
4555 break;
4556
4557 case 3:
4558 ql_dbg(ql_dbg_disc, vha, 0x200e, "HBA in F P2P topology.\n");
4559 ha->switch_cap = sw_cap;
4560 ha->operating_mode = P2P;
4561 ha->current_topology = ISP_CFG_F;
4562 strcpy(connect_type, "(F_Port)");
4563 break;
4564
4565 default:
4566 ql_dbg(ql_dbg_disc, vha, 0x200f,
4567 "HBA in unknown topology %x, using NL.\n", topo);
4568 ha->current_topology = ISP_CFG_NL;
4569 strcpy(connect_type, "(Loop)");
4570 break;
4571 }
4572
4573
4574
4575 id.b.domain = domain;
4576 id.b.area = area;
4577 id.b.al_pa = al_pa;
4578 id.b.rsvd_1 = 0;
4579 spin_lock_irqsave(&ha->hardware_lock, flags);
4580 if (!(topo == 2 && ha->flags.n2n_bigger))
4581 qlt_update_host_map(vha, id);
4582 spin_unlock_irqrestore(&ha->hardware_lock, flags);
4583
4584 if (!vha->flags.init_done)
4585 ql_log(ql_log_info, vha, 0x2010,
4586 "Topology - %s, Host Loop address 0x%x.\n",
4587 connect_type, vha->loop_id);
4588
4589 return(rval);
4590}
4591
4592inline void
4593qla2x00_set_model_info(scsi_qla_host_t *vha, uint8_t *model, size_t len,
4594 const char *def)
4595{
4596 char *st, *en;
4597 uint16_t index;
4598 uint64_t zero[2] = { 0 };
4599 struct qla_hw_data *ha = vha->hw;
4600 int use_tbl = !IS_QLA24XX_TYPE(ha) && !IS_QLA25XX(ha) &&
4601 !IS_CNA_CAPABLE(ha) && !IS_QLA2031(ha);
4602
4603 if (len > sizeof(zero))
4604 len = sizeof(zero);
4605 if (memcmp(model, &zero, len) != 0) {
4606 memcpy(ha->model_number, model, len);
4607 st = en = ha->model_number;
4608 en += len - 1;
4609 while (en > st) {
4610 if (*en != 0x20 && *en != 0x00)
4611 break;
4612 *en-- = '\0';
4613 }
4614
4615 index = (ha->pdev->subsystem_device & 0xff);
4616 if (use_tbl &&
4617 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4618 index < QLA_MODEL_NAMES)
4619 strlcpy(ha->model_desc,
4620 qla2x00_model_name[index * 2 + 1],
4621 sizeof(ha->model_desc));
4622 } else {
4623 index = (ha->pdev->subsystem_device & 0xff);
4624 if (use_tbl &&
4625 ha->pdev->subsystem_vendor == PCI_VENDOR_ID_QLOGIC &&
4626 index < QLA_MODEL_NAMES) {
4627 strlcpy(ha->model_number,
4628 qla2x00_model_name[index * 2],
4629 sizeof(ha->model_number));
4630 strlcpy(ha->model_desc,
4631 qla2x00_model_name[index * 2 + 1],
4632 sizeof(ha->model_desc));
4633 } else {
4634 strlcpy(ha->model_number, def,
4635 sizeof(ha->model_number));
4636 }
4637 }
4638 if (IS_FWI2_CAPABLE(ha))
4639 qla2xxx_get_vpd_field(vha, "\x82", ha->model_desc,
4640 sizeof(ha->model_desc));
4641}
4642
4643
4644
4645
4646static void qla2xxx_nvram_wwn_from_ofw(scsi_qla_host_t *vha, nvram_t *nv)
4647{
4648#ifdef CONFIG_SPARC
4649 struct qla_hw_data *ha = vha->hw;
4650 struct pci_dev *pdev = ha->pdev;
4651 struct device_node *dp = pci_device_to_OF_node(pdev);
4652 const u8 *val;
4653 int len;
4654
4655 val = of_get_property(dp, "port-wwn", &len);
4656 if (val && len >= WWN_SIZE)
4657 memcpy(nv->port_name, val, WWN_SIZE);
4658
4659 val = of_get_property(dp, "node-wwn", &len);
4660 if (val && len >= WWN_SIZE)
4661 memcpy(nv->node_name, val, WWN_SIZE);
4662#endif
4663}
4664
4665
4666
4667
4668
4669
4670
4671
4672
4673
4674
4675
4676
4677
4678int
4679qla2x00_nvram_config(scsi_qla_host_t *vha)
4680{
4681 int rval;
4682 uint8_t chksum = 0;
4683 uint16_t cnt;
4684 uint8_t *dptr1, *dptr2;
4685 struct qla_hw_data *ha = vha->hw;
4686 init_cb_t *icb = ha->init_cb;
4687 nvram_t *nv = ha->nvram;
4688 uint8_t *ptr = ha->nvram;
4689 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
4690
4691 rval = QLA_SUCCESS;
4692
4693
4694 ha->nvram_size = sizeof(*nv);
4695 ha->nvram_base = 0;
4696 if (!IS_QLA2100(ha) && !IS_QLA2200(ha) && !IS_QLA2300(ha))
4697 if ((rd_reg_word(®->ctrl_status) >> 14) == 1)
4698 ha->nvram_base = 0x80;
4699
4700
4701 ha->isp_ops->read_nvram(vha, ptr, ha->nvram_base, ha->nvram_size);
4702 for (cnt = 0, chksum = 0; cnt < ha->nvram_size; cnt++)
4703 chksum += *ptr++;
4704
4705 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x010f,
4706 "Contents of NVRAM.\n");
4707 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0110,
4708 nv, ha->nvram_size);
4709
4710
4711 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
4712 nv->nvram_version < 1) {
4713
4714 ql_log(ql_log_warn, vha, 0x0064,
4715 "Inconsistent NVRAM detected: checksum=%#x id=%.4s version=%#x.\n",
4716 chksum, nv->id, nv->nvram_version);
4717 ql_log(ql_log_warn, vha, 0x0065,
4718 "Falling back to "
4719 "functioning (yet invalid -- WWPN) defaults.\n");
4720
4721
4722
4723
4724 memset(nv, 0, ha->nvram_size);
4725 nv->parameter_block_version = ICB_VERSION;
4726
4727 if (IS_QLA23XX(ha)) {
4728 nv->firmware_options[0] = BIT_2 | BIT_1;
4729 nv->firmware_options[1] = BIT_7 | BIT_5;
4730 nv->add_firmware_options[0] = BIT_5;
4731 nv->add_firmware_options[1] = BIT_5 | BIT_4;
4732 nv->frame_payload_size = cpu_to_le16(2048);
4733 nv->special_options[1] = BIT_7;
4734 } else if (IS_QLA2200(ha)) {
4735 nv->firmware_options[0] = BIT_2 | BIT_1;
4736 nv->firmware_options[1] = BIT_7 | BIT_5;
4737 nv->add_firmware_options[0] = BIT_5;
4738 nv->add_firmware_options[1] = BIT_5 | BIT_4;
4739 nv->frame_payload_size = cpu_to_le16(1024);
4740 } else if (IS_QLA2100(ha)) {
4741 nv->firmware_options[0] = BIT_3 | BIT_1;
4742 nv->firmware_options[1] = BIT_5;
4743 nv->frame_payload_size = cpu_to_le16(1024);
4744 }
4745
4746 nv->max_iocb_allocation = cpu_to_le16(256);
4747 nv->execution_throttle = cpu_to_le16(16);
4748 nv->retry_count = 8;
4749 nv->retry_delay = 1;
4750
4751 nv->port_name[0] = 33;
4752 nv->port_name[3] = 224;
4753 nv->port_name[4] = 139;
4754
4755 qla2xxx_nvram_wwn_from_ofw(vha, nv);
4756
4757 nv->login_timeout = 4;
4758
4759
4760
4761
4762 nv->host_p[1] = BIT_2;
4763 nv->reset_delay = 5;
4764 nv->port_down_retry_count = 8;
4765 nv->max_luns_per_target = cpu_to_le16(8);
4766 nv->link_down_timeout = 60;
4767
4768 rval = 1;
4769 }
4770
4771
4772 memset(icb, 0, ha->init_cb_size);
4773
4774
4775
4776
4777 nv->firmware_options[0] |= (BIT_6 | BIT_1);
4778 nv->firmware_options[0] &= ~(BIT_5 | BIT_4);
4779 nv->firmware_options[1] |= (BIT_5 | BIT_0);
4780 nv->firmware_options[1] &= ~BIT_4;
4781
4782 if (IS_QLA23XX(ha)) {
4783 nv->firmware_options[0] |= BIT_2;
4784 nv->firmware_options[0] &= ~BIT_3;
4785 nv->special_options[0] &= ~BIT_6;
4786 nv->add_firmware_options[1] |= BIT_5 | BIT_4;
4787
4788 if (IS_QLA2300(ha)) {
4789 if (ha->fb_rev == FPM_2310) {
4790 strcpy(ha->model_number, "QLA2310");
4791 } else {
4792 strcpy(ha->model_number, "QLA2300");
4793 }
4794 } else {
4795 qla2x00_set_model_info(vha, nv->model_number,
4796 sizeof(nv->model_number), "QLA23xx");
4797 }
4798 } else if (IS_QLA2200(ha)) {
4799 nv->firmware_options[0] |= BIT_2;
4800
4801
4802
4803
4804 if ((nv->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) ==
4805 (BIT_5 | BIT_4)) {
4806
4807 nv->add_firmware_options[0] &= ~(BIT_6 | BIT_5 | BIT_4);
4808 nv->add_firmware_options[0] |= BIT_5;
4809 }
4810 strcpy(ha->model_number, "QLA22xx");
4811 } else {
4812 strcpy(ha->model_number, "QLA2100");
4813 }
4814
4815
4816
4817
4818 dptr1 = (uint8_t *)icb;
4819 dptr2 = (uint8_t *)&nv->parameter_block_version;
4820 cnt = (uint8_t *)&icb->request_q_outpointer - (uint8_t *)&icb->version;
4821 while (cnt--)
4822 *dptr1++ = *dptr2++;
4823
4824
4825 dptr1 = (uint8_t *)icb->add_firmware_options;
4826 cnt = (uint8_t *)icb->reserved_3 - (uint8_t *)icb->add_firmware_options;
4827 while (cnt--)
4828 *dptr1++ = *dptr2++;
4829 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
4830
4831 if (nv->host_p[1] & BIT_7) {
4832 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
4833 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
4834 }
4835
4836
4837 if ((icb->firmware_options[1] & BIT_6) == 0) {
4838
4839
4840
4841
4842 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
4843 icb->node_name[0] &= 0xF0;
4844 }
4845
4846
4847
4848
4849
4850
4851
4852
4853
4854 if (nv->host_p[0] & BIT_7)
4855 ql2xextended_error_logging = QL_DBG_DEFAULT1_MASK;
4856 ha->flags.disable_risc_code_load = ((nv->host_p[0] & BIT_4) ? 1 : 0);
4857
4858 if (!IS_QLA2100(ha) && !IS_QLA2200(ha))
4859 ha->flags.disable_risc_code_load = 0;
4860 ha->flags.enable_lip_reset = ((nv->host_p[1] & BIT_1) ? 1 : 0);
4861 ha->flags.enable_lip_full_login = ((nv->host_p[1] & BIT_2) ? 1 : 0);
4862 ha->flags.enable_target_reset = ((nv->host_p[1] & BIT_3) ? 1 : 0);
4863 ha->flags.enable_led_scheme = (nv->special_options[1] & BIT_4) ? 1 : 0;
4864 ha->flags.disable_serdes = 0;
4865
4866 ha->operating_mode =
4867 (icb->add_firmware_options[0] & (BIT_6 | BIT_5 | BIT_4)) >> 4;
4868
4869 memcpy(ha->fw_seriallink_options, nv->seriallink_options,
4870 sizeof(ha->fw_seriallink_options));
4871
4872
4873 ha->serial0 = icb->port_name[5];
4874 ha->serial1 = icb->port_name[6];
4875 ha->serial2 = icb->port_name[7];
4876 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
4877 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
4878
4879 icb->execution_throttle = cpu_to_le16(0xFFFF);
4880
4881 ha->retry_count = nv->retry_count;
4882
4883
4884 if (nv->login_timeout != ql2xlogintimeout)
4885 nv->login_timeout = ql2xlogintimeout;
4886 if (nv->login_timeout < 4)
4887 nv->login_timeout = 4;
4888 ha->login_timeout = nv->login_timeout;
4889
4890
4891 ha->r_a_tov = 100;
4892
4893 ha->loop_reset_delay = nv->reset_delay;
4894
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905 if (nv->link_down_timeout == 0) {
4906 ha->loop_down_abort_time =
4907 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
4908 } else {
4909 ha->link_down_timeout = nv->link_down_timeout;
4910 ha->loop_down_abort_time =
4911 (LOOP_DOWN_TIME - ha->link_down_timeout);
4912 }
4913
4914
4915
4916
4917 ha->port_down_retry_count = nv->port_down_retry_count;
4918 if (qlport_down_retry)
4919 ha->port_down_retry_count = qlport_down_retry;
4920
4921 ha->login_retry_count = nv->retry_count;
4922 if (ha->port_down_retry_count == nv->port_down_retry_count &&
4923 ha->port_down_retry_count > 3)
4924 ha->login_retry_count = ha->port_down_retry_count;
4925 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
4926 ha->login_retry_count = ha->port_down_retry_count;
4927 if (ql2xloginretrycount)
4928 ha->login_retry_count = ql2xloginretrycount;
4929
4930 icb->lun_enables = cpu_to_le16(0);
4931 icb->command_resource_count = 0;
4932 icb->immediate_notify_resource_count = 0;
4933 icb->timeout = cpu_to_le16(0);
4934
4935 if (IS_QLA2100(ha) || IS_QLA2200(ha)) {
4936
4937 icb->firmware_options[0] &= ~BIT_3;
4938 icb->add_firmware_options[0] &=
4939 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4940 icb->add_firmware_options[0] |= BIT_2;
4941 icb->response_accumulation_timer = 3;
4942 icb->interrupt_delay_timer = 5;
4943
4944 vha->flags.process_response_queue = 1;
4945 } else {
4946
4947 if (!vha->flags.init_done) {
4948 ha->zio_mode = icb->add_firmware_options[0] &
4949 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
4950 ha->zio_timer = icb->interrupt_delay_timer ?
4951 icb->interrupt_delay_timer : 2;
4952 }
4953 icb->add_firmware_options[0] &=
4954 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0);
4955 vha->flags.process_response_queue = 0;
4956 if (ha->zio_mode != QLA_ZIO_DISABLED) {
4957 ha->zio_mode = QLA_ZIO_MODE_6;
4958
4959 ql_log(ql_log_info, vha, 0x0068,
4960 "ZIO mode %d enabled; timer delay (%d us).\n",
4961 ha->zio_mode, ha->zio_timer * 100);
4962
4963 icb->add_firmware_options[0] |= (uint8_t)ha->zio_mode;
4964 icb->interrupt_delay_timer = (uint8_t)ha->zio_timer;
4965 vha->flags.process_response_queue = 1;
4966 }
4967 }
4968
4969 if (rval) {
4970 ql_log(ql_log_warn, vha, 0x0069,
4971 "NVRAM configuration failed.\n");
4972 }
4973 return (rval);
4974}
4975
4976static void
4977qla2x00_rport_del(void *data)
4978{
4979 fc_port_t *fcport = data;
4980 struct fc_rport *rport;
4981 unsigned long flags;
4982
4983 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
4984 rport = fcport->drport ? fcport->drport : fcport->rport;
4985 fcport->drport = NULL;
4986 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
4987 if (rport) {
4988 ql_dbg(ql_dbg_disc, fcport->vha, 0x210b,
4989 "%s %8phN. rport %p roles %x\n",
4990 __func__, fcport->port_name, rport,
4991 rport->roles);
4992
4993 fc_remote_port_delete(rport);
4994 }
4995}
4996
4997void qla2x00_set_fcport_state(fc_port_t *fcport, int state)
4998{
4999 int old_state;
5000
5001 old_state = atomic_read(&fcport->state);
5002 atomic_set(&fcport->state, state);
5003
5004
5005 if (old_state && old_state != state) {
5006 ql_dbg(ql_dbg_disc, fcport->vha, 0x207d,
5007 "FCPort %8phC state transitioned from %s to %s - portid=%02x%02x%02x.\n",
5008 fcport->port_name, port_state_str[old_state],
5009 port_state_str[state], fcport->d_id.b.domain,
5010 fcport->d_id.b.area, fcport->d_id.b.al_pa);
5011 }
5012}
5013
5014
5015
5016
5017
5018
5019
5020
5021fc_port_t *
5022qla2x00_alloc_fcport(scsi_qla_host_t *vha, gfp_t flags)
5023{
5024 fc_port_t *fcport;
5025
5026 fcport = kzalloc(sizeof(fc_port_t), flags);
5027 if (!fcport)
5028 return NULL;
5029
5030 fcport->ct_desc.ct_sns = dma_alloc_coherent(&vha->hw->pdev->dev,
5031 sizeof(struct ct_sns_pkt), &fcport->ct_desc.ct_sns_dma,
5032 flags);
5033 if (!fcport->ct_desc.ct_sns) {
5034 ql_log(ql_log_warn, vha, 0xd049,
5035 "Failed to allocate ct_sns request.\n");
5036 kfree(fcport);
5037 return NULL;
5038 }
5039
5040
5041 fcport->vha = vha;
5042 fcport->port_type = FCT_UNKNOWN;
5043 fcport->loop_id = FC_NO_LOOP_ID;
5044 qla2x00_set_fcport_state(fcport, FCS_UNCONFIGURED);
5045 fcport->supported_classes = FC_COS_UNSPECIFIED;
5046 fcport->fp_speed = PORT_SPEED_UNKNOWN;
5047
5048 fcport->disc_state = DSC_DELETED;
5049 fcport->fw_login_state = DSC_LS_PORT_UNAVAIL;
5050 fcport->deleted = QLA_SESS_DELETED;
5051 fcport->login_retry = vha->hw->login_retry_count;
5052 fcport->chip_reset = vha->hw->base_qpair->chip_reset;
5053 fcport->logout_on_delete = 1;
5054 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
5055 fcport->tgt_short_link_down_cnt = 0;
5056 fcport->dev_loss_tmo = 0;
5057
5058 if (!fcport->ct_desc.ct_sns) {
5059 ql_log(ql_log_warn, vha, 0xd049,
5060 "Failed to allocate ct_sns request.\n");
5061 kfree(fcport);
5062 return NULL;
5063 }
5064
5065 INIT_WORK(&fcport->del_work, qla24xx_delete_sess_fn);
5066 INIT_WORK(&fcport->free_work, qlt_free_session_done);
5067 INIT_WORK(&fcport->reg_work, qla_register_fcport_fn);
5068 INIT_LIST_HEAD(&fcport->gnl_entry);
5069 INIT_LIST_HEAD(&fcport->list);
5070
5071 INIT_LIST_HEAD(&fcport->sess_cmd_list);
5072 spin_lock_init(&fcport->sess_cmd_lock);
5073
5074 return fcport;
5075}
5076
5077void
5078qla2x00_free_fcport(fc_port_t *fcport)
5079{
5080 if (fcport->ct_desc.ct_sns) {
5081 dma_free_coherent(&fcport->vha->hw->pdev->dev,
5082 sizeof(struct ct_sns_pkt), fcport->ct_desc.ct_sns,
5083 fcport->ct_desc.ct_sns_dma);
5084
5085 fcport->ct_desc.ct_sns = NULL;
5086 }
5087 list_del(&fcport->list);
5088 qla2x00_clear_loop_id(fcport);
5089 kfree(fcport);
5090}
5091
5092static void qla_get_login_template(scsi_qla_host_t *vha)
5093{
5094 struct qla_hw_data *ha = vha->hw;
5095 int rval;
5096 u32 *bp, sz;
5097 __be32 *q;
5098
5099 memset(ha->init_cb, 0, ha->init_cb_size);
5100 sz = min_t(int, sizeof(struct fc_els_flogi), ha->init_cb_size);
5101 rval = qla24xx_get_port_login_templ(vha, ha->init_cb_dma,
5102 ha->init_cb, sz);
5103 if (rval != QLA_SUCCESS) {
5104 ql_dbg(ql_dbg_init, vha, 0x00d1,
5105 "PLOGI ELS param read fail.\n");
5106 return;
5107 }
5108 q = (__be32 *)&ha->plogi_els_payld.fl_csp;
5109
5110 bp = (uint32_t *)ha->init_cb;
5111 cpu_to_be32_array(q, bp, sz / 4);
5112 ha->flags.plogi_template_valid = 1;
5113}
5114
5115
5116
5117
5118
5119
5120
5121
5122
5123
5124
5125
5126
5127static int
5128qla2x00_configure_loop(scsi_qla_host_t *vha)
5129{
5130 int rval;
5131 unsigned long flags, save_flags;
5132 struct qla_hw_data *ha = vha->hw;
5133
5134 rval = QLA_SUCCESS;
5135
5136
5137 if (test_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags)) {
5138 rval = qla2x00_configure_hba(vha);
5139 if (rval != QLA_SUCCESS) {
5140 ql_dbg(ql_dbg_disc, vha, 0x2013,
5141 "Unable to configure HBA.\n");
5142 return (rval);
5143 }
5144 }
5145
5146 save_flags = flags = vha->dpc_flags;
5147 ql_dbg(ql_dbg_disc, vha, 0x2014,
5148 "Configure loop -- dpc flags = 0x%lx.\n", flags);
5149
5150
5151
5152
5153
5154 clear_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5155 clear_bit(RSCN_UPDATE, &vha->dpc_flags);
5156
5157 qla2x00_get_data_rate(vha);
5158 qla_get_login_template(vha);
5159
5160
5161 if ((ha->current_topology == ISP_CFG_FL ||
5162 ha->current_topology == ISP_CFG_F) &&
5163 (test_bit(LOCAL_LOOP_UPDATE, &flags))) {
5164
5165 set_bit(RSCN_UPDATE, &flags);
5166 clear_bit(LOCAL_LOOP_UPDATE, &flags);
5167
5168 } else if (ha->current_topology == ISP_CFG_NL ||
5169 ha->current_topology == ISP_CFG_N) {
5170 clear_bit(RSCN_UPDATE, &flags);
5171 set_bit(LOCAL_LOOP_UPDATE, &flags);
5172 } else if (!vha->flags.online ||
5173 (test_bit(ABORT_ISP_ACTIVE, &flags))) {
5174 set_bit(RSCN_UPDATE, &flags);
5175 set_bit(LOCAL_LOOP_UPDATE, &flags);
5176 }
5177
5178 if (test_bit(LOCAL_LOOP_UPDATE, &flags)) {
5179 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5180 ql_dbg(ql_dbg_disc, vha, 0x2015,
5181 "Loop resync needed, failing.\n");
5182 rval = QLA_FUNCTION_FAILED;
5183 } else
5184 rval = qla2x00_configure_local_loop(vha);
5185 }
5186
5187 if (rval == QLA_SUCCESS && test_bit(RSCN_UPDATE, &flags)) {
5188 if (LOOP_TRANSITION(vha)) {
5189 ql_dbg(ql_dbg_disc, vha, 0x2099,
5190 "Needs RSCN update and loop transition.\n");
5191 rval = QLA_FUNCTION_FAILED;
5192 }
5193 else
5194 rval = qla2x00_configure_fabric(vha);
5195 }
5196
5197 if (rval == QLA_SUCCESS) {
5198 if (atomic_read(&vha->loop_down_timer) ||
5199 test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5200 rval = QLA_FUNCTION_FAILED;
5201 } else {
5202 atomic_set(&vha->loop_state, LOOP_READY);
5203 ql_dbg(ql_dbg_disc, vha, 0x2069,
5204 "LOOP READY.\n");
5205 ha->flags.fw_init_done = 1;
5206
5207
5208
5209
5210
5211 if (qla_tgt_mode_enabled(vha) ||
5212 qla_dual_mode_enabled(vha)) {
5213 spin_lock_irqsave(&ha->tgt.atio_lock, flags);
5214 qlt_24xx_process_atio_queue(vha, 0);
5215 spin_unlock_irqrestore(&ha->tgt.atio_lock,
5216 flags);
5217 }
5218 }
5219 }
5220
5221 if (rval) {
5222 ql_dbg(ql_dbg_disc, vha, 0x206a,
5223 "%s *** FAILED ***.\n", __func__);
5224 } else {
5225 ql_dbg(ql_dbg_disc, vha, 0x206b,
5226 "%s: exiting normally.\n", __func__);
5227 }
5228
5229
5230 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags)) {
5231 if (test_bit(LOCAL_LOOP_UPDATE, &save_flags))
5232 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5233 if (test_bit(RSCN_UPDATE, &save_flags)) {
5234 set_bit(RSCN_UPDATE, &vha->dpc_flags);
5235 }
5236 }
5237
5238 return (rval);
5239}
5240
5241static int qla2x00_configure_n2n_loop(scsi_qla_host_t *vha)
5242{
5243 unsigned long flags;
5244 fc_port_t *fcport;
5245
5246 if (test_and_clear_bit(N2N_LOGIN_NEEDED, &vha->dpc_flags))
5247 set_bit(RELOGIN_NEEDED, &vha->dpc_flags);
5248
5249 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5250 if (fcport->n2n_flag) {
5251 qla24xx_fcport_handle_login(vha, fcport);
5252 return QLA_SUCCESS;
5253 }
5254 }
5255
5256 spin_lock_irqsave(&vha->work_lock, flags);
5257 vha->scan.scan_retry++;
5258 spin_unlock_irqrestore(&vha->work_lock, flags);
5259
5260 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5261 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5262 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5263 }
5264 return QLA_FUNCTION_FAILED;
5265}
5266
5267
5268
5269
5270
5271
5272
5273
5274
5275
5276
5277static int
5278qla2x00_configure_local_loop(scsi_qla_host_t *vha)
5279{
5280 int rval, rval2;
5281 int found_devs;
5282 int found;
5283 fc_port_t *fcport, *new_fcport;
5284 uint16_t index;
5285 uint16_t entries;
5286 struct gid_list_info *gid;
5287 uint16_t loop_id;
5288 uint8_t domain, area, al_pa;
5289 struct qla_hw_data *ha = vha->hw;
5290 unsigned long flags;
5291
5292
5293 if (N2N_TOPO(ha))
5294 return qla2x00_configure_n2n_loop(vha);
5295
5296 found_devs = 0;
5297 new_fcport = NULL;
5298 entries = MAX_FIBRE_DEVICES_LOOP;
5299
5300
5301 memset(ha->gid_list, 0, qla2x00_gid_list_size(ha));
5302 rval = qla2x00_get_id_list(vha, ha->gid_list, ha->gid_list_dma,
5303 &entries);
5304 if (rval != QLA_SUCCESS)
5305 goto err;
5306
5307 ql_dbg(ql_dbg_disc, vha, 0x2011,
5308 "Entries in ID list (%d).\n", entries);
5309 ql_dump_buffer(ql_dbg_disc + ql_dbg_buffer, vha, 0x2075,
5310 ha->gid_list, entries * sizeof(*ha->gid_list));
5311
5312 if (entries == 0) {
5313 spin_lock_irqsave(&vha->work_lock, flags);
5314 vha->scan.scan_retry++;
5315 spin_unlock_irqrestore(&vha->work_lock, flags);
5316
5317 if (vha->scan.scan_retry < MAX_SCAN_RETRIES) {
5318 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5319 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5320 }
5321 } else {
5322 vha->scan.scan_retry = 0;
5323 }
5324
5325 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5326 fcport->scan_state = QLA_FCPORT_SCAN;
5327 }
5328
5329
5330 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5331 if (new_fcport == NULL) {
5332 ql_log(ql_log_warn, vha, 0x2012,
5333 "Memory allocation failed for fcport.\n");
5334 rval = QLA_MEMORY_ALLOC_FAILED;
5335 goto err;
5336 }
5337 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5338
5339
5340 gid = ha->gid_list;
5341 for (index = 0; index < entries; index++) {
5342 domain = gid->domain;
5343 area = gid->area;
5344 al_pa = gid->al_pa;
5345 if (IS_QLA2100(ha) || IS_QLA2200(ha))
5346 loop_id = gid->loop_id_2100;
5347 else
5348 loop_id = le16_to_cpu(gid->loop_id);
5349 gid = (void *)gid + ha->gid_list_info_size;
5350
5351
5352 if ((domain & 0xf0) == 0xf0)
5353 continue;
5354
5355
5356 if (area && domain && ((area != vha->d_id.b.area) ||
5357 (domain != vha->d_id.b.domain)) &&
5358 (ha->current_topology == ISP_CFG_NL))
5359 continue;
5360
5361
5362
5363 if (loop_id > LAST_LOCAL_LOOP_ID)
5364 continue;
5365
5366 memset(new_fcport->port_name, 0, WWN_SIZE);
5367
5368
5369 new_fcport->d_id.b.domain = domain;
5370 new_fcport->d_id.b.area = area;
5371 new_fcport->d_id.b.al_pa = al_pa;
5372 new_fcport->loop_id = loop_id;
5373 new_fcport->scan_state = QLA_FCPORT_FOUND;
5374
5375 rval2 = qla2x00_get_port_database(vha, new_fcport, 0);
5376 if (rval2 != QLA_SUCCESS) {
5377 ql_dbg(ql_dbg_disc, vha, 0x2097,
5378 "Failed to retrieve fcport information "
5379 "-- get_port_database=%x, loop_id=0x%04x.\n",
5380 rval2, new_fcport->loop_id);
5381
5382 if (ha->current_topology != ISP_CFG_N) {
5383 ql_dbg(ql_dbg_disc, vha, 0x2105,
5384 "Scheduling resync.\n");
5385 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5386 continue;
5387 }
5388 }
5389
5390 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5391
5392 found = 0;
5393 fcport = NULL;
5394 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5395 if (memcmp(new_fcport->port_name, fcport->port_name,
5396 WWN_SIZE))
5397 continue;
5398
5399 fcport->flags &= ~FCF_FABRIC_DEVICE;
5400 fcport->loop_id = new_fcport->loop_id;
5401 fcport->port_type = new_fcport->port_type;
5402 fcport->d_id.b24 = new_fcport->d_id.b24;
5403 memcpy(fcport->node_name, new_fcport->node_name,
5404 WWN_SIZE);
5405 fcport->scan_state = QLA_FCPORT_FOUND;
5406 found++;
5407 break;
5408 }
5409
5410 if (!found) {
5411
5412 list_add_tail(&new_fcport->list, &vha->vp_fcports);
5413
5414
5415 fcport = new_fcport;
5416
5417 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5418
5419 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5420
5421 if (new_fcport == NULL) {
5422 ql_log(ql_log_warn, vha, 0xd031,
5423 "Failed to allocate memory for fcport.\n");
5424 rval = QLA_MEMORY_ALLOC_FAILED;
5425 goto err;
5426 }
5427 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
5428 new_fcport->flags &= ~FCF_FABRIC_DEVICE;
5429 }
5430
5431 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
5432
5433
5434 fcport->fp_speed = ha->link_data_rate;
5435
5436 found_devs++;
5437 }
5438
5439 list_for_each_entry(fcport, &vha->vp_fcports, list) {
5440 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5441 break;
5442
5443 if (fcport->scan_state == QLA_FCPORT_SCAN) {
5444 if ((qla_dual_mode_enabled(vha) ||
5445 qla_ini_mode_enabled(vha)) &&
5446 atomic_read(&fcport->state) == FCS_ONLINE) {
5447 qla2x00_mark_device_lost(vha, fcport,
5448 ql2xplogiabsentdevice);
5449 if (fcport->loop_id != FC_NO_LOOP_ID &&
5450 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
5451 fcport->port_type != FCT_INITIATOR &&
5452 fcport->port_type != FCT_BROADCAST) {
5453 ql_dbg(ql_dbg_disc, vha, 0x20f0,
5454 "%s %d %8phC post del sess\n",
5455 __func__, __LINE__,
5456 fcport->port_name);
5457
5458 qlt_schedule_sess_for_deletion(fcport);
5459 continue;
5460 }
5461 }
5462 }
5463
5464 if (fcport->scan_state == QLA_FCPORT_FOUND)
5465 qla24xx_fcport_handle_login(vha, fcport);
5466 }
5467
5468 qla2x00_free_fcport(new_fcport);
5469
5470 return rval;
5471
5472err:
5473 ql_dbg(ql_dbg_disc, vha, 0x2098,
5474 "Configure local loop error exit: rval=%x.\n", rval);
5475 return rval;
5476}
5477
5478static void
5479qla2x00_iidma_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
5480{
5481 int rval;
5482 uint16_t mb[MAILBOX_REGISTER_COUNT];
5483 struct qla_hw_data *ha = vha->hw;
5484
5485 if (!IS_IIDMA_CAPABLE(ha))
5486 return;
5487
5488 if (atomic_read(&fcport->state) != FCS_ONLINE)
5489 return;
5490
5491 if (fcport->fp_speed == PORT_SPEED_UNKNOWN ||
5492 fcport->fp_speed > ha->link_data_rate ||
5493 !ha->flags.gpsc_supported)
5494 return;
5495
5496 rval = qla2x00_set_idma_speed(vha, fcport->loop_id, fcport->fp_speed,
5497 mb);
5498 if (rval != QLA_SUCCESS) {
5499 ql_dbg(ql_dbg_disc, vha, 0x2004,
5500 "Unable to adjust iIDMA %8phN -- %04x %x %04x %04x.\n",
5501 fcport->port_name, rval, fcport->fp_speed, mb[0], mb[1]);
5502 } else {
5503 ql_dbg(ql_dbg_disc, vha, 0x2005,
5504 "iIDMA adjusted to %s GB/s (%X) on %8phN.\n",
5505 qla2x00_get_link_speed_str(ha, fcport->fp_speed),
5506 fcport->fp_speed, fcport->port_name);
5507 }
5508}
5509
5510void qla_do_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5511{
5512 qla2x00_iidma_fcport(vha, fcport);
5513 qla24xx_update_fcport_fcp_prio(vha, fcport);
5514}
5515
5516int qla_post_iidma_work(struct scsi_qla_host *vha, fc_port_t *fcport)
5517{
5518 struct qla_work_evt *e;
5519
5520 e = qla2x00_alloc_work(vha, QLA_EVT_IIDMA);
5521 if (!e)
5522 return QLA_FUNCTION_FAILED;
5523
5524 e->u.fcport.fcport = fcport;
5525 return qla2x00_post_work(vha, e);
5526}
5527
5528
5529static void
5530qla2x00_reg_remote_port(scsi_qla_host_t *vha, fc_port_t *fcport)
5531{
5532 struct fc_rport_identifiers rport_ids;
5533 struct fc_rport *rport;
5534 unsigned long flags;
5535
5536 if (atomic_read(&fcport->state) == FCS_ONLINE)
5537 return;
5538
5539 rport_ids.node_name = wwn_to_u64(fcport->node_name);
5540 rport_ids.port_name = wwn_to_u64(fcport->port_name);
5541 rport_ids.port_id = fcport->d_id.b.domain << 16 |
5542 fcport->d_id.b.area << 8 | fcport->d_id.b.al_pa;
5543 rport_ids.roles = FC_RPORT_ROLE_UNKNOWN;
5544 fcport->rport = rport = fc_remote_port_add(vha->host, 0, &rport_ids);
5545 if (!rport) {
5546 ql_log(ql_log_warn, vha, 0x2006,
5547 "Unable to allocate fc remote port.\n");
5548 return;
5549 }
5550
5551 spin_lock_irqsave(fcport->vha->host->host_lock, flags);
5552 *((fc_port_t **)rport->dd_data) = fcport;
5553 spin_unlock_irqrestore(fcport->vha->host->host_lock, flags);
5554 fcport->dev_loss_tmo = rport->dev_loss_tmo;
5555
5556 rport->supported_classes = fcport->supported_classes;
5557
5558 rport_ids.roles = FC_PORT_ROLE_UNKNOWN;
5559 if (fcport->port_type == FCT_INITIATOR)
5560 rport_ids.roles |= FC_PORT_ROLE_FCP_INITIATOR;
5561 if (fcport->port_type == FCT_TARGET)
5562 rport_ids.roles |= FC_PORT_ROLE_FCP_TARGET;
5563 if (fcport->port_type & FCT_NVME_INITIATOR)
5564 rport_ids.roles |= FC_PORT_ROLE_NVME_INITIATOR;
5565 if (fcport->port_type & FCT_NVME_TARGET)
5566 rport_ids.roles |= FC_PORT_ROLE_NVME_TARGET;
5567 if (fcport->port_type & FCT_NVME_DISCOVERY)
5568 rport_ids.roles |= FC_PORT_ROLE_NVME_DISCOVERY;
5569
5570 fc_remote_port_rolechg(rport, rport_ids.roles);
5571
5572 ql_dbg(ql_dbg_disc, vha, 0x20ee,
5573 "%s: %8phN. rport %ld:0:%d (%p) is %s mode\n",
5574 __func__, fcport->port_name, vha->host_no,
5575 rport->scsi_target_id, rport,
5576 (fcport->port_type == FCT_TARGET) ? "tgt" :
5577 ((fcport->port_type & FCT_NVME) ? "nvme" : "ini"));
5578}
5579
5580
5581
5582
5583
5584
5585
5586
5587
5588
5589
5590
5591
5592
5593
5594
5595void
5596qla2x00_update_fcport(scsi_qla_host_t *vha, fc_port_t *fcport)
5597{
5598 if (IS_SW_RESV_ADDR(fcport->d_id))
5599 return;
5600
5601 ql_dbg(ql_dbg_disc, vha, 0x20ef, "%s %8phC\n",
5602 __func__, fcport->port_name);
5603
5604 qla2x00_set_fcport_disc_state(fcport, DSC_UPD_FCPORT);
5605 fcport->login_retry = vha->hw->login_retry_count;
5606 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
5607 fcport->deleted = 0;
5608 if (vha->hw->current_topology == ISP_CFG_NL)
5609 fcport->logout_on_delete = 0;
5610 else
5611 fcport->logout_on_delete = 1;
5612 fcport->n2n_chip_reset = fcport->n2n_link_reset_cnt = 0;
5613
5614 if (fcport->tgt_link_down_time < fcport->dev_loss_tmo) {
5615 fcport->tgt_short_link_down_cnt++;
5616 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
5617 }
5618
5619 switch (vha->hw->current_topology) {
5620 case ISP_CFG_N:
5621 case ISP_CFG_NL:
5622 fcport->keep_nport_handle = 1;
5623 break;
5624 default:
5625 break;
5626 }
5627
5628 qla2x00_iidma_fcport(vha, fcport);
5629
5630 qla2x00_dfs_create_rport(vha, fcport);
5631
5632 if (NVME_TARGET(vha->hw, fcport)) {
5633 qla_nvme_register_remote(vha, fcport);
5634 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE);
5635 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
5636 return;
5637 }
5638
5639 qla24xx_update_fcport_fcp_prio(vha, fcport);
5640
5641 switch (vha->host->active_mode) {
5642 case MODE_INITIATOR:
5643 qla2x00_reg_remote_port(vha, fcport);
5644 break;
5645 case MODE_TARGET:
5646 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5647 !vha->vha_tgt.qla_tgt->tgt_stopped)
5648 qlt_fc_port_added(vha, fcport);
5649 break;
5650 case MODE_DUAL:
5651 qla2x00_reg_remote_port(vha, fcport);
5652 if (!vha->vha_tgt.qla_tgt->tgt_stop &&
5653 !vha->vha_tgt.qla_tgt->tgt_stopped)
5654 qlt_fc_port_added(vha, fcport);
5655 break;
5656 default:
5657 break;
5658 }
5659
5660 qla2x00_set_fcport_state(fcport, FCS_ONLINE);
5661
5662 if (IS_IIDMA_CAPABLE(vha->hw) && vha->hw->flags.gpsc_supported) {
5663 if (fcport->id_changed) {
5664 fcport->id_changed = 0;
5665 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5666 "%s %d %8phC post gfpnid fcp_cnt %d\n",
5667 __func__, __LINE__, fcport->port_name,
5668 vha->fcport_count);
5669 qla24xx_post_gfpnid_work(vha, fcport);
5670 } else {
5671 ql_dbg(ql_dbg_disc, vha, 0x20d7,
5672 "%s %d %8phC post gpsc fcp_cnt %d\n",
5673 __func__, __LINE__, fcport->port_name,
5674 vha->fcport_count);
5675 qla24xx_post_gpsc_work(vha, fcport);
5676 }
5677 }
5678
5679 qla2x00_set_fcport_disc_state(fcport, DSC_LOGIN_COMPLETE);
5680}
5681
5682void qla_register_fcport_fn(struct work_struct *work)
5683{
5684 fc_port_t *fcport = container_of(work, struct fc_port, reg_work);
5685 u32 rscn_gen = fcport->rscn_gen;
5686 u16 data[2];
5687
5688 if (IS_SW_RESV_ADDR(fcport->d_id))
5689 return;
5690
5691 qla2x00_update_fcport(fcport->vha, fcport);
5692
5693 if (rscn_gen != fcport->rscn_gen) {
5694
5695 switch (fcport->next_disc_state) {
5696 case DSC_DELETE_PEND:
5697 qlt_schedule_sess_for_deletion(fcport);
5698 break;
5699 case DSC_ADISC:
5700 data[0] = data[1] = 0;
5701 qla2x00_post_async_adisc_work(fcport->vha, fcport,
5702 data);
5703 break;
5704 default:
5705 break;
5706 }
5707 }
5708}
5709
5710
5711
5712
5713
5714
5715
5716
5717
5718
5719
5720
5721static int
5722qla2x00_configure_fabric(scsi_qla_host_t *vha)
5723{
5724 int rval;
5725 fc_port_t *fcport;
5726 uint16_t mb[MAILBOX_REGISTER_COUNT];
5727 uint16_t loop_id;
5728 LIST_HEAD(new_fcports);
5729 struct qla_hw_data *ha = vha->hw;
5730 int discovery_gen;
5731
5732
5733 if (IS_FWI2_CAPABLE(ha))
5734 loop_id = NPH_F_PORT;
5735 else
5736 loop_id = SNS_FL_PORT;
5737 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_node_name, 1);
5738 if (rval != QLA_SUCCESS) {
5739 ql_dbg(ql_dbg_disc, vha, 0x20a0,
5740 "MBX_GET_PORT_NAME failed, No FL Port.\n");
5741
5742 vha->device_flags &= ~SWITCH_FOUND;
5743 return (QLA_SUCCESS);
5744 }
5745 vha->device_flags |= SWITCH_FOUND;
5746
5747 rval = qla2x00_get_port_name(vha, loop_id, vha->fabric_port_name, 0);
5748 if (rval != QLA_SUCCESS)
5749 ql_dbg(ql_dbg_disc, vha, 0x20ff,
5750 "Failed to get Fabric Port Name\n");
5751
5752 if (qla_tgt_mode_enabled(vha) || qla_dual_mode_enabled(vha)) {
5753 rval = qla2x00_send_change_request(vha, 0x3, 0);
5754 if (rval != QLA_SUCCESS)
5755 ql_log(ql_log_warn, vha, 0x121,
5756 "Failed to enable receiving of RSCN requests: 0x%x.\n",
5757 rval);
5758 }
5759
5760 do {
5761 qla2x00_mgmt_svr_login(vha);
5762
5763
5764 loop_id = NPH_SNS_LID(ha);
5765 rval = ha->isp_ops->fabric_login(vha, loop_id, 0xff, 0xff,
5766 0xfc, mb, BIT_1|BIT_0);
5767 if (rval != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
5768 ql_dbg(ql_dbg_disc, vha, 0x20a1,
5769 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x mb[2]=%x mb[6]=%x mb[7]=%x (%x).\n",
5770 loop_id, mb[0], mb[1], mb[2], mb[6], mb[7], rval);
5771 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5772 return rval;
5773 }
5774
5775
5776 if (ql2xfdmienable &&
5777 test_and_clear_bit(REGISTER_FDMI_NEEDED, &vha->dpc_flags))
5778 qla2x00_fdmi_register(vha);
5779
5780 if (test_and_clear_bit(REGISTER_FC4_NEEDED, &vha->dpc_flags)) {
5781 if (qla2x00_rft_id(vha)) {
5782
5783 ql_dbg(ql_dbg_disc, vha, 0x20a2,
5784 "Register FC-4 TYPE failed.\n");
5785 if (test_bit(LOOP_RESYNC_NEEDED,
5786 &vha->dpc_flags))
5787 break;
5788 }
5789 if (qla2x00_rff_id(vha, FC4_TYPE_FCP_SCSI)) {
5790
5791 ql_dbg(ql_dbg_disc, vha, 0x209a,
5792 "Register FC-4 Features failed.\n");
5793 if (test_bit(LOOP_RESYNC_NEEDED,
5794 &vha->dpc_flags))
5795 break;
5796 }
5797 if (vha->flags.nvme_enabled) {
5798 if (qla2x00_rff_id(vha, FC_TYPE_NVME)) {
5799 ql_dbg(ql_dbg_disc, vha, 0x2049,
5800 "Register NVME FC Type Features failed.\n");
5801 }
5802 }
5803 if (qla2x00_rnn_id(vha)) {
5804
5805 ql_dbg(ql_dbg_disc, vha, 0x2104,
5806 "Register Node Name failed.\n");
5807 if (test_bit(LOOP_RESYNC_NEEDED,
5808 &vha->dpc_flags))
5809 break;
5810 } else if (qla2x00_rsnn_nn(vha)) {
5811
5812 ql_dbg(ql_dbg_disc, vha, 0x209b,
5813 "Register Symbolic Node Name failed.\n");
5814 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5815 break;
5816 }
5817 }
5818
5819
5820
5821
5822
5823
5824
5825
5826 qlt_do_generation_tick(vha, &discovery_gen);
5827
5828 if (USE_ASYNC_SCAN(ha)) {
5829 rval = qla24xx_async_gpnft(vha, FC4_TYPE_FCP_SCSI,
5830 NULL);
5831 if (rval)
5832 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5833 } else {
5834 list_for_each_entry(fcport, &vha->vp_fcports, list)
5835 fcport->scan_state = QLA_FCPORT_SCAN;
5836
5837 rval = qla2x00_find_all_fabric_devs(vha);
5838 }
5839 if (rval != QLA_SUCCESS)
5840 break;
5841 } while (0);
5842
5843 if (!vha->nvme_local_port && vha->flags.nvme_enabled)
5844 qla_nvme_register_hba(vha);
5845
5846 if (rval)
5847 ql_dbg(ql_dbg_disc, vha, 0x2068,
5848 "Configure fabric error exit rval=%d.\n", rval);
5849
5850 return (rval);
5851}
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863
5864
5865
5866static int
5867qla2x00_find_all_fabric_devs(scsi_qla_host_t *vha)
5868{
5869 int rval;
5870 uint16_t loop_id;
5871 fc_port_t *fcport, *new_fcport;
5872 int found;
5873
5874 sw_info_t *swl;
5875 int swl_idx;
5876 int first_dev, last_dev;
5877 port_id_t wrap = {}, nxt_d_id;
5878 struct qla_hw_data *ha = vha->hw;
5879 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
5880 unsigned long flags;
5881
5882 rval = QLA_SUCCESS;
5883
5884
5885 if (!ha->swl)
5886 ha->swl = kcalloc(ha->max_fibre_devices, sizeof(sw_info_t),
5887 GFP_KERNEL);
5888 swl = ha->swl;
5889 if (!swl) {
5890
5891 ql_dbg(ql_dbg_disc, vha, 0x209c,
5892 "GID_PT allocations failed, fallback on GA_NXT.\n");
5893 } else {
5894 memset(swl, 0, ha->max_fibre_devices * sizeof(sw_info_t));
5895 if (qla2x00_gid_pt(vha, swl) != QLA_SUCCESS) {
5896 swl = NULL;
5897 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5898 return rval;
5899 } else if (qla2x00_gpn_id(vha, swl) != QLA_SUCCESS) {
5900 swl = NULL;
5901 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5902 return rval;
5903 } else if (qla2x00_gnn_id(vha, swl) != QLA_SUCCESS) {
5904 swl = NULL;
5905 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5906 return rval;
5907 } else if (qla2x00_gfpn_id(vha, swl) != QLA_SUCCESS) {
5908 swl = NULL;
5909 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5910 return rval;
5911 }
5912
5913
5914 if (swl) {
5915 qla2x00_gff_id(vha, swl);
5916 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
5917 return rval;
5918 }
5919 }
5920 swl_idx = 0;
5921
5922
5923 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
5924 if (new_fcport == NULL) {
5925 ql_log(ql_log_warn, vha, 0x209d,
5926 "Failed to allocate memory for fcport.\n");
5927 return (QLA_MEMORY_ALLOC_FAILED);
5928 }
5929 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
5930
5931 first_dev = 1;
5932 last_dev = 0;
5933
5934
5935 loop_id = ha->min_external_loopid;
5936 for (; loop_id <= ha->max_loop_id; loop_id++) {
5937 if (qla2x00_is_reserved_id(vha, loop_id))
5938 continue;
5939
5940 if (ha->current_topology == ISP_CFG_FL &&
5941 (atomic_read(&vha->loop_down_timer) ||
5942 LOOP_TRANSITION(vha))) {
5943 atomic_set(&vha->loop_down_timer, 0);
5944 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
5945 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
5946 break;
5947 }
5948
5949 if (swl != NULL) {
5950 if (last_dev) {
5951 wrap.b24 = new_fcport->d_id.b24;
5952 } else {
5953 new_fcport->d_id.b24 = swl[swl_idx].d_id.b24;
5954 memcpy(new_fcport->node_name,
5955 swl[swl_idx].node_name, WWN_SIZE);
5956 memcpy(new_fcport->port_name,
5957 swl[swl_idx].port_name, WWN_SIZE);
5958 memcpy(new_fcport->fabric_port_name,
5959 swl[swl_idx].fabric_port_name, WWN_SIZE);
5960 new_fcport->fp_speed = swl[swl_idx].fp_speed;
5961 new_fcport->fc4_type = swl[swl_idx].fc4_type;
5962
5963 new_fcport->nvme_flag = 0;
5964 if (vha->flags.nvme_enabled &&
5965 swl[swl_idx].fc4_type & FS_FC4TYPE_NVME) {
5966 ql_log(ql_log_info, vha, 0x2131,
5967 "FOUND: NVME port %8phC as FC Type 28h\n",
5968 new_fcport->port_name);
5969 }
5970
5971 if (swl[swl_idx].d_id.b.rsvd_1 != 0) {
5972 last_dev = 1;
5973 }
5974 swl_idx++;
5975 }
5976 } else {
5977
5978 rval = qla2x00_ga_nxt(vha, new_fcport);
5979 if (rval != QLA_SUCCESS) {
5980 ql_log(ql_log_warn, vha, 0x209e,
5981 "SNS scan failed -- assuming "
5982 "zero-entry result.\n");
5983 rval = QLA_SUCCESS;
5984 break;
5985 }
5986 }
5987
5988
5989 if (first_dev) {
5990 wrap.b24 = new_fcport->d_id.b24;
5991 first_dev = 0;
5992 } else if (new_fcport->d_id.b24 == wrap.b24) {
5993 ql_dbg(ql_dbg_disc, vha, 0x209f,
5994 "Device wrap (%02x%02x%02x).\n",
5995 new_fcport->d_id.b.domain,
5996 new_fcport->d_id.b.area,
5997 new_fcport->d_id.b.al_pa);
5998 break;
5999 }
6000
6001
6002 if (new_fcport->d_id.b24 == base_vha->d_id.b24)
6003 continue;
6004
6005
6006 if (qla2x00_is_a_vp_did(vha, new_fcport->d_id.b24))
6007 continue;
6008
6009
6010 if (((new_fcport->d_id.b24 & 0xffff00) ==
6011 (vha->d_id.b24 & 0xffff00)) && ha->current_topology ==
6012 ISP_CFG_FL)
6013 continue;
6014
6015
6016 if ((new_fcport->d_id.b.domain & 0xf0) == 0xf0)
6017 continue;
6018
6019
6020 if (ql2xgffidenable &&
6021 (!(new_fcport->fc4_type & FS_FC4TYPE_FCP) &&
6022 new_fcport->fc4_type != 0))
6023 continue;
6024
6025 spin_lock_irqsave(&vha->hw->tgt.sess_lock, flags);
6026
6027
6028 found = 0;
6029 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6030 if (memcmp(new_fcport->port_name, fcport->port_name,
6031 WWN_SIZE))
6032 continue;
6033
6034 fcport->scan_state = QLA_FCPORT_FOUND;
6035
6036 found++;
6037
6038
6039 memcpy(fcport->fabric_port_name,
6040 new_fcport->fabric_port_name, WWN_SIZE);
6041 fcport->fp_speed = new_fcport->fp_speed;
6042
6043
6044
6045
6046
6047 if (fcport->d_id.b24 == new_fcport->d_id.b24 &&
6048 (atomic_read(&fcport->state) == FCS_ONLINE ||
6049 (vha->host->active_mode == MODE_TARGET))) {
6050 break;
6051 }
6052
6053 if (fcport->login_retry == 0)
6054 fcport->login_retry =
6055 vha->hw->login_retry_count;
6056
6057
6058
6059 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0) {
6060 fcport->d_id.b24 = new_fcport->d_id.b24;
6061 qla2x00_clear_loop_id(fcport);
6062 fcport->flags |= (FCF_FABRIC_DEVICE |
6063 FCF_LOGIN_NEEDED);
6064 break;
6065 }
6066
6067
6068
6069
6070
6071
6072 if (qla_tgt_mode_enabled(base_vha)) {
6073 ql_dbg(ql_dbg_tgt_mgt, vha, 0xf080,
6074 "port changed FC ID, %8phC"
6075 " old %x:%x:%x (loop_id 0x%04x)-> new %x:%x:%x\n",
6076 fcport->port_name,
6077 fcport->d_id.b.domain,
6078 fcport->d_id.b.area,
6079 fcport->d_id.b.al_pa,
6080 fcport->loop_id,
6081 new_fcport->d_id.b.domain,
6082 new_fcport->d_id.b.area,
6083 new_fcport->d_id.b.al_pa);
6084 fcport->d_id.b24 = new_fcport->d_id.b24;
6085 break;
6086 }
6087
6088 fcport->d_id.b24 = new_fcport->d_id.b24;
6089 fcport->flags |= FCF_LOGIN_NEEDED;
6090 break;
6091 }
6092
6093 if (found && NVME_TARGET(vha->hw, fcport)) {
6094 if (fcport->disc_state == DSC_DELETE_PEND) {
6095 qla2x00_set_fcport_disc_state(fcport, DSC_GNL);
6096 vha->fcport_count--;
6097 fcport->login_succ = 0;
6098 }
6099 }
6100
6101 if (found) {
6102 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6103 continue;
6104 }
6105
6106 new_fcport->scan_state = QLA_FCPORT_FOUND;
6107 list_add_tail(&new_fcport->list, &vha->vp_fcports);
6108
6109 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, flags);
6110
6111
6112
6113 nxt_d_id.b24 = new_fcport->d_id.b24;
6114 new_fcport = qla2x00_alloc_fcport(vha, GFP_KERNEL);
6115 if (new_fcport == NULL) {
6116 ql_log(ql_log_warn, vha, 0xd032,
6117 "Memory allocation failed for fcport.\n");
6118 return (QLA_MEMORY_ALLOC_FAILED);
6119 }
6120 new_fcport->flags |= (FCF_FABRIC_DEVICE | FCF_LOGIN_NEEDED);
6121 new_fcport->d_id.b24 = nxt_d_id.b24;
6122 }
6123
6124 qla2x00_free_fcport(new_fcport);
6125
6126
6127
6128
6129 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6130 if (test_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags))
6131 break;
6132
6133 if ((fcport->flags & FCF_FABRIC_DEVICE) == 0)
6134 continue;
6135
6136 if (fcport->scan_state == QLA_FCPORT_SCAN) {
6137 if ((qla_dual_mode_enabled(vha) ||
6138 qla_ini_mode_enabled(vha)) &&
6139 atomic_read(&fcport->state) == FCS_ONLINE) {
6140 qla2x00_mark_device_lost(vha, fcport,
6141 ql2xplogiabsentdevice);
6142 if (fcport->loop_id != FC_NO_LOOP_ID &&
6143 (fcport->flags & FCF_FCP2_DEVICE) == 0 &&
6144 fcport->port_type != FCT_INITIATOR &&
6145 fcport->port_type != FCT_BROADCAST) {
6146 ql_dbg(ql_dbg_disc, vha, 0x20f0,
6147 "%s %d %8phC post del sess\n",
6148 __func__, __LINE__,
6149 fcport->port_name);
6150 qlt_schedule_sess_for_deletion(fcport);
6151 continue;
6152 }
6153 }
6154 }
6155
6156 if (fcport->scan_state == QLA_FCPORT_FOUND &&
6157 (fcport->flags & FCF_LOGIN_NEEDED) != 0)
6158 qla24xx_fcport_handle_login(vha, fcport);
6159 }
6160 return (rval);
6161}
6162
6163
6164int
6165qla2x00_reserve_mgmt_server_loop_id(scsi_qla_host_t *vha)
6166{
6167 int loop_id = FC_NO_LOOP_ID;
6168 int lid = NPH_MGMT_SERVER - vha->vp_idx;
6169 unsigned long flags;
6170 struct qla_hw_data *ha = vha->hw;
6171
6172 if (vha->vp_idx == 0) {
6173 set_bit(NPH_MGMT_SERVER, ha->loop_id_map);
6174 return NPH_MGMT_SERVER;
6175 }
6176
6177
6178 spin_lock_irqsave(&ha->vport_slock, flags);
6179 for (; lid > 0; lid--) {
6180 if (!test_bit(lid, vha->hw->loop_id_map)) {
6181 set_bit(lid, vha->hw->loop_id_map);
6182 loop_id = lid;
6183 break;
6184 }
6185 }
6186 spin_unlock_irqrestore(&ha->vport_slock, flags);
6187
6188 return loop_id;
6189}
6190
6191
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203
6204
6205int
6206qla2x00_fabric_login(scsi_qla_host_t *vha, fc_port_t *fcport,
6207 uint16_t *next_loopid)
6208{
6209 int rval;
6210 int retry;
6211 uint16_t tmp_loopid;
6212 uint16_t mb[MAILBOX_REGISTER_COUNT];
6213 struct qla_hw_data *ha = vha->hw;
6214
6215 retry = 0;
6216 tmp_loopid = 0;
6217
6218 for (;;) {
6219 ql_dbg(ql_dbg_disc, vha, 0x2000,
6220 "Trying Fabric Login w/loop id 0x%04x for port "
6221 "%02x%02x%02x.\n",
6222 fcport->loop_id, fcport->d_id.b.domain,
6223 fcport->d_id.b.area, fcport->d_id.b.al_pa);
6224
6225
6226 rval = ha->isp_ops->fabric_login(vha, fcport->loop_id,
6227 fcport->d_id.b.domain, fcport->d_id.b.area,
6228 fcport->d_id.b.al_pa, mb, BIT_0);
6229 if (rval != QLA_SUCCESS) {
6230 return rval;
6231 }
6232 if (mb[0] == MBS_PORT_ID_USED) {
6233
6234
6235
6236
6237
6238
6239
6240 retry++;
6241 tmp_loopid = fcport->loop_id;
6242 fcport->loop_id = mb[1];
6243
6244 ql_dbg(ql_dbg_disc, vha, 0x2001,
6245 "Fabric Login: port in use - next loop "
6246 "id=0x%04x, port id= %02x%02x%02x.\n",
6247 fcport->loop_id, fcport->d_id.b.domain,
6248 fcport->d_id.b.area, fcport->d_id.b.al_pa);
6249
6250 } else if (mb[0] == MBS_COMMAND_COMPLETE) {
6251
6252
6253
6254 if (retry) {
6255
6256 *next_loopid = tmp_loopid;
6257 } else {
6258
6259
6260
6261
6262 *next_loopid = (fcport->loop_id + 1);
6263 }
6264
6265 if (mb[1] & BIT_0) {
6266 fcport->port_type = FCT_INITIATOR;
6267 } else {
6268 fcport->port_type = FCT_TARGET;
6269 if (mb[1] & BIT_1) {
6270 fcport->flags |= FCF_FCP2_DEVICE;
6271 }
6272 }
6273
6274 if (mb[10] & BIT_0)
6275 fcport->supported_classes |= FC_COS_CLASS2;
6276 if (mb[10] & BIT_1)
6277 fcport->supported_classes |= FC_COS_CLASS3;
6278
6279 if (IS_FWI2_CAPABLE(ha)) {
6280 if (mb[10] & BIT_7)
6281 fcport->flags |=
6282 FCF_CONF_COMP_SUPPORTED;
6283 }
6284
6285 rval = QLA_SUCCESS;
6286 break;
6287 } else if (mb[0] == MBS_LOOP_ID_USED) {
6288
6289
6290
6291 fcport->loop_id++;
6292 rval = qla2x00_find_new_loop_id(vha, fcport);
6293 if (rval != QLA_SUCCESS) {
6294
6295 break;
6296 }
6297 } else if (mb[0] == MBS_COMMAND_ERROR) {
6298
6299
6300
6301
6302
6303 *next_loopid = fcport->loop_id;
6304 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
6305 fcport->d_id.b.domain, fcport->d_id.b.area,
6306 fcport->d_id.b.al_pa);
6307 qla2x00_mark_device_lost(vha, fcport, 1);
6308
6309 rval = 1;
6310 break;
6311 } else {
6312
6313
6314
6315 ql_dbg(ql_dbg_disc, vha, 0x2002,
6316 "Failed=%x port_id=%02x%02x%02x loop_id=%x "
6317 "jiffies=%lx.\n", mb[0], fcport->d_id.b.domain,
6318 fcport->d_id.b.area, fcport->d_id.b.al_pa,
6319 fcport->loop_id, jiffies);
6320
6321 *next_loopid = fcport->loop_id;
6322 ha->isp_ops->fabric_logout(vha, fcport->loop_id,
6323 fcport->d_id.b.domain, fcport->d_id.b.area,
6324 fcport->d_id.b.al_pa);
6325 qla2x00_clear_loop_id(fcport);
6326 fcport->login_retry = 0;
6327
6328 rval = 3;
6329 break;
6330 }
6331 }
6332
6333 return (rval);
6334}
6335
6336
6337
6338
6339
6340
6341
6342
6343
6344
6345
6346
6347
6348
6349int
6350qla2x00_local_device_login(scsi_qla_host_t *vha, fc_port_t *fcport)
6351{
6352 int rval;
6353 uint16_t mb[MAILBOX_REGISTER_COUNT];
6354
6355 memset(mb, 0, sizeof(mb));
6356 rval = qla2x00_login_local_device(vha, fcport, mb, BIT_0);
6357 if (rval == QLA_SUCCESS) {
6358
6359 if (mb[0] == MBS_COMMAND_ERROR)
6360 rval = 1;
6361 else if (mb[0] == MBS_COMMAND_PARAMETER_ERROR)
6362
6363 rval = 3;
6364 }
6365
6366 return (rval);
6367}
6368
6369
6370
6371
6372
6373
6374
6375
6376
6377
6378
6379int
6380qla2x00_loop_resync(scsi_qla_host_t *vha)
6381{
6382 int rval = QLA_SUCCESS;
6383 uint32_t wait_time;
6384
6385 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6386 if (vha->flags.online) {
6387 if (!(rval = qla2x00_fw_ready(vha))) {
6388
6389 wait_time = 256;
6390 do {
6391 if (!IS_QLAFX00(vha->hw)) {
6392
6393
6394
6395
6396 qla2x00_marker(vha, vha->hw->base_qpair,
6397 0, 0, MK_SYNC_ALL);
6398 vha->marker_needed = 0;
6399 }
6400
6401
6402 clear_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
6403
6404 if (IS_QLAFX00(vha->hw))
6405 qlafx00_configure_devices(vha);
6406 else
6407 qla2x00_configure_loop(vha);
6408
6409 wait_time--;
6410 } while (!atomic_read(&vha->loop_down_timer) &&
6411 !(test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6412 && wait_time && (test_bit(LOOP_RESYNC_NEEDED,
6413 &vha->dpc_flags)));
6414 }
6415 }
6416
6417 if (test_bit(ISP_ABORT_NEEDED, &vha->dpc_flags))
6418 return (QLA_FUNCTION_FAILED);
6419
6420 if (rval)
6421 ql_dbg(ql_dbg_disc, vha, 0x206c,
6422 "%s *** FAILED ***.\n", __func__);
6423
6424 return (rval);
6425}
6426
6427
6428
6429
6430
6431
6432
6433
6434
6435int qla2x00_perform_loop_resync(scsi_qla_host_t *ha)
6436{
6437 int32_t rval = 0;
6438
6439 if (!test_and_set_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) {
6440
6441 atomic_set(&ha->loop_down_timer, 0);
6442 if (!(ha->device_flags & DFLG_NO_CABLE)) {
6443 atomic_set(&ha->loop_state, LOOP_UP);
6444 set_bit(LOCAL_LOOP_UPDATE, &ha->dpc_flags);
6445 set_bit(REGISTER_FC4_NEEDED, &ha->dpc_flags);
6446 set_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags);
6447
6448 rval = qla2x00_loop_resync(ha);
6449 } else
6450 atomic_set(&ha->loop_state, LOOP_DEAD);
6451
6452 clear_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags);
6453 }
6454
6455 return rval;
6456}
6457
6458void
6459qla2x00_update_fcports(scsi_qla_host_t *base_vha)
6460{
6461 fc_port_t *fcport;
6462 struct scsi_qla_host *vha;
6463 struct qla_hw_data *ha = base_vha->hw;
6464 unsigned long flags;
6465
6466 spin_lock_irqsave(&ha->vport_slock, flags);
6467
6468 list_for_each_entry(vha, &base_vha->hw->vp_list, list) {
6469 atomic_inc(&vha->vref_count);
6470 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6471 if (fcport->drport &&
6472 atomic_read(&fcport->state) != FCS_UNCONFIGURED) {
6473 spin_unlock_irqrestore(&ha->vport_slock, flags);
6474 qla2x00_rport_del(fcport);
6475
6476 spin_lock_irqsave(&ha->vport_slock, flags);
6477 }
6478 }
6479 atomic_dec(&vha->vref_count);
6480 wake_up(&vha->vref_waitq);
6481 }
6482 spin_unlock_irqrestore(&ha->vport_slock, flags);
6483}
6484
6485
6486void
6487qla83xx_reset_ownership(scsi_qla_host_t *vha)
6488{
6489 struct qla_hw_data *ha = vha->hw;
6490 uint32_t drv_presence, drv_presence_mask;
6491 uint32_t dev_part_info1, dev_part_info2, class_type;
6492 uint32_t class_type_mask = 0x3;
6493 uint16_t fcoe_other_function = 0xffff, i;
6494
6495 if (IS_QLA8044(ha)) {
6496 drv_presence = qla8044_rd_direct(vha,
6497 QLA8044_CRB_DRV_ACTIVE_INDEX);
6498 dev_part_info1 = qla8044_rd_direct(vha,
6499 QLA8044_CRB_DEV_PART_INFO_INDEX);
6500 dev_part_info2 = qla8044_rd_direct(vha,
6501 QLA8044_CRB_DEV_PART_INFO2);
6502 } else {
6503 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6504 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO1, &dev_part_info1);
6505 qla83xx_rd_reg(vha, QLA83XX_DEV_PARTINFO2, &dev_part_info2);
6506 }
6507 for (i = 0; i < 8; i++) {
6508 class_type = ((dev_part_info1 >> (i * 4)) & class_type_mask);
6509 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6510 (i != ha->portnum)) {
6511 fcoe_other_function = i;
6512 break;
6513 }
6514 }
6515 if (fcoe_other_function == 0xffff) {
6516 for (i = 0; i < 8; i++) {
6517 class_type = ((dev_part_info2 >> (i * 4)) &
6518 class_type_mask);
6519 if ((class_type == QLA83XX_CLASS_TYPE_FCOE) &&
6520 ((i + 8) != ha->portnum)) {
6521 fcoe_other_function = i + 8;
6522 break;
6523 }
6524 }
6525 }
6526
6527
6528
6529
6530 drv_presence_mask = ~((1 << (ha->portnum)) |
6531 ((fcoe_other_function == 0xffff) ?
6532 0 : (1 << (fcoe_other_function))));
6533
6534
6535
6536
6537 if (!(drv_presence & drv_presence_mask) &&
6538 (ha->portnum < fcoe_other_function)) {
6539 ql_dbg(ql_dbg_p3p, vha, 0xb07f,
6540 "This host is Reset owner.\n");
6541 ha->flags.nic_core_reset_owner = 1;
6542 }
6543}
6544
6545static int
6546__qla83xx_set_drv_ack(scsi_qla_host_t *vha)
6547{
6548 int rval = QLA_SUCCESS;
6549 struct qla_hw_data *ha = vha->hw;
6550 uint32_t drv_ack;
6551
6552 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6553 if (rval == QLA_SUCCESS) {
6554 drv_ack |= (1 << ha->portnum);
6555 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6556 }
6557
6558 return rval;
6559}
6560
6561static int
6562__qla83xx_clear_drv_ack(scsi_qla_host_t *vha)
6563{
6564 int rval = QLA_SUCCESS;
6565 struct qla_hw_data *ha = vha->hw;
6566 uint32_t drv_ack;
6567
6568 rval = qla83xx_rd_reg(vha, QLA83XX_IDC_DRIVER_ACK, &drv_ack);
6569 if (rval == QLA_SUCCESS) {
6570 drv_ack &= ~(1 << ha->portnum);
6571 rval = qla83xx_wr_reg(vha, QLA83XX_IDC_DRIVER_ACK, drv_ack);
6572 }
6573
6574 return rval;
6575}
6576
6577static const char *
6578qla83xx_dev_state_to_string(uint32_t dev_state)
6579{
6580 switch (dev_state) {
6581 case QLA8XXX_DEV_COLD:
6582 return "COLD/RE-INIT";
6583 case QLA8XXX_DEV_INITIALIZING:
6584 return "INITIALIZING";
6585 case QLA8XXX_DEV_READY:
6586 return "READY";
6587 case QLA8XXX_DEV_NEED_RESET:
6588 return "NEED RESET";
6589 case QLA8XXX_DEV_NEED_QUIESCENT:
6590 return "NEED QUIESCENT";
6591 case QLA8XXX_DEV_FAILED:
6592 return "FAILED";
6593 case QLA8XXX_DEV_QUIESCENT:
6594 return "QUIESCENT";
6595 default:
6596 return "Unknown";
6597 }
6598}
6599
6600
6601void
6602qla83xx_idc_audit(scsi_qla_host_t *vha, int audit_type)
6603{
6604 struct qla_hw_data *ha = vha->hw;
6605 uint32_t idc_audit_reg = 0, duration_secs = 0;
6606
6607 switch (audit_type) {
6608 case IDC_AUDIT_TIMESTAMP:
6609 ha->idc_audit_ts = (jiffies_to_msecs(jiffies) / 1000);
6610 idc_audit_reg = (ha->portnum) |
6611 (IDC_AUDIT_TIMESTAMP << 7) | (ha->idc_audit_ts << 8);
6612 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6613 break;
6614
6615 case IDC_AUDIT_COMPLETION:
6616 duration_secs = ((jiffies_to_msecs(jiffies) -
6617 jiffies_to_msecs(ha->idc_audit_ts)) / 1000);
6618 idc_audit_reg = (ha->portnum) |
6619 (IDC_AUDIT_COMPLETION << 7) | (duration_secs << 8);
6620 qla83xx_wr_reg(vha, QLA83XX_IDC_AUDIT, idc_audit_reg);
6621 break;
6622
6623 default:
6624 ql_log(ql_log_warn, vha, 0xb078,
6625 "Invalid audit type specified.\n");
6626 break;
6627 }
6628}
6629
6630
6631static int
6632qla83xx_initiating_reset(scsi_qla_host_t *vha)
6633{
6634 struct qla_hw_data *ha = vha->hw;
6635 uint32_t idc_control, dev_state;
6636
6637 __qla83xx_get_idc_control(vha, &idc_control);
6638 if ((idc_control & QLA83XX_IDC_RESET_DISABLED)) {
6639 ql_log(ql_log_info, vha, 0xb080,
6640 "NIC Core reset has been disabled. idc-control=0x%x\n",
6641 idc_control);
6642 return QLA_FUNCTION_FAILED;
6643 }
6644
6645
6646 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6647 if (ha->flags.nic_core_reset_owner && dev_state == QLA8XXX_DEV_READY) {
6648 qla83xx_wr_reg(vha, QLA83XX_IDC_DEV_STATE,
6649 QLA8XXX_DEV_NEED_RESET);
6650 ql_log(ql_log_info, vha, 0xb056, "HW State: NEED RESET.\n");
6651 qla83xx_idc_audit(vha, IDC_AUDIT_TIMESTAMP);
6652 } else {
6653 const char *state = qla83xx_dev_state_to_string(dev_state);
6654
6655 ql_log(ql_log_info, vha, 0xb057, "HW State: %s.\n", state);
6656
6657
6658
6659 while (dev_state == QLA8XXX_DEV_READY) {
6660 qla83xx_idc_unlock(vha, 0);
6661 msleep(200);
6662 qla83xx_idc_lock(vha, 0);
6663 qla83xx_rd_reg(vha, QLA83XX_IDC_DEV_STATE, &dev_state);
6664 }
6665 }
6666
6667
6668 __qla83xx_set_drv_ack(vha);
6669
6670 return QLA_SUCCESS;
6671}
6672
6673int
6674__qla83xx_set_idc_control(scsi_qla_host_t *vha, uint32_t idc_control)
6675{
6676 return qla83xx_wr_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6677}
6678
6679int
6680__qla83xx_get_idc_control(scsi_qla_host_t *vha, uint32_t *idc_control)
6681{
6682 return qla83xx_rd_reg(vha, QLA83XX_IDC_CONTROL, idc_control);
6683}
6684
6685static int
6686qla83xx_check_driver_presence(scsi_qla_host_t *vha)
6687{
6688 uint32_t drv_presence = 0;
6689 struct qla_hw_data *ha = vha->hw;
6690
6691 qla83xx_rd_reg(vha, QLA83XX_IDC_DRV_PRESENCE, &drv_presence);
6692 if (drv_presence & (1 << ha->portnum))
6693 return QLA_SUCCESS;
6694 else
6695 return QLA_TEST_FAILED;
6696}
6697
6698int
6699qla83xx_nic_core_reset(scsi_qla_host_t *vha)
6700{
6701 int rval = QLA_SUCCESS;
6702 struct qla_hw_data *ha = vha->hw;
6703
6704 ql_dbg(ql_dbg_p3p, vha, 0xb058,
6705 "Entered %s().\n", __func__);
6706
6707 if (vha->device_flags & DFLG_DEV_FAILED) {
6708 ql_log(ql_log_warn, vha, 0xb059,
6709 "Device in unrecoverable FAILED state.\n");
6710 return QLA_FUNCTION_FAILED;
6711 }
6712
6713 qla83xx_idc_lock(vha, 0);
6714
6715 if (qla83xx_check_driver_presence(vha) != QLA_SUCCESS) {
6716 ql_log(ql_log_warn, vha, 0xb05a,
6717 "Function=0x%x has been removed from IDC participation.\n",
6718 ha->portnum);
6719 rval = QLA_FUNCTION_FAILED;
6720 goto exit;
6721 }
6722
6723 qla83xx_reset_ownership(vha);
6724
6725 rval = qla83xx_initiating_reset(vha);
6726
6727
6728
6729
6730
6731 if (rval == QLA_SUCCESS) {
6732 rval = qla83xx_idc_state_handler(vha);
6733
6734 if (rval == QLA_SUCCESS)
6735 ha->flags.nic_core_hung = 0;
6736 __qla83xx_clear_drv_ack(vha);
6737 }
6738
6739exit:
6740 qla83xx_idc_unlock(vha, 0);
6741
6742 ql_dbg(ql_dbg_p3p, vha, 0xb05b, "Exiting %s.\n", __func__);
6743
6744 return rval;
6745}
6746
6747int
6748qla2xxx_mctp_dump(scsi_qla_host_t *vha)
6749{
6750 struct qla_hw_data *ha = vha->hw;
6751 int rval = QLA_FUNCTION_FAILED;
6752
6753 if (!IS_MCTP_CAPABLE(ha)) {
6754
6755 ql_log(ql_log_info, vha, 0x506d,
6756 "This board is not MCTP capable\n");
6757 return rval;
6758 }
6759
6760 if (!ha->mctp_dump) {
6761 ha->mctp_dump = dma_alloc_coherent(&ha->pdev->dev,
6762 MCTP_DUMP_SIZE, &ha->mctp_dump_dma, GFP_KERNEL);
6763
6764 if (!ha->mctp_dump) {
6765 ql_log(ql_log_warn, vha, 0x506e,
6766 "Failed to allocate memory for mctp dump\n");
6767 return rval;
6768 }
6769 }
6770
6771#define MCTP_DUMP_STR_ADDR 0x00000000
6772 rval = qla2x00_dump_mctp_data(vha, ha->mctp_dump_dma,
6773 MCTP_DUMP_STR_ADDR, MCTP_DUMP_SIZE/4);
6774 if (rval != QLA_SUCCESS) {
6775 ql_log(ql_log_warn, vha, 0x506f,
6776 "Failed to capture mctp dump\n");
6777 } else {
6778 ql_log(ql_log_info, vha, 0x5070,
6779 "Mctp dump capture for host (%ld/%p).\n",
6780 vha->host_no, ha->mctp_dump);
6781 ha->mctp_dumped = 1;
6782 }
6783
6784 if (!ha->flags.nic_core_reset_hdlr_active && !ha->portnum) {
6785 ha->flags.nic_core_reset_hdlr_active = 1;
6786 rval = qla83xx_restart_nic_firmware(vha);
6787 if (rval)
6788
6789 ql_log(ql_log_warn, vha, 0x5071,
6790 "Failed to restart nic firmware\n");
6791 else
6792 ql_dbg(ql_dbg_p3p, vha, 0xb084,
6793 "Restarted NIC firmware successfully.\n");
6794 ha->flags.nic_core_reset_hdlr_active = 0;
6795 }
6796
6797 return rval;
6798
6799}
6800
6801
6802
6803
6804
6805
6806
6807
6808
6809void
6810qla2x00_quiesce_io(scsi_qla_host_t *vha)
6811{
6812 struct qla_hw_data *ha = vha->hw;
6813 struct scsi_qla_host *vp;
6814
6815 ql_dbg(ql_dbg_dpc, vha, 0x401d,
6816 "Quiescing I/O - ha=%p.\n", ha);
6817
6818 atomic_set(&ha->loop_down_timer, LOOP_DOWN_TIME);
6819 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6820 atomic_set(&vha->loop_state, LOOP_DOWN);
6821 qla2x00_mark_all_devices_lost(vha);
6822 list_for_each_entry(vp, &ha->vp_list, list)
6823 qla2x00_mark_all_devices_lost(vp);
6824 } else {
6825 if (!atomic_read(&vha->loop_down_timer))
6826 atomic_set(&vha->loop_down_timer,
6827 LOOP_DOWN_TIME);
6828 }
6829
6830 WARN_ON_ONCE(qla2x00_eh_wait_for_pending_commands(vha, 0, 0, WAIT_HOST)
6831 != QLA_SUCCESS);
6832}
6833
6834void
6835qla2x00_abort_isp_cleanup(scsi_qla_host_t *vha)
6836{
6837 struct qla_hw_data *ha = vha->hw;
6838 struct scsi_qla_host *vp;
6839 unsigned long flags;
6840 fc_port_t *fcport;
6841 u16 i;
6842
6843
6844
6845
6846 if (!(IS_P3P_TYPE(ha)))
6847 vha->flags.online = 0;
6848 ha->flags.chip_reset_done = 0;
6849 clear_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
6850 vha->qla_stats.total_isp_aborts++;
6851
6852 ql_log(ql_log_info, vha, 0x00af,
6853 "Performing ISP error recovery - ha=%p.\n", ha);
6854
6855 ha->flags.purge_mbox = 1;
6856
6857
6858
6859
6860 if (!(IS_P3P_TYPE(ha)))
6861 ha->isp_ops->reset_chip(vha);
6862
6863 ha->link_data_rate = PORT_SPEED_UNKNOWN;
6864 SAVE_TOPO(ha);
6865 ha->flags.rida_fmt2 = 0;
6866 ha->flags.n2n_ae = 0;
6867 ha->flags.lip_ae = 0;
6868 ha->current_topology = 0;
6869 QLA_FW_STOPPED(ha);
6870 ha->flags.fw_init_done = 0;
6871 ha->chip_reset++;
6872 ha->base_qpair->chip_reset = ha->chip_reset;
6873 ha->base_qpair->cmd_cnt = ha->base_qpair->cmd_completion_cnt = 0;
6874 for (i = 0; i < ha->max_qpairs; i++) {
6875 if (ha->queue_pair_map[i]) {
6876 ha->queue_pair_map[i]->chip_reset =
6877 ha->base_qpair->chip_reset;
6878 ha->queue_pair_map[i]->cmd_cnt =
6879 ha->queue_pair_map[i]->cmd_completion_cnt = 0;
6880 }
6881 }
6882
6883
6884 if (atomic_read(&ha->num_pend_mbx_stage3)) {
6885 clear_bit(MBX_INTR_WAIT, &ha->mbx_cmd_flags);
6886 complete(&ha->mbx_intr_comp);
6887 }
6888
6889 i = 0;
6890 while (atomic_read(&ha->num_pend_mbx_stage3) ||
6891 atomic_read(&ha->num_pend_mbx_stage2) ||
6892 atomic_read(&ha->num_pend_mbx_stage1)) {
6893 msleep(20);
6894 i++;
6895 if (i > 50)
6896 break;
6897 }
6898 ha->flags.purge_mbox = 0;
6899
6900 atomic_set(&vha->loop_down_timer, LOOP_DOWN_TIME);
6901 if (atomic_read(&vha->loop_state) != LOOP_DOWN) {
6902 atomic_set(&vha->loop_state, LOOP_DOWN);
6903 qla2x00_mark_all_devices_lost(vha);
6904
6905 spin_lock_irqsave(&ha->vport_slock, flags);
6906 list_for_each_entry(vp, &ha->vp_list, list) {
6907 atomic_inc(&vp->vref_count);
6908 spin_unlock_irqrestore(&ha->vport_slock, flags);
6909
6910 qla2x00_mark_all_devices_lost(vp);
6911
6912 spin_lock_irqsave(&ha->vport_slock, flags);
6913 atomic_dec(&vp->vref_count);
6914 }
6915 spin_unlock_irqrestore(&ha->vport_slock, flags);
6916 } else {
6917 if (!atomic_read(&vha->loop_down_timer))
6918 atomic_set(&vha->loop_down_timer,
6919 LOOP_DOWN_TIME);
6920 }
6921
6922
6923 list_for_each_entry(fcport, &vha->vp_fcports, list) {
6924 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6925 fcport->scan_state = 0;
6926 }
6927 spin_lock_irqsave(&ha->vport_slock, flags);
6928 list_for_each_entry(vp, &ha->vp_list, list) {
6929 atomic_inc(&vp->vref_count);
6930 spin_unlock_irqrestore(&ha->vport_slock, flags);
6931
6932 list_for_each_entry(fcport, &vp->vp_fcports, list)
6933 fcport->flags &= ~(FCF_LOGIN_NEEDED | FCF_ASYNC_SENT);
6934
6935 spin_lock_irqsave(&ha->vport_slock, flags);
6936 atomic_dec(&vp->vref_count);
6937 }
6938 spin_unlock_irqrestore(&ha->vport_slock, flags);
6939
6940
6941 if (IS_P3P_TYPE(ha)) {
6942 qla82xx_chip_reset_cleanup(vha);
6943 ql_log(ql_log_info, vha, 0x00b4,
6944 "Done chip reset cleanup.\n");
6945
6946
6947 vha->flags.online = 0;
6948 }
6949
6950
6951 qla2x00_abort_all_cmds(vha, DID_RESET << 16);
6952
6953 wmb();
6954}
6955
6956
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966int
6967qla2x00_abort_isp(scsi_qla_host_t *vha)
6968{
6969 int rval;
6970 uint8_t status = 0;
6971 struct qla_hw_data *ha = vha->hw;
6972 struct scsi_qla_host *vp;
6973 struct req_que *req = ha->req_q_map[0];
6974 unsigned long flags;
6975
6976 if (vha->flags.online) {
6977 qla2x00_abort_isp_cleanup(vha);
6978
6979 if (vha->hw->flags.port_isolated)
6980 return status;
6981
6982 if (qla2x00_isp_reg_stat(ha)) {
6983 ql_log(ql_log_info, vha, 0x803f,
6984 "ISP Abort - ISP reg disconnect, exiting.\n");
6985 return status;
6986 }
6987
6988 if (test_and_clear_bit(ISP_ABORT_TO_ROM, &vha->dpc_flags)) {
6989 ha->flags.chip_reset_done = 1;
6990 vha->flags.online = 1;
6991 status = 0;
6992 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
6993 return status;
6994 }
6995
6996 if (IS_QLA8031(ha)) {
6997 ql_dbg(ql_dbg_p3p, vha, 0xb05c,
6998 "Clearing fcoe driver presence.\n");
6999 if (qla83xx_clear_drv_presence(vha) != QLA_SUCCESS)
7000 ql_dbg(ql_dbg_p3p, vha, 0xb073,
7001 "Error while clearing DRV-Presence.\n");
7002 }
7003
7004 if (unlikely(pci_channel_offline(ha->pdev) &&
7005 ha->flags.pci_channel_io_perm_failure)) {
7006 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7007 status = 0;
7008 return status;
7009 }
7010
7011 switch (vha->qlini_mode) {
7012 case QLA2XXX_INI_MODE_DISABLED:
7013 if (!qla_tgt_mode_enabled(vha))
7014 return 0;
7015 break;
7016 case QLA2XXX_INI_MODE_DUAL:
7017 if (!qla_dual_mode_enabled(vha))
7018 return 0;
7019 break;
7020 case QLA2XXX_INI_MODE_ENABLED:
7021 default:
7022 break;
7023 }
7024
7025 ha->isp_ops->get_flash_version(vha, req->ring);
7026
7027 if (qla2x00_isp_reg_stat(ha)) {
7028 ql_log(ql_log_info, vha, 0x803f,
7029 "ISP Abort - ISP reg disconnect pre nvram config, exiting.\n");
7030 return status;
7031 }
7032 ha->isp_ops->nvram_config(vha);
7033
7034 if (qla2x00_isp_reg_stat(ha)) {
7035 ql_log(ql_log_info, vha, 0x803f,
7036 "ISP Abort - ISP reg disconnect post nvmram config, exiting.\n");
7037 return status;
7038 }
7039 if (!qla2x00_restart_isp(vha)) {
7040 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7041
7042 if (!atomic_read(&vha->loop_down_timer)) {
7043
7044
7045
7046
7047 vha->marker_needed = 1;
7048 }
7049
7050 vha->flags.online = 1;
7051
7052 ha->isp_ops->enable_intrs(ha);
7053
7054 ha->isp_abort_cnt = 0;
7055 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7056
7057 if (IS_QLA81XX(ha) || IS_QLA8031(ha))
7058 qla2x00_get_fw_version(vha);
7059 if (ha->fce) {
7060 ha->flags.fce_enabled = 1;
7061 memset(ha->fce, 0,
7062 fce_calc_size(ha->fce_bufs));
7063 rval = qla2x00_enable_fce_trace(vha,
7064 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
7065 &ha->fce_bufs);
7066 if (rval) {
7067 ql_log(ql_log_warn, vha, 0x8033,
7068 "Unable to reinitialize FCE "
7069 "(%d).\n", rval);
7070 ha->flags.fce_enabled = 0;
7071 }
7072 }
7073
7074 if (ha->eft) {
7075 memset(ha->eft, 0, EFT_SIZE);
7076 rval = qla2x00_enable_eft_trace(vha,
7077 ha->eft_dma, EFT_NUM_BUFFERS);
7078 if (rval) {
7079 ql_log(ql_log_warn, vha, 0x8034,
7080 "Unable to reinitialize EFT "
7081 "(%d).\n", rval);
7082 }
7083 }
7084 } else {
7085 vha->flags.online = 1;
7086 if (test_bit(ISP_ABORT_RETRY, &vha->dpc_flags)) {
7087 if (ha->isp_abort_cnt == 0) {
7088 ql_log(ql_log_fatal, vha, 0x8035,
7089 "ISP error recover failed - "
7090 "board disabled.\n");
7091
7092
7093
7094
7095 qla2x00_abort_isp_cleanup(vha);
7096 vha->flags.online = 0;
7097 clear_bit(ISP_ABORT_RETRY,
7098 &vha->dpc_flags);
7099 status = 0;
7100 } else {
7101 ha->isp_abort_cnt--;
7102 ql_dbg(ql_dbg_taskm, vha, 0x8020,
7103 "ISP abort - retry remaining %d.\n",
7104 ha->isp_abort_cnt);
7105 status = 1;
7106 }
7107 } else {
7108 ha->isp_abort_cnt = MAX_RETRIES_OF_ISP_ABORT;
7109 ql_dbg(ql_dbg_taskm, vha, 0x8021,
7110 "ISP error recovery - retrying (%d) "
7111 "more times.\n", ha->isp_abort_cnt);
7112 set_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
7113 status = 1;
7114 }
7115 }
7116
7117 }
7118
7119 if (vha->hw->flags.port_isolated) {
7120 qla2x00_abort_isp_cleanup(vha);
7121 return status;
7122 }
7123
7124 if (!status) {
7125 ql_dbg(ql_dbg_taskm, vha, 0x8022, "%s succeeded.\n", __func__);
7126 qla2x00_configure_hba(vha);
7127 spin_lock_irqsave(&ha->vport_slock, flags);
7128 list_for_each_entry(vp, &ha->vp_list, list) {
7129 if (vp->vp_idx) {
7130 atomic_inc(&vp->vref_count);
7131 spin_unlock_irqrestore(&ha->vport_slock, flags);
7132
7133 qla2x00_vp_abort_isp(vp);
7134
7135 spin_lock_irqsave(&ha->vport_slock, flags);
7136 atomic_dec(&vp->vref_count);
7137 }
7138 }
7139 spin_unlock_irqrestore(&ha->vport_slock, flags);
7140
7141 if (IS_QLA8031(ha)) {
7142 ql_dbg(ql_dbg_p3p, vha, 0xb05d,
7143 "Setting back fcoe driver presence.\n");
7144 if (qla83xx_set_drv_presence(vha) != QLA_SUCCESS)
7145 ql_dbg(ql_dbg_p3p, vha, 0xb074,
7146 "Error while setting DRV-Presence.\n");
7147 }
7148 } else {
7149 ql_log(ql_log_warn, vha, 0x8023, "%s **** FAILED ****.\n",
7150 __func__);
7151 }
7152
7153 return(status);
7154}
7155
7156
7157
7158
7159
7160
7161
7162
7163
7164
7165
7166static int
7167qla2x00_restart_isp(scsi_qla_host_t *vha)
7168{
7169 int status;
7170 struct qla_hw_data *ha = vha->hw;
7171
7172
7173 if (qla2x00_isp_firmware(vha)) {
7174 vha->flags.online = 0;
7175 status = ha->isp_ops->chip_diag(vha);
7176 if (status)
7177 return status;
7178 status = qla2x00_setup_chip(vha);
7179 if (status)
7180 return status;
7181 }
7182
7183 status = qla2x00_init_rings(vha);
7184 if (status)
7185 return status;
7186
7187 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
7188 ha->flags.chip_reset_done = 1;
7189
7190
7191 qla25xx_init_queues(ha);
7192
7193 status = qla2x00_fw_ready(vha);
7194 if (status) {
7195
7196 return vha->device_flags & DFLG_NO_CABLE ? 0 : status;
7197 }
7198
7199
7200 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
7201 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
7202
7203 return 0;
7204}
7205
7206static int
7207qla25xx_init_queues(struct qla_hw_data *ha)
7208{
7209 struct rsp_que *rsp = NULL;
7210 struct req_que *req = NULL;
7211 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
7212 int ret = -1;
7213 int i;
7214
7215 for (i = 1; i < ha->max_rsp_queues; i++) {
7216 rsp = ha->rsp_q_map[i];
7217 if (rsp && test_bit(i, ha->rsp_qid_map)) {
7218 rsp->options &= ~BIT_0;
7219 ret = qla25xx_init_rsp_que(base_vha, rsp);
7220 if (ret != QLA_SUCCESS)
7221 ql_dbg(ql_dbg_init, base_vha, 0x00ff,
7222 "%s Rsp que: %d init failed.\n",
7223 __func__, rsp->id);
7224 else
7225 ql_dbg(ql_dbg_init, base_vha, 0x0100,
7226 "%s Rsp que: %d inited.\n",
7227 __func__, rsp->id);
7228 }
7229 }
7230 for (i = 1; i < ha->max_req_queues; i++) {
7231 req = ha->req_q_map[i];
7232 if (req && test_bit(i, ha->req_qid_map)) {
7233
7234 req->options &= ~BIT_0;
7235 ret = qla25xx_init_req_que(base_vha, req);
7236 if (ret != QLA_SUCCESS)
7237 ql_dbg(ql_dbg_init, base_vha, 0x0101,
7238 "%s Req que: %d init failed.\n",
7239 __func__, req->id);
7240 else
7241 ql_dbg(ql_dbg_init, base_vha, 0x0102,
7242 "%s Req que: %d inited.\n",
7243 __func__, req->id);
7244 }
7245 }
7246 return ret;
7247}
7248
7249
7250
7251
7252
7253
7254
7255
7256int
7257qla2x00_reset_adapter(scsi_qla_host_t *vha)
7258{
7259 unsigned long flags = 0;
7260 struct qla_hw_data *ha = vha->hw;
7261 struct device_reg_2xxx __iomem *reg = &ha->iobase->isp;
7262
7263 vha->flags.online = 0;
7264 ha->isp_ops->disable_intrs(ha);
7265
7266 spin_lock_irqsave(&ha->hardware_lock, flags);
7267 wrt_reg_word(®->hccr, HCCR_RESET_RISC);
7268 rd_reg_word(®->hccr);
7269 wrt_reg_word(®->hccr, HCCR_RELEASE_RISC);
7270 rd_reg_word(®->hccr);
7271 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7272
7273 return QLA_SUCCESS;
7274}
7275
7276int
7277qla24xx_reset_adapter(scsi_qla_host_t *vha)
7278{
7279 unsigned long flags = 0;
7280 struct qla_hw_data *ha = vha->hw;
7281 struct device_reg_24xx __iomem *reg = &ha->iobase->isp24;
7282
7283 if (IS_P3P_TYPE(ha))
7284 return QLA_SUCCESS;
7285
7286 vha->flags.online = 0;
7287 ha->isp_ops->disable_intrs(ha);
7288
7289 spin_lock_irqsave(&ha->hardware_lock, flags);
7290 wrt_reg_dword(®->hccr, HCCRX_SET_RISC_RESET);
7291 rd_reg_dword(®->hccr);
7292 wrt_reg_dword(®->hccr, HCCRX_REL_RISC_PAUSE);
7293 rd_reg_dword(®->hccr);
7294 spin_unlock_irqrestore(&ha->hardware_lock, flags);
7295
7296 if (IS_NOPOLLING_TYPE(ha))
7297 ha->isp_ops->enable_intrs(ha);
7298
7299 return QLA_SUCCESS;
7300}
7301
7302
7303
7304
7305static void qla24xx_nvram_wwn_from_ofw(scsi_qla_host_t *vha,
7306 struct nvram_24xx *nv)
7307{
7308#ifdef CONFIG_SPARC
7309 struct qla_hw_data *ha = vha->hw;
7310 struct pci_dev *pdev = ha->pdev;
7311 struct device_node *dp = pci_device_to_OF_node(pdev);
7312 const u8 *val;
7313 int len;
7314
7315 val = of_get_property(dp, "port-wwn", &len);
7316 if (val && len >= WWN_SIZE)
7317 memcpy(nv->port_name, val, WWN_SIZE);
7318
7319 val = of_get_property(dp, "node-wwn", &len);
7320 if (val && len >= WWN_SIZE)
7321 memcpy(nv->node_name, val, WWN_SIZE);
7322#endif
7323}
7324
7325int
7326qla24xx_nvram_config(scsi_qla_host_t *vha)
7327{
7328 int rval;
7329 struct init_cb_24xx *icb;
7330 struct nvram_24xx *nv;
7331 __le32 *dptr;
7332 uint8_t *dptr1, *dptr2;
7333 uint32_t chksum;
7334 uint16_t cnt;
7335 struct qla_hw_data *ha = vha->hw;
7336
7337 rval = QLA_SUCCESS;
7338 icb = (struct init_cb_24xx *)ha->init_cb;
7339 nv = ha->nvram;
7340
7341
7342 if (ha->port_no == 0) {
7343 ha->nvram_base = FA_NVRAM_FUNC0_ADDR;
7344 ha->vpd_base = FA_NVRAM_VPD0_ADDR;
7345 } else {
7346 ha->nvram_base = FA_NVRAM_FUNC1_ADDR;
7347 ha->vpd_base = FA_NVRAM_VPD1_ADDR;
7348 }
7349
7350 ha->nvram_size = sizeof(*nv);
7351 ha->vpd_size = FA_NVRAM_VPD_SIZE;
7352
7353
7354 ha->vpd = ha->nvram + VPD_OFFSET;
7355 ha->isp_ops->read_nvram(vha, ha->vpd,
7356 ha->nvram_base - FA_NVRAM_FUNC0_ADDR, FA_NVRAM_VPD_SIZE * 4);
7357
7358
7359 dptr = (__force __le32 *)nv;
7360 ha->isp_ops->read_nvram(vha, dptr, ha->nvram_base, ha->nvram_size);
7361 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
7362 chksum += le32_to_cpu(*dptr);
7363
7364 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x006a,
7365 "Contents of NVRAM\n");
7366 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x010d,
7367 nv, ha->nvram_size);
7368
7369
7370 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
7371 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
7372
7373 ql_log(ql_log_warn, vha, 0x006b,
7374 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
7375 chksum, nv->id, nv->nvram_version);
7376 ql_dump_buffer(ql_dbg_init, vha, 0x006b, nv, sizeof(*nv));
7377 ql_log(ql_log_warn, vha, 0x006c,
7378 "Falling back to functioning (yet invalid -- WWPN) "
7379 "defaults.\n");
7380
7381
7382
7383
7384 memset(nv, 0, ha->nvram_size);
7385 nv->nvram_version = cpu_to_le16(ICB_VERSION);
7386 nv->version = cpu_to_le16(ICB_VERSION);
7387 nv->frame_payload_size = cpu_to_le16(2048);
7388 nv->execution_throttle = cpu_to_le16(0xFFFF);
7389 nv->exchange_count = cpu_to_le16(0);
7390 nv->hard_address = cpu_to_le16(124);
7391 nv->port_name[0] = 0x21;
7392 nv->port_name[1] = 0x00 + ha->port_no + 1;
7393 nv->port_name[2] = 0x00;
7394 nv->port_name[3] = 0xe0;
7395 nv->port_name[4] = 0x8b;
7396 nv->port_name[5] = 0x1c;
7397 nv->port_name[6] = 0x55;
7398 nv->port_name[7] = 0x86;
7399 nv->node_name[0] = 0x20;
7400 nv->node_name[1] = 0x00;
7401 nv->node_name[2] = 0x00;
7402 nv->node_name[3] = 0xe0;
7403 nv->node_name[4] = 0x8b;
7404 nv->node_name[5] = 0x1c;
7405 nv->node_name[6] = 0x55;
7406 nv->node_name[7] = 0x86;
7407 qla24xx_nvram_wwn_from_ofw(vha, nv);
7408 nv->login_retry_count = cpu_to_le16(8);
7409 nv->interrupt_delay_timer = cpu_to_le16(0);
7410 nv->login_timeout = cpu_to_le16(0);
7411 nv->firmware_options_1 =
7412 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
7413 nv->firmware_options_2 = cpu_to_le32(2 << 4);
7414 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
7415 nv->firmware_options_3 = cpu_to_le32(2 << 13);
7416 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
7417 nv->efi_parameters = cpu_to_le32(0);
7418 nv->reset_delay = 5;
7419 nv->max_luns_per_target = cpu_to_le16(128);
7420 nv->port_down_retry_count = cpu_to_le16(30);
7421 nv->link_down_timeout = cpu_to_le16(30);
7422
7423 rval = 1;
7424 }
7425
7426 if (qla_tgt_mode_enabled(vha)) {
7427
7428 nv->firmware_options_1 &= cpu_to_le32(~BIT_13);
7429
7430 nv->host_p &= cpu_to_le32(~BIT_10);
7431 }
7432
7433 qlt_24xx_config_nvram_stage1(vha, nv);
7434
7435
7436 memset(icb, 0, ha->init_cb_size);
7437
7438
7439 dptr1 = (uint8_t *)icb;
7440 dptr2 = (uint8_t *)&nv->version;
7441 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
7442 while (cnt--)
7443 *dptr1++ = *dptr2++;
7444
7445 icb->login_retry_count = nv->login_retry_count;
7446 icb->link_down_on_nos = nv->link_down_on_nos;
7447
7448
7449 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
7450 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
7451 cnt = (uint8_t *)&icb->reserved_3 -
7452 (uint8_t *)&icb->interrupt_delay_timer;
7453 while (cnt--)
7454 *dptr1++ = *dptr2++;
7455 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
7456
7457
7458
7459 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
7460 "QLA2462");
7461
7462 qlt_24xx_config_nvram_stage2(vha, icb);
7463
7464 if (nv->host_p & cpu_to_le32(BIT_15)) {
7465
7466 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
7467 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
7468 }
7469
7470
7471 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
7472
7473
7474
7475
7476 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
7477 icb->node_name[0] &= 0xF0;
7478 }
7479
7480
7481 ha->flags.disable_risc_code_load = 0;
7482 ha->flags.enable_lip_reset = 0;
7483 ha->flags.enable_lip_full_login =
7484 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
7485 ha->flags.enable_target_reset =
7486 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
7487 ha->flags.enable_led_scheme = 0;
7488 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
7489
7490 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
7491 (BIT_6 | BIT_5 | BIT_4)) >> 4;
7492
7493 memcpy(ha->fw_seriallink_options24, nv->seriallink_options,
7494 sizeof(ha->fw_seriallink_options24));
7495
7496
7497 ha->serial0 = icb->port_name[5];
7498 ha->serial1 = icb->port_name[6];
7499 ha->serial2 = icb->port_name[7];
7500 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
7501 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
7502
7503 icb->execution_throttle = cpu_to_le16(0xFFFF);
7504
7505 ha->retry_count = le16_to_cpu(nv->login_retry_count);
7506
7507
7508 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
7509 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
7510 if (le16_to_cpu(nv->login_timeout) < 4)
7511 nv->login_timeout = cpu_to_le16(4);
7512 ha->login_timeout = le16_to_cpu(nv->login_timeout);
7513
7514
7515 ha->r_a_tov = 100;
7516
7517 ha->loop_reset_delay = nv->reset_delay;
7518
7519
7520
7521
7522
7523
7524
7525
7526
7527
7528
7529 if (le16_to_cpu(nv->link_down_timeout) == 0) {
7530 ha->loop_down_abort_time =
7531 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
7532 } else {
7533 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
7534 ha->loop_down_abort_time =
7535 (LOOP_DOWN_TIME - ha->link_down_timeout);
7536 }
7537
7538
7539 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
7540 if (qlport_down_retry)
7541 ha->port_down_retry_count = qlport_down_retry;
7542
7543
7544 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
7545 if (ha->port_down_retry_count ==
7546 le16_to_cpu(nv->port_down_retry_count) &&
7547 ha->port_down_retry_count > 3)
7548 ha->login_retry_count = ha->port_down_retry_count;
7549 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
7550 ha->login_retry_count = ha->port_down_retry_count;
7551 if (ql2xloginretrycount)
7552 ha->login_retry_count = ql2xloginretrycount;
7553
7554
7555 icb->firmware_options_3 |= cpu_to_le32(BIT_8);
7556
7557
7558 if (!vha->flags.init_done) {
7559 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
7560 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
7561 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
7562 le16_to_cpu(icb->interrupt_delay_timer) : 2;
7563 }
7564 icb->firmware_options_2 &= cpu_to_le32(
7565 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
7566 if (ha->zio_mode != QLA_ZIO_DISABLED) {
7567 ha->zio_mode = QLA_ZIO_MODE_6;
7568
7569 ql_log(ql_log_info, vha, 0x006f,
7570 "ZIO mode %d enabled; timer delay (%d us).\n",
7571 ha->zio_mode, ha->zio_timer * 100);
7572
7573 icb->firmware_options_2 |= cpu_to_le32(
7574 (uint32_t)ha->zio_mode);
7575 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
7576 }
7577
7578 if (rval) {
7579 ql_log(ql_log_warn, vha, 0x0070,
7580 "NVRAM configuration failed.\n");
7581 }
7582 return (rval);
7583}
7584
7585static void
7586qla27xx_print_image(struct scsi_qla_host *vha, char *name,
7587 struct qla27xx_image_status *image_status)
7588{
7589 ql_dbg(ql_dbg_init, vha, 0x018b,
7590 "%s %s: mask=%#02x gen=%#04x ver=%u.%u map=%#01x sum=%#08x sig=%#08x\n",
7591 name, "status",
7592 image_status->image_status_mask,
7593 le16_to_cpu(image_status->generation),
7594 image_status->ver_major,
7595 image_status->ver_minor,
7596 image_status->bitmap,
7597 le32_to_cpu(image_status->checksum),
7598 le32_to_cpu(image_status->signature));
7599}
7600
7601static bool
7602qla28xx_check_aux_image_status_signature(
7603 struct qla27xx_image_status *image_status)
7604{
7605 ulong signature = le32_to_cpu(image_status->signature);
7606
7607 return signature != QLA28XX_AUX_IMG_STATUS_SIGN;
7608}
7609
7610static bool
7611qla27xx_check_image_status_signature(struct qla27xx_image_status *image_status)
7612{
7613 ulong signature = le32_to_cpu(image_status->signature);
7614
7615 return
7616 signature != QLA27XX_IMG_STATUS_SIGN &&
7617 signature != QLA28XX_IMG_STATUS_SIGN;
7618}
7619
7620static ulong
7621qla27xx_image_status_checksum(struct qla27xx_image_status *image_status)
7622{
7623 __le32 *p = (__force __le32 *)image_status;
7624 uint n = sizeof(*image_status) / sizeof(*p);
7625 uint32_t sum = 0;
7626
7627 for ( ; n--; p++)
7628 sum += le32_to_cpup(p);
7629
7630 return sum;
7631}
7632
7633static inline uint
7634qla28xx_component_bitmask(struct qla27xx_image_status *aux, uint bitmask)
7635{
7636 return aux->bitmap & bitmask ?
7637 QLA27XX_SECONDARY_IMAGE : QLA27XX_PRIMARY_IMAGE;
7638}
7639
7640static void
7641qla28xx_component_status(
7642 struct active_regions *active_regions, struct qla27xx_image_status *aux)
7643{
7644 active_regions->aux.board_config =
7645 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_BOARD_CONFIG);
7646
7647 active_regions->aux.vpd_nvram =
7648 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_VPD_NVRAM);
7649
7650 active_regions->aux.npiv_config_0_1 =
7651 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_0_1);
7652
7653 active_regions->aux.npiv_config_2_3 =
7654 qla28xx_component_bitmask(aux, QLA28XX_AUX_IMG_NPIV_CONFIG_2_3);
7655}
7656
7657static int
7658qla27xx_compare_image_generation(
7659 struct qla27xx_image_status *pri_image_status,
7660 struct qla27xx_image_status *sec_image_status)
7661{
7662
7663 int16_t delta =
7664 le16_to_cpu(pri_image_status->generation) -
7665 le16_to_cpu(sec_image_status->generation);
7666
7667 ql_dbg(ql_dbg_init, NULL, 0x0180, "generation delta = %d\n", delta);
7668
7669 return delta;
7670}
7671
7672void
7673qla28xx_get_aux_images(
7674 struct scsi_qla_host *vha, struct active_regions *active_regions)
7675{
7676 struct qla_hw_data *ha = vha->hw;
7677 struct qla27xx_image_status pri_aux_image_status, sec_aux_image_status;
7678 bool valid_pri_image = false, valid_sec_image = false;
7679 bool active_pri_image = false, active_sec_image = false;
7680
7681 if (!ha->flt_region_aux_img_status_pri) {
7682 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary aux image not addressed\n");
7683 goto check_sec_image;
7684 }
7685
7686 qla24xx_read_flash_data(vha, (uint32_t *)&pri_aux_image_status,
7687 ha->flt_region_aux_img_status_pri,
7688 sizeof(pri_aux_image_status) >> 2);
7689 qla27xx_print_image(vha, "Primary aux image", &pri_aux_image_status);
7690
7691 if (qla28xx_check_aux_image_status_signature(&pri_aux_image_status)) {
7692 ql_dbg(ql_dbg_init, vha, 0x018b,
7693 "Primary aux image signature (%#x) not valid\n",
7694 le32_to_cpu(pri_aux_image_status.signature));
7695 goto check_sec_image;
7696 }
7697
7698 if (qla27xx_image_status_checksum(&pri_aux_image_status)) {
7699 ql_dbg(ql_dbg_init, vha, 0x018c,
7700 "Primary aux image checksum failed\n");
7701 goto check_sec_image;
7702 }
7703
7704 valid_pri_image = true;
7705
7706 if (pri_aux_image_status.image_status_mask & 1) {
7707 ql_dbg(ql_dbg_init, vha, 0x018d,
7708 "Primary aux image is active\n");
7709 active_pri_image = true;
7710 }
7711
7712check_sec_image:
7713 if (!ha->flt_region_aux_img_status_sec) {
7714 ql_dbg(ql_dbg_init, vha, 0x018a,
7715 "Secondary aux image not addressed\n");
7716 goto check_valid_image;
7717 }
7718
7719 qla24xx_read_flash_data(vha, (uint32_t *)&sec_aux_image_status,
7720 ha->flt_region_aux_img_status_sec,
7721 sizeof(sec_aux_image_status) >> 2);
7722 qla27xx_print_image(vha, "Secondary aux image", &sec_aux_image_status);
7723
7724 if (qla28xx_check_aux_image_status_signature(&sec_aux_image_status)) {
7725 ql_dbg(ql_dbg_init, vha, 0x018b,
7726 "Secondary aux image signature (%#x) not valid\n",
7727 le32_to_cpu(sec_aux_image_status.signature));
7728 goto check_valid_image;
7729 }
7730
7731 if (qla27xx_image_status_checksum(&sec_aux_image_status)) {
7732 ql_dbg(ql_dbg_init, vha, 0x018c,
7733 "Secondary aux image checksum failed\n");
7734 goto check_valid_image;
7735 }
7736
7737 valid_sec_image = true;
7738
7739 if (sec_aux_image_status.image_status_mask & 1) {
7740 ql_dbg(ql_dbg_init, vha, 0x018d,
7741 "Secondary aux image is active\n");
7742 active_sec_image = true;
7743 }
7744
7745check_valid_image:
7746 if (valid_pri_image && active_pri_image &&
7747 valid_sec_image && active_sec_image) {
7748 if (qla27xx_compare_image_generation(&pri_aux_image_status,
7749 &sec_aux_image_status) >= 0) {
7750 qla28xx_component_status(active_regions,
7751 &pri_aux_image_status);
7752 } else {
7753 qla28xx_component_status(active_regions,
7754 &sec_aux_image_status);
7755 }
7756 } else if (valid_pri_image && active_pri_image) {
7757 qla28xx_component_status(active_regions, &pri_aux_image_status);
7758 } else if (valid_sec_image && active_sec_image) {
7759 qla28xx_component_status(active_regions, &sec_aux_image_status);
7760 }
7761
7762 ql_dbg(ql_dbg_init, vha, 0x018f,
7763 "aux images active: BCFG=%u VPD/NVR=%u NPIV0/1=%u NPIV2/3=%u\n",
7764 active_regions->aux.board_config,
7765 active_regions->aux.vpd_nvram,
7766 active_regions->aux.npiv_config_0_1,
7767 active_regions->aux.npiv_config_2_3);
7768}
7769
7770void
7771qla27xx_get_active_image(struct scsi_qla_host *vha,
7772 struct active_regions *active_regions)
7773{
7774 struct qla_hw_data *ha = vha->hw;
7775 struct qla27xx_image_status pri_image_status, sec_image_status;
7776 bool valid_pri_image = false, valid_sec_image = false;
7777 bool active_pri_image = false, active_sec_image = false;
7778
7779 if (!ha->flt_region_img_status_pri) {
7780 ql_dbg(ql_dbg_init, vha, 0x018a, "Primary image not addressed\n");
7781 goto check_sec_image;
7782 }
7783
7784 if (qla24xx_read_flash_data(vha, (uint32_t *)&pri_image_status,
7785 ha->flt_region_img_status_pri, sizeof(pri_image_status) >> 2) !=
7786 QLA_SUCCESS) {
7787 WARN_ON_ONCE(true);
7788 goto check_sec_image;
7789 }
7790 qla27xx_print_image(vha, "Primary image", &pri_image_status);
7791
7792 if (qla27xx_check_image_status_signature(&pri_image_status)) {
7793 ql_dbg(ql_dbg_init, vha, 0x018b,
7794 "Primary image signature (%#x) not valid\n",
7795 le32_to_cpu(pri_image_status.signature));
7796 goto check_sec_image;
7797 }
7798
7799 if (qla27xx_image_status_checksum(&pri_image_status)) {
7800 ql_dbg(ql_dbg_init, vha, 0x018c,
7801 "Primary image checksum failed\n");
7802 goto check_sec_image;
7803 }
7804
7805 valid_pri_image = true;
7806
7807 if (pri_image_status.image_status_mask & 1) {
7808 ql_dbg(ql_dbg_init, vha, 0x018d,
7809 "Primary image is active\n");
7810 active_pri_image = true;
7811 }
7812
7813check_sec_image:
7814 if (!ha->flt_region_img_status_sec) {
7815 ql_dbg(ql_dbg_init, vha, 0x018a, "Secondary image not addressed\n");
7816 goto check_valid_image;
7817 }
7818
7819 qla24xx_read_flash_data(vha, (uint32_t *)(&sec_image_status),
7820 ha->flt_region_img_status_sec, sizeof(sec_image_status) >> 2);
7821 qla27xx_print_image(vha, "Secondary image", &sec_image_status);
7822
7823 if (qla27xx_check_image_status_signature(&sec_image_status)) {
7824 ql_dbg(ql_dbg_init, vha, 0x018b,
7825 "Secondary image signature (%#x) not valid\n",
7826 le32_to_cpu(sec_image_status.signature));
7827 goto check_valid_image;
7828 }
7829
7830 if (qla27xx_image_status_checksum(&sec_image_status)) {
7831 ql_dbg(ql_dbg_init, vha, 0x018c,
7832 "Secondary image checksum failed\n");
7833 goto check_valid_image;
7834 }
7835
7836 valid_sec_image = true;
7837
7838 if (sec_image_status.image_status_mask & 1) {
7839 ql_dbg(ql_dbg_init, vha, 0x018d,
7840 "Secondary image is active\n");
7841 active_sec_image = true;
7842 }
7843
7844check_valid_image:
7845 if (valid_pri_image && active_pri_image)
7846 active_regions->global = QLA27XX_PRIMARY_IMAGE;
7847
7848 if (valid_sec_image && active_sec_image) {
7849 if (!active_regions->global ||
7850 qla27xx_compare_image_generation(
7851 &pri_image_status, &sec_image_status) < 0) {
7852 active_regions->global = QLA27XX_SECONDARY_IMAGE;
7853 }
7854 }
7855
7856 ql_dbg(ql_dbg_init, vha, 0x018f, "active image %s (%u)\n",
7857 active_regions->global == QLA27XX_DEFAULT_IMAGE ?
7858 "default (boot/fw)" :
7859 active_regions->global == QLA27XX_PRIMARY_IMAGE ?
7860 "primary" :
7861 active_regions->global == QLA27XX_SECONDARY_IMAGE ?
7862 "secondary" : "invalid",
7863 active_regions->global);
7864}
7865
7866bool qla24xx_risc_firmware_invalid(uint32_t *dword)
7867{
7868 return
7869 !(dword[4] | dword[5] | dword[6] | dword[7]) ||
7870 !(~dword[4] | ~dword[5] | ~dword[6] | ~dword[7]);
7871}
7872
7873static int
7874qla24xx_load_risc_flash(scsi_qla_host_t *vha, uint32_t *srisc_addr,
7875 uint32_t faddr)
7876{
7877 int rval;
7878 uint templates, segments, fragment;
7879 ulong i;
7880 uint j;
7881 ulong dlen;
7882 uint32_t *dcode;
7883 uint32_t risc_addr, risc_size, risc_attr = 0;
7884 struct qla_hw_data *ha = vha->hw;
7885 struct req_que *req = ha->req_q_map[0];
7886 struct fwdt *fwdt = ha->fwdt;
7887
7888 ql_dbg(ql_dbg_init, vha, 0x008b,
7889 "FW: Loading firmware from flash (%x).\n", faddr);
7890
7891 dcode = (uint32_t *)req->ring;
7892 qla24xx_read_flash_data(vha, dcode, faddr, 8);
7893 if (qla24xx_risc_firmware_invalid(dcode)) {
7894 ql_log(ql_log_fatal, vha, 0x008c,
7895 "Unable to verify the integrity of flash firmware "
7896 "image.\n");
7897 ql_log(ql_log_fatal, vha, 0x008d,
7898 "Firmware data: %08x %08x %08x %08x.\n",
7899 dcode[0], dcode[1], dcode[2], dcode[3]);
7900
7901 return QLA_FUNCTION_FAILED;
7902 }
7903
7904 dcode = (uint32_t *)req->ring;
7905 *srisc_addr = 0;
7906 segments = FA_RISC_CODE_SEGMENTS;
7907 for (j = 0; j < segments; j++) {
7908 ql_dbg(ql_dbg_init, vha, 0x008d,
7909 "-> Loading segment %u...\n", j);
7910 qla24xx_read_flash_data(vha, dcode, faddr, 10);
7911 risc_addr = be32_to_cpu((__force __be32)dcode[2]);
7912 risc_size = be32_to_cpu((__force __be32)dcode[3]);
7913 if (!*srisc_addr) {
7914 *srisc_addr = risc_addr;
7915 risc_attr = be32_to_cpu((__force __be32)dcode[9]);
7916 }
7917
7918 dlen = ha->fw_transfer_size >> 2;
7919 for (fragment = 0; risc_size; fragment++) {
7920 if (dlen > risc_size)
7921 dlen = risc_size;
7922
7923 ql_dbg(ql_dbg_init, vha, 0x008e,
7924 "-> Loading fragment %u: %#x <- %#x (%#lx dwords)...\n",
7925 fragment, risc_addr, faddr, dlen);
7926 qla24xx_read_flash_data(vha, dcode, faddr, dlen);
7927 for (i = 0; i < dlen; i++)
7928 dcode[i] = swab32(dcode[i]);
7929
7930 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
7931 if (rval) {
7932 ql_log(ql_log_fatal, vha, 0x008f,
7933 "-> Failed load firmware fragment %u.\n",
7934 fragment);
7935 return QLA_FUNCTION_FAILED;
7936 }
7937
7938 faddr += dlen;
7939 risc_addr += dlen;
7940 risc_size -= dlen;
7941 }
7942 }
7943
7944 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
7945 return QLA_SUCCESS;
7946
7947 templates = (risc_attr & BIT_9) ? 2 : 1;
7948 ql_dbg(ql_dbg_init, vha, 0x0160, "-> templates = %u\n", templates);
7949 for (j = 0; j < templates; j++, fwdt++) {
7950 vfree(fwdt->template);
7951 fwdt->template = NULL;
7952 fwdt->length = 0;
7953
7954 dcode = (uint32_t *)req->ring;
7955 qla24xx_read_flash_data(vha, dcode, faddr, 7);
7956 risc_size = be32_to_cpu((__force __be32)dcode[2]);
7957 ql_dbg(ql_dbg_init, vha, 0x0161,
7958 "-> fwdt%u template array at %#x (%#x dwords)\n",
7959 j, faddr, risc_size);
7960 if (!risc_size || !~risc_size) {
7961 ql_dbg(ql_dbg_init, vha, 0x0162,
7962 "-> fwdt%u failed to read array\n", j);
7963 goto failed;
7964 }
7965
7966
7967 faddr += 7;
7968 risc_size -= 8;
7969
7970 ql_dbg(ql_dbg_init, vha, 0x0163,
7971 "-> fwdt%u template allocate template %#x words...\n",
7972 j, risc_size);
7973 fwdt->template = vmalloc(risc_size * sizeof(*dcode));
7974 if (!fwdt->template) {
7975 ql_log(ql_log_warn, vha, 0x0164,
7976 "-> fwdt%u failed allocate template.\n", j);
7977 goto failed;
7978 }
7979
7980 dcode = fwdt->template;
7981 qla24xx_read_flash_data(vha, dcode, faddr, risc_size);
7982
7983 if (!qla27xx_fwdt_template_valid(dcode)) {
7984 ql_log(ql_log_warn, vha, 0x0165,
7985 "-> fwdt%u failed template validate\n", j);
7986 goto failed;
7987 }
7988
7989 dlen = qla27xx_fwdt_template_size(dcode);
7990 ql_dbg(ql_dbg_init, vha, 0x0166,
7991 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
7992 j, dlen, dlen / sizeof(*dcode));
7993 if (dlen > risc_size * sizeof(*dcode)) {
7994 ql_log(ql_log_warn, vha, 0x0167,
7995 "-> fwdt%u template exceeds array (%-lu bytes)\n",
7996 j, dlen - risc_size * sizeof(*dcode));
7997 goto failed;
7998 }
7999
8000 fwdt->length = dlen;
8001 ql_dbg(ql_dbg_init, vha, 0x0168,
8002 "-> fwdt%u loaded template ok\n", j);
8003
8004 faddr += risc_size + 1;
8005 }
8006
8007 return QLA_SUCCESS;
8008
8009failed:
8010 vfree(fwdt->template);
8011 fwdt->template = NULL;
8012 fwdt->length = 0;
8013
8014 return QLA_SUCCESS;
8015}
8016
8017#define QLA_FW_URL "http://ldriver.qlogic.com/firmware/"
8018
8019int
8020qla2x00_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8021{
8022 int rval;
8023 int i, fragment;
8024 uint16_t *wcode;
8025 __be16 *fwcode;
8026 uint32_t risc_addr, risc_size, fwclen, wlen, *seg;
8027 struct fw_blob *blob;
8028 struct qla_hw_data *ha = vha->hw;
8029 struct req_que *req = ha->req_q_map[0];
8030
8031
8032 blob = qla2x00_request_firmware(vha);
8033 if (!blob) {
8034 ql_log(ql_log_info, vha, 0x0083,
8035 "Firmware image unavailable.\n");
8036 ql_log(ql_log_info, vha, 0x0084,
8037 "Firmware images can be retrieved from: "QLA_FW_URL ".\n");
8038 return QLA_FUNCTION_FAILED;
8039 }
8040
8041 rval = QLA_SUCCESS;
8042
8043 wcode = (uint16_t *)req->ring;
8044 *srisc_addr = 0;
8045 fwcode = (__force __be16 *)blob->fw->data;
8046 fwclen = 0;
8047
8048
8049 if (blob->fw->size < 8 * sizeof(uint16_t)) {
8050 ql_log(ql_log_fatal, vha, 0x0085,
8051 "Unable to verify integrity of firmware image (%zd).\n",
8052 blob->fw->size);
8053 goto fail_fw_integrity;
8054 }
8055 for (i = 0; i < 4; i++)
8056 wcode[i] = be16_to_cpu(fwcode[i + 4]);
8057 if ((wcode[0] == 0xffff && wcode[1] == 0xffff && wcode[2] == 0xffff &&
8058 wcode[3] == 0xffff) || (wcode[0] == 0 && wcode[1] == 0 &&
8059 wcode[2] == 0 && wcode[3] == 0)) {
8060 ql_log(ql_log_fatal, vha, 0x0086,
8061 "Unable to verify integrity of firmware image.\n");
8062 ql_log(ql_log_fatal, vha, 0x0087,
8063 "Firmware data: %04x %04x %04x %04x.\n",
8064 wcode[0], wcode[1], wcode[2], wcode[3]);
8065 goto fail_fw_integrity;
8066 }
8067
8068 seg = blob->segs;
8069 while (*seg && rval == QLA_SUCCESS) {
8070 risc_addr = *seg;
8071 *srisc_addr = *srisc_addr == 0 ? *seg : *srisc_addr;
8072 risc_size = be16_to_cpu(fwcode[3]);
8073
8074
8075 fwclen += risc_size * sizeof(uint16_t);
8076 if (blob->fw->size < fwclen) {
8077 ql_log(ql_log_fatal, vha, 0x0088,
8078 "Unable to verify integrity of firmware image "
8079 "(%zd).\n", blob->fw->size);
8080 goto fail_fw_integrity;
8081 }
8082
8083 fragment = 0;
8084 while (risc_size > 0 && rval == QLA_SUCCESS) {
8085 wlen = (uint16_t)(ha->fw_transfer_size >> 1);
8086 if (wlen > risc_size)
8087 wlen = risc_size;
8088 ql_dbg(ql_dbg_init, vha, 0x0089,
8089 "Loading risc segment@ risc addr %x number of "
8090 "words 0x%x.\n", risc_addr, wlen);
8091
8092 for (i = 0; i < wlen; i++)
8093 wcode[i] = swab16((__force u32)fwcode[i]);
8094
8095 rval = qla2x00_load_ram(vha, req->dma, risc_addr,
8096 wlen);
8097 if (rval) {
8098 ql_log(ql_log_fatal, vha, 0x008a,
8099 "Failed to load segment %d of firmware.\n",
8100 fragment);
8101 break;
8102 }
8103
8104 fwcode += wlen;
8105 risc_addr += wlen;
8106 risc_size -= wlen;
8107 fragment++;
8108 }
8109
8110
8111 seg++;
8112 }
8113 return rval;
8114
8115fail_fw_integrity:
8116 return QLA_FUNCTION_FAILED;
8117}
8118
8119static int
8120qla24xx_load_risc_blob(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8121{
8122 int rval;
8123 uint templates, segments, fragment;
8124 uint32_t *dcode;
8125 ulong dlen;
8126 uint32_t risc_addr, risc_size, risc_attr = 0;
8127 ulong i;
8128 uint j;
8129 struct fw_blob *blob;
8130 __be32 *fwcode;
8131 struct qla_hw_data *ha = vha->hw;
8132 struct req_que *req = ha->req_q_map[0];
8133 struct fwdt *fwdt = ha->fwdt;
8134
8135 ql_dbg(ql_dbg_init, vha, 0x0090,
8136 "-> FW: Loading via request-firmware.\n");
8137
8138 blob = qla2x00_request_firmware(vha);
8139 if (!blob) {
8140 ql_log(ql_log_warn, vha, 0x0092,
8141 "-> Firmware file not found.\n");
8142
8143 return QLA_FUNCTION_FAILED;
8144 }
8145
8146 fwcode = (__force __be32 *)blob->fw->data;
8147 dcode = (__force uint32_t *)fwcode;
8148 if (qla24xx_risc_firmware_invalid(dcode)) {
8149 ql_log(ql_log_fatal, vha, 0x0093,
8150 "Unable to verify integrity of firmware image (%zd).\n",
8151 blob->fw->size);
8152 ql_log(ql_log_fatal, vha, 0x0095,
8153 "Firmware data: %08x %08x %08x %08x.\n",
8154 dcode[0], dcode[1], dcode[2], dcode[3]);
8155 return QLA_FUNCTION_FAILED;
8156 }
8157
8158 dcode = (uint32_t *)req->ring;
8159 *srisc_addr = 0;
8160 segments = FA_RISC_CODE_SEGMENTS;
8161 for (j = 0; j < segments; j++) {
8162 ql_dbg(ql_dbg_init, vha, 0x0096,
8163 "-> Loading segment %u...\n", j);
8164 risc_addr = be32_to_cpu(fwcode[2]);
8165 risc_size = be32_to_cpu(fwcode[3]);
8166
8167 if (!*srisc_addr) {
8168 *srisc_addr = risc_addr;
8169 risc_attr = be32_to_cpu(fwcode[9]);
8170 }
8171
8172 dlen = ha->fw_transfer_size >> 2;
8173 for (fragment = 0; risc_size; fragment++) {
8174 if (dlen > risc_size)
8175 dlen = risc_size;
8176
8177 ql_dbg(ql_dbg_init, vha, 0x0097,
8178 "-> Loading fragment %u: %#x <- %#x (%#lx words)...\n",
8179 fragment, risc_addr,
8180 (uint32_t)(fwcode - (typeof(fwcode))blob->fw->data),
8181 dlen);
8182
8183 for (i = 0; i < dlen; i++)
8184 dcode[i] = swab32((__force u32)fwcode[i]);
8185
8186 rval = qla2x00_load_ram(vha, req->dma, risc_addr, dlen);
8187 if (rval) {
8188 ql_log(ql_log_fatal, vha, 0x0098,
8189 "-> Failed load firmware fragment %u.\n",
8190 fragment);
8191 return QLA_FUNCTION_FAILED;
8192 }
8193
8194 fwcode += dlen;
8195 risc_addr += dlen;
8196 risc_size -= dlen;
8197 }
8198 }
8199
8200 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
8201 return QLA_SUCCESS;
8202
8203 templates = (risc_attr & BIT_9) ? 2 : 1;
8204 ql_dbg(ql_dbg_init, vha, 0x0170, "-> templates = %u\n", templates);
8205 for (j = 0; j < templates; j++, fwdt++) {
8206 vfree(fwdt->template);
8207 fwdt->template = NULL;
8208 fwdt->length = 0;
8209
8210 risc_size = be32_to_cpu(fwcode[2]);
8211 ql_dbg(ql_dbg_init, vha, 0x0171,
8212 "-> fwdt%u template array at %#x (%#x dwords)\n",
8213 j, (uint32_t)((void *)fwcode - (void *)blob->fw->data),
8214 risc_size);
8215 if (!risc_size || !~risc_size) {
8216 ql_dbg(ql_dbg_init, vha, 0x0172,
8217 "-> fwdt%u failed to read array\n", j);
8218 goto failed;
8219 }
8220
8221
8222 fwcode += 7;
8223 risc_size -= 8;
8224
8225 ql_dbg(ql_dbg_init, vha, 0x0173,
8226 "-> fwdt%u template allocate template %#x words...\n",
8227 j, risc_size);
8228 fwdt->template = vmalloc(risc_size * sizeof(*dcode));
8229 if (!fwdt->template) {
8230 ql_log(ql_log_warn, vha, 0x0174,
8231 "-> fwdt%u failed allocate template.\n", j);
8232 goto failed;
8233 }
8234
8235 dcode = fwdt->template;
8236 for (i = 0; i < risc_size; i++)
8237 dcode[i] = (__force u32)fwcode[i];
8238
8239 if (!qla27xx_fwdt_template_valid(dcode)) {
8240 ql_log(ql_log_warn, vha, 0x0175,
8241 "-> fwdt%u failed template validate\n", j);
8242 goto failed;
8243 }
8244
8245 dlen = qla27xx_fwdt_template_size(dcode);
8246 ql_dbg(ql_dbg_init, vha, 0x0176,
8247 "-> fwdt%u template size %#lx bytes (%#lx words)\n",
8248 j, dlen, dlen / sizeof(*dcode));
8249 if (dlen > risc_size * sizeof(*dcode)) {
8250 ql_log(ql_log_warn, vha, 0x0177,
8251 "-> fwdt%u template exceeds array (%-lu bytes)\n",
8252 j, dlen - risc_size * sizeof(*dcode));
8253 goto failed;
8254 }
8255
8256 fwdt->length = dlen;
8257 ql_dbg(ql_dbg_init, vha, 0x0178,
8258 "-> fwdt%u loaded template ok\n", j);
8259
8260 fwcode += risc_size + 1;
8261 }
8262
8263 return QLA_SUCCESS;
8264
8265failed:
8266 vfree(fwdt->template);
8267 fwdt->template = NULL;
8268 fwdt->length = 0;
8269
8270 return QLA_SUCCESS;
8271}
8272
8273int
8274qla24xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8275{
8276 int rval;
8277
8278 if (ql2xfwloadbin == 1)
8279 return qla81xx_load_risc(vha, srisc_addr);
8280
8281
8282
8283
8284
8285
8286 rval = qla24xx_load_risc_blob(vha, srisc_addr);
8287 if (rval == QLA_SUCCESS)
8288 return rval;
8289
8290 return qla24xx_load_risc_flash(vha, srisc_addr,
8291 vha->hw->flt_region_fw);
8292}
8293
8294int
8295qla81xx_load_risc(scsi_qla_host_t *vha, uint32_t *srisc_addr)
8296{
8297 int rval;
8298 struct qla_hw_data *ha = vha->hw;
8299 struct active_regions active_regions = { };
8300
8301 if (ql2xfwloadbin == 2)
8302 goto try_blob_fw;
8303
8304
8305
8306
8307
8308
8309
8310 if (!IS_QLA27XX(ha) && !IS_QLA28XX(ha))
8311 goto try_primary_fw;
8312
8313 qla27xx_get_active_image(vha, &active_regions);
8314
8315 if (active_regions.global != QLA27XX_SECONDARY_IMAGE)
8316 goto try_primary_fw;
8317
8318 ql_dbg(ql_dbg_init, vha, 0x008b,
8319 "Loading secondary firmware image.\n");
8320 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw_sec);
8321 if (!rval)
8322 return rval;
8323
8324try_primary_fw:
8325 ql_dbg(ql_dbg_init, vha, 0x008b,
8326 "Loading primary firmware image.\n");
8327 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_fw);
8328 if (!rval)
8329 return rval;
8330
8331try_blob_fw:
8332 rval = qla24xx_load_risc_blob(vha, srisc_addr);
8333 if (!rval || !ha->flt_region_gold_fw)
8334 return rval;
8335
8336 ql_log(ql_log_info, vha, 0x0099,
8337 "Attempting to fallback to golden firmware.\n");
8338 rval = qla24xx_load_risc_flash(vha, srisc_addr, ha->flt_region_gold_fw);
8339 if (rval)
8340 return rval;
8341
8342 ql_log(ql_log_info, vha, 0x009a, "Need firmware flash update.\n");
8343 ha->flags.running_gold_fw = 1;
8344 return rval;
8345}
8346
8347void
8348qla2x00_try_to_stop_firmware(scsi_qla_host_t *vha)
8349{
8350 int ret, retries;
8351 struct qla_hw_data *ha = vha->hw;
8352
8353 if (ha->flags.pci_channel_io_perm_failure)
8354 return;
8355 if (!IS_FWI2_CAPABLE(ha))
8356 return;
8357 if (!ha->fw_major_version)
8358 return;
8359 if (!ha->flags.fw_started)
8360 return;
8361
8362 ret = qla2x00_stop_firmware(vha);
8363 for (retries = 5; ret != QLA_SUCCESS && ret != QLA_FUNCTION_TIMEOUT &&
8364 ret != QLA_INVALID_COMMAND && retries ; retries--) {
8365 ha->isp_ops->reset_chip(vha);
8366 if (ha->isp_ops->chip_diag(vha) != QLA_SUCCESS)
8367 continue;
8368 if (qla2x00_setup_chip(vha) != QLA_SUCCESS)
8369 continue;
8370 ql_log(ql_log_info, vha, 0x8015,
8371 "Attempting retry of stop-firmware command.\n");
8372 ret = qla2x00_stop_firmware(vha);
8373 }
8374
8375 QLA_FW_STOPPED(ha);
8376 ha->flags.fw_init_done = 0;
8377}
8378
8379int
8380qla24xx_configure_vhba(scsi_qla_host_t *vha)
8381{
8382 int rval = QLA_SUCCESS;
8383 int rval2;
8384 uint16_t mb[MAILBOX_REGISTER_COUNT];
8385 struct qla_hw_data *ha = vha->hw;
8386 struct scsi_qla_host *base_vha = pci_get_drvdata(ha->pdev);
8387
8388 if (!vha->vp_idx)
8389 return -EINVAL;
8390
8391 rval = qla2x00_fw_ready(base_vha);
8392
8393 if (rval == QLA_SUCCESS) {
8394 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8395 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
8396 }
8397
8398 vha->flags.management_server_logged_in = 0;
8399
8400
8401 rval2 = ha->isp_ops->fabric_login(vha, NPH_SNS, 0xff, 0xff, 0xfc, mb,
8402 BIT_1);
8403 if (rval2 != QLA_SUCCESS || mb[0] != MBS_COMMAND_COMPLETE) {
8404 if (rval2 == QLA_MEMORY_ALLOC_FAILED)
8405 ql_dbg(ql_dbg_init, vha, 0x0120,
8406 "Failed SNS login: loop_id=%x, rval2=%d\n",
8407 NPH_SNS, rval2);
8408 else
8409 ql_dbg(ql_dbg_init, vha, 0x0103,
8410 "Failed SNS login: loop_id=%x mb[0]=%x mb[1]=%x "
8411 "mb[2]=%x mb[6]=%x mb[7]=%x.\n",
8412 NPH_SNS, mb[0], mb[1], mb[2], mb[6], mb[7]);
8413 return (QLA_FUNCTION_FAILED);
8414 }
8415
8416 atomic_set(&vha->loop_down_timer, 0);
8417 atomic_set(&vha->loop_state, LOOP_UP);
8418 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
8419 set_bit(LOCAL_LOOP_UPDATE, &vha->dpc_flags);
8420 rval = qla2x00_loop_resync(base_vha);
8421
8422 return rval;
8423}
8424
8425
8426
8427static LIST_HEAD(qla_cs84xx_list);
8428static DEFINE_MUTEX(qla_cs84xx_mutex);
8429
8430static struct qla_chip_state_84xx *
8431qla84xx_get_chip(struct scsi_qla_host *vha)
8432{
8433 struct qla_chip_state_84xx *cs84xx;
8434 struct qla_hw_data *ha = vha->hw;
8435
8436 mutex_lock(&qla_cs84xx_mutex);
8437
8438
8439 list_for_each_entry(cs84xx, &qla_cs84xx_list, list) {
8440 if (cs84xx->bus == ha->pdev->bus) {
8441 kref_get(&cs84xx->kref);
8442 goto done;
8443 }
8444 }
8445
8446 cs84xx = kzalloc(sizeof(*cs84xx), GFP_KERNEL);
8447 if (!cs84xx)
8448 goto done;
8449
8450 kref_init(&cs84xx->kref);
8451 spin_lock_init(&cs84xx->access_lock);
8452 mutex_init(&cs84xx->fw_update_mutex);
8453 cs84xx->bus = ha->pdev->bus;
8454
8455 list_add_tail(&cs84xx->list, &qla_cs84xx_list);
8456done:
8457 mutex_unlock(&qla_cs84xx_mutex);
8458 return cs84xx;
8459}
8460
8461static void
8462__qla84xx_chip_release(struct kref *kref)
8463{
8464 struct qla_chip_state_84xx *cs84xx =
8465 container_of(kref, struct qla_chip_state_84xx, kref);
8466
8467 mutex_lock(&qla_cs84xx_mutex);
8468 list_del(&cs84xx->list);
8469 mutex_unlock(&qla_cs84xx_mutex);
8470 kfree(cs84xx);
8471}
8472
8473void
8474qla84xx_put_chip(struct scsi_qla_host *vha)
8475{
8476 struct qla_hw_data *ha = vha->hw;
8477
8478 if (ha->cs84xx)
8479 kref_put(&ha->cs84xx->kref, __qla84xx_chip_release);
8480}
8481
8482static int
8483qla84xx_init_chip(scsi_qla_host_t *vha)
8484{
8485 int rval;
8486 uint16_t status[2];
8487 struct qla_hw_data *ha = vha->hw;
8488
8489 mutex_lock(&ha->cs84xx->fw_update_mutex);
8490
8491 rval = qla84xx_verify_chip(vha, status);
8492
8493 mutex_unlock(&ha->cs84xx->fw_update_mutex);
8494
8495 return rval != QLA_SUCCESS || status[0] ? QLA_FUNCTION_FAILED :
8496 QLA_SUCCESS;
8497}
8498
8499
8500
8501int
8502qla81xx_nvram_config(scsi_qla_host_t *vha)
8503{
8504 int rval;
8505 struct init_cb_81xx *icb;
8506 struct nvram_81xx *nv;
8507 __le32 *dptr;
8508 uint8_t *dptr1, *dptr2;
8509 uint32_t chksum;
8510 uint16_t cnt;
8511 struct qla_hw_data *ha = vha->hw;
8512 uint32_t faddr;
8513 struct active_regions active_regions = { };
8514
8515 rval = QLA_SUCCESS;
8516 icb = (struct init_cb_81xx *)ha->init_cb;
8517 nv = ha->nvram;
8518
8519
8520 ha->nvram_size = sizeof(*nv);
8521 ha->vpd_size = FA_NVRAM_VPD_SIZE;
8522 if (IS_P3P_TYPE(ha) || IS_QLA8031(ha))
8523 ha->vpd_size = FA_VPD_SIZE_82XX;
8524
8525 if (IS_QLA28XX(ha) || IS_QLA27XX(ha))
8526 qla28xx_get_aux_images(vha, &active_regions);
8527
8528
8529 ha->vpd = ha->nvram + VPD_OFFSET;
8530
8531 faddr = ha->flt_region_vpd;
8532 if (IS_QLA28XX(ha)) {
8533 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8534 faddr = ha->flt_region_vpd_sec;
8535 ql_dbg(ql_dbg_init, vha, 0x0110,
8536 "Loading %s nvram image.\n",
8537 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8538 "primary" : "secondary");
8539 }
8540 ha->isp_ops->read_optrom(vha, ha->vpd, faddr << 2, ha->vpd_size);
8541
8542
8543 faddr = ha->flt_region_nvram;
8544 if (IS_QLA28XX(ha)) {
8545 if (active_regions.aux.vpd_nvram == QLA27XX_SECONDARY_IMAGE)
8546 faddr = ha->flt_region_nvram_sec;
8547 }
8548 ql_dbg(ql_dbg_init, vha, 0x0110,
8549 "Loading %s nvram image.\n",
8550 active_regions.aux.vpd_nvram == QLA27XX_PRIMARY_IMAGE ?
8551 "primary" : "secondary");
8552 ha->isp_ops->read_optrom(vha, ha->nvram, faddr << 2, ha->nvram_size);
8553
8554 dptr = (__force __le32 *)nv;
8555 for (cnt = 0, chksum = 0; cnt < ha->nvram_size >> 2; cnt++, dptr++)
8556 chksum += le32_to_cpu(*dptr);
8557
8558 ql_dbg(ql_dbg_init + ql_dbg_buffer, vha, 0x0111,
8559 "Contents of NVRAM:\n");
8560 ql_dump_buffer(ql_dbg_init + ql_dbg_buffer, vha, 0x0112,
8561 nv, ha->nvram_size);
8562
8563
8564 if (chksum || memcmp("ISP ", nv->id, sizeof(nv->id)) ||
8565 le16_to_cpu(nv->nvram_version) < ICB_VERSION) {
8566
8567 ql_log(ql_log_info, vha, 0x0073,
8568 "Inconsistent NVRAM checksum=%#x id=%.4s version=%#x.\n",
8569 chksum, nv->id, le16_to_cpu(nv->nvram_version));
8570 ql_dump_buffer(ql_dbg_init, vha, 0x0073, nv, sizeof(*nv));
8571 ql_log(ql_log_info, vha, 0x0074,
8572 "Falling back to functioning (yet invalid -- WWPN) "
8573 "defaults.\n");
8574
8575
8576
8577
8578 memset(nv, 0, ha->nvram_size);
8579 nv->nvram_version = cpu_to_le16(ICB_VERSION);
8580 nv->version = cpu_to_le16(ICB_VERSION);
8581 nv->frame_payload_size = cpu_to_le16(2048);
8582 nv->execution_throttle = cpu_to_le16(0xFFFF);
8583 nv->exchange_count = cpu_to_le16(0);
8584 nv->port_name[0] = 0x21;
8585 nv->port_name[1] = 0x00 + ha->port_no + 1;
8586 nv->port_name[2] = 0x00;
8587 nv->port_name[3] = 0xe0;
8588 nv->port_name[4] = 0x8b;
8589 nv->port_name[5] = 0x1c;
8590 nv->port_name[6] = 0x55;
8591 nv->port_name[7] = 0x86;
8592 nv->node_name[0] = 0x20;
8593 nv->node_name[1] = 0x00;
8594 nv->node_name[2] = 0x00;
8595 nv->node_name[3] = 0xe0;
8596 nv->node_name[4] = 0x8b;
8597 nv->node_name[5] = 0x1c;
8598 nv->node_name[6] = 0x55;
8599 nv->node_name[7] = 0x86;
8600 nv->login_retry_count = cpu_to_le16(8);
8601 nv->interrupt_delay_timer = cpu_to_le16(0);
8602 nv->login_timeout = cpu_to_le16(0);
8603 nv->firmware_options_1 =
8604 cpu_to_le32(BIT_14|BIT_13|BIT_2|BIT_1);
8605 nv->firmware_options_2 = cpu_to_le32(2 << 4);
8606 nv->firmware_options_2 |= cpu_to_le32(BIT_12);
8607 nv->firmware_options_3 = cpu_to_le32(2 << 13);
8608 nv->host_p = cpu_to_le32(BIT_11|BIT_10);
8609 nv->efi_parameters = cpu_to_le32(0);
8610 nv->reset_delay = 5;
8611 nv->max_luns_per_target = cpu_to_le16(128);
8612 nv->port_down_retry_count = cpu_to_le16(30);
8613 nv->link_down_timeout = cpu_to_le16(180);
8614 nv->enode_mac[0] = 0x00;
8615 nv->enode_mac[1] = 0xC0;
8616 nv->enode_mac[2] = 0xDD;
8617 nv->enode_mac[3] = 0x04;
8618 nv->enode_mac[4] = 0x05;
8619 nv->enode_mac[5] = 0x06 + ha->port_no + 1;
8620
8621 rval = 1;
8622 }
8623
8624 if (IS_T10_PI_CAPABLE(ha))
8625 nv->frame_payload_size &= cpu_to_le16(~7);
8626
8627 qlt_81xx_config_nvram_stage1(vha, nv);
8628
8629
8630 memset(icb, 0, ha->init_cb_size);
8631
8632
8633 dptr1 = (uint8_t *)icb;
8634 dptr2 = (uint8_t *)&nv->version;
8635 cnt = (uint8_t *)&icb->response_q_inpointer - (uint8_t *)&icb->version;
8636 while (cnt--)
8637 *dptr1++ = *dptr2++;
8638
8639 icb->login_retry_count = nv->login_retry_count;
8640
8641
8642 dptr1 = (uint8_t *)&icb->interrupt_delay_timer;
8643 dptr2 = (uint8_t *)&nv->interrupt_delay_timer;
8644 cnt = (uint8_t *)&icb->reserved_5 -
8645 (uint8_t *)&icb->interrupt_delay_timer;
8646 while (cnt--)
8647 *dptr1++ = *dptr2++;
8648
8649 memcpy(icb->enode_mac, nv->enode_mac, sizeof(icb->enode_mac));
8650
8651 if (!memcmp(icb->enode_mac, "\0\0\0\0\0\0", sizeof(icb->enode_mac))) {
8652 icb->enode_mac[0] = 0x00;
8653 icb->enode_mac[1] = 0xC0;
8654 icb->enode_mac[2] = 0xDD;
8655 icb->enode_mac[3] = 0x04;
8656 icb->enode_mac[4] = 0x05;
8657 icb->enode_mac[5] = 0x06 + ha->port_no + 1;
8658 }
8659
8660
8661 memcpy(ha->ex_init_cb, &nv->ex_version, sizeof(*ha->ex_init_cb));
8662 ha->frame_payload_size = le16_to_cpu(icb->frame_payload_size);
8663
8664
8665
8666 qla2x00_set_model_info(vha, nv->model_name, sizeof(nv->model_name),
8667 "QLE8XXX");
8668
8669 qlt_81xx_config_nvram_stage2(vha, icb);
8670
8671
8672 if (nv->host_p & cpu_to_le32(BIT_15)) {
8673 memcpy(icb->node_name, nv->alternate_node_name, WWN_SIZE);
8674 memcpy(icb->port_name, nv->alternate_port_name, WWN_SIZE);
8675 }
8676
8677
8678 if ((icb->firmware_options_1 & cpu_to_le32(BIT_14)) == 0) {
8679
8680
8681
8682
8683 memcpy(icb->node_name, icb->port_name, WWN_SIZE);
8684 icb->node_name[0] &= 0xF0;
8685 }
8686
8687 if (IS_QLA28XX(ha) || IS_QLA27XX(ha)) {
8688 if ((nv->enhanced_features & BIT_7) == 0)
8689 ha->flags.scm_supported_a = 1;
8690 }
8691
8692
8693 ha->flags.disable_risc_code_load = 0;
8694 ha->flags.enable_lip_reset = 0;
8695 ha->flags.enable_lip_full_login =
8696 le32_to_cpu(nv->host_p) & BIT_10 ? 1 : 0;
8697 ha->flags.enable_target_reset =
8698 le32_to_cpu(nv->host_p) & BIT_11 ? 1 : 0;
8699 ha->flags.enable_led_scheme = 0;
8700 ha->flags.disable_serdes = le32_to_cpu(nv->host_p) & BIT_5 ? 1 : 0;
8701
8702 ha->operating_mode = (le32_to_cpu(icb->firmware_options_2) &
8703 (BIT_6 | BIT_5 | BIT_4)) >> 4;
8704
8705
8706 ha->serial0 = icb->port_name[5];
8707 ha->serial1 = icb->port_name[6];
8708 ha->serial2 = icb->port_name[7];
8709 memcpy(vha->node_name, icb->node_name, WWN_SIZE);
8710 memcpy(vha->port_name, icb->port_name, WWN_SIZE);
8711
8712 icb->execution_throttle = cpu_to_le16(0xFFFF);
8713
8714 ha->retry_count = le16_to_cpu(nv->login_retry_count);
8715
8716
8717 if (le16_to_cpu(nv->login_timeout) < ql2xlogintimeout)
8718 nv->login_timeout = cpu_to_le16(ql2xlogintimeout);
8719 if (le16_to_cpu(nv->login_timeout) < 4)
8720 nv->login_timeout = cpu_to_le16(4);
8721 ha->login_timeout = le16_to_cpu(nv->login_timeout);
8722
8723
8724 ha->r_a_tov = 100;
8725
8726 ha->loop_reset_delay = nv->reset_delay;
8727
8728
8729
8730
8731
8732
8733
8734
8735
8736
8737
8738 if (le16_to_cpu(nv->link_down_timeout) == 0) {
8739 ha->loop_down_abort_time =
8740 (LOOP_DOWN_TIME - LOOP_DOWN_TIMEOUT);
8741 } else {
8742 ha->link_down_timeout = le16_to_cpu(nv->link_down_timeout);
8743 ha->loop_down_abort_time =
8744 (LOOP_DOWN_TIME - ha->link_down_timeout);
8745 }
8746
8747
8748 ha->port_down_retry_count = le16_to_cpu(nv->port_down_retry_count);
8749 if (qlport_down_retry)
8750 ha->port_down_retry_count = qlport_down_retry;
8751
8752
8753 ha->login_retry_count = le16_to_cpu(nv->login_retry_count);
8754 if (ha->port_down_retry_count ==
8755 le16_to_cpu(nv->port_down_retry_count) &&
8756 ha->port_down_retry_count > 3)
8757 ha->login_retry_count = ha->port_down_retry_count;
8758 else if (ha->port_down_retry_count > (int)ha->login_retry_count)
8759 ha->login_retry_count = ha->port_down_retry_count;
8760 if (ql2xloginretrycount)
8761 ha->login_retry_count = ql2xloginretrycount;
8762
8763
8764 if (!vha->hw->flags.msix_enabled &&
8765 (IS_QLA83XX(ha) || IS_QLA27XX(ha) || IS_QLA28XX(ha)))
8766 icb->firmware_options_2 |= cpu_to_le32(BIT_22);
8767
8768
8769 if (!vha->flags.init_done) {
8770 ha->zio_mode = le32_to_cpu(icb->firmware_options_2) &
8771 (BIT_3 | BIT_2 | BIT_1 | BIT_0);
8772 ha->zio_timer = le16_to_cpu(icb->interrupt_delay_timer) ?
8773 le16_to_cpu(icb->interrupt_delay_timer) : 2;
8774 }
8775 icb->firmware_options_2 &= cpu_to_le32(
8776 ~(BIT_3 | BIT_2 | BIT_1 | BIT_0));
8777 vha->flags.process_response_queue = 0;
8778 if (ha->zio_mode != QLA_ZIO_DISABLED) {
8779 ha->zio_mode = QLA_ZIO_MODE_6;
8780
8781 ql_log(ql_log_info, vha, 0x0075,
8782 "ZIO mode %d enabled; timer delay (%d us).\n",
8783 ha->zio_mode,
8784 ha->zio_timer * 100);
8785
8786 icb->firmware_options_2 |= cpu_to_le32(
8787 (uint32_t)ha->zio_mode);
8788 icb->interrupt_delay_timer = cpu_to_le16(ha->zio_timer);
8789 vha->flags.process_response_queue = 1;
8790 }
8791
8792
8793 icb->firmware_options_3 |= cpu_to_le32(BIT_0);
8794
8795
8796 icb->firmware_options_3 |= cpu_to_le32(BIT_8);
8797
8798
8799 ha->fc4_type_priority = qla2xxx_get_fc4_priority(vha);
8800
8801 if (rval) {
8802 ql_log(ql_log_warn, vha, 0x0076,
8803 "NVRAM configuration failed.\n");
8804 }
8805 return (rval);
8806}
8807
8808int
8809qla82xx_restart_isp(scsi_qla_host_t *vha)
8810{
8811 int status, rval;
8812 struct qla_hw_data *ha = vha->hw;
8813 struct scsi_qla_host *vp;
8814 unsigned long flags;
8815
8816 status = qla2x00_init_rings(vha);
8817 if (!status) {
8818 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8819 ha->flags.chip_reset_done = 1;
8820
8821 status = qla2x00_fw_ready(vha);
8822 if (!status) {
8823
8824 qla2x00_marker(vha, ha->base_qpair, 0, 0, MK_SYNC_ALL);
8825 vha->flags.online = 1;
8826 set_bit(LOOP_RESYNC_NEEDED, &vha->dpc_flags);
8827 }
8828
8829
8830 if ((vha->device_flags & DFLG_NO_CABLE))
8831 status = 0;
8832 }
8833
8834 if (!status) {
8835 clear_bit(RESET_MARKER_NEEDED, &vha->dpc_flags);
8836
8837 if (!atomic_read(&vha->loop_down_timer)) {
8838
8839
8840
8841
8842 vha->marker_needed = 1;
8843 }
8844
8845 ha->isp_ops->enable_intrs(ha);
8846
8847 ha->isp_abort_cnt = 0;
8848 clear_bit(ISP_ABORT_RETRY, &vha->dpc_flags);
8849
8850
8851 status = qla82xx_check_md_needed(vha);
8852
8853 if (ha->fce) {
8854 ha->flags.fce_enabled = 1;
8855 memset(ha->fce, 0,
8856 fce_calc_size(ha->fce_bufs));
8857 rval = qla2x00_enable_fce_trace(vha,
8858 ha->fce_dma, ha->fce_bufs, ha->fce_mb,
8859 &ha->fce_bufs);
8860 if (rval) {
8861 ql_log(ql_log_warn, vha, 0x8001,
8862 "Unable to reinitialize FCE (%d).\n",
8863 rval);
8864 ha->flags.fce_enabled = 0;
8865 }
8866 }
8867
8868 if (ha->eft) {
8869 memset(ha->eft, 0, EFT_SIZE);
8870 rval = qla2x00_enable_eft_trace(vha,
8871 ha->eft_dma, EFT_NUM_BUFFERS);
8872 if (rval) {
8873 ql_log(ql_log_warn, vha, 0x8010,
8874 "Unable to reinitialize EFT (%d).\n",
8875 rval);
8876 }
8877 }
8878 }
8879
8880 if (!status) {
8881 ql_dbg(ql_dbg_taskm, vha, 0x8011,
8882 "qla82xx_restart_isp succeeded.\n");
8883
8884 spin_lock_irqsave(&ha->vport_slock, flags);
8885 list_for_each_entry(vp, &ha->vp_list, list) {
8886 if (vp->vp_idx) {
8887 atomic_inc(&vp->vref_count);
8888 spin_unlock_irqrestore(&ha->vport_slock, flags);
8889
8890 qla2x00_vp_abort_isp(vp);
8891
8892 spin_lock_irqsave(&ha->vport_slock, flags);
8893 atomic_dec(&vp->vref_count);
8894 }
8895 }
8896 spin_unlock_irqrestore(&ha->vport_slock, flags);
8897
8898 } else {
8899 ql_log(ql_log_warn, vha, 0x8016,
8900 "qla82xx_restart_isp **** FAILED ****.\n");
8901 }
8902
8903 return status;
8904}
8905
8906
8907
8908
8909
8910
8911
8912
8913
8914
8915
8916
8917
8918
8919
8920
8921
8922
8923
8924static int
8925qla24xx_get_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
8926{
8927 int i, entries;
8928 uint8_t pid_match, wwn_match;
8929 int priority;
8930 uint32_t pid1, pid2;
8931 uint64_t wwn1, wwn2;
8932 struct qla_fcp_prio_entry *pri_entry;
8933 struct qla_hw_data *ha = vha->hw;
8934
8935 if (!ha->fcp_prio_cfg || !ha->flags.fcp_prio_enabled)
8936 return -1;
8937
8938 priority = -1;
8939 entries = ha->fcp_prio_cfg->num_entries;
8940 pri_entry = &ha->fcp_prio_cfg->entry[0];
8941
8942 for (i = 0; i < entries; i++) {
8943 pid_match = wwn_match = 0;
8944
8945 if (!(pri_entry->flags & FCP_PRIO_ENTRY_VALID)) {
8946 pri_entry++;
8947 continue;
8948 }
8949
8950
8951 if (pri_entry->flags & FCP_PRIO_ENTRY_SPID_VALID) {
8952 pid1 = pri_entry->src_pid & INVALID_PORT_ID;
8953 pid2 = vha->d_id.b24 & INVALID_PORT_ID;
8954 if (pid1 == INVALID_PORT_ID)
8955 pid_match++;
8956 else if (pid1 == pid2)
8957 pid_match++;
8958 }
8959
8960
8961 if (pri_entry->flags & FCP_PRIO_ENTRY_DPID_VALID) {
8962 pid1 = pri_entry->dst_pid & INVALID_PORT_ID;
8963 pid2 = fcport->d_id.b24 & INVALID_PORT_ID;
8964 if (pid1 == INVALID_PORT_ID)
8965 pid_match++;
8966 else if (pid1 == pid2)
8967 pid_match++;
8968 }
8969
8970
8971 if (pri_entry->flags & FCP_PRIO_ENTRY_SWWN_VALID) {
8972 wwn1 = wwn_to_u64(vha->port_name);
8973 wwn2 = wwn_to_u64(pri_entry->src_wwpn);
8974 if (wwn2 == (uint64_t)-1)
8975 wwn_match++;
8976 else if (wwn1 == wwn2)
8977 wwn_match++;
8978 }
8979
8980
8981 if (pri_entry->flags & FCP_PRIO_ENTRY_DWWN_VALID) {
8982 wwn1 = wwn_to_u64(fcport->port_name);
8983 wwn2 = wwn_to_u64(pri_entry->dst_wwpn);
8984 if (wwn2 == (uint64_t)-1)
8985 wwn_match++;
8986 else if (wwn1 == wwn2)
8987 wwn_match++;
8988 }
8989
8990 if (pid_match == 2 || wwn_match == 2) {
8991
8992 if (pri_entry->flags & FCP_PRIO_ENTRY_TAG_VALID)
8993 priority = pri_entry->tag;
8994 break;
8995 }
8996
8997 pri_entry++;
8998 }
8999
9000 return priority;
9001}
9002
9003
9004
9005
9006
9007
9008
9009
9010
9011
9012
9013
9014
9015
9016
9017int
9018qla24xx_update_fcport_fcp_prio(scsi_qla_host_t *vha, fc_port_t *fcport)
9019{
9020 int ret;
9021 int priority;
9022 uint16_t mb[5];
9023
9024 if (fcport->port_type != FCT_TARGET ||
9025 fcport->loop_id == FC_NO_LOOP_ID)
9026 return QLA_FUNCTION_FAILED;
9027
9028 priority = qla24xx_get_fcp_prio(vha, fcport);
9029 if (priority < 0)
9030 return QLA_FUNCTION_FAILED;
9031
9032 if (IS_P3P_TYPE(vha->hw)) {
9033 fcport->fcp_prio = priority & 0xf;
9034 return QLA_SUCCESS;
9035 }
9036
9037 ret = qla24xx_set_fcp_prio(vha, fcport->loop_id, priority, mb);
9038 if (ret == QLA_SUCCESS) {
9039 if (fcport->fcp_prio != priority)
9040 ql_dbg(ql_dbg_user, vha, 0x709e,
9041 "Updated FCP_CMND priority - value=%d loop_id=%d "
9042 "port_id=%02x%02x%02x.\n", priority,
9043 fcport->loop_id, fcport->d_id.b.domain,
9044 fcport->d_id.b.area, fcport->d_id.b.al_pa);
9045 fcport->fcp_prio = priority & 0xf;
9046 } else
9047 ql_dbg(ql_dbg_user, vha, 0x704f,
9048 "Unable to update FCP_CMND priority - ret=0x%x for "
9049 "loop_id=%d port_id=%02x%02x%02x.\n", ret, fcport->loop_id,
9050 fcport->d_id.b.domain, fcport->d_id.b.area,
9051 fcport->d_id.b.al_pa);
9052 return ret;
9053}
9054
9055
9056
9057
9058
9059
9060
9061
9062
9063
9064
9065
9066
9067
9068int
9069qla24xx_update_all_fcp_prio(scsi_qla_host_t *vha)
9070{
9071 int ret;
9072 fc_port_t *fcport;
9073
9074 ret = QLA_FUNCTION_FAILED;
9075
9076 list_for_each_entry(fcport, &vha->vp_fcports, list)
9077 ret = qla24xx_update_fcport_fcp_prio(vha, fcport);
9078
9079 return ret;
9080}
9081
9082struct qla_qpair *qla2xxx_create_qpair(struct scsi_qla_host *vha, int qos,
9083 int vp_idx, bool startqp)
9084{
9085 int rsp_id = 0;
9086 int req_id = 0;
9087 int i;
9088 struct qla_hw_data *ha = vha->hw;
9089 uint16_t qpair_id = 0;
9090 struct qla_qpair *qpair = NULL;
9091 struct qla_msix_entry *msix;
9092
9093 if (!(ha->fw_attributes & BIT_6) || !ha->flags.msix_enabled) {
9094 ql_log(ql_log_warn, vha, 0x00181,
9095 "FW/Driver is not multi-queue capable.\n");
9096 return NULL;
9097 }
9098
9099 if (ql2xmqsupport || ql2xnvmeenable) {
9100 qpair = kzalloc(sizeof(struct qla_qpair), GFP_KERNEL);
9101 if (qpair == NULL) {
9102 ql_log(ql_log_warn, vha, 0x0182,
9103 "Failed to allocate memory for queue pair.\n");
9104 return NULL;
9105 }
9106
9107 qpair->hw = vha->hw;
9108 qpair->vha = vha;
9109 qpair->qp_lock_ptr = &qpair->qp_lock;
9110 spin_lock_init(&qpair->qp_lock);
9111 qpair->use_shadow_reg = IS_SHADOW_REG_CAPABLE(ha) ? 1 : 0;
9112
9113
9114 mutex_lock(&ha->mq_lock);
9115 qpair_id = find_first_zero_bit(ha->qpair_qid_map, ha->max_qpairs);
9116 if (ha->num_qpairs >= ha->max_qpairs) {
9117 mutex_unlock(&ha->mq_lock);
9118 ql_log(ql_log_warn, vha, 0x0183,
9119 "No resources to create additional q pair.\n");
9120 goto fail_qid_map;
9121 }
9122 ha->num_qpairs++;
9123 set_bit(qpair_id, ha->qpair_qid_map);
9124 ha->queue_pair_map[qpair_id] = qpair;
9125 qpair->id = qpair_id;
9126 qpair->vp_idx = vp_idx;
9127 qpair->fw_started = ha->flags.fw_started;
9128 INIT_LIST_HEAD(&qpair->hints_list);
9129 qpair->chip_reset = ha->base_qpair->chip_reset;
9130 qpair->enable_class_2 = ha->base_qpair->enable_class_2;
9131 qpair->enable_explicit_conf =
9132 ha->base_qpair->enable_explicit_conf;
9133
9134 for (i = 0; i < ha->msix_count; i++) {
9135 msix = &ha->msix_entries[i];
9136 if (msix->in_use)
9137 continue;
9138 qpair->msix = msix;
9139 ql_dbg(ql_dbg_multiq, vha, 0xc00f,
9140 "Vector %x selected for qpair\n", msix->vector);
9141 break;
9142 }
9143 if (!qpair->msix) {
9144 ql_log(ql_log_warn, vha, 0x0184,
9145 "Out of MSI-X vectors!.\n");
9146 goto fail_msix;
9147 }
9148
9149 qpair->msix->in_use = 1;
9150 list_add_tail(&qpair->qp_list_elem, &vha->qp_list);
9151 qpair->pdev = ha->pdev;
9152 if (IS_QLA27XX(ha) || IS_QLA83XX(ha) || IS_QLA28XX(ha))
9153 qpair->reqq_start_iocbs = qla_83xx_start_iocbs;
9154
9155 mutex_unlock(&ha->mq_lock);
9156
9157
9158 rsp_id = qla25xx_create_rsp_que(ha, 0, 0, 0, qpair, startqp);
9159 if (!rsp_id) {
9160 ql_log(ql_log_warn, vha, 0x0185,
9161 "Failed to create response queue.\n");
9162 goto fail_rsp;
9163 }
9164
9165 qpair->rsp = ha->rsp_q_map[rsp_id];
9166
9167
9168 req_id = qla25xx_create_req_que(ha, 0, vp_idx, 0, rsp_id, qos,
9169 startqp);
9170 if (!req_id) {
9171 ql_log(ql_log_warn, vha, 0x0186,
9172 "Failed to create request queue.\n");
9173 goto fail_req;
9174 }
9175
9176 qpair->req = ha->req_q_map[req_id];
9177 qpair->rsp->req = qpair->req;
9178 qpair->rsp->qpair = qpair;
9179
9180 qla_cpu_update(qpair, smp_processor_id());
9181
9182 if (IS_T10_PI_CAPABLE(ha) && ql2xenabledif) {
9183 if (ha->fw_attributes & BIT_4)
9184 qpair->difdix_supported = 1;
9185 }
9186
9187 qpair->srb_mempool = mempool_create_slab_pool(SRB_MIN_REQ, srb_cachep);
9188 if (!qpair->srb_mempool) {
9189 ql_log(ql_log_warn, vha, 0xd036,
9190 "Failed to create srb mempool for qpair %d\n",
9191 qpair->id);
9192 goto fail_mempool;
9193 }
9194
9195
9196 qpair->online = 1;
9197
9198 if (!vha->flags.qpairs_available)
9199 vha->flags.qpairs_available = 1;
9200
9201 ql_dbg(ql_dbg_multiq, vha, 0xc00d,
9202 "Request/Response queue pair created, id %d\n",
9203 qpair->id);
9204 ql_dbg(ql_dbg_init, vha, 0x0187,
9205 "Request/Response queue pair created, id %d\n",
9206 qpair->id);
9207 }
9208 return qpair;
9209
9210fail_mempool:
9211fail_req:
9212 qla25xx_delete_rsp_que(vha, qpair->rsp);
9213fail_rsp:
9214 mutex_lock(&ha->mq_lock);
9215 qpair->msix->in_use = 0;
9216 list_del(&qpair->qp_list_elem);
9217 if (list_empty(&vha->qp_list))
9218 vha->flags.qpairs_available = 0;
9219fail_msix:
9220 ha->queue_pair_map[qpair_id] = NULL;
9221 clear_bit(qpair_id, ha->qpair_qid_map);
9222 ha->num_qpairs--;
9223 mutex_unlock(&ha->mq_lock);
9224fail_qid_map:
9225 kfree(qpair);
9226 return NULL;
9227}
9228
9229int qla2xxx_delete_qpair(struct scsi_qla_host *vha, struct qla_qpair *qpair)
9230{
9231 int ret = QLA_FUNCTION_FAILED;
9232 struct qla_hw_data *ha = qpair->hw;
9233
9234 qpair->delete_in_progress = 1;
9235
9236 ret = qla25xx_delete_req_que(vha, qpair->req);
9237 if (ret != QLA_SUCCESS)
9238 goto fail;
9239
9240 ret = qla25xx_delete_rsp_que(vha, qpair->rsp);
9241 if (ret != QLA_SUCCESS)
9242 goto fail;
9243
9244 mutex_lock(&ha->mq_lock);
9245 ha->queue_pair_map[qpair->id] = NULL;
9246 clear_bit(qpair->id, ha->qpair_qid_map);
9247 ha->num_qpairs--;
9248 list_del(&qpair->qp_list_elem);
9249 if (list_empty(&vha->qp_list)) {
9250 vha->flags.qpairs_available = 0;
9251 vha->flags.qpairs_req_created = 0;
9252 vha->flags.qpairs_rsp_created = 0;
9253 }
9254 mempool_destroy(qpair->srb_mempool);
9255 kfree(qpair);
9256 mutex_unlock(&ha->mq_lock);
9257
9258 return QLA_SUCCESS;
9259fail:
9260 return ret;
9261}
9262
9263uint64_t
9264qla2x00_count_set_bits(uint32_t num)
9265{
9266
9267 u64 count = 0;
9268
9269 while (num) {
9270 num &= (num - 1);
9271 count++;
9272 }
9273 return count;
9274}
9275
9276uint64_t
9277qla2x00_get_num_tgts(scsi_qla_host_t *vha)
9278{
9279 fc_port_t *f, *tf;
9280 u64 count = 0;
9281
9282 f = NULL;
9283 tf = NULL;
9284
9285 list_for_each_entry_safe(f, tf, &vha->vp_fcports, list) {
9286 if (f->port_type != FCT_TARGET)
9287 continue;
9288 count++;
9289 }
9290 return count;
9291}
9292
9293int qla2xxx_reset_stats(struct Scsi_Host *host, u32 flags)
9294{
9295 scsi_qla_host_t *vha = shost_priv(host);
9296 fc_port_t *fcport = NULL;
9297 unsigned long int_flags;
9298
9299 if (flags & QLA2XX_HW_ERROR)
9300 vha->hw_err_cnt = 0;
9301 if (flags & QLA2XX_SHT_LNK_DWN)
9302 vha->short_link_down_cnt = 0;
9303 if (flags & QLA2XX_INT_ERR)
9304 vha->interface_err_cnt = 0;
9305 if (flags & QLA2XX_CMD_TIMEOUT)
9306 vha->cmd_timeout_cnt = 0;
9307 if (flags & QLA2XX_RESET_CMD_ERR)
9308 vha->reset_cmd_err_cnt = 0;
9309 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) {
9310 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags);
9311 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9312 fcport->tgt_short_link_down_cnt = 0;
9313 fcport->tgt_link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
9314 }
9315 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags);
9316 }
9317 vha->link_down_time = QLA2XX_MAX_LINK_DOWN_TIME;
9318 return 0;
9319}
9320
9321int qla2xxx_start_stats(struct Scsi_Host *host, u32 flags)
9322{
9323 return qla2xxx_reset_stats(host, flags);
9324}
9325
9326int qla2xxx_stop_stats(struct Scsi_Host *host, u32 flags)
9327{
9328 return qla2xxx_reset_stats(host, flags);
9329}
9330
9331int qla2xxx_get_ini_stats(struct Scsi_Host *host, u32 flags,
9332 void *data, u64 size)
9333{
9334 scsi_qla_host_t *vha = shost_priv(host);
9335 struct ql_vnd_host_stats_resp *resp = (struct ql_vnd_host_stats_resp *)data;
9336 struct ql_vnd_stats *rsp_data = &resp->stats;
9337 u64 ini_entry_count = 0;
9338 u64 i = 0;
9339 u64 entry_count = 0;
9340 u64 num_tgt = 0;
9341 u32 tmp_stat_type = 0;
9342 fc_port_t *fcport = NULL;
9343 unsigned long int_flags;
9344
9345
9346 tmp_stat_type = flags;
9347
9348 if (tmp_stat_type & BIT_17) {
9349 num_tgt = qla2x00_get_num_tgts(vha);
9350
9351 tmp_stat_type &= ~(1 << 17);
9352 }
9353 ini_entry_count = qla2x00_count_set_bits(tmp_stat_type);
9354
9355 entry_count = ini_entry_count + num_tgt;
9356
9357 rsp_data->entry_count = entry_count;
9358
9359 i = 0;
9360 if (flags & QLA2XX_HW_ERROR) {
9361 rsp_data->entry[i].stat_type = QLA2XX_HW_ERROR;
9362 rsp_data->entry[i].tgt_num = 0x0;
9363 rsp_data->entry[i].cnt = vha->hw_err_cnt;
9364 i++;
9365 }
9366
9367 if (flags & QLA2XX_SHT_LNK_DWN) {
9368 rsp_data->entry[i].stat_type = QLA2XX_SHT_LNK_DWN;
9369 rsp_data->entry[i].tgt_num = 0x0;
9370 rsp_data->entry[i].cnt = vha->short_link_down_cnt;
9371 i++;
9372 }
9373
9374 if (flags & QLA2XX_INT_ERR) {
9375 rsp_data->entry[i].stat_type = QLA2XX_INT_ERR;
9376 rsp_data->entry[i].tgt_num = 0x0;
9377 rsp_data->entry[i].cnt = vha->interface_err_cnt;
9378 i++;
9379 }
9380
9381 if (flags & QLA2XX_CMD_TIMEOUT) {
9382 rsp_data->entry[i].stat_type = QLA2XX_CMD_TIMEOUT;
9383 rsp_data->entry[i].tgt_num = 0x0;
9384 rsp_data->entry[i].cnt = vha->cmd_timeout_cnt;
9385 i++;
9386 }
9387
9388 if (flags & QLA2XX_RESET_CMD_ERR) {
9389 rsp_data->entry[i].stat_type = QLA2XX_RESET_CMD_ERR;
9390 rsp_data->entry[i].tgt_num = 0x0;
9391 rsp_data->entry[i].cnt = vha->reset_cmd_err_cnt;
9392 i++;
9393 }
9394
9395
9396
9397
9398 if (flags & QLA2XX_TGT_SHT_LNK_DOWN) {
9399 spin_lock_irqsave(&vha->hw->tgt.sess_lock, int_flags);
9400 list_for_each_entry(fcport, &vha->vp_fcports, list) {
9401 if (fcport->port_type != FCT_TARGET)
9402 continue;
9403 if (!fcport->rport)
9404 continue;
9405 rsp_data->entry[i].stat_type = QLA2XX_TGT_SHT_LNK_DOWN;
9406 rsp_data->entry[i].tgt_num = fcport->rport->number;
9407 rsp_data->entry[i].cnt = fcport->tgt_short_link_down_cnt;
9408 i++;
9409 }
9410 spin_unlock_irqrestore(&vha->hw->tgt.sess_lock, int_flags);
9411 }
9412 resp->status = EXT_STATUS_OK;
9413
9414 return 0;
9415}
9416
9417int qla2xxx_get_tgt_stats(struct Scsi_Host *host, u32 flags,
9418 struct fc_rport *rport, void *data, u64 size)
9419{
9420 struct ql_vnd_tgt_stats_resp *tgt_data = data;
9421 fc_port_t *fcport = *(fc_port_t **)rport->dd_data;
9422
9423 tgt_data->status = 0;
9424 tgt_data->stats.entry_count = 1;
9425 tgt_data->stats.entry[0].stat_type = flags;
9426 tgt_data->stats.entry[0].tgt_num = rport->number;
9427 tgt_data->stats.entry[0].cnt = fcport->tgt_short_link_down_cnt;
9428
9429 return 0;
9430}
9431
9432int qla2xxx_disable_port(struct Scsi_Host *host)
9433{
9434 scsi_qla_host_t *vha = shost_priv(host);
9435
9436 vha->hw->flags.port_isolated = 1;
9437
9438 if (qla2x00_chip_is_down(vha))
9439 return 0;
9440
9441 if (vha->flags.online) {
9442 qla2x00_abort_isp_cleanup(vha);
9443 qla2x00_wait_for_sess_deletion(vha);
9444 }
9445
9446 return 0;
9447}
9448
9449int qla2xxx_enable_port(struct Scsi_Host *host)
9450{
9451 scsi_qla_host_t *vha = shost_priv(host);
9452
9453 vha->hw->flags.port_isolated = 0;
9454
9455 vha->flags.online = 1;
9456 set_bit(ISP_ABORT_NEEDED, &vha->dpc_flags);
9457 qla2xxx_wake_dpc(vha);
9458
9459 return 0;
9460}
9461