linux/drivers/scsi/pm8001/pm8001_hwi.c
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   1/*
   2 * PMC-Sierra SPC 8001 SAS/SATA based host adapters driver
   3 *
   4 * Copyright (c) 2008-2009 USI Co., Ltd.
   5 * All rights reserved.
   6 *
   7 * Redistribution and use in source and binary forms, with or without
   8 * modification, are permitted provided that the following conditions
   9 * are met:
  10 * 1. Redistributions of source code must retain the above copyright
  11 *    notice, this list of conditions, and the following disclaimer,
  12 *    without modification.
  13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
  14 *    substantially similar to the "NO WARRANTY" disclaimer below
  15 *    ("Disclaimer") and any redistribution must be conditioned upon
  16 *    including a substantially similar Disclaimer requirement for further
  17 *    binary redistribution.
  18 * 3. Neither the names of the above-listed copyright holders nor the names
  19 *    of any contributors may be used to endorse or promote products derived
  20 *    from this software without specific prior written permission.
  21 *
  22 * Alternatively, this software may be distributed under the terms of the
  23 * GNU General Public License ("GPL") version 2 as published by the Free
  24 * Software Foundation.
  25 *
  26 * NO WARRANTY
  27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
  30 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  31 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  32 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  33 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  34 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  35 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
  36 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  37 * POSSIBILITY OF SUCH DAMAGES.
  38 *
  39 */
  40 #include <linux/slab.h>
  41 #include "pm8001_sas.h"
  42 #include "pm8001_hwi.h"
  43 #include "pm8001_chips.h"
  44 #include "pm8001_ctl.h"
  45
  46/**
  47 * read_main_config_table - read the configure table and save it.
  48 * @pm8001_ha: our hba card information
  49 */
  50static void read_main_config_table(struct pm8001_hba_info *pm8001_ha)
  51{
  52        void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
  53        pm8001_ha->main_cfg_tbl.pm8001_tbl.signature    =
  54                                pm8001_mr32(address, 0x00);
  55        pm8001_ha->main_cfg_tbl.pm8001_tbl.interface_rev =
  56                                pm8001_mr32(address, 0x04);
  57        pm8001_ha->main_cfg_tbl.pm8001_tbl.firmware_rev =
  58                                pm8001_mr32(address, 0x08);
  59        pm8001_ha->main_cfg_tbl.pm8001_tbl.max_out_io   =
  60                                pm8001_mr32(address, 0x0C);
  61        pm8001_ha->main_cfg_tbl.pm8001_tbl.max_sgl      =
  62                                pm8001_mr32(address, 0x10);
  63        pm8001_ha->main_cfg_tbl.pm8001_tbl.ctrl_cap_flag =
  64                                pm8001_mr32(address, 0x14);
  65        pm8001_ha->main_cfg_tbl.pm8001_tbl.gst_offset   =
  66                                pm8001_mr32(address, 0x18);
  67        pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_queue_offset =
  68                pm8001_mr32(address, MAIN_IBQ_OFFSET);
  69        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_queue_offset =
  70                pm8001_mr32(address, MAIN_OBQ_OFFSET);
  71        pm8001_ha->main_cfg_tbl.pm8001_tbl.hda_mode_flag        =
  72                pm8001_mr32(address, MAIN_HDA_FLAGS_OFFSET);
  73
  74        /* read analog Setting offset from the configuration table */
  75        pm8001_ha->main_cfg_tbl.pm8001_tbl.anolog_setup_table_offset =
  76                pm8001_mr32(address, MAIN_ANALOG_SETUP_OFFSET);
  77
  78        /* read Error Dump Offset and Length */
  79        pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset0 =
  80                pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_OFFSET);
  81        pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length0 =
  82                pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP0_LENGTH);
  83        pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_offset1 =
  84                pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_OFFSET);
  85        pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_dump_length1 =
  86                pm8001_mr32(address, MAIN_FATAL_ERROR_RDUMP1_LENGTH);
  87}
  88
  89/**
  90 * read_general_status_table - read the general status table and save it.
  91 * @pm8001_ha: our hba card information
  92 */
  93static void read_general_status_table(struct pm8001_hba_info *pm8001_ha)
  94{
  95        void __iomem *address = pm8001_ha->general_stat_tbl_addr;
  96        pm8001_ha->gs_tbl.pm8001_tbl.gst_len_mpistate   =
  97                                pm8001_mr32(address, 0x00);
  98        pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state0   =
  99                                pm8001_mr32(address, 0x04);
 100        pm8001_ha->gs_tbl.pm8001_tbl.iq_freeze_state1   =
 101                                pm8001_mr32(address, 0x08);
 102        pm8001_ha->gs_tbl.pm8001_tbl.msgu_tcnt          =
 103                                pm8001_mr32(address, 0x0C);
 104        pm8001_ha->gs_tbl.pm8001_tbl.iop_tcnt           =
 105                                pm8001_mr32(address, 0x10);
 106        pm8001_ha->gs_tbl.pm8001_tbl.rsvd               =
 107                                pm8001_mr32(address, 0x14);
 108        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[0]       =
 109                                pm8001_mr32(address, 0x18);
 110        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[1]       =
 111                                pm8001_mr32(address, 0x1C);
 112        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[2]       =
 113                                pm8001_mr32(address, 0x20);
 114        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[3]       =
 115                                pm8001_mr32(address, 0x24);
 116        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[4]       =
 117                                pm8001_mr32(address, 0x28);
 118        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[5]       =
 119                                pm8001_mr32(address, 0x2C);
 120        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[6]       =
 121                                pm8001_mr32(address, 0x30);
 122        pm8001_ha->gs_tbl.pm8001_tbl.phy_state[7]       =
 123                                pm8001_mr32(address, 0x34);
 124        pm8001_ha->gs_tbl.pm8001_tbl.gpio_input_val     =
 125                                pm8001_mr32(address, 0x38);
 126        pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[0]           =
 127                                pm8001_mr32(address, 0x3C);
 128        pm8001_ha->gs_tbl.pm8001_tbl.rsvd1[1]           =
 129                                pm8001_mr32(address, 0x40);
 130        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[0]        =
 131                                pm8001_mr32(address, 0x44);
 132        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[1]        =
 133                                pm8001_mr32(address, 0x48);
 134        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[2]        =
 135                                pm8001_mr32(address, 0x4C);
 136        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[3]        =
 137                                pm8001_mr32(address, 0x50);
 138        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[4]        =
 139                                pm8001_mr32(address, 0x54);
 140        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[5]        =
 141                                pm8001_mr32(address, 0x58);
 142        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[6]        =
 143                                pm8001_mr32(address, 0x5C);
 144        pm8001_ha->gs_tbl.pm8001_tbl.recover_err_info[7]        =
 145                                pm8001_mr32(address, 0x60);
 146}
 147
 148/**
 149 * read_inbnd_queue_table - read the inbound queue table and save it.
 150 * @pm8001_ha: our hba card information
 151 */
 152static void read_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 153{
 154        int i;
 155        void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 156        for (i = 0; i < PM8001_MAX_INB_NUM; i++) {
 157                u32 offset = i * 0x20;
 158                pm8001_ha->inbnd_q_tbl[i].pi_pci_bar =
 159                      get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 160                pm8001_ha->inbnd_q_tbl[i].pi_offset =
 161                        pm8001_mr32(address, (offset + 0x18));
 162        }
 163}
 164
 165/**
 166 * read_outbnd_queue_table - read the outbound queue table and save it.
 167 * @pm8001_ha: our hba card information
 168 */
 169static void read_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha)
 170{
 171        int i;
 172        void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 173        for (i = 0; i < PM8001_MAX_OUTB_NUM; i++) {
 174                u32 offset = i * 0x24;
 175                pm8001_ha->outbnd_q_tbl[i].ci_pci_bar =
 176                      get_pci_bar_index(pm8001_mr32(address, (offset + 0x14)));
 177                pm8001_ha->outbnd_q_tbl[i].ci_offset =
 178                        pm8001_mr32(address, (offset + 0x18));
 179        }
 180}
 181
 182/**
 183 * init_default_table_values - init the default table.
 184 * @pm8001_ha: our hba card information
 185 */
 186static void init_default_table_values(struct pm8001_hba_info *pm8001_ha)
 187{
 188        int i;
 189        u32 offsetib, offsetob;
 190        void __iomem *addressib = pm8001_ha->inbnd_q_tbl_addr;
 191        void __iomem *addressob = pm8001_ha->outbnd_q_tbl_addr;
 192        u32 ib_offset = pm8001_ha->ib_offset;
 193        u32 ob_offset = pm8001_ha->ob_offset;
 194        u32 ci_offset = pm8001_ha->ci_offset;
 195        u32 pi_offset = pm8001_ha->pi_offset;
 196
 197        pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd          = 0;
 198        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3     = 0;
 199        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7     = 0;
 200        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3    = 0;
 201        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7    = 0;
 202        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid0_3 =
 203                                                                         0;
 204        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ITNexus_event_pid4_7 =
 205                                                                         0;
 206        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid0_3 = 0;
 207        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_ssp_event_pid4_7 = 0;
 208        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid0_3 = 0;
 209        pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_tgt_smp_event_pid4_7 = 0;
 210
 211        pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr         =
 212                pm8001_ha->memoryMap.region[AAP1].phys_addr_hi;
 213        pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr         =
 214                pm8001_ha->memoryMap.region[AAP1].phys_addr_lo;
 215        pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size               =
 216                PM8001_EVENT_LOG_SIZE;
 217        pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option             = 0x01;
 218        pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr     =
 219                pm8001_ha->memoryMap.region[IOP].phys_addr_hi;
 220        pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr     =
 221                pm8001_ha->memoryMap.region[IOP].phys_addr_lo;
 222        pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size           =
 223                PM8001_EVENT_LOG_SIZE;
 224        pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option         = 0x01;
 225        pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt          = 0x01;
 226        for (i = 0; i < pm8001_ha->max_q_num; i++) {
 227                pm8001_ha->inbnd_q_tbl[i].element_pri_size_cnt  =
 228                        PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x00<<30);
 229                pm8001_ha->inbnd_q_tbl[i].upper_base_addr       =
 230                        pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_hi;
 231                pm8001_ha->inbnd_q_tbl[i].lower_base_addr       =
 232                pm8001_ha->memoryMap.region[ib_offset + i].phys_addr_lo;
 233                pm8001_ha->inbnd_q_tbl[i].base_virt             =
 234                  (u8 *)pm8001_ha->memoryMap.region[ib_offset + i].virt_ptr;
 235                pm8001_ha->inbnd_q_tbl[i].total_length          =
 236                        pm8001_ha->memoryMap.region[ib_offset + i].total_len;
 237                pm8001_ha->inbnd_q_tbl[i].ci_upper_base_addr    =
 238                        pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_hi;
 239                pm8001_ha->inbnd_q_tbl[i].ci_lower_base_addr    =
 240                        pm8001_ha->memoryMap.region[ci_offset + i].phys_addr_lo;
 241                pm8001_ha->inbnd_q_tbl[i].ci_virt               =
 242                        pm8001_ha->memoryMap.region[ci_offset + i].virt_ptr;
 243                pm8001_write_32(pm8001_ha->inbnd_q_tbl[i].ci_virt, 0, 0);
 244                offsetib = i * 0x20;
 245                pm8001_ha->inbnd_q_tbl[i].pi_pci_bar            =
 246                        get_pci_bar_index(pm8001_mr32(addressib,
 247                                (offsetib + 0x14)));
 248                pm8001_ha->inbnd_q_tbl[i].pi_offset             =
 249                        pm8001_mr32(addressib, (offsetib + 0x18));
 250                pm8001_ha->inbnd_q_tbl[i].producer_idx          = 0;
 251                pm8001_ha->inbnd_q_tbl[i].consumer_index        = 0;
 252        }
 253        for (i = 0; i < pm8001_ha->max_q_num; i++) {
 254                pm8001_ha->outbnd_q_tbl[i].element_size_cnt     =
 255                        PM8001_MPI_QUEUE | (pm8001_ha->iomb_size << 16) | (0x01<<30);
 256                pm8001_ha->outbnd_q_tbl[i].upper_base_addr      =
 257                        pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_hi;
 258                pm8001_ha->outbnd_q_tbl[i].lower_base_addr      =
 259                        pm8001_ha->memoryMap.region[ob_offset + i].phys_addr_lo;
 260                pm8001_ha->outbnd_q_tbl[i].base_virt            =
 261                  (u8 *)pm8001_ha->memoryMap.region[ob_offset + i].virt_ptr;
 262                pm8001_ha->outbnd_q_tbl[i].total_length         =
 263                        pm8001_ha->memoryMap.region[ob_offset + i].total_len;
 264                pm8001_ha->outbnd_q_tbl[i].pi_upper_base_addr   =
 265                        pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_hi;
 266                pm8001_ha->outbnd_q_tbl[i].pi_lower_base_addr   =
 267                        pm8001_ha->memoryMap.region[pi_offset + i].phys_addr_lo;
 268                pm8001_ha->outbnd_q_tbl[i].interrup_vec_cnt_delay       =
 269                        0 | (10 << 16) | (i << 24);
 270                pm8001_ha->outbnd_q_tbl[i].pi_virt              =
 271                        pm8001_ha->memoryMap.region[pi_offset + i].virt_ptr;
 272                pm8001_write_32(pm8001_ha->outbnd_q_tbl[i].pi_virt, 0, 0);
 273                offsetob = i * 0x24;
 274                pm8001_ha->outbnd_q_tbl[i].ci_pci_bar           =
 275                        get_pci_bar_index(pm8001_mr32(addressob,
 276                        offsetob + 0x14));
 277                pm8001_ha->outbnd_q_tbl[i].ci_offset            =
 278                        pm8001_mr32(addressob, (offsetob + 0x18));
 279                pm8001_ha->outbnd_q_tbl[i].consumer_idx         = 0;
 280                pm8001_ha->outbnd_q_tbl[i].producer_index       = 0;
 281        }
 282}
 283
 284/**
 285 * update_main_config_table - update the main default table to the HBA.
 286 * @pm8001_ha: our hba card information
 287 */
 288static void update_main_config_table(struct pm8001_hba_info *pm8001_ha)
 289{
 290        void __iomem *address = pm8001_ha->main_cfg_tbl_addr;
 291        pm8001_mw32(address, 0x24,
 292                pm8001_ha->main_cfg_tbl.pm8001_tbl.inbound_q_nppd_hppd);
 293        pm8001_mw32(address, 0x28,
 294                pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid0_3);
 295        pm8001_mw32(address, 0x2C,
 296                pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_hw_event_pid4_7);
 297        pm8001_mw32(address, 0x30,
 298                pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid0_3);
 299        pm8001_mw32(address, 0x34,
 300                pm8001_ha->main_cfg_tbl.pm8001_tbl.outbound_ncq_event_pid4_7);
 301        pm8001_mw32(address, 0x38,
 302                pm8001_ha->main_cfg_tbl.pm8001_tbl.
 303                                        outbound_tgt_ITNexus_event_pid0_3);
 304        pm8001_mw32(address, 0x3C,
 305                pm8001_ha->main_cfg_tbl.pm8001_tbl.
 306                                        outbound_tgt_ITNexus_event_pid4_7);
 307        pm8001_mw32(address, 0x40,
 308                pm8001_ha->main_cfg_tbl.pm8001_tbl.
 309                                        outbound_tgt_ssp_event_pid0_3);
 310        pm8001_mw32(address, 0x44,
 311                pm8001_ha->main_cfg_tbl.pm8001_tbl.
 312                                        outbound_tgt_ssp_event_pid4_7);
 313        pm8001_mw32(address, 0x48,
 314                pm8001_ha->main_cfg_tbl.pm8001_tbl.
 315                                        outbound_tgt_smp_event_pid0_3);
 316        pm8001_mw32(address, 0x4C,
 317                pm8001_ha->main_cfg_tbl.pm8001_tbl.
 318                                        outbound_tgt_smp_event_pid4_7);
 319        pm8001_mw32(address, 0x50,
 320                pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_event_log_addr);
 321        pm8001_mw32(address, 0x54,
 322                pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_event_log_addr);
 323        pm8001_mw32(address, 0x58,
 324                pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_size);
 325        pm8001_mw32(address, 0x5C,
 326                pm8001_ha->main_cfg_tbl.pm8001_tbl.event_log_option);
 327        pm8001_mw32(address, 0x60,
 328                pm8001_ha->main_cfg_tbl.pm8001_tbl.upper_iop_event_log_addr);
 329        pm8001_mw32(address, 0x64,
 330                pm8001_ha->main_cfg_tbl.pm8001_tbl.lower_iop_event_log_addr);
 331        pm8001_mw32(address, 0x68,
 332                pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_size);
 333        pm8001_mw32(address, 0x6C,
 334                pm8001_ha->main_cfg_tbl.pm8001_tbl.iop_event_log_option);
 335        pm8001_mw32(address, 0x70,
 336                pm8001_ha->main_cfg_tbl.pm8001_tbl.fatal_err_interrupt);
 337}
 338
 339/**
 340 * update_inbnd_queue_table - update the inbound queue table to the HBA.
 341 * @pm8001_ha: our hba card information
 342 * @number: entry in the queue
 343 */
 344static void update_inbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 345                                     int number)
 346{
 347        void __iomem *address = pm8001_ha->inbnd_q_tbl_addr;
 348        u16 offset = number * 0x20;
 349        pm8001_mw32(address, offset + 0x00,
 350                pm8001_ha->inbnd_q_tbl[number].element_pri_size_cnt);
 351        pm8001_mw32(address, offset + 0x04,
 352                pm8001_ha->inbnd_q_tbl[number].upper_base_addr);
 353        pm8001_mw32(address, offset + 0x08,
 354                pm8001_ha->inbnd_q_tbl[number].lower_base_addr);
 355        pm8001_mw32(address, offset + 0x0C,
 356                pm8001_ha->inbnd_q_tbl[number].ci_upper_base_addr);
 357        pm8001_mw32(address, offset + 0x10,
 358                pm8001_ha->inbnd_q_tbl[number].ci_lower_base_addr);
 359}
 360
 361/**
 362 * update_outbnd_queue_table - update the outbound queue table to the HBA.
 363 * @pm8001_ha: our hba card information
 364 * @number: entry in the queue
 365 */
 366static void update_outbnd_queue_table(struct pm8001_hba_info *pm8001_ha,
 367                                      int number)
 368{
 369        void __iomem *address = pm8001_ha->outbnd_q_tbl_addr;
 370        u16 offset = number * 0x24;
 371        pm8001_mw32(address, offset + 0x00,
 372                pm8001_ha->outbnd_q_tbl[number].element_size_cnt);
 373        pm8001_mw32(address, offset + 0x04,
 374                pm8001_ha->outbnd_q_tbl[number].upper_base_addr);
 375        pm8001_mw32(address, offset + 0x08,
 376                pm8001_ha->outbnd_q_tbl[number].lower_base_addr);
 377        pm8001_mw32(address, offset + 0x0C,
 378                pm8001_ha->outbnd_q_tbl[number].pi_upper_base_addr);
 379        pm8001_mw32(address, offset + 0x10,
 380                pm8001_ha->outbnd_q_tbl[number].pi_lower_base_addr);
 381        pm8001_mw32(address, offset + 0x1C,
 382                pm8001_ha->outbnd_q_tbl[number].interrup_vec_cnt_delay);
 383}
 384
 385/**
 386 * pm8001_bar4_shift - function is called to shift BAR base address
 387 * @pm8001_ha : our hba card information
 388 * @shiftValue : shifting value in memory bar.
 389 */
 390int pm8001_bar4_shift(struct pm8001_hba_info *pm8001_ha, u32 shiftValue)
 391{
 392        u32 regVal;
 393        unsigned long start;
 394
 395        /* program the inbound AXI translation Lower Address */
 396        pm8001_cw32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW, shiftValue);
 397
 398        /* confirm the setting is written */
 399        start = jiffies + HZ; /* 1 sec */
 400        do {
 401                regVal = pm8001_cr32(pm8001_ha, 1, SPC_IBW_AXI_TRANSLATION_LOW);
 402        } while ((regVal != shiftValue) && time_before(jiffies, start));
 403
 404        if (regVal != shiftValue) {
 405                pm8001_dbg(pm8001_ha, INIT,
 406                           "TIMEOUT:SPC_IBW_AXI_TRANSLATION_LOW = 0x%x\n",
 407                           regVal);
 408                return -1;
 409        }
 410        return 0;
 411}
 412
 413/**
 414 * mpi_set_phys_g3_with_ssc
 415 * @pm8001_ha: our hba card information
 416 * @SSCbit: set SSCbit to 0 to disable all phys ssc; 1 to enable all phys ssc.
 417 */
 418static void mpi_set_phys_g3_with_ssc(struct pm8001_hba_info *pm8001_ha,
 419                                     u32 SSCbit)
 420{
 421        u32 offset, i;
 422        unsigned long flags;
 423
 424#define SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR 0x00030000
 425#define SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR 0x00040000
 426#define SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET 0x1074
 427#define SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET 0x1074
 428#define PHY_G3_WITHOUT_SSC_BIT_SHIFT 12
 429#define PHY_G3_WITH_SSC_BIT_SHIFT 13
 430#define SNW3_PHY_CAPABILITIES_PARITY 31
 431
 432   /*
 433    * Using shifted destination address 0x3_0000:0x1074 + 0x4000*N (N=0:3)
 434    * Using shifted destination address 0x4_0000:0x1074 + 0x4000*(N-4) (N=4:7)
 435    */
 436        spin_lock_irqsave(&pm8001_ha->lock, flags);
 437        if (-1 == pm8001_bar4_shift(pm8001_ha,
 438                                SAS2_SETTINGS_LOCAL_PHY_0_3_SHIFT_ADDR)) {
 439                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 440                return;
 441        }
 442
 443        for (i = 0; i < 4; i++) {
 444                offset = SAS2_SETTINGS_LOCAL_PHY_0_3_OFFSET + 0x4000 * i;
 445                pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 446        }
 447        /* shift membase 3 for SAS2_SETTINGS_LOCAL_PHY 4 - 7 */
 448        if (-1 == pm8001_bar4_shift(pm8001_ha,
 449                                SAS2_SETTINGS_LOCAL_PHY_4_7_SHIFT_ADDR)) {
 450                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 451                return;
 452        }
 453        for (i = 4; i < 8; i++) {
 454                offset = SAS2_SETTINGS_LOCAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 455                pm8001_cw32(pm8001_ha, 2, offset, 0x80001501);
 456        }
 457        /*************************************************************
 458        Change the SSC upspreading value to 0x0 so that upspreading is disabled.
 459        Device MABC SMOD0 Controls
 460        Address: (via MEMBASE-III):
 461        Using shifted destination address 0x0_0000: with Offset 0xD8
 462
 463        31:28 R/W Reserved Do not change
 464        27:24 R/W SAS_SMOD_SPRDUP 0000
 465        23:20 R/W SAS_SMOD_SPRDDN 0000
 466        19:0  R/W  Reserved Do not change
 467        Upon power-up this register will read as 0x8990c016,
 468        and I would like you to change the SAS_SMOD_SPRDUP bits to 0b0000
 469        so that the written value will be 0x8090c016.
 470        This will ensure only down-spreading SSC is enabled on the SPC.
 471        *************************************************************/
 472        pm8001_cr32(pm8001_ha, 2, 0xd8);
 473        pm8001_cw32(pm8001_ha, 2, 0xd8, 0x8000C016);
 474
 475        /*set the shifted destination address to 0x0 to avoid error operation */
 476        pm8001_bar4_shift(pm8001_ha, 0x0);
 477        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 478        return;
 479}
 480
 481/**
 482 * mpi_set_open_retry_interval_reg
 483 * @pm8001_ha: our hba card information
 484 * @interval: interval time for each OPEN_REJECT (RETRY). The units are in 1us.
 485 */
 486static void mpi_set_open_retry_interval_reg(struct pm8001_hba_info *pm8001_ha,
 487                                            u32 interval)
 488{
 489        u32 offset;
 490        u32 value;
 491        u32 i;
 492        unsigned long flags;
 493
 494#define OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR 0x00030000
 495#define OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR 0x00040000
 496#define OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET 0x30B4
 497#define OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET 0x30B4
 498#define OPEN_RETRY_INTERVAL_REG_MASK 0x0000FFFF
 499
 500        value = interval & OPEN_RETRY_INTERVAL_REG_MASK;
 501        spin_lock_irqsave(&pm8001_ha->lock, flags);
 502        /* shift bar and set the OPEN_REJECT(RETRY) interval time of PHY 0 -3.*/
 503        if (-1 == pm8001_bar4_shift(pm8001_ha,
 504                             OPEN_RETRY_INTERVAL_PHY_0_3_SHIFT_ADDR)) {
 505                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 506                return;
 507        }
 508        for (i = 0; i < 4; i++) {
 509                offset = OPEN_RETRY_INTERVAL_PHY_0_3_OFFSET + 0x4000 * i;
 510                pm8001_cw32(pm8001_ha, 2, offset, value);
 511        }
 512
 513        if (-1 == pm8001_bar4_shift(pm8001_ha,
 514                             OPEN_RETRY_INTERVAL_PHY_4_7_SHIFT_ADDR)) {
 515                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 516                return;
 517        }
 518        for (i = 4; i < 8; i++) {
 519                offset = OPEN_RETRY_INTERVAL_PHY_4_7_OFFSET + 0x4000 * (i-4);
 520                pm8001_cw32(pm8001_ha, 2, offset, value);
 521        }
 522        /*set the shifted destination address to 0x0 to avoid error operation */
 523        pm8001_bar4_shift(pm8001_ha, 0x0);
 524        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 525        return;
 526}
 527
 528/**
 529 * mpi_init_check - check firmware initialization status.
 530 * @pm8001_ha: our hba card information
 531 */
 532static int mpi_init_check(struct pm8001_hba_info *pm8001_ha)
 533{
 534        u32 max_wait_count;
 535        u32 value;
 536        u32 gst_len_mpistate;
 537        /* Write bit0=1 to Inbound DoorBell Register to tell the SPC FW the
 538        table is updated */
 539        pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_UPDATE);
 540        /* wait until Inbound DoorBell Clear Register toggled */
 541        max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 542        do {
 543                udelay(1);
 544                value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 545                value &= SPC_MSGU_CFG_TABLE_UPDATE;
 546        } while ((value != 0) && (--max_wait_count));
 547
 548        if (!max_wait_count)
 549                return -1;
 550        /* check the MPI-State for initialization */
 551        gst_len_mpistate =
 552                pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 553                GST_GSTLEN_MPIS_OFFSET);
 554        if (GST_MPI_STATE_INIT != (gst_len_mpistate & GST_MPI_STATE_MASK))
 555                return -1;
 556        /* check MPI Initialization error */
 557        gst_len_mpistate = gst_len_mpistate >> 16;
 558        if (0x0000 != gst_len_mpistate)
 559                return -1;
 560        return 0;
 561}
 562
 563/**
 564 * check_fw_ready - The LLDD check if the FW is ready, if not, return error.
 565 * @pm8001_ha: our hba card information
 566 */
 567static int check_fw_ready(struct pm8001_hba_info *pm8001_ha)
 568{
 569        u32 value, value1;
 570        u32 max_wait_count;
 571        /* check error state */
 572        value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 573        value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 574        /* check AAP error */
 575        if (SCRATCH_PAD1_ERR == (value & SCRATCH_PAD_STATE_MASK)) {
 576                /* error state */
 577                value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 578                return -1;
 579        }
 580
 581        /* check IOP error */
 582        if (SCRATCH_PAD2_ERR == (value1 & SCRATCH_PAD_STATE_MASK)) {
 583                /* error state */
 584                value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3);
 585                return -1;
 586        }
 587
 588        /* bit 4-31 of scratch pad1 should be zeros if it is not
 589        in error state*/
 590        if (value & SCRATCH_PAD1_STATE_MASK) {
 591                /* error case */
 592                pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0);
 593                return -1;
 594        }
 595
 596        /* bit 2, 4-31 of scratch pad2 should be zeros if it is not
 597        in error state */
 598        if (value1 & SCRATCH_PAD2_STATE_MASK) {
 599                /* error case */
 600                return -1;
 601        }
 602
 603        max_wait_count = 1 * 1000 * 1000;/* 1 sec timeout */
 604
 605        /* wait until scratch pad 1 and 2 registers in ready state  */
 606        do {
 607                udelay(1);
 608                value = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 609                        & SCRATCH_PAD1_RDY;
 610                value1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 611                        & SCRATCH_PAD2_RDY;
 612                if ((--max_wait_count) == 0)
 613                        return -1;
 614        } while ((value != SCRATCH_PAD1_RDY) || (value1 != SCRATCH_PAD2_RDY));
 615        return 0;
 616}
 617
 618static void init_pci_device_addresses(struct pm8001_hba_info *pm8001_ha)
 619{
 620        void __iomem *base_addr;
 621        u32     value;
 622        u32     offset;
 623        u32     pcibar;
 624        u32     pcilogic;
 625
 626        value = pm8001_cr32(pm8001_ha, 0, 0x44);
 627        offset = value & 0x03FFFFFF;
 628        pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 Offset: %x\n", offset);
 629        pcilogic = (value & 0xFC000000) >> 26;
 630        pcibar = get_pci_bar_index(pcilogic);
 631        pm8001_dbg(pm8001_ha, INIT, "Scratchpad 0 PCI BAR: %d\n", pcibar);
 632        pm8001_ha->main_cfg_tbl_addr = base_addr =
 633                pm8001_ha->io_mem[pcibar].memvirtaddr + offset;
 634        pm8001_ha->general_stat_tbl_addr =
 635                base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x18);
 636        pm8001_ha->inbnd_q_tbl_addr =
 637                base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x1C);
 638        pm8001_ha->outbnd_q_tbl_addr =
 639                base_addr + pm8001_cr32(pm8001_ha, pcibar, offset + 0x20);
 640}
 641
 642/**
 643 * pm8001_chip_init - the main init function that initialize whole PM8001 chip.
 644 * @pm8001_ha: our hba card information
 645 */
 646static int pm8001_chip_init(struct pm8001_hba_info *pm8001_ha)
 647{
 648        u32 i = 0;
 649        u16 deviceid;
 650        pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 651        /* 8081 controllers need BAR shift to access MPI space
 652        * as this is shared with BIOS data */
 653        if (deviceid == 0x8081 || deviceid == 0x0042) {
 654                if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 655                        pm8001_dbg(pm8001_ha, FAIL,
 656                                   "Shift Bar4 to 0x%x failed\n",
 657                                   GSM_SM_BASE);
 658                        return -1;
 659                }
 660        }
 661        /* check the firmware status */
 662        if (-1 == check_fw_ready(pm8001_ha)) {
 663                pm8001_dbg(pm8001_ha, FAIL, "Firmware is not ready!\n");
 664                return -EBUSY;
 665        }
 666
 667        /* Initialize pci space address eg: mpi offset */
 668        init_pci_device_addresses(pm8001_ha);
 669        init_default_table_values(pm8001_ha);
 670        read_main_config_table(pm8001_ha);
 671        read_general_status_table(pm8001_ha);
 672        read_inbnd_queue_table(pm8001_ha);
 673        read_outbnd_queue_table(pm8001_ha);
 674        /* update main config table ,inbound table and outbound table */
 675        update_main_config_table(pm8001_ha);
 676        for (i = 0; i < pm8001_ha->max_q_num; i++)
 677                update_inbnd_queue_table(pm8001_ha, i);
 678        for (i = 0; i < pm8001_ha->max_q_num; i++)
 679                update_outbnd_queue_table(pm8001_ha, i);
 680        /* 8081 controller donot require these operations */
 681        if (deviceid != 0x8081 && deviceid != 0x0042) {
 682                mpi_set_phys_g3_with_ssc(pm8001_ha, 0);
 683                /* 7->130ms, 34->500ms, 119->1.5s */
 684                mpi_set_open_retry_interval_reg(pm8001_ha, 119);
 685        }
 686        /* notify firmware update finished and check initialization status */
 687        if (0 == mpi_init_check(pm8001_ha)) {
 688                pm8001_dbg(pm8001_ha, INIT, "MPI initialize successful!\n");
 689        } else
 690                return -EBUSY;
 691        /*This register is a 16-bit timer with a resolution of 1us. This is the
 692        timer used for interrupt delay/coalescing in the PCIe Application Layer.
 693        Zero is not a valid value. A value of 1 in the register will cause the
 694        interrupts to be normal. A value greater than 1 will cause coalescing
 695        delays.*/
 696        pm8001_cw32(pm8001_ha, 1, 0x0033c0, 0x1);
 697        pm8001_cw32(pm8001_ha, 1, 0x0033c4, 0x0);
 698        return 0;
 699}
 700
 701static int mpi_uninit_check(struct pm8001_hba_info *pm8001_ha)
 702{
 703        u32 max_wait_count;
 704        u32 value;
 705        u32 gst_len_mpistate;
 706        u16 deviceid;
 707        pci_read_config_word(pm8001_ha->pdev, PCI_DEVICE_ID, &deviceid);
 708        if (deviceid == 0x8081 || deviceid == 0x0042) {
 709                if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_SM_BASE)) {
 710                        pm8001_dbg(pm8001_ha, FAIL,
 711                                   "Shift Bar4 to 0x%x failed\n",
 712                                   GSM_SM_BASE);
 713                        return -1;
 714                }
 715        }
 716        init_pci_device_addresses(pm8001_ha);
 717        /* Write bit1=1 to Inbound DoorBell Register to tell the SPC FW the
 718        table is stop */
 719        pm8001_cw32(pm8001_ha, 0, MSGU_IBDB_SET, SPC_MSGU_CFG_TABLE_RESET);
 720
 721        /* wait until Inbound DoorBell Clear Register toggled */
 722        max_wait_count = 1 * 1000 * 1000;/* 1 sec */
 723        do {
 724                udelay(1);
 725                value = pm8001_cr32(pm8001_ha, 0, MSGU_IBDB_SET);
 726                value &= SPC_MSGU_CFG_TABLE_RESET;
 727        } while ((value != 0) && (--max_wait_count));
 728
 729        if (!max_wait_count) {
 730                pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:IBDB value/=0x%x\n",
 731                           value);
 732                return -1;
 733        }
 734
 735        /* check the MPI-State for termination in progress */
 736        /* wait until Inbound DoorBell Clear Register toggled */
 737        max_wait_count = 1 * 1000 * 1000;  /* 1 sec */
 738        do {
 739                udelay(1);
 740                gst_len_mpistate =
 741                        pm8001_mr32(pm8001_ha->general_stat_tbl_addr,
 742                        GST_GSTLEN_MPIS_OFFSET);
 743                if (GST_MPI_STATE_UNINIT ==
 744                        (gst_len_mpistate & GST_MPI_STATE_MASK))
 745                        break;
 746        } while (--max_wait_count);
 747        if (!max_wait_count) {
 748                pm8001_dbg(pm8001_ha, FAIL, " TIME OUT MPI State = 0x%x\n",
 749                           gst_len_mpistate & GST_MPI_STATE_MASK);
 750                return -1;
 751        }
 752        return 0;
 753}
 754
 755/**
 756 * soft_reset_ready_check - Function to check FW is ready for soft reset.
 757 * @pm8001_ha: our hba card information
 758 */
 759static u32 soft_reset_ready_check(struct pm8001_hba_info *pm8001_ha)
 760{
 761        u32 regVal, regVal1, regVal2;
 762        if (mpi_uninit_check(pm8001_ha) != 0) {
 763                pm8001_dbg(pm8001_ha, FAIL, "MPI state is not ready\n");
 764                return -1;
 765        }
 766        /* read the scratch pad 2 register bit 2 */
 767        regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2)
 768                & SCRATCH_PAD2_FWRDY_RST;
 769        if (regVal == SCRATCH_PAD2_FWRDY_RST) {
 770                pm8001_dbg(pm8001_ha, INIT, "Firmware is ready for reset.\n");
 771        } else {
 772                unsigned long flags;
 773                /* Trigger NMI twice via RB6 */
 774                spin_lock_irqsave(&pm8001_ha->lock, flags);
 775                if (-1 == pm8001_bar4_shift(pm8001_ha, RB6_ACCESS_REG)) {
 776                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 777                        pm8001_dbg(pm8001_ha, FAIL,
 778                                   "Shift Bar4 to 0x%x failed\n",
 779                                   RB6_ACCESS_REG);
 780                        return -1;
 781                }
 782                pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET,
 783                        RB6_MAGIC_NUMBER_RST);
 784                pm8001_cw32(pm8001_ha, 2, SPC_RB6_OFFSET, RB6_MAGIC_NUMBER_RST);
 785                /* wait for 100 ms */
 786                mdelay(100);
 787                regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2) &
 788                        SCRATCH_PAD2_FWRDY_RST;
 789                if (regVal != SCRATCH_PAD2_FWRDY_RST) {
 790                        regVal1 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
 791                        regVal2 = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
 792                        pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT:MSGU_SCRATCH_PAD1=0x%x, MSGU_SCRATCH_PAD2=0x%x\n",
 793                                   regVal1, regVal2);
 794                        pm8001_dbg(pm8001_ha, FAIL,
 795                                   "SCRATCH_PAD0 value = 0x%x\n",
 796                                   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_0));
 797                        pm8001_dbg(pm8001_ha, FAIL,
 798                                   "SCRATCH_PAD3 value = 0x%x\n",
 799                                   pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_3));
 800                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 801                        return -1;
 802                }
 803                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 804        }
 805        return 0;
 806}
 807
 808/**
 809 * pm8001_chip_soft_rst - soft reset the PM8001 chip, so that the clear all
 810 * the FW register status to the originated status.
 811 * @pm8001_ha: our hba card information
 812 */
 813static int
 814pm8001_chip_soft_rst(struct pm8001_hba_info *pm8001_ha)
 815{
 816        u32     regVal, toggleVal;
 817        u32     max_wait_count;
 818        u32     regVal1, regVal2, regVal3;
 819        u32     signature = 0x252acbcd; /* for host scratch pad0 */
 820        unsigned long flags;
 821
 822        /* step1: Check FW is ready for soft reset */
 823        if (soft_reset_ready_check(pm8001_ha) != 0) {
 824                pm8001_dbg(pm8001_ha, FAIL, "FW is not ready\n");
 825                return -1;
 826        }
 827
 828        /* step 2: clear NMI status register on AAP1 and IOP, write the same
 829        value to clear */
 830        /* map 0x60000 to BAR4(0x20), BAR2(win) */
 831        spin_lock_irqsave(&pm8001_ha->lock, flags);
 832        if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_AAP1_ADDR_BASE)) {
 833                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 834                pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 835                           MBIC_AAP1_ADDR_BASE);
 836                return -1;
 837        }
 838        regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP);
 839        pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (IOP)= 0x%x\n",
 840                   regVal);
 841        pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_IOP, 0x0);
 842        /* map 0x70000 to BAR4(0x20), BAR2(win) */
 843        if (-1 == pm8001_bar4_shift(pm8001_ha, MBIC_IOP_ADDR_BASE)) {
 844                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 845                pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 846                           MBIC_IOP_ADDR_BASE);
 847                return -1;
 848        }
 849        regVal = pm8001_cr32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1);
 850        pm8001_dbg(pm8001_ha, INIT, "MBIC - NMI Enable VPE0 (AAP1)= 0x%x\n",
 851                   regVal);
 852        pm8001_cw32(pm8001_ha, 2, MBIC_NMI_ENABLE_VPE0_AAP1, 0x0);
 853
 854        regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE);
 855        pm8001_dbg(pm8001_ha, INIT, "PCIE -Event Interrupt Enable = 0x%x\n",
 856                   regVal);
 857        pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT_ENABLE, 0x0);
 858
 859        regVal = pm8001_cr32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT);
 860        pm8001_dbg(pm8001_ha, INIT, "PCIE - Event Interrupt  = 0x%x\n",
 861                   regVal);
 862        pm8001_cw32(pm8001_ha, 1, PCIE_EVENT_INTERRUPT, regVal);
 863
 864        regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE);
 865        pm8001_dbg(pm8001_ha, INIT, "PCIE -Error Interrupt Enable = 0x%x\n",
 866                   regVal);
 867        pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT_ENABLE, 0x0);
 868
 869        regVal = pm8001_cr32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT);
 870        pm8001_dbg(pm8001_ha, INIT, "PCIE - Error Interrupt = 0x%x\n", regVal);
 871        pm8001_cw32(pm8001_ha, 1, PCIE_ERROR_INTERRUPT, regVal);
 872
 873        /* read the scratch pad 1 register bit 2 */
 874        regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1)
 875                & SCRATCH_PAD1_RST;
 876        toggleVal = regVal ^ SCRATCH_PAD1_RST;
 877
 878        /* set signature in host scratch pad0 register to tell SPC that the
 879        host performs the soft reset */
 880        pm8001_cw32(pm8001_ha, 0, MSGU_HOST_SCRATCH_PAD_0, signature);
 881
 882        /* read required registers for confirmming */
 883        /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 884        if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 885                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 886                pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
 887                           GSM_ADDR_BASE);
 888                return -1;
 889        }
 890        pm8001_dbg(pm8001_ha, INIT,
 891                   "GSM 0x0(0x00007b88)-GSM Configuration and Reset = 0x%x\n",
 892                   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
 893
 894        /* step 3: host read GSM Configuration and Reset register */
 895        regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
 896        /* Put those bits to low */
 897        /* GSM XCBI offset = 0x70 0000
 898        0x00 Bit 13 COM_SLV_SW_RSTB 1
 899        0x00 Bit 12 QSSP_SW_RSTB 1
 900        0x00 Bit 11 RAAE_SW_RSTB 1
 901        0x00 Bit 9 RB_1_SW_RSTB 1
 902        0x00 Bit 8 SM_SW_RSTB 1
 903        */
 904        regVal &= ~(0x00003b00);
 905        /* host write GSM Configuration and Reset register */
 906        pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
 907        pm8001_dbg(pm8001_ha, INIT,
 908                   "GSM 0x0 (0x00007b88 ==> 0x00004088) - GSM Configuration and Reset is set to = 0x%x\n",
 909                   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
 910
 911        /* step 4: */
 912        /* disable GSM - Read Address Parity Check */
 913        regVal1 = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
 914        pm8001_dbg(pm8001_ha, INIT,
 915                   "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
 916                   regVal1);
 917        pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, 0x0);
 918        pm8001_dbg(pm8001_ha, INIT,
 919                   "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
 920                   pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
 921
 922        /* disable GSM - Write Address Parity Check */
 923        regVal2 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
 924        pm8001_dbg(pm8001_ha, INIT,
 925                   "GSM 0x700040 - Write Address Parity Check Enable = 0x%x\n",
 926                   regVal2);
 927        pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, 0x0);
 928        pm8001_dbg(pm8001_ha, INIT,
 929                   "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
 930                   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
 931
 932        /* disable GSM - Write Data Parity Check */
 933        regVal3 = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
 934        pm8001_dbg(pm8001_ha, INIT, "GSM 0x300048 - Write Data Parity Check Enable = 0x%x\n",
 935                   regVal3);
 936        pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, 0x0);
 937        pm8001_dbg(pm8001_ha, INIT,
 938                   "GSM 0x300048 - Write Data Parity Check Enable is set to = 0x%x\n",
 939                   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
 940
 941        /* step 5: delay 10 usec */
 942        udelay(10);
 943        /* step 5-b: set GPIO-0 output control to tristate anyway */
 944        if (-1 == pm8001_bar4_shift(pm8001_ha, GPIO_ADDR_BASE)) {
 945                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 946                pm8001_dbg(pm8001_ha, INIT, "Shift Bar4 to 0x%x failed\n",
 947                           GPIO_ADDR_BASE);
 948                return -1;
 949        }
 950        regVal = pm8001_cr32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET);
 951        pm8001_dbg(pm8001_ha, INIT, "GPIO Output Control Register: = 0x%x\n",
 952                   regVal);
 953        /* set GPIO-0 output control to tri-state */
 954        regVal &= 0xFFFFFFFC;
 955        pm8001_cw32(pm8001_ha, 2, GPIO_GPIO_0_0UTPUT_CTL_OFFSET, regVal);
 956
 957        /* Step 6: Reset the IOP and AAP1 */
 958        /* map 0x00000 to BAR4(0x20), BAR2(win) */
 959        if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
 960                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 961                pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
 962                           SPC_TOP_LEVEL_ADDR_BASE);
 963                return -1;
 964        }
 965        regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 966        pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting IOP/AAP1:= 0x%x\n",
 967                   regVal);
 968        regVal &= ~(SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
 969        pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 970
 971        /* step 7: Reset the BDMA/OSSP */
 972        regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 973        pm8001_dbg(pm8001_ha, INIT, "Top Register before resetting BDMA/OSSP: = 0x%x\n",
 974                   regVal);
 975        regVal &= ~(SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 976        pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 977
 978        /* step 8: delay 10 usec */
 979        udelay(10);
 980
 981        /* step 9: bring the BDMA and OSSP out of reset */
 982        regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
 983        pm8001_dbg(pm8001_ha, INIT,
 984                   "Top Register before bringing up BDMA/OSSP:= 0x%x\n",
 985                   regVal);
 986        regVal |= (SPC_REG_RESET_BDMA_CORE | SPC_REG_RESET_OSSP);
 987        pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
 988
 989        /* step 10: delay 10 usec */
 990        udelay(10);
 991
 992        /* step 11: reads and sets the GSM Configuration and Reset Register */
 993        /* map 0x0700000 to BAR4(0x20), BAR2(win) */
 994        if (-1 == pm8001_bar4_shift(pm8001_ha, GSM_ADDR_BASE)) {
 995                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
 996                pm8001_dbg(pm8001_ha, FAIL, "SPC Shift Bar4 to 0x%x failed\n",
 997                           GSM_ADDR_BASE);
 998                return -1;
 999        }
1000        pm8001_dbg(pm8001_ha, INIT,
1001                   "GSM 0x0 (0x00007b88)-GSM Configuration and Reset = 0x%x\n",
1002                   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1003        regVal = pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET);
1004        /* Put those bits to high */
1005        /* GSM XCBI offset = 0x70 0000
1006        0x00 Bit 13 COM_SLV_SW_RSTB 1
1007        0x00 Bit 12 QSSP_SW_RSTB 1
1008        0x00 Bit 11 RAAE_SW_RSTB 1
1009        0x00 Bit 9   RB_1_SW_RSTB 1
1010        0x00 Bit 8   SM_SW_RSTB 1
1011        */
1012        regVal |= (GSM_CONFIG_RESET_VALUE);
1013        pm8001_cw32(pm8001_ha, 2, GSM_CONFIG_RESET, regVal);
1014        pm8001_dbg(pm8001_ha, INIT, "GSM (0x00004088 ==> 0x00007b88) - GSM Configuration and Reset is set to = 0x%x\n",
1015                   pm8001_cr32(pm8001_ha, 2, GSM_CONFIG_RESET));
1016
1017        /* step 12: Restore GSM - Read Address Parity Check */
1018        regVal = pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK);
1019        /* just for debugging */
1020        pm8001_dbg(pm8001_ha, INIT,
1021                   "GSM 0x700038 - Read Address Parity Check Enable = 0x%x\n",
1022                   regVal);
1023        pm8001_cw32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK, regVal1);
1024        pm8001_dbg(pm8001_ha, INIT, "GSM 0x700038 - Read Address Parity Check Enable is set to = 0x%x\n",
1025                   pm8001_cr32(pm8001_ha, 2, GSM_READ_ADDR_PARITY_CHECK));
1026        /* Restore GSM - Write Address Parity Check */
1027        regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK);
1028        pm8001_cw32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK, regVal2);
1029        pm8001_dbg(pm8001_ha, INIT,
1030                   "GSM 0x700040 - Write Address Parity Check Enable is set to = 0x%x\n",
1031                   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_ADDR_PARITY_CHECK));
1032        /* Restore GSM - Write Data Parity Check */
1033        regVal = pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK);
1034        pm8001_cw32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK, regVal3);
1035        pm8001_dbg(pm8001_ha, INIT,
1036                   "GSM 0x700048 - Write Data Parity Check Enable is set to = 0x%x\n",
1037                   pm8001_cr32(pm8001_ha, 2, GSM_WRITE_DATA_PARITY_CHECK));
1038
1039        /* step 13: bring the IOP and AAP1 out of reset */
1040        /* map 0x00000 to BAR4(0x20), BAR2(win) */
1041        if (-1 == pm8001_bar4_shift(pm8001_ha, SPC_TOP_LEVEL_ADDR_BASE)) {
1042                spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1043                pm8001_dbg(pm8001_ha, FAIL, "Shift Bar4 to 0x%x failed\n",
1044                           SPC_TOP_LEVEL_ADDR_BASE);
1045                return -1;
1046        }
1047        regVal = pm8001_cr32(pm8001_ha, 2, SPC_REG_RESET);
1048        regVal |= (SPC_REG_RESET_PCS_IOP_SS | SPC_REG_RESET_PCS_AAP1_SS);
1049        pm8001_cw32(pm8001_ha, 2, SPC_REG_RESET, regVal);
1050
1051        /* step 14: delay 10 usec - Normal Mode */
1052        udelay(10);
1053        /* check Soft Reset Normal mode or Soft Reset HDA mode */
1054        if (signature == SPC_SOFT_RESET_SIGNATURE) {
1055                /* step 15 (Normal Mode): wait until scratch pad1 register
1056                bit 2 toggled */
1057                max_wait_count = 2 * 1000 * 1000;/* 2 sec */
1058                do {
1059                        udelay(1);
1060                        regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1) &
1061                                SCRATCH_PAD1_RST;
1062                } while ((regVal != toggleVal) && (--max_wait_count));
1063
1064                if (!max_wait_count) {
1065                        regVal = pm8001_cr32(pm8001_ha, 0,
1066                                MSGU_SCRATCH_PAD_1);
1067                        pm8001_dbg(pm8001_ha, FAIL, "TIMEOUT : ToggleVal 0x%x,MSGU_SCRATCH_PAD1 = 0x%x\n",
1068                                   toggleVal, regVal);
1069                        pm8001_dbg(pm8001_ha, FAIL,
1070                                   "SCRATCH_PAD0 value = 0x%x\n",
1071                                   pm8001_cr32(pm8001_ha, 0,
1072                                               MSGU_SCRATCH_PAD_0));
1073                        pm8001_dbg(pm8001_ha, FAIL,
1074                                   "SCRATCH_PAD2 value = 0x%x\n",
1075                                   pm8001_cr32(pm8001_ha, 0,
1076                                               MSGU_SCRATCH_PAD_2));
1077                        pm8001_dbg(pm8001_ha, FAIL,
1078                                   "SCRATCH_PAD3 value = 0x%x\n",
1079                                   pm8001_cr32(pm8001_ha, 0,
1080                                               MSGU_SCRATCH_PAD_3));
1081                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1082                        return -1;
1083                }
1084
1085                /* step 16 (Normal) - Clear ODMR and ODCR */
1086                pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1087                pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1088
1089                /* step 17 (Normal Mode): wait for the FW and IOP to get
1090                ready - 1 sec timeout */
1091                /* Wait for the SPC Configuration Table to be ready */
1092                if (check_fw_ready(pm8001_ha) == -1) {
1093                        regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_1);
1094                        /* return error if MPI Configuration Table not ready */
1095                        pm8001_dbg(pm8001_ha, INIT,
1096                                   "FW not ready SCRATCH_PAD1 = 0x%x\n",
1097                                   regVal);
1098                        regVal = pm8001_cr32(pm8001_ha, 0, MSGU_SCRATCH_PAD_2);
1099                        /* return error if MPI Configuration Table not ready */
1100                        pm8001_dbg(pm8001_ha, INIT,
1101                                   "FW not ready SCRATCH_PAD2 = 0x%x\n",
1102                                   regVal);
1103                        pm8001_dbg(pm8001_ha, INIT,
1104                                   "SCRATCH_PAD0 value = 0x%x\n",
1105                                   pm8001_cr32(pm8001_ha, 0,
1106                                               MSGU_SCRATCH_PAD_0));
1107                        pm8001_dbg(pm8001_ha, INIT,
1108                                   "SCRATCH_PAD3 value = 0x%x\n",
1109                                   pm8001_cr32(pm8001_ha, 0,
1110                                               MSGU_SCRATCH_PAD_3));
1111                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1112                        return -1;
1113                }
1114        }
1115        pm8001_bar4_shift(pm8001_ha, 0);
1116        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1117
1118        pm8001_dbg(pm8001_ha, INIT, "SPC soft reset Complete\n");
1119        return 0;
1120}
1121
1122static void pm8001_hw_chip_rst(struct pm8001_hba_info *pm8001_ha)
1123{
1124        u32 i;
1125        u32 regVal;
1126        pm8001_dbg(pm8001_ha, INIT, "chip reset start\n");
1127
1128        /* do SPC chip reset. */
1129        regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1130        regVal &= ~(SPC_REG_RESET_DEVICE);
1131        pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1132
1133        /* delay 10 usec */
1134        udelay(10);
1135
1136        /* bring chip reset out of reset */
1137        regVal = pm8001_cr32(pm8001_ha, 1, SPC_REG_RESET);
1138        regVal |= SPC_REG_RESET_DEVICE;
1139        pm8001_cw32(pm8001_ha, 1, SPC_REG_RESET, regVal);
1140
1141        /* delay 10 usec */
1142        udelay(10);
1143
1144        /* wait for 20 msec until the firmware gets reloaded */
1145        i = 20;
1146        do {
1147                mdelay(1);
1148        } while ((--i) != 0);
1149
1150        pm8001_dbg(pm8001_ha, INIT, "chip reset finished\n");
1151}
1152
1153/**
1154 * pm8001_chip_iounmap - which mapped when initialized.
1155 * @pm8001_ha: our hba card information
1156 */
1157void pm8001_chip_iounmap(struct pm8001_hba_info *pm8001_ha)
1158{
1159        s8 bar, logical = 0;
1160        for (bar = 0; bar < PCI_STD_NUM_BARS; bar++) {
1161                /*
1162                ** logical BARs for SPC:
1163                ** bar 0 and 1 - logical BAR0
1164                ** bar 2 and 3 - logical BAR1
1165                ** bar4 - logical BAR2
1166                ** bar5 - logical BAR3
1167                ** Skip the appropriate assignments:
1168                */
1169                if ((bar == 1) || (bar == 3))
1170                        continue;
1171                if (pm8001_ha->io_mem[logical].memvirtaddr) {
1172                        iounmap(pm8001_ha->io_mem[logical].memvirtaddr);
1173                        logical++;
1174                }
1175        }
1176}
1177
1178#ifndef PM8001_USE_MSIX
1179/**
1180 * pm8001_chip_intx_interrupt_enable - enable PM8001 chip interrupt
1181 * @pm8001_ha: our hba card information
1182 */
1183static void
1184pm8001_chip_intx_interrupt_enable(struct pm8001_hba_info *pm8001_ha)
1185{
1186        pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_CLEAR_ALL);
1187        pm8001_cw32(pm8001_ha, 0, MSGU_ODCR, ODCR_CLEAR_ALL);
1188}
1189
1190/**
1191 * pm8001_chip_intx_interrupt_disable - disable PM8001 chip interrupt
1192 * @pm8001_ha: our hba card information
1193 */
1194static void
1195pm8001_chip_intx_interrupt_disable(struct pm8001_hba_info *pm8001_ha)
1196{
1197        pm8001_cw32(pm8001_ha, 0, MSGU_ODMR, ODMR_MASK_ALL);
1198}
1199
1200#else
1201
1202/**
1203 * pm8001_chip_msix_interrupt_enable - enable PM8001 chip interrupt
1204 * @pm8001_ha: our hba card information
1205 * @int_vec_idx: interrupt number to enable
1206 */
1207static void
1208pm8001_chip_msix_interrupt_enable(struct pm8001_hba_info *pm8001_ha,
1209        u32 int_vec_idx)
1210{
1211        u32 msi_index;
1212        u32 value;
1213        msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1214        msi_index += MSIX_TABLE_BASE;
1215        pm8001_cw32(pm8001_ha, 0, msi_index, MSIX_INTERRUPT_ENABLE);
1216        value = (1 << int_vec_idx);
1217        pm8001_cw32(pm8001_ha, 0,  MSGU_ODCR, value);
1218
1219}
1220
1221/**
1222 * pm8001_chip_msix_interrupt_disable - disable PM8001 chip interrupt
1223 * @pm8001_ha: our hba card information
1224 * @int_vec_idx: interrupt number to disable
1225 */
1226static void
1227pm8001_chip_msix_interrupt_disable(struct pm8001_hba_info *pm8001_ha,
1228        u32 int_vec_idx)
1229{
1230        u32 msi_index;
1231        msi_index = int_vec_idx * MSIX_TABLE_ELEMENT_SIZE;
1232        msi_index += MSIX_TABLE_BASE;
1233        pm8001_cw32(pm8001_ha, 0,  msi_index, MSIX_INTERRUPT_DISABLE);
1234}
1235#endif
1236
1237/**
1238 * pm8001_chip_interrupt_enable - enable PM8001 chip interrupt
1239 * @pm8001_ha: our hba card information
1240 * @vec: unused
1241 */
1242static void
1243pm8001_chip_interrupt_enable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1244{
1245#ifdef PM8001_USE_MSIX
1246        pm8001_chip_msix_interrupt_enable(pm8001_ha, 0);
1247#else
1248        pm8001_chip_intx_interrupt_enable(pm8001_ha);
1249#endif
1250}
1251
1252/**
1253 * pm8001_chip_interrupt_disable - disable PM8001 chip interrupt
1254 * @pm8001_ha: our hba card information
1255 * @vec: unused
1256 */
1257static void
1258pm8001_chip_interrupt_disable(struct pm8001_hba_info *pm8001_ha, u8 vec)
1259{
1260#ifdef PM8001_USE_MSIX
1261        pm8001_chip_msix_interrupt_disable(pm8001_ha, 0);
1262#else
1263        pm8001_chip_intx_interrupt_disable(pm8001_ha);
1264#endif
1265}
1266
1267/**
1268 * pm8001_mpi_msg_free_get - get the free message buffer for transfer
1269 * inbound queue.
1270 * @circularQ: the inbound queue  we want to transfer to HBA.
1271 * @messageSize: the message size of this transfer, normally it is 64 bytes
1272 * @messagePtr: the pointer to message.
1273 */
1274int pm8001_mpi_msg_free_get(struct inbound_queue_table *circularQ,
1275                            u16 messageSize, void **messagePtr)
1276{
1277        u32 offset, consumer_index;
1278        struct mpi_msg_hdr *msgHeader;
1279        u8 bcCount = 1; /* only support single buffer */
1280
1281        /* Checks is the requested message size can be allocated in this queue*/
1282        if (messageSize > IOMB_SIZE_SPCV) {
1283                *messagePtr = NULL;
1284                return -1;
1285        }
1286
1287        /* Stores the new consumer index */
1288        consumer_index = pm8001_read_32(circularQ->ci_virt);
1289        circularQ->consumer_index = cpu_to_le32(consumer_index);
1290        if (((circularQ->producer_idx + bcCount) % PM8001_MPI_QUEUE) ==
1291                le32_to_cpu(circularQ->consumer_index)) {
1292                *messagePtr = NULL;
1293                return -1;
1294        }
1295        /* get memory IOMB buffer address */
1296        offset = circularQ->producer_idx * messageSize;
1297        /* increment to next bcCount element */
1298        circularQ->producer_idx = (circularQ->producer_idx + bcCount)
1299                                % PM8001_MPI_QUEUE;
1300        /* Adds that distance to the base of the region virtual address plus
1301        the message header size*/
1302        msgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt + offset);
1303        *messagePtr = ((void *)msgHeader) + sizeof(struct mpi_msg_hdr);
1304        return 0;
1305}
1306
1307/**
1308 * pm8001_mpi_build_cmd- build the message queue for transfer, update the PI to
1309 * FW to tell the fw to get this message from IOMB.
1310 * @pm8001_ha: our hba card information
1311 * @circularQ: the inbound queue we want to transfer to HBA.
1312 * @opCode: the operation code represents commands which LLDD and fw recognized.
1313 * @payload: the command payload of each operation command.
1314 * @nb: size in bytes of the command payload
1315 * @responseQueue: queue to interrupt on w/ command response (if any)
1316 */
1317int pm8001_mpi_build_cmd(struct pm8001_hba_info *pm8001_ha,
1318                         struct inbound_queue_table *circularQ,
1319                         u32 opCode, void *payload, size_t nb,
1320                         u32 responseQueue)
1321{
1322        u32 Header = 0, hpriority = 0, bc = 1, category = 0x02;
1323        void *pMessage;
1324        unsigned long flags;
1325        int q_index = circularQ - pm8001_ha->inbnd_q_tbl;
1326        int rv = -1;
1327
1328        WARN_ON(q_index >= PM8001_MAX_INB_NUM);
1329        spin_lock_irqsave(&circularQ->iq_lock, flags);
1330        rv = pm8001_mpi_msg_free_get(circularQ, pm8001_ha->iomb_size,
1331                        &pMessage);
1332        if (rv < 0) {
1333                pm8001_dbg(pm8001_ha, IO, "No free mpi buffer\n");
1334                rv = -ENOMEM;
1335                goto done;
1336        }
1337
1338        if (nb > (pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr)))
1339                nb = pm8001_ha->iomb_size - sizeof(struct mpi_msg_hdr);
1340        memcpy(pMessage, payload, nb);
1341        if (nb + sizeof(struct mpi_msg_hdr) < pm8001_ha->iomb_size)
1342                memset(pMessage + nb, 0, pm8001_ha->iomb_size -
1343                                (nb + sizeof(struct mpi_msg_hdr)));
1344
1345        /*Build the header*/
1346        Header = ((1 << 31) | (hpriority << 30) | ((bc & 0x1f) << 24)
1347                | ((responseQueue & 0x3F) << 16)
1348                | ((category & 0xF) << 12) | (opCode & 0xFFF));
1349
1350        pm8001_write_32((pMessage - 4), 0, cpu_to_le32(Header));
1351        /*Update the PI to the firmware*/
1352        pm8001_cw32(pm8001_ha, circularQ->pi_pci_bar,
1353                circularQ->pi_offset, circularQ->producer_idx);
1354        pm8001_dbg(pm8001_ha, DEVIO,
1355                   "INB Q %x OPCODE:%x , UPDATED PI=%d CI=%d\n",
1356                   responseQueue, opCode, circularQ->producer_idx,
1357                   circularQ->consumer_index);
1358done:
1359        spin_unlock_irqrestore(&circularQ->iq_lock, flags);
1360        return rv;
1361}
1362
1363u32 pm8001_mpi_msg_free_set(struct pm8001_hba_info *pm8001_ha, void *pMsg,
1364                            struct outbound_queue_table *circularQ, u8 bc)
1365{
1366        u32 producer_index;
1367        struct mpi_msg_hdr *msgHeader;
1368        struct mpi_msg_hdr *pOutBoundMsgHeader;
1369
1370        msgHeader = (struct mpi_msg_hdr *)(pMsg - sizeof(struct mpi_msg_hdr));
1371        pOutBoundMsgHeader = (struct mpi_msg_hdr *)(circularQ->base_virt +
1372                                circularQ->consumer_idx * pm8001_ha->iomb_size);
1373        if (pOutBoundMsgHeader != msgHeader) {
1374                pm8001_dbg(pm8001_ha, FAIL,
1375                           "consumer_idx = %d msgHeader = %p\n",
1376                           circularQ->consumer_idx, msgHeader);
1377
1378                /* Update the producer index from SPC */
1379                producer_index = pm8001_read_32(circularQ->pi_virt);
1380                circularQ->producer_index = cpu_to_le32(producer_index);
1381                pm8001_dbg(pm8001_ha, FAIL,
1382                           "consumer_idx = %d producer_index = %dmsgHeader = %p\n",
1383                           circularQ->consumer_idx,
1384                           circularQ->producer_index, msgHeader);
1385                return 0;
1386        }
1387        /* free the circular queue buffer elements associated with the message*/
1388        circularQ->consumer_idx = (circularQ->consumer_idx + bc)
1389                                % PM8001_MPI_QUEUE;
1390        /* update the CI of outbound queue */
1391        pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar, circularQ->ci_offset,
1392                circularQ->consumer_idx);
1393        /* Update the producer index from SPC*/
1394        producer_index = pm8001_read_32(circularQ->pi_virt);
1395        circularQ->producer_index = cpu_to_le32(producer_index);
1396        pm8001_dbg(pm8001_ha, IO, " CI=%d PI=%d\n",
1397                   circularQ->consumer_idx, circularQ->producer_index);
1398        return 0;
1399}
1400
1401/**
1402 * pm8001_mpi_msg_consume- get the MPI message from outbound queue
1403 * message table.
1404 * @pm8001_ha: our hba card information
1405 * @circularQ: the outbound queue  table.
1406 * @messagePtr1: the message contents of this outbound message.
1407 * @pBC: the message size.
1408 */
1409u32 pm8001_mpi_msg_consume(struct pm8001_hba_info *pm8001_ha,
1410                           struct outbound_queue_table *circularQ,
1411                           void **messagePtr1, u8 *pBC)
1412{
1413        struct mpi_msg_hdr      *msgHeader;
1414        __le32  msgHeader_tmp;
1415        u32 header_tmp;
1416        do {
1417                /* If there are not-yet-delivered messages ... */
1418                if (le32_to_cpu(circularQ->producer_index)
1419                        != circularQ->consumer_idx) {
1420                        /*Get the pointer to the circular queue buffer element*/
1421                        msgHeader = (struct mpi_msg_hdr *)
1422                                (circularQ->base_virt +
1423                                circularQ->consumer_idx * pm8001_ha->iomb_size);
1424                        /* read header */
1425                        header_tmp = pm8001_read_32(msgHeader);
1426                        msgHeader_tmp = cpu_to_le32(header_tmp);
1427                        pm8001_dbg(pm8001_ha, DEVIO,
1428                                   "outbound opcode msgheader:%x ci=%d pi=%d\n",
1429                                   msgHeader_tmp, circularQ->consumer_idx,
1430                                   circularQ->producer_index);
1431                        if (0 != (le32_to_cpu(msgHeader_tmp) & 0x80000000)) {
1432                                if (OPC_OUB_SKIP_ENTRY !=
1433                                        (le32_to_cpu(msgHeader_tmp) & 0xfff)) {
1434                                        *messagePtr1 =
1435                                                ((u8 *)msgHeader) +
1436                                                sizeof(struct mpi_msg_hdr);
1437                                        *pBC = (u8)((le32_to_cpu(msgHeader_tmp)
1438                                                >> 24) & 0x1f);
1439                                        pm8001_dbg(pm8001_ha, IO,
1440                                                   ": CI=%d PI=%d msgHeader=%x\n",
1441                                                   circularQ->consumer_idx,
1442                                                   circularQ->producer_index,
1443                                                   msgHeader_tmp);
1444                                        return MPI_IO_STATUS_SUCCESS;
1445                                } else {
1446                                        circularQ->consumer_idx =
1447                                                (circularQ->consumer_idx +
1448                                                ((le32_to_cpu(msgHeader_tmp)
1449                                                 >> 24) & 0x1f))
1450                                                        % PM8001_MPI_QUEUE;
1451                                        msgHeader_tmp = 0;
1452                                        pm8001_write_32(msgHeader, 0, 0);
1453                                        /* update the CI of outbound queue */
1454                                        pm8001_cw32(pm8001_ha,
1455                                                circularQ->ci_pci_bar,
1456                                                circularQ->ci_offset,
1457                                                circularQ->consumer_idx);
1458                                }
1459                        } else {
1460                                circularQ->consumer_idx =
1461                                        (circularQ->consumer_idx +
1462                                        ((le32_to_cpu(msgHeader_tmp) >> 24) &
1463                                        0x1f)) % PM8001_MPI_QUEUE;
1464                                msgHeader_tmp = 0;
1465                                pm8001_write_32(msgHeader, 0, 0);
1466                                /* update the CI of outbound queue */
1467                                pm8001_cw32(pm8001_ha, circularQ->ci_pci_bar,
1468                                        circularQ->ci_offset,
1469                                        circularQ->consumer_idx);
1470                                return MPI_IO_STATUS_FAIL;
1471                        }
1472                } else {
1473                        u32 producer_index;
1474                        void *pi_virt = circularQ->pi_virt;
1475                        /* spurious interrupt during setup if
1476                         * kexec-ing and driver doing a doorbell access
1477                         * with the pre-kexec oq interrupt setup
1478                         */
1479                        if (!pi_virt)
1480                                break;
1481                        /* Update the producer index from SPC */
1482                        producer_index = pm8001_read_32(pi_virt);
1483                        circularQ->producer_index = cpu_to_le32(producer_index);
1484                }
1485        } while (le32_to_cpu(circularQ->producer_index) !=
1486                circularQ->consumer_idx);
1487        /* while we don't have any more not-yet-delivered message */
1488        /* report empty */
1489        return MPI_IO_STATUS_BUSY;
1490}
1491
1492void pm8001_work_fn(struct work_struct *work)
1493{
1494        struct pm8001_work *pw = container_of(work, struct pm8001_work, work);
1495        struct pm8001_device *pm8001_dev;
1496        struct domain_device *dev;
1497
1498        /*
1499         * So far, all users of this stash an associated structure here.
1500         * If we get here, and this pointer is null, then the action
1501         * was cancelled. This nullification happens when the device
1502         * goes away.
1503         */
1504        if (pw->handler != IO_FATAL_ERROR) {
1505                pm8001_dev = pw->data; /* Most stash device structure */
1506                if ((pm8001_dev == NULL)
1507                 || ((pw->handler != IO_XFER_ERROR_BREAK)
1508                         && (pm8001_dev->dev_type == SAS_PHY_UNUSED))) {
1509                        kfree(pw);
1510                        return;
1511                }
1512        }
1513
1514        switch (pw->handler) {
1515        case IO_XFER_ERROR_BREAK:
1516        {       /* This one stashes the sas_task instead */
1517                struct sas_task *t = (struct sas_task *)pm8001_dev;
1518                u32 tag;
1519                struct pm8001_ccb_info *ccb;
1520                struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1521                unsigned long flags, flags1;
1522                struct task_status_struct *ts;
1523                int i;
1524
1525                if (pm8001_query_task(t) == TMF_RESP_FUNC_SUCC)
1526                        break; /* Task still on lu */
1527                spin_lock_irqsave(&pm8001_ha->lock, flags);
1528
1529                spin_lock_irqsave(&t->task_state_lock, flags1);
1530                if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1531                        spin_unlock_irqrestore(&t->task_state_lock, flags1);
1532                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1533                        break; /* Task got completed by another */
1534                }
1535                spin_unlock_irqrestore(&t->task_state_lock, flags1);
1536
1537                /* Search for a possible ccb that matches the task */
1538                for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1539                        ccb = &pm8001_ha->ccb_info[i];
1540                        tag = ccb->ccb_tag;
1541                        if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1542                                break;
1543                }
1544                if (!ccb) {
1545                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1546                        break; /* Task got freed by another */
1547                }
1548                ts = &t->task_status;
1549                ts->resp = SAS_TASK_COMPLETE;
1550                /* Force the midlayer to retry */
1551                ts->stat = SAS_QUEUE_FULL;
1552                pm8001_dev = ccb->device;
1553                if (pm8001_dev)
1554                        atomic_dec(&pm8001_dev->running_req);
1555                spin_lock_irqsave(&t->task_state_lock, flags1);
1556                t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
1557                t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
1558                t->task_state_flags |= SAS_TASK_STATE_DONE;
1559                if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
1560                        spin_unlock_irqrestore(&t->task_state_lock, flags1);
1561                        pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
1562                                   t, pw->handler, ts->resp, ts->stat);
1563                        pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1564                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1565                } else {
1566                        spin_unlock_irqrestore(&t->task_state_lock, flags1);
1567                        pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
1568                        mb();/* in order to force CPU ordering */
1569                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1570                        t->task_done(t);
1571                }
1572        }       break;
1573        case IO_XFER_OPEN_RETRY_TIMEOUT:
1574        {       /* This one stashes the sas_task instead */
1575                struct sas_task *t = (struct sas_task *)pm8001_dev;
1576                u32 tag;
1577                struct pm8001_ccb_info *ccb;
1578                struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1579                unsigned long flags, flags1;
1580                int i, ret = 0;
1581
1582                pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
1583
1584                ret = pm8001_query_task(t);
1585
1586                if (ret == TMF_RESP_FUNC_SUCC)
1587                        pm8001_dbg(pm8001_ha, IO, "...Task on lu\n");
1588                else if (ret == TMF_RESP_FUNC_COMPLETE)
1589                        pm8001_dbg(pm8001_ha, IO, "...Task NOT on lu\n");
1590                else
1591                        pm8001_dbg(pm8001_ha, DEVIO, "...query task failed!!!\n");
1592
1593                spin_lock_irqsave(&pm8001_ha->lock, flags);
1594
1595                spin_lock_irqsave(&t->task_state_lock, flags1);
1596
1597                if (unlikely((t->task_state_flags & SAS_TASK_STATE_DONE))) {
1598                        spin_unlock_irqrestore(&t->task_state_lock, flags1);
1599                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1600                        if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1601                                (void)pm8001_abort_task(t);
1602                        break; /* Task got completed by another */
1603                }
1604
1605                spin_unlock_irqrestore(&t->task_state_lock, flags1);
1606
1607                /* Search for a possible ccb that matches the task */
1608                for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1609                        ccb = &pm8001_ha->ccb_info[i];
1610                        tag = ccb->ccb_tag;
1611                        if ((tag != 0xFFFFFFFF) && (ccb->task == t))
1612                                break;
1613                }
1614                if (!ccb) {
1615                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1616                        if (ret == TMF_RESP_FUNC_SUCC) /* task on lu */
1617                                (void)pm8001_abort_task(t);
1618                        break; /* Task got freed by another */
1619                }
1620
1621                pm8001_dev = ccb->device;
1622                dev = pm8001_dev->sas_device;
1623
1624                switch (ret) {
1625                case TMF_RESP_FUNC_SUCC: /* task on lu */
1626                        ccb->open_retry = 1; /* Snub completion */
1627                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1628                        ret = pm8001_abort_task(t);
1629                        ccb->open_retry = 0;
1630                        switch (ret) {
1631                        case TMF_RESP_FUNC_SUCC:
1632                        case TMF_RESP_FUNC_COMPLETE:
1633                                break;
1634                        default: /* device misbehavior */
1635                                ret = TMF_RESP_FUNC_FAILED;
1636                                pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1637                                pm8001_I_T_nexus_reset(dev);
1638                                break;
1639                        }
1640                        break;
1641
1642                case TMF_RESP_FUNC_COMPLETE: /* task not on lu */
1643                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1644                        /* Do we need to abort the task locally? */
1645                        break;
1646
1647                default: /* device misbehavior */
1648                        spin_unlock_irqrestore(&pm8001_ha->lock, flags);
1649                        ret = TMF_RESP_FUNC_FAILED;
1650                        pm8001_dbg(pm8001_ha, IO, "...Reset phy\n");
1651                        pm8001_I_T_nexus_reset(dev);
1652                }
1653
1654                if (ret == TMF_RESP_FUNC_FAILED)
1655                        t = NULL;
1656                pm8001_open_reject_retry(pm8001_ha, t, pm8001_dev);
1657                pm8001_dbg(pm8001_ha, IO, "...Complete\n");
1658        }       break;
1659        case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1660                dev = pm8001_dev->sas_device;
1661                pm8001_I_T_nexus_event_handler(dev);
1662                break;
1663        case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
1664                dev = pm8001_dev->sas_device;
1665                pm8001_I_T_nexus_reset(dev);
1666                break;
1667        case IO_DS_IN_ERROR:
1668                dev = pm8001_dev->sas_device;
1669                pm8001_I_T_nexus_reset(dev);
1670                break;
1671        case IO_DS_NON_OPERATIONAL:
1672                dev = pm8001_dev->sas_device;
1673                pm8001_I_T_nexus_reset(dev);
1674                break;
1675        case IO_FATAL_ERROR:
1676        {
1677                struct pm8001_hba_info *pm8001_ha = pw->pm8001_ha;
1678                struct pm8001_ccb_info *ccb;
1679                struct task_status_struct *ts;
1680                struct sas_task *task;
1681                int i;
1682                u32 tag, device_id;
1683
1684                for (i = 0; ccb = NULL, i < PM8001_MAX_CCB; i++) {
1685                        ccb = &pm8001_ha->ccb_info[i];
1686                        task = ccb->task;
1687                        ts = &task->task_status;
1688                        tag = ccb->ccb_tag;
1689                        /* check if tag is NULL */
1690                        if (!tag) {
1691                                pm8001_dbg(pm8001_ha, FAIL,
1692                                        "tag Null\n");
1693                                continue;
1694                        }
1695                        if (task != NULL) {
1696                                dev = task->dev;
1697                                if (!dev) {
1698                                        pm8001_dbg(pm8001_ha, FAIL,
1699                                                "dev is NULL\n");
1700                                        continue;
1701                                }
1702                                /*complete sas task and update to top layer */
1703                                pm8001_ccb_task_free(pm8001_ha, task, ccb, tag);
1704                                ts->resp = SAS_TASK_COMPLETE;
1705                                task->task_done(task);
1706                        } else if (tag != 0xFFFFFFFF) {
1707                                /* complete the internal commands/non-sas task */
1708                                pm8001_dev = ccb->device;
1709                                if (pm8001_dev->dcompletion) {
1710                                        complete(pm8001_dev->dcompletion);
1711                                        pm8001_dev->dcompletion = NULL;
1712                                }
1713                                complete(pm8001_ha->nvmd_completion);
1714                                pm8001_tag_free(pm8001_ha, tag);
1715                        }
1716                }
1717                /* Deregister all the device ids  */
1718                for (i = 0; i < PM8001_MAX_DEVICES; i++) {
1719                        pm8001_dev = &pm8001_ha->devices[i];
1720                        device_id = pm8001_dev->device_id;
1721                        if (device_id) {
1722                                PM8001_CHIP_DISP->dereg_dev_req(pm8001_ha, device_id);
1723                                pm8001_free_dev(pm8001_dev);
1724                        }
1725                }
1726        }       break;
1727        }
1728        kfree(pw);
1729}
1730
1731int pm8001_handle_event(struct pm8001_hba_info *pm8001_ha, void *data,
1732                               int handler)
1733{
1734        struct pm8001_work *pw;
1735        int ret = 0;
1736
1737        pw = kmalloc(sizeof(struct pm8001_work), GFP_ATOMIC);
1738        if (pw) {
1739                pw->pm8001_ha = pm8001_ha;
1740                pw->data = data;
1741                pw->handler = handler;
1742                INIT_WORK(&pw->work, pm8001_work_fn);
1743                queue_work(pm8001_wq, &pw->work);
1744        } else
1745                ret = -ENOMEM;
1746
1747        return ret;
1748}
1749
1750static void pm8001_send_abort_all(struct pm8001_hba_info *pm8001_ha,
1751                struct pm8001_device *pm8001_ha_dev)
1752{
1753        int res;
1754        u32 ccb_tag;
1755        struct pm8001_ccb_info *ccb;
1756        struct sas_task *task = NULL;
1757        struct task_abort_req task_abort;
1758        struct inbound_queue_table *circularQ;
1759        u32 opc = OPC_INB_SATA_ABORT;
1760        int ret;
1761
1762        if (!pm8001_ha_dev) {
1763                pm8001_dbg(pm8001_ha, FAIL, "dev is null\n");
1764                return;
1765        }
1766
1767        task = sas_alloc_slow_task(GFP_ATOMIC);
1768
1769        if (!task) {
1770                pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task\n");
1771                return;
1772        }
1773
1774        task->task_done = pm8001_task_done;
1775
1776        res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1777        if (res)
1778                return;
1779
1780        ccb = &pm8001_ha->ccb_info[ccb_tag];
1781        ccb->device = pm8001_ha_dev;
1782        ccb->ccb_tag = ccb_tag;
1783        ccb->task = task;
1784
1785        circularQ = &pm8001_ha->inbnd_q_tbl[0];
1786
1787        memset(&task_abort, 0, sizeof(task_abort));
1788        task_abort.abort_all = cpu_to_le32(1);
1789        task_abort.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1790        task_abort.tag = cpu_to_le32(ccb_tag);
1791
1792        ret = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &task_abort,
1793                        sizeof(task_abort), 0);
1794        if (ret)
1795                pm8001_tag_free(pm8001_ha, ccb_tag);
1796
1797}
1798
1799static void pm8001_send_read_log(struct pm8001_hba_info *pm8001_ha,
1800                struct pm8001_device *pm8001_ha_dev)
1801{
1802        struct sata_start_req sata_cmd;
1803        int res;
1804        u32 ccb_tag;
1805        struct pm8001_ccb_info *ccb;
1806        struct sas_task *task = NULL;
1807        struct host_to_dev_fis fis;
1808        struct domain_device *dev;
1809        struct inbound_queue_table *circularQ;
1810        u32 opc = OPC_INB_SATA_HOST_OPSTART;
1811
1812        task = sas_alloc_slow_task(GFP_ATOMIC);
1813
1814        if (!task) {
1815                pm8001_dbg(pm8001_ha, FAIL, "cannot allocate task !!!\n");
1816                return;
1817        }
1818        task->task_done = pm8001_task_done;
1819
1820        res = pm8001_tag_alloc(pm8001_ha, &ccb_tag);
1821        if (res) {
1822                sas_free_task(task);
1823                pm8001_dbg(pm8001_ha, FAIL, "cannot allocate tag !!!\n");
1824                return;
1825        }
1826
1827        /* allocate domain device by ourselves as libsas
1828         * is not going to provide any
1829        */
1830        dev = kzalloc(sizeof(struct domain_device), GFP_ATOMIC);
1831        if (!dev) {
1832                sas_free_task(task);
1833                pm8001_tag_free(pm8001_ha, ccb_tag);
1834                pm8001_dbg(pm8001_ha, FAIL,
1835                           "Domain device cannot be allocated\n");
1836                return;
1837        }
1838        task->dev = dev;
1839        task->dev->lldd_dev = pm8001_ha_dev;
1840
1841        ccb = &pm8001_ha->ccb_info[ccb_tag];
1842        ccb->device = pm8001_ha_dev;
1843        ccb->ccb_tag = ccb_tag;
1844        ccb->task = task;
1845        pm8001_ha_dev->id |= NCQ_READ_LOG_FLAG;
1846        pm8001_ha_dev->id |= NCQ_2ND_RLE_FLAG;
1847
1848        memset(&sata_cmd, 0, sizeof(sata_cmd));
1849        circularQ = &pm8001_ha->inbnd_q_tbl[0];
1850
1851        /* construct read log FIS */
1852        memset(&fis, 0, sizeof(struct host_to_dev_fis));
1853        fis.fis_type = 0x27;
1854        fis.flags = 0x80;
1855        fis.command = ATA_CMD_READ_LOG_EXT;
1856        fis.lbal = 0x10;
1857        fis.sector_count = 0x1;
1858
1859        sata_cmd.tag = cpu_to_le32(ccb_tag);
1860        sata_cmd.device_id = cpu_to_le32(pm8001_ha_dev->device_id);
1861        sata_cmd.ncqtag_atap_dir_m |= ((0x1 << 7) | (0x5 << 9));
1862        memcpy(&sata_cmd.sata_fis, &fis, sizeof(struct host_to_dev_fis));
1863
1864        res = pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &sata_cmd,
1865                        sizeof(sata_cmd), 0);
1866        if (res) {
1867                sas_free_task(task);
1868                pm8001_tag_free(pm8001_ha, ccb_tag);
1869                kfree(dev);
1870        }
1871}
1872
1873/**
1874 * mpi_ssp_completion- process the event that FW response to the SSP request.
1875 * @pm8001_ha: our hba card information
1876 * @piomb: the message contents of this outbound message.
1877 *
1878 * When FW has completed a ssp request for example a IO request, after it has
1879 * filled the SG data with the data, it will trigger this event representing
1880 * that he has finished the job; please check the corresponding buffer.
1881 * So we will tell the caller who maybe waiting the result to tell upper layer
1882 * that the task has been finished.
1883 */
1884static void
1885mpi_ssp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
1886{
1887        struct sas_task *t;
1888        struct pm8001_ccb_info *ccb;
1889        unsigned long flags;
1890        u32 status;
1891        u32 param;
1892        u32 tag;
1893        struct ssp_completion_resp *psspPayload;
1894        struct task_status_struct *ts;
1895        struct ssp_response_iu *iu;
1896        struct pm8001_device *pm8001_dev;
1897        psspPayload = (struct ssp_completion_resp *)(piomb + 4);
1898        status = le32_to_cpu(psspPayload->status);
1899        tag = le32_to_cpu(psspPayload->tag);
1900        ccb = &pm8001_ha->ccb_info[tag];
1901        if ((status == IO_ABORTED) && ccb->open_retry) {
1902                /* Being completed by another */
1903                ccb->open_retry = 0;
1904                return;
1905        }
1906        pm8001_dev = ccb->device;
1907        param = le32_to_cpu(psspPayload->param);
1908
1909        t = ccb->task;
1910
1911        if (status && status != IO_UNDERFLOW)
1912                pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", status);
1913        if (unlikely(!t || !t->lldd_task || !t->dev))
1914                return;
1915        ts = &t->task_status;
1916        /* Print sas address of IO failed device */
1917        if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
1918                (status != IO_UNDERFLOW))
1919                pm8001_dbg(pm8001_ha, FAIL, "SAS Address of IO Failure Drive:%016llx\n",
1920                           SAS_ADDR(t->dev->sas_addr));
1921
1922        if (status)
1923                pm8001_dbg(pm8001_ha, IOERR,
1924                           "status:0x%x, tag:0x%x, task:0x%p\n",
1925                           status, tag, t);
1926
1927        switch (status) {
1928        case IO_SUCCESS:
1929                pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS,param = %d\n",
1930                           param);
1931                if (param == 0) {
1932                        ts->resp = SAS_TASK_COMPLETE;
1933                        ts->stat = SAS_SAM_STAT_GOOD;
1934                } else {
1935                        ts->resp = SAS_TASK_COMPLETE;
1936                        ts->stat = SAS_PROTO_RESPONSE;
1937                        ts->residual = param;
1938                        iu = &psspPayload->ssp_resp_iu;
1939                        sas_ssp_task_response(pm8001_ha->dev, t, iu);
1940                }
1941                if (pm8001_dev)
1942                        atomic_dec(&pm8001_dev->running_req);
1943                break;
1944        case IO_ABORTED:
1945                pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
1946                ts->resp = SAS_TASK_COMPLETE;
1947                ts->stat = SAS_ABORTED_TASK;
1948                break;
1949        case IO_UNDERFLOW:
1950                /* SSP Completion with error */
1951                pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW,param = %d\n",
1952                           param);
1953                ts->resp = SAS_TASK_COMPLETE;
1954                ts->stat = SAS_DATA_UNDERRUN;
1955                ts->residual = param;
1956                if (pm8001_dev)
1957                        atomic_dec(&pm8001_dev->running_req);
1958                break;
1959        case IO_NO_DEVICE:
1960                pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
1961                ts->resp = SAS_TASK_UNDELIVERED;
1962                ts->stat = SAS_PHY_DOWN;
1963                break;
1964        case IO_XFER_ERROR_BREAK:
1965                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
1966                ts->resp = SAS_TASK_COMPLETE;
1967                ts->stat = SAS_OPEN_REJECT;
1968                /* Force the midlayer to retry */
1969                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1970                break;
1971        case IO_XFER_ERROR_PHY_NOT_READY:
1972                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
1973                ts->resp = SAS_TASK_COMPLETE;
1974                ts->stat = SAS_OPEN_REJECT;
1975                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1976                break;
1977        case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
1978                pm8001_dbg(pm8001_ha, IO,
1979                           "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
1980                ts->resp = SAS_TASK_COMPLETE;
1981                ts->stat = SAS_OPEN_REJECT;
1982                ts->open_rej_reason = SAS_OREJ_EPROTO;
1983                break;
1984        case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
1985                pm8001_dbg(pm8001_ha, IO,
1986                           "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
1987                ts->resp = SAS_TASK_COMPLETE;
1988                ts->stat = SAS_OPEN_REJECT;
1989                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
1990                break;
1991        case IO_OPEN_CNX_ERROR_BREAK:
1992                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
1993                ts->resp = SAS_TASK_COMPLETE;
1994                ts->stat = SAS_OPEN_REJECT;
1995                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
1996                break;
1997        case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
1998                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
1999                ts->resp = SAS_TASK_COMPLETE;
2000                ts->stat = SAS_OPEN_REJECT;
2001                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2002                if (!t->uldd_task)
2003                        pm8001_handle_event(pm8001_ha,
2004                                pm8001_dev,
2005                                IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2006                break;
2007        case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2008                pm8001_dbg(pm8001_ha, IO,
2009                           "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2010                ts->resp = SAS_TASK_COMPLETE;
2011                ts->stat = SAS_OPEN_REJECT;
2012                ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2013                break;
2014        case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2015                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2016                ts->resp = SAS_TASK_COMPLETE;
2017                ts->stat = SAS_OPEN_REJECT;
2018                ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2019                break;
2020        case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2021                pm8001_dbg(pm8001_ha, IO,
2022                           "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2023                ts->resp = SAS_TASK_UNDELIVERED;
2024                ts->stat = SAS_OPEN_REJECT;
2025                ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2026                break;
2027        case IO_XFER_ERROR_NAK_RECEIVED:
2028                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2029                ts->resp = SAS_TASK_COMPLETE;
2030                ts->stat = SAS_OPEN_REJECT;
2031                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2032                break;
2033        case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2034                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2035                ts->resp = SAS_TASK_COMPLETE;
2036                ts->stat = SAS_NAK_R_ERR;
2037                break;
2038        case IO_XFER_ERROR_DMA:
2039                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2040                ts->resp = SAS_TASK_COMPLETE;
2041                ts->stat = SAS_OPEN_REJECT;
2042                break;
2043        case IO_XFER_OPEN_RETRY_TIMEOUT:
2044                pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2045                ts->resp = SAS_TASK_COMPLETE;
2046                ts->stat = SAS_OPEN_REJECT;
2047                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2048                break;
2049        case IO_XFER_ERROR_OFFSET_MISMATCH:
2050                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2051                ts->resp = SAS_TASK_COMPLETE;
2052                ts->stat = SAS_OPEN_REJECT;
2053                break;
2054        case IO_PORT_IN_RESET:
2055                pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2056                ts->resp = SAS_TASK_COMPLETE;
2057                ts->stat = SAS_OPEN_REJECT;
2058                break;
2059        case IO_DS_NON_OPERATIONAL:
2060                pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2061                ts->resp = SAS_TASK_COMPLETE;
2062                ts->stat = SAS_OPEN_REJECT;
2063                if (!t->uldd_task)
2064                        pm8001_handle_event(pm8001_ha,
2065                                pm8001_dev,
2066                                IO_DS_NON_OPERATIONAL);
2067                break;
2068        case IO_DS_IN_RECOVERY:
2069                pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
2070                ts->resp = SAS_TASK_COMPLETE;
2071                ts->stat = SAS_OPEN_REJECT;
2072                break;
2073        case IO_TM_TAG_NOT_FOUND:
2074                pm8001_dbg(pm8001_ha, IO, "IO_TM_TAG_NOT_FOUND\n");
2075                ts->resp = SAS_TASK_COMPLETE;
2076                ts->stat = SAS_OPEN_REJECT;
2077                break;
2078        case IO_SSP_EXT_IU_ZERO_LEN_ERROR:
2079                pm8001_dbg(pm8001_ha, IO, "IO_SSP_EXT_IU_ZERO_LEN_ERROR\n");
2080                ts->resp = SAS_TASK_COMPLETE;
2081                ts->stat = SAS_OPEN_REJECT;
2082                break;
2083        case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2084                pm8001_dbg(pm8001_ha, IO,
2085                           "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2086                ts->resp = SAS_TASK_COMPLETE;
2087                ts->stat = SAS_OPEN_REJECT;
2088                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2089                break;
2090        default:
2091                pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2092                /* not allowed case. Therefore, return failed status */
2093                ts->resp = SAS_TASK_COMPLETE;
2094                ts->stat = SAS_OPEN_REJECT;
2095                break;
2096        }
2097        pm8001_dbg(pm8001_ha, IO, "scsi_status = %x\n",
2098                   psspPayload->ssp_resp_iu.status);
2099        spin_lock_irqsave(&t->task_state_lock, flags);
2100        t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2101        t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2102        t->task_state_flags |= SAS_TASK_STATE_DONE;
2103        if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2104                spin_unlock_irqrestore(&t->task_state_lock, flags);
2105                pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2106                           t, status, ts->resp, ts->stat);
2107                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2108        } else {
2109                spin_unlock_irqrestore(&t->task_state_lock, flags);
2110                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2111                mb();/* in order to force CPU ordering */
2112                t->task_done(t);
2113        }
2114}
2115
2116/*See the comments for mpi_ssp_completion */
2117static void mpi_ssp_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2118{
2119        struct sas_task *t;
2120        unsigned long flags;
2121        struct task_status_struct *ts;
2122        struct pm8001_ccb_info *ccb;
2123        struct pm8001_device *pm8001_dev;
2124        struct ssp_event_resp *psspPayload =
2125                (struct ssp_event_resp *)(piomb + 4);
2126        u32 event = le32_to_cpu(psspPayload->event);
2127        u32 tag = le32_to_cpu(psspPayload->tag);
2128        u32 port_id = le32_to_cpu(psspPayload->port_id);
2129        u32 dev_id = le32_to_cpu(psspPayload->device_id);
2130
2131        ccb = &pm8001_ha->ccb_info[tag];
2132        t = ccb->task;
2133        pm8001_dev = ccb->device;
2134        if (event)
2135                pm8001_dbg(pm8001_ha, FAIL, "sas IO status 0x%x\n", event);
2136        if (unlikely(!t || !t->lldd_task || !t->dev))
2137                return;
2138        ts = &t->task_status;
2139        pm8001_dbg(pm8001_ha, DEVIO, "port_id = %x,device_id = %x\n",
2140                   port_id, dev_id);
2141        switch (event) {
2142        case IO_OVERFLOW:
2143                pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2144                ts->resp = SAS_TASK_COMPLETE;
2145                ts->stat = SAS_DATA_OVERRUN;
2146                ts->residual = 0;
2147                if (pm8001_dev)
2148                        atomic_dec(&pm8001_dev->running_req);
2149                break;
2150        case IO_XFER_ERROR_BREAK:
2151                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2152                pm8001_handle_event(pm8001_ha, t, IO_XFER_ERROR_BREAK);
2153                return;
2154        case IO_XFER_ERROR_PHY_NOT_READY:
2155                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2156                ts->resp = SAS_TASK_COMPLETE;
2157                ts->stat = SAS_OPEN_REJECT;
2158                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2159                break;
2160        case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2161                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2162                ts->resp = SAS_TASK_COMPLETE;
2163                ts->stat = SAS_OPEN_REJECT;
2164                ts->open_rej_reason = SAS_OREJ_EPROTO;
2165                break;
2166        case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2167                pm8001_dbg(pm8001_ha, IO,
2168                           "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2169                ts->resp = SAS_TASK_COMPLETE;
2170                ts->stat = SAS_OPEN_REJECT;
2171                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2172                break;
2173        case IO_OPEN_CNX_ERROR_BREAK:
2174                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2175                ts->resp = SAS_TASK_COMPLETE;
2176                ts->stat = SAS_OPEN_REJECT;
2177                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2178                break;
2179        case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2180                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2181                ts->resp = SAS_TASK_COMPLETE;
2182                ts->stat = SAS_OPEN_REJECT;
2183                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2184                if (!t->uldd_task)
2185                        pm8001_handle_event(pm8001_ha,
2186                                pm8001_dev,
2187                                IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2188                break;
2189        case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2190                pm8001_dbg(pm8001_ha, IO,
2191                           "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2192                ts->resp = SAS_TASK_COMPLETE;
2193                ts->stat = SAS_OPEN_REJECT;
2194                ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2195                break;
2196        case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2197                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2198                ts->resp = SAS_TASK_COMPLETE;
2199                ts->stat = SAS_OPEN_REJECT;
2200                ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2201                break;
2202        case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2203                pm8001_dbg(pm8001_ha, IO,
2204                           "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2205                ts->resp = SAS_TASK_COMPLETE;
2206                ts->stat = SAS_OPEN_REJECT;
2207                ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2208                break;
2209        case IO_XFER_ERROR_NAK_RECEIVED:
2210                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2211                ts->resp = SAS_TASK_COMPLETE;
2212                ts->stat = SAS_OPEN_REJECT;
2213                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2214                break;
2215        case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2216                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2217                ts->resp = SAS_TASK_COMPLETE;
2218                ts->stat = SAS_NAK_R_ERR;
2219                break;
2220        case IO_XFER_OPEN_RETRY_TIMEOUT:
2221                pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2222                pm8001_handle_event(pm8001_ha, t, IO_XFER_OPEN_RETRY_TIMEOUT);
2223                return;
2224        case IO_XFER_ERROR_UNEXPECTED_PHASE:
2225                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2226                ts->resp = SAS_TASK_COMPLETE;
2227                ts->stat = SAS_DATA_OVERRUN;
2228                break;
2229        case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2230                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2231                ts->resp = SAS_TASK_COMPLETE;
2232                ts->stat = SAS_DATA_OVERRUN;
2233                break;
2234        case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2235                pm8001_dbg(pm8001_ha, IO,
2236                           "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2237                ts->resp = SAS_TASK_COMPLETE;
2238                ts->stat = SAS_DATA_OVERRUN;
2239                break;
2240        case IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT:
2241                pm8001_dbg(pm8001_ha, IO,
2242                           "IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT\n");
2243                ts->resp = SAS_TASK_COMPLETE;
2244                ts->stat = SAS_DATA_OVERRUN;
2245                break;
2246        case IO_XFER_ERROR_OFFSET_MISMATCH:
2247                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2248                ts->resp = SAS_TASK_COMPLETE;
2249                ts->stat = SAS_DATA_OVERRUN;
2250                break;
2251        case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2252                pm8001_dbg(pm8001_ha, IO,
2253                           "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2254                ts->resp = SAS_TASK_COMPLETE;
2255                ts->stat = SAS_DATA_OVERRUN;
2256                break;
2257        case IO_XFER_CMD_FRAME_ISSUED:
2258                pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2259                return;
2260        default:
2261                pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2262                /* not allowed case. Therefore, return failed status */
2263                ts->resp = SAS_TASK_COMPLETE;
2264                ts->stat = SAS_DATA_OVERRUN;
2265                break;
2266        }
2267        spin_lock_irqsave(&t->task_state_lock, flags);
2268        t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2269        t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2270        t->task_state_flags |= SAS_TASK_STATE_DONE;
2271        if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2272                spin_unlock_irqrestore(&t->task_state_lock, flags);
2273                pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with event 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2274                           t, event, ts->resp, ts->stat);
2275                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2276        } else {
2277                spin_unlock_irqrestore(&t->task_state_lock, flags);
2278                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2279                mb();/* in order to force CPU ordering */
2280                t->task_done(t);
2281        }
2282}
2283
2284/*See the comments for mpi_ssp_completion */
2285static void
2286mpi_sata_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2287{
2288        struct sas_task *t;
2289        struct pm8001_ccb_info *ccb;
2290        u32 param;
2291        u32 status;
2292        u32 tag;
2293        int i, j;
2294        u8 sata_addr_low[4];
2295        u32 temp_sata_addr_low;
2296        u8 sata_addr_hi[4];
2297        u32 temp_sata_addr_hi;
2298        struct sata_completion_resp *psataPayload;
2299        struct task_status_struct *ts;
2300        struct ata_task_resp *resp ;
2301        u32 *sata_resp;
2302        struct pm8001_device *pm8001_dev;
2303        unsigned long flags;
2304
2305        psataPayload = (struct sata_completion_resp *)(piomb + 4);
2306        status = le32_to_cpu(psataPayload->status);
2307        tag = le32_to_cpu(psataPayload->tag);
2308
2309        if (!tag) {
2310                pm8001_dbg(pm8001_ha, FAIL, "tag null\n");
2311                return;
2312        }
2313        ccb = &pm8001_ha->ccb_info[tag];
2314        param = le32_to_cpu(psataPayload->param);
2315        if (ccb) {
2316                t = ccb->task;
2317                pm8001_dev = ccb->device;
2318        } else {
2319                pm8001_dbg(pm8001_ha, FAIL, "ccb null\n");
2320                return;
2321        }
2322
2323        if (t) {
2324                if (t->dev && (t->dev->lldd_dev))
2325                        pm8001_dev = t->dev->lldd_dev;
2326        } else {
2327                pm8001_dbg(pm8001_ha, FAIL, "task null\n");
2328                return;
2329        }
2330
2331        if ((pm8001_dev && !(pm8001_dev->id & NCQ_READ_LOG_FLAG))
2332                && unlikely(!t || !t->lldd_task || !t->dev)) {
2333                pm8001_dbg(pm8001_ha, FAIL, "task or dev null\n");
2334                return;
2335        }
2336
2337        ts = &t->task_status;
2338        if (!ts) {
2339                pm8001_dbg(pm8001_ha, FAIL, "ts null\n");
2340                return;
2341        }
2342
2343        if (status)
2344                pm8001_dbg(pm8001_ha, IOERR,
2345                           "status:0x%x, tag:0x%x, task::0x%p\n",
2346                           status, tag, t);
2347
2348        /* Print sas address of IO failed device */
2349        if ((status != IO_SUCCESS) && (status != IO_OVERFLOW) &&
2350                (status != IO_UNDERFLOW)) {
2351                if (!((t->dev->parent) &&
2352                        (dev_is_expander(t->dev->parent->dev_type)))) {
2353                        for (i = 0, j = 4; j <= 7 && i <= 3; i++, j++)
2354                                sata_addr_low[i] = pm8001_ha->sas_addr[j];
2355                        for (i = 0, j = 0; j <= 3 && i <= 3; i++, j++)
2356                                sata_addr_hi[i] = pm8001_ha->sas_addr[j];
2357                        memcpy(&temp_sata_addr_low, sata_addr_low,
2358                                sizeof(sata_addr_low));
2359                        memcpy(&temp_sata_addr_hi, sata_addr_hi,
2360                                sizeof(sata_addr_hi));
2361                        temp_sata_addr_hi = (((temp_sata_addr_hi >> 24) & 0xff)
2362                                                |((temp_sata_addr_hi << 8) &
2363                                                0xff0000) |
2364                                                ((temp_sata_addr_hi >> 8)
2365                                                & 0xff00) |
2366                                                ((temp_sata_addr_hi << 24) &
2367                                                0xff000000));
2368                        temp_sata_addr_low = ((((temp_sata_addr_low >> 24)
2369                                                & 0xff) |
2370                                                ((temp_sata_addr_low << 8)
2371                                                & 0xff0000) |
2372                                                ((temp_sata_addr_low >> 8)
2373                                                & 0xff00) |
2374                                                ((temp_sata_addr_low << 24)
2375                                                & 0xff000000)) +
2376                                                pm8001_dev->attached_phy +
2377                                                0x10);
2378                        pm8001_dbg(pm8001_ha, FAIL,
2379                                   "SAS Address of IO Failure Drive:%08x%08x\n",
2380                                   temp_sata_addr_hi,
2381                                   temp_sata_addr_low);
2382                } else {
2383                        pm8001_dbg(pm8001_ha, FAIL,
2384                                   "SAS Address of IO Failure Drive:%016llx\n",
2385                                   SAS_ADDR(t->dev->sas_addr));
2386                }
2387        }
2388        switch (status) {
2389        case IO_SUCCESS:
2390                pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2391                if (param == 0) {
2392                        ts->resp = SAS_TASK_COMPLETE;
2393                        ts->stat = SAS_SAM_STAT_GOOD;
2394                        /* check if response is for SEND READ LOG */
2395                        if (pm8001_dev &&
2396                                (pm8001_dev->id & NCQ_READ_LOG_FLAG)) {
2397                                /* set new bit for abort_all */
2398                                pm8001_dev->id |= NCQ_ABORT_ALL_FLAG;
2399                                /* clear bit for read log */
2400                                pm8001_dev->id = pm8001_dev->id & 0x7FFFFFFF;
2401                                pm8001_send_abort_all(pm8001_ha, pm8001_dev);
2402                                /* Free the tag */
2403                                pm8001_tag_free(pm8001_ha, tag);
2404                                sas_free_task(t);
2405                                return;
2406                        }
2407                } else {
2408                        u8 len;
2409                        ts->resp = SAS_TASK_COMPLETE;
2410                        ts->stat = SAS_PROTO_RESPONSE;
2411                        ts->residual = param;
2412                        pm8001_dbg(pm8001_ha, IO,
2413                                   "SAS_PROTO_RESPONSE len = %d\n",
2414                                   param);
2415                        sata_resp = &psataPayload->sata_resp[0];
2416                        resp = (struct ata_task_resp *)ts->buf;
2417                        if (t->ata_task.dma_xfer == 0 &&
2418                            t->data_dir == DMA_FROM_DEVICE) {
2419                                len = sizeof(struct pio_setup_fis);
2420                                pm8001_dbg(pm8001_ha, IO,
2421                                           "PIO read len = %d\n", len);
2422                        } else if (t->ata_task.use_ncq) {
2423                                len = sizeof(struct set_dev_bits_fis);
2424                                pm8001_dbg(pm8001_ha, IO, "FPDMA len = %d\n",
2425                                           len);
2426                        } else {
2427                                len = sizeof(struct dev_to_host_fis);
2428                                pm8001_dbg(pm8001_ha, IO, "other len = %d\n",
2429                                           len);
2430                        }
2431                        if (SAS_STATUS_BUF_SIZE >= sizeof(*resp)) {
2432                                resp->frame_len = len;
2433                                memcpy(&resp->ending_fis[0], sata_resp, len);
2434                                ts->buf_valid_size = sizeof(*resp);
2435                        } else
2436                                pm8001_dbg(pm8001_ha, IO,
2437                                           "response too large\n");
2438                }
2439                if (pm8001_dev)
2440                        atomic_dec(&pm8001_dev->running_req);
2441                break;
2442        case IO_ABORTED:
2443                pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB Tag\n");
2444                ts->resp = SAS_TASK_COMPLETE;
2445                ts->stat = SAS_ABORTED_TASK;
2446                if (pm8001_dev)
2447                        atomic_dec(&pm8001_dev->running_req);
2448                break;
2449                /* following cases are to do cases */
2450        case IO_UNDERFLOW:
2451                /* SATA Completion with error */
2452                pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW param = %d\n", param);
2453                ts->resp = SAS_TASK_COMPLETE;
2454                ts->stat = SAS_DATA_UNDERRUN;
2455                ts->residual =  param;
2456                if (pm8001_dev)
2457                        atomic_dec(&pm8001_dev->running_req);
2458                break;
2459        case IO_NO_DEVICE:
2460                pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2461                ts->resp = SAS_TASK_UNDELIVERED;
2462                ts->stat = SAS_PHY_DOWN;
2463                if (pm8001_dev)
2464                        atomic_dec(&pm8001_dev->running_req);
2465                break;
2466        case IO_XFER_ERROR_BREAK:
2467                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2468                ts->resp = SAS_TASK_COMPLETE;
2469                ts->stat = SAS_INTERRUPTED;
2470                if (pm8001_dev)
2471                        atomic_dec(&pm8001_dev->running_req);
2472                break;
2473        case IO_XFER_ERROR_PHY_NOT_READY:
2474                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2475                ts->resp = SAS_TASK_COMPLETE;
2476                ts->stat = SAS_OPEN_REJECT;
2477                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2478                if (pm8001_dev)
2479                        atomic_dec(&pm8001_dev->running_req);
2480                break;
2481        case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2482                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2483                ts->resp = SAS_TASK_COMPLETE;
2484                ts->stat = SAS_OPEN_REJECT;
2485                ts->open_rej_reason = SAS_OREJ_EPROTO;
2486                if (pm8001_dev)
2487                        atomic_dec(&pm8001_dev->running_req);
2488                break;
2489        case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2490                pm8001_dbg(pm8001_ha, IO,
2491                           "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2492                ts->resp = SAS_TASK_COMPLETE;
2493                ts->stat = SAS_OPEN_REJECT;
2494                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2495                if (pm8001_dev)
2496                        atomic_dec(&pm8001_dev->running_req);
2497                break;
2498        case IO_OPEN_CNX_ERROR_BREAK:
2499                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2500                ts->resp = SAS_TASK_COMPLETE;
2501                ts->stat = SAS_OPEN_REJECT;
2502                ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2503                if (pm8001_dev)
2504                        atomic_dec(&pm8001_dev->running_req);
2505                break;
2506        case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2507                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2508                ts->resp = SAS_TASK_COMPLETE;
2509                ts->stat = SAS_DEV_NO_RESPONSE;
2510                if (!t->uldd_task) {
2511                        pm8001_handle_event(pm8001_ha,
2512                                pm8001_dev,
2513                                IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2514                        ts->resp = SAS_TASK_UNDELIVERED;
2515                        ts->stat = SAS_QUEUE_FULL;
2516                        pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2517                        return;
2518                }
2519                break;
2520        case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2521                pm8001_dbg(pm8001_ha, IO,
2522                           "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2523                ts->resp = SAS_TASK_UNDELIVERED;
2524                ts->stat = SAS_OPEN_REJECT;
2525                ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2526                if (!t->uldd_task) {
2527                        pm8001_handle_event(pm8001_ha,
2528                                pm8001_dev,
2529                                IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2530                        ts->resp = SAS_TASK_UNDELIVERED;
2531                        ts->stat = SAS_QUEUE_FULL;
2532                        pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2533                        return;
2534                }
2535                break;
2536        case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2537                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2538                ts->resp = SAS_TASK_COMPLETE;
2539                ts->stat = SAS_OPEN_REJECT;
2540                ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2541                if (pm8001_dev)
2542                        atomic_dec(&pm8001_dev->running_req);
2543                break;
2544        case IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY:
2545                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY\n");
2546                ts->resp = SAS_TASK_COMPLETE;
2547                ts->stat = SAS_DEV_NO_RESPONSE;
2548                if (!t->uldd_task) {
2549                        pm8001_handle_event(pm8001_ha,
2550                                pm8001_dev,
2551                                IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY);
2552                        ts->resp = SAS_TASK_UNDELIVERED;
2553                        ts->stat = SAS_QUEUE_FULL;
2554                        pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2555                        return;
2556                }
2557                break;
2558        case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2559                pm8001_dbg(pm8001_ha, IO,
2560                           "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2561                ts->resp = SAS_TASK_COMPLETE;
2562                ts->stat = SAS_OPEN_REJECT;
2563                ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2564                if (pm8001_dev)
2565                        atomic_dec(&pm8001_dev->running_req);
2566                break;
2567        case IO_XFER_ERROR_NAK_RECEIVED:
2568                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2569                ts->resp = SAS_TASK_COMPLETE;
2570                ts->stat = SAS_NAK_R_ERR;
2571                if (pm8001_dev)
2572                        atomic_dec(&pm8001_dev->running_req);
2573                break;
2574        case IO_XFER_ERROR_ACK_NAK_TIMEOUT:
2575                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_ACK_NAK_TIMEOUT\n");
2576                ts->resp = SAS_TASK_COMPLETE;
2577                ts->stat = SAS_NAK_R_ERR;
2578                if (pm8001_dev)
2579                        atomic_dec(&pm8001_dev->running_req);
2580                break;
2581        case IO_XFER_ERROR_DMA:
2582                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_DMA\n");
2583                ts->resp = SAS_TASK_COMPLETE;
2584                ts->stat = SAS_ABORTED_TASK;
2585                if (pm8001_dev)
2586                        atomic_dec(&pm8001_dev->running_req);
2587                break;
2588        case IO_XFER_ERROR_SATA_LINK_TIMEOUT:
2589                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_SATA_LINK_TIMEOUT\n");
2590                ts->resp = SAS_TASK_UNDELIVERED;
2591                ts->stat = SAS_DEV_NO_RESPONSE;
2592                if (pm8001_dev)
2593                        atomic_dec(&pm8001_dev->running_req);
2594                break;
2595        case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2596                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2597                ts->resp = SAS_TASK_COMPLETE;
2598                ts->stat = SAS_DATA_UNDERRUN;
2599                if (pm8001_dev)
2600                        atomic_dec(&pm8001_dev->running_req);
2601                break;
2602        case IO_XFER_OPEN_RETRY_TIMEOUT:
2603                pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2604                ts->resp = SAS_TASK_COMPLETE;
2605                ts->stat = SAS_OPEN_TO;
2606                if (pm8001_dev)
2607                        atomic_dec(&pm8001_dev->running_req);
2608                break;
2609        case IO_PORT_IN_RESET:
2610                pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
2611                ts->resp = SAS_TASK_COMPLETE;
2612                ts->stat = SAS_DEV_NO_RESPONSE;
2613                if (pm8001_dev)
2614                        atomic_dec(&pm8001_dev->running_req);
2615                break;
2616        case IO_DS_NON_OPERATIONAL:
2617                pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
2618                ts->resp = SAS_TASK_COMPLETE;
2619                ts->stat = SAS_DEV_NO_RESPONSE;
2620                if (!t->uldd_task) {
2621                        pm8001_handle_event(pm8001_ha, pm8001_dev,
2622                                    IO_DS_NON_OPERATIONAL);
2623                        ts->resp = SAS_TASK_UNDELIVERED;
2624                        ts->stat = SAS_QUEUE_FULL;
2625                        pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2626                        return;
2627                }
2628                break;
2629        case IO_DS_IN_RECOVERY:
2630                pm8001_dbg(pm8001_ha, IO, "  IO_DS_IN_RECOVERY\n");
2631                ts->resp = SAS_TASK_COMPLETE;
2632                ts->stat = SAS_DEV_NO_RESPONSE;
2633                if (pm8001_dev)
2634                        atomic_dec(&pm8001_dev->running_req);
2635                break;
2636        case IO_DS_IN_ERROR:
2637                pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_ERROR\n");
2638                ts->resp = SAS_TASK_COMPLETE;
2639                ts->stat = SAS_DEV_NO_RESPONSE;
2640                if (!t->uldd_task) {
2641                        pm8001_handle_event(pm8001_ha, pm8001_dev,
2642                                    IO_DS_IN_ERROR);
2643                        ts->resp = SAS_TASK_UNDELIVERED;
2644                        ts->stat = SAS_QUEUE_FULL;
2645                        pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2646                        return;
2647                }
2648                break;
2649        case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
2650                pm8001_dbg(pm8001_ha, IO,
2651                           "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
2652                ts->resp = SAS_TASK_COMPLETE;
2653                ts->stat = SAS_OPEN_REJECT;
2654                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2655                if (pm8001_dev)
2656                        atomic_dec(&pm8001_dev->running_req);
2657                break;
2658        default:
2659                pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
2660                /* not allowed case. Therefore, return failed status */
2661                ts->resp = SAS_TASK_COMPLETE;
2662                ts->stat = SAS_DEV_NO_RESPONSE;
2663                if (pm8001_dev)
2664                        atomic_dec(&pm8001_dev->running_req);
2665                break;
2666        }
2667        spin_lock_irqsave(&t->task_state_lock, flags);
2668        t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2669        t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2670        t->task_state_flags |= SAS_TASK_STATE_DONE;
2671        if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2672                spin_unlock_irqrestore(&t->task_state_lock, flags);
2673                pm8001_dbg(pm8001_ha, FAIL,
2674                           "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2675                           t, status, ts->resp, ts->stat);
2676                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2677        } else {
2678                spin_unlock_irqrestore(&t->task_state_lock, flags);
2679                pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2680        }
2681}
2682
2683/*See the comments for mpi_ssp_completion */
2684static void mpi_sata_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
2685{
2686        struct sas_task *t;
2687        struct task_status_struct *ts;
2688        struct pm8001_ccb_info *ccb;
2689        struct pm8001_device *pm8001_dev;
2690        struct sata_event_resp *psataPayload =
2691                (struct sata_event_resp *)(piomb + 4);
2692        u32 event = le32_to_cpu(psataPayload->event);
2693        u32 tag = le32_to_cpu(psataPayload->tag);
2694        u32 port_id = le32_to_cpu(psataPayload->port_id);
2695        u32 dev_id = le32_to_cpu(psataPayload->device_id);
2696        unsigned long flags;
2697
2698        ccb = &pm8001_ha->ccb_info[tag];
2699
2700        if (ccb) {
2701                t = ccb->task;
2702                pm8001_dev = ccb->device;
2703        } else {
2704                pm8001_dbg(pm8001_ha, FAIL, "No CCB !!!. returning\n");
2705        }
2706        if (event)
2707                pm8001_dbg(pm8001_ha, FAIL, "SATA EVENT 0x%x\n", event);
2708
2709        /* Check if this is NCQ error */
2710        if (event == IO_XFER_ERROR_ABORTED_NCQ_MODE) {
2711                /* find device using device id */
2712                pm8001_dev = pm8001_find_dev(pm8001_ha, dev_id);
2713                /* send read log extension */
2714                if (pm8001_dev)
2715                        pm8001_send_read_log(pm8001_ha, pm8001_dev);
2716                return;
2717        }
2718
2719        ccb = &pm8001_ha->ccb_info[tag];
2720        t = ccb->task;
2721        pm8001_dev = ccb->device;
2722        if (event)
2723                pm8001_dbg(pm8001_ha, FAIL, "sata IO status 0x%x\n", event);
2724        if (unlikely(!t || !t->lldd_task || !t->dev))
2725                return;
2726        ts = &t->task_status;
2727        pm8001_dbg(pm8001_ha, DEVIO,
2728                   "port_id:0x%x, device_id:0x%x, tag:0x%x, event:0x%x\n",
2729                   port_id, dev_id, tag, event);
2730        switch (event) {
2731        case IO_OVERFLOW:
2732                pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2733                ts->resp = SAS_TASK_COMPLETE;
2734                ts->stat = SAS_DATA_OVERRUN;
2735                ts->residual = 0;
2736                if (pm8001_dev)
2737                        atomic_dec(&pm8001_dev->running_req);
2738                break;
2739        case IO_XFER_ERROR_BREAK:
2740                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2741                ts->resp = SAS_TASK_COMPLETE;
2742                ts->stat = SAS_INTERRUPTED;
2743                break;
2744        case IO_XFER_ERROR_PHY_NOT_READY:
2745                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2746                ts->resp = SAS_TASK_COMPLETE;
2747                ts->stat = SAS_OPEN_REJECT;
2748                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
2749                break;
2750        case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2751                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2752                ts->resp = SAS_TASK_COMPLETE;
2753                ts->stat = SAS_OPEN_REJECT;
2754                ts->open_rej_reason = SAS_OREJ_EPROTO;
2755                break;
2756        case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2757                pm8001_dbg(pm8001_ha, IO,
2758                           "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2759                ts->resp = SAS_TASK_COMPLETE;
2760                ts->stat = SAS_OPEN_REJECT;
2761                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2762                break;
2763        case IO_OPEN_CNX_ERROR_BREAK:
2764                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2765                ts->resp = SAS_TASK_COMPLETE;
2766                ts->stat = SAS_OPEN_REJECT;
2767                ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2768                break;
2769        case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2770                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2771                ts->resp = SAS_TASK_UNDELIVERED;
2772                ts->stat = SAS_DEV_NO_RESPONSE;
2773                if (!t->uldd_task) {
2774                        pm8001_handle_event(pm8001_ha,
2775                                pm8001_dev,
2776                                IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2777                        ts->resp = SAS_TASK_COMPLETE;
2778                        ts->stat = SAS_QUEUE_FULL;
2779                        pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2780                        return;
2781                }
2782                break;
2783        case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2784                pm8001_dbg(pm8001_ha, IO,
2785                           "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2786                ts->resp = SAS_TASK_UNDELIVERED;
2787                ts->stat = SAS_OPEN_REJECT;
2788                ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2789                break;
2790        case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2791                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2792                ts->resp = SAS_TASK_COMPLETE;
2793                ts->stat = SAS_OPEN_REJECT;
2794                ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2795                break;
2796        case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2797                pm8001_dbg(pm8001_ha, IO,
2798                           "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2799                ts->resp = SAS_TASK_COMPLETE;
2800                ts->stat = SAS_OPEN_REJECT;
2801                ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
2802                break;
2803        case IO_XFER_ERROR_NAK_RECEIVED:
2804                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_NAK_RECEIVED\n");
2805                ts->resp = SAS_TASK_COMPLETE;
2806                ts->stat = SAS_NAK_R_ERR;
2807                break;
2808        case IO_XFER_ERROR_PEER_ABORTED:
2809                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PEER_ABORTED\n");
2810                ts->resp = SAS_TASK_COMPLETE;
2811                ts->stat = SAS_NAK_R_ERR;
2812                break;
2813        case IO_XFER_ERROR_REJECTED_NCQ_MODE:
2814                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_REJECTED_NCQ_MODE\n");
2815                ts->resp = SAS_TASK_COMPLETE;
2816                ts->stat = SAS_DATA_UNDERRUN;
2817                break;
2818        case IO_XFER_OPEN_RETRY_TIMEOUT:
2819                pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
2820                ts->resp = SAS_TASK_COMPLETE;
2821                ts->stat = SAS_OPEN_TO;
2822                break;
2823        case IO_XFER_ERROR_UNEXPECTED_PHASE:
2824                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_UNEXPECTED_PHASE\n");
2825                ts->resp = SAS_TASK_COMPLETE;
2826                ts->stat = SAS_OPEN_TO;
2827                break;
2828        case IO_XFER_ERROR_XFER_RDY_OVERRUN:
2829                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_XFER_RDY_OVERRUN\n");
2830                ts->resp = SAS_TASK_COMPLETE;
2831                ts->stat = SAS_OPEN_TO;
2832                break;
2833        case IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED:
2834                pm8001_dbg(pm8001_ha, IO,
2835                           "IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED\n");
2836                ts->resp = SAS_TASK_COMPLETE;
2837                ts->stat = SAS_OPEN_TO;
2838                break;
2839        case IO_XFER_ERROR_OFFSET_MISMATCH:
2840                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_OFFSET_MISMATCH\n");
2841                ts->resp = SAS_TASK_COMPLETE;
2842                ts->stat = SAS_OPEN_TO;
2843                break;
2844        case IO_XFER_ERROR_XFER_ZERO_DATA_LEN:
2845                pm8001_dbg(pm8001_ha, IO,
2846                           "IO_XFER_ERROR_XFER_ZERO_DATA_LEN\n");
2847                ts->resp = SAS_TASK_COMPLETE;
2848                ts->stat = SAS_OPEN_TO;
2849                break;
2850        case IO_XFER_CMD_FRAME_ISSUED:
2851                pm8001_dbg(pm8001_ha, IO, "IO_XFER_CMD_FRAME_ISSUED\n");
2852                break;
2853        case IO_XFER_PIO_SETUP_ERROR:
2854                pm8001_dbg(pm8001_ha, IO, "IO_XFER_PIO_SETUP_ERROR\n");
2855                ts->resp = SAS_TASK_COMPLETE;
2856                ts->stat = SAS_OPEN_TO;
2857                break;
2858        default:
2859                pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", event);
2860                /* not allowed case. Therefore, return failed status */
2861                ts->resp = SAS_TASK_COMPLETE;
2862                ts->stat = SAS_OPEN_TO;
2863                break;
2864        }
2865        spin_lock_irqsave(&t->task_state_lock, flags);
2866        t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
2867        t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
2868        t->task_state_flags |= SAS_TASK_STATE_DONE;
2869        if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
2870                spin_unlock_irqrestore(&t->task_state_lock, flags);
2871                pm8001_dbg(pm8001_ha, FAIL,
2872                           "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
2873                           t, event, ts->resp, ts->stat);
2874                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
2875        } else {
2876                spin_unlock_irqrestore(&t->task_state_lock, flags);
2877                pm8001_ccb_task_free_done(pm8001_ha, t, ccb, tag);
2878        }
2879}
2880
2881/*See the comments for mpi_ssp_completion */
2882static void
2883mpi_smp_completion(struct pm8001_hba_info *pm8001_ha, void *piomb)
2884{
2885        struct sas_task *t;
2886        struct pm8001_ccb_info *ccb;
2887        unsigned long flags;
2888        u32 status;
2889        u32 tag;
2890        struct smp_completion_resp *psmpPayload;
2891        struct task_status_struct *ts;
2892        struct pm8001_device *pm8001_dev;
2893
2894        psmpPayload = (struct smp_completion_resp *)(piomb + 4);
2895        status = le32_to_cpu(psmpPayload->status);
2896        tag = le32_to_cpu(psmpPayload->tag);
2897
2898        ccb = &pm8001_ha->ccb_info[tag];
2899        t = ccb->task;
2900        ts = &t->task_status;
2901        pm8001_dev = ccb->device;
2902        if (status) {
2903                pm8001_dbg(pm8001_ha, FAIL, "smp IO status 0x%x\n", status);
2904                pm8001_dbg(pm8001_ha, IOERR,
2905                           "status:0x%x, tag:0x%x, task:0x%p\n",
2906                           status, tag, t);
2907        }
2908        if (unlikely(!t || !t->lldd_task || !t->dev))
2909                return;
2910
2911        switch (status) {
2912        case IO_SUCCESS:
2913                pm8001_dbg(pm8001_ha, IO, "IO_SUCCESS\n");
2914                ts->resp = SAS_TASK_COMPLETE;
2915                ts->stat = SAS_SAM_STAT_GOOD;
2916                if (pm8001_dev)
2917                        atomic_dec(&pm8001_dev->running_req);
2918                break;
2919        case IO_ABORTED:
2920                pm8001_dbg(pm8001_ha, IO, "IO_ABORTED IOMB\n");
2921                ts->resp = SAS_TASK_COMPLETE;
2922                ts->stat = SAS_ABORTED_TASK;
2923                if (pm8001_dev)
2924                        atomic_dec(&pm8001_dev->running_req);
2925                break;
2926        case IO_OVERFLOW:
2927                pm8001_dbg(pm8001_ha, IO, "IO_UNDERFLOW\n");
2928                ts->resp = SAS_TASK_COMPLETE;
2929                ts->stat = SAS_DATA_OVERRUN;
2930                ts->residual = 0;
2931                if (pm8001_dev)
2932                        atomic_dec(&pm8001_dev->running_req);
2933                break;
2934        case IO_NO_DEVICE:
2935                pm8001_dbg(pm8001_ha, IO, "IO_NO_DEVICE\n");
2936                ts->resp = SAS_TASK_COMPLETE;
2937                ts->stat = SAS_PHY_DOWN;
2938                break;
2939        case IO_ERROR_HW_TIMEOUT:
2940                pm8001_dbg(pm8001_ha, IO, "IO_ERROR_HW_TIMEOUT\n");
2941                ts->resp = SAS_TASK_COMPLETE;
2942                ts->stat = SAS_SAM_STAT_BUSY;
2943                break;
2944        case IO_XFER_ERROR_BREAK:
2945                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_BREAK\n");
2946                ts->resp = SAS_TASK_COMPLETE;
2947                ts->stat = SAS_SAM_STAT_BUSY;
2948                break;
2949        case IO_XFER_ERROR_PHY_NOT_READY:
2950                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_PHY_NOT_READY\n");
2951                ts->resp = SAS_TASK_COMPLETE;
2952                ts->stat = SAS_SAM_STAT_BUSY;
2953                break;
2954        case IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED:
2955                pm8001_dbg(pm8001_ha, IO,
2956                           "IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED\n");
2957                ts->resp = SAS_TASK_COMPLETE;
2958                ts->stat = SAS_OPEN_REJECT;
2959                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2960                break;
2961        case IO_OPEN_CNX_ERROR_ZONE_VIOLATION:
2962                pm8001_dbg(pm8001_ha, IO,
2963                           "IO_OPEN_CNX_ERROR_ZONE_VIOLATION\n");
2964                ts->resp = SAS_TASK_COMPLETE;
2965                ts->stat = SAS_OPEN_REJECT;
2966                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2967                break;
2968        case IO_OPEN_CNX_ERROR_BREAK:
2969                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_BREAK\n");
2970                ts->resp = SAS_TASK_COMPLETE;
2971                ts->stat = SAS_OPEN_REJECT;
2972                ts->open_rej_reason = SAS_OREJ_RSVD_CONT0;
2973                break;
2974        case IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS:
2975                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS\n");
2976                ts->resp = SAS_TASK_COMPLETE;
2977                ts->stat = SAS_OPEN_REJECT;
2978                ts->open_rej_reason = SAS_OREJ_UNKNOWN;
2979                pm8001_handle_event(pm8001_ha,
2980                                pm8001_dev,
2981                                IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS);
2982                break;
2983        case IO_OPEN_CNX_ERROR_BAD_DESTINATION:
2984                pm8001_dbg(pm8001_ha, IO,
2985                           "IO_OPEN_CNX_ERROR_BAD_DESTINATION\n");
2986                ts->resp = SAS_TASK_COMPLETE;
2987                ts->stat = SAS_OPEN_REJECT;
2988                ts->open_rej_reason = SAS_OREJ_BAD_DEST;
2989                break;
2990        case IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED:
2991                pm8001_dbg(pm8001_ha, IO, "IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED\n");
2992                ts->resp = SAS_TASK_COMPLETE;
2993                ts->stat = SAS_OPEN_REJECT;
2994                ts->open_rej_reason = SAS_OREJ_CONN_RATE;
2995                break;
2996        case IO_OPEN_CNX_ERROR_WRONG_DESTINATION:
2997                pm8001_dbg(pm8001_ha, IO,
2998                           "IO_OPEN_CNX_ERROR_WRONG_DESTINATION\n");
2999                ts->resp = SAS_TASK_COMPLETE;
3000                ts->stat = SAS_OPEN_REJECT;
3001                ts->open_rej_reason = SAS_OREJ_WRONG_DEST;
3002                break;
3003        case IO_XFER_ERROR_RX_FRAME:
3004                pm8001_dbg(pm8001_ha, IO, "IO_XFER_ERROR_RX_FRAME\n");
3005                ts->resp = SAS_TASK_COMPLETE;
3006                ts->stat = SAS_DEV_NO_RESPONSE;
3007                break;
3008        case IO_XFER_OPEN_RETRY_TIMEOUT:
3009                pm8001_dbg(pm8001_ha, IO, "IO_XFER_OPEN_RETRY_TIMEOUT\n");
3010                ts->resp = SAS_TASK_COMPLETE;
3011                ts->stat = SAS_OPEN_REJECT;
3012                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3013                break;
3014        case IO_ERROR_INTERNAL_SMP_RESOURCE:
3015                pm8001_dbg(pm8001_ha, IO, "IO_ERROR_INTERNAL_SMP_RESOURCE\n");
3016                ts->resp = SAS_TASK_COMPLETE;
3017                ts->stat = SAS_QUEUE_FULL;
3018                break;
3019        case IO_PORT_IN_RESET:
3020                pm8001_dbg(pm8001_ha, IO, "IO_PORT_IN_RESET\n");
3021                ts->resp = SAS_TASK_COMPLETE;
3022                ts->stat = SAS_OPEN_REJECT;
3023                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3024                break;
3025        case IO_DS_NON_OPERATIONAL:
3026                pm8001_dbg(pm8001_ha, IO, "IO_DS_NON_OPERATIONAL\n");
3027                ts->resp = SAS_TASK_COMPLETE;
3028                ts->stat = SAS_DEV_NO_RESPONSE;
3029                break;
3030        case IO_DS_IN_RECOVERY:
3031                pm8001_dbg(pm8001_ha, IO, "IO_DS_IN_RECOVERY\n");
3032                ts->resp = SAS_TASK_COMPLETE;
3033                ts->stat = SAS_OPEN_REJECT;
3034                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3035                break;
3036        case IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY:
3037                pm8001_dbg(pm8001_ha, IO,
3038                           "IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY\n");
3039                ts->resp = SAS_TASK_COMPLETE;
3040                ts->stat = SAS_OPEN_REJECT;
3041                ts->open_rej_reason = SAS_OREJ_RSVD_RETRY;
3042                break;
3043        default:
3044                pm8001_dbg(pm8001_ha, DEVIO, "Unknown status 0x%x\n", status);
3045                ts->resp = SAS_TASK_COMPLETE;
3046                ts->stat = SAS_DEV_NO_RESPONSE;
3047                /* not allowed case. Therefore, return failed status */
3048                break;
3049        }
3050        spin_lock_irqsave(&t->task_state_lock, flags);
3051        t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3052        t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3053        t->task_state_flags |= SAS_TASK_STATE_DONE;
3054        if (unlikely((t->task_state_flags & SAS_TASK_STATE_ABORTED))) {
3055                spin_unlock_irqrestore(&t->task_state_lock, flags);
3056                pm8001_dbg(pm8001_ha, FAIL, "task 0x%p done with io_status 0x%x resp 0x%x stat 0x%x but aborted by upper layer!\n",
3057                           t, status, ts->resp, ts->stat);
3058                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3059        } else {
3060                spin_unlock_irqrestore(&t->task_state_lock, flags);
3061                pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3062                mb();/* in order to force CPU ordering */
3063                t->task_done(t);
3064        }
3065}
3066
3067void pm8001_mpi_set_dev_state_resp(struct pm8001_hba_info *pm8001_ha,
3068                void *piomb)
3069{
3070        struct set_dev_state_resp *pPayload =
3071                (struct set_dev_state_resp *)(piomb + 4);
3072        u32 tag = le32_to_cpu(pPayload->tag);
3073        struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3074        struct pm8001_device *pm8001_dev = ccb->device;
3075        u32 status = le32_to_cpu(pPayload->status);
3076        u32 device_id = le32_to_cpu(pPayload->device_id);
3077        u8 pds = le32_to_cpu(pPayload->pds_nds) & PDS_BITS;
3078        u8 nds = le32_to_cpu(pPayload->pds_nds) & NDS_BITS;
3079        pm8001_dbg(pm8001_ha, MSG, "Set device id = 0x%x state from 0x%x to 0x%x status = 0x%x!\n",
3080                   device_id, pds, nds, status);
3081        complete(pm8001_dev->setds_completion);
3082        ccb->task = NULL;
3083        ccb->ccb_tag = 0xFFFFFFFF;
3084        pm8001_tag_free(pm8001_ha, tag);
3085}
3086
3087void pm8001_mpi_set_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3088{
3089        struct get_nvm_data_resp *pPayload =
3090                (struct get_nvm_data_resp *)(piomb + 4);
3091        u32 tag = le32_to_cpu(pPayload->tag);
3092        struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3093        u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3094        complete(pm8001_ha->nvmd_completion);
3095        pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3096        if ((dlen_status & NVMD_STAT) != 0) {
3097                pm8001_dbg(pm8001_ha, FAIL, "Set nvm data error %x\n",
3098                                dlen_status);
3099        }
3100        ccb->task = NULL;
3101        ccb->ccb_tag = 0xFFFFFFFF;
3102        pm8001_tag_free(pm8001_ha, tag);
3103}
3104
3105void
3106pm8001_mpi_get_nvmd_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3107{
3108        struct fw_control_ex    *fw_control_context;
3109        struct get_nvm_data_resp *pPayload =
3110                (struct get_nvm_data_resp *)(piomb + 4);
3111        u32 tag = le32_to_cpu(pPayload->tag);
3112        struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3113        u32 dlen_status = le32_to_cpu(pPayload->dlen_status);
3114        u32 ir_tds_bn_dps_das_nvm =
3115                le32_to_cpu(pPayload->ir_tda_bn_dps_das_nvm);
3116        void *virt_addr = pm8001_ha->memoryMap.region[NVMD].virt_ptr;
3117        fw_control_context = ccb->fw_control_context;
3118
3119        pm8001_dbg(pm8001_ha, MSG, "Get nvm data complete!\n");
3120        if ((dlen_status & NVMD_STAT) != 0) {
3121                pm8001_dbg(pm8001_ha, FAIL, "Get nvm data error %x\n",
3122                                dlen_status);
3123                complete(pm8001_ha->nvmd_completion);
3124                /* We should free tag during failure also, the tag is not being
3125                 * freed by requesting path anywhere.
3126                 */
3127                ccb->task = NULL;
3128                ccb->ccb_tag = 0xFFFFFFFF;
3129                pm8001_tag_free(pm8001_ha, tag);
3130                return;
3131        }
3132        if (ir_tds_bn_dps_das_nvm & IPMode) {
3133                /* indirect mode - IR bit set */
3134                pm8001_dbg(pm8001_ha, MSG, "Get NVMD success, IR=1\n");
3135                if ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == TWI_DEVICE) {
3136                        if (ir_tds_bn_dps_das_nvm == 0x80a80200) {
3137                                memcpy(pm8001_ha->sas_addr,
3138                                      ((u8 *)virt_addr + 4),
3139                                       SAS_ADDR_SIZE);
3140                                pm8001_dbg(pm8001_ha, MSG, "Get SAS address from VPD successfully!\n");
3141                        }
3142                } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == C_SEEPROM)
3143                        || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == VPD_FLASH) ||
3144                        ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == EXPAN_ROM)) {
3145                                ;
3146                } else if (((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == AAP1_RDUMP)
3147                        || ((ir_tds_bn_dps_das_nvm & NVMD_TYPE) == IOP_RDUMP)) {
3148                        ;
3149                } else {
3150                        /* Should not be happened*/
3151                        pm8001_dbg(pm8001_ha, MSG,
3152                                   "(IR=1)Wrong Device type 0x%x\n",
3153                                   ir_tds_bn_dps_das_nvm);
3154                }
3155        } else /* direct mode */{
3156                pm8001_dbg(pm8001_ha, MSG,
3157                           "Get NVMD success, IR=0, dataLen=%d\n",
3158                           (dlen_status & NVMD_LEN) >> 24);
3159        }
3160        /* Though fw_control_context is freed below, usrAddr still needs
3161         * to be updated as this holds the response to the request function
3162         */
3163        memcpy(fw_control_context->usrAddr,
3164                pm8001_ha->memoryMap.region[NVMD].virt_ptr,
3165                fw_control_context->len);
3166        kfree(ccb->fw_control_context);
3167        /* To avoid race condition, complete should be
3168         * called after the message is copied to
3169         * fw_control_context->usrAddr
3170         */
3171        complete(pm8001_ha->nvmd_completion);
3172        pm8001_dbg(pm8001_ha, MSG, "Set nvm data complete!\n");
3173        ccb->task = NULL;
3174        ccb->ccb_tag = 0xFFFFFFFF;
3175        pm8001_tag_free(pm8001_ha, tag);
3176}
3177
3178int pm8001_mpi_local_phy_ctl(struct pm8001_hba_info *pm8001_ha, void *piomb)
3179{
3180        u32 tag;
3181        struct local_phy_ctl_resp *pPayload =
3182                (struct local_phy_ctl_resp *)(piomb + 4);
3183        u32 status = le32_to_cpu(pPayload->status);
3184        u32 phy_id = le32_to_cpu(pPayload->phyop_phyid) & ID_BITS;
3185        u32 phy_op = le32_to_cpu(pPayload->phyop_phyid) & OP_BITS;
3186        tag = le32_to_cpu(pPayload->tag);
3187        if (status != 0) {
3188                pm8001_dbg(pm8001_ha, MSG,
3189                           "%x phy execute %x phy op failed!\n",
3190                           phy_id, phy_op);
3191        } else {
3192                pm8001_dbg(pm8001_ha, MSG,
3193                           "%x phy execute %x phy op success!\n",
3194                           phy_id, phy_op);
3195                pm8001_ha->phy[phy_id].reset_success = true;
3196        }
3197        if (pm8001_ha->phy[phy_id].enable_completion) {
3198                complete(pm8001_ha->phy[phy_id].enable_completion);
3199                pm8001_ha->phy[phy_id].enable_completion = NULL;
3200        }
3201        pm8001_tag_free(pm8001_ha, tag);
3202        return 0;
3203}
3204
3205/**
3206 * pm8001_bytes_dmaed - one of the interface function communication with libsas
3207 * @pm8001_ha: our hba card information
3208 * @i: which phy that received the event.
3209 *
3210 * when HBA driver received the identify done event or initiate FIS received
3211 * event(for SATA), it will invoke this function to notify the sas layer that
3212 * the sas toplogy has formed, please discover the the whole sas domain,
3213 * while receive a broadcast(change) primitive just tell the sas
3214 * layer to discover the changed domain rather than the whole domain.
3215 */
3216void pm8001_bytes_dmaed(struct pm8001_hba_info *pm8001_ha, int i)
3217{
3218        struct pm8001_phy *phy = &pm8001_ha->phy[i];
3219        struct asd_sas_phy *sas_phy = &phy->sas_phy;
3220        if (!phy->phy_attached)
3221                return;
3222
3223        if (sas_phy->phy) {
3224                struct sas_phy *sphy = sas_phy->phy;
3225                sphy->negotiated_linkrate = sas_phy->linkrate;
3226                sphy->minimum_linkrate = phy->minimum_linkrate;
3227                sphy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3228                sphy->maximum_linkrate = phy->maximum_linkrate;
3229                sphy->maximum_linkrate_hw = phy->maximum_linkrate;
3230        }
3231
3232        if (phy->phy_type & PORT_TYPE_SAS) {
3233                struct sas_identify_frame *id;
3234                id = (struct sas_identify_frame *)phy->frame_rcvd;
3235                id->dev_type = phy->identify.device_type;
3236                id->initiator_bits = SAS_PROTOCOL_ALL;
3237                id->target_bits = phy->identify.target_port_protocols;
3238        } else if (phy->phy_type & PORT_TYPE_SATA) {
3239                /*Nothing*/
3240        }
3241        pm8001_dbg(pm8001_ha, MSG, "phy %d byte dmaded.\n", i);
3242
3243        sas_phy->frame_rcvd_size = phy->frame_rcvd_size;
3244        sas_notify_port_event(sas_phy, PORTE_BYTES_DMAED, GFP_ATOMIC);
3245}
3246
3247/* Get the link rate speed  */
3248void pm8001_get_lrate_mode(struct pm8001_phy *phy, u8 link_rate)
3249{
3250        struct sas_phy *sas_phy = phy->sas_phy.phy;
3251
3252        switch (link_rate) {
3253        case PHY_SPEED_120:
3254                phy->sas_phy.linkrate = SAS_LINK_RATE_12_0_GBPS;
3255                phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_12_0_GBPS;
3256                break;
3257        case PHY_SPEED_60:
3258                phy->sas_phy.linkrate = SAS_LINK_RATE_6_0_GBPS;
3259                phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_6_0_GBPS;
3260                break;
3261        case PHY_SPEED_30:
3262                phy->sas_phy.linkrate = SAS_LINK_RATE_3_0_GBPS;
3263                phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_3_0_GBPS;
3264                break;
3265        case PHY_SPEED_15:
3266                phy->sas_phy.linkrate = SAS_LINK_RATE_1_5_GBPS;
3267                phy->sas_phy.phy->negotiated_linkrate = SAS_LINK_RATE_1_5_GBPS;
3268                break;
3269        }
3270        sas_phy->negotiated_linkrate = phy->sas_phy.linkrate;
3271        sas_phy->maximum_linkrate_hw = SAS_LINK_RATE_6_0_GBPS;
3272        sas_phy->minimum_linkrate_hw = SAS_LINK_RATE_1_5_GBPS;
3273        sas_phy->maximum_linkrate = SAS_LINK_RATE_6_0_GBPS;
3274        sas_phy->minimum_linkrate = SAS_LINK_RATE_1_5_GBPS;
3275}
3276
3277/**
3278 * pm8001_get_attached_sas_addr - extract/generate attached SAS address
3279 * @phy: pointer to asd_phy
3280 * @sas_addr: pointer to buffer where the SAS address is to be written
3281 *
3282 * This function extracts the SAS address from an IDENTIFY frame
3283 * received.  If OOB is SATA, then a SAS address is generated from the
3284 * HA tables.
3285 *
3286 * LOCKING: the frame_rcvd_lock needs to be held since this parses the frame
3287 * buffer.
3288 */
3289void pm8001_get_attached_sas_addr(struct pm8001_phy *phy,
3290        u8 *sas_addr)
3291{
3292        if (phy->sas_phy.frame_rcvd[0] == 0x34
3293                && phy->sas_phy.oob_mode == SATA_OOB_MODE) {
3294                struct pm8001_hba_info *pm8001_ha = phy->sas_phy.ha->lldd_ha;
3295                /* FIS device-to-host */
3296                u64 addr = be64_to_cpu(*(__be64 *)pm8001_ha->sas_addr);
3297                addr += phy->sas_phy.id;
3298                *(__be64 *)sas_addr = cpu_to_be64(addr);
3299        } else {
3300                struct sas_identify_frame *idframe =
3301                        (void *) phy->sas_phy.frame_rcvd;
3302                memcpy(sas_addr, idframe->sas_addr, SAS_ADDR_SIZE);
3303        }
3304}
3305
3306/**
3307 * pm8001_hw_event_ack_req- For PM8001,some events need to acknowage to FW.
3308 * @pm8001_ha: our hba card information
3309 * @Qnum: the outbound queue message number.
3310 * @SEA: source of event to ack
3311 * @port_id: port id.
3312 * @phyId: phy id.
3313 * @param0: parameter 0.
3314 * @param1: parameter 1.
3315 */
3316static void pm8001_hw_event_ack_req(struct pm8001_hba_info *pm8001_ha,
3317        u32 Qnum, u32 SEA, u32 port_id, u32 phyId, u32 param0, u32 param1)
3318{
3319        struct hw_event_ack_req  payload;
3320        u32 opc = OPC_INB_SAS_HW_EVENT_ACK;
3321
3322        struct inbound_queue_table *circularQ;
3323
3324        memset((u8 *)&payload, 0, sizeof(payload));
3325        circularQ = &pm8001_ha->inbnd_q_tbl[Qnum];
3326        payload.tag = cpu_to_le32(1);
3327        payload.sea_phyid_portid = cpu_to_le32(((SEA & 0xFFFF) << 8) |
3328                ((phyId & 0x0F) << 4) | (port_id & 0x0F));
3329        payload.param0 = cpu_to_le32(param0);
3330        payload.param1 = cpu_to_le32(param1);
3331        pm8001_mpi_build_cmd(pm8001_ha, circularQ, opc, &payload,
3332                        sizeof(payload), 0);
3333}
3334
3335static int pm8001_chip_phy_ctl_req(struct pm8001_hba_info *pm8001_ha,
3336        u32 phyId, u32 phy_op);
3337
3338/**
3339 * hw_event_sas_phy_up -FW tells me a SAS phy up event.
3340 * @pm8001_ha: our hba card information
3341 * @piomb: IO message buffer
3342 */
3343static void
3344hw_event_sas_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3345{
3346        struct hw_event_resp *pPayload =
3347                (struct hw_event_resp *)(piomb + 4);
3348        u32 lr_evt_status_phyid_portid =
3349                le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3350        u8 link_rate =
3351                (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3352        u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3353        u8 phy_id =
3354                (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3355        u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3356        u8 portstate = (u8)(npip_portstate & 0x0000000F);
3357        struct pm8001_port *port = &pm8001_ha->port[port_id];
3358        struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3359        unsigned long flags;
3360        u8 deviceType = pPayload->sas_identify.dev_type;
3361        port->port_state =  portstate;
3362        phy->phy_state = PHY_STATE_LINK_UP_SPC;
3363        pm8001_dbg(pm8001_ha, MSG,
3364                   "HW_EVENT_SAS_PHY_UP port id = %d, phy id = %d\n",
3365                   port_id, phy_id);
3366
3367        switch (deviceType) {
3368        case SAS_PHY_UNUSED:
3369                pm8001_dbg(pm8001_ha, MSG, "device type no device.\n");
3370                break;
3371        case SAS_END_DEVICE:
3372                pm8001_dbg(pm8001_ha, MSG, "end device.\n");
3373                pm8001_chip_phy_ctl_req(pm8001_ha, phy_id,
3374                        PHY_NOTIFY_ENABLE_SPINUP);
3375                port->port_attached = 1;
3376                pm8001_get_lrate_mode(phy, link_rate);
3377                break;
3378        case SAS_EDGE_EXPANDER_DEVICE:
3379                pm8001_dbg(pm8001_ha, MSG, "expander device.\n");
3380                port->port_attached = 1;
3381                pm8001_get_lrate_mode(phy, link_rate);
3382                break;
3383        case SAS_FANOUT_EXPANDER_DEVICE:
3384                pm8001_dbg(pm8001_ha, MSG, "fanout expander device.\n");
3385                port->port_attached = 1;
3386                pm8001_get_lrate_mode(phy, link_rate);
3387                break;
3388        default:
3389                pm8001_dbg(pm8001_ha, DEVIO, "unknown device type(%x)\n",
3390                           deviceType);
3391                break;
3392        }
3393        phy->phy_type |= PORT_TYPE_SAS;
3394        phy->identify.device_type = deviceType;
3395        phy->phy_attached = 1;
3396        if (phy->identify.device_type == SAS_END_DEVICE)
3397                phy->identify.target_port_protocols = SAS_PROTOCOL_SSP;
3398        else if (phy->identify.device_type != SAS_PHY_UNUSED)
3399                phy->identify.target_port_protocols = SAS_PROTOCOL_SMP;
3400        phy->sas_phy.oob_mode = SAS_OOB_MODE;
3401        sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3402        spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3403        memcpy(phy->frame_rcvd, &pPayload->sas_identify,
3404                sizeof(struct sas_identify_frame)-4);
3405        phy->frame_rcvd_size = sizeof(struct sas_identify_frame) - 4;
3406        pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3407        spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3408        if (pm8001_ha->flags == PM8001F_RUN_TIME)
3409                mdelay(200);/*delay a moment to wait disk to spinup*/
3410        pm8001_bytes_dmaed(pm8001_ha, phy_id);
3411}
3412
3413/**
3414 * hw_event_sata_phy_up -FW tells me a SATA phy up event.
3415 * @pm8001_ha: our hba card information
3416 * @piomb: IO message buffer
3417 */
3418static void
3419hw_event_sata_phy_up(struct pm8001_hba_info *pm8001_ha, void *piomb)
3420{
3421        struct hw_event_resp *pPayload =
3422                (struct hw_event_resp *)(piomb + 4);
3423        u32 lr_evt_status_phyid_portid =
3424                le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3425        u8 link_rate =
3426                (u8)((lr_evt_status_phyid_portid & 0xF0000000) >> 28);
3427        u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3428        u8 phy_id =
3429                (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3430        u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3431        u8 portstate = (u8)(npip_portstate & 0x0000000F);
3432        struct pm8001_port *port = &pm8001_ha->port[port_id];
3433        struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3434        unsigned long flags;
3435        pm8001_dbg(pm8001_ha, DEVIO, "HW_EVENT_SATA_PHY_UP port id = %d, phy id = %d\n",
3436                   port_id, phy_id);
3437        port->port_state =  portstate;
3438        phy->phy_state = PHY_STATE_LINK_UP_SPC;
3439        port->port_attached = 1;
3440        pm8001_get_lrate_mode(phy, link_rate);
3441        phy->phy_type |= PORT_TYPE_SATA;
3442        phy->phy_attached = 1;
3443        phy->sas_phy.oob_mode = SATA_OOB_MODE;
3444        sas_notify_phy_event(&phy->sas_phy, PHYE_OOB_DONE, GFP_ATOMIC);
3445        spin_lock_irqsave(&phy->sas_phy.frame_rcvd_lock, flags);
3446        memcpy(phy->frame_rcvd, ((u8 *)&pPayload->sata_fis - 4),
3447                sizeof(struct dev_to_host_fis));
3448        phy->frame_rcvd_size = sizeof(struct dev_to_host_fis);
3449        phy->identify.target_port_protocols = SAS_PROTOCOL_SATA;
3450        phy->identify.device_type = SAS_SATA_DEV;
3451        pm8001_get_attached_sas_addr(phy, phy->sas_phy.attached_sas_addr);
3452        spin_unlock_irqrestore(&phy->sas_phy.frame_rcvd_lock, flags);
3453        pm8001_bytes_dmaed(pm8001_ha, phy_id);
3454}
3455
3456/**
3457 * hw_event_phy_down -we should notify the libsas the phy is down.
3458 * @pm8001_ha: our hba card information
3459 * @piomb: IO message buffer
3460 */
3461static void
3462hw_event_phy_down(struct pm8001_hba_info *pm8001_ha, void *piomb)
3463{
3464        struct hw_event_resp *pPayload =
3465                (struct hw_event_resp *)(piomb + 4);
3466        u32 lr_evt_status_phyid_portid =
3467                le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3468        u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3469        u8 phy_id =
3470                (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3471        u32 npip_portstate = le32_to_cpu(pPayload->npip_portstate);
3472        u8 portstate = (u8)(npip_portstate & 0x0000000F);
3473        struct pm8001_port *port = &pm8001_ha->port[port_id];
3474        struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3475        port->port_state =  portstate;
3476        phy->phy_type = 0;
3477        phy->identify.device_type = 0;
3478        phy->phy_attached = 0;
3479        memset(&phy->dev_sas_addr, 0, SAS_ADDR_SIZE);
3480        switch (portstate) {
3481        case PORT_VALID:
3482                break;
3483        case PORT_INVALID:
3484                pm8001_dbg(pm8001_ha, MSG, " PortInvalid portID %d\n",
3485                           port_id);
3486                pm8001_dbg(pm8001_ha, MSG,
3487                           " Last phy Down and port invalid\n");
3488                port->port_attached = 0;
3489                pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3490                        port_id, phy_id, 0, 0);
3491                break;
3492        case PORT_IN_RESET:
3493                pm8001_dbg(pm8001_ha, MSG, " Port In Reset portID %d\n",
3494                           port_id);
3495                break;
3496        case PORT_NOT_ESTABLISHED:
3497                pm8001_dbg(pm8001_ha, MSG,
3498                           " phy Down and PORT_NOT_ESTABLISHED\n");
3499                port->port_attached = 0;
3500                break;
3501        case PORT_LOSTCOMM:
3502                pm8001_dbg(pm8001_ha, MSG, " phy Down and PORT_LOSTCOMM\n");
3503                pm8001_dbg(pm8001_ha, MSG,
3504                           " Last phy Down and port invalid\n");
3505                port->port_attached = 0;
3506                pm8001_hw_event_ack_req(pm8001_ha, 0, HW_EVENT_PHY_DOWN,
3507                        port_id, phy_id, 0, 0);
3508                break;
3509        default:
3510                port->port_attached = 0;
3511                pm8001_dbg(pm8001_ha, DEVIO, " phy Down and(default) = %x\n",
3512                           portstate);
3513                break;
3514
3515        }
3516}
3517
3518/**
3519 * pm8001_mpi_reg_resp -process register device ID response.
3520 * @pm8001_ha: our hba card information
3521 * @piomb: IO message buffer
3522 *
3523 * when sas layer find a device it will notify LLDD, then the driver register
3524 * the domain device to FW, this event is the return device ID which the FW
3525 * has assigned, from now, inter-communication with FW is no longer using the
3526 * SAS address, use device ID which FW assigned.
3527 */
3528int pm8001_mpi_reg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3529{
3530        u32 status;
3531        u32 device_id;
3532        u32 htag;
3533        struct pm8001_ccb_info *ccb;
3534        struct pm8001_device *pm8001_dev;
3535        struct dev_reg_resp *registerRespPayload =
3536                (struct dev_reg_resp *)(piomb + 4);
3537
3538        htag = le32_to_cpu(registerRespPayload->tag);
3539        ccb = &pm8001_ha->ccb_info[htag];
3540        pm8001_dev = ccb->device;
3541        status = le32_to_cpu(registerRespPayload->status);
3542        device_id = le32_to_cpu(registerRespPayload->device_id);
3543        pm8001_dbg(pm8001_ha, MSG, " register device is status = %d\n",
3544                   status);
3545        switch (status) {
3546        case DEVREG_SUCCESS:
3547                pm8001_dbg(pm8001_ha, MSG, "DEVREG_SUCCESS\n");
3548                pm8001_dev->device_id = device_id;
3549                break;
3550        case DEVREG_FAILURE_OUT_OF_RESOURCE:
3551                pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_OUT_OF_RESOURCE\n");
3552                break;
3553        case DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED:
3554                pm8001_dbg(pm8001_ha, MSG,
3555                           "DEVREG_FAILURE_DEVICE_ALREADY_REGISTERED\n");
3556                break;
3557        case DEVREG_FAILURE_INVALID_PHY_ID:
3558                pm8001_dbg(pm8001_ha, MSG, "DEVREG_FAILURE_INVALID_PHY_ID\n");
3559                break;
3560        case DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED:
3561                pm8001_dbg(pm8001_ha, MSG,
3562                           "DEVREG_FAILURE_PHY_ID_ALREADY_REGISTERED\n");
3563                break;
3564        case DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE:
3565                pm8001_dbg(pm8001_ha, MSG,
3566                           "DEVREG_FAILURE_PORT_ID_OUT_OF_RANGE\n");
3567                break;
3568        case DEVREG_FAILURE_PORT_NOT_VALID_STATE:
3569                pm8001_dbg(pm8001_ha, MSG,
3570                           "DEVREG_FAILURE_PORT_NOT_VALID_STATE\n");
3571                break;
3572        case DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID:
3573                pm8001_dbg(pm8001_ha, MSG,
3574                           "DEVREG_FAILURE_DEVICE_TYPE_NOT_VALID\n");
3575                break;
3576        default:
3577                pm8001_dbg(pm8001_ha, MSG,
3578                           "DEVREG_FAILURE_DEVICE_TYPE_NOT_SUPPORTED\n");
3579                break;
3580        }
3581        complete(pm8001_dev->dcompletion);
3582        ccb->task = NULL;
3583        ccb->ccb_tag = 0xFFFFFFFF;
3584        pm8001_tag_free(pm8001_ha, htag);
3585        return 0;
3586}
3587
3588int pm8001_mpi_dereg_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3589{
3590        u32 status;
3591        u32 device_id;
3592        struct dev_reg_resp *registerRespPayload =
3593                (struct dev_reg_resp *)(piomb + 4);
3594
3595        status = le32_to_cpu(registerRespPayload->status);
3596        device_id = le32_to_cpu(registerRespPayload->device_id);
3597        if (status != 0)
3598                pm8001_dbg(pm8001_ha, MSG,
3599                           " deregister device failed ,status = %x, device_id = %x\n",
3600                           status, device_id);
3601        return 0;
3602}
3603
3604/**
3605 * pm8001_mpi_fw_flash_update_resp - Response from FW for flash update command.
3606 * @pm8001_ha: our hba card information
3607 * @piomb: IO message buffer
3608 */
3609int pm8001_mpi_fw_flash_update_resp(struct pm8001_hba_info *pm8001_ha,
3610                void *piomb)
3611{
3612        u32 status;
3613        struct fw_flash_Update_resp *ppayload =
3614                (struct fw_flash_Update_resp *)(piomb + 4);
3615        u32 tag = le32_to_cpu(ppayload->tag);
3616        struct pm8001_ccb_info *ccb = &pm8001_ha->ccb_info[tag];
3617        status = le32_to_cpu(ppayload->status);
3618        switch (status) {
3619        case FLASH_UPDATE_COMPLETE_PENDING_REBOOT:
3620                pm8001_dbg(pm8001_ha, MSG,
3621                           ": FLASH_UPDATE_COMPLETE_PENDING_REBOOT\n");
3622                break;
3623        case FLASH_UPDATE_IN_PROGRESS:
3624                pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_IN_PROGRESS\n");
3625                break;
3626        case FLASH_UPDATE_HDR_ERR:
3627                pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HDR_ERR\n");
3628                break;
3629        case FLASH_UPDATE_OFFSET_ERR:
3630                pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_OFFSET_ERR\n");
3631                break;
3632        case FLASH_UPDATE_CRC_ERR:
3633                pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_CRC_ERR\n");
3634                break;
3635        case FLASH_UPDATE_LENGTH_ERR:
3636                pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_LENGTH_ERR\n");
3637                break;
3638        case FLASH_UPDATE_HW_ERR:
3639                pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_HW_ERR\n");
3640                break;
3641        case FLASH_UPDATE_DNLD_NOT_SUPPORTED:
3642                pm8001_dbg(pm8001_ha, MSG,
3643                           ": FLASH_UPDATE_DNLD_NOT_SUPPORTED\n");
3644                break;
3645        case FLASH_UPDATE_DISABLED:
3646                pm8001_dbg(pm8001_ha, MSG, ": FLASH_UPDATE_DISABLED\n");
3647                break;
3648        default:
3649                pm8001_dbg(pm8001_ha, DEVIO, "No matched status = %d\n",
3650                           status);
3651                break;
3652        }
3653        kfree(ccb->fw_control_context);
3654        ccb->task = NULL;
3655        ccb->ccb_tag = 0xFFFFFFFF;
3656        pm8001_tag_free(pm8001_ha, tag);
3657        complete(pm8001_ha->nvmd_completion);
3658        return 0;
3659}
3660
3661int pm8001_mpi_general_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3662{
3663        u32 status;
3664        int i;
3665        struct general_event_resp *pPayload =
3666                (struct general_event_resp *)(piomb + 4);
3667        status = le32_to_cpu(pPayload->status);
3668        pm8001_dbg(pm8001_ha, MSG, " status = 0x%x\n", status);
3669        for (i = 0; i < GENERAL_EVENT_PAYLOAD; i++)
3670                pm8001_dbg(pm8001_ha, MSG, "inb_IOMB_payload[0x%x] 0x%x,\n",
3671                           i,
3672                           pPayload->inb_IOMB_payload[i]);
3673        return 0;
3674}
3675
3676int pm8001_mpi_task_abort_resp(struct pm8001_hba_info *pm8001_ha, void *piomb)
3677{
3678        struct sas_task *t;
3679        struct pm8001_ccb_info *ccb;
3680        unsigned long flags;
3681        u32 status ;
3682        u32 tag, scp;
3683        struct task_status_struct *ts;
3684        struct pm8001_device *pm8001_dev;
3685
3686        struct task_abort_resp *pPayload =
3687                (struct task_abort_resp *)(piomb + 4);
3688
3689        status = le32_to_cpu(pPayload->status);
3690        tag = le32_to_cpu(pPayload->tag);
3691        if (!tag) {
3692                pm8001_dbg(pm8001_ha, FAIL, " TAG NULL. RETURNING !!!\n");
3693                return -1;
3694        }
3695
3696        scp = le32_to_cpu(pPayload->scp);
3697        ccb = &pm8001_ha->ccb_info[tag];
3698        t = ccb->task;
3699        pm8001_dev = ccb->device; /* retrieve device */
3700
3701        if (!t) {
3702                pm8001_dbg(pm8001_ha, FAIL, " TASK NULL. RETURNING !!!\n");
3703                return -1;
3704        }
3705        ts = &t->task_status;
3706        if (status != 0)
3707                pm8001_dbg(pm8001_ha, FAIL, "task abort failed status 0x%x ,tag = 0x%x, scp= 0x%x\n",
3708                           status, tag, scp);
3709        switch (status) {
3710        case IO_SUCCESS:
3711                pm8001_dbg(pm8001_ha, EH, "IO_SUCCESS\n");
3712                ts->resp = SAS_TASK_COMPLETE;
3713                ts->stat = SAS_SAM_STAT_GOOD;
3714                break;
3715        case IO_NOT_VALID:
3716                pm8001_dbg(pm8001_ha, EH, "IO_NOT_VALID\n");
3717                ts->resp = TMF_RESP_FUNC_FAILED;
3718                break;
3719        }
3720        spin_lock_irqsave(&t->task_state_lock, flags);
3721        t->task_state_flags &= ~SAS_TASK_STATE_PENDING;
3722        t->task_state_flags &= ~SAS_TASK_AT_INITIATOR;
3723        t->task_state_flags |= SAS_TASK_STATE_DONE;
3724        spin_unlock_irqrestore(&t->task_state_lock, flags);
3725        pm8001_ccb_task_free(pm8001_ha, t, ccb, tag);
3726        mb();
3727
3728        if (pm8001_dev->id & NCQ_ABORT_ALL_FLAG) {
3729                pm8001_tag_free(pm8001_ha, tag);
3730                sas_free_task(t);
3731                /* clear the flag */
3732                pm8001_dev->id &= 0xBFFFFFFF;
3733        } else
3734                t->task_done(t);
3735
3736        return 0;
3737}
3738
3739/**
3740 * mpi_hw_event -The hw event has come.
3741 * @pm8001_ha: our hba card information
3742 * @piomb: IO message buffer
3743 */
3744static int mpi_hw_event(struct pm8001_hba_info *pm8001_ha, void *piomb)
3745{
3746        unsigned long flags;
3747        struct hw_event_resp *pPayload =
3748                (struct hw_event_resp *)(piomb + 4);
3749        u32 lr_evt_status_phyid_portid =
3750                le32_to_cpu(pPayload->lr_evt_status_phyid_portid);
3751        u8 port_id = (u8)(lr_evt_status_phyid_portid & 0x0000000F);
3752        u8 phy_id =
3753                (u8)((lr_evt_status_phyid_portid & 0x000000F0) >> 4);
3754        u16 eventType =
3755                (u16)((lr_evt_status_phyid_portid & 0x00FFFF00) >> 8);
3756        u8 status =
3757                (u8)((lr_evt_status_phyid_portid & 0x0F000000) >> 24);
3758        struct sas_ha_struct *sas_ha = pm8001_ha->sas;
3759        struct pm8001_phy *phy = &pm8001_ha->phy[phy_id];
3760        struct asd_sas_phy *sas_phy = sas_ha->sas_phy[phy_id];
3761        pm8001_dbg(pm8001_ha, DEVIO,
3762                   "SPC HW event for portid:%d, phyid:%d, event:%x, status:%x\n",
3763                   port_id, phy_id, eventType, status);
3764        switch (eventType) {
3765        case HW_EVENT_PHY_START_STATUS:
3766                pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS status = %x\n",
3767                           status);
3768                if (status == 0)
3769                        phy->phy_state = 1;
3770
3771                if (pm8001_ha->flags == PM8001F_RUN_TIME &&
3772                                phy->enable_completion != NULL) {
3773                        complete(phy->enable_completion);
3774                        phy->enable_completion = NULL;
3775                }
3776                break;
3777        case HW_EVENT_SAS_PHY_UP:
3778                pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_START_STATUS\n");
3779                hw_event_sas_phy_up(pm8001_ha, piomb);
3780                break;
3781        case HW_EVENT_SATA_PHY_UP:
3782                pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_PHY_UP\n");
3783                hw_event_sata_phy_up(pm8001_ha, piomb);
3784                break;
3785        case HW_EVENT_PHY_STOP_STATUS:
3786                pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_STOP_STATUS status = %x\n",
3787                           status);
3788                if (status == 0)
3789                        phy->phy_state = 0;
3790                break;
3791        case HW_EVENT_SATA_SPINUP_HOLD:
3792                pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_SATA_SPINUP_HOLD\n");
3793                sas_notify_phy_event(&phy->sas_phy, PHYE_SPINUP_HOLD,
3794                        GFP_ATOMIC);
3795                break;
3796        case HW_EVENT_PHY_DOWN:
3797                pm8001_dbg(pm8001_ha, MSG, "HW_EVENT_PHY_DOWN\n");
3798                sas_notify_phy_event(&phy->sas_phy, PHYE_LOSS_OF_SIGNAL,
3799                        GFP_ATOMIC);
3800