linux/drivers/scsi/mpt3sas/mpt3sas_base.c
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   1/*
   2 * This is the Fusion MPT base driver providing common API layer interface
   3 * for access to MPT (Message Passing Technology) firmware.
   4 *
   5 * This code is based on drivers/scsi/mpt3sas/mpt3sas_base.c
   6 * Copyright (C) 2012-2014  LSI Corporation
   7 * Copyright (C) 2013-2014 Avago Technologies
   8 *  (mailto: MPT-FusionLinux.pdl@avagotech.com)
   9 *
  10 * This program is free software; you can redistribute it and/or
  11 * modify it under the terms of the GNU General Public License
  12 * as published by the Free Software Foundation; either version 2
  13 * of the License, or (at your option) any later version.
  14 *
  15 * This program is distributed in the hope that it will be useful,
  16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18 * GNU General Public License for more details.
  19 *
  20 * NO WARRANTY
  21 * THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR
  22 * CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT
  23 * LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT,
  24 * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is
  25 * solely responsible for determining the appropriateness of using and
  26 * distributing the Program and assumes all risks associated with its
  27 * exercise of rights under this Agreement, including but not limited to
  28 * the risks and costs of program errors, damage to or loss of data,
  29 * programs or equipment, and unavailability or interruption of operations.
  30
  31 * DISCLAIMER OF LIABILITY
  32 * NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY
  33 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  34 * DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND
  35 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
  36 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
  37 * USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED
  38 * HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES
  39
  40 * You should have received a copy of the GNU General Public License
  41 * along with this program; if not, write to the Free Software
  42 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301,
  43 * USA.
  44 */
  45
  46#include <linux/kernel.h>
  47#include <linux/module.h>
  48#include <linux/errno.h>
  49#include <linux/init.h>
  50#include <linux/slab.h>
  51#include <linux/types.h>
  52#include <linux/pci.h>
  53#include <linux/kdev_t.h>
  54#include <linux/blkdev.h>
  55#include <linux/delay.h>
  56#include <linux/interrupt.h>
  57#include <linux/dma-mapping.h>
  58#include <linux/io.h>
  59#include <linux/time.h>
  60#include <linux/ktime.h>
  61#include <linux/kthread.h>
  62#include <asm/page.h>        /* To get host page size per arch */
  63#include <linux/aer.h>
  64
  65
  66#include "mpt3sas_base.h"
  67
  68static MPT_CALLBACK     mpt_callbacks[MPT_MAX_CALLBACKS];
  69
  70
  71#define FAULT_POLLING_INTERVAL 1000 /* in milliseconds */
  72
  73 /* maximum controller queue depth */
  74#define MAX_HBA_QUEUE_DEPTH     30000
  75#define MAX_CHAIN_DEPTH         100000
  76static int max_queue_depth = -1;
  77module_param(max_queue_depth, int, 0444);
  78MODULE_PARM_DESC(max_queue_depth, " max controller queue depth ");
  79
  80static int max_sgl_entries = -1;
  81module_param(max_sgl_entries, int, 0444);
  82MODULE_PARM_DESC(max_sgl_entries, " max sg entries ");
  83
  84static int msix_disable = -1;
  85module_param(msix_disable, int, 0444);
  86MODULE_PARM_DESC(msix_disable, " disable msix routed interrupts (default=0)");
  87
  88static int smp_affinity_enable = 1;
  89module_param(smp_affinity_enable, int, 0444);
  90MODULE_PARM_DESC(smp_affinity_enable, "SMP affinity feature enable/disable Default: enable(1)");
  91
  92static int max_msix_vectors = -1;
  93module_param(max_msix_vectors, int, 0444);
  94MODULE_PARM_DESC(max_msix_vectors,
  95        " max msix vectors");
  96
  97static int irqpoll_weight = -1;
  98module_param(irqpoll_weight, int, 0444);
  99MODULE_PARM_DESC(irqpoll_weight,
 100        "irq poll weight (default= one fourth of HBA queue depth)");
 101
 102static int mpt3sas_fwfault_debug;
 103MODULE_PARM_DESC(mpt3sas_fwfault_debug,
 104        " enable detection of firmware fault and halt firmware - (default=0)");
 105
 106static int perf_mode = -1;
 107module_param(perf_mode, int, 0444);
 108MODULE_PARM_DESC(perf_mode,
 109        "Performance mode (only for Aero/Sea Generation), options:\n\t\t"
 110        "0 - balanced: high iops mode is enabled &\n\t\t"
 111        "interrupt coalescing is enabled only on high iops queues,\n\t\t"
 112        "1 - iops: high iops mode is disabled &\n\t\t"
 113        "interrupt coalescing is enabled on all queues,\n\t\t"
 114        "2 - latency: high iops mode is disabled &\n\t\t"
 115        "interrupt coalescing is enabled on all queues with timeout value 0xA,\n"
 116        "\t\tdefault - default perf_mode is 'balanced'"
 117        );
 118
 119enum mpt3sas_perf_mode {
 120        MPT_PERF_MODE_DEFAULT   = -1,
 121        MPT_PERF_MODE_BALANCED  = 0,
 122        MPT_PERF_MODE_IOPS      = 1,
 123        MPT_PERF_MODE_LATENCY   = 2,
 124};
 125
 126static int
 127_base_wait_on_iocstate(struct MPT3SAS_ADAPTER *ioc,
 128                u32 ioc_state, int timeout);
 129static int
 130_base_get_ioc_facts(struct MPT3SAS_ADAPTER *ioc);
 131static void
 132_base_clear_outstanding_commands(struct MPT3SAS_ADAPTER *ioc);
 133
 134/**
 135 * mpt3sas_base_check_cmd_timeout - Function
 136 *              to check timeout and command termination due
 137 *              to Host reset.
 138 *
 139 * @ioc:        per adapter object.
 140 * @status:     Status of issued command.
 141 * @mpi_request:mf request pointer.
 142 * @sz:         size of buffer.
 143 *
 144 * Return: 1/0 Reset to be done or Not
 145 */
 146u8
 147mpt3sas_base_check_cmd_timeout(struct MPT3SAS_ADAPTER *ioc,
 148                u8 status, void *mpi_request, int sz)
 149{
 150        u8 issue_reset = 0;
 151
 152        if (!(status & MPT3_CMD_RESET))
 153                issue_reset = 1;
 154
 155        ioc_err(ioc, "Command %s\n",
 156                issue_reset == 0 ? "terminated due to Host Reset" : "Timeout");
 157        _debug_dump_mf(mpi_request, sz);
 158
 159        return issue_reset;
 160}
 161
 162/**
 163 * _scsih_set_fwfault_debug - global setting of ioc->fwfault_debug.
 164 * @val: ?
 165 * @kp: ?
 166 *
 167 * Return: ?
 168 */
 169static int
 170_scsih_set_fwfault_debug(const char *val, const struct kernel_param *kp)
 171{
 172        int ret = param_set_int(val, kp);
 173        struct MPT3SAS_ADAPTER *ioc;
 174
 175        if (ret)
 176                return ret;
 177
 178        /* global ioc spinlock to protect controller list on list operations */
 179        pr_info("setting fwfault_debug(%d)\n", mpt3sas_fwfault_debug);
 180        spin_lock(&gioc_lock);
 181        list_for_each_entry(ioc, &mpt3sas_ioc_list, list)
 182                ioc->fwfault_debug = mpt3sas_fwfault_debug;
 183        spin_unlock(&gioc_lock);
 184        return 0;
 185}
 186module_param_call(mpt3sas_fwfault_debug, _scsih_set_fwfault_debug,
 187        param_get_int, &mpt3sas_fwfault_debug, 0644);
 188
 189/**
 190 * _base_readl_aero - retry readl for max three times.
 191 * @addr: MPT Fusion system interface register address
 192 *
 193 * Retry the readl() for max three times if it gets zero value
 194 * while reading the system interface register.
 195 */
 196static inline u32
 197_base_readl_aero(const volatile void __iomem *addr)
 198{
 199        u32 i = 0, ret_val;
 200
 201        do {
 202                ret_val = readl(addr);
 203                i++;
 204        } while (ret_val == 0 && i < 3);
 205
 206        return ret_val;
 207}
 208
 209static inline u32
 210_base_readl(const volatile void __iomem *addr)
 211{
 212        return readl(addr);
 213}
 214
 215/**
 216 * _base_clone_reply_to_sys_mem - copies reply to reply free iomem
 217 *                                in BAR0 space.
 218 *
 219 * @ioc: per adapter object
 220 * @reply: reply message frame(lower 32bit addr)
 221 * @index: System request message index.
 222 */
 223static void
 224_base_clone_reply_to_sys_mem(struct MPT3SAS_ADAPTER *ioc, u32 reply,
 225                u32 index)
 226{
 227        /*
 228         * 256 is offset within sys register.
 229         * 256 offset MPI frame starts. Max MPI frame supported is 32.
 230         * 32 * 128 = 4K. From here, Clone of reply free for mcpu starts
 231         */
 232        u16 cmd_credit = ioc->facts.RequestCredit + 1;
 233        void __iomem *reply_free_iomem = (void __iomem *)ioc->chip +
 234                        MPI_FRAME_START_OFFSET +
 235                        (cmd_credit * ioc->request_sz) + (index * sizeof(u32));
 236
 237        writel(reply, reply_free_iomem);
 238}
 239
 240/**
 241 * _base_clone_mpi_to_sys_mem - Writes/copies MPI frames
 242 *                              to system/BAR0 region.
 243 *
 244 * @dst_iomem: Pointer to the destination location in BAR0 space.
 245 * @src: Pointer to the Source data.
 246 * @size: Size of data to be copied.
 247 */
 248static void
 249_base_clone_mpi_to_sys_mem(void *dst_iomem, void *src, u32 size)
 250{
 251        int i;
 252        u32 *src_virt_mem = (u32 *)src;
 253
 254        for (i = 0; i < size/4; i++)
 255                writel((u32)src_virt_mem[i],
 256                                (void __iomem *)dst_iomem + (i * 4));
 257}
 258
 259/**
 260 * _base_clone_to_sys_mem - Writes/copies data to system/BAR0 region
 261 *
 262 * @dst_iomem: Pointer to the destination location in BAR0 space.
 263 * @src: Pointer to the Source data.
 264 * @size: Size of data to be copied.
 265 */
 266static void
 267_base_clone_to_sys_mem(void __iomem *dst_iomem, void *src, u32 size)
 268{
 269        int i;
 270        u32 *src_virt_mem = (u32 *)(src);
 271
 272        for (i = 0; i < size/4; i++)
 273                writel((u32)src_virt_mem[i],
 274                        (void __iomem *)dst_iomem + (i * 4));
 275}
 276
 277/**
 278 * _base_get_chain - Calculates and Returns virtual chain address
 279 *                       for the provided smid in BAR0 space.
 280 *
 281 * @ioc: per adapter object
 282 * @smid: system request message index
 283 * @sge_chain_count: Scatter gather chain count.
 284 *
 285 * Return: the chain address.
 286 */
 287static inline void __iomem*
 288_base_get_chain(struct MPT3SAS_ADAPTER *ioc, u16 smid,
 289                u8 sge_chain_count)
 290{
 291        void __iomem *base_chain, *chain_virt;
 292        u16 cmd_credit = ioc->facts.RequestCredit + 1;
 293
 294        base_chain  = (void __iomem *)ioc->chip + MPI_FRAME_START_OFFSET +
 295                (cmd_credit * ioc->request_sz) +
 296                REPLY_FREE_POOL_SIZE;
 297        chain_virt = base_chain + (smid * ioc->facts.MaxChainDepth *
 298                        ioc->request_sz) + (sge_chain_count * ioc->request_sz);
 299        return chain_virt;
 300}
 301
 302/**
 303 * _base_get_chain_phys - Calculates and Returns physical address
 304 *                      in BAR0 for scatter gather chains, for
 305 *                      the provided smid.
 306 *
 307 * @ioc: per adapter object
 308 * @smid: system request message index
 309 * @sge_chain_count: Scatter gather chain count.
 310 *
 311 * Return: Physical chain address.
 312 */
 313static inline phys_addr_t
 314_base_get_chain_phys(struct MPT3SAS_ADAPTER *ioc, u16 smid,
 315                u8 sge_chain_count)
 316{
 317        phys_addr_t base_chain_phys, chain_phys;
 318        u16 cmd_credit = ioc->facts.RequestCredit + 1;
 319
 320        base_chain_phys  = ioc->chip_phys + MPI_FRAME_START_OFFSET +
 321                (cmd_credit * ioc->request_sz) +
 322                REPLY_FREE_POOL_SIZE;
 323        chain_phys = base_chain_phys + (smid * ioc->facts.MaxChainDepth *
 324                        ioc->request_sz) + (sge_chain_count * ioc->request_sz);
 325        return chain_phys;
 326}
 327
 328/**
 329 * _base_get_buffer_bar0 - Calculates and Returns BAR0 mapped Host
 330 *                      buffer address for the provided smid.
 331 *                      (Each smid can have 64K starts from 17024)
 332 *
 333 * @ioc: per adapter object
 334 * @smid: system request message index
 335 *
 336 * Return: Pointer to buffer location in BAR0.
 337 */
 338
 339static void __iomem *
 340_base_get_buffer_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 341{
 342        u16 cmd_credit = ioc->facts.RequestCredit + 1;
 343        // Added extra 1 to reach end of chain.
 344        void __iomem *chain_end = _base_get_chain(ioc,
 345                        cmd_credit + 1,
 346                        ioc->facts.MaxChainDepth);
 347        return chain_end + (smid * 64 * 1024);
 348}
 349
 350/**
 351 * _base_get_buffer_phys_bar0 - Calculates and Returns BAR0 mapped
 352 *              Host buffer Physical address for the provided smid.
 353 *              (Each smid can have 64K starts from 17024)
 354 *
 355 * @ioc: per adapter object
 356 * @smid: system request message index
 357 *
 358 * Return: Pointer to buffer location in BAR0.
 359 */
 360static phys_addr_t
 361_base_get_buffer_phys_bar0(struct MPT3SAS_ADAPTER *ioc, u16 smid)
 362{
 363        u16 cmd_credit = ioc->facts.RequestCredit + 1;
 364        phys_addr_t chain_end_phys = _base_get_chain_phys(ioc,
 365                        cmd_credit + 1,
 366                        ioc->facts.MaxChainDepth);
 367        return chain_end_phys + (smid * 64 * 1024);
 368}
 369
 370/**
 371 * _base_get_chain_buffer_dma_to_chain_buffer - Iterates chain
 372 *                      lookup list and Provides chain_buffer
 373 *                      address for the matching dma address.
 374 *                      (Each smid can have 64K starts from 17024)
 375 *
 376 * @ioc: per adapter object
 377 * @chain_buffer_dma: Chain buffer dma address.
 378 *
 379 * Return: Pointer to chain buffer. Or Null on Failure.
 380 */
 381static void *
 382_base_get_chain_buffer_dma_to_chain_buffer(struct MPT3SAS_ADAPTER *ioc,
 383                dma_addr_t chain_buffer_dma)
 384{
 385        u16 index, j;
 386        struct chain_tracker *ct;
 387
 388        for (index = 0; index < ioc->scsiio_depth; index++) {
 389                for (j = 0; j < ioc->chains_needed_per_io; j++) {
 390                        ct = &ioc->chain_lookup[index].chains_per_smid[j];
 391                        if (ct && ct->chain_buffer_dma == chain_buffer_dma)
 392                                return ct->chain_buffer;
 393                }
 394        }
 395        ioc_info(ioc, "Provided chain_buffer_dma address is not in the lookup list\n");
 396        return NULL;
 397}
 398
 399/**
 400 * _clone_sg_entries -  MPI EP's scsiio and config requests
 401 *                      are handled here. Base function for
 402 *                      double buffering, before submitting
 403 *                      the requests.
 404 *
 405 * @ioc: per adapter object.
 406 * @mpi_request: mf request pointer.
 407 * @smid: system request message index.
 408 */
 409static void _clone_sg_entries(struct MPT3SAS_ADAPTER *ioc,
 410                void *mpi_request, u16 smid)
 411{
 412        Mpi2SGESimple32_t *sgel, *sgel_next;
 413        u32  sgl_flags, sge_chain_count = 0;
 414        bool is_write = false;
 415        u16 i = 0;
 416        void __iomem *buffer_iomem;
 417        phys_addr_t buffer_iomem_phys;
 418        void __iomem *buff_ptr;
 419        phys_addr_t buff_ptr_phys;
 420        void __iomem *dst_chain_addr[MCPU_MAX_CHAINS_PER_IO];
 421        void *src_chain_addr[MCPU_MAX_CHAINS_PER_IO];
 422        phys_addr_t dst_addr_phys;
 423        MPI2RequestHeader_t *request_hdr;
 424        struct scsi_cmnd *scmd;
 425        struct scatterlist *sg_scmd = NULL;
 426        int is_scsiio_req = 0;
 427
 428        request_hdr = (MPI2RequestHeader_t *) mpi_request;
 429
 430        if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST) {
 431                Mpi25SCSIIORequest_t *scsiio_request =
 432                        (Mpi25SCSIIORequest_t *)mpi_request;
 433                sgel = (Mpi2SGESimple32_t *) &scsiio_request->SGL;
 434                is_scsiio_req = 1;
 435        } else if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
 436                Mpi2ConfigRequest_t  *config_req =
 437                        (Mpi2ConfigRequest_t *)mpi_request;
 438                sgel = (Mpi2SGESimple32_t *) &config_req->PageBufferSGE;
 439        } else
 440                return;
 441
 442        /* From smid we can get scsi_cmd, once we have sg_scmd,
 443         * we just need to get sg_virt and sg_next to get virtual
 444         * address associated with sgel->Address.
 445         */
 446
 447        if (is_scsiio_req) {
 448                /* Get scsi_cmd using smid */
 449                scmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
 450                if (scmd == NULL) {
 451                        ioc_err(ioc, "scmd is NULL\n");
 452                        return;
 453                }
 454
 455                /* Get sg_scmd from scmd provided */
 456                sg_scmd = scsi_sglist(scmd);
 457        }
 458
 459        /*
 460         * 0 - 255      System register
 461         * 256 - 4352   MPI Frame. (This is based on maxCredit 32)
 462         * 4352 - 4864  Reply_free pool (512 byte is reserved
 463         *              considering maxCredit 32. Reply need extra
 464         *              room, for mCPU case kept four times of
 465         *              maxCredit).
 466         * 4864 - 17152 SGE chain element. (32cmd * 3 chain of
 467         *              128 byte size = 12288)
 468         * 17152 - x    Host buffer mapped with smid.
 469         *              (Each smid can have 64K Max IO.)
 470         * BAR0+Last 1K MSIX Addr and Data
 471         * Total size in use 2113664 bytes of 4MB BAR0
 472         */
 473
 474        buffer_iomem = _base_get_buffer_bar0(ioc, smid);
 475        buffer_iomem_phys = _base_get_buffer_phys_bar0(ioc, smid);
 476
 477        buff_ptr = buffer_iomem;
 478        buff_ptr_phys = buffer_iomem_phys;
 479        WARN_ON(buff_ptr_phys > U32_MAX);
 480
 481        if (le32_to_cpu(sgel->FlagsLength) &
 482                        (MPI2_SGE_FLAGS_HOST_TO_IOC << MPI2_SGE_FLAGS_SHIFT))
 483                is_write = true;
 484
 485        for (i = 0; i < MPT_MIN_PHYS_SEGMENTS + ioc->facts.MaxChainDepth; i++) {
 486
 487                sgl_flags =
 488                    (le32_to_cpu(sgel->FlagsLength) >> MPI2_SGE_FLAGS_SHIFT);
 489
 490                switch (sgl_flags & MPI2_SGE_FLAGS_ELEMENT_MASK) {
 491                case MPI2_SGE_FLAGS_CHAIN_ELEMENT:
 492                        /*
 493                         * Helper function which on passing
 494                         * chain_buffer_dma returns chain_buffer. Get
 495                         * the virtual address for sgel->Address
 496                         */
 497                        sgel_next =
 498                                _base_get_chain_buffer_dma_to_chain_buffer(ioc,
 499                                                le32_to_cpu(sgel->Address));
 500                        if (sgel_next == NULL)
 501                                return;
 502                        /*
 503                         * This is coping 128 byte chain
 504                         * frame (not a host buffer)
 505                         */
 506                        dst_chain_addr[sge_chain_count] =
 507                                _base_get_chain(ioc,
 508                                        smid, sge_chain_count);
 509                        src_chain_addr[sge_chain_count] =
 510                                                (void *) sgel_next;
 511                        dst_addr_phys = _base_get_chain_phys(ioc,
 512                                                smid, sge_chain_count);
 513                        WARN_ON(dst_addr_phys > U32_MAX);
 514                        sgel->Address =
 515                                cpu_to_le32(lower_32_bits(dst_addr_phys));
 516                        sgel = sgel_next;
 517                        sge_chain_count++;
 518                        break;
 519                case MPI2_SGE_FLAGS_SIMPLE_ELEMENT:
 520                        if (is_write) {
 521                                if (is_scsiio_req) {
 522                                        _base_clone_to_sys_mem(buff_ptr,
 523                                            sg_virt(sg_scmd),
 524                                            (le32_to_cpu(sgel->FlagsLength) &
 525                                            0x00ffffff));
 526                                        /*
 527                                         * FIXME: this relies on a a zero
 528                                         * PCI mem_offset.
 529                                         */
 530                                        sgel->Address =
 531                                            cpu_to_le32((u32)buff_ptr_phys);
 532                                } else {
 533                                        _base_clone_to_sys_mem(buff_ptr,
 534                                            ioc->config_vaddr,
 535                                            (le32_to_cpu(sgel->FlagsLength) &
 536                                            0x00ffffff));
 537                                        sgel->Address =
 538                                            cpu_to_le32((u32)buff_ptr_phys);
 539                                }
 540                        }
 541                        buff_ptr += (le32_to_cpu(sgel->FlagsLength) &
 542                            0x00ffffff);
 543                        buff_ptr_phys += (le32_to_cpu(sgel->FlagsLength) &
 544                            0x00ffffff);
 545                        if ((le32_to_cpu(sgel->FlagsLength) &
 546                            (MPI2_SGE_FLAGS_END_OF_BUFFER
 547                                        << MPI2_SGE_FLAGS_SHIFT)))
 548                                goto eob_clone_chain;
 549                        else {
 550                                /*
 551                                 * Every single element in MPT will have
 552                                 * associated sg_next. Better to sanity that
 553                                 * sg_next is not NULL, but it will be a bug
 554                                 * if it is null.
 555                                 */
 556                                if (is_scsiio_req) {
 557                                        sg_scmd = sg_next(sg_scmd);
 558                                        if (sg_scmd)
 559                                                sgel++;
 560                                        else
 561                                                goto eob_clone_chain;
 562                                }
 563                        }
 564                        break;
 565                }
 566        }
 567
 568eob_clone_chain:
 569        for (i = 0; i < sge_chain_count; i++) {
 570                if (is_scsiio_req)
 571                        _base_clone_to_sys_mem(dst_chain_addr[i],
 572                                src_chain_addr[i], ioc->request_sz);
 573        }
 574}
 575
 576/**
 577 *  mpt3sas_remove_dead_ioc_func - kthread context to remove dead ioc
 578 * @arg: input argument, used to derive ioc
 579 *
 580 * Return:
 581 * 0 if controller is removed from pci subsystem.
 582 * -1 for other case.
 583 */
 584static int mpt3sas_remove_dead_ioc_func(void *arg)
 585{
 586        struct MPT3SAS_ADAPTER *ioc = (struct MPT3SAS_ADAPTER *)arg;
 587        struct pci_dev *pdev;
 588
 589        if (!ioc)
 590                return -1;
 591
 592        pdev = ioc->pdev;
 593        if (!pdev)
 594                return -1;
 595        pci_stop_and_remove_bus_device_locked(pdev);
 596        return 0;
 597}
 598
 599/**
 600 * _base_sync_drv_fw_timestamp - Sync Drive-Fw TimeStamp.
 601 * @ioc: Per Adapter Object
 602 *
 603 * Return: nothing.
 604 */
 605static void _base_sync_drv_fw_timestamp(struct MPT3SAS_ADAPTER *ioc)
 606{
 607        Mpi26IoUnitControlRequest_t *mpi_request;
 608        Mpi26IoUnitControlReply_t *mpi_reply;
 609        u16 smid;
 610        ktime_t current_time;
 611        u64 TimeStamp = 0;
 612        u8 issue_reset = 0;
 613
 614        mutex_lock(&ioc->scsih_cmds.mutex);
 615        if (ioc->scsih_cmds.status != MPT3_CMD_NOT_USED) {
 616                ioc_err(ioc, "scsih_cmd in use %s\n", __func__);
 617                goto out;
 618        }
 619        ioc->scsih_cmds.status = MPT3_CMD_PENDING;
 620        smid = mpt3sas_base_get_smid(ioc, ioc->scsih_cb_idx);
 621        if (!smid) {
 622                ioc_err(ioc, "Failed obtaining a smid %s\n", __func__);
 623                ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
 624                goto out;
 625        }
 626        mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
 627        ioc->scsih_cmds.smid = smid;
 628        memset(mpi_request, 0, sizeof(Mpi26IoUnitControlRequest_t));
 629        mpi_request->Function = MPI2_FUNCTION_IO_UNIT_CONTROL;
 630        mpi_request->Operation = MPI26_CTRL_OP_SET_IOC_PARAMETER;
 631        mpi_request->IOCParameter = MPI26_SET_IOC_PARAMETER_SYNC_TIMESTAMP;
 632        current_time = ktime_get_real();
 633        TimeStamp = ktime_to_ms(current_time);
 634        mpi_request->Reserved7 = cpu_to_le32(TimeStamp & 0xFFFFFFFF);
 635        mpi_request->IOCParameterValue = cpu_to_le32(TimeStamp >> 32);
 636        init_completion(&ioc->scsih_cmds.done);
 637        ioc->put_smid_default(ioc, smid);
 638        dinitprintk(ioc, ioc_info(ioc,
 639            "Io Unit Control Sync TimeStamp (sending), @time %lld ms\n",
 640            TimeStamp));
 641        wait_for_completion_timeout(&ioc->scsih_cmds.done,
 642                MPT3SAS_TIMESYNC_TIMEOUT_SECONDS*HZ);
 643        if (!(ioc->scsih_cmds.status & MPT3_CMD_COMPLETE)) {
 644                mpt3sas_check_cmd_timeout(ioc,
 645                    ioc->scsih_cmds.status, mpi_request,
 646                    sizeof(Mpi2SasIoUnitControlRequest_t)/4, issue_reset);
 647                goto issue_host_reset;
 648        }
 649        if (ioc->scsih_cmds.status & MPT3_CMD_REPLY_VALID) {
 650                mpi_reply = ioc->scsih_cmds.reply;
 651                dinitprintk(ioc, ioc_info(ioc,
 652                    "Io Unit Control sync timestamp (complete): ioc_status(0x%04x), loginfo(0x%08x)\n",
 653                    le16_to_cpu(mpi_reply->IOCStatus),
 654                    le32_to_cpu(mpi_reply->IOCLogInfo)));
 655        }
 656issue_host_reset:
 657        if (issue_reset)
 658                mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
 659        ioc->scsih_cmds.status = MPT3_CMD_NOT_USED;
 660out:
 661        mutex_unlock(&ioc->scsih_cmds.mutex);
 662}
 663
 664/**
 665 * _base_fault_reset_work - workq handling ioc fault conditions
 666 * @work: input argument, used to derive ioc
 667 *
 668 * Context: sleep.
 669 */
 670static void
 671_base_fault_reset_work(struct work_struct *work)
 672{
 673        struct MPT3SAS_ADAPTER *ioc =
 674            container_of(work, struct MPT3SAS_ADAPTER, fault_reset_work.work);
 675        unsigned long    flags;
 676        u32 doorbell;
 677        int rc;
 678        struct task_struct *p;
 679
 680
 681        spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 682        if ((ioc->shost_recovery && (ioc->ioc_coredump_loop == 0)) ||
 683                        ioc->pci_error_recovery)
 684                goto rearm_timer;
 685        spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 686
 687        doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 688        if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_MASK) {
 689                ioc_err(ioc, "SAS host is non-operational !!!!\n");
 690
 691                /* It may be possible that EEH recovery can resolve some of
 692                 * pci bus failure issues rather removing the dead ioc function
 693                 * by considering controller is in a non-operational state. So
 694                 * here priority is given to the EEH recovery. If it doesn't
 695                 * not resolve this issue, mpt3sas driver will consider this
 696                 * controller to non-operational state and remove the dead ioc
 697                 * function.
 698                 */
 699                if (ioc->non_operational_loop++ < 5) {
 700                        spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock,
 701                                                         flags);
 702                        goto rearm_timer;
 703                }
 704
 705                /*
 706                 * Call _scsih_flush_pending_cmds callback so that we flush all
 707                 * pending commands back to OS. This call is required to avoid
 708                 * deadlock at block layer. Dead IOC will fail to do diag reset,
 709                 * and this call is safe since dead ioc will never return any
 710                 * command back from HW.
 711                 */
 712                ioc->schedule_dead_ioc_flush_running_cmds(ioc);
 713                /*
 714                 * Set remove_host flag early since kernel thread will
 715                 * take some time to execute.
 716                 */
 717                ioc->remove_host = 1;
 718                /*Remove the Dead Host */
 719                p = kthread_run(mpt3sas_remove_dead_ioc_func, ioc,
 720                    "%s_dead_ioc_%d", ioc->driver_name, ioc->id);
 721                if (IS_ERR(p))
 722                        ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread failed !!!!\n",
 723                                __func__);
 724                else
 725                        ioc_err(ioc, "%s: Running mpt3sas_dead_ioc thread success !!!!\n",
 726                                __func__);
 727                return; /* don't rearm timer */
 728        }
 729
 730        if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_COREDUMP) {
 731                u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
 732                    ioc->manu_pg11.CoreDumpTOSec :
 733                    MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
 734
 735                timeout /= (FAULT_POLLING_INTERVAL/1000);
 736
 737                if (ioc->ioc_coredump_loop == 0) {
 738                        mpt3sas_print_coredump_info(ioc,
 739                            doorbell & MPI2_DOORBELL_DATA_MASK);
 740                        /* do not accept any IOs and disable the interrupts */
 741                        spin_lock_irqsave(
 742                            &ioc->ioc_reset_in_progress_lock, flags);
 743                        ioc->shost_recovery = 1;
 744                        spin_unlock_irqrestore(
 745                            &ioc->ioc_reset_in_progress_lock, flags);
 746                        mpt3sas_base_mask_interrupts(ioc);
 747                        _base_clear_outstanding_commands(ioc);
 748                }
 749
 750                ioc_info(ioc, "%s: CoreDump loop %d.",
 751                    __func__, ioc->ioc_coredump_loop);
 752
 753                /* Wait until CoreDump completes or times out */
 754                if (ioc->ioc_coredump_loop++ < timeout) {
 755                        spin_lock_irqsave(
 756                            &ioc->ioc_reset_in_progress_lock, flags);
 757                        goto rearm_timer;
 758                }
 759        }
 760
 761        if (ioc->ioc_coredump_loop) {
 762                if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_COREDUMP)
 763                        ioc_err(ioc, "%s: CoreDump completed. LoopCount: %d",
 764                            __func__, ioc->ioc_coredump_loop);
 765                else
 766                        ioc_err(ioc, "%s: CoreDump Timed out. LoopCount: %d",
 767                            __func__, ioc->ioc_coredump_loop);
 768                ioc->ioc_coredump_loop = MPT3SAS_COREDUMP_LOOP_DONE;
 769        }
 770        ioc->non_operational_loop = 0;
 771        if ((doorbell & MPI2_IOC_STATE_MASK) != MPI2_IOC_STATE_OPERATIONAL) {
 772                rc = mpt3sas_base_hard_reset_handler(ioc, FORCE_BIG_HAMMER);
 773                ioc_warn(ioc, "%s: hard reset: %s\n",
 774                         __func__, rc == 0 ? "success" : "failed");
 775                doorbell = mpt3sas_base_get_iocstate(ioc, 0);
 776                if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
 777                        mpt3sas_print_fault_code(ioc, doorbell &
 778                            MPI2_DOORBELL_DATA_MASK);
 779                } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
 780                    MPI2_IOC_STATE_COREDUMP)
 781                        mpt3sas_print_coredump_info(ioc, doorbell &
 782                            MPI2_DOORBELL_DATA_MASK);
 783                if (rc && (doorbell & MPI2_IOC_STATE_MASK) !=
 784                    MPI2_IOC_STATE_OPERATIONAL)
 785                        return; /* don't rearm timer */
 786        }
 787        ioc->ioc_coredump_loop = 0;
 788        if (ioc->time_sync_interval &&
 789            ++ioc->timestamp_update_count >= ioc->time_sync_interval) {
 790                ioc->timestamp_update_count = 0;
 791                _base_sync_drv_fw_timestamp(ioc);
 792        }
 793        spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 794 rearm_timer:
 795        if (ioc->fault_reset_work_q)
 796                queue_delayed_work(ioc->fault_reset_work_q,
 797                    &ioc->fault_reset_work,
 798                    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 799        spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 800}
 801
 802/**
 803 * mpt3sas_base_start_watchdog - start the fault_reset_work_q
 804 * @ioc: per adapter object
 805 *
 806 * Context: sleep.
 807 */
 808void
 809mpt3sas_base_start_watchdog(struct MPT3SAS_ADAPTER *ioc)
 810{
 811        unsigned long    flags;
 812
 813        if (ioc->fault_reset_work_q)
 814                return;
 815
 816        ioc->timestamp_update_count = 0;
 817        /* initialize fault polling */
 818
 819        INIT_DELAYED_WORK(&ioc->fault_reset_work, _base_fault_reset_work);
 820        snprintf(ioc->fault_reset_work_q_name,
 821            sizeof(ioc->fault_reset_work_q_name), "poll_%s%d_status",
 822            ioc->driver_name, ioc->id);
 823        ioc->fault_reset_work_q =
 824                create_singlethread_workqueue(ioc->fault_reset_work_q_name);
 825        if (!ioc->fault_reset_work_q) {
 826                ioc_err(ioc, "%s: failed (line=%d)\n", __func__, __LINE__);
 827                return;
 828        }
 829        spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 830        if (ioc->fault_reset_work_q)
 831                queue_delayed_work(ioc->fault_reset_work_q,
 832                    &ioc->fault_reset_work,
 833                    msecs_to_jiffies(FAULT_POLLING_INTERVAL));
 834        spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 835}
 836
 837/**
 838 * mpt3sas_base_stop_watchdog - stop the fault_reset_work_q
 839 * @ioc: per adapter object
 840 *
 841 * Context: sleep.
 842 */
 843void
 844mpt3sas_base_stop_watchdog(struct MPT3SAS_ADAPTER *ioc)
 845{
 846        unsigned long flags;
 847        struct workqueue_struct *wq;
 848
 849        spin_lock_irqsave(&ioc->ioc_reset_in_progress_lock, flags);
 850        wq = ioc->fault_reset_work_q;
 851        ioc->fault_reset_work_q = NULL;
 852        spin_unlock_irqrestore(&ioc->ioc_reset_in_progress_lock, flags);
 853        if (wq) {
 854                if (!cancel_delayed_work_sync(&ioc->fault_reset_work))
 855                        flush_workqueue(wq);
 856                destroy_workqueue(wq);
 857        }
 858}
 859
 860/**
 861 * mpt3sas_base_fault_info - verbose translation of firmware FAULT code
 862 * @ioc: per adapter object
 863 * @fault_code: fault code
 864 */
 865void
 866mpt3sas_base_fault_info(struct MPT3SAS_ADAPTER *ioc , u16 fault_code)
 867{
 868        ioc_err(ioc, "fault_state(0x%04x)!\n", fault_code);
 869}
 870
 871/**
 872 * mpt3sas_base_coredump_info - verbose translation of firmware CoreDump state
 873 * @ioc: per adapter object
 874 * @fault_code: fault code
 875 *
 876 * Return: nothing.
 877 */
 878void
 879mpt3sas_base_coredump_info(struct MPT3SAS_ADAPTER *ioc, u16 fault_code)
 880{
 881        ioc_err(ioc, "coredump_state(0x%04x)!\n", fault_code);
 882}
 883
 884/**
 885 * mpt3sas_base_wait_for_coredump_completion - Wait until coredump
 886 * completes or times out
 887 * @ioc: per adapter object
 888 * @caller: caller function name
 889 *
 890 * Return: 0 for success, non-zero for failure.
 891 */
 892int
 893mpt3sas_base_wait_for_coredump_completion(struct MPT3SAS_ADAPTER *ioc,
 894                const char *caller)
 895{
 896        u8 timeout = (ioc->manu_pg11.CoreDumpTOSec) ?
 897                        ioc->manu_pg11.CoreDumpTOSec :
 898                        MPT3SAS_DEFAULT_COREDUMP_TIMEOUT_SECONDS;
 899
 900        int ioc_state = _base_wait_on_iocstate(ioc, MPI2_IOC_STATE_FAULT,
 901                                        timeout);
 902
 903        if (ioc_state)
 904                ioc_err(ioc,
 905                    "%s: CoreDump timed out. (ioc_state=0x%x)\n",
 906                    caller, ioc_state);
 907        else
 908                ioc_info(ioc,
 909                    "%s: CoreDump completed. (ioc_state=0x%x)\n",
 910                    caller, ioc_state);
 911
 912        return ioc_state;
 913}
 914
 915/**
 916 * mpt3sas_halt_firmware - halt's mpt controller firmware
 917 * @ioc: per adapter object
 918 *
 919 * For debugging timeout related issues.  Writing 0xCOFFEE00
 920 * to the doorbell register will halt controller firmware. With
 921 * the purpose to stop both driver and firmware, the enduser can
 922 * obtain a ring buffer from controller UART.
 923 */
 924void
 925mpt3sas_halt_firmware(struct MPT3SAS_ADAPTER *ioc)
 926{
 927        u32 doorbell;
 928
 929        if (!ioc->fwfault_debug)
 930                return;
 931
 932        dump_stack();
 933
 934        doorbell = ioc->base_readl(&ioc->chip->Doorbell);
 935        if ((doorbell & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
 936                mpt3sas_print_fault_code(ioc, doorbell &
 937                    MPI2_DOORBELL_DATA_MASK);
 938        } else if ((doorbell & MPI2_IOC_STATE_MASK) ==
 939            MPI2_IOC_STATE_COREDUMP) {
 940                mpt3sas_print_coredump_info(ioc, doorbell &
 941                    MPI2_DOORBELL_DATA_MASK);
 942        } else {
 943                writel(0xC0FFEE00, &ioc->chip->Doorbell);
 944                ioc_err(ioc, "Firmware is halted due to command timeout\n");
 945        }
 946
 947        if (ioc->fwfault_debug == 2)
 948                for (;;)
 949                        ;
 950        else
 951                panic("panic in %s\n", __func__);
 952}
 953
 954/**
 955 * _base_sas_ioc_info - verbose translation of the ioc status
 956 * @ioc: per adapter object
 957 * @mpi_reply: reply mf payload returned from firmware
 958 * @request_hdr: request mf
 959 */
 960static void
 961_base_sas_ioc_info(struct MPT3SAS_ADAPTER *ioc, MPI2DefaultReply_t *mpi_reply,
 962        MPI2RequestHeader_t *request_hdr)
 963{
 964        u16 ioc_status = le16_to_cpu(mpi_reply->IOCStatus) &
 965            MPI2_IOCSTATUS_MASK;
 966        char *desc = NULL;
 967        u16 frame_sz;
 968        char *func_str = NULL;
 969
 970        /* SCSI_IO, RAID_PASS are handled from _scsih_scsi_ioc_info */
 971        if (request_hdr->Function == MPI2_FUNCTION_SCSI_IO_REQUEST ||
 972            request_hdr->Function == MPI2_FUNCTION_RAID_SCSI_IO_PASSTHROUGH ||
 973            request_hdr->Function == MPI2_FUNCTION_EVENT_NOTIFICATION)
 974                return;
 975
 976        if (ioc_status == MPI2_IOCSTATUS_CONFIG_INVALID_PAGE)
 977                return;
 978        /*
 979         * Older Firmware version doesn't support driver trigger pages.
 980         * So, skip displaying 'config invalid type' type
 981         * of error message.
 982         */
 983        if (request_hdr->Function == MPI2_FUNCTION_CONFIG) {
 984                Mpi2ConfigRequest_t *rqst = (Mpi2ConfigRequest_t *)request_hdr;
 985
 986                if ((rqst->ExtPageType ==
 987                    MPI2_CONFIG_EXTPAGETYPE_DRIVER_PERSISTENT_TRIGGER) &&
 988                    !(ioc->logging_level & MPT_DEBUG_CONFIG)) {
 989                        return;
 990                }
 991        }
 992
 993        switch (ioc_status) {
 994
 995/****************************************************************************
 996*  Common IOCStatus values for all replies
 997****************************************************************************/
 998
 999        case MPI2_IOCSTATUS_INVALID_FUNCTION:
1000                desc = "invalid function";
1001                break;
1002        case MPI2_IOCSTATUS_BUSY:
1003                desc = "busy";
1004                break;
1005        case MPI2_IOCSTATUS_INVALID_SGL:
1006                desc = "invalid sgl";
1007                break;
1008        case MPI2_IOCSTATUS_INTERNAL_ERROR:
1009                desc = "internal error";
1010                break;
1011        case MPI2_IOCSTATUS_INVALID_VPID:
1012                desc = "invalid vpid";
1013                break;
1014        case MPI2_IOCSTATUS_INSUFFICIENT_RESOURCES:
1015                desc = "insufficient resources";
1016                break;
1017        case MPI2_IOCSTATUS_INSUFFICIENT_POWER:
1018                desc = "insufficient power";
1019                break;
1020        case MPI2_IOCSTATUS_INVALID_FIELD:
1021                desc = "invalid field";
1022                break;
1023        case MPI2_IOCSTATUS_INVALID_STATE:
1024                desc = "invalid state";
1025                break;
1026        case MPI2_IOCSTATUS_OP_STATE_NOT_SUPPORTED:
1027                desc = "op state not supported";
1028                break;
1029
1030/****************************************************************************
1031*  Config IOCStatus values
1032****************************************************************************/
1033
1034        case MPI2_IOCSTATUS_CONFIG_INVALID_ACTION:
1035                desc = "config invalid action";
1036                break;
1037        case MPI2_IOCSTATUS_CONFIG_INVALID_TYPE:
1038                desc = "config invalid type";
1039                break;
1040        case MPI2_IOCSTATUS_CONFIG_INVALID_PAGE:
1041                desc = "config invalid page";
1042                break;
1043        case MPI2_IOCSTATUS_CONFIG_INVALID_DATA:
1044                desc = "config invalid data";
1045                break;
1046        case MPI2_IOCSTATUS_CONFIG_NO_DEFAULTS:
1047                desc = "config no defaults";
1048                break;
1049        case MPI2_IOCSTATUS_CONFIG_CANT_COMMIT:
1050                desc = "config cant commit";
1051                break;
1052
1053/****************************************************************************
1054*  SCSI IO Reply
1055****************************************************************************/
1056
1057        case MPI2_IOCSTATUS_SCSI_RECOVERED_ERROR:
1058        case MPI2_IOCSTATUS_SCSI_INVALID_DEVHANDLE:
1059        case MPI2_IOCSTATUS_SCSI_DEVICE_NOT_THERE:
1060        case MPI2_IOCSTATUS_SCSI_DATA_OVERRUN:
1061        case MPI2_IOCSTATUS_SCSI_DATA_UNDERRUN:
1062        case MPI2_IOCSTATUS_SCSI_IO_DATA_ERROR:
1063        case MPI2_IOCSTATUS_SCSI_PROTOCOL_ERROR:
1064        case MPI2_IOCSTATUS_SCSI_TASK_TERMINATED:
1065        case MPI2_IOCSTATUS_SCSI_RESIDUAL_MISMATCH:
1066        case MPI2_IOCSTATUS_SCSI_TASK_MGMT_FAILED:
1067        case MPI2_IOCSTATUS_SCSI_IOC_TERMINATED:
1068        case MPI2_IOCSTATUS_SCSI_EXT_TERMINATED:
1069                break;
1070
1071/****************************************************************************
1072*  For use by SCSI Initiator and SCSI Target end-to-end data protection
1073****************************************************************************/
1074
1075        case MPI2_IOCSTATUS_EEDP_GUARD_ERROR:
1076                desc = "eedp guard error";
1077                break;
1078        case MPI2_IOCSTATUS_EEDP_REF_TAG_ERROR:
1079                desc = "eedp ref tag error";
1080                break;
1081        case MPI2_IOCSTATUS_EEDP_APP_TAG_ERROR:
1082                desc = "eedp app tag error";
1083                break;
1084
1085/****************************************************************************
1086*  SCSI Target values
1087****************************************************************************/
1088
1089        case MPI2_IOCSTATUS_TARGET_INVALID_IO_INDEX:
1090                desc = "target invalid io index";
1091                break;
1092        case MPI2_IOCSTATUS_TARGET_ABORTED:
1093                desc = "target aborted";
1094                break;
1095        case MPI2_IOCSTATUS_TARGET_NO_CONN_RETRYABLE:
1096                desc = "target no conn retryable";
1097                break;
1098        case MPI2_IOCSTATUS_TARGET_NO_CONNECTION:
1099                desc = "target no connection";
1100                break;
1101        case MPI2_IOCSTATUS_TARGET_XFER_COUNT_MISMATCH:
1102                desc = "target xfer count mismatch";
1103                break;
1104        case MPI2_IOCSTATUS_TARGET_DATA_OFFSET_ERROR:
1105                desc = "target data offset error";
1106                break;
1107        case MPI2_IOCSTATUS_TARGET_TOO_MUCH_WRITE_DATA:
1108                desc = "target too much write data";
1109                break;
1110        case MPI2_IOCSTATUS_TARGET_IU_TOO_SHORT:
1111                desc = "target iu too short";
1112                break;
1113        case MPI2_IOCSTATUS_TARGET_ACK_NAK_TIMEOUT:
1114                desc = "target ack nak timeout";
1115                break;
1116        case MPI2_IOCSTATUS_TARGET_NAK_RECEIVED:
1117                desc = "target nak received";
1118                break;
1119
1120/****************************************************************************
1121*  Serial Attached SCSI values
1122****************************************************************************/
1123
1124        case MPI2_IOCSTATUS_SAS_SMP_REQUEST_FAILED:
1125                desc = "smp request failed";
1126                break;
1127        case MPI2_IOCSTATUS_SAS_SMP_DATA_OVERRUN:
1128                desc = "smp data overrun";
1129                break;
1130
1131/****************************************************************************
1132*  Diagnostic Buffer Post / Diagnostic Release values
1133****************************************************************************/
1134
1135        case MPI2_IOCSTATUS_DIAGNOSTIC_RELEASED:
1136                desc = "diagnostic released";
1137                break;
1138        default:
1139                break;
1140        }
1141
1142        if (!desc)
1143                return;
1144
1145        switch (request_hdr->Function) {
1146        case MPI2_FUNCTION_CONFIG:
1147                frame_sz = sizeof(Mpi2ConfigRequest_t) + ioc->sge_size;
1148                func_str = "config_page";
1149                break;
1150        case MPI2_FUNCTION_SCSI_TASK_MGMT:
1151                frame_sz = sizeof(Mpi2SCSITaskManagementRequest_t);
1152                func_str = "task_mgmt";
1153                break;
1154        case MPI2_FUNCTION_SAS_IO_UNIT_CONTROL:
1155                frame_sz = sizeof(Mpi2SasIoUnitControlRequest_t);
1156                func_str = "sas_iounit_ctl";
1157                break;
1158        case MPI2_FUNCTION_SCSI_ENCLOSURE_PROCESSOR:
1159                frame_sz = sizeof(Mpi2SepRequest_t);
1160                func_str = "enclosure";
1161                break;
1162        case MPI2_FUNCTION_IOC_INIT:
1163                frame_sz = sizeof(Mpi2IOCInitRequest_t);
1164                func_str = "ioc_init";
1165                break;
1166        case MPI2_FUNCTION_PORT_ENABLE:
1167                frame_sz = sizeof(Mpi2PortEnableRequest_t);
1168                func_str = "port_enable";
1169                break;
1170        case MPI2_FUNCTION_SMP_PASSTHROUGH:
1171                frame_sz = sizeof(Mpi2SmpPassthroughRequest_t) + ioc->sge_size;
1172                func_str = "smp_passthru";
1173                break;
1174        case MPI2_FUNCTION_NVME_ENCAPSULATED:
1175                frame_sz = sizeof(Mpi26NVMeEncapsulatedRequest_t) +
1176                    ioc->sge_size;
1177                func_str = "nvme_encapsulated";
1178                break;
1179        default:
1180                frame_sz = 32;
1181                func_str = "unknown";
1182                break;
1183        }
1184
1185        ioc_warn(ioc, "ioc_status: %s(0x%04x), request(0x%p),(%s)\n",
1186                 desc, ioc_status, request_hdr, func_str);
1187
1188        _debug_dump_mf(request_hdr, frame_sz/4);
1189}
1190
1191/**
1192 * _base_display_event_data - verbose translation of firmware asyn events
1193 * @ioc: per adapter object
1194 * @mpi_reply: reply mf payload returned from firmware
1195 */
1196static void
1197_base_display_event_data(struct MPT3SAS_ADAPTER *ioc,
1198        Mpi2EventNotificationReply_t *mpi_reply)
1199{
1200        char *desc = NULL;
1201        u16 event;
1202
1203        if (!(ioc->logging_level & MPT_DEBUG_EVENTS))
1204                return;
1205
1206        event = le16_to_cpu(mpi_reply->Event);
1207
1208        switch (event) {
1209        case MPI2_EVENT_LOG_DATA:
1210                desc = "Log Data";
1211                break;
1212        case MPI2_EVENT_STATE_CHANGE:
1213                desc = "Status Change";
1214                break;
1215        case MPI2_EVENT_HARD_RESET_RECEIVED:
1216                desc = "Hard Reset Received";
1217                break;
1218        case MPI2_EVENT_EVENT_CHANGE:
1219                desc = "Event Change";
1220                break;
1221        case MPI2_EVENT_SAS_DEVICE_STATUS_CHANGE:
1222                desc = "Device Status Change";
1223                break;
1224        case MPI2_EVENT_IR_OPERATION_STATUS:
1225                if (!ioc->hide_ir_msg)
1226                        desc = "IR Operation Status";
1227                break;
1228        case MPI2_EVENT_SAS_DISCOVERY:
1229        {
1230                Mpi2EventDataSasDiscovery_t *event_data =
1231                    (Mpi2EventDataSasDiscovery_t *)mpi_reply->EventData;
1232                ioc_info(ioc, "Discovery: (%s)",
1233                         event_data->ReasonCode == MPI2_EVENT_SAS_DISC_RC_STARTED ?
1234                         "start" : "stop");
1235                if (event_data->DiscoveryStatus)
1236                        pr_cont(" discovery_status(0x%08x)",
1237                            le32_to_cpu(event_data->DiscoveryStatus));
1238                pr_cont("\n");
1239                return;
1240        }
1241        case MPI2_EVENT_SAS_BROADCAST_PRIMITIVE:
1242                desc = "SAS Broadcast Primitive";
1243                break;
1244        case MPI2_EVENT_SAS_INIT_DEVICE_STATUS_CHANGE:
1245                desc = "SAS Init Device Status Change";
1246                break;
1247        case MPI2_EVENT_SAS_INIT_TABLE_OVERFLOW:
1248                desc = "SAS Init Table Overflow";
1249                break;
1250        case MPI2_EVENT_SAS_TOPOLOGY_CHANGE_LIST:
1251                desc = "SAS Topology Change List";
1252                break;
1253        case MPI2_EVENT_SAS_ENCL_DEVICE_STATUS_CHANGE:
1254                desc = "SAS Enclosure Device Status Change";
1255                break;
1256        case MPI2_EVENT_IR_VOLUME:
1257                if (!ioc->hide_ir_msg)
1258                        desc = "IR Volume";
1259                break;
1260        case MPI2_EVENT_IR_PHYSICAL_DISK:
1261                if (!ioc->hide_ir_msg)
1262                        desc = "IR Physical Disk";
1263                break;
1264        case MPI2_EVENT_IR_CONFIGURATION_CHANGE_LIST:
1265                if (!ioc->hide_ir_msg)
1266                        desc = "IR Configuration Change List";
1267                break;
1268        case MPI2_EVENT_LOG_ENTRY_ADDED:
1269                if (!ioc->hide_ir_msg)
1270                        desc = "Log Entry Added";
1271                break;
1272        case MPI2_EVENT_TEMP_THRESHOLD:
1273                desc = "Temperature Threshold";
1274                break;
1275        case MPI2_EVENT_ACTIVE_CABLE_EXCEPTION:
1276                desc = "Cable Event";
1277                break;
1278        case MPI2_EVENT_SAS_DEVICE_DISCOVERY_ERROR:
1279                desc = "SAS Device Discovery Error";
1280                break;
1281        case MPI2_EVENT_PCIE_DEVICE_STATUS_CHANGE:
1282                desc = "PCIE Device Status Change";
1283                break;
1284        case MPI2_EVENT_PCIE_ENUMERATION:
1285        {
1286                Mpi26EventDataPCIeEnumeration_t *event_data =
1287                        (Mpi26EventDataPCIeEnumeration_t *)mpi_reply->EventData;
1288                ioc_info(ioc, "PCIE Enumeration: (%s)",
1289                         event_data->ReasonCode == MPI26_EVENT_PCIE_ENUM_RC_STARTED ?
1290                         "start" : "stop");
1291                if (event_data->EnumerationStatus)
1292                        pr_cont("enumeration_status(0x%08x)",
1293                                le32_to_cpu(event_data->EnumerationStatus));
1294                pr_cont("\n");
1295                return;
1296        }
1297        case MPI2_EVENT_PCIE_TOPOLOGY_CHANGE_LIST:
1298                desc = "PCIE Topology Change List";
1299                break;
1300        }
1301
1302        if (!desc)
1303                return;
1304
1305        ioc_info(ioc, "%s\n", desc);
1306}
1307
1308/**
1309 * _base_sas_log_info - verbose translation of firmware log info
1310 * @ioc: per adapter object
1311 * @log_info: log info
1312 */
1313static void
1314_base_sas_log_info(struct MPT3SAS_ADAPTER *ioc , u32 log_info)
1315{
1316        union loginfo_type {
1317                u32     loginfo;
1318                struct {
1319                        u32     subcode:16;
1320                        u32     code:8;
1321                        u32     originator:4;
1322                        u32     bus_type:4;
1323                } dw;
1324        };
1325        union loginfo_type sas_loginfo;
1326        char *originator_str = NULL;
1327
1328        sas_loginfo.loginfo = log_info;
1329        if (sas_loginfo.dw.bus_type != 3 /*SAS*/)
1330                return;
1331
1332        /* each nexus loss loginfo */
1333        if (log_info == 0x31170000)
1334                return;
1335
1336        /* eat the loginfos associated with task aborts */
1337        if (ioc->ignore_loginfos && (log_info == 0x30050000 || log_info ==
1338            0x31140000 || log_info == 0x31130000))
1339                return;
1340
1341        switch (sas_loginfo.dw.originator) {
1342        case 0:
1343                originator_str = "IOP";
1344                break;
1345        case 1:
1346                originator_str = "PL";
1347                break;
1348        case 2:
1349                if (!ioc->hide_ir_msg)
1350                        originator_str = "IR";
1351                else
1352                        originator_str = "WarpDrive";
1353                break;
1354        }
1355
1356        ioc_warn(ioc, "log_info(0x%08x): originator(%s), code(0x%02x), sub_code(0x%04x)\n",
1357                 log_info,
1358                 originator_str, sas_loginfo.dw.code, sas_loginfo.dw.subcode);
1359}
1360
1361/**
1362 * _base_display_reply_info - handle reply descriptors depending on IOC Status
1363 * @ioc: per adapter object
1364 * @smid: system request message index
1365 * @msix_index: MSIX table index supplied by the OS
1366 * @reply: reply message frame (lower 32bit addr)
1367 */
1368static void
1369_base_display_reply_info(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1370        u32 reply)
1371{
1372        MPI2DefaultReply_t *mpi_reply;
1373        u16 ioc_status;
1374        u32 loginfo = 0;
1375
1376        mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1377        if (unlikely(!mpi_reply)) {
1378                ioc_err(ioc, "mpi_reply not valid at %s:%d/%s()!\n",
1379                        __FILE__, __LINE__, __func__);
1380                return;
1381        }
1382        ioc_status = le16_to_cpu(mpi_reply->IOCStatus);
1383
1384        if ((ioc_status & MPI2_IOCSTATUS_MASK) &&
1385            (ioc->logging_level & MPT_DEBUG_REPLY)) {
1386                _base_sas_ioc_info(ioc , mpi_reply,
1387                   mpt3sas_base_get_msg_frame(ioc, smid));
1388        }
1389
1390        if (ioc_status & MPI2_IOCSTATUS_FLAG_LOG_INFO_AVAILABLE) {
1391                loginfo = le32_to_cpu(mpi_reply->IOCLogInfo);
1392                _base_sas_log_info(ioc, loginfo);
1393        }
1394
1395        if (ioc_status || loginfo) {
1396                ioc_status &= MPI2_IOCSTATUS_MASK;
1397                mpt3sas_trigger_mpi(ioc, ioc_status, loginfo);
1398        }
1399}
1400
1401/**
1402 * mpt3sas_base_done - base internal command completion routine
1403 * @ioc: per adapter object
1404 * @smid: system request message index
1405 * @msix_index: MSIX table index supplied by the OS
1406 * @reply: reply message frame(lower 32bit addr)
1407 *
1408 * Return:
1409 * 1 meaning mf should be freed from _base_interrupt
1410 * 0 means the mf is freed from this function.
1411 */
1412u8
1413mpt3sas_base_done(struct MPT3SAS_ADAPTER *ioc, u16 smid, u8 msix_index,
1414        u32 reply)
1415{
1416        MPI2DefaultReply_t *mpi_reply;
1417
1418        mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1419        if (mpi_reply && mpi_reply->Function == MPI2_FUNCTION_EVENT_ACK)
1420                return mpt3sas_check_for_pending_internal_cmds(ioc, smid);
1421
1422        if (ioc->base_cmds.status == MPT3_CMD_NOT_USED)
1423                return 1;
1424
1425        ioc->base_cmds.status |= MPT3_CMD_COMPLETE;
1426        if (mpi_reply) {
1427                ioc->base_cmds.status |= MPT3_CMD_REPLY_VALID;
1428                memcpy(ioc->base_cmds.reply, mpi_reply, mpi_reply->MsgLength*4);
1429        }
1430        ioc->base_cmds.status &= ~MPT3_CMD_PENDING;
1431
1432        complete(&ioc->base_cmds.done);
1433        return 1;
1434}
1435
1436/**
1437 * _base_async_event - main callback handler for firmware asyn events
1438 * @ioc: per adapter object
1439 * @msix_index: MSIX table index supplied by the OS
1440 * @reply: reply message frame(lower 32bit addr)
1441 *
1442 * Return:
1443 * 1 meaning mf should be freed from _base_interrupt
1444 * 0 means the mf is freed from this function.
1445 */
1446static u8
1447_base_async_event(struct MPT3SAS_ADAPTER *ioc, u8 msix_index, u32 reply)
1448{
1449        Mpi2EventNotificationReply_t *mpi_reply;
1450        Mpi2EventAckRequest_t *ack_request;
1451        u16 smid;
1452        struct _event_ack_list *delayed_event_ack;
1453
1454        mpi_reply = mpt3sas_base_get_reply_virt_addr(ioc, reply);
1455        if (!mpi_reply)
1456                return 1;
1457        if (mpi_reply->Function != MPI2_FUNCTION_EVENT_NOTIFICATION)
1458                return 1;
1459
1460        _base_display_event_data(ioc, mpi_reply);
1461
1462        if (!(mpi_reply->AckRequired & MPI2_EVENT_NOTIFICATION_ACK_REQUIRED))
1463                goto out;
1464        smid = mpt3sas_base_get_smid(ioc, ioc->base_cb_idx);
1465        if (!smid) {
1466                delayed_event_ack = kzalloc(sizeof(*delayed_event_ack),
1467                                        GFP_ATOMIC);
1468                if (!delayed_event_ack)
1469                        goto out;
1470                INIT_LIST_HEAD(&delayed_event_ack->list);
1471                delayed_event_ack->Event = mpi_reply->Event;
1472                delayed_event_ack->EventContext = mpi_reply->EventContext;
1473                list_add_tail(&delayed_event_ack->list,
1474                                &ioc->delayed_event_ack_list);
1475                dewtprintk(ioc,
1476                           ioc_info(ioc, "DELAYED: EVENT ACK: event (0x%04x)\n",
1477                                    le16_to_cpu(mpi_reply->Event)));
1478                goto out;
1479        }
1480
1481        ack_request = mpt3sas_base_get_msg_frame(ioc, smid);
1482        memset(ack_request, 0, sizeof(Mpi2EventAckRequest_t));
1483        ack_request->Function = MPI2_FUNCTION_EVENT_ACK;
1484        ack_request->Event = mpi_reply->Event;
1485        ack_request->EventContext = mpi_reply->EventContext;
1486        ack_request->VF_ID = 0;  /* TODO */
1487        ack_request->VP_ID = 0;
1488        ioc->put_smid_default(ioc, smid);
1489
1490 out:
1491
1492        /* scsih callback handler */
1493        mpt3sas_scsih_event_callback(ioc, msix_index, reply);
1494
1495        /* ctl callback handler */
1496        mpt3sas_ctl_event_callback(ioc, msix_index, reply);
1497
1498        return 1;
1499}
1500
1501static struct scsiio_tracker *
1502_get_st_from_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1503{
1504        struct scsi_cmnd *cmd;
1505
1506        if (WARN_ON(!smid) ||
1507            WARN_ON(smid >= ioc->hi_priority_smid))
1508                return NULL;
1509
1510        cmd = mpt3sas_scsih_scsi_lookup_get(ioc, smid);
1511        if (cmd)
1512                return scsi_cmd_priv(cmd);
1513
1514        return NULL;
1515}
1516
1517/**
1518 * _base_get_cb_idx - obtain the callback index
1519 * @ioc: per adapter object
1520 * @smid: system request message index
1521 *
1522 * Return: callback index.
1523 */
1524static u8
1525_base_get_cb_idx(struct MPT3SAS_ADAPTER *ioc, u16 smid)
1526{
1527        int i;
1528        u16 ctl_smid = ioc->scsiio_depth - INTERNAL_SCSIIO_CMDS_COUNT + 1;
1529        u8 cb_idx = 0xFF;
1530
1531        if (smid < ioc->hi_priority_smid) {
1532                struct scsiio_tracker *st;
1533
1534                if (smid < ctl_smid) {
1535                        st = _get_st_from_smid(ioc, smid);
1536                        if (st)
1537                                cb_idx = st->cb_idx;
1538                } else if (smid == ctl_smid)
1539                        cb_idx = ioc->ctl_cb_idx;
1540        } else if (smid < ioc->internal_smid) {
1541                i = smid - ioc->hi_priority_smid;
1542                cb_idx = ioc->hpr_lookup[i].cb_idx;
1543        } else if (smid <= ioc->hba_queue_depth) {
1544                i = smid - ioc->internal_smid;
1545                cb_idx = ioc->internal_lookup[i].cb_idx;
1546        }
1547        return cb_idx;
1548}
1549
1550/**
1551 * mpt3sas_base_mask_interrupts - disable interrupts
1552 * @ioc: per adapter object
1553 *
1554 * Disabling ResetIRQ, Reply and Doorbell Interrupts
1555 */
1556void
1557mpt3sas_base_mask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1558{
1559        u32 him_register;
1560
1561        ioc->mask_interrupts = 1;
1562        him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1563        him_register |= MPI2_HIM_DIM + MPI2_HIM_RIM + MPI2_HIM_RESET_IRQ_MASK;
1564        writel(him_register, &ioc->chip->HostInterruptMask);
1565        ioc->base_readl(&ioc->chip->HostInterruptMask);
1566}
1567
1568/**
1569 * mpt3sas_base_unmask_interrupts - enable interrupts
1570 * @ioc: per adapter object
1571 *
1572 * Enabling only Reply Interrupts
1573 */
1574void
1575mpt3sas_base_unmask_interrupts(struct MPT3SAS_ADAPTER *ioc)
1576{
1577        u32 him_register;
1578
1579        him_register = ioc->base_readl(&ioc->chip->HostInterruptMask);
1580        him_register &= ~MPI2_HIM_RIM;
1581        writel(him_register, &ioc->chip->HostInterruptMask);
1582        ioc->mask_interrupts = 0;
1583}
1584
1585union reply_descriptor {
1586        u64 word;
1587        struct {
1588                u32 low;
1589                u32 high;
1590        } u;
1591};
1592
1593static u32 base_mod64(u64 dividend, u32 divisor)
1594{
1595        u32 remainder;
1596
1597        if (!divisor)
1598                pr_err("mpt3sas: DIVISOR is zero, in div fn\n");
1599        remainder = do_div(dividend, divisor);
1600        return remainder;
1601}
1602
1603/**
1604 * _base_process_reply_queue - Process reply descriptors from reply
1605 *              descriptor post queue.
1606 * @reply_q: per IRQ's reply queue object.
1607 *
1608 * Return: number of reply descriptors processed from reply
1609 *              descriptor queue.
1610 */
1611static int
1612_base_process_reply_queue(struct adapter_reply_queue *reply_q)
1613{
1614        union reply_descriptor rd;
1615        u64 completed_cmds;
1616        u8 request_descript_type;
1617        u16 smid;
1618        u8 cb_idx;
1619        u32 reply;
1620        u8 msix_index = reply_q->msix_index;
1621        struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1622        Mpi2ReplyDescriptorsUnion_t *rpf;
1623        u8 rc;
1624
1625        completed_cmds = 0;
1626        if (!atomic_add_unless(&reply_q->busy, 1, 1))
1627                return completed_cmds;
1628
1629        rpf = &reply_q->reply_post_free[reply_q->reply_post_host_index];
1630        request_descript_type = rpf->Default.ReplyFlags
1631             & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1632        if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED) {
1633                atomic_dec(&reply_q->busy);
1634                return completed_cmds;
1635        }
1636
1637        cb_idx = 0xFF;
1638        do {
1639                rd.word = le64_to_cpu(rpf->Words);
1640                if (rd.u.low == UINT_MAX || rd.u.high == UINT_MAX)
1641                        goto out;
1642                reply = 0;
1643                smid = le16_to_cpu(rpf->Default.DescriptorTypeDependent1);
1644                if (request_descript_type ==
1645                    MPI25_RPY_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO_SUCCESS ||
1646                    request_descript_type ==
1647                    MPI2_RPY_DESCRIPT_FLAGS_SCSI_IO_SUCCESS ||
1648                    request_descript_type ==
1649                    MPI26_RPY_DESCRIPT_FLAGS_PCIE_ENCAPSULATED_SUCCESS) {
1650                        cb_idx = _base_get_cb_idx(ioc, smid);
1651                        if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1652                            (likely(mpt_callbacks[cb_idx] != NULL))) {
1653                                rc = mpt_callbacks[cb_idx](ioc, smid,
1654                                    msix_index, 0);
1655                                if (rc)
1656                                        mpt3sas_base_free_smid(ioc, smid);
1657                        }
1658                } else if (request_descript_type ==
1659                    MPI2_RPY_DESCRIPT_FLAGS_ADDRESS_REPLY) {
1660                        reply = le32_to_cpu(
1661                            rpf->AddressReply.ReplyFrameAddress);
1662                        if (reply > ioc->reply_dma_max_address ||
1663                            reply < ioc->reply_dma_min_address)
1664                                reply = 0;
1665                        if (smid) {
1666                                cb_idx = _base_get_cb_idx(ioc, smid);
1667                                if ((likely(cb_idx < MPT_MAX_CALLBACKS)) &&
1668                                    (likely(mpt_callbacks[cb_idx] != NULL))) {
1669                                        rc = mpt_callbacks[cb_idx](ioc, smid,
1670                                            msix_index, reply);
1671                                        if (reply)
1672                                                _base_display_reply_info(ioc,
1673                                                    smid, msix_index, reply);
1674                                        if (rc)
1675                                                mpt3sas_base_free_smid(ioc,
1676                                                    smid);
1677                                }
1678                        } else {
1679                                _base_async_event(ioc, msix_index, reply);
1680                        }
1681
1682                        /* reply free queue handling */
1683                        if (reply) {
1684                                ioc->reply_free_host_index =
1685                                    (ioc->reply_free_host_index ==
1686                                    (ioc->reply_free_queue_depth - 1)) ?
1687                                    0 : ioc->reply_free_host_index + 1;
1688                                ioc->reply_free[ioc->reply_free_host_index] =
1689                                    cpu_to_le32(reply);
1690                                if (ioc->is_mcpu_endpoint)
1691                                        _base_clone_reply_to_sys_mem(ioc,
1692                                                reply,
1693                                                ioc->reply_free_host_index);
1694                                writel(ioc->reply_free_host_index,
1695                                    &ioc->chip->ReplyFreeHostIndex);
1696                        }
1697                }
1698
1699                rpf->Words = cpu_to_le64(ULLONG_MAX);
1700                reply_q->reply_post_host_index =
1701                    (reply_q->reply_post_host_index ==
1702                    (ioc->reply_post_queue_depth - 1)) ? 0 :
1703                    reply_q->reply_post_host_index + 1;
1704                request_descript_type =
1705                    reply_q->reply_post_free[reply_q->reply_post_host_index].
1706                    Default.ReplyFlags & MPI2_RPY_DESCRIPT_FLAGS_TYPE_MASK;
1707                completed_cmds++;
1708                /* Update the reply post host index after continuously
1709                 * processing the threshold number of Reply Descriptors.
1710                 * So that FW can find enough entries to post the Reply
1711                 * Descriptors in the reply descriptor post queue.
1712                 */
1713                if (completed_cmds >= ioc->thresh_hold) {
1714                        if (ioc->combined_reply_queue) {
1715                                writel(reply_q->reply_post_host_index |
1716                                                ((msix_index  & 7) <<
1717                                                 MPI2_RPHI_MSIX_INDEX_SHIFT),
1718                                    ioc->replyPostRegisterIndex[msix_index/8]);
1719                        } else {
1720                                writel(reply_q->reply_post_host_index |
1721                                                (msix_index <<
1722                                                 MPI2_RPHI_MSIX_INDEX_SHIFT),
1723                                                &ioc->chip->ReplyPostHostIndex);
1724                        }
1725                        if (!reply_q->irq_poll_scheduled) {
1726                                reply_q->irq_poll_scheduled = true;
1727                                irq_poll_sched(&reply_q->irqpoll);
1728                        }
1729                        atomic_dec(&reply_q->busy);
1730                        return completed_cmds;
1731                }
1732                if (request_descript_type == MPI2_RPY_DESCRIPT_FLAGS_UNUSED)
1733                        goto out;
1734                if (!reply_q->reply_post_host_index)
1735                        rpf = reply_q->reply_post_free;
1736                else
1737                        rpf++;
1738        } while (1);
1739
1740 out:
1741
1742        if (!completed_cmds) {
1743                atomic_dec(&reply_q->busy);
1744                return completed_cmds;
1745        }
1746
1747        if (ioc->is_warpdrive) {
1748                writel(reply_q->reply_post_host_index,
1749                ioc->reply_post_host_index[msix_index]);
1750                atomic_dec(&reply_q->busy);
1751                return completed_cmds;
1752        }
1753
1754        /* Update Reply Post Host Index.
1755         * For those HBA's which support combined reply queue feature
1756         * 1. Get the correct Supplemental Reply Post Host Index Register.
1757         *    i.e. (msix_index / 8)th entry from Supplemental Reply Post Host
1758         *    Index Register address bank i.e replyPostRegisterIndex[],
1759         * 2. Then update this register with new reply host index value
1760         *    in ReplyPostIndex field and the MSIxIndex field with
1761         *    msix_index value reduced to a value between 0 and 7,
1762         *    using a modulo 8 operation. Since each Supplemental Reply Post
1763         *    Host Index Register supports 8 MSI-X vectors.
1764         *
1765         * For other HBA's just update the Reply Post Host Index register with
1766         * new reply host index value in ReplyPostIndex Field and msix_index
1767         * value in MSIxIndex field.
1768         */
1769        if (ioc->combined_reply_queue)
1770                writel(reply_q->reply_post_host_index | ((msix_index  & 7) <<
1771                        MPI2_RPHI_MSIX_INDEX_SHIFT),
1772                        ioc->replyPostRegisterIndex[msix_index/8]);
1773        else
1774                writel(reply_q->reply_post_host_index | (msix_index <<
1775                        MPI2_RPHI_MSIX_INDEX_SHIFT),
1776                        &ioc->chip->ReplyPostHostIndex);
1777        atomic_dec(&reply_q->busy);
1778        return completed_cmds;
1779}
1780
1781/**
1782 * _base_interrupt - MPT adapter (IOC) specific interrupt handler.
1783 * @irq: irq number (not used)
1784 * @bus_id: bus identifier cookie == pointer to MPT_ADAPTER structure
1785 *
1786 * Return: IRQ_HANDLED if processed, else IRQ_NONE.
1787 */
1788static irqreturn_t
1789_base_interrupt(int irq, void *bus_id)
1790{
1791        struct adapter_reply_queue *reply_q = bus_id;
1792        struct MPT3SAS_ADAPTER *ioc = reply_q->ioc;
1793
1794        if (ioc->mask_interrupts)
1795                return IRQ_NONE;
1796        if (reply_q->irq_poll_scheduled)
1797                return IRQ_HANDLED;
1798        return ((_base_process_reply_queue(reply_q) > 0) ?
1799                        IRQ_HANDLED : IRQ_NONE);
1800}
1801
1802/**
1803 * _base_irqpoll - IRQ poll callback handler
1804 * @irqpoll: irq_poll object
1805 * @budget: irq poll weight
1806 *
1807 * Return: number of reply descriptors processed
1808 */
1809static int
1810_base_irqpoll(struct irq_poll *irqpoll, int budget)
1811{
1812        struct adapter_reply_queue *reply_q;
1813        int num_entries = 0;
1814
1815        reply_q = container_of(irqpoll, struct adapter_reply_queue,
1816                        irqpoll);
1817        if (reply_q->irq_line_enable) {
1818                disable_irq_nosync(reply_q->os_irq);
1819                reply_q->irq_line_enable = false;
1820        }
1821        num_entries = _base_process_reply_queue(reply_q);
1822        if (num_entries < budget) {
1823                irq_poll_complete(irqpoll);
1824                reply_q->irq_poll_scheduled = false;
1825                reply_q->irq_line_enable = true;
1826                enable_irq(reply_q->os_irq);
1827                /*
1828                 * Go for one more round of processing the
1829                 * reply descriptor post queue in case the HBA
1830                 * Firmware has posted some reply descriptors
1831                 * while reenabling the IRQ.
1832                 */
1833                _base_process_reply_queue(reply_q);
1834        }
1835
1836        return num_entries;
1837}
1838
1839/**
1840 * _base_init_irqpolls - initliaze IRQ polls
1841 * @ioc: per adapter object
1842 *
1843 * Return: nothing
1844 */
1845static void
1846_base_init_irqpolls(struct MPT3SAS_ADAPTER *ioc)
1847{
1848        struct adapter_reply_queue *reply_q, *next;
1849
1850        if (list_empty(&ioc->reply_queue_list))
1851                return;
1852
1853        list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
1854                irq_poll_init(&reply_q->irqpoll,
1855                        ioc->hba_queue_depth/4, _base_irqpoll);
1856                reply_q->irq_poll_scheduled = false;
1857                reply_q->irq_line_enable = true;
1858                reply_q->os_irq = pci_irq_vector(ioc->pdev,
1859                    reply_q->msix_index);
1860        }
1861}
1862
1863/**
1864 * _base_is_controller_msix_enabled - is controller support muli-reply queues
1865 * @ioc: per adapter object
1866 *
1867 * Return: Whether or not MSI/X is enabled.
1868 */
1869static inline int
1870_base_is_controller_msix_enabled(struct MPT3SAS_ADAPTER *ioc)
1871{
1872        return (ioc->facts.IOCCapabilities &
1873            MPI2_IOCFACTS_CAPABILITY_MSI_X_INDEX) && ioc->msix_enable;
1874}
1875
1876/**
1877 * mpt3sas_base_sync_reply_irqs - flush pending MSIX interrupts
1878 * @ioc: per adapter object
1879 * @poll: poll over reply descriptor pools incase interrupt for
1880 *              timed-out SCSI command got delayed
1881 * Context: non-ISR context
1882 *
1883 * Called when a Task Management request has completed.
1884 */
1885void
1886mpt3sas_base_sync_reply_irqs(struct MPT3SAS_ADAPTER *ioc, u8 poll)
1887{
1888        struct adapter_reply_queue *reply_q;
1889
1890        /* If MSIX capability is turned off
1891         * then multi-queues are not enabled
1892         */
1893        if (!_base_is_controller_msix_enabled(ioc))
1894                return;
1895
1896        list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
1897                if (ioc->shost_recovery || ioc->remove_host ||
1898                                ioc->pci_error_recovery)
1899                        return;
1900                /* TMs are on msix_index == 0 */
1901                if (reply_q->msix_index == 0)
1902                        continue;
1903                synchronize_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index));
1904                if (reply_q->irq_poll_scheduled) {
1905                        /* Calling irq_poll_disable will wait for any pending
1906                         * callbacks to have completed.
1907                         */
1908                        irq_poll_disable(&reply_q->irqpoll);
1909                        irq_poll_enable(&reply_q->irqpoll);
1910                        /* check how the scheduled poll has ended,
1911                         * clean up only if necessary
1912                         */
1913                        if (reply_q->irq_poll_scheduled) {
1914                                reply_q->irq_poll_scheduled = false;
1915                                reply_q->irq_line_enable = true;
1916                                enable_irq(reply_q->os_irq);
1917                        }
1918                }
1919        }
1920        if (poll)
1921                _base_process_reply_queue(reply_q);
1922}
1923
1924/**
1925 * mpt3sas_base_release_callback_handler - clear interrupt callback handler
1926 * @cb_idx: callback index
1927 */
1928void
1929mpt3sas_base_release_callback_handler(u8 cb_idx)
1930{
1931        mpt_callbacks[cb_idx] = NULL;
1932}
1933
1934/**
1935 * mpt3sas_base_register_callback_handler - obtain index for the interrupt callback handler
1936 * @cb_func: callback function
1937 *
1938 * Return: Index of @cb_func.
1939 */
1940u8
1941mpt3sas_base_register_callback_handler(MPT_CALLBACK cb_func)
1942{
1943        u8 cb_idx;
1944
1945        for (cb_idx = MPT_MAX_CALLBACKS-1; cb_idx; cb_idx--)
1946                if (mpt_callbacks[cb_idx] == NULL)
1947                        break;
1948
1949        mpt_callbacks[cb_idx] = cb_func;
1950        return cb_idx;
1951}
1952
1953/**
1954 * mpt3sas_base_initialize_callback_handler - initialize the interrupt callback handler
1955 */
1956void
1957mpt3sas_base_initialize_callback_handler(void)
1958{
1959        u8 cb_idx;
1960
1961        for (cb_idx = 0; cb_idx < MPT_MAX_CALLBACKS; cb_idx++)
1962                mpt3sas_base_release_callback_handler(cb_idx);
1963}
1964
1965
1966/**
1967 * _base_build_zero_len_sge - build zero length sg entry
1968 * @ioc: per adapter object
1969 * @paddr: virtual address for SGE
1970 *
1971 * Create a zero length scatter gather entry to insure the IOCs hardware has
1972 * something to use if the target device goes brain dead and tries
1973 * to send data even when none is asked for.
1974 */
1975static void
1976_base_build_zero_len_sge(struct MPT3SAS_ADAPTER *ioc, void *paddr)
1977{
1978        u32 flags_length = (u32)((MPI2_SGE_FLAGS_LAST_ELEMENT |
1979            MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST |
1980            MPI2_SGE_FLAGS_SIMPLE_ELEMENT) <<
1981            MPI2_SGE_FLAGS_SHIFT);
1982        ioc->base_add_sg_single(paddr, flags_length, -1);
1983}
1984
1985/**
1986 * _base_add_sg_single_32 - Place a simple 32 bit SGE at address pAddr.
1987 * @paddr: virtual address for SGE
1988 * @flags_length: SGE flags and data transfer length
1989 * @dma_addr: Physical address
1990 */
1991static void
1992_base_add_sg_single_32(void *paddr, u32 flags_length, dma_addr_t dma_addr)
1993{
1994        Mpi2SGESimple32_t *sgel = paddr;
1995
1996        flags_length |= (MPI2_SGE_FLAGS_32_BIT_ADDRESSING |
1997            MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
1998        sgel->FlagsLength = cpu_to_le32(flags_length);
1999        sgel->Address = cpu_to_le32(dma_addr);
2000}
2001
2002
2003/**
2004 * _base_add_sg_single_64 - Place a simple 64 bit SGE at address pAddr.
2005 * @paddr: virtual address for SGE
2006 * @flags_length: SGE flags and data transfer length
2007 * @dma_addr: Physical address
2008 */
2009static void
2010_base_add_sg_single_64(void *paddr, u32 flags_length, dma_addr_t dma_addr)
2011{
2012        Mpi2SGESimple64_t *sgel = paddr;
2013
2014        flags_length |= (MPI2_SGE_FLAGS_64_BIT_ADDRESSING |
2015            MPI2_SGE_FLAGS_SYSTEM_ADDRESS) << MPI2_SGE_FLAGS_SHIFT;
2016        sgel->FlagsLength = cpu_to_le32(flags_length);
2017        sgel->Address = cpu_to_le64(dma_addr);
2018}
2019
2020/**
2021 * _base_get_chain_buffer_tracker - obtain chain tracker
2022 * @ioc: per adapter object
2023 * @scmd: SCSI commands of the IO request
2024 *
2025 * Return: chain tracker from chain_lookup table using key as
2026 * smid and smid's chain_offset.
2027 */
2028static struct chain_tracker *
2029_base_get_chain_buffer_tracker(struct MPT3SAS_ADAPTER *ioc,
2030                               struct scsi_cmnd *scmd)
2031{
2032        struct chain_tracker *chain_req;
2033        struct scsiio_tracker *st = scsi_cmd_priv(scmd);
2034        u16 smid = st->smid;
2035        u8 chain_offset =
2036           atomic_read(&ioc->chain_lookup[smid - 1].chain_offset);
2037
2038        if (chain_offset == ioc->chains_needed_per_io)
2039                return NULL;
2040
2041        chain_req = &ioc->chain_lookup[smid - 1].chains_per_smid[chain_offset];
2042        atomic_inc(&ioc->chain_lookup[smid - 1].chain_offset);
2043        return chain_req;
2044}
2045
2046
2047/**
2048 * _base_build_sg - build generic sg
2049 * @ioc: per adapter object
2050 * @psge: virtual address for SGE
2051 * @data_out_dma: physical address for WRITES
2052 * @data_out_sz: data xfer size for WRITES
2053 * @data_in_dma: physical address for READS
2054 * @data_in_sz: data xfer size for READS
2055 */
2056static void
2057_base_build_sg(struct MPT3SAS_ADAPTER *ioc, void *psge,
2058        dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2059        size_t data_in_sz)
2060{
2061        u32 sgl_flags;
2062
2063        if (!data_out_sz && !data_in_sz) {
2064                _base_build_zero_len_sge(ioc, psge);
2065                return;
2066        }
2067
2068        if (data_out_sz && data_in_sz) {
2069                /* WRITE sgel first */
2070                sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2071                    MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_HOST_TO_IOC);
2072                sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2073                ioc->base_add_sg_single(psge, sgl_flags |
2074                    data_out_sz, data_out_dma);
2075
2076                /* incr sgel */
2077                psge += ioc->sge_size;
2078
2079                /* READ sgel last */
2080                sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2081                    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2082                    MPI2_SGE_FLAGS_END_OF_LIST);
2083                sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2084                ioc->base_add_sg_single(psge, sgl_flags |
2085                    data_in_sz, data_in_dma);
2086        } else if (data_out_sz) /* WRITE */ {
2087                sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2088                    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2089                    MPI2_SGE_FLAGS_END_OF_LIST | MPI2_SGE_FLAGS_HOST_TO_IOC);
2090                sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2091                ioc->base_add_sg_single(psge, sgl_flags |
2092                    data_out_sz, data_out_dma);
2093        } else if (data_in_sz) /* READ */ {
2094                sgl_flags = (MPI2_SGE_FLAGS_SIMPLE_ELEMENT |
2095                    MPI2_SGE_FLAGS_LAST_ELEMENT | MPI2_SGE_FLAGS_END_OF_BUFFER |
2096                    MPI2_SGE_FLAGS_END_OF_LIST);
2097                sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2098                ioc->base_add_sg_single(psge, sgl_flags |
2099                    data_in_sz, data_in_dma);
2100        }
2101}
2102
2103/* IEEE format sgls */
2104
2105/**
2106 * _base_build_nvme_prp - This function is called for NVMe end devices to build
2107 *                        a native SGL (NVMe PRP).
2108 * @ioc: per adapter object
2109 * @smid: system request message index for getting asscociated SGL
2110 * @nvme_encap_request: the NVMe request msg frame pointer
2111 * @data_out_dma: physical address for WRITES
2112 * @data_out_sz: data xfer size for WRITES
2113 * @data_in_dma: physical address for READS
2114 * @data_in_sz: data xfer size for READS
2115 *
2116 * The native SGL is built starting in the first PRP
2117 * entry of the NVMe message (PRP1).  If the data buffer is small enough to be
2118 * described entirely using PRP1, then PRP2 is not used.  If needed, PRP2 is
2119 * used to describe a larger data buffer.  If the data buffer is too large to
2120 * describe using the two PRP entriess inside the NVMe message, then PRP1
2121 * describes the first data memory segment, and PRP2 contains a pointer to a PRP
2122 * list located elsewhere in memory to describe the remaining data memory
2123 * segments.  The PRP list will be contiguous.
2124 *
2125 * The native SGL for NVMe devices is a Physical Region Page (PRP).  A PRP
2126 * consists of a list of PRP entries to describe a number of noncontigous
2127 * physical memory segments as a single memory buffer, just as a SGL does.  Note
2128 * however, that this function is only used by the IOCTL call, so the memory
2129 * given will be guaranteed to be contiguous.  There is no need to translate
2130 * non-contiguous SGL into a PRP in this case.  All PRPs will describe
2131 * contiguous space that is one page size each.
2132 *
2133 * Each NVMe message contains two PRP entries.  The first (PRP1) either contains
2134 * a PRP list pointer or a PRP element, depending upon the command.  PRP2
2135 * contains the second PRP element if the memory being described fits within 2
2136 * PRP entries, or a PRP list pointer if the PRP spans more than two entries.
2137 *
2138 * A PRP list pointer contains the address of a PRP list, structured as a linear
2139 * array of PRP entries.  Each PRP entry in this list describes a segment of
2140 * physical memory.
2141 *
2142 * Each 64-bit PRP entry comprises an address and an offset field.  The address
2143 * always points at the beginning of a 4KB physical memory page, and the offset
2144 * describes where within that 4KB page the memory segment begins.  Only the
2145 * first element in a PRP list may contain a non-zero offset, implying that all
2146 * memory segments following the first begin at the start of a 4KB page.
2147 *
2148 * Each PRP element normally describes 4KB of physical memory, with exceptions
2149 * for the first and last elements in the list.  If the memory being described
2150 * by the list begins at a non-zero offset within the first 4KB page, then the
2151 * first PRP element will contain a non-zero offset indicating where the region
2152 * begins within the 4KB page.  The last memory segment may end before the end
2153 * of the 4KB segment, depending upon the overall size of the memory being
2154 * described by the PRP list.
2155 *
2156 * Since PRP entries lack any indication of size, the overall data buffer length
2157 * is used to determine where the end of the data memory buffer is located, and
2158 * how many PRP entries are required to describe it.
2159 */
2160static void
2161_base_build_nvme_prp(struct MPT3SAS_ADAPTER *ioc, u16 smid,
2162        Mpi26NVMeEncapsulatedRequest_t *nvme_encap_request,
2163        dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2164        size_t data_in_sz)
2165{
2166        int             prp_size = NVME_PRP_SIZE;
2167        __le64          *prp_entry, *prp1_entry, *prp2_entry;
2168        __le64          *prp_page;
2169        dma_addr_t      prp_entry_dma, prp_page_dma, dma_addr;
2170        u32             offset, entry_len;
2171        u32             page_mask_result, page_mask;
2172        size_t          length;
2173        struct mpt3sas_nvme_cmd *nvme_cmd =
2174                (void *)nvme_encap_request->NVMe_Command;
2175
2176        /*
2177         * Not all commands require a data transfer. If no data, just return
2178         * without constructing any PRP.
2179         */
2180        if (!data_in_sz && !data_out_sz)
2181                return;
2182        prp1_entry = &nvme_cmd->prp1;
2183        prp2_entry = &nvme_cmd->prp2;
2184        prp_entry = prp1_entry;
2185        /*
2186         * For the PRP entries, use the specially allocated buffer of
2187         * contiguous memory.
2188         */
2189        prp_page = (__le64 *)mpt3sas_base_get_pcie_sgl(ioc, smid);
2190        prp_page_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2191
2192        /*
2193         * Check if we are within 1 entry of a page boundary we don't
2194         * want our first entry to be a PRP List entry.
2195         */
2196        page_mask = ioc->page_size - 1;
2197        page_mask_result = (uintptr_t)((u8 *)prp_page + prp_size) & page_mask;
2198        if (!page_mask_result) {
2199                /* Bump up to next page boundary. */
2200                prp_page = (__le64 *)((u8 *)prp_page + prp_size);
2201                prp_page_dma = prp_page_dma + prp_size;
2202        }
2203
2204        /*
2205         * Set PRP physical pointer, which initially points to the current PRP
2206         * DMA memory page.
2207         */
2208        prp_entry_dma = prp_page_dma;
2209
2210        /* Get physical address and length of the data buffer. */
2211        if (data_in_sz) {
2212                dma_addr = data_in_dma;
2213                length = data_in_sz;
2214        } else {
2215                dma_addr = data_out_dma;
2216                length = data_out_sz;
2217        }
2218
2219        /* Loop while the length is not zero. */
2220        while (length) {
2221                /*
2222                 * Check if we need to put a list pointer here if we are at
2223                 * page boundary - prp_size (8 bytes).
2224                 */
2225                page_mask_result = (prp_entry_dma + prp_size) & page_mask;
2226                if (!page_mask_result) {
2227                        /*
2228                         * This is the last entry in a PRP List, so we need to
2229                         * put a PRP list pointer here.  What this does is:
2230                         *   - bump the current memory pointer to the next
2231                         *     address, which will be the next full page.
2232                         *   - set the PRP Entry to point to that page.  This
2233                         *     is now the PRP List pointer.
2234                         *   - bump the PRP Entry pointer the start of the
2235                         *     next page.  Since all of this PRP memory is
2236                         *     contiguous, no need to get a new page - it's
2237                         *     just the next address.
2238                         */
2239                        prp_entry_dma++;
2240                        *prp_entry = cpu_to_le64(prp_entry_dma);
2241                        prp_entry++;
2242                }
2243
2244                /* Need to handle if entry will be part of a page. */
2245                offset = dma_addr & page_mask;
2246                entry_len = ioc->page_size - offset;
2247
2248                if (prp_entry == prp1_entry) {
2249                        /*
2250                         * Must fill in the first PRP pointer (PRP1) before
2251                         * moving on.
2252                         */
2253                        *prp1_entry = cpu_to_le64(dma_addr);
2254
2255                        /*
2256                         * Now point to the second PRP entry within the
2257                         * command (PRP2).
2258                         */
2259                        prp_entry = prp2_entry;
2260                } else if (prp_entry == prp2_entry) {
2261                        /*
2262                         * Should the PRP2 entry be a PRP List pointer or just
2263                         * a regular PRP pointer?  If there is more than one
2264                         * more page of data, must use a PRP List pointer.
2265                         */
2266                        if (length > ioc->page_size) {
2267                                /*
2268                                 * PRP2 will contain a PRP List pointer because
2269                                 * more PRP's are needed with this command. The
2270                                 * list will start at the beginning of the
2271                                 * contiguous buffer.
2272                                 */
2273                                *prp2_entry = cpu_to_le64(prp_entry_dma);
2274
2275                                /*
2276                                 * The next PRP Entry will be the start of the
2277                                 * first PRP List.
2278                                 */
2279                                prp_entry = prp_page;
2280                        } else {
2281                                /*
2282                                 * After this, the PRP Entries are complete.
2283                                 * This command uses 2 PRP's and no PRP list.
2284                                 */
2285                                *prp2_entry = cpu_to_le64(dma_addr);
2286                        }
2287                } else {
2288                        /*
2289                         * Put entry in list and bump the addresses.
2290                         *
2291                         * After PRP1 and PRP2 are filled in, this will fill in
2292                         * all remaining PRP entries in a PRP List, one per
2293                         * each time through the loop.
2294                         */
2295                        *prp_entry = cpu_to_le64(dma_addr);
2296                        prp_entry++;
2297                        prp_entry_dma++;
2298                }
2299
2300                /*
2301                 * Bump the phys address of the command's data buffer by the
2302                 * entry_len.
2303                 */
2304                dma_addr += entry_len;
2305
2306                /* Decrement length accounting for last partial page. */
2307                if (entry_len > length)
2308                        length = 0;
2309                else
2310                        length -= entry_len;
2311        }
2312}
2313
2314/**
2315 * base_make_prp_nvme - Prepare PRPs (Physical Region Page) -
2316 *                      SGLs specific to NVMe drives only
2317 *
2318 * @ioc:                per adapter object
2319 * @scmd:               SCSI command from the mid-layer
2320 * @mpi_request:        mpi request
2321 * @smid:               msg Index
2322 * @sge_count:          scatter gather element count.
2323 *
2324 * Return:              true: PRPs are built
2325 *                      false: IEEE SGLs needs to be built
2326 */
2327static void
2328base_make_prp_nvme(struct MPT3SAS_ADAPTER *ioc,
2329                struct scsi_cmnd *scmd,
2330                Mpi25SCSIIORequest_t *mpi_request,
2331                u16 smid, int sge_count)
2332{
2333        int sge_len, num_prp_in_chain = 0;
2334        Mpi25IeeeSgeChain64_t *main_chain_element, *ptr_first_sgl;
2335        __le64 *curr_buff;
2336        dma_addr_t msg_dma, sge_addr, offset;
2337        u32 page_mask, page_mask_result;
2338        struct scatterlist *sg_scmd;
2339        u32 first_prp_len;
2340        int data_len = scsi_bufflen(scmd);
2341        u32 nvme_pg_size;
2342
2343        nvme_pg_size = max_t(u32, ioc->page_size, NVME_PRP_PAGE_SIZE);
2344        /*
2345         * Nvme has a very convoluted prp format.  One prp is required
2346         * for each page or partial page. Driver need to split up OS sg_list
2347         * entries if it is longer than one page or cross a page
2348         * boundary.  Driver also have to insert a PRP list pointer entry as
2349         * the last entry in each physical page of the PRP list.
2350         *
2351         * NOTE: The first PRP "entry" is actually placed in the first
2352         * SGL entry in the main message as IEEE 64 format.  The 2nd
2353         * entry in the main message is the chain element, and the rest
2354         * of the PRP entries are built in the contiguous pcie buffer.
2355         */
2356        page_mask = nvme_pg_size - 1;
2357
2358        /*
2359         * Native SGL is needed.
2360         * Put a chain element in main message frame that points to the first
2361         * chain buffer.
2362         *
2363         * NOTE:  The ChainOffset field must be 0 when using a chain pointer to
2364         *        a native SGL.
2365         */
2366
2367        /* Set main message chain element pointer */
2368        main_chain_element = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2369        /*
2370         * For NVMe the chain element needs to be the 2nd SG entry in the main
2371         * message.
2372         */
2373        main_chain_element = (Mpi25IeeeSgeChain64_t *)
2374                ((u8 *)main_chain_element + sizeof(MPI25_IEEE_SGE_CHAIN64));
2375
2376        /*
2377         * For the PRP entries, use the specially allocated buffer of
2378         * contiguous memory.  Normal chain buffers can't be used
2379         * because each chain buffer would need to be the size of an OS
2380         * page (4k).
2381         */
2382        curr_buff = mpt3sas_base_get_pcie_sgl(ioc, smid);
2383        msg_dma = mpt3sas_base_get_pcie_sgl_dma(ioc, smid);
2384
2385        main_chain_element->Address = cpu_to_le64(msg_dma);
2386        main_chain_element->NextChainOffset = 0;
2387        main_chain_element->Flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2388                        MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2389                        MPI26_IEEE_SGE_FLAGS_NSF_NVME_PRP;
2390
2391        /* Build first prp, sge need not to be page aligned*/
2392        ptr_first_sgl = (pMpi25IeeeSgeChain64_t)&mpi_request->SGL;
2393        sg_scmd = scsi_sglist(scmd);
2394        sge_addr = sg_dma_address(sg_scmd);
2395        sge_len = sg_dma_len(sg_scmd);
2396
2397        offset = sge_addr & page_mask;
2398        first_prp_len = nvme_pg_size - offset;
2399
2400        ptr_first_sgl->Address = cpu_to_le64(sge_addr);
2401        ptr_first_sgl->Length = cpu_to_le32(first_prp_len);
2402
2403        data_len -= first_prp_len;
2404
2405        if (sge_len > first_prp_len) {
2406                sge_addr += first_prp_len;
2407                sge_len -= first_prp_len;
2408        } else if (data_len && (sge_len == first_prp_len)) {
2409                sg_scmd = sg_next(sg_scmd);
2410                sge_addr = sg_dma_address(sg_scmd);
2411                sge_len = sg_dma_len(sg_scmd);
2412        }
2413
2414        for (;;) {
2415                offset = sge_addr & page_mask;
2416
2417                /* Put PRP pointer due to page boundary*/
2418                page_mask_result = (uintptr_t)(curr_buff + 1) & page_mask;
2419                if (unlikely(!page_mask_result)) {
2420                        scmd_printk(KERN_NOTICE,
2421                                scmd, "page boundary curr_buff: 0x%p\n",
2422                                curr_buff);
2423                        msg_dma += 8;
2424                        *curr_buff = cpu_to_le64(msg_dma);
2425                        curr_buff++;
2426                        num_prp_in_chain++;
2427                }
2428
2429                *curr_buff = cpu_to_le64(sge_addr);
2430                curr_buff++;
2431                msg_dma += 8;
2432                num_prp_in_chain++;
2433
2434                sge_addr += nvme_pg_size;
2435                sge_len -= nvme_pg_size;
2436                data_len -= nvme_pg_size;
2437
2438                if (data_len <= 0)
2439                        break;
2440
2441                if (sge_len > 0)
2442                        continue;
2443
2444                sg_scmd = sg_next(sg_scmd);
2445                sge_addr = sg_dma_address(sg_scmd);
2446                sge_len = sg_dma_len(sg_scmd);
2447        }
2448
2449        main_chain_element->Length =
2450                cpu_to_le32(num_prp_in_chain * sizeof(u64));
2451        return;
2452}
2453
2454static bool
2455base_is_prp_possible(struct MPT3SAS_ADAPTER *ioc,
2456        struct _pcie_device *pcie_device, struct scsi_cmnd *scmd, int sge_count)
2457{
2458        u32 data_length = 0;
2459        bool build_prp = true;
2460
2461        data_length = scsi_bufflen(scmd);
2462        if (pcie_device &&
2463            (mpt3sas_scsih_is_pcie_scsi_device(pcie_device->device_info))) {
2464                build_prp = false;
2465                return build_prp;
2466        }
2467
2468        /* If Datalenth is <= 16K and number of SGE’s entries are <= 2
2469         * we built IEEE SGL
2470         */
2471        if ((data_length <= NVME_PRP_PAGE_SIZE*4) && (sge_count <= 2))
2472                build_prp = false;
2473
2474        return build_prp;
2475}
2476
2477/**
2478 * _base_check_pcie_native_sgl - This function is called for PCIe end devices to
2479 * determine if the driver needs to build a native SGL.  If so, that native
2480 * SGL is built in the special contiguous buffers allocated especially for
2481 * PCIe SGL creation.  If the driver will not build a native SGL, return
2482 * TRUE and a normal IEEE SGL will be built.  Currently this routine
2483 * supports NVMe.
2484 * @ioc: per adapter object
2485 * @mpi_request: mf request pointer
2486 * @smid: system request message index
2487 * @scmd: scsi command
2488 * @pcie_device: points to the PCIe device's info
2489 *
2490 * Return: 0 if native SGL was built, 1 if no SGL was built
2491 */
2492static int
2493_base_check_pcie_native_sgl(struct MPT3SAS_ADAPTER *ioc,
2494        Mpi25SCSIIORequest_t *mpi_request, u16 smid, struct scsi_cmnd *scmd,
2495        struct _pcie_device *pcie_device)
2496{
2497        int sges_left;
2498
2499        /* Get the SG list pointer and info. */
2500        sges_left = scsi_dma_map(scmd);
2501        if (sges_left < 0) {
2502                sdev_printk(KERN_ERR, scmd->device,
2503                        "scsi_dma_map failed: request for %d bytes!\n",
2504                        scsi_bufflen(scmd));
2505                return 1;
2506        }
2507
2508        /* Check if we need to build a native SG list. */
2509        if (!base_is_prp_possible(ioc, pcie_device,
2510                                scmd, sges_left)) {
2511                /* We built a native SG list, just return. */
2512                goto out;
2513        }
2514
2515        /*
2516         * Build native NVMe PRP.
2517         */
2518        base_make_prp_nvme(ioc, scmd, mpi_request,
2519                        smid, sges_left);
2520
2521        return 0;
2522out:
2523        scsi_dma_unmap(scmd);
2524        return 1;
2525}
2526
2527/**
2528 * _base_add_sg_single_ieee - add sg element for IEEE format
2529 * @paddr: virtual address for SGE
2530 * @flags: SGE flags
2531 * @chain_offset: number of 128 byte elements from start of segment
2532 * @length: data transfer length
2533 * @dma_addr: Physical address
2534 */
2535static void
2536_base_add_sg_single_ieee(void *paddr, u8 flags, u8 chain_offset, u32 length,
2537        dma_addr_t dma_addr)
2538{
2539        Mpi25IeeeSgeChain64_t *sgel = paddr;
2540
2541        sgel->Flags = flags;
2542        sgel->NextChainOffset = chain_offset;
2543        sgel->Length = cpu_to_le32(length);
2544        sgel->Address = cpu_to_le64(dma_addr);
2545}
2546
2547/**
2548 * _base_build_zero_len_sge_ieee - build zero length sg entry for IEEE format
2549 * @ioc: per adapter object
2550 * @paddr: virtual address for SGE
2551 *
2552 * Create a zero length scatter gather entry to insure the IOCs hardware has
2553 * something to use if the target device goes brain dead and tries
2554 * to send data even when none is asked for.
2555 */
2556static void
2557_base_build_zero_len_sge_ieee(struct MPT3SAS_ADAPTER *ioc, void *paddr)
2558{
2559        u8 sgl_flags = (MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2560                MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR |
2561                MPI25_IEEE_SGE_FLAGS_END_OF_LIST);
2562
2563        _base_add_sg_single_ieee(paddr, sgl_flags, 0, 0, -1);
2564}
2565
2566/**
2567 * _base_build_sg_scmd - main sg creation routine
2568 *              pcie_device is unused here!
2569 * @ioc: per adapter object
2570 * @scmd: scsi command
2571 * @smid: system request message index
2572 * @unused: unused pcie_device pointer
2573 * Context: none.
2574 *
2575 * The main routine that builds scatter gather table from a given
2576 * scsi request sent via the .queuecommand main handler.
2577 *
2578 * Return: 0 success, anything else error
2579 */
2580static int
2581_base_build_sg_scmd(struct MPT3SAS_ADAPTER *ioc,
2582        struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *unused)
2583{
2584        Mpi2SCSIIORequest_t *mpi_request;
2585        dma_addr_t chain_dma;
2586        struct scatterlist *sg_scmd;
2587        void *sg_local, *chain;
2588        u32 chain_offset;
2589        u32 chain_length;
2590        u32 chain_flags;
2591        int sges_left;
2592        u32 sges_in_segment;
2593        u32 sgl_flags;
2594        u32 sgl_flags_last_element;
2595        u32 sgl_flags_end_buffer;
2596        struct chain_tracker *chain_req;
2597
2598        mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2599
2600        /* init scatter gather flags */
2601        sgl_flags = MPI2_SGE_FLAGS_SIMPLE_ELEMENT;
2602        if (scmd->sc_data_direction == DMA_TO_DEVICE)
2603                sgl_flags |= MPI2_SGE_FLAGS_HOST_TO_IOC;
2604        sgl_flags_last_element = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT)
2605            << MPI2_SGE_FLAGS_SHIFT;
2606        sgl_flags_end_buffer = (sgl_flags | MPI2_SGE_FLAGS_LAST_ELEMENT |
2607            MPI2_SGE_FLAGS_END_OF_BUFFER | MPI2_SGE_FLAGS_END_OF_LIST)
2608            << MPI2_SGE_FLAGS_SHIFT;
2609        sgl_flags = sgl_flags << MPI2_SGE_FLAGS_SHIFT;
2610
2611        sg_scmd = scsi_sglist(scmd);
2612        sges_left = scsi_dma_map(scmd);
2613        if (sges_left < 0) {
2614                sdev_printk(KERN_ERR, scmd->device,
2615                 "scsi_dma_map failed: request for %d bytes!\n",
2616                 scsi_bufflen(scmd));
2617                return -ENOMEM;
2618        }
2619
2620        sg_local = &mpi_request->SGL;
2621        sges_in_segment = ioc->max_sges_in_main_message;
2622        if (sges_left <= sges_in_segment)
2623                goto fill_in_last_segment;
2624
2625        mpi_request->ChainOffset = (offsetof(Mpi2SCSIIORequest_t, SGL) +
2626            (sges_in_segment * ioc->sge_size))/4;
2627
2628        /* fill in main message segment when there is a chain following */
2629        while (sges_in_segment) {
2630                if (sges_in_segment == 1)
2631                        ioc->base_add_sg_single(sg_local,
2632                            sgl_flags_last_element | sg_dma_len(sg_scmd),
2633                            sg_dma_address(sg_scmd));
2634                else
2635                        ioc->base_add_sg_single(sg_local, sgl_flags |
2636                            sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2637                sg_scmd = sg_next(sg_scmd);
2638                sg_local += ioc->sge_size;
2639                sges_left--;
2640                sges_in_segment--;
2641        }
2642
2643        /* initializing the chain flags and pointers */
2644        chain_flags = MPI2_SGE_FLAGS_CHAIN_ELEMENT << MPI2_SGE_FLAGS_SHIFT;
2645        chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2646        if (!chain_req)
2647                return -1;
2648        chain = chain_req->chain_buffer;
2649        chain_dma = chain_req->chain_buffer_dma;
2650        do {
2651                sges_in_segment = (sges_left <=
2652                    ioc->max_sges_in_chain_message) ? sges_left :
2653                    ioc->max_sges_in_chain_message;
2654                chain_offset = (sges_left == sges_in_segment) ?
2655                    0 : (sges_in_segment * ioc->sge_size)/4;
2656                chain_length = sges_in_segment * ioc->sge_size;
2657                if (chain_offset) {
2658                        chain_offset = chain_offset <<
2659                            MPI2_SGE_CHAIN_OFFSET_SHIFT;
2660                        chain_length += ioc->sge_size;
2661                }
2662                ioc->base_add_sg_single(sg_local, chain_flags | chain_offset |
2663                    chain_length, chain_dma);
2664                sg_local = chain;
2665                if (!chain_offset)
2666                        goto fill_in_last_segment;
2667
2668                /* fill in chain segments */
2669                while (sges_in_segment) {
2670                        if (sges_in_segment == 1)
2671                                ioc->base_add_sg_single(sg_local,
2672                                    sgl_flags_last_element |
2673                                    sg_dma_len(sg_scmd),
2674                                    sg_dma_address(sg_scmd));
2675                        else
2676                                ioc->base_add_sg_single(sg_local, sgl_flags |
2677                                    sg_dma_len(sg_scmd),
2678                                    sg_dma_address(sg_scmd));
2679                        sg_scmd = sg_next(sg_scmd);
2680                        sg_local += ioc->sge_size;
2681                        sges_left--;
2682                        sges_in_segment--;
2683                }
2684
2685                chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2686                if (!chain_req)
2687                        return -1;
2688                chain = chain_req->chain_buffer;
2689                chain_dma = chain_req->chain_buffer_dma;
2690        } while (1);
2691
2692
2693 fill_in_last_segment:
2694
2695        /* fill the last segment */
2696        while (sges_left) {
2697                if (sges_left == 1)
2698                        ioc->base_add_sg_single(sg_local, sgl_flags_end_buffer |
2699                            sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2700                else
2701                        ioc->base_add_sg_single(sg_local, sgl_flags |
2702                            sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2703                sg_scmd = sg_next(sg_scmd);
2704                sg_local += ioc->sge_size;
2705                sges_left--;
2706        }
2707
2708        return 0;
2709}
2710
2711/**
2712 * _base_build_sg_scmd_ieee - main sg creation routine for IEEE format
2713 * @ioc: per adapter object
2714 * @scmd: scsi command
2715 * @smid: system request message index
2716 * @pcie_device: Pointer to pcie_device. If set, the pcie native sgl will be
2717 * constructed on need.
2718 * Context: none.
2719 *
2720 * The main routine that builds scatter gather table from a given
2721 * scsi request sent via the .queuecommand main handler.
2722 *
2723 * Return: 0 success, anything else error
2724 */
2725static int
2726_base_build_sg_scmd_ieee(struct MPT3SAS_ADAPTER *ioc,
2727        struct scsi_cmnd *scmd, u16 smid, struct _pcie_device *pcie_device)
2728{
2729        Mpi25SCSIIORequest_t *mpi_request;
2730        dma_addr_t chain_dma;
2731        struct scatterlist *sg_scmd;
2732        void *sg_local, *chain;
2733        u32 chain_offset;
2734        u32 chain_length;
2735        int sges_left;
2736        u32 sges_in_segment;
2737        u8 simple_sgl_flags;
2738        u8 simple_sgl_flags_last;
2739        u8 chain_sgl_flags;
2740        struct chain_tracker *chain_req;
2741
2742        mpi_request = mpt3sas_base_get_msg_frame(ioc, smid);
2743
2744        /* init scatter gather flags */
2745        simple_sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2746            MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2747        simple_sgl_flags_last = simple_sgl_flags |
2748            MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2749        chain_sgl_flags = MPI2_IEEE_SGE_FLAGS_CHAIN_ELEMENT |
2750            MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2751
2752        /* Check if we need to build a native SG list. */
2753        if ((pcie_device) && (_base_check_pcie_native_sgl(ioc, mpi_request,
2754                        smid, scmd, pcie_device) == 0)) {
2755                /* We built a native SG list, just return. */
2756                return 0;
2757        }
2758
2759        sg_scmd = scsi_sglist(scmd);
2760        sges_left = scsi_dma_map(scmd);
2761        if (sges_left < 0) {
2762                sdev_printk(KERN_ERR, scmd->device,
2763                        "scsi_dma_map failed: request for %d bytes!\n",
2764                        scsi_bufflen(scmd));
2765                return -ENOMEM;
2766        }
2767
2768        sg_local = &mpi_request->SGL;
2769        sges_in_segment = (ioc->request_sz -
2770                   offsetof(Mpi25SCSIIORequest_t, SGL))/ioc->sge_size_ieee;
2771        if (sges_left <= sges_in_segment)
2772                goto fill_in_last_segment;
2773
2774        mpi_request->ChainOffset = (sges_in_segment - 1 /* chain element */) +
2775            (offsetof(Mpi25SCSIIORequest_t, SGL)/ioc->sge_size_ieee);
2776
2777        /* fill in main message segment when there is a chain following */
2778        while (sges_in_segment > 1) {
2779                _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2780                    sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2781                sg_scmd = sg_next(sg_scmd);
2782                sg_local += ioc->sge_size_ieee;
2783                sges_left--;
2784                sges_in_segment--;
2785        }
2786
2787        /* initializing the pointers */
2788        chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2789        if (!chain_req)
2790                return -1;
2791        chain = chain_req->chain_buffer;
2792        chain_dma = chain_req->chain_buffer_dma;
2793        do {
2794                sges_in_segment = (sges_left <=
2795                    ioc->max_sges_in_chain_message) ? sges_left :
2796                    ioc->max_sges_in_chain_message;
2797                chain_offset = (sges_left == sges_in_segment) ?
2798                    0 : sges_in_segment;
2799                chain_length = sges_in_segment * ioc->sge_size_ieee;
2800                if (chain_offset)
2801                        chain_length += ioc->sge_size_ieee;
2802                _base_add_sg_single_ieee(sg_local, chain_sgl_flags,
2803                    chain_offset, chain_length, chain_dma);
2804
2805                sg_local = chain;
2806                if (!chain_offset)
2807                        goto fill_in_last_segment;
2808
2809                /* fill in chain segments */
2810                while (sges_in_segment) {
2811                        _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2812                            sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2813                        sg_scmd = sg_next(sg_scmd);
2814                        sg_local += ioc->sge_size_ieee;
2815                        sges_left--;
2816                        sges_in_segment--;
2817                }
2818
2819                chain_req = _base_get_chain_buffer_tracker(ioc, scmd);
2820                if (!chain_req)
2821                        return -1;
2822                chain = chain_req->chain_buffer;
2823                chain_dma = chain_req->chain_buffer_dma;
2824        } while (1);
2825
2826
2827 fill_in_last_segment:
2828
2829        /* fill the last segment */
2830        while (sges_left > 0) {
2831                if (sges_left == 1)
2832                        _base_add_sg_single_ieee(sg_local,
2833                            simple_sgl_flags_last, 0, sg_dma_len(sg_scmd),
2834                            sg_dma_address(sg_scmd));
2835                else
2836                        _base_add_sg_single_ieee(sg_local, simple_sgl_flags, 0,
2837                            sg_dma_len(sg_scmd), sg_dma_address(sg_scmd));
2838                sg_scmd = sg_next(sg_scmd);
2839                sg_local += ioc->sge_size_ieee;
2840                sges_left--;
2841        }
2842
2843        return 0;
2844}
2845
2846/**
2847 * _base_build_sg_ieee - build generic sg for IEEE format
2848 * @ioc: per adapter object
2849 * @psge: virtual address for SGE
2850 * @data_out_dma: physical address for WRITES
2851 * @data_out_sz: data xfer size for WRITES
2852 * @data_in_dma: physical address for READS
2853 * @data_in_sz: data xfer size for READS
2854 */
2855static void
2856_base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
2857        dma_addr_t data_out_dma, size_t data_out_sz, dma_addr_t data_in_dma,
2858        size_t data_in_sz)
2859{
2860        u8 sgl_flags;
2861
2862        if (!data_out_sz && !data_in_sz) {
2863                _base_build_zero_len_sge_ieee(ioc, psge);
2864                return;
2865        }
2866
2867        if (data_out_sz && data_in_sz) {
2868                /* WRITE sgel first */
2869                sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2870                    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2871                _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2872                    data_out_dma);
2873
2874                /* incr sgel */
2875                psge += ioc->sge_size_ieee;
2876
2877                /* READ sgel last */
2878                sgl_flags |= MPI25_IEEE_SGE_FLAGS_END_OF_LIST;
2879                _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2880                    data_in_dma);
2881        } else if (data_out_sz) /* WRITE */ {
2882                sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2883                    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2884                    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2885                _base_add_sg_single_ieee(psge, sgl_flags, 0, data_out_sz,
2886                    data_out_dma);
2887        } else if (data_in_sz) /* READ */ {
2888                sgl_flags = MPI2_IEEE_SGE_FLAGS_SIMPLE_ELEMENT |
2889                    MPI25_IEEE_SGE_FLAGS_END_OF_LIST |
2890                    MPI2_IEEE_SGE_FLAGS_SYSTEM_ADDR;
2891                _base_add_sg_single_ieee(psge, sgl_flags, 0, data_in_sz,
2892                    data_in_dma);
2893        }
2894}
2895
2896#define convert_to_kb(x) ((x) << (PAGE_SHIFT - 10))
2897
2898/**
2899 * _base_config_dma_addressing - set dma addressing
2900 * @ioc: per adapter object
2901 * @pdev: PCI device struct
2902 *
2903 * Return: 0 for success, non-zero for failure.
2904 */
2905static int
2906_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
2907{
2908        struct sysinfo s;
2909
2910        if (ioc->is_mcpu_endpoint ||
2911            sizeof(dma_addr_t) == 4 || ioc->use_32bit_dma ||
2912            dma_get_required_mask(&pdev->dev) <= 32)
2913                ioc->dma_mask = 32;
2914        /* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
2915        else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
2916                ioc->dma_mask = 63;
2917        else
2918                ioc->dma_mask = 64;
2919
2920        if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)) ||
2921            dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(ioc->dma_mask)))
2922                return -ENODEV;
2923
2924        if (ioc->dma_mask > 32) {
2925                ioc->base_add_sg_single = &_base_add_sg_single_64;
2926                ioc->sge_size = sizeof(Mpi2SGESimple64_t);
2927        } else {
2928                ioc->base_add_sg_single = &_base_add_sg_single_32;
2929                ioc->sge_size = sizeof(Mpi2SGESimple32_t);
2930        }
2931
2932        si_meminfo(&s);
2933        ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
2934                ioc->dma_mask, convert_to_kb(s.totalram));
2935
2936        return 0;
2937}
2938
2939/**
2940 * _base_check_enable_msix - checks MSIX capabable.
2941 * @ioc: per adapter object
2942 *
2943 * Check to see if card is capable of MSIX, and set number
2944 * of available msix vectors
2945 */
2946static int
2947_base_check_enable_msix(struct MPT3SAS_ADAPTER *ioc)
2948{
2949        int base;
2950        u16 message_control;
2951
2952        /* Check whether controller SAS2008 B0 controller,
2953         * if it is SAS2008 B0 controller use IO-APIC instead of MSIX
2954         */
2955        if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 &&
2956            ioc->pdev->revision == SAS2_PCI_DEVICE_B0_REVISION) {
2957                return -EINVAL;
2958        }
2959
2960        base = pci_find_capability(ioc->pdev, PCI_CAP_ID_MSIX);
2961        if (!base) {
2962                dfailprintk(ioc, ioc_info(ioc, "msix not supported\n"));
2963                return -EINVAL;
2964        }
2965
2966        /* get msix vector count */
2967        /* NUMA_IO not supported for older controllers */
2968        if (ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2004 ||
2969            ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2008 ||
2970            ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_1 ||
2971            ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_2 ||
2972            ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2108_3 ||
2973            ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_1 ||
2974            ioc->pdev->device == MPI2_MFGPAGE_DEVID_SAS2116_2)
2975                ioc->msix_vector_count = 1;
2976        else {
2977                pci_read_config_word(ioc->pdev, base + 2, &message_control);
2978                ioc->msix_vector_count = (message_control & 0x3FF) + 1;
2979        }
2980        dinitprintk(ioc, ioc_info(ioc, "msix is supported, vector_count(%d)\n",
2981                                  ioc->msix_vector_count));
2982        return 0;
2983}
2984
2985/**
2986 * mpt3sas_base_free_irq - free irq
2987 * @ioc: per adapter object
2988 *
2989 * Freeing respective reply_queue from the list.
2990 */
2991void
2992mpt3sas_base_free_irq(struct MPT3SAS_ADAPTER *ioc)
2993{
2994        struct adapter_reply_queue *reply_q, *next;
2995
2996        if (list_empty(&ioc->reply_queue_list))
2997                return;
2998
2999        list_for_each_entry_safe(reply_q, next, &ioc->reply_queue_list, list) {
3000                list_del(&reply_q->list);
3001                if (ioc->smp_affinity_enable)
3002                        irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3003                            reply_q->msix_index), NULL);
3004                free_irq(pci_irq_vector(ioc->pdev, reply_q->msix_index),
3005                         reply_q);
3006                kfree(reply_q);
3007        }
3008}
3009
3010/**
3011 * _base_request_irq - request irq
3012 * @ioc: per adapter object
3013 * @index: msix index into vector table
3014 *
3015 * Inserting respective reply_queue into the list.
3016 */
3017static int
3018_base_request_irq(struct MPT3SAS_ADAPTER *ioc, u8 index)
3019{
3020        struct pci_dev *pdev = ioc->pdev;
3021        struct adapter_reply_queue *reply_q;
3022        int r;
3023
3024        reply_q =  kzalloc(sizeof(struct adapter_reply_queue), GFP_KERNEL);
3025        if (!reply_q) {
3026                ioc_err(ioc, "unable to allocate memory %zu!\n",
3027                        sizeof(struct adapter_reply_queue));
3028                return -ENOMEM;
3029        }
3030        reply_q->ioc = ioc;
3031        reply_q->msix_index = index;
3032
3033        atomic_set(&reply_q->busy, 0);
3034        if (ioc->msix_enable)
3035                snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d-msix%d",
3036                    ioc->driver_name, ioc->id, index);
3037        else
3038                snprintf(reply_q->name, MPT_NAME_LENGTH, "%s%d",
3039                    ioc->driver_name, ioc->id);
3040        r = request_irq(pci_irq_vector(pdev, index), _base_interrupt,
3041                        IRQF_SHARED, reply_q->name, reply_q);
3042        if (r) {
3043                pr_err("%s: unable to allocate interrupt %d!\n",
3044                       reply_q->name, pci_irq_vector(pdev, index));
3045                kfree(reply_q);
3046                return -EBUSY;
3047        }
3048
3049        INIT_LIST_HEAD(&reply_q->list);
3050        list_add_tail(&reply_q->list, &ioc->reply_queue_list);
3051        return 0;
3052}
3053
3054/**
3055 * _base_assign_reply_queues - assigning msix index for each cpu
3056 * @ioc: per adapter object
3057 *
3058 * The enduser would need to set the affinity via /proc/irq/#/smp_affinity
3059 *
3060 * It would nice if we could call irq_set_affinity, however it is not
3061 * an exported symbol
3062 */
3063static void
3064_base_assign_reply_queues(struct MPT3SAS_ADAPTER *ioc)
3065{
3066        unsigned int cpu, nr_cpus, nr_msix, index = 0;
3067        struct adapter_reply_queue *reply_q;
3068        int local_numa_node;
3069
3070        if (!_base_is_controller_msix_enabled(ioc))
3071                return;
3072
3073        if (ioc->msix_load_balance)
3074                return;
3075
3076        memset(ioc->cpu_msix_table, 0, ioc->cpu_msix_table_sz);
3077
3078        nr_cpus = num_online_cpus();
3079        nr_msix = ioc->reply_queue_count = min(ioc->reply_queue_count,
3080                                               ioc->facts.MaxMSIxVectors);
3081        if (!nr_msix)
3082                return;
3083
3084        if (ioc->smp_affinity_enable) {
3085
3086                /*
3087                 * set irq affinity to local numa node for those irqs
3088                 * corresponding to high iops queues.
3089                 */
3090                if (ioc->high_iops_queues) {
3091                        local_numa_node = dev_to_node(&ioc->pdev->dev);
3092                        for (index = 0; index < ioc->high_iops_queues;
3093                            index++) {
3094                                irq_set_affinity_hint(pci_irq_vector(ioc->pdev,
3095                                    index), cpumask_of_node(local_numa_node));
3096                        }
3097                }
3098
3099                list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3100                        const cpumask_t *mask;
3101
3102                        if (reply_q->msix_index < ioc->high_iops_queues)
3103                                continue;
3104
3105                        mask = pci_irq_get_affinity(ioc->pdev,
3106                            reply_q->msix_index);
3107                        if (!mask) {
3108                                ioc_warn(ioc, "no affinity for msi %x\n",
3109                                         reply_q->msix_index);
3110                                goto fall_back;
3111                        }
3112
3113                        for_each_cpu_and(cpu, mask, cpu_online_mask) {
3114                                if (cpu >= ioc->cpu_msix_table_sz)
3115                                        break;
3116                                ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3117                        }
3118                }
3119                return;
3120        }
3121
3122fall_back:
3123        cpu = cpumask_first(cpu_online_mask);
3124        nr_msix -= ioc->high_iops_queues;
3125        index = 0;
3126
3127        list_for_each_entry(reply_q, &ioc->reply_queue_list, list) {
3128                unsigned int i, group = nr_cpus / nr_msix;
3129
3130                if (reply_q->msix_index < ioc->high_iops_queues)
3131                        continue;
3132
3133                if (cpu >= nr_cpus)
3134                        break;
3135
3136                if (index < nr_cpus % nr_msix)
3137                        group++;
3138
3139                for (i = 0 ; i < group ; i++) {
3140                        ioc->cpu_msix_table[cpu] = reply_q->msix_index;
3141                        cpu = cpumask_next(cpu, cpu_online_mask);
3142                }
3143                index++;
3144        }
3145}
3146
3147/**
3148 * _base_check_and_enable_high_iops_queues - enable high iops mode
3149 * @ioc: per adapter object
3150 * @hba_msix_vector_count: msix vectors supported by HBA
3151 *
3152 * Enable high iops queues only if
3153 *  - HBA is a SEA/AERO controller and
3154 *  - MSI-Xs vector supported by the HBA is 128 and
3155 *  - total CPU count in the system >=16 and
3156 *  - loaded driver with default max_msix_vectors module parameter and
3157 *  - system booted in non kdump mode
3158 *
3159 * Return: nothing.
3160 */
3161static void
3162_base_check_and_enable_high_iops_queues(struct MPT3SAS_ADAPTER *ioc,
3163                int hba_msix_vector_count)
3164{
3165        u16 lnksta, speed;
3166
3167        if (perf_mode == MPT_PERF_MODE_IOPS ||
3168            perf_mode == MPT_PERF_MODE_LATENCY) {
3169                ioc->high_iops_queues = 0;
3170                return;
3171        }
3172
3173        if (perf_mode == MPT_PERF_MODE_DEFAULT) {
3174
3175                pcie_capability_read_word(ioc->pdev, PCI_EXP_LNKSTA, &lnksta);
3176                speed = lnksta & PCI_EXP_LNKSTA_CLS;
3177
3178                if (speed < 0x4) {
3179                        ioc->high_iops_queues = 0;
3180                        return;
3181                }
3182        }
3183
3184        if (!reset_devices && ioc->is_aero_ioc &&
3185            hba_msix_vector_count == MPT3SAS_GEN35_MAX_MSIX_QUEUES &&
3186            num_online_cpus() >= MPT3SAS_HIGH_IOPS_REPLY_QUEUES &&
3187            max_msix_vectors == -1)
3188                ioc->high_iops_queues = MPT3SAS_HIGH_IOPS_REPLY_QUEUES;
3189        else
3190                ioc->high_iops_queues = 0;
3191}
3192
3193/**
3194 * mpt3sas_base_disable_msix - disables msix
3195 * @ioc: per adapter object
3196 *
3197 */
3198void
3199mpt3sas_base_disable_msix(struct MPT3SAS_ADAPTER *ioc)
3200{
3201        if (!ioc->msix_enable)
3202                return;
3203        pci_free_irq_vectors(ioc->pdev);
3204        ioc->msix_enable = 0;
3205}
3206
3207/**
3208 * _base_alloc_irq_vectors - allocate msix vectors
3209 * @ioc: per adapter object
3210 *
3211 */
3212static int
3213_base_alloc_irq_vectors(struct MPT3SAS_ADAPTER *ioc)
3214{
3215        int i, irq_flags = PCI_IRQ_MSIX;
3216        struct irq_affinity desc = { .pre_vectors = ioc->high_iops_queues };
3217        struct irq_affinity *descp = &desc;
3218
3219        if (ioc->smp_affinity_enable)
3220                irq_flags |= PCI_IRQ_AFFINITY;
3221        else
3222                descp = NULL;
3223
3224        ioc_info(ioc, " %d %d\n", ioc->high_iops_queues,
3225            ioc->reply_queue_count);
3226
3227        i = pci_alloc_irq_vectors_affinity(ioc->pdev,
3228            ioc->high_iops_queues,
3229            ioc->reply_queue_count, irq_flags, descp);
3230
3231        return i;
3232}
3233
3234/**
3235 * _base_enable_msix - enables msix, failback to io_apic
3236 * @ioc: per adapter object
3237 *
3238 */
3239static int
3240_base_enable_msix(struct MPT3SAS_ADAPTER *ioc)
3241{
3242        int r;
3243        int i, local_max_msix_vectors;
3244        u8 try_msix = 0;
3245
3246        ioc->msix_load_balance = false;
3247
3248        if (msix_disable == -1 || msix_disable == 0)
3249                try_msix = 1;
3250
3251        if (!try_msix)
3252                goto try_ioapic;
3253
3254        if (_base_check_enable_msix(ioc) != 0)
3255                goto try_ioapic;
3256
3257        ioc_info(ioc, "MSI-X vectors supported: %d\n", ioc->msix_vector_count);
3258        pr_info("\t no of cores: %d, max_msix_vectors: %d\n",
3259                ioc->cpu_count, max_msix_vectors);
3260        if (ioc->is_aero_ioc)
3261                _base_check_and_enable_high_iops_queues(ioc,
3262                        ioc->msix_vector_count);
3263        ioc->reply_queue_count =
3264                min_t(int, ioc->cpu_count + ioc->high_iops_queues,
3265                ioc->msix_vector_count);
3266
3267        if (!ioc->rdpq_array_enable && max_msix_vectors == -1)
3268                local_max_msix_vectors = (reset_devices) ? 1 : 8;
3269        else
3270                local_max_msix_vectors = max_msix_vectors;
3271
3272        if (local_max_msix_vectors > 0)
3273                ioc->reply_queue_count = min_t(int, local_max_msix_vectors,
3274                        ioc->reply_queue_count);
3275        else if (local_max_msix_vectors == 0)
3276                goto try_ioapic;
3277
3278        /*
3279         * Enable msix_load_balance only if combined reply queue mode is
3280         * disabled on SAS3 & above generation HBA devices.
3281         */
3282        if (!ioc->combined_reply_queue &&
3283            ioc->hba_mpi_version_belonged != MPI2_VERSION) {
3284                ioc_info(ioc,
3285                    "combined ReplyQueue is off, Enabling msix load balance\n");
3286                ioc->msix_load_balance = true;
3287        }
3288
3289        /*
3290         * smp affinity setting is not need when msix load balance
3291         * is enabled.
3292         */
3293        if (ioc->msix_load_balance)
3294                ioc->smp_affinity_enable = 0;
3295
3296        r = _base_alloc_irq_vectors(ioc);
3297        if (r < 0) {
3298                ioc_info(ioc, "pci_alloc_irq_vectors failed (r=%d) !!!\n", r);
3299                goto try_ioapic;
3300        }
3301
3302        ioc->msix_enable = 1;
3303        ioc->reply_queue_count = r;
3304        for (i = 0; i < ioc->reply_queue_count; i++) {
3305                r = _base_request_irq(ioc, i);
3306                if (r) {
3307                        mpt3sas_base_free_irq(ioc);
3308                        mpt3sas_base_disable_msix(ioc);
3309                        goto try_ioapic;
3310                }
3311        }
3312
3313        ioc_info(ioc, "High IOPs queues : %s\n",
3314                        ioc->high_iops_queues ? "enabled" : "disabled");
3315
3316        return 0;
3317
3318/* failback to io_apic interrupt routing */
3319 try_ioapic:
3320        ioc->high_iops_queues = 0;
3321        ioc_info(ioc, "High IOPs queues : disabled\n");
3322        ioc->reply_queue_count = 1;
3323        r = pci_alloc_irq_vectors(ioc->pdev, 1, 1, PCI_IRQ_LEGACY);
3324        if (r < 0) {
3325                dfailprintk(ioc,
3326                            ioc_info(ioc, "pci_alloc_irq_vector(legacy) failed (r=%d) !!!\n",
3327                                     r));
3328        } else
3329                r = _base_request_irq(ioc, 0);
3330
3331        return r;
3332}
3333
3334/**
3335 * mpt3sas_base_unmap_resources - free controller resources
3336 * @ioc: per adapter object
3337 */
3338static void
3339mpt3sas_base_unmap_resources(struct MPT3SAS_ADAPTER *ioc)
3340{
3341        struct pci_dev *pdev = ioc->pdev;
3342
3343        dexitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3344
3345        mpt3sas_base_free_irq(ioc);
3346        mpt3sas_base_disable_msix(ioc);
3347
3348        kfree(ioc->replyPostRegisterIndex);
3349        ioc->replyPostRegisterIndex = NULL;
3350
3351
3352        if (ioc->chip_phys) {
3353                iounmap(ioc->chip);
3354                ioc->chip_phys = 0;
3355        }
3356
3357        if (pci_is_enabled(pdev)) {
3358                pci_release_selected_regions(ioc->pdev, ioc->bars);
3359                pci_disable_pcie_error_reporting(pdev);
3360                pci_disable_device(pdev);
3361        }
3362}
3363
3364static int
3365_base_diag_reset(struct MPT3SAS_ADAPTER *ioc);
3366
3367/**
3368 * mpt3sas_base_check_for_fault_and_issue_reset - check if IOC is in fault state
3369 *     and if it is in fault state then issue diag reset.
3370 * @ioc: per adapter object
3371 *
3372 * Return: 0 for success, non-zero for failure.
3373 */
3374int
3375mpt3sas_base_check_for_fault_and_issue_reset(struct MPT3SAS_ADAPTER *ioc)
3376{
3377        u32 ioc_state;
3378        int rc = -EFAULT;
3379
3380        dinitprintk(ioc, pr_info("%s\n", __func__));
3381        if (ioc->pci_error_recovery)
3382                return 0;
3383        ioc_state = mpt3sas_base_get_iocstate(ioc, 0);
3384        dhsprintk(ioc, pr_info("%s: ioc_state(0x%08x)\n", __func__, ioc_state));
3385
3386        if ((ioc_state & MPI2_IOC_STATE_MASK) == MPI2_IOC_STATE_FAULT) {
3387                mpt3sas_print_fault_code(ioc, ioc_state &
3388                    MPI2_DOORBELL_DATA_MASK);
3389                mpt3sas_base_mask_interrupts(ioc);
3390                rc = _base_diag_reset(ioc);
3391        } else if ((ioc_state & MPI2_IOC_STATE_MASK) ==
3392            MPI2_IOC_STATE_COREDUMP) {
3393                mpt3sas_print_coredump_info(ioc, ioc_state &
3394                     MPI2_DOORBELL_DATA_MASK);
3395                mpt3sas_base_wait_for_coredump_completion(ioc, __func__);
3396                mpt3sas_base_mask_interrupts(ioc);
3397                rc = _base_diag_reset(ioc);
3398        }
3399
3400        return rc;
3401}
3402
3403/**
3404 * mpt3sas_base_map_resources - map in controller resources (io/irq/memap)
3405 * @ioc: per adapter object
3406 *
3407 * Return: 0 for success, non-zero for failure.
3408 */
3409int
3410mpt3sas_base_map_resources(struct MPT3SAS_ADAPTER *ioc)
3411{
3412        struct pci_dev *pdev = ioc->pdev;
3413        u32 memap_sz;
3414        u32 pio_sz;
3415        int i, r = 0, rc;
3416        u64 pio_chip = 0;
3417        phys_addr_t chip_phys = 0;
3418        struct adapter_reply_queue *reply_q;
3419
3420        dinitprintk(ioc, ioc_info(ioc, "%s\n", __func__));
3421
3422        ioc->bars = pci_select_bars(pdev, IORESOURCE_MEM);
3423        if (pci_enable_device_mem(pdev)) {
3424                ioc_warn(ioc, "pci_enable_device_mem: failed\n");
3425                ioc->bars = 0;
3426                return -ENODEV;
3427        }
3428
3429
3430        if (pci_request_selected_regions(pdev, ioc->bars,
3431            ioc->driver_name)) {
3432                ioc_warn(ioc, "pci_request_selected_regions: failed\n");
3433                ioc->bars = 0;
3434                r = -ENODEV;
3435                goto out_fail;
3436        }
3437
3438/* AER (Advanced Error Reporting) hooks */
3439        pci_enable_pcie_error_reporting(pdev);
3440
3441        pci_set_master(pdev);
3442
3443
3444        if (_base_config_dma_addressing(ioc, pdev) != 0) {
3445                ioc_warn(ioc, "no suitable DMA mask for %s\n", pci_name(pdev));
3446                r = -ENODEV;
3447                goto out_fail;
3448        }
3449
3450        for (i = 0, memap_sz = 0, pio_sz = 0; (i < DEVICE_COUNT_RESOURCE) &&
3451             (!memap_sz || !pio_sz); i++) {
3452                if (pci_resource_flags(pdev, i) & IORESOURCE_IO) {
3453                        if (pio_sz)
3454                                continue;
3455                        pio_chip = (u64)pci_resource_start(pdev, i);
3456                        pio_sz = pci_resource_len(pdev, i);
3457                } else if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
3458                        if (memap_sz)
3459                                continue;
3460                        ioc->chip_phys = pci_resource_start(pdev, i);
3461                        chip_phys = ioc->chip_phys;
3462                        memap_sz = pci_resource_len(pdev, i);
3463                        ioc->chip = ioremap(ioc->chip_phys, memap_sz);
3464                }
3465        }
3466
3467        if (ioc->chip == NULL) {
3468                ioc_err(ioc,
3469                    "unable to map adapter memory! or resource not found\n");
3470                r = -EINVAL;
3471                goto out_fail;
3472        }
3473
3474        mpt3sas_base_mask_interrupts(ioc);
3475
3476        r = _base_get_ioc_facts(ioc);
3477        if (r) {
3478                rc = mpt3sas_base_check_for_fault_and_issue_reset(ioc);
3479                if (rc || (_base_get_ioc_facts(ioc)))
3480                        goto out_fail;
3481        }
3482
3483        if (!ioc->rdpq_array_enable_assigned) {
3484                ioc->rdpq_array_enable = ioc->rdpq_array_capable;
3485                ioc->rdpq_array_enable_assigned = 1;
3486        }
3487
3488        r = _base_enable_msix(ioc);
3489        if (r)
3490                goto out_fail;
3491
3492        if (!ioc->is_driver_loading)
3493                _base_init_irqpolls(ioc);
3494        /* Use the Combined reply queue feature only for SAS3 C0 & higher
3495         * revision HBAs and also only when reply queue count is greater than 8
3496         */
3497        if (ioc->combined_reply_queue) {
3498                /* Determine the Supplemental Reply Post Host Index Registers
3499                 * Addresse. Supplemental Reply Post Host Index Registers
3500                 * starts at offset MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET and
3501                 * each register is at offset bytes of
3502                 * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET from previous one.
3503                 */
3504                ioc->replyPostRegisterIndex = kcalloc(
3505                     ioc->combined_reply_index_count,
3506                     sizeof(resource_size_t *), GFP_KERNEL);
3507                if (!ioc->replyPostRegisterIndex) {
3508                        ioc_err(ioc,
3509                            "allocation for replyPostRegisterIndex failed!\n");
3510                        r = -ENOMEM;
3511                        goto out_fail;
3512                }
3513
3514                for (i = 0; i < ioc->combined_reply_index_count; i++) {
3515                        ioc->replyPostRegisterIndex[i] = (resource_size_t *)
3516                             ((u8 __force *)&ioc->chip->Doorbell +
3517                             MPI25_SUP_REPLY_POST_HOST_INDEX_OFFSET +
3518                             (i * MPT3_SUP_REPLY_POST_HOST_INDEX_REG_OFFSET));
3519                }
3520        }
3521
3522        if (ioc->is_warpdrive) {
3523                ioc->reply_post_host_index[0] = (resource_size_t __iomem *)
3524                    &ioc->chip->ReplyPostHostIndex;
3525
3526                for (i = 1; i < ioc->cpu_msix_table_sz; i++)
3527                        ioc->reply_post_host_index[i] =
3528                        (resource_size_t __iomem *)
3529                        ((u8 __iomem *)&ioc->chip->Doorbell + (0x4000 + ((i - 1)
3530                        * 4)));
3531        }
3532
3533        list_for_each_entry(reply_q, &ioc->reply_queue_list, list)
3534                pr_info("%s: %s enabled: IRQ %d\n",
3535                        reply_q->name,
3536                        ioc->msix_enable ? "PCI-MSI-X" : "IO-APIC",
3537                        pci_irq_vector(ioc->pdev, reply_q->msix_index));
3538
3539        ioc_info(ioc, "iomem(%pap), mapped(0x%p), size(%d)\n",
3540                 &chip_phys, ioc->chip, memap_sz);
3541        ioc_info(ioc, "ioport(0x%016llx), size(%d)\n",
3542                 (unsigned long long)pio_chip, pio_sz);
3543
3544        /* Save PCI configuration state for recovery from PCI AER/EEH errors */
3545        pci_save_state(pdev);
3546        return 0;
3547
3548 out_fail:
3549        mpt3sas_base_unmap_resources(ioc);
3550        return r;
3551}
3552
3553/**
3554 * mpt3sas_base_get_msg_frame - obtain request mf pointer
3555 * @ioc: per adapter object
3556 * @smid: system request message index(smid zero is invalid)
3557 *
3558 * Return: virt pointer to message frame.
3559 */
3560void *
3561mpt3sas_base_get_msg_frame(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3562{
3563        return (void *)(ioc->request + (smid * ioc->request_sz));
3564}
3565
3566/**
3567 * mpt3sas_base_get_sense_buffer - obtain a sense buffer virt addr
3568 * @ioc: per adapter object
3569 * @smid: system request message index
3570 *
3571 * Return: virt pointer to sense buffer.
3572 */
3573void *
3574mpt3sas_base_get_sense_buffer(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3575{
3576        return (void *)(ioc->sense + ((smid - 1) * SCSI_SENSE_BUFFERSIZE));
3577}
3578
3579/**
3580 * mpt3sas_base_get_sense_buffer_dma - obtain a sense buffer dma addr
3581 * @ioc: per adapter object
3582 * @smid: system request message index
3583 *
3584 * Return: phys pointer to the low 32bit address of the sense buffer.
3585 */
3586__le32
3587mpt3sas_base_get_sense_buffer_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3588{
3589        return cpu_to_le32(ioc->sense_dma + ((smid - 1) *
3590            SCSI_SENSE_BUFFERSIZE));
3591}
3592
3593/**
3594 * mpt3sas_base_get_pcie_sgl - obtain a PCIe SGL virt addr
3595 * @ioc: per adapter object
3596 * @smid: system request message index
3597 *
3598 * Return: virt pointer to a PCIe SGL.
3599 */
3600void *
3601mpt3sas_base_get_pcie_sgl(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3602{
3603        return (void *)(ioc->pcie_sg_lookup[smid - 1].pcie_sgl);
3604}
3605
3606/**
3607 * mpt3sas_base_get_pcie_sgl_dma - obtain a PCIe SGL dma addr
3608 * @ioc: per adapter object
3609 * @smid: system request message index
3610 *
3611 * Return: phys pointer to the address of the PCIe buffer.
3612 */
3613dma_addr_t
3614mpt3sas_base_get_pcie_sgl_dma(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3615{
3616        return ioc->pcie_sg_lookup[smid - 1].pcie_sgl_dma;
3617}
3618
3619/**
3620 * mpt3sas_base_get_reply_virt_addr - obtain reply frames virt address
3621 * @ioc: per adapter object
3622 * @phys_addr: lower 32 physical addr of the reply
3623 *
3624 * Converts 32bit lower physical addr into a virt address.
3625 */
3626void *
3627mpt3sas_base_get_reply_virt_addr(struct MPT3SAS_ADAPTER *ioc, u32 phys_addr)
3628{
3629        if (!phys_addr)
3630                return NULL;
3631        return ioc->reply + (phys_addr - (u32)ioc->reply_dma);
3632}
3633
3634/**
3635 * _base_get_msix_index - get the msix index
3636 * @ioc: per adapter object
3637 * @scmd: scsi_cmnd object
3638 *
3639 * Return: msix index of general reply queues,
3640 * i.e. reply queue on which IO request's reply
3641 * should be posted by the HBA firmware.
3642 */
3643static inline u8
3644_base_get_msix_index(struct MPT3SAS_ADAPTER *ioc,
3645        struct scsi_cmnd *scmd)
3646{
3647        /* Enables reply_queue load balancing */
3648        if (ioc->msix_load_balance)
3649                return ioc->reply_queue_count ?
3650                    base_mod64(atomic64_add_return(1,
3651                    &ioc->total_io_cnt), ioc->reply_queue_count) : 0;
3652
3653        if (scmd && ioc->shost->nr_hw_queues > 1) {
3654                u32 tag = blk_mq_unique_tag(scmd->request);
3655
3656                return blk_mq_unique_tag_to_hwq(tag) +
3657                        ioc->high_iops_queues;
3658        }
3659
3660        return ioc->cpu_msix_table[raw_smp_processor_id()];
3661}
3662
3663/**
3664 * _base_get_high_iops_msix_index - get the msix index of
3665 *                              high iops queues
3666 * @ioc: per adapter object
3667 * @scmd: scsi_cmnd object
3668 *
3669 * Return: msix index of high iops reply queues.
3670 * i.e. high iops reply queue on which IO request's
3671 * reply should be posted by the HBA firmware.
3672 */
3673static inline u8
3674_base_get_high_iops_msix_index(struct MPT3SAS_ADAPTER *ioc,
3675        struct scsi_cmnd *scmd)
3676{
3677        /**
3678         * Round robin the IO interrupts among the high iops
3679         * reply queues in terms of batch count 16 when outstanding
3680         * IOs on the target device is >=8.
3681         */
3682
3683        if (scsi_device_busy(scmd->device) > MPT3SAS_DEVICE_HIGH_IOPS_DEPTH)
3684                return base_mod64((
3685                    atomic64_add_return(1, &ioc->high_iops_outstanding) /
3686                    MPT3SAS_HIGH_IOPS_BATCH_COUNT),
3687                    MPT3SAS_HIGH_IOPS_REPLY_QUEUES);
3688
3689        return _base_get_msix_index(ioc, scmd);
3690}
3691
3692/**
3693 * mpt3sas_base_get_smid - obtain a free smid from internal queue
3694 * @ioc: per adapter object
3695 * @cb_idx: callback index
3696 *
3697 * Return: smid (zero is invalid)
3698 */
3699u16
3700mpt3sas_base_get_smid(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3701{
3702        unsigned long flags;
3703        struct request_tracker *request;
3704        u16 smid;
3705
3706        spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3707        if (list_empty(&ioc->internal_free_list)) {
3708                spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3709                ioc_err(ioc, "%s: smid not available\n", __func__);
3710                return 0;
3711        }
3712
3713        request = list_entry(ioc->internal_free_list.next,
3714            struct request_tracker, tracker_list);
3715        request->cb_idx = cb_idx;
3716        smid = request->smid;
3717        list_del(&request->tracker_list);
3718        spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3719        return smid;
3720}
3721
3722/**
3723 * mpt3sas_base_get_smid_scsiio - obtain a free smid from scsiio queue
3724 * @ioc: per adapter object
3725 * @cb_idx: callback index
3726 * @scmd: pointer to scsi command object
3727 *
3728 * Return: smid (zero is invalid)
3729 */
3730u16
3731mpt3sas_base_get_smid_scsiio(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx,
3732        struct scsi_cmnd *scmd)
3733{
3734        struct scsiio_tracker *request = scsi_cmd_priv(scmd);
3735        u16 smid;
3736        u32 tag, unique_tag;
3737
3738        unique_tag = blk_mq_unique_tag(scmd->request);
3739        tag = blk_mq_unique_tag_to_tag(unique_tag);
3740
3741        /*
3742         * Store hw queue number corresponding to the tag.
3743         * This hw queue number is used later to determine
3744         * the unique_tag using the logic below. This unique_tag
3745         * is used to retrieve the scmd pointer corresponding
3746         * to tag using scsi_host_find_tag() API.
3747         *
3748         * tag = smid - 1;
3749         * unique_tag = ioc->io_queue_num[tag] << BLK_MQ_UNIQUE_TAG_BITS | tag;
3750         */
3751        ioc->io_queue_num[tag] = blk_mq_unique_tag_to_hwq(unique_tag);
3752
3753        smid = tag + 1;
3754        request->cb_idx = cb_idx;
3755        request->smid = smid;
3756        request->scmd = scmd;
3757        INIT_LIST_HEAD(&request->chain_list);
3758        return smid;
3759}
3760
3761/**
3762 * mpt3sas_base_get_smid_hpr - obtain a free smid from hi-priority queue
3763 * @ioc: per adapter object
3764 * @cb_idx: callback index
3765 *
3766 * Return: smid (zero is invalid)
3767 */
3768u16
3769mpt3sas_base_get_smid_hpr(struct MPT3SAS_ADAPTER *ioc, u8 cb_idx)
3770{
3771        unsigned long flags;
3772        struct request_tracker *request;
3773        u16 smid;
3774
3775        spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3776        if (list_empty(&ioc->hpr_free_list)) {
3777                spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3778                return 0;
3779        }
3780
3781        request = list_entry(ioc->hpr_free_list.next,
3782            struct request_tracker, tracker_list);
3783        request->cb_idx = cb_idx;
3784        smid = request->smid;
3785        list_del(&request->tracker_list);
3786        spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3787        return smid;
3788}
3789
3790static void
3791_base_recovery_check(struct MPT3SAS_ADAPTER *ioc)
3792{
3793        /*
3794         * See _wait_for_commands_to_complete() call with regards to this code.
3795         */
3796        if (ioc->shost_recovery && ioc->pending_io_count) {
3797                ioc->pending_io_count = scsi_host_busy(ioc->shost);
3798                if (ioc->pending_io_count == 0)
3799                        wake_up(&ioc->reset_wq);
3800        }
3801}
3802
3803void mpt3sas_base_clear_st(struct MPT3SAS_ADAPTER *ioc,
3804                           struct scsiio_tracker *st)
3805{
3806        if (WARN_ON(st->smid == 0))
3807                return;
3808        st->cb_idx = 0xFF;
3809        st->direct_io = 0;
3810        st->scmd = NULL;
3811        atomic_set(&ioc->chain_lookup[st->smid - 1].chain_offset, 0);
3812        st->smid = 0;
3813}
3814
3815/**
3816 * mpt3sas_base_free_smid - put smid back on free_list
3817 * @ioc: per adapter object
3818 * @smid: system request message index
3819 */
3820void
3821mpt3sas_base_free_smid(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3822{
3823        unsigned long flags;
3824        int i;
3825
3826        if (smid < ioc->hi_priority_smid) {
3827                struct scsiio_tracker *st;
3828                void *request;
3829
3830                st = _get_st_from_smid(ioc, smid);
3831                if (!st) {
3832                        _base_recovery_check(ioc);
3833                        return;
3834                }
3835
3836                /* Clear MPI request frame */
3837                request = mpt3sas_base_get_msg_frame(ioc, smid);
3838                memset(request, 0, ioc->request_sz);
3839
3840                mpt3sas_base_clear_st(ioc, st);
3841                _base_recovery_check(ioc);
3842                ioc->io_queue_num[smid - 1] = 0;
3843                return;
3844        }
3845
3846        spin_lock_irqsave(&ioc->scsi_lookup_lock, flags);
3847        if (smid < ioc->internal_smid) {
3848                /* hi-priority */
3849                i = smid - ioc->hi_priority_smid;
3850                ioc->hpr_lookup[i].cb_idx = 0xFF;
3851                list_add(&ioc->hpr_lookup[i].tracker_list, &ioc->hpr_free_list);
3852        } else if (smid <= ioc->hba_queue_depth) {
3853                /* internal queue */
3854                i = smid - ioc->internal_smid;
3855                ioc->internal_lookup[i].cb_idx = 0xFF;
3856                list_add(&ioc->internal_lookup[i].tracker_list,
3857                    &ioc->internal_free_list);
3858        }
3859        spin_unlock_irqrestore(&ioc->scsi_lookup_lock, flags);
3860}
3861
3862/**
3863 * _base_mpi_ep_writeq - 32 bit write to MMIO
3864 * @b: data payload
3865 * @addr: address in MMIO space
3866 * @writeq_lock: spin lock
3867 *
3868 * This special handling for MPI EP to take care of 32 bit
3869 * environment where its not quarenteed to send the entire word
3870 * in one transfer.
3871 */
3872static inline void
3873_base_mpi_ep_writeq(__u64 b, volatile void __iomem *addr,
3874                                        spinlock_t *writeq_lock)
3875{
3876        unsigned long flags;
3877
3878        spin_lock_irqsave(writeq_lock, flags);
3879        __raw_writel((u32)(b), addr);
3880        __raw_writel((u32)(b >> 32), (addr + 4));
3881        spin_unlock_irqrestore(writeq_lock, flags);
3882}
3883
3884/**
3885 * _base_writeq - 64 bit write to MMIO
3886 * @b: data payload
3887 * @addr: address in MMIO space
3888 * @writeq_lock: spin lock
3889 *
3890 * Glue for handling an atomic 64 bit word to MMIO. This special handling takes
3891 * care of 32 bit environment where its not quarenteed to send the entire word
3892 * in one transfer.
3893 */
3894#if defined(writeq) && defined(CONFIG_64BIT)
3895static inline void
3896_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
3897{
3898        wmb();
3899        __raw_writeq(b, addr);
3900        barrier();
3901}
3902#else
3903static inline void
3904_base_writeq(__u64 b, volatile void __iomem *addr, spinlock_t *writeq_lock)
3905{
3906        _base_mpi_ep_writeq(b, addr, writeq_lock);
3907}
3908#endif
3909
3910/**
3911 * _base_set_and_get_msix_index - get the msix index and assign to msix_io
3912 *                                variable of scsi tracker
3913 * @ioc: per adapter object
3914 * @smid: system request message index
3915 *
3916 * Return: msix index.
3917 */
3918static u8
3919_base_set_and_get_msix_index(struct MPT3SAS_ADAPTER *ioc, u16 smid)
3920{
3921        struct scsiio_tracker *st = NULL;
3922
3923        if (smid < ioc->hi_priority_smid)
3924                st = _get_st_from_smid(ioc, smid);
3925
3926        if (st == NULL)
3927                return  _base_get_msix_index(ioc, NULL);
3928
3929        st->msix_io = ioc->get_msix_index_for_smlio(ioc, st->scmd);
3930        return st->msix_io;
3931}
3932
3933/**
3934 * _base_put_smid_mpi_ep_scsi_io - send SCSI_IO request to firmware
3935 * @ioc: per adapter object
3936 * @smid: system request message index
3937 * @handle: device handle
3938 */
3939static void
3940_base_put_smid_mpi_ep_scsi_io(struct MPT3SAS_ADAPTER *ioc,
3941        u16 smid, u16 handle)
3942{
3943        Mpi2RequestDescriptorUnion_t descriptor;
3944        u64 *request = (u64 *)&descriptor;
3945        void *mpi_req_iomem;
3946        __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
3947
3948        _clone_sg_entries(ioc, (void *) mfp, smid);
3949        mpi_req_iomem = (void __force *)ioc->chip +
3950                        MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
3951        _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
3952                                        ioc->request_sz);
3953        descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3954        descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3955        descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3956        descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3957        descriptor.SCSIIO.LMID = 0;
3958        _base_mpi_ep_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3959            &ioc->scsi_lookup_lock);
3960}
3961
3962/**
3963 * _base_put_smid_scsi_io - send SCSI_IO request to firmware
3964 * @ioc: per adapter object
3965 * @smid: system request message index
3966 * @handle: device handle
3967 */
3968static void
3969_base_put_smid_scsi_io(struct MPT3SAS_ADAPTER *ioc, u16 smid, u16 handle)
3970{
3971        Mpi2RequestDescriptorUnion_t descriptor;
3972        u64 *request = (u64 *)&descriptor;
3973
3974
3975        descriptor.SCSIIO.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
3976        descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
3977        descriptor.SCSIIO.SMID = cpu_to_le16(smid);
3978        descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
3979        descriptor.SCSIIO.LMID = 0;
3980        _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
3981            &ioc->scsi_lookup_lock);
3982}
3983
3984/**
3985 * _base_put_smid_fast_path - send fast path request to firmware
3986 * @ioc: per adapter object
3987 * @smid: system request message index
3988 * @handle: device handle
3989 */
3990static void
3991_base_put_smid_fast_path(struct MPT3SAS_ADAPTER *ioc, u16 smid,
3992        u16 handle)
3993{
3994        Mpi2RequestDescriptorUnion_t descriptor;
3995        u64 *request = (u64 *)&descriptor;
3996
3997        descriptor.SCSIIO.RequestFlags =
3998            MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
3999        descriptor.SCSIIO.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4000        descriptor.SCSIIO.SMID = cpu_to_le16(smid);
4001        descriptor.SCSIIO.DevHandle = cpu_to_le16(handle);
4002        descriptor.SCSIIO.LMID = 0;
4003        _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4004            &ioc->scsi_lookup_lock);
4005}
4006
4007/**
4008 * _base_put_smid_hi_priority - send Task Management request to firmware
4009 * @ioc: per adapter object
4010 * @smid: system request message index
4011 * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4012 */
4013static void
4014_base_put_smid_hi_priority(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4015        u16 msix_task)
4016{
4017        Mpi2RequestDescriptorUnion_t descriptor;
4018        void *mpi_req_iomem;
4019        u64 *request;
4020
4021        if (ioc->is_mcpu_endpoint) {
4022                __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4023
4024                /* TBD 256 is offset within sys register. */
4025                mpi_req_iomem = (void __force *)ioc->chip
4026                                        + MPI_FRAME_START_OFFSET
4027                                        + (smid * ioc->request_sz);
4028                _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4029                                                        ioc->request_sz);
4030        }
4031
4032        request = (u64 *)&descriptor;
4033
4034        descriptor.HighPriority.RequestFlags =
4035            MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4036        descriptor.HighPriority.MSIxIndex =  msix_task;
4037        descriptor.HighPriority.SMID = cpu_to_le16(smid);
4038        descriptor.HighPriority.LMID = 0;
4039        descriptor.HighPriority.Reserved1 = 0;
4040        if (ioc->is_mcpu_endpoint)
4041                _base_mpi_ep_writeq(*request,
4042                                &ioc->chip->RequestDescriptorPostLow,
4043                                &ioc->scsi_lookup_lock);
4044        else
4045                _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4046                    &ioc->scsi_lookup_lock);
4047}
4048
4049/**
4050 * mpt3sas_base_put_smid_nvme_encap - send NVMe encapsulated request to
4051 *  firmware
4052 * @ioc: per adapter object
4053 * @smid: system request message index
4054 */
4055void
4056mpt3sas_base_put_smid_nvme_encap(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4057{
4058        Mpi2RequestDescriptorUnion_t descriptor;
4059        u64 *request = (u64 *)&descriptor;
4060
4061        descriptor.Default.RequestFlags =
4062                MPI26_REQ_DESCRIPT_FLAGS_PCIE_ENCAPSULATED;
4063        descriptor.Default.MSIxIndex =  _base_set_and_get_msix_index(ioc, smid);
4064        descriptor.Default.SMID = cpu_to_le16(smid);
4065        descriptor.Default.LMID = 0;
4066        descriptor.Default.DescriptorTypeDependent = 0;
4067        _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4068            &ioc->scsi_lookup_lock);
4069}
4070
4071/**
4072 * _base_put_smid_default - Default, primarily used for config pages
4073 * @ioc: per adapter object
4074 * @smid: system request message index
4075 */
4076static void
4077_base_put_smid_default(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4078{
4079        Mpi2RequestDescriptorUnion_t descriptor;
4080        void *mpi_req_iomem;
4081        u64 *request;
4082
4083        if (ioc->is_mcpu_endpoint) {
4084                __le32 *mfp = (__le32 *)mpt3sas_base_get_msg_frame(ioc, smid);
4085
4086                _clone_sg_entries(ioc, (void *) mfp, smid);
4087                /* TBD 256 is offset within sys register */
4088                mpi_req_iomem = (void __force *)ioc->chip +
4089                        MPI_FRAME_START_OFFSET + (smid * ioc->request_sz);
4090                _base_clone_mpi_to_sys_mem(mpi_req_iomem, (void *)mfp,
4091                                                        ioc->request_sz);
4092        }
4093        request = (u64 *)&descriptor;
4094        descriptor.Default.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4095        descriptor.Default.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4096        descriptor.Default.SMID = cpu_to_le16(smid);
4097        descriptor.Default.LMID = 0;
4098        descriptor.Default.DescriptorTypeDependent = 0;
4099        if (ioc->is_mcpu_endpoint)
4100                _base_mpi_ep_writeq(*request,
4101                                &ioc->chip->RequestDescriptorPostLow,
4102                                &ioc->scsi_lookup_lock);
4103        else
4104                _base_writeq(*request, &ioc->chip->RequestDescriptorPostLow,
4105                                &ioc->scsi_lookup_lock);
4106}
4107
4108/**
4109 * _base_put_smid_scsi_io_atomic - send SCSI_IO request to firmware using
4110 *   Atomic Request Descriptor
4111 * @ioc: per adapter object
4112 * @smid: system request message index
4113 * @handle: device handle, unused in this function, for function type match
4114 *
4115 * Return: nothing.
4116 */
4117static void
4118_base_put_smid_scsi_io_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4119        u16 handle)
4120{
4121        Mpi26AtomicRequestDescriptor_t descriptor;
4122        u32 *request = (u32 *)&descriptor;
4123
4124        descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_SCSI_IO;
4125        descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4126        descriptor.SMID = cpu_to_le16(smid);
4127
4128        writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4129}
4130
4131/**
4132 * _base_put_smid_fast_path_atomic - send fast path request to firmware
4133 * using Atomic Request Descriptor
4134 * @ioc: per adapter object
4135 * @smid: system request message index
4136 * @handle: device handle, unused in this function, for function type match
4137 * Return: nothing
4138 */
4139static void
4140_base_put_smid_fast_path_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4141        u16 handle)
4142{
4143        Mpi26AtomicRequestDescriptor_t descriptor;
4144        u32 *request = (u32 *)&descriptor;
4145
4146        descriptor.RequestFlags = MPI25_REQ_DESCRIPT_FLAGS_FAST_PATH_SCSI_IO;
4147        descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4148        descriptor.SMID = cpu_to_le16(smid);
4149
4150        writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4151}
4152
4153/**
4154 * _base_put_smid_hi_priority_atomic - send Task Management request to
4155 * firmware using Atomic Request Descriptor
4156 * @ioc: per adapter object
4157 * @smid: system request message index
4158 * @msix_task: msix_task will be same as msix of IO in case of task abort else 0
4159 *
4160 * Return: nothing.
4161 */
4162static void
4163_base_put_smid_hi_priority_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid,
4164        u16 msix_task)
4165{
4166        Mpi26AtomicRequestDescriptor_t descriptor;
4167        u32 *request = (u32 *)&descriptor;
4168
4169        descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_HIGH_PRIORITY;
4170        descriptor.MSIxIndex = msix_task;
4171        descriptor.SMID = cpu_to_le16(smid);
4172
4173        writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4174}
4175
4176/**
4177 * _base_put_smid_default_atomic - Default, primarily used for config pages
4178 * use Atomic Request Descriptor
4179 * @ioc: per adapter object
4180 * @smid: system request message index
4181 *
4182 * Return: nothing.
4183 */
4184static void
4185_base_put_smid_default_atomic(struct MPT3SAS_ADAPTER *ioc, u16 smid)
4186{
4187        Mpi26AtomicRequestDescriptor_t descriptor;
4188        u32 *request = (u32 *)&descriptor;
4189
4190        descriptor.RequestFlags = MPI2_REQ_DESCRIPT_FLAGS_DEFAULT_TYPE;
4191        descriptor.MSIxIndex = _base_set_and_get_msix_index(ioc, smid);
4192        descriptor.SMID = cpu_to_le16(smid);
4193
4194        writel(cpu_to_le32(*request), &ioc->chip->AtomicRequestDescriptorPost);
4195}
4196
4197/**
4198 * _base_display_OEMs_branding - Display branding string
4199 * @ioc: per adapter object
4200 */
4201static void
4202_base_display_OEMs_branding(struct MPT3SAS_ADAPTER *ioc)
4203{
4204        if (ioc->pdev->subsystem_vendor != PCI_VENDOR_ID_INTEL)
4205                return;
4206
4207        switch (ioc->pdev->subsystem_vendor) {
4208        case PCI_VENDOR_ID_INTEL:
4209                switch (ioc->pdev->device) {
4210                case MPI2_MFGPAGE_DEVID_SAS2008:
4211                        switch (ioc->pdev->subsystem_device) {
4212                        case MPT2SAS_INTEL_RMS2LL080_SSDID:
4213                                ioc_info(ioc, "%s\n",
4214                                         MPT2SAS_INTEL_RMS2LL080_BRANDING);
4215                                break;
4216                        case MPT2SAS_INTEL_RMS2LL040_SSDID:
4217                                ioc_info(ioc, "%s\n",
4218                                         MPT2SAS_INTEL_RMS2LL040_BRANDING);
4219                                break;
4220                        case MPT2SAS_INTEL_SSD910_SSDID:
4221                                ioc_info(ioc, "%s\n",
4222                                         MPT2SAS_INTEL_SSD910_BRANDING);
4223                                break;
4224                        default:
4225                                ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4226                                         ioc->pdev->subsystem_device);
4227                                break;
4228                        }
4229                        break;
4230                case MPI2_MFGPAGE_DEVID_SAS2308_2:
4231                        switch (ioc->pdev->subsystem_device) {
4232                        case MPT2SAS_INTEL_RS25GB008_SSDID:
4233                                ioc_info(ioc, "%s\n",
4234                                         MPT2SAS_INTEL_RS25GB008_BRANDING);
4235                                break;
4236                        case MPT2SAS_INTEL_RMS25JB080_SSDID:
4237                                ioc_info(ioc, "%s\n",
4238                                         MPT2SAS_INTEL_RMS25JB080_BRANDING);
4239                                break;
4240                        case MPT2SAS_INTEL_RMS25JB040_SSDID:
4241                                ioc_info(ioc, "%s\n",
4242                                         MPT2SAS_INTEL_RMS25JB040_BRANDING);
4243                                break;
4244                        case MPT2SAS_INTEL_RMS25KB080_SSDID:
4245                                ioc_info(ioc, "%s\n",
4246                                         MPT2SAS_INTEL_RMS25KB080_BRANDING);
4247                                break;
4248                        case MPT2SAS_INTEL_RMS25KB040_SSDID:
4249                                ioc_info(ioc, "%s\n",
4250                                         MPT2SAS_INTEL_RMS25KB040_BRANDING);
4251                                break;
4252                        case MPT2SAS_INTEL_RMS25LB040_SSDID:
4253                                ioc_info(ioc, "%s\n",
4254                                         MPT2SAS_INTEL_RMS25LB040_BRANDING);
4255                                break;
4256                        case MPT2SAS_INTEL_RMS25LB080_SSDID:
4257                                ioc_info(ioc, "%s\n",
4258                                         MPT2SAS_INTEL_RMS25LB080_BRANDING);
4259                                break;
4260                        default:
4261                                ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4262                                         ioc->pdev->subsystem_device);
4263                                break;
4264                        }
4265                        break;
4266                case MPI25_MFGPAGE_DEVID_SAS3008:
4267                        switch (ioc->pdev->subsystem_device) {
4268                        case MPT3SAS_INTEL_RMS3JC080_SSDID:
4269                                ioc_info(ioc, "%s\n",
4270                                         MPT3SAS_INTEL_RMS3JC080_BRANDING);
4271                                break;
4272
4273                        case MPT3SAS_INTEL_RS3GC008_SSDID:
4274                                ioc_info(ioc, "%s\n",
4275                                         MPT3SAS_INTEL_RS3GC008_BRANDING);
4276                                break;
4277                        case MPT3SAS_INTEL_RS3FC044_SSDID:
4278                                ioc_info(ioc, "%s\n",
4279                                         MPT3SAS_INTEL_RS3FC044_BRANDING);
4280                                break;
4281                        case MPT3SAS_INTEL_RS3UC080_SSDID:
4282                                ioc_info(ioc, "%s\n",
4283                                         MPT3SAS_INTEL_RS3UC080_BRANDING);
4284                                break;
4285                        default:
4286                                ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4287                                         ioc->pdev->subsystem_device);
4288                                break;
4289                        }
4290                        break;
4291                default:
4292                        ioc_info(ioc, "Intel(R) Controller: Subsystem ID: 0x%X\n",
4293                                 ioc->pdev->subsystem_device);
4294                        break;
4295                }
4296                break;
4297        case PCI_VENDOR_ID_DELL:
4298                switch (ioc->pdev->device) {
4299                case MPI2_MFGPAGE_DEVID_SAS2008:
4300                        switch (ioc->pdev->subsystem_device) {
4301                        case MPT2SAS_DELL_6GBPS_SAS_HBA_SSDID:
4302                                ioc_info(ioc, "%s\n",
4303                                         MPT2SAS_DELL_6GBPS_SAS_HBA_BRANDING);
4304                                break;
4305                        case MPT2SAS_DELL_PERC_H200_ADAPTER_SSDID:
4306                                ioc_info(ioc, "%s\n",
4307                                         MPT2SAS_DELL_PERC_H200_ADAPTER_BRANDING);
4308                                break;
4309                        case MPT2SAS_DELL_PERC_H200_INTEGRATED_SSDID:
4310                                ioc_info(ioc, "%s\n",
4311                                         MPT2SAS_DELL_PERC_H200_INTEGRATED_BRANDING);
4312                                break;
4313                        case MPT2SAS_DELL_PERC_H200_MODULAR_SSDID:
4314                                ioc_info(ioc, "%s\n",
4315                                         MPT2SAS_DELL_PERC_H200_MODULAR_BRANDING);