linux/drivers/scsi/advansys.c
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   1// SPDX-License-Identifier: GPL-2.0-or-later
   2/*
   3 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters
   4 *
   5 * Copyright (c) 1995-2000 Advanced System Products, Inc.
   6 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc.
   7 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx>
   8 * Copyright (c) 2014 Hannes Reinecke <hare@suse.de>
   9 * All Rights Reserved.
  10 */
  11
  12/*
  13 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys)
  14 * changed its name to ConnectCom Solutions, Inc.
  15 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets
  16 */
  17
  18#include <linux/module.h>
  19#include <linux/string.h>
  20#include <linux/kernel.h>
  21#include <linux/types.h>
  22#include <linux/ioport.h>
  23#include <linux/interrupt.h>
  24#include <linux/delay.h>
  25#include <linux/slab.h>
  26#include <linux/mm.h>
  27#include <linux/proc_fs.h>
  28#include <linux/init.h>
  29#include <linux/blkdev.h>
  30#include <linux/isa.h>
  31#include <linux/eisa.h>
  32#include <linux/pci.h>
  33#include <linux/spinlock.h>
  34#include <linux/dma-mapping.h>
  35#include <linux/firmware.h>
  36#include <linux/dmapool.h>
  37
  38#include <asm/io.h>
  39#include <asm/dma.h>
  40
  41#include <scsi/scsi_cmnd.h>
  42#include <scsi/scsi_device.h>
  43#include <scsi/scsi_tcq.h>
  44#include <scsi/scsi.h>
  45#include <scsi/scsi_host.h>
  46
  47#define DRV_NAME "advansys"
  48#define ASC_VERSION "3.5"       /* AdvanSys Driver Version */
  49
  50/* FIXME:
  51 *
  52 *  1. Use scsi_transport_spi
  53 *  2. advansys_info is not safe against multiple simultaneous callers
  54 *  3. Add module_param to override ISA/VLB ioport array
  55 */
  56
  57/* Enable driver /proc statistics. */
  58#define ADVANSYS_STATS
  59
  60/* Enable driver tracing. */
  61#undef ADVANSYS_DEBUG
  62
  63typedef unsigned char uchar;
  64
  65#define isodd_word(val)   ((((uint)val) & (uint)0x0001) != 0)
  66
  67#define PCI_VENDOR_ID_ASP               0x10cd
  68#define PCI_DEVICE_ID_ASP_1200A         0x1100
  69#define PCI_DEVICE_ID_ASP_ABP940        0x1200
  70#define PCI_DEVICE_ID_ASP_ABP940U       0x1300
  71#define PCI_DEVICE_ID_ASP_ABP940UW      0x2300
  72#define PCI_DEVICE_ID_38C0800_REV1      0x2500
  73#define PCI_DEVICE_ID_38C1600_REV1      0x2700
  74
  75#define PortAddr                 unsigned int   /* port address size  */
  76#define inp(port)                inb(port)
  77#define outp(port, byte)         outb((byte), (port))
  78
  79#define inpw(port)               inw(port)
  80#define outpw(port, word)        outw((word), (port))
  81
  82#define ASC_MAX_SG_QUEUE    7
  83#define ASC_MAX_SG_LIST     255
  84
  85#define ASC_CS_TYPE  unsigned short
  86
  87#define ASC_IS_EISA         (0x0002)
  88#define ASC_IS_PCI          (0x0004)
  89#define ASC_IS_PCI_ULTRA    (0x0104)
  90#define ASC_IS_PCMCIA       (0x0008)
  91#define ASC_IS_MCA          (0x0020)
  92#define ASC_IS_VL           (0x0040)
  93#define ASC_IS_WIDESCSI_16  (0x0100)
  94#define ASC_IS_WIDESCSI_32  (0x0200)
  95#define ASC_IS_BIG_ENDIAN   (0x8000)
  96
  97#define ASC_CHIP_MIN_VER_VL      (0x01)
  98#define ASC_CHIP_MAX_VER_VL      (0x07)
  99#define ASC_CHIP_MIN_VER_PCI     (0x09)
 100#define ASC_CHIP_MAX_VER_PCI     (0x0F)
 101#define ASC_CHIP_VER_PCI_BIT     (0x08)
 102#define ASC_CHIP_VER_ASYN_BUG    (0x21)
 103#define ASC_CHIP_VER_PCI             0x08
 104#define ASC_CHIP_VER_PCI_ULTRA_3150  (ASC_CHIP_VER_PCI | 0x02)
 105#define ASC_CHIP_VER_PCI_ULTRA_3050  (ASC_CHIP_VER_PCI | 0x03)
 106#define ASC_CHIP_MIN_VER_EISA (0x41)
 107#define ASC_CHIP_MAX_VER_EISA (0x47)
 108#define ASC_CHIP_VER_EISA_BIT (0x40)
 109#define ASC_CHIP_LATEST_VER_EISA   ((ASC_CHIP_MIN_VER_EISA - 1) + 3)
 110#define ASC_MAX_VL_DMA_COUNT    (0x07FFFFFFL)
 111#define ASC_MAX_PCI_DMA_COUNT   (0xFFFFFFFFL)
 112
 113#define ASC_SCSI_ID_BITS  3
 114#define ASC_SCSI_TIX_TYPE     uchar
 115#define ASC_ALL_DEVICE_BIT_SET  0xFF
 116#define ASC_SCSI_BIT_ID_TYPE  uchar
 117#define ASC_MAX_TID       7
 118#define ASC_MAX_LUN       7
 119#define ASC_SCSI_WIDTH_BIT_SET  0xFF
 120#define ASC_MAX_SENSE_LEN   32
 121#define ASC_MIN_SENSE_LEN   14
 122#define ASC_SCSI_RESET_HOLD_TIME_US  60
 123
 124/*
 125 * Narrow boards only support 12-byte commands, while wide boards
 126 * extend to 16-byte commands.
 127 */
 128#define ASC_MAX_CDB_LEN     12
 129#define ADV_MAX_CDB_LEN     16
 130
 131#define MS_SDTR_LEN    0x03
 132#define MS_WDTR_LEN    0x02
 133
 134#define ASC_SG_LIST_PER_Q   7
 135#define QS_FREE        0x00
 136#define QS_READY       0x01
 137#define QS_DISC1       0x02
 138#define QS_DISC2       0x04
 139#define QS_BUSY        0x08
 140#define QS_ABORTED     0x40
 141#define QS_DONE        0x80
 142#define QC_NO_CALLBACK   0x01
 143#define QC_SG_SWAP_QUEUE 0x02
 144#define QC_SG_HEAD       0x04
 145#define QC_DATA_IN       0x08
 146#define QC_DATA_OUT      0x10
 147#define QC_URGENT        0x20
 148#define QC_MSG_OUT       0x40
 149#define QC_REQ_SENSE     0x80
 150#define QCSG_SG_XFER_LIST  0x02
 151#define QCSG_SG_XFER_MORE  0x04
 152#define QCSG_SG_XFER_END   0x08
 153#define QD_IN_PROGRESS       0x00
 154#define QD_NO_ERROR          0x01
 155#define QD_ABORTED_BY_HOST   0x02
 156#define QD_WITH_ERROR        0x04
 157#define QD_INVALID_REQUEST   0x80
 158#define QD_INVALID_HOST_NUM  0x81
 159#define QD_INVALID_DEVICE    0x82
 160#define QD_ERR_INTERNAL      0xFF
 161#define QHSTA_NO_ERROR               0x00
 162#define QHSTA_M_SEL_TIMEOUT          0x11
 163#define QHSTA_M_DATA_OVER_RUN        0x12
 164#define QHSTA_M_DATA_UNDER_RUN       0x12
 165#define QHSTA_M_UNEXPECTED_BUS_FREE  0x13
 166#define QHSTA_M_BAD_BUS_PHASE_SEQ    0x14
 167#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21
 168#define QHSTA_D_ASC_DVC_ERROR_CODE_SET  0x22
 169#define QHSTA_D_HOST_ABORT_FAILED       0x23
 170#define QHSTA_D_EXE_SCSI_Q_FAILED       0x24
 171#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25
 172#define QHSTA_D_ASPI_NO_BUF_POOL        0x26
 173#define QHSTA_M_WTM_TIMEOUT         0x41
 174#define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
 175#define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
 176#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
 177#define QHSTA_M_TARGET_STATUS_BUSY  0x45
 178#define QHSTA_M_BAD_TAG_CODE        0x46
 179#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY  0x47
 180#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48
 181#define QHSTA_D_LRAM_CMP_ERROR        0x81
 182#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1
 183#define ASC_FLAG_SCSIQ_REQ        0x01
 184#define ASC_FLAG_BIOS_SCSIQ_REQ   0x02
 185#define ASC_FLAG_BIOS_ASYNC_IO    0x04
 186#define ASC_FLAG_SRB_LINEAR_ADDR  0x08
 187#define ASC_FLAG_WIN16            0x10
 188#define ASC_FLAG_WIN32            0x20
 189#define ASC_FLAG_DOS_VM_CALLBACK  0x80
 190#define ASC_TAG_FLAG_EXTRA_BYTES               0x10
 191#define ASC_TAG_FLAG_DISABLE_DISCONNECT        0x04
 192#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX  0x08
 193#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40
 194#define ASC_SCSIQ_CPY_BEG              4
 195#define ASC_SCSIQ_SGHD_CPY_BEG         2
 196#define ASC_SCSIQ_B_FWD                0
 197#define ASC_SCSIQ_B_BWD                1
 198#define ASC_SCSIQ_B_STATUS             2
 199#define ASC_SCSIQ_B_QNO                3
 200#define ASC_SCSIQ_B_CNTL               4
 201#define ASC_SCSIQ_B_SG_QUEUE_CNT       5
 202#define ASC_SCSIQ_D_DATA_ADDR          8
 203#define ASC_SCSIQ_D_DATA_CNT          12
 204#define ASC_SCSIQ_B_SENSE_LEN         20
 205#define ASC_SCSIQ_DONE_INFO_BEG       22
 206#define ASC_SCSIQ_D_SRBPTR            22
 207#define ASC_SCSIQ_B_TARGET_IX         26
 208#define ASC_SCSIQ_B_CDB_LEN           28
 209#define ASC_SCSIQ_B_TAG_CODE          29
 210#define ASC_SCSIQ_W_VM_ID             30
 211#define ASC_SCSIQ_DONE_STATUS         32
 212#define ASC_SCSIQ_HOST_STATUS         33
 213#define ASC_SCSIQ_SCSI_STATUS         34
 214#define ASC_SCSIQ_CDB_BEG             36
 215#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56
 216#define ASC_SCSIQ_DW_REMAIN_XFER_CNT  60
 217#define ASC_SCSIQ_B_FIRST_SG_WK_QP    48
 218#define ASC_SCSIQ_B_SG_WK_QP          49
 219#define ASC_SCSIQ_B_SG_WK_IX          50
 220#define ASC_SCSIQ_W_ALT_DC1           52
 221#define ASC_SCSIQ_B_LIST_CNT          6
 222#define ASC_SCSIQ_B_CUR_LIST_CNT      7
 223#define ASC_SGQ_B_SG_CNTL             4
 224#define ASC_SGQ_B_SG_HEAD_QP          5
 225#define ASC_SGQ_B_SG_LIST_CNT         6
 226#define ASC_SGQ_B_SG_CUR_LIST_CNT     7
 227#define ASC_SGQ_LIST_BEG              8
 228#define ASC_DEF_SCSI1_QNG    4
 229#define ASC_MAX_SCSI1_QNG    4
 230#define ASC_DEF_SCSI2_QNG    16
 231#define ASC_MAX_SCSI2_QNG    32
 232#define ASC_TAG_CODE_MASK    0x23
 233#define ASC_STOP_REQ_RISC_STOP      0x01
 234#define ASC_STOP_ACK_RISC_STOP      0x03
 235#define ASC_STOP_CLEAN_UP_BUSY_Q    0x10
 236#define ASC_STOP_CLEAN_UP_DISC_Q    0x20
 237#define ASC_STOP_HOST_REQ_RISC_HALT 0x40
 238#define ASC_TIDLUN_TO_IX(tid, lun)  (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS))
 239#define ASC_TID_TO_TARGET_ID(tid)   (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid))
 240#define ASC_TIX_TO_TARGET_ID(tix)   (0x01 << ((tix) & ASC_MAX_TID))
 241#define ASC_TIX_TO_TID(tix)         ((tix) & ASC_MAX_TID)
 242#define ASC_TID_TO_TIX(tid)         ((tid) & ASC_MAX_TID)
 243#define ASC_TIX_TO_LUN(tix)         (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN)
 244#define ASC_QNO_TO_QADDR(q_no)      ((ASC_QADR_BEG)+((int)(q_no) << 6))
 245
 246typedef struct asc_scsiq_1 {
 247        uchar status;
 248        uchar q_no;
 249        uchar cntl;
 250        uchar sg_queue_cnt;
 251        uchar target_id;
 252        uchar target_lun;
 253        __le32 data_addr;
 254        __le32 data_cnt;
 255        __le32 sense_addr;
 256        uchar sense_len;
 257        uchar extra_bytes;
 258} ASC_SCSIQ_1;
 259
 260typedef struct asc_scsiq_2 {
 261        u32 srb_tag;
 262        uchar target_ix;
 263        uchar flag;
 264        uchar cdb_len;
 265        uchar tag_code;
 266        ushort vm_id;
 267} ASC_SCSIQ_2;
 268
 269typedef struct asc_scsiq_3 {
 270        uchar done_stat;
 271        uchar host_stat;
 272        uchar scsi_stat;
 273        uchar scsi_msg;
 274} ASC_SCSIQ_3;
 275
 276typedef struct asc_scsiq_4 {
 277        uchar cdb[ASC_MAX_CDB_LEN];
 278        uchar y_first_sg_list_qp;
 279        uchar y_working_sg_qp;
 280        uchar y_working_sg_ix;
 281        uchar y_res;
 282        ushort x_req_count;
 283        ushort x_reconnect_rtn;
 284        __le32 x_saved_data_addr;
 285        __le32 x_saved_data_cnt;
 286} ASC_SCSIQ_4;
 287
 288typedef struct asc_q_done_info {
 289        ASC_SCSIQ_2 d2;
 290        ASC_SCSIQ_3 d3;
 291        uchar q_status;
 292        uchar q_no;
 293        uchar cntl;
 294        uchar sense_len;
 295        uchar extra_bytes;
 296        uchar res;
 297        u32 remain_bytes;
 298} ASC_QDONE_INFO;
 299
 300typedef struct asc_sg_list {
 301        __le32 addr;
 302        __le32 bytes;
 303} ASC_SG_LIST;
 304
 305typedef struct asc_sg_head {
 306        ushort entry_cnt;
 307        ushort queue_cnt;
 308        ushort entry_to_copy;
 309        ushort res;
 310        ASC_SG_LIST sg_list[];
 311} ASC_SG_HEAD;
 312
 313typedef struct asc_scsi_q {
 314        ASC_SCSIQ_1 q1;
 315        ASC_SCSIQ_2 q2;
 316        uchar *cdbptr;
 317        ASC_SG_HEAD *sg_head;
 318        ushort remain_sg_entry_cnt;
 319        ushort next_sg_index;
 320} ASC_SCSI_Q;
 321
 322typedef struct asc_scsi_bios_req_q {
 323        ASC_SCSIQ_1 r1;
 324        ASC_SCSIQ_2 r2;
 325        uchar *cdbptr;
 326        ASC_SG_HEAD *sg_head;
 327        uchar *sense_ptr;
 328        ASC_SCSIQ_3 r3;
 329        uchar cdb[ASC_MAX_CDB_LEN];
 330        uchar sense[ASC_MIN_SENSE_LEN];
 331} ASC_SCSI_BIOS_REQ_Q;
 332
 333typedef struct asc_risc_q {
 334        uchar fwd;
 335        uchar bwd;
 336        ASC_SCSIQ_1 i1;
 337        ASC_SCSIQ_2 i2;
 338        ASC_SCSIQ_3 i3;
 339        ASC_SCSIQ_4 i4;
 340} ASC_RISC_Q;
 341
 342typedef struct asc_sg_list_q {
 343        uchar seq_no;
 344        uchar q_no;
 345        uchar cntl;
 346        uchar sg_head_qp;
 347        uchar sg_list_cnt;
 348        uchar sg_cur_list_cnt;
 349} ASC_SG_LIST_Q;
 350
 351typedef struct asc_risc_sg_list_q {
 352        uchar fwd;
 353        uchar bwd;
 354        ASC_SG_LIST_Q sg;
 355        ASC_SG_LIST sg_list[7];
 356} ASC_RISC_SG_LIST_Q;
 357
 358#define ASCQ_ERR_Q_STATUS             0x0D
 359#define ASCQ_ERR_CUR_QNG              0x17
 360#define ASCQ_ERR_SG_Q_LINKS           0x18
 361#define ASCQ_ERR_ISR_RE_ENTRY         0x1A
 362#define ASCQ_ERR_CRITICAL_RE_ENTRY    0x1B
 363#define ASCQ_ERR_ISR_ON_CRITICAL      0x1C
 364
 365/*
 366 * Warning code values are set in ASC_DVC_VAR  'warn_code'.
 367 */
 368#define ASC_WARN_NO_ERROR             0x0000
 369#define ASC_WARN_IO_PORT_ROTATE       0x0001
 370#define ASC_WARN_EEPROM_CHKSUM        0x0002
 371#define ASC_WARN_IRQ_MODIFIED         0x0004
 372#define ASC_WARN_AUTO_CONFIG          0x0008
 373#define ASC_WARN_CMD_QNG_CONFLICT     0x0010
 374#define ASC_WARN_EEPROM_RECOVER       0x0020
 375#define ASC_WARN_CFG_MSW_RECOVER      0x0040
 376
 377/*
 378 * Error code values are set in {ASC/ADV}_DVC_VAR  'err_code'.
 379 */
 380#define ASC_IERR_NO_CARRIER             0x0001  /* No more carrier memory */
 381#define ASC_IERR_MCODE_CHKSUM           0x0002  /* micro code check sum error */
 382#define ASC_IERR_SET_PC_ADDR            0x0004
 383#define ASC_IERR_START_STOP_CHIP        0x0008  /* start/stop chip failed */
 384#define ASC_IERR_ILLEGAL_CONNECTION     0x0010  /* Illegal cable connection */
 385#define ASC_IERR_SINGLE_END_DEVICE      0x0020  /* SE device on DIFF bus */
 386#define ASC_IERR_REVERSED_CABLE         0x0040  /* Narrow flat cable reversed */
 387#define ASC_IERR_SET_SCSI_ID            0x0080  /* set SCSI ID failed */
 388#define ASC_IERR_HVD_DEVICE             0x0100  /* HVD device on LVD port */
 389#define ASC_IERR_BAD_SIGNATURE          0x0200  /* signature not found */
 390#define ASC_IERR_NO_BUS_TYPE            0x0400
 391#define ASC_IERR_BIST_PRE_TEST          0x0800  /* BIST pre-test error */
 392#define ASC_IERR_BIST_RAM_TEST          0x1000  /* BIST RAM test error */
 393#define ASC_IERR_BAD_CHIPTYPE           0x2000  /* Invalid chip_type setting */
 394
 395#define ASC_DEF_MAX_TOTAL_QNG   (0xF0)
 396#define ASC_MIN_TAG_Q_PER_DVC   (0x04)
 397#define ASC_MIN_FREE_Q        (0x02)
 398#define ASC_MIN_TOTAL_QNG     ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q))
 399#define ASC_MAX_TOTAL_QNG 240
 400#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16
 401#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG   8
 402#define ASC_MAX_PCI_INRAM_TOTAL_QNG  20
 403#define ASC_MAX_INRAM_TAG_QNG   16
 404#define ASC_IOADR_GAP   0x10
 405#define ASC_SYN_MAX_OFFSET         0x0F
 406#define ASC_DEF_SDTR_OFFSET        0x0F
 407#define ASC_SDTR_ULTRA_PCI_10MB_INDEX  0x02
 408#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41
 409
 410/* The narrow chip only supports a limited selection of transfer rates.
 411 * These are encoded in the range 0..7 or 0..15 depending whether the chip
 412 * is Ultra-capable or not.  These tables let us convert from one to the other.
 413 */
 414static const unsigned char asc_syn_xfer_period[8] = {
 415        25, 30, 35, 40, 50, 60, 70, 85
 416};
 417
 418static const unsigned char asc_syn_ultra_xfer_period[16] = {
 419        12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107
 420};
 421
 422typedef struct ext_msg {
 423        uchar msg_type;
 424        uchar msg_len;
 425        uchar msg_req;
 426        union {
 427                struct {
 428                        uchar sdtr_xfer_period;
 429                        uchar sdtr_req_ack_offset;
 430                } sdtr;
 431                struct {
 432                        uchar wdtr_width;
 433                } wdtr;
 434                struct {
 435                        uchar mdp_b3;
 436                        uchar mdp_b2;
 437                        uchar mdp_b1;
 438                        uchar mdp_b0;
 439                } mdp;
 440        } u_ext_msg;
 441        uchar res;
 442} EXT_MSG;
 443
 444#define xfer_period     u_ext_msg.sdtr.sdtr_xfer_period
 445#define req_ack_offset  u_ext_msg.sdtr.sdtr_req_ack_offset
 446#define wdtr_width      u_ext_msg.wdtr.wdtr_width
 447#define mdp_b3          u_ext_msg.mdp_b3
 448#define mdp_b2          u_ext_msg.mdp_b2
 449#define mdp_b1          u_ext_msg.mdp_b1
 450#define mdp_b0          u_ext_msg.mdp_b0
 451
 452typedef struct asc_dvc_cfg {
 453        ASC_SCSI_BIT_ID_TYPE can_tagged_qng;
 454        ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled;
 455        ASC_SCSI_BIT_ID_TYPE disc_enable;
 456        ASC_SCSI_BIT_ID_TYPE sdtr_enable;
 457        uchar chip_scsi_id;
 458        uchar chip_version;
 459        ushort mcode_date;
 460        ushort mcode_version;
 461        uchar max_tag_qng[ASC_MAX_TID + 1];
 462        uchar sdtr_period_offset[ASC_MAX_TID + 1];
 463        uchar adapter_info[6];
 464} ASC_DVC_CFG;
 465
 466#define ASC_DEF_DVC_CNTL       0xFFFF
 467#define ASC_DEF_CHIP_SCSI_ID   7
 468#define ASC_DEF_ISA_DMA_SPEED  4
 469#define ASC_INIT_STATE_BEG_GET_CFG   0x0001
 470#define ASC_INIT_STATE_END_GET_CFG   0x0002
 471#define ASC_INIT_STATE_BEG_SET_CFG   0x0004
 472#define ASC_INIT_STATE_END_SET_CFG   0x0008
 473#define ASC_INIT_STATE_BEG_LOAD_MC   0x0010
 474#define ASC_INIT_STATE_END_LOAD_MC   0x0020
 475#define ASC_INIT_STATE_BEG_INQUIRY   0x0040
 476#define ASC_INIT_STATE_END_INQUIRY   0x0080
 477#define ASC_INIT_RESET_SCSI_DONE     0x0100
 478#define ASC_INIT_STATE_WITHOUT_EEP   0x8000
 479#define ASC_BUG_FIX_IF_NOT_DWB       0x0001
 480#define ASC_BUG_FIX_ASYN_USE_SYN     0x0002
 481#define ASC_MIN_TAGGED_CMD  7
 482#define ASC_MAX_SCSI_RESET_WAIT      30
 483#define ASC_OVERRUN_BSIZE               64
 484
 485struct asc_dvc_var;             /* Forward Declaration. */
 486
 487typedef struct asc_dvc_var {
 488        PortAddr iop_base;
 489        ushort err_code;
 490        ushort dvc_cntl;
 491        ushort bug_fix_cntl;
 492        ushort bus_type;
 493        ASC_SCSI_BIT_ID_TYPE init_sdtr;
 494        ASC_SCSI_BIT_ID_TYPE sdtr_done;
 495        ASC_SCSI_BIT_ID_TYPE use_tagged_qng;
 496        ASC_SCSI_BIT_ID_TYPE unit_not_ready;
 497        ASC_SCSI_BIT_ID_TYPE queue_full_or_busy;
 498        ASC_SCSI_BIT_ID_TYPE start_motor;
 499        uchar *overrun_buf;
 500        dma_addr_t overrun_dma;
 501        uchar scsi_reset_wait;
 502        uchar chip_no;
 503        bool is_in_int;
 504        uchar max_total_qng;
 505        uchar cur_total_qng;
 506        uchar in_critical_cnt;
 507        uchar last_q_shortage;
 508        ushort init_state;
 509        uchar cur_dvc_qng[ASC_MAX_TID + 1];
 510        uchar max_dvc_qng[ASC_MAX_TID + 1];
 511        ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1];
 512        ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1];
 513        const uchar *sdtr_period_tbl;
 514        ASC_DVC_CFG *cfg;
 515        ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always;
 516        char redo_scam;
 517        ushort res2;
 518        uchar dos_int13_table[ASC_MAX_TID + 1];
 519        unsigned int max_dma_count;
 520        ASC_SCSI_BIT_ID_TYPE no_scam;
 521        ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer;
 522        uchar min_sdtr_index;
 523        uchar max_sdtr_index;
 524        struct asc_board *drv_ptr;
 525        unsigned int uc_break;
 526} ASC_DVC_VAR;
 527
 528typedef struct asc_dvc_inq_info {
 529        uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 530} ASC_DVC_INQ_INFO;
 531
 532typedef struct asc_cap_info {
 533        u32 lba;
 534        u32 blk_size;
 535} ASC_CAP_INFO;
 536
 537typedef struct asc_cap_info_array {
 538        ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1];
 539} ASC_CAP_INFO_ARRAY;
 540
 541#define ASC_MCNTL_NO_SEL_TIMEOUT  (ushort)0x0001
 542#define ASC_MCNTL_NULL_TARGET     (ushort)0x0002
 543#define ASC_CNTL_INITIATOR         (ushort)0x0001
 544#define ASC_CNTL_BIOS_GT_1GB       (ushort)0x0002
 545#define ASC_CNTL_BIOS_GT_2_DISK    (ushort)0x0004
 546#define ASC_CNTL_BIOS_REMOVABLE    (ushort)0x0008
 547#define ASC_CNTL_NO_SCAM           (ushort)0x0010
 548#define ASC_CNTL_INT_MULTI_Q       (ushort)0x0080
 549#define ASC_CNTL_NO_LUN_SUPPORT    (ushort)0x0040
 550#define ASC_CNTL_NO_VERIFY_COPY    (ushort)0x0100
 551#define ASC_CNTL_RESET_SCSI        (ushort)0x0200
 552#define ASC_CNTL_INIT_INQUIRY      (ushort)0x0400
 553#define ASC_CNTL_INIT_VERBOSE      (ushort)0x0800
 554#define ASC_CNTL_SCSI_PARITY       (ushort)0x1000
 555#define ASC_CNTL_BURST_MODE        (ushort)0x2000
 556#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000
 557#define ASC_EEP_DVC_CFG_BEG_VL    2
 558#define ASC_EEP_MAX_DVC_ADDR_VL   15
 559#define ASC_EEP_DVC_CFG_BEG      32
 560#define ASC_EEP_MAX_DVC_ADDR     45
 561#define ASC_EEP_MAX_RETRY        20
 562
 563/*
 564 * These macros keep the chip SCSI id  bitfields in board order. C bitfields
 565 * aren't portable between big and little-endian platforms so they are not used.
 566 */
 567
 568#define ASC_EEP_GET_CHIP_ID(cfg)    ((cfg)->id_speed & 0x0f)
 569#define ASC_EEP_GET_DMA_SPD(cfg)    (((cfg)->id_speed & 0xf0) >> 4)
 570#define ASC_EEP_SET_CHIP_ID(cfg, sid) \
 571   ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID))
 572#define ASC_EEP_SET_DMA_SPD(cfg, spd) \
 573   ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4)
 574
 575typedef struct asceep_config {
 576        ushort cfg_lsw;
 577        ushort cfg_msw;
 578        uchar init_sdtr;
 579        uchar disc_enable;
 580        uchar use_cmd_qng;
 581        uchar start_motor;
 582        uchar max_total_qng;
 583        uchar max_tag_qng;
 584        uchar bios_scan;
 585        uchar power_up_wait;
 586        uchar no_scam;
 587        uchar id_speed;         /* low order 4 bits is chip scsi id */
 588        /* high order 4 bits is isa dma speed */
 589        uchar dos_int13_table[ASC_MAX_TID + 1];
 590        uchar adapter_info[6];
 591        ushort cntl;
 592        ushort chksum;
 593} ASCEEP_CONFIG;
 594
 595#define ASC_EEP_CMD_READ          0x80
 596#define ASC_EEP_CMD_WRITE         0x40
 597#define ASC_EEP_CMD_WRITE_ABLE    0x30
 598#define ASC_EEP_CMD_WRITE_DISABLE 0x00
 599#define ASCV_MSGOUT_BEG         0x0000
 600#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3)
 601#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4)
 602#define ASCV_BREAK_SAVED_CODE   (ushort)0x0006
 603#define ASCV_MSGIN_BEG          (ASCV_MSGOUT_BEG+8)
 604#define ASCV_MSGIN_SDTR_PERIOD  (ASCV_MSGIN_BEG+3)
 605#define ASCV_MSGIN_SDTR_OFFSET  (ASCV_MSGIN_BEG+4)
 606#define ASCV_SDTR_DATA_BEG      (ASCV_MSGIN_BEG+8)
 607#define ASCV_SDTR_DONE_BEG      (ASCV_SDTR_DATA_BEG+8)
 608#define ASCV_MAX_DVC_QNG_BEG    (ushort)0x0020
 609#define ASCV_BREAK_ADDR           (ushort)0x0028
 610#define ASCV_BREAK_NOTIFY_COUNT   (ushort)0x002A
 611#define ASCV_BREAK_CONTROL        (ushort)0x002C
 612#define ASCV_BREAK_HIT_COUNT      (ushort)0x002E
 613
 614#define ASCV_ASCDVC_ERR_CODE_W  (ushort)0x0030
 615#define ASCV_MCODE_CHKSUM_W   (ushort)0x0032
 616#define ASCV_MCODE_SIZE_W     (ushort)0x0034
 617#define ASCV_STOP_CODE_B      (ushort)0x0036
 618#define ASCV_DVC_ERR_CODE_B   (ushort)0x0037
 619#define ASCV_OVERRUN_PADDR_D  (ushort)0x0038
 620#define ASCV_OVERRUN_BSIZE_D  (ushort)0x003C
 621#define ASCV_HALTCODE_W       (ushort)0x0040
 622#define ASCV_CHKSUM_W         (ushort)0x0042
 623#define ASCV_MC_DATE_W        (ushort)0x0044
 624#define ASCV_MC_VER_W         (ushort)0x0046
 625#define ASCV_NEXTRDY_B        (ushort)0x0048
 626#define ASCV_DONENEXT_B       (ushort)0x0049
 627#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A
 628#define ASCV_SCSIBUSY_B       (ushort)0x004B
 629#define ASCV_Q_DONE_IN_PROGRESS_B  (ushort)0x004C
 630#define ASCV_CURCDB_B         (ushort)0x004D
 631#define ASCV_RCLUN_B          (ushort)0x004E
 632#define ASCV_BUSY_QHEAD_B     (ushort)0x004F
 633#define ASCV_DISC1_QHEAD_B    (ushort)0x0050
 634#define ASCV_DISC_ENABLE_B    (ushort)0x0052
 635#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053
 636#define ASCV_HOSTSCSI_ID_B    (ushort)0x0055
 637#define ASCV_MCODE_CNTL_B     (ushort)0x0056
 638#define ASCV_NULL_TARGET_B    (ushort)0x0057
 639#define ASCV_FREE_Q_HEAD_W    (ushort)0x0058
 640#define ASCV_DONE_Q_TAIL_W    (ushort)0x005A
 641#define ASCV_FREE_Q_HEAD_B    (ushort)(ASCV_FREE_Q_HEAD_W+1)
 642#define ASCV_DONE_Q_TAIL_B    (ushort)(ASCV_DONE_Q_TAIL_W+1)
 643#define ASCV_HOST_FLAG_B      (ushort)0x005D
 644#define ASCV_TOTAL_READY_Q_B  (ushort)0x0064
 645#define ASCV_VER_SERIAL_B     (ushort)0x0065
 646#define ASCV_HALTCODE_SAVED_W (ushort)0x0066
 647#define ASCV_WTM_FLAG_B       (ushort)0x0068
 648#define ASCV_RISC_FLAG_B      (ushort)0x006A
 649#define ASCV_REQ_SG_LIST_QP   (ushort)0x006B
 650#define ASC_HOST_FLAG_IN_ISR        0x01
 651#define ASC_HOST_FLAG_ACK_INT       0x02
 652#define ASC_RISC_FLAG_GEN_INT      0x01
 653#define ASC_RISC_FLAG_REQ_SG_LIST  0x02
 654#define IOP_CTRL         (0x0F)
 655#define IOP_STATUS       (0x0E)
 656#define IOP_INT_ACK      IOP_STATUS
 657#define IOP_REG_IFC      (0x0D)
 658#define IOP_SYN_OFFSET    (0x0B)
 659#define IOP_EXTRA_CONTROL (0x0D)
 660#define IOP_REG_PC        (0x0C)
 661#define IOP_RAM_ADDR      (0x0A)
 662#define IOP_RAM_DATA      (0x08)
 663#define IOP_EEP_DATA      (0x06)
 664#define IOP_EEP_CMD       (0x07)
 665#define IOP_VERSION       (0x03)
 666#define IOP_CONFIG_HIGH   (0x04)
 667#define IOP_CONFIG_LOW    (0x02)
 668#define IOP_SIG_BYTE      (0x01)
 669#define IOP_SIG_WORD      (0x00)
 670#define IOP_REG_DC1      (0x0E)
 671#define IOP_REG_DC0      (0x0C)
 672#define IOP_REG_SB       (0x0B)
 673#define IOP_REG_DA1      (0x0A)
 674#define IOP_REG_DA0      (0x08)
 675#define IOP_REG_SC       (0x09)
 676#define IOP_DMA_SPEED    (0x07)
 677#define IOP_REG_FLAG     (0x07)
 678#define IOP_FIFO_H       (0x06)
 679#define IOP_FIFO_L       (0x04)
 680#define IOP_REG_ID       (0x05)
 681#define IOP_REG_QP       (0x03)
 682#define IOP_REG_IH       (0x02)
 683#define IOP_REG_IX       (0x01)
 684#define IOP_REG_AX       (0x00)
 685#define IFC_REG_LOCK      (0x00)
 686#define IFC_REG_UNLOCK    (0x09)
 687#define IFC_WR_EN_FILTER  (0x10)
 688#define IFC_RD_NO_EEPROM  (0x10)
 689#define IFC_SLEW_RATE     (0x20)
 690#define IFC_ACT_NEG       (0x40)
 691#define IFC_INP_FILTER    (0x80)
 692#define IFC_INIT_DEFAULT  (IFC_ACT_NEG | IFC_REG_UNLOCK)
 693#define SC_SEL   (uchar)(0x80)
 694#define SC_BSY   (uchar)(0x40)
 695#define SC_ACK   (uchar)(0x20)
 696#define SC_REQ   (uchar)(0x10)
 697#define SC_ATN   (uchar)(0x08)
 698#define SC_IO    (uchar)(0x04)
 699#define SC_CD    (uchar)(0x02)
 700#define SC_MSG   (uchar)(0x01)
 701#define SEC_SCSI_CTL         (uchar)(0x80)
 702#define SEC_ACTIVE_NEGATE    (uchar)(0x40)
 703#define SEC_SLEW_RATE        (uchar)(0x20)
 704#define SEC_ENABLE_FILTER    (uchar)(0x10)
 705#define ASC_HALT_EXTMSG_IN     (ushort)0x8000
 706#define ASC_HALT_CHK_CONDITION (ushort)0x8100
 707#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200
 708#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX  (ushort)0x8300
 709#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX   (ushort)0x8400
 710#define ASC_HALT_SDTR_REJECTED (ushort)0x4000
 711#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000
 712#define ASC_MAX_QNO        0xF8
 713#define ASC_DATA_SEC_BEG   (ushort)0x0080
 714#define ASC_DATA_SEC_END   (ushort)0x0080
 715#define ASC_CODE_SEC_BEG   (ushort)0x0080
 716#define ASC_CODE_SEC_END   (ushort)0x0080
 717#define ASC_QADR_BEG       (0x4000)
 718#define ASC_QADR_USED      (ushort)(ASC_MAX_QNO * 64)
 719#define ASC_QADR_END       (ushort)0x7FFF
 720#define ASC_QLAST_ADR      (ushort)0x7FC0
 721#define ASC_QBLK_SIZE      0x40
 722#define ASC_BIOS_DATA_QBEG 0xF8
 723#define ASC_MIN_ACTIVE_QNO 0x01
 724#define ASC_QLINK_END      0xFF
 725#define ASC_EEPROM_WORDS   0x10
 726#define ASC_MAX_MGS_LEN    0x10
 727#define ASC_BIOS_ADDR_DEF  0xDC00
 728#define ASC_BIOS_SIZE      0x3800
 729#define ASC_BIOS_RAM_OFF   0x3800
 730#define ASC_BIOS_RAM_SIZE  0x800
 731#define ASC_BIOS_MIN_ADDR  0xC000
 732#define ASC_BIOS_MAX_ADDR  0xEC00
 733#define ASC_BIOS_BANK_SIZE 0x0400
 734#define ASC_MCODE_START_ADDR  0x0080
 735#define ASC_CFG0_HOST_INT_ON    0x0020
 736#define ASC_CFG0_BIOS_ON        0x0040
 737#define ASC_CFG0_VERA_BURST_ON  0x0080
 738#define ASC_CFG0_SCSI_PARITY_ON 0x0800
 739#define ASC_CFG1_SCSI_TARGET_ON 0x0080
 740#define ASC_CFG1_LRAM_8BITS_ON  0x0800
 741#define ASC_CFG_MSW_CLR_MASK    0x3080
 742#define CSW_TEST1             (ASC_CS_TYPE)0x8000
 743#define CSW_AUTO_CONFIG       (ASC_CS_TYPE)0x4000
 744#define CSW_RESERVED1         (ASC_CS_TYPE)0x2000
 745#define CSW_IRQ_WRITTEN       (ASC_CS_TYPE)0x1000
 746#define CSW_33MHZ_SELECTED    (ASC_CS_TYPE)0x0800
 747#define CSW_TEST2             (ASC_CS_TYPE)0x0400
 748#define CSW_TEST3             (ASC_CS_TYPE)0x0200
 749#define CSW_RESERVED2         (ASC_CS_TYPE)0x0100
 750#define CSW_DMA_DONE          (ASC_CS_TYPE)0x0080
 751#define CSW_FIFO_RDY          (ASC_CS_TYPE)0x0040
 752#define CSW_EEP_READ_DONE     (ASC_CS_TYPE)0x0020
 753#define CSW_HALTED            (ASC_CS_TYPE)0x0010
 754#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008
 755#define CSW_PARITY_ERR        (ASC_CS_TYPE)0x0004
 756#define CSW_SCSI_RESET_LATCH  (ASC_CS_TYPE)0x0002
 757#define CSW_INT_PENDING       (ASC_CS_TYPE)0x0001
 758#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000
 759#define CIW_INT_ACK      (ASC_CS_TYPE)0x0100
 760#define CIW_TEST1        (ASC_CS_TYPE)0x0200
 761#define CIW_TEST2        (ASC_CS_TYPE)0x0400
 762#define CIW_SEL_33MHZ    (ASC_CS_TYPE)0x0800
 763#define CIW_IRQ_ACT      (ASC_CS_TYPE)0x1000
 764#define CC_CHIP_RESET   (uchar)0x80
 765#define CC_SCSI_RESET   (uchar)0x40
 766#define CC_HALT         (uchar)0x20
 767#define CC_SINGLE_STEP  (uchar)0x10
 768#define CC_DMA_ABLE     (uchar)0x08
 769#define CC_TEST         (uchar)0x04
 770#define CC_BANK_ONE     (uchar)0x02
 771#define CC_DIAG         (uchar)0x01
 772#define ASC_1000_ID0W      0x04C1
 773#define ASC_1000_ID0W_FIX  0x00C1
 774#define ASC_1000_ID1B      0x25
 775#define ASC_EISA_REV_IOP_MASK  (0x0C83)
 776#define ASC_EISA_CFG_IOP_MASK  (0x0C86)
 777#define ASC_GET_EISA_SLOT(iop)  (PortAddr)((iop) & 0xF000)
 778#define INS_HALTINT        (ushort)0x6281
 779#define INS_HALT           (ushort)0x6280
 780#define INS_SINT           (ushort)0x6200
 781#define INS_RFLAG_WTM      (ushort)0x7380
 782#define ASC_MC_SAVE_CODE_WSIZE  0x500
 783#define ASC_MC_SAVE_DATA_WSIZE  0x40
 784
 785typedef struct asc_mc_saved {
 786        ushort data[ASC_MC_SAVE_DATA_WSIZE];
 787        ushort code[ASC_MC_SAVE_CODE_WSIZE];
 788} ASC_MC_SAVED;
 789
 790#define AscGetQDoneInProgress(port)         AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B)
 791#define AscPutQDoneInProgress(port, val)    AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val)
 792#define AscGetVarFreeQHead(port)            AscReadLramWord((port), ASCV_FREE_Q_HEAD_W)
 793#define AscGetVarDoneQTail(port)            AscReadLramWord((port), ASCV_DONE_Q_TAIL_W)
 794#define AscPutVarFreeQHead(port, val)       AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val)
 795#define AscPutVarDoneQTail(port, val)       AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val)
 796#define AscGetRiscVarFreeQHead(port)        AscReadLramByte((port), ASCV_NEXTRDY_B)
 797#define AscGetRiscVarDoneQTail(port)        AscReadLramByte((port), ASCV_DONENEXT_B)
 798#define AscPutRiscVarFreeQHead(port, val)   AscWriteLramByte((port), ASCV_NEXTRDY_B, val)
 799#define AscPutRiscVarDoneQTail(port, val)   AscWriteLramByte((port), ASCV_DONENEXT_B, val)
 800#define AscPutMCodeSDTRDoneAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data))
 801#define AscGetMCodeSDTRDoneAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id))
 802#define AscPutMCodeInitSDTRAtID(port, id, data)  AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data)
 803#define AscGetMCodeInitSDTRAtID(port, id)        AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id))
 804#define AscGetChipSignatureByte(port)     (uchar)inp((port)+IOP_SIG_BYTE)
 805#define AscGetChipSignatureWord(port)     (ushort)inpw((port)+IOP_SIG_WORD)
 806#define AscGetChipVerNo(port)             (uchar)inp((port)+IOP_VERSION)
 807#define AscGetChipCfgLsw(port)            (ushort)inpw((port)+IOP_CONFIG_LOW)
 808#define AscGetChipCfgMsw(port)            (ushort)inpw((port)+IOP_CONFIG_HIGH)
 809#define AscSetChipCfgLsw(port, data)      outpw((port)+IOP_CONFIG_LOW, data)
 810#define AscSetChipCfgMsw(port, data)      outpw((port)+IOP_CONFIG_HIGH, data)
 811#define AscGetChipEEPCmd(port)            (uchar)inp((port)+IOP_EEP_CMD)
 812#define AscSetChipEEPCmd(port, data)      outp((port)+IOP_EEP_CMD, data)
 813#define AscGetChipEEPData(port)           (ushort)inpw((port)+IOP_EEP_DATA)
 814#define AscSetChipEEPData(port, data)     outpw((port)+IOP_EEP_DATA, data)
 815#define AscGetChipLramAddr(port)          (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR))
 816#define AscSetChipLramAddr(port, addr)    outpw((PortAddr)((port)+IOP_RAM_ADDR), addr)
 817#define AscGetChipLramData(port)          (ushort)inpw((port)+IOP_RAM_DATA)
 818#define AscSetChipLramData(port, data)    outpw((port)+IOP_RAM_DATA, data)
 819#define AscGetChipIFC(port)               (uchar)inp((port)+IOP_REG_IFC)
 820#define AscSetChipIFC(port, data)          outp((port)+IOP_REG_IFC, data)
 821#define AscGetChipStatus(port)            (ASC_CS_TYPE)inpw((port)+IOP_STATUS)
 822#define AscSetChipStatus(port, cs_val)    outpw((port)+IOP_STATUS, cs_val)
 823#define AscGetChipControl(port)           (uchar)inp((port)+IOP_CTRL)
 824#define AscSetChipControl(port, cc_val)   outp((port)+IOP_CTRL, cc_val)
 825#define AscGetChipSyn(port)               (uchar)inp((port)+IOP_SYN_OFFSET)
 826#define AscSetChipSyn(port, data)         outp((port)+IOP_SYN_OFFSET, data)
 827#define AscSetPCAddr(port, data)          outpw((port)+IOP_REG_PC, data)
 828#define AscGetPCAddr(port)                (ushort)inpw((port)+IOP_REG_PC)
 829#define AscIsIntPending(port)             (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH))
 830#define AscGetChipScsiID(port)            ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID)
 831#define AscGetExtraControl(port)          (uchar)inp((port)+IOP_EXTRA_CONTROL)
 832#define AscSetExtraControl(port, data)    outp((port)+IOP_EXTRA_CONTROL, data)
 833#define AscReadChipAX(port)               (ushort)inpw((port)+IOP_REG_AX)
 834#define AscWriteChipAX(port, data)        outpw((port)+IOP_REG_AX, data)
 835#define AscReadChipIX(port)               (uchar)inp((port)+IOP_REG_IX)
 836#define AscWriteChipIX(port, data)        outp((port)+IOP_REG_IX, data)
 837#define AscReadChipIH(port)               (ushort)inpw((port)+IOP_REG_IH)
 838#define AscWriteChipIH(port, data)        outpw((port)+IOP_REG_IH, data)
 839#define AscReadChipQP(port)               (uchar)inp((port)+IOP_REG_QP)
 840#define AscWriteChipQP(port, data)        outp((port)+IOP_REG_QP, data)
 841#define AscReadChipFIFO_L(port)           (ushort)inpw((port)+IOP_REG_FIFO_L)
 842#define AscWriteChipFIFO_L(port, data)    outpw((port)+IOP_REG_FIFO_L, data)
 843#define AscReadChipFIFO_H(port)           (ushort)inpw((port)+IOP_REG_FIFO_H)
 844#define AscWriteChipFIFO_H(port, data)    outpw((port)+IOP_REG_FIFO_H, data)
 845#define AscReadChipDmaSpeed(port)         (uchar)inp((port)+IOP_DMA_SPEED)
 846#define AscWriteChipDmaSpeed(port, data)  outp((port)+IOP_DMA_SPEED, data)
 847#define AscReadChipDA0(port)              (ushort)inpw((port)+IOP_REG_DA0)
 848#define AscWriteChipDA0(port)             outpw((port)+IOP_REG_DA0, data)
 849#define AscReadChipDA1(port)              (ushort)inpw((port)+IOP_REG_DA1)
 850#define AscWriteChipDA1(port)             outpw((port)+IOP_REG_DA1, data)
 851#define AscReadChipDC0(port)              (ushort)inpw((port)+IOP_REG_DC0)
 852#define AscWriteChipDC0(port)             outpw((port)+IOP_REG_DC0, data)
 853#define AscReadChipDC1(port)              (ushort)inpw((port)+IOP_REG_DC1)
 854#define AscWriteChipDC1(port)             outpw((port)+IOP_REG_DC1, data)
 855#define AscReadChipDvcID(port)            (uchar)inp((port)+IOP_REG_ID)
 856#define AscWriteChipDvcID(port, data)     outp((port)+IOP_REG_ID, data)
 857
 858#define AdvPortAddr  void __iomem *     /* Virtual memory address size */
 859
 860/*
 861 * Define Adv Library required memory access macros.
 862 */
 863#define ADV_MEM_READB(addr) readb(addr)
 864#define ADV_MEM_READW(addr) readw(addr)
 865#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr)
 866#define ADV_MEM_WRITEW(addr, word) writew(word, addr)
 867#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr)
 868
 869/*
 870 * Define total number of simultaneous maximum element scatter-gather
 871 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the
 872 * maximum number of outstanding commands per wide host adapter. Each
 873 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather
 874 * elements. Allow each command to have at least one ADV_SG_BLOCK structure.
 875 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK
 876 * structures or 255 scatter-gather elements.
 877 */
 878#define ADV_TOT_SG_BLOCK        ASC_DEF_MAX_HOST_QNG
 879
 880/*
 881 * Define maximum number of scatter-gather elements per request.
 882 */
 883#define ADV_MAX_SG_LIST         255
 884#define NO_OF_SG_PER_BLOCK              15
 885
 886#define ADV_EEP_DVC_CFG_BEGIN           (0x00)
 887#define ADV_EEP_DVC_CFG_END             (0x15)
 888#define ADV_EEP_DVC_CTL_BEGIN           (0x16)  /* location of OEM name */
 889#define ADV_EEP_MAX_WORD_ADDR           (0x1E)
 890
 891#define ADV_EEP_DELAY_MS                100
 892
 893#define ADV_EEPROM_BIG_ENDIAN          0x8000   /* EEPROM Bit 15 */
 894#define ADV_EEPROM_BIOS_ENABLE         0x4000   /* EEPROM Bit 14 */
 895/*
 896 * For the ASC3550 Bit 13 is Termination Polarity control bit.
 897 * For later ICs Bit 13 controls whether the CIS (Card Information
 898 * Service Section) is loaded from EEPROM.
 899 */
 900#define ADV_EEPROM_TERM_POL            0x2000   /* EEPROM Bit 13 */
 901#define ADV_EEPROM_CIS_LD              0x2000   /* EEPROM Bit 13 */
 902/*
 903 * ASC38C1600 Bit 11
 904 *
 905 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify
 906 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then
 907 * Function 0 will specify INT B.
 908 *
 909 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify
 910 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then
 911 * Function 1 will specify INT A.
 912 */
 913#define ADV_EEPROM_INTAB               0x0800   /* EEPROM Bit 11 */
 914
 915typedef struct adveep_3550_config {
 916        /* Word Offset, Description */
 917
 918        ushort cfg_lsw;         /* 00 power up initialization */
 919        /*  bit 13 set - Term Polarity Control */
 920        /*  bit 14 set - BIOS Enable */
 921        /*  bit 15 set - Big Endian Mode */
 922        ushort cfg_msw;         /* 01 unused      */
 923        ushort disc_enable;     /* 02 disconnect enable */
 924        ushort wdtr_able;       /* 03 Wide DTR able */
 925        ushort sdtr_able;       /* 04 Synchronous DTR able */
 926        ushort start_motor;     /* 05 send start up motor */
 927        ushort tagqng_able;     /* 06 tag queuing able */
 928        ushort bios_scan;       /* 07 BIOS device control */
 929        ushort scam_tolerant;   /* 08 no scam */
 930
 931        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
 932        uchar bios_boot_delay;  /*    power up wait */
 933
 934        uchar scsi_reset_delay; /* 10 reset delay */
 935        uchar bios_id_lun;      /*    first boot device scsi id & lun */
 936        /*    high nibble is lun */
 937        /*    low nibble is scsi id */
 938
 939        uchar termination;      /* 11 0 - automatic */
 940        /*    1 - low off / high off */
 941        /*    2 - low off / high on */
 942        /*    3 - low on  / high on */
 943        /*    There is no low on  / high off */
 944
 945        uchar reserved1;        /*    reserved byte (not used) */
 946
 947        ushort bios_ctrl;       /* 12 BIOS control bits */
 948        /*  bit 0  BIOS don't act as initiator. */
 949        /*  bit 1  BIOS > 1 GB support */
 950        /*  bit 2  BIOS > 2 Disk Support */
 951        /*  bit 3  BIOS don't support removables */
 952        /*  bit 4  BIOS support bootable CD */
 953        /*  bit 5  BIOS scan enabled */
 954        /*  bit 6  BIOS support multiple LUNs */
 955        /*  bit 7  BIOS display of message */
 956        /*  bit 8  SCAM disabled */
 957        /*  bit 9  Reset SCSI bus during init. */
 958        /*  bit 10 */
 959        /*  bit 11 No verbose initialization. */
 960        /*  bit 12 SCSI parity enabled */
 961        /*  bit 13 */
 962        /*  bit 14 */
 963        /*  bit 15 */
 964        ushort ultra_able;      /* 13 ULTRA speed able */
 965        ushort reserved2;       /* 14 reserved */
 966        uchar max_host_qng;     /* 15 maximum host queuing */
 967        uchar max_dvc_qng;      /*    maximum per device queuing */
 968        ushort dvc_cntl;        /* 16 control bit for driver */
 969        ushort bug_fix;         /* 17 control bit for bug fix */
 970        ushort serial_number_word1;     /* 18 Board serial number word 1 */
 971        ushort serial_number_word2;     /* 19 Board serial number word 2 */
 972        ushort serial_number_word3;     /* 20 Board serial number word 3 */
 973        ushort check_sum;       /* 21 EEP check sum */
 974        uchar oem_name[16];     /* 22 OEM name */
 975        ushort dvc_err_code;    /* 30 last device driver error code */
 976        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
 977        ushort adv_err_addr;    /* 32 last uc error address */
 978        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
 979        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
 980        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
 981        ushort num_of_err;      /* 36 number of error */
 982} ADVEEP_3550_CONFIG;
 983
 984typedef struct adveep_38C0800_config {
 985        /* Word Offset, Description */
 986
 987        ushort cfg_lsw;         /* 00 power up initialization */
 988        /*  bit 13 set - Load CIS */
 989        /*  bit 14 set - BIOS Enable */
 990        /*  bit 15 set - Big Endian Mode */
 991        ushort cfg_msw;         /* 01 unused      */
 992        ushort disc_enable;     /* 02 disconnect enable */
 993        ushort wdtr_able;       /* 03 Wide DTR able */
 994        ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
 995        ushort start_motor;     /* 05 send start up motor */
 996        ushort tagqng_able;     /* 06 tag queuing able */
 997        ushort bios_scan;       /* 07 BIOS device control */
 998        ushort scam_tolerant;   /* 08 no scam */
 999
1000        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1001        uchar bios_boot_delay;  /*    power up wait */
1002
1003        uchar scsi_reset_delay; /* 10 reset delay */
1004        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1005        /*    high nibble is lun */
1006        /*    low nibble is scsi id */
1007
1008        uchar termination_se;   /* 11 0 - automatic */
1009        /*    1 - low off / high off */
1010        /*    2 - low off / high on */
1011        /*    3 - low on  / high on */
1012        /*    There is no low on  / high off */
1013
1014        uchar termination_lvd;  /* 11 0 - automatic */
1015        /*    1 - low off / high off */
1016        /*    2 - low off / high on */
1017        /*    3 - low on  / high on */
1018        /*    There is no low on  / high off */
1019
1020        ushort bios_ctrl;       /* 12 BIOS control bits */
1021        /*  bit 0  BIOS don't act as initiator. */
1022        /*  bit 1  BIOS > 1 GB support */
1023        /*  bit 2  BIOS > 2 Disk Support */
1024        /*  bit 3  BIOS don't support removables */
1025        /*  bit 4  BIOS support bootable CD */
1026        /*  bit 5  BIOS scan enabled */
1027        /*  bit 6  BIOS support multiple LUNs */
1028        /*  bit 7  BIOS display of message */
1029        /*  bit 8  SCAM disabled */
1030        /*  bit 9  Reset SCSI bus during init. */
1031        /*  bit 10 */
1032        /*  bit 11 No verbose initialization. */
1033        /*  bit 12 SCSI parity enabled */
1034        /*  bit 13 */
1035        /*  bit 14 */
1036        /*  bit 15 */
1037        ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1038        ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1039        uchar max_host_qng;     /* 15 maximum host queueing */
1040        uchar max_dvc_qng;      /*    maximum per device queuing */
1041        ushort dvc_cntl;        /* 16 control bit for driver */
1042        ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1043        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1044        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1045        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1046        ushort check_sum;       /* 21 EEP check sum */
1047        uchar oem_name[16];     /* 22 OEM name */
1048        ushort dvc_err_code;    /* 30 last device driver error code */
1049        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1050        ushort adv_err_addr;    /* 32 last uc error address */
1051        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1052        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1053        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1054        ushort reserved36;      /* 36 reserved */
1055        ushort reserved37;      /* 37 reserved */
1056        ushort reserved38;      /* 38 reserved */
1057        ushort reserved39;      /* 39 reserved */
1058        ushort reserved40;      /* 40 reserved */
1059        ushort reserved41;      /* 41 reserved */
1060        ushort reserved42;      /* 42 reserved */
1061        ushort reserved43;      /* 43 reserved */
1062        ushort reserved44;      /* 44 reserved */
1063        ushort reserved45;      /* 45 reserved */
1064        ushort reserved46;      /* 46 reserved */
1065        ushort reserved47;      /* 47 reserved */
1066        ushort reserved48;      /* 48 reserved */
1067        ushort reserved49;      /* 49 reserved */
1068        ushort reserved50;      /* 50 reserved */
1069        ushort reserved51;      /* 51 reserved */
1070        ushort reserved52;      /* 52 reserved */
1071        ushort reserved53;      /* 53 reserved */
1072        ushort reserved54;      /* 54 reserved */
1073        ushort reserved55;      /* 55 reserved */
1074        ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1075        ushort cisprt_msw;      /* 57 CIS PTR MSW */
1076        ushort subsysvid;       /* 58 SubSystem Vendor ID */
1077        ushort subsysid;        /* 59 SubSystem ID */
1078        ushort reserved60;      /* 60 reserved */
1079        ushort reserved61;      /* 61 reserved */
1080        ushort reserved62;      /* 62 reserved */
1081        ushort reserved63;      /* 63 reserved */
1082} ADVEEP_38C0800_CONFIG;
1083
1084typedef struct adveep_38C1600_config {
1085        /* Word Offset, Description */
1086
1087        ushort cfg_lsw;         /* 00 power up initialization */
1088        /*  bit 11 set - Func. 0 INTB, Func. 1 INTA */
1089        /*       clear - Func. 0 INTA, Func. 1 INTB */
1090        /*  bit 13 set - Load CIS */
1091        /*  bit 14 set - BIOS Enable */
1092        /*  bit 15 set - Big Endian Mode */
1093        ushort cfg_msw;         /* 01 unused */
1094        ushort disc_enable;     /* 02 disconnect enable */
1095        ushort wdtr_able;       /* 03 Wide DTR able */
1096        ushort sdtr_speed1;     /* 04 SDTR Speed TID 0-3 */
1097        ushort start_motor;     /* 05 send start up motor */
1098        ushort tagqng_able;     /* 06 tag queuing able */
1099        ushort bios_scan;       /* 07 BIOS device control */
1100        ushort scam_tolerant;   /* 08 no scam */
1101
1102        uchar adapter_scsi_id;  /* 09 Host Adapter ID */
1103        uchar bios_boot_delay;  /*    power up wait */
1104
1105        uchar scsi_reset_delay; /* 10 reset delay */
1106        uchar bios_id_lun;      /*    first boot device scsi id & lun */
1107        /*    high nibble is lun */
1108        /*    low nibble is scsi id */
1109
1110        uchar termination_se;   /* 11 0 - automatic */
1111        /*    1 - low off / high off */
1112        /*    2 - low off / high on */
1113        /*    3 - low on  / high on */
1114        /*    There is no low on  / high off */
1115
1116        uchar termination_lvd;  /* 11 0 - automatic */
1117        /*    1 - low off / high off */
1118        /*    2 - low off / high on */
1119        /*    3 - low on  / high on */
1120        /*    There is no low on  / high off */
1121
1122        ushort bios_ctrl;       /* 12 BIOS control bits */
1123        /*  bit 0  BIOS don't act as initiator. */
1124        /*  bit 1  BIOS > 1 GB support */
1125        /*  bit 2  BIOS > 2 Disk Support */
1126        /*  bit 3  BIOS don't support removables */
1127        /*  bit 4  BIOS support bootable CD */
1128        /*  bit 5  BIOS scan enabled */
1129        /*  bit 6  BIOS support multiple LUNs */
1130        /*  bit 7  BIOS display of message */
1131        /*  bit 8  SCAM disabled */
1132        /*  bit 9  Reset SCSI bus during init. */
1133        /*  bit 10 Basic Integrity Checking disabled */
1134        /*  bit 11 No verbose initialization. */
1135        /*  bit 12 SCSI parity enabled */
1136        /*  bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */
1137        /*  bit 14 */
1138        /*  bit 15 */
1139        ushort sdtr_speed2;     /* 13 SDTR speed TID 4-7 */
1140        ushort sdtr_speed3;     /* 14 SDTR speed TID 8-11 */
1141        uchar max_host_qng;     /* 15 maximum host queueing */
1142        uchar max_dvc_qng;      /*    maximum per device queuing */
1143        ushort dvc_cntl;        /* 16 control bit for driver */
1144        ushort sdtr_speed4;     /* 17 SDTR speed 4 TID 12-15 */
1145        ushort serial_number_word1;     /* 18 Board serial number word 1 */
1146        ushort serial_number_word2;     /* 19 Board serial number word 2 */
1147        ushort serial_number_word3;     /* 20 Board serial number word 3 */
1148        ushort check_sum;       /* 21 EEP check sum */
1149        uchar oem_name[16];     /* 22 OEM name */
1150        ushort dvc_err_code;    /* 30 last device driver error code */
1151        ushort adv_err_code;    /* 31 last uc and Adv Lib error code */
1152        ushort adv_err_addr;    /* 32 last uc error address */
1153        ushort saved_dvc_err_code;      /* 33 saved last dev. driver error code   */
1154        ushort saved_adv_err_code;      /* 34 saved last uc and Adv Lib error code */
1155        ushort saved_adv_err_addr;      /* 35 saved last uc error address         */
1156        ushort reserved36;      /* 36 reserved */
1157        ushort reserved37;      /* 37 reserved */
1158        ushort reserved38;      /* 38 reserved */
1159        ushort reserved39;      /* 39 reserved */
1160        ushort reserved40;      /* 40 reserved */
1161        ushort reserved41;      /* 41 reserved */
1162        ushort reserved42;      /* 42 reserved */
1163        ushort reserved43;      /* 43 reserved */
1164        ushort reserved44;      /* 44 reserved */
1165        ushort reserved45;      /* 45 reserved */
1166        ushort reserved46;      /* 46 reserved */
1167        ushort reserved47;      /* 47 reserved */
1168        ushort reserved48;      /* 48 reserved */
1169        ushort reserved49;      /* 49 reserved */
1170        ushort reserved50;      /* 50 reserved */
1171        ushort reserved51;      /* 51 reserved */
1172        ushort reserved52;      /* 52 reserved */
1173        ushort reserved53;      /* 53 reserved */
1174        ushort reserved54;      /* 54 reserved */
1175        ushort reserved55;      /* 55 reserved */
1176        ushort cisptr_lsw;      /* 56 CIS PTR LSW */
1177        ushort cisprt_msw;      /* 57 CIS PTR MSW */
1178        ushort subsysvid;       /* 58 SubSystem Vendor ID */
1179        ushort subsysid;        /* 59 SubSystem ID */
1180        ushort reserved60;      /* 60 reserved */
1181        ushort reserved61;      /* 61 reserved */
1182        ushort reserved62;      /* 62 reserved */
1183        ushort reserved63;      /* 63 reserved */
1184} ADVEEP_38C1600_CONFIG;
1185
1186/*
1187 * EEPROM Commands
1188 */
1189#define ASC_EEP_CMD_DONE             0x0200
1190
1191/* bios_ctrl */
1192#define BIOS_CTRL_BIOS               0x0001
1193#define BIOS_CTRL_EXTENDED_XLAT      0x0002
1194#define BIOS_CTRL_GT_2_DISK          0x0004
1195#define BIOS_CTRL_BIOS_REMOVABLE     0x0008
1196#define BIOS_CTRL_BOOTABLE_CD        0x0010
1197#define BIOS_CTRL_MULTIPLE_LUN       0x0040
1198#define BIOS_CTRL_DISPLAY_MSG        0x0080
1199#define BIOS_CTRL_NO_SCAM            0x0100
1200#define BIOS_CTRL_RESET_SCSI_BUS     0x0200
1201#define BIOS_CTRL_INIT_VERBOSE       0x0800
1202#define BIOS_CTRL_SCSI_PARITY        0x1000
1203#define BIOS_CTRL_AIPP_DIS           0x2000
1204
1205#define ADV_3550_MEMSIZE   0x2000       /* 8 KB Internal Memory */
1206
1207#define ADV_38C0800_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1208
1209/*
1210 * XXX - Since ASC38C1600 Rev.3 has a local RAM failure issue, there is
1211 * a special 16K Adv Library and Microcode version. After the issue is
1212 * resolved, should restore 32K support.
1213 *
1214 * #define ADV_38C1600_MEMSIZE  0x8000L   * 32 KB Internal Memory *
1215 */
1216#define ADV_38C1600_MEMSIZE  0x4000     /* 16 KB Internal Memory */
1217
1218/*
1219 * Byte I/O register address from base of 'iop_base'.
1220 */
1221#define IOPB_INTR_STATUS_REG    0x00
1222#define IOPB_CHIP_ID_1          0x01
1223#define IOPB_INTR_ENABLES       0x02
1224#define IOPB_CHIP_TYPE_REV      0x03
1225#define IOPB_RES_ADDR_4         0x04
1226#define IOPB_RES_ADDR_5         0x05
1227#define IOPB_RAM_DATA           0x06
1228#define IOPB_RES_ADDR_7         0x07
1229#define IOPB_FLAG_REG           0x08
1230#define IOPB_RES_ADDR_9         0x09
1231#define IOPB_RISC_CSR           0x0A
1232#define IOPB_RES_ADDR_B         0x0B
1233#define IOPB_RES_ADDR_C         0x0C
1234#define IOPB_RES_ADDR_D         0x0D
1235#define IOPB_SOFT_OVER_WR       0x0E
1236#define IOPB_RES_ADDR_F         0x0F
1237#define IOPB_MEM_CFG            0x10
1238#define IOPB_RES_ADDR_11        0x11
1239#define IOPB_GPIO_DATA          0x12
1240#define IOPB_RES_ADDR_13        0x13
1241#define IOPB_FLASH_PAGE         0x14
1242#define IOPB_RES_ADDR_15        0x15
1243#define IOPB_GPIO_CNTL          0x16
1244#define IOPB_RES_ADDR_17        0x17
1245#define IOPB_FLASH_DATA         0x18
1246#define IOPB_RES_ADDR_19        0x19
1247#define IOPB_RES_ADDR_1A        0x1A
1248#define IOPB_RES_ADDR_1B        0x1B
1249#define IOPB_RES_ADDR_1C        0x1C
1250#define IOPB_RES_ADDR_1D        0x1D
1251#define IOPB_RES_ADDR_1E        0x1E
1252#define IOPB_RES_ADDR_1F        0x1F
1253#define IOPB_DMA_CFG0           0x20
1254#define IOPB_DMA_CFG1           0x21
1255#define IOPB_TICKLE             0x22
1256#define IOPB_DMA_REG_WR         0x23
1257#define IOPB_SDMA_STATUS        0x24
1258#define IOPB_SCSI_BYTE_CNT      0x25
1259#define IOPB_HOST_BYTE_CNT      0x26
1260#define IOPB_BYTE_LEFT_TO_XFER  0x27
1261#define IOPB_BYTE_TO_XFER_0     0x28
1262#define IOPB_BYTE_TO_XFER_1     0x29
1263#define IOPB_BYTE_TO_XFER_2     0x2A
1264#define IOPB_BYTE_TO_XFER_3     0x2B
1265#define IOPB_ACC_GRP            0x2C
1266#define IOPB_RES_ADDR_2D        0x2D
1267#define IOPB_DEV_ID             0x2E
1268#define IOPB_RES_ADDR_2F        0x2F
1269#define IOPB_SCSI_DATA          0x30
1270#define IOPB_RES_ADDR_31        0x31
1271#define IOPB_RES_ADDR_32        0x32
1272#define IOPB_SCSI_DATA_HSHK     0x33
1273#define IOPB_SCSI_CTRL          0x34
1274#define IOPB_RES_ADDR_35        0x35
1275#define IOPB_RES_ADDR_36        0x36
1276#define IOPB_RES_ADDR_37        0x37
1277#define IOPB_RAM_BIST           0x38
1278#define IOPB_PLL_TEST           0x39
1279#define IOPB_PCI_INT_CFG        0x3A
1280#define IOPB_RES_ADDR_3B        0x3B
1281#define IOPB_RFIFO_CNT          0x3C
1282#define IOPB_RES_ADDR_3D        0x3D
1283#define IOPB_RES_ADDR_3E        0x3E
1284#define IOPB_RES_ADDR_3F        0x3F
1285
1286/*
1287 * Word I/O register address from base of 'iop_base'.
1288 */
1289#define IOPW_CHIP_ID_0          0x00    /* CID0  */
1290#define IOPW_CTRL_REG           0x02    /* CC    */
1291#define IOPW_RAM_ADDR           0x04    /* LA    */
1292#define IOPW_RAM_DATA           0x06    /* LD    */
1293#define IOPW_RES_ADDR_08        0x08
1294#define IOPW_RISC_CSR           0x0A    /* CSR   */
1295#define IOPW_SCSI_CFG0          0x0C    /* CFG0  */
1296#define IOPW_SCSI_CFG1          0x0E    /* CFG1  */
1297#define IOPW_RES_ADDR_10        0x10
1298#define IOPW_SEL_MASK           0x12    /* SM    */
1299#define IOPW_RES_ADDR_14        0x14
1300#define IOPW_FLASH_ADDR         0x16    /* FA    */
1301#define IOPW_RES_ADDR_18        0x18
1302#define IOPW_EE_CMD             0x1A    /* EC    */
1303#define IOPW_EE_DATA            0x1C    /* ED    */
1304#define IOPW_SFIFO_CNT          0x1E    /* SFC   */
1305#define IOPW_RES_ADDR_20        0x20
1306#define IOPW_Q_BASE             0x22    /* QB    */
1307#define IOPW_QP                 0x24    /* QP    */
1308#define IOPW_IX                 0x26    /* IX    */
1309#define IOPW_SP                 0x28    /* SP    */
1310#define IOPW_PC                 0x2A    /* PC    */
1311#define IOPW_RES_ADDR_2C        0x2C
1312#define IOPW_RES_ADDR_2E        0x2E
1313#define IOPW_SCSI_DATA          0x30    /* SD    */
1314#define IOPW_SCSI_DATA_HSHK     0x32    /* SDH   */
1315#define IOPW_SCSI_CTRL          0x34    /* SC    */
1316#define IOPW_HSHK_CFG           0x36    /* HCFG  */
1317#define IOPW_SXFR_STATUS        0x36    /* SXS   */
1318#define IOPW_SXFR_CNTL          0x38    /* SXL   */
1319#define IOPW_SXFR_CNTH          0x3A    /* SXH   */
1320#define IOPW_RES_ADDR_3C        0x3C
1321#define IOPW_RFIFO_DATA         0x3E    /* RFD   */
1322
1323/*
1324 * Doubleword I/O register address from base of 'iop_base'.
1325 */
1326#define IOPDW_RES_ADDR_0         0x00
1327#define IOPDW_RAM_DATA           0x04
1328#define IOPDW_RES_ADDR_8         0x08
1329#define IOPDW_RES_ADDR_C         0x0C
1330#define IOPDW_RES_ADDR_10        0x10
1331#define IOPDW_COMMA              0x14
1332#define IOPDW_COMMB              0x18
1333#define IOPDW_RES_ADDR_1C        0x1C
1334#define IOPDW_SDMA_ADDR0         0x20
1335#define IOPDW_SDMA_ADDR1         0x24
1336#define IOPDW_SDMA_COUNT         0x28
1337#define IOPDW_SDMA_ERROR         0x2C
1338#define IOPDW_RDMA_ADDR0         0x30
1339#define IOPDW_RDMA_ADDR1         0x34
1340#define IOPDW_RDMA_COUNT         0x38
1341#define IOPDW_RDMA_ERROR         0x3C
1342
1343#define ADV_CHIP_ID_BYTE         0x25
1344#define ADV_CHIP_ID_WORD         0x04C1
1345
1346#define ADV_INTR_ENABLE_HOST_INTR                   0x01
1347#define ADV_INTR_ENABLE_SEL_INTR                    0x02
1348#define ADV_INTR_ENABLE_DPR_INTR                    0x04
1349#define ADV_INTR_ENABLE_RTA_INTR                    0x08
1350#define ADV_INTR_ENABLE_RMA_INTR                    0x10
1351#define ADV_INTR_ENABLE_RST_INTR                    0x20
1352#define ADV_INTR_ENABLE_DPE_INTR                    0x40
1353#define ADV_INTR_ENABLE_GLOBAL_INTR                 0x80
1354
1355#define ADV_INTR_STATUS_INTRA            0x01
1356#define ADV_INTR_STATUS_INTRB            0x02
1357#define ADV_INTR_STATUS_INTRC            0x04
1358
1359#define ADV_RISC_CSR_STOP           (0x0000)
1360#define ADV_RISC_TEST_COND          (0x2000)
1361#define ADV_RISC_CSR_RUN            (0x4000)
1362#define ADV_RISC_CSR_SINGLE_STEP    (0x8000)
1363
1364#define ADV_CTRL_REG_HOST_INTR      0x0100
1365#define ADV_CTRL_REG_SEL_INTR       0x0200
1366#define ADV_CTRL_REG_DPR_INTR       0x0400
1367#define ADV_CTRL_REG_RTA_INTR       0x0800
1368#define ADV_CTRL_REG_RMA_INTR       0x1000
1369#define ADV_CTRL_REG_RES_BIT14      0x2000
1370#define ADV_CTRL_REG_DPE_INTR       0x4000
1371#define ADV_CTRL_REG_POWER_DONE     0x8000
1372#define ADV_CTRL_REG_ANY_INTR       0xFF00
1373
1374#define ADV_CTRL_REG_CMD_RESET             0x00C6
1375#define ADV_CTRL_REG_CMD_WR_IO_REG         0x00C5
1376#define ADV_CTRL_REG_CMD_RD_IO_REG         0x00C4
1377#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE  0x00C3
1378#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE  0x00C2
1379
1380#define ADV_TICKLE_NOP                      0x00
1381#define ADV_TICKLE_A                        0x01
1382#define ADV_TICKLE_B                        0x02
1383#define ADV_TICKLE_C                        0x03
1384
1385#define AdvIsIntPending(port) \
1386    (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR)
1387
1388/*
1389 * SCSI_CFG0 Register bit definitions
1390 */
1391#define TIMER_MODEAB    0xC000  /* Watchdog, Second, and Select. Timer Ctrl. */
1392#define PARITY_EN       0x2000  /* Enable SCSI Parity Error detection */
1393#define EVEN_PARITY     0x1000  /* Select Even Parity */
1394#define WD_LONG         0x0800  /* Watchdog Interval, 1: 57 min, 0: 13 sec */
1395#define QUEUE_128       0x0400  /* Queue Size, 1: 128 byte, 0: 64 byte */
1396#define PRIM_MODE       0x0100  /* Primitive SCSI mode */
1397#define SCAM_EN         0x0080  /* Enable SCAM selection */
1398#define SEL_TMO_LONG    0x0040  /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */
1399#define CFRM_ID         0x0020  /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */
1400#define OUR_ID_EN       0x0010  /* Enable OUR_ID bits */
1401#define OUR_ID          0x000F  /* SCSI ID */
1402
1403/*
1404 * SCSI_CFG1 Register bit definitions
1405 */
1406#define BIG_ENDIAN      0x8000  /* Enable Big Endian Mode MIO:15, EEP:15 */
1407#define TERM_POL        0x2000  /* Terminator Polarity Ctrl. MIO:13, EEP:13 */
1408#define SLEW_RATE       0x1000  /* SCSI output buffer slew rate */
1409#define FILTER_SEL      0x0C00  /* Filter Period Selection */
1410#define  FLTR_DISABLE    0x0000 /* Input Filtering Disabled */
1411#define  FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */
1412#define  FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */
1413#define ACTIVE_DBL      0x0200  /* Disable Active Negation */
1414#define DIFF_MODE       0x0100  /* SCSI differential Mode (Read-Only) */
1415#define DIFF_SENSE      0x0080  /* 1: No SE cables, 0: SE cable (Read-Only) */
1416#define TERM_CTL_SEL    0x0040  /* Enable TERM_CTL_H and TERM_CTL_L */
1417#define TERM_CTL        0x0030  /* External SCSI Termination Bits */
1418#define  TERM_CTL_H      0x0020 /* Enable External SCSI Upper Termination */
1419#define  TERM_CTL_L      0x0010 /* Enable External SCSI Lower Termination */
1420#define CABLE_DETECT    0x000F  /* External SCSI Cable Connection Status */
1421
1422/*
1423 * Addendum for ASC-38C0800 Chip
1424 *
1425 * The ASC-38C1600 Chip uses the same definitions except that the
1426 * bus mode override bits [12:10] have been moved to byte register
1427 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in
1428 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV)
1429 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only.
1430 * Also each ASC-38C1600 function or channel uses only cable bits [5:4]
1431 * and [1:0]. Bits [14], [7:6], [3:2] are unused.
1432 */
1433#define DIS_TERM_DRV    0x4000  /* 1: Read c_det[3:0], 0: cannot read */
1434#define HVD_LVD_SE      0x1C00  /* Device Detect Bits */
1435#define  HVD             0x1000 /* HVD Device Detect */
1436#define  LVD             0x0800 /* LVD Device Detect */
1437#define  SE              0x0400 /* SE Device Detect */
1438#define TERM_LVD        0x00C0  /* LVD Termination Bits */
1439#define  TERM_LVD_HI     0x0080 /* Enable LVD Upper Termination */
1440#define  TERM_LVD_LO     0x0040 /* Enable LVD Lower Termination */
1441#define TERM_SE         0x0030  /* SE Termination Bits */
1442#define  TERM_SE_HI      0x0020 /* Enable SE Upper Termination */
1443#define  TERM_SE_LO      0x0010 /* Enable SE Lower Termination */
1444#define C_DET_LVD       0x000C  /* LVD Cable Detect Bits */
1445#define  C_DET3          0x0008 /* Cable Detect for LVD External Wide */
1446#define  C_DET2          0x0004 /* Cable Detect for LVD Internal Wide */
1447#define C_DET_SE        0x0003  /* SE Cable Detect Bits */
1448#define  C_DET1          0x0002 /* Cable Detect for SE Internal Wide */
1449#define  C_DET0          0x0001 /* Cable Detect for SE Internal Narrow */
1450
1451#define CABLE_ILLEGAL_A 0x7
1452    /* x 0 0 0  | on  on | Illegal (all 3 connectors are used) */
1453
1454#define CABLE_ILLEGAL_B 0xB
1455    /* 0 x 0 0  | on  on | Illegal (all 3 connectors are used) */
1456
1457/*
1458 * MEM_CFG Register bit definitions
1459 */
1460#define BIOS_EN         0x40    /* BIOS Enable MIO:14,EEP:14 */
1461#define FAST_EE_CLK     0x20    /* Diagnostic Bit */
1462#define RAM_SZ          0x1C    /* Specify size of RAM to RISC */
1463#define  RAM_SZ_2KB      0x00   /* 2 KB */
1464#define  RAM_SZ_4KB      0x04   /* 4 KB */
1465#define  RAM_SZ_8KB      0x08   /* 8 KB */
1466#define  RAM_SZ_16KB     0x0C   /* 16 KB */
1467#define  RAM_SZ_32KB     0x10   /* 32 KB */
1468#define  RAM_SZ_64KB     0x14   /* 64 KB */
1469
1470/*
1471 * DMA_CFG0 Register bit definitions
1472 *
1473 * This register is only accessible to the host.
1474 */
1475#define BC_THRESH_ENB   0x80    /* PCI DMA Start Conditions */
1476#define FIFO_THRESH     0x70    /* PCI DMA FIFO Threshold */
1477#define  FIFO_THRESH_16B  0x00  /* 16 bytes */
1478#define  FIFO_THRESH_32B  0x20  /* 32 bytes */
1479#define  FIFO_THRESH_48B  0x30  /* 48 bytes */
1480#define  FIFO_THRESH_64B  0x40  /* 64 bytes */
1481#define  FIFO_THRESH_80B  0x50  /* 80 bytes (default) */
1482#define  FIFO_THRESH_96B  0x60  /* 96 bytes */
1483#define  FIFO_THRESH_112B 0x70  /* 112 bytes */
1484#define START_CTL       0x0C    /* DMA start conditions */
1485#define  START_CTL_TH    0x00   /* Wait threshold level (default) */
1486#define  START_CTL_ID    0x04   /* Wait SDMA/SBUS idle */
1487#define  START_CTL_THID  0x08   /* Wait threshold and SDMA/SBUS idle */
1488#define  START_CTL_EMFU  0x0C   /* Wait SDMA FIFO empty/full */
1489#define READ_CMD        0x03    /* Memory Read Method */
1490#define  READ_CMD_MR     0x00   /* Memory Read */
1491#define  READ_CMD_MRL    0x02   /* Memory Read Long */
1492#define  READ_CMD_MRM    0x03   /* Memory Read Multiple (default) */
1493
1494/*
1495 * ASC-38C0800 RAM BIST Register bit definitions
1496 */
1497#define RAM_TEST_MODE         0x80
1498#define PRE_TEST_MODE         0x40
1499#define NORMAL_MODE           0x00
1500#define RAM_TEST_DONE         0x10
1501#define RAM_TEST_STATUS       0x0F
1502#define  RAM_TEST_HOST_ERROR   0x08
1503#define  RAM_TEST_INTRAM_ERROR 0x04
1504#define  RAM_TEST_RISC_ERROR   0x02
1505#define  RAM_TEST_SCSI_ERROR   0x01
1506#define  RAM_TEST_SUCCESS      0x00
1507#define PRE_TEST_VALUE        0x05
1508#define NORMAL_VALUE          0x00
1509
1510/*
1511 * ASC38C1600 Definitions
1512 *
1513 * IOPB_PCI_INT_CFG Bit Field Definitions
1514 */
1515
1516#define INTAB_LD        0x80    /* Value loaded from EEPROM Bit 11. */
1517
1518/*
1519 * Bit 1 can be set to change the interrupt for the Function to operate in
1520 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in
1521 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same
1522 * mode, otherwise the operating mode is undefined.
1523 */
1524#define TOTEMPOLE       0x02
1525
1526/*
1527 * Bit 0 can be used to change the Int Pin for the Function. The value is
1528 * 0 by default for both Functions with Function 0 using INT A and Function
1529 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set,
1530 * INT A is used.
1531 *
1532 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin
1533 * value specified in the PCI Configuration Space.
1534 */
1535#define INTAB           0x01
1536
1537/*
1538 * Adv Library Status Definitions
1539 */
1540#define ADV_TRUE        1
1541#define ADV_FALSE       0
1542#define ADV_SUCCESS     1
1543#define ADV_BUSY        0
1544#define ADV_ERROR       (-1)
1545
1546/*
1547 * ADV_DVC_VAR 'warn_code' values
1548 */
1549#define ASC_WARN_BUSRESET_ERROR         0x0001  /* SCSI Bus Reset error */
1550#define ASC_WARN_EEPROM_CHKSUM          0x0002  /* EEP check sum error */
1551#define ASC_WARN_EEPROM_TERMINATION     0x0004  /* EEP termination bad field */
1552#define ASC_WARN_ERROR                  0xFFFF  /* ADV_ERROR return */
1553
1554#define ADV_MAX_TID                     15      /* max. target identifier */
1555#define ADV_MAX_LUN                     7       /* max. logical unit number */
1556
1557/*
1558 * Fixed locations of microcode operating variables.
1559 */
1560#define ASC_MC_CODE_BEGIN_ADDR          0x0028  /* microcode start address */
1561#define ASC_MC_CODE_END_ADDR            0x002A  /* microcode end address */
1562#define ASC_MC_CODE_CHK_SUM             0x002C  /* microcode code checksum */
1563#define ASC_MC_VERSION_DATE             0x0038  /* microcode version */
1564#define ASC_MC_VERSION_NUM              0x003A  /* microcode number */
1565#define ASC_MC_BIOSMEM                  0x0040  /* BIOS RISC Memory Start */
1566#define ASC_MC_BIOSLEN                  0x0050  /* BIOS RISC Memory Length */
1567#define ASC_MC_BIOS_SIGNATURE           0x0058  /* BIOS Signature 0x55AA */
1568#define ASC_MC_BIOS_VERSION             0x005A  /* BIOS Version (2 bytes) */
1569#define ASC_MC_SDTR_SPEED1              0x0090  /* SDTR Speed for TID 0-3 */
1570#define ASC_MC_SDTR_SPEED2              0x0092  /* SDTR Speed for TID 4-7 */
1571#define ASC_MC_SDTR_SPEED3              0x0094  /* SDTR Speed for TID 8-11 */
1572#define ASC_MC_SDTR_SPEED4              0x0096  /* SDTR Speed for TID 12-15 */
1573#define ASC_MC_CHIP_TYPE                0x009A
1574#define ASC_MC_INTRB_CODE               0x009B
1575#define ASC_MC_WDTR_ABLE                0x009C
1576#define ASC_MC_SDTR_ABLE                0x009E
1577#define ASC_MC_TAGQNG_ABLE              0x00A0
1578#define ASC_MC_DISC_ENABLE              0x00A2
1579#define ASC_MC_IDLE_CMD_STATUS          0x00A4
1580#define ASC_MC_IDLE_CMD                 0x00A6
1581#define ASC_MC_IDLE_CMD_PARAMETER       0x00A8
1582#define ASC_MC_DEFAULT_SCSI_CFG0        0x00AC
1583#define ASC_MC_DEFAULT_SCSI_CFG1        0x00AE
1584#define ASC_MC_DEFAULT_MEM_CFG          0x00B0
1585#define ASC_MC_DEFAULT_SEL_MASK         0x00B2
1586#define ASC_MC_SDTR_DONE                0x00B6
1587#define ASC_MC_NUMBER_OF_QUEUED_CMD     0x00C0
1588#define ASC_MC_NUMBER_OF_MAX_CMD        0x00D0
1589#define ASC_MC_DEVICE_HSHK_CFG_TABLE    0x0100
1590#define ASC_MC_CONTROL_FLAG             0x0122  /* Microcode control flag. */
1591#define ASC_MC_WDTR_DONE                0x0124
1592#define ASC_MC_CAM_MODE_MASK            0x015E  /* CAM mode TID bitmask. */
1593#define ASC_MC_ICQ                      0x0160
1594#define ASC_MC_IRQ                      0x0164
1595#define ASC_MC_PPR_ABLE                 0x017A
1596
1597/*
1598 * BIOS LRAM variable absolute offsets.
1599 */
1600#define BIOS_CODESEG    0x54
1601#define BIOS_CODELEN    0x56
1602#define BIOS_SIGNATURE  0x58
1603#define BIOS_VERSION    0x5A
1604
1605/*
1606 * Microcode Control Flags
1607 *
1608 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122)
1609 * and handled by the microcode.
1610 */
1611#define CONTROL_FLAG_IGNORE_PERR        0x0001  /* Ignore DMA Parity Errors */
1612#define CONTROL_FLAG_ENABLE_AIPP        0x0002  /* Enabled AIPP checking. */
1613
1614/*
1615 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format
1616 */
1617#define HSHK_CFG_WIDE_XFR       0x8000
1618#define HSHK_CFG_RATE           0x0F00
1619#define HSHK_CFG_OFFSET         0x001F
1620
1621#define ASC_DEF_MAX_HOST_QNG    0xFD    /* Max. number of host commands (253) */
1622#define ASC_DEF_MIN_HOST_QNG    0x10    /* Min. number of host commands (16) */
1623#define ASC_DEF_MAX_DVC_QNG     0x3F    /* Max. number commands per device (63) */
1624#define ASC_DEF_MIN_DVC_QNG     0x04    /* Min. number commands per device (4) */
1625
1626#define ASC_QC_DATA_CHECK  0x01 /* Require ASC_QC_DATA_OUT set or clear. */
1627#define ASC_QC_DATA_OUT    0x02 /* Data out DMA transfer. */
1628#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */
1629#define ASC_QC_NO_OVERRUN  0x08 /* Don't report overrun. */
1630#define ASC_QC_FREEZE_TIDQ 0x10 /* Freeze TID queue after request. XXX TBD */
1631
1632#define ASC_QSC_NO_DISC     0x01        /* Don't allow disconnect for request. */
1633#define ASC_QSC_NO_TAGMSG   0x02        /* Don't allow tag queuing for request. */
1634#define ASC_QSC_NO_SYNC     0x04        /* Don't use Synch. transfer on request. */
1635#define ASC_QSC_NO_WIDE     0x08        /* Don't use Wide transfer on request. */
1636#define ASC_QSC_REDO_DTR    0x10        /* Renegotiate WDTR/SDTR before request. */
1637/*
1638 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or
1639 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used.
1640 */
1641#define ASC_QSC_HEAD_TAG    0x40        /* Use Head Tag Message (0x21). */
1642#define ASC_QSC_ORDERED_TAG 0x80        /* Use Ordered Tag Message (0x22). */
1643
1644/*
1645 * All fields here are accessed by the board microcode and need to be
1646 * little-endian.
1647 */
1648typedef struct adv_carr_t {
1649        __le32 carr_va; /* Carrier Virtual Address */
1650        __le32 carr_pa; /* Carrier Physical Address */
1651        __le32 areq_vpa;        /* ADV_SCSI_REQ_Q Virtual or Physical Address */
1652        /*
1653         * next_vpa [31:4]            Carrier Virtual or Physical Next Pointer
1654         *
1655         * next_vpa [3:1]             Reserved Bits
1656         * next_vpa [0]               Done Flag set in Response Queue.
1657         */
1658        __le32 next_vpa;
1659} ADV_CARR_T;
1660
1661/*
1662 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field.
1663 */
1664#define ADV_NEXT_VPA_MASK       0xFFFFFFF0
1665
1666#define ADV_RQ_DONE             0x00000001
1667#define ADV_RQ_GOOD             0x00000002
1668#define ADV_CQ_STOPPER          0x00000000
1669
1670#define ADV_GET_CARRP(carrp) ((carrp) & ADV_NEXT_VPA_MASK)
1671
1672/*
1673 * Each carrier is 64 bytes, and we need three additional
1674 * carrier for icq, irq, and the termination carrier.
1675 */
1676#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 3)
1677
1678#define ADV_CARRIER_BUFSIZE \
1679        (ADV_CARRIER_COUNT * sizeof(ADV_CARR_T))
1680
1681#define ADV_CHIP_ASC3550          0x01  /* Ultra-Wide IC */
1682#define ADV_CHIP_ASC38C0800       0x02  /* Ultra2-Wide/LVD IC */
1683#define ADV_CHIP_ASC38C1600       0x03  /* Ultra3-Wide/LVD2 IC */
1684
1685/*
1686 * Adapter temporary configuration structure
1687 *
1688 * This structure can be discarded after initialization. Don't add
1689 * fields here needed after initialization.
1690 *
1691 * Field naming convention:
1692 *
1693 *  *_enable indicates the field enables or disables a feature. The
1694 *  value of the field is never reset.
1695 */
1696typedef struct adv_dvc_cfg {
1697        ushort disc_enable;     /* enable disconnection */
1698        uchar chip_version;     /* chip version */
1699        uchar termination;      /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */
1700        ushort control_flag;    /* Microcode Control Flag */
1701        ushort mcode_date;      /* Microcode date */
1702        ushort mcode_version;   /* Microcode version */
1703        ushort serial1;         /* EEPROM serial number word 1 */
1704        ushort serial2;         /* EEPROM serial number word 2 */
1705        ushort serial3;         /* EEPROM serial number word 3 */
1706} ADV_DVC_CFG;
1707
1708struct adv_dvc_var;
1709struct adv_scsi_req_q;
1710
1711typedef struct adv_sg_block {
1712        uchar reserved1;
1713        uchar reserved2;
1714        uchar reserved3;
1715        uchar sg_cnt;           /* Valid entries in block. */
1716        __le32 sg_ptr;  /* Pointer to next sg block. */
1717        struct {
1718                __le32 sg_addr; /* SG element address. */
1719                __le32 sg_count;        /* SG element count. */
1720        } sg_list[NO_OF_SG_PER_BLOCK];
1721} ADV_SG_BLOCK;
1722
1723/*
1724 * ADV_SCSI_REQ_Q - microcode request structure
1725 *
1726 * All fields in this structure up to byte 60 are used by the microcode.
1727 * The microcode makes assumptions about the size and ordering of fields
1728 * in this structure. Do not change the structure definition here without
1729 * coordinating the change with the microcode.
1730 *
1731 * All fields accessed by microcode must be maintained in little_endian
1732 * order.
1733 */
1734typedef struct adv_scsi_req_q {
1735        uchar cntl;             /* Ucode flags and state (ASC_MC_QC_*). */
1736        uchar target_cmd;
1737        uchar target_id;        /* Device target identifier. */
1738        uchar target_lun;       /* Device target logical unit number. */
1739        __le32 data_addr;       /* Data buffer physical address. */
1740        __le32 data_cnt;        /* Data count. Ucode sets to residual. */
1741        __le32 sense_addr;
1742        __le32 carr_pa;
1743        uchar mflag;
1744        uchar sense_len;
1745        uchar cdb_len;          /* SCSI CDB length. Must <= 16 bytes. */
1746        uchar scsi_cntl;
1747        uchar done_status;      /* Completion status. */
1748        uchar scsi_status;      /* SCSI status byte. */
1749        uchar host_status;      /* Ucode host status. */
1750        uchar sg_working_ix;
1751        uchar cdb[12];          /* SCSI CDB bytes 0-11. */
1752        __le32 sg_real_addr;    /* SG list physical address. */
1753        __le32 scsiq_rptr;
1754        uchar cdb16[4];         /* SCSI CDB bytes 12-15. */
1755        __le32 scsiq_ptr;
1756        __le32 carr_va;
1757        /*
1758         * End of microcode structure - 60 bytes. The rest of the structure
1759         * is used by the Adv Library and ignored by the microcode.
1760         */
1761        u32 srb_tag;
1762        ADV_SG_BLOCK *sg_list_ptr;      /* SG list virtual address. */
1763} ADV_SCSI_REQ_Q;
1764
1765/*
1766 * The following two structures are used to process Wide Board requests.
1767 *
1768 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library
1769 * and microcode with the ADV_SCSI_REQ_Q field 'srb_tag' set to the
1770 * SCSI request tag. The adv_req_t structure 'cmndp' field in turn points
1771 * to the Mid-Level SCSI request structure.
1772 *
1773 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each
1774 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux
1775 * up to 255 scatter-gather elements may be used per request or
1776 * ADV_SCSI_REQ_Q.
1777 *
1778 * Both structures must be 32 byte aligned.
1779 */
1780typedef struct adv_sgblk {
1781        ADV_SG_BLOCK sg_block;  /* Sgblock structure. */
1782        dma_addr_t sg_addr;     /* Physical address */
1783        struct adv_sgblk *next_sgblkp;  /* Next scatter-gather structure. */
1784} adv_sgblk_t;
1785
1786typedef struct adv_req {
1787        ADV_SCSI_REQ_Q scsi_req_q;      /* Adv Library request structure. */
1788        uchar align[24];        /* Request structure padding. */
1789        struct scsi_cmnd *cmndp;        /* Mid-Level SCSI command pointer. */
1790        dma_addr_t req_addr;
1791        adv_sgblk_t *sgblkp;    /* Adv Library scatter-gather pointer. */
1792} adv_req_t __aligned(32);
1793
1794/*
1795 * Adapter operation variable structure.
1796 *
1797 * One structure is required per host adapter.
1798 *
1799 * Field naming convention:
1800 *
1801 *  *_able indicates both whether a feature should be enabled or disabled
1802 *  and whether a device is capable of the feature. At initialization
1803 *  this field may be set, but later if a device is found to be incapable
1804 *  of the feature, the field is cleared.
1805 */
1806typedef struct adv_dvc_var {
1807        AdvPortAddr iop_base;   /* I/O port address */
1808        ushort err_code;        /* fatal error code */
1809        ushort bios_ctrl;       /* BIOS control word, EEPROM word 12 */
1810        ushort wdtr_able;       /* try WDTR for a device */
1811        ushort sdtr_able;       /* try SDTR for a device */
1812        ushort ultra_able;      /* try SDTR Ultra speed for a device */
1813        ushort sdtr_speed1;     /* EEPROM SDTR Speed for TID 0-3   */
1814        ushort sdtr_speed2;     /* EEPROM SDTR Speed for TID 4-7   */
1815        ushort sdtr_speed3;     /* EEPROM SDTR Speed for TID 8-11  */
1816        ushort sdtr_speed4;     /* EEPROM SDTR Speed for TID 12-15 */
1817        ushort tagqng_able;     /* try tagged queuing with a device */
1818        ushort ppr_able;        /* PPR message capable per TID bitmask. */
1819        uchar max_dvc_qng;      /* maximum number of tagged commands per device */
1820        ushort start_motor;     /* start motor command allowed */
1821        uchar scsi_reset_wait;  /* delay in seconds after scsi bus reset */
1822        uchar chip_no;          /* should be assigned by caller */
1823        uchar max_host_qng;     /* maximum number of Q'ed command allowed */
1824        ushort no_scam;         /* scam_tolerant of EEPROM */
1825        struct asc_board *drv_ptr;      /* driver pointer to private structure */
1826        uchar chip_scsi_id;     /* chip SCSI target ID */
1827        uchar chip_type;
1828        uchar bist_err_code;
1829        ADV_CARR_T *carrier;
1830        ADV_CARR_T *carr_freelist;      /* Carrier free list. */
1831        dma_addr_t carrier_addr;
1832        ADV_CARR_T *icq_sp;     /* Initiator command queue stopper pointer. */
1833        ADV_CARR_T *irq_sp;     /* Initiator response queue stopper pointer. */
1834        ushort carr_pending_cnt;        /* Count of pending carriers. */
1835        /*
1836         * Note: The following fields will not be used after initialization. The
1837         * driver may discard the buffer after initialization is done.
1838         */
1839        ADV_DVC_CFG *cfg;       /* temporary configuration structure  */
1840} ADV_DVC_VAR;
1841
1842/*
1843 * Microcode idle loop commands
1844 */
1845#define IDLE_CMD_COMPLETED           0
1846#define IDLE_CMD_STOP_CHIP           0x0001
1847#define IDLE_CMD_STOP_CHIP_SEND_INT  0x0002
1848#define IDLE_CMD_SEND_INT            0x0004
1849#define IDLE_CMD_ABORT               0x0008
1850#define IDLE_CMD_DEVICE_RESET        0x0010
1851#define IDLE_CMD_SCSI_RESET_START    0x0020     /* Assert SCSI Bus Reset */
1852#define IDLE_CMD_SCSI_RESET_END      0x0040     /* Deassert SCSI Bus Reset */
1853#define IDLE_CMD_SCSIREQ             0x0080
1854
1855#define IDLE_CMD_STATUS_SUCCESS      0x0001
1856#define IDLE_CMD_STATUS_FAILURE      0x0002
1857
1858/*
1859 * AdvSendIdleCmd() flag definitions.
1860 */
1861#define ADV_NOWAIT     0x01
1862
1863/*
1864 * Wait loop time out values.
1865 */
1866#define SCSI_WAIT_100_MSEC           100UL      /* 100 milliseconds */
1867#define SCSI_US_PER_MSEC             1000       /* microseconds per millisecond */
1868#define SCSI_MAX_RETRY               10 /* retry count */
1869
1870#define ADV_ASYNC_RDMA_FAILURE          0x01    /* Fatal RDMA failure. */
1871#define ADV_ASYNC_SCSI_BUS_RESET_DET    0x02    /* Detected SCSI Bus Reset. */
1872#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03    /* Carrier Ready failure. */
1873#define ADV_RDMA_IN_CARR_AND_Q_INVALID  0x04    /* RDMAed-in data invalid. */
1874
1875#define ADV_HOST_SCSI_BUS_RESET      0x80       /* Host Initiated SCSI Bus Reset. */
1876
1877/* Read byte from a register. */
1878#define AdvReadByteRegister(iop_base, reg_off) \
1879     (ADV_MEM_READB((iop_base) + (reg_off)))
1880
1881/* Write byte to a register. */
1882#define AdvWriteByteRegister(iop_base, reg_off, byte) \
1883     (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte)))
1884
1885/* Read word (2 bytes) from a register. */
1886#define AdvReadWordRegister(iop_base, reg_off) \
1887     (ADV_MEM_READW((iop_base) + (reg_off)))
1888
1889/* Write word (2 bytes) to a register. */
1890#define AdvWriteWordRegister(iop_base, reg_off, word) \
1891     (ADV_MEM_WRITEW((iop_base) + (reg_off), (word)))
1892
1893/* Write dword (4 bytes) to a register. */
1894#define AdvWriteDWordRegister(iop_base, reg_off, dword) \
1895     (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword)))
1896
1897/* Read byte from LRAM. */
1898#define AdvReadByteLram(iop_base, addr, byte) \
1899do { \
1900    ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1901    (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \
1902} while (0)
1903
1904/* Write byte to LRAM. */
1905#define AdvWriteByteLram(iop_base, addr, byte) \
1906    (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1907     ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte)))
1908
1909/* Read word (2 bytes) from LRAM. */
1910#define AdvReadWordLram(iop_base, addr, word) \
1911do { \
1912    ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \
1913    (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \
1914} while (0)
1915
1916/* Write word (2 bytes) to LRAM. */
1917#define AdvWriteWordLram(iop_base, addr, word) \
1918    (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1919     ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1920
1921/* Write little-endian double word (4 bytes) to LRAM */
1922/* Because of unspecified C language ordering don't use auto-increment. */
1923#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \
1924    ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \
1925      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1926                     cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \
1927     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \
1928      ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \
1929                     cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF)))))
1930
1931/* Read word (2 bytes) from LRAM assuming that the address is already set. */
1932#define AdvReadWordAutoIncLram(iop_base) \
1933     (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA))
1934
1935/* Write word (2 bytes) to LRAM assuming that the address is already set. */
1936#define AdvWriteWordAutoIncLram(iop_base, word) \
1937     (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word)))
1938
1939/*
1940 * Define macro to check for Condor signature.
1941 *
1942 * Evaluate to ADV_TRUE if a Condor chip is found the specified port
1943 * address 'iop_base'. Otherwise evalue to ADV_FALSE.
1944 */
1945#define AdvFindSignature(iop_base) \
1946    (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \
1947    ADV_CHIP_ID_BYTE) && \
1948     (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \
1949    ADV_CHIP_ID_WORD)) ?  ADV_TRUE : ADV_FALSE)
1950
1951/*
1952 * Define macro to Return the version number of the chip at 'iop_base'.
1953 *
1954 * The second parameter 'bus_type' is currently unused.
1955 */
1956#define AdvGetChipVersion(iop_base, bus_type) \
1957    AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV)
1958
1959/*
1960 * Abort an SRB in the chip's RISC Memory. The 'srb_tag' argument must
1961 * match the ADV_SCSI_REQ_Q 'srb_tag' field.
1962 *
1963 * If the request has not yet been sent to the device it will simply be
1964 * aborted from RISC memory. If the request is disconnected it will be
1965 * aborted on reselection by sending an Abort Message to the target ID.
1966 *
1967 * Return value:
1968 *      ADV_TRUE(1) - Queue was successfully aborted.
1969 *      ADV_FALSE(0) - Queue was not found on the active queue list.
1970 */
1971#define AdvAbortQueue(asc_dvc, srb_tag) \
1972     AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \
1973                    (ADV_DCNT) (srb_tag))
1974
1975/*
1976 * Send a Bus Device Reset Message to the specified target ID.
1977 *
1978 * All outstanding commands will be purged if sending the
1979 * Bus Device Reset Message is successful.
1980 *
1981 * Return Value:
1982 *      ADV_TRUE(1) - All requests on the target are purged.
1983 *      ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests
1984 *                     are not purged.
1985 */
1986#define AdvResetDevice(asc_dvc, target_id) \
1987     AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET,  \
1988                    (ADV_DCNT) (target_id))
1989
1990/*
1991 * SCSI Wide Type definition.
1992 */
1993#define ADV_SCSI_BIT_ID_TYPE   ushort
1994
1995/*
1996 * AdvInitScsiTarget() 'cntl_flag' options.
1997 */
1998#define ADV_SCAN_LUN           0x01
1999#define ADV_CAPINFO_NOLUN      0x02
2000
2001/*
2002 * Convert target id to target id bit mask.
2003 */
2004#define ADV_TID_TO_TIDMASK(tid)   (0x01 << ((tid) & ADV_MAX_TID))
2005
2006/*
2007 * ADV_SCSI_REQ_Q 'done_status' and 'host_status' return values.
2008 */
2009
2010#define QD_NO_STATUS         0x00       /* Request not completed yet. */
2011#define QD_NO_ERROR          0x01
2012#define QD_ABORTED_BY_HOST   0x02
2013#define QD_WITH_ERROR        0x04
2014
2015#define QHSTA_NO_ERROR              0x00
2016#define QHSTA_M_SEL_TIMEOUT         0x11
2017#define QHSTA_M_DATA_OVER_RUN       0x12
2018#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13
2019#define QHSTA_M_QUEUE_ABORTED       0x15
2020#define QHSTA_M_SXFR_SDMA_ERR       0x16        /* SXFR_STATUS SCSI DMA Error */
2021#define QHSTA_M_SXFR_SXFR_PERR      0x17        /* SXFR_STATUS SCSI Bus Parity Error */
2022#define QHSTA_M_RDMA_PERR           0x18        /* RISC PCI DMA parity error */
2023#define QHSTA_M_SXFR_OFF_UFLW       0x19        /* SXFR_STATUS Offset Underflow */
2024#define QHSTA_M_SXFR_OFF_OFLW       0x20        /* SXFR_STATUS Offset Overflow */
2025#define QHSTA_M_SXFR_WD_TMO         0x21        /* SXFR_STATUS Watchdog Timeout */
2026#define QHSTA_M_SXFR_DESELECTED     0x22        /* SXFR_STATUS Deselected */
2027/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */
2028#define QHSTA_M_SXFR_XFR_OFLW       0x12        /* SXFR_STATUS Transfer Overflow */
2029#define QHSTA_M_SXFR_XFR_PH_ERR     0x24        /* SXFR_STATUS Transfer Phase Error */
2030#define QHSTA_M_SXFR_UNKNOWN_ERROR  0x25        /* SXFR_STATUS Unknown Error */
2031#define QHSTA_M_SCSI_BUS_RESET      0x30        /* Request aborted from SBR */
2032#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31       /* Request aborted from unsol. SBR */
2033#define QHSTA_M_BUS_DEVICE_RESET    0x32        /* Request aborted from BDR */
2034#define QHSTA_M_DIRECTION_ERR       0x35        /* Data Phase mismatch */
2035#define QHSTA_M_DIRECTION_ERR_HUNG  0x36        /* Data Phase mismatch and bus hang */
2036#define QHSTA_M_WTM_TIMEOUT         0x41
2037#define QHSTA_M_BAD_CMPL_STATUS_IN  0x42
2038#define QHSTA_M_NO_AUTO_REQ_SENSE   0x43
2039#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44
2040#define QHSTA_M_INVALID_DEVICE      0x45        /* Bad target ID */
2041#define QHSTA_M_FROZEN_TIDQ         0x46        /* TID Queue frozen. */
2042#define QHSTA_M_SGBACKUP_ERROR      0x47        /* Scatter-Gather backup error */
2043
2044/* Return the address that is aligned at the next doubleword >= to 'addr'. */
2045#define ADV_32BALIGN(addr)     (((ulong) (addr) + 0x1F) & ~0x1F)
2046
2047/*
2048 * Total contiguous memory needed for driver SG blocks.
2049 *
2050 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum
2051 * number of scatter-gather elements the driver supports in a
2052 * single request.
2053 */
2054
2055#define ADV_SG_LIST_MAX_BYTE_SIZE \
2056         (sizeof(ADV_SG_BLOCK) * \
2057          ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK))
2058
2059/* struct asc_board flags */
2060#define ASC_IS_WIDE_BOARD       0x04    /* AdvanSys Wide Board */
2061
2062#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0)
2063
2064#define NO_ISA_DMA              0xff    /* No ISA DMA Channel Used */
2065
2066#define ASC_INFO_SIZE           128     /* advansys_info() line size */
2067
2068/* Asc Library return codes */
2069#define ASC_TRUE        1
2070#define ASC_FALSE       0
2071#define ASC_NOERROR     1
2072#define ASC_BUSY        0
2073#define ASC_ERROR       (-1)
2074
2075#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1)
2076#ifndef ADVANSYS_STATS
2077#define ASC_STATS_ADD(shost, counter, count)
2078#else /* ADVANSYS_STATS */
2079#define ASC_STATS_ADD(shost, counter, count) \
2080        (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count))
2081#endif /* ADVANSYS_STATS */
2082
2083/* If the result wraps when calculating tenths, return 0. */
2084#define ASC_TENTHS(num, den) \
2085    (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \
2086    0 : ((((num) * 10)/(den)) - (10 * ((num)/(den)))))
2087
2088/*
2089 * Display a message to the console.
2090 */
2091#define ASC_PRINT(s) \
2092    { \
2093        printk("advansys: "); \
2094        printk(s); \
2095    }
2096
2097#define ASC_PRINT1(s, a1) \
2098    { \
2099        printk("advansys: "); \
2100        printk((s), (a1)); \
2101    }
2102
2103#define ASC_PRINT2(s, a1, a2) \
2104    { \
2105        printk("advansys: "); \
2106        printk((s), (a1), (a2)); \
2107    }
2108
2109#define ASC_PRINT3(s, a1, a2, a3) \
2110    { \
2111        printk("advansys: "); \
2112        printk((s), (a1), (a2), (a3)); \
2113    }
2114
2115#define ASC_PRINT4(s, a1, a2, a3, a4) \
2116    { \
2117        printk("advansys: "); \
2118        printk((s), (a1), (a2), (a3), (a4)); \
2119    }
2120
2121#ifndef ADVANSYS_DEBUG
2122
2123#define ASC_DBG(lvl, s...)
2124#define ASC_DBG_PRT_SCSI_HOST(lvl, s)
2125#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp)
2126#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2127#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone)
2128#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp)
2129#define ASC_DBG_PRT_HEX(lvl, name, start, length)
2130#define ASC_DBG_PRT_CDB(lvl, cdb, len)
2131#define ASC_DBG_PRT_SENSE(lvl, sense, len)
2132#define ASC_DBG_PRT_INQUIRY(lvl, inq, len)
2133
2134#else /* ADVANSYS_DEBUG */
2135
2136/*
2137 * Debugging Message Levels:
2138 * 0: Errors Only
2139 * 1: High-Level Tracing
2140 * 2-N: Verbose Tracing
2141 */
2142
2143#define ASC_DBG(lvl, format, arg...) {                                  \
2144        if (asc_dbglvl >= (lvl))                                        \
2145                printk(KERN_DEBUG "%s: %s: " format, DRV_NAME,          \
2146                        __func__ , ## arg);                             \
2147}
2148
2149#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \
2150    { \
2151        if (asc_dbglvl >= (lvl)) { \
2152            asc_prt_scsi_host(s); \
2153        } \
2154    }
2155
2156#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \
2157    { \
2158        if (asc_dbglvl >= (lvl)) { \
2159            asc_prt_asc_scsi_q(scsiqp); \
2160        } \
2161    }
2162
2163#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \
2164    { \
2165        if (asc_dbglvl >= (lvl)) { \
2166            asc_prt_asc_qdone_info(qdone); \
2167        } \
2168    }
2169
2170#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \
2171    { \
2172        if (asc_dbglvl >= (lvl)) { \
2173            asc_prt_adv_scsi_req_q(scsiqp); \
2174        } \
2175    }
2176
2177#define ASC_DBG_PRT_HEX(lvl, name, start, length) \
2178    { \
2179        if (asc_dbglvl >= (lvl)) { \
2180            asc_prt_hex((name), (start), (length)); \
2181        } \
2182    }
2183
2184#define ASC_DBG_PRT_CDB(lvl, cdb, len) \
2185        ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len));
2186
2187#define ASC_DBG_PRT_SENSE(lvl, sense, len) \
2188        ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len));
2189
2190#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \
2191        ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len));
2192#endif /* ADVANSYS_DEBUG */
2193
2194#ifdef ADVANSYS_STATS
2195
2196/* Per board statistics structure */
2197struct asc_stats {
2198        /* Driver Entrypoint Statistics */
2199        unsigned int queuecommand;      /* # calls to advansys_queuecommand() */
2200        unsigned int reset;             /* # calls to advansys_eh_bus_reset() */
2201        unsigned int biosparam; /* # calls to advansys_biosparam() */
2202        unsigned int interrupt; /* # advansys_interrupt() calls */
2203        unsigned int callback;  /* # calls to asc/adv_isr_callback() */
2204        unsigned int done;              /* # calls to request's scsi_done function */
2205        unsigned int build_error;       /* # asc/adv_build_req() ASC_ERROR returns. */
2206        unsigned int adv_build_noreq;   /* # adv_build_req() adv_req_t alloc. fail. */
2207        unsigned int adv_build_nosg;    /* # adv_build_req() adv_sgblk_t alloc. fail. */
2208        /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */
2209        unsigned int exe_noerror;       /* # ASC_NOERROR returns. */
2210        unsigned int exe_busy;  /* # ASC_BUSY returns. */
2211        unsigned int exe_error; /* # ASC_ERROR returns. */
2212        unsigned int exe_unknown;       /* # unknown returns. */
2213        /* Data Transfer Statistics */
2214        unsigned int xfer_cnt;  /* # I/O requests received */
2215        unsigned int xfer_elem; /* # scatter-gather elements */
2216        unsigned int xfer_sect; /* # 512-byte blocks */
2217};
2218#endif /* ADVANSYS_STATS */
2219
2220/*
2221 * Structure allocated for each board.
2222 *
2223 * This structure is allocated by scsi_host_alloc() at the end
2224 * of the 'Scsi_Host' structure starting at the 'hostdata'
2225 * field. It is guaranteed to be allocated from DMA-able memory.
2226 */
2227struct asc_board {
2228        struct device *dev;
2229        struct Scsi_Host *shost;
2230        uint flags;             /* Board flags */
2231        unsigned int irq;
2232        union {
2233                ASC_DVC_VAR asc_dvc_var;        /* Narrow board */
2234                ADV_DVC_VAR adv_dvc_var;        /* Wide board */
2235        } dvc_var;
2236        union {
2237                ASC_DVC_CFG asc_dvc_cfg;        /* Narrow board */
2238                ADV_DVC_CFG adv_dvc_cfg;        /* Wide board */
2239        } dvc_cfg;
2240        ushort asc_n_io_port;   /* Number I/O ports. */
2241        ADV_SCSI_BIT_ID_TYPE init_tidmask;      /* Target init./valid mask */
2242        ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */
2243        ADV_SCSI_BIT_ID_TYPE queue_full;        /* Queue full mask */
2244        ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */
2245        union {
2246                ASCEEP_CONFIG asc_eep;  /* Narrow EEPROM config. */
2247                ADVEEP_3550_CONFIG adv_3550_eep;        /* 3550 EEPROM config. */
2248                ADVEEP_38C0800_CONFIG adv_38C0800_eep;  /* 38C0800 EEPROM config. */
2249                ADVEEP_38C1600_CONFIG adv_38C1600_eep;  /* 38C1600 EEPROM config. */
2250        } eep_config;
2251        /* /proc/scsi/advansys/[0...] */
2252#ifdef ADVANSYS_STATS
2253        struct asc_stats asc_stats;     /* Board statistics */
2254#endif                          /* ADVANSYS_STATS */
2255        /*
2256         * The following fields are used only for Narrow Boards.
2257         */
2258        uchar sdtr_data[ASC_MAX_TID + 1];       /* SDTR information */
2259        /*
2260         * The following fields are used only for Wide Boards.
2261         */
2262        void __iomem *ioremap_addr;     /* I/O Memory remap address. */
2263        ushort ioport;          /* I/O Port address. */
2264        adv_req_t *adv_reqp;    /* Request structures. */
2265        dma_addr_t adv_reqp_addr;
2266        size_t adv_reqp_size;
2267        struct dma_pool *adv_sgblk_pool;        /* Scatter-gather structures. */
2268        ushort bios_signature;  /* BIOS Signature. */
2269        ushort bios_version;    /* BIOS Version. */
2270        ushort bios_codeseg;    /* BIOS Code Segment. */
2271        ushort bios_codelen;    /* BIOS Code Segment Length. */
2272};
2273
2274#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \
2275                                                        dvc_var.asc_dvc_var)
2276#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \
2277                                                        dvc_var.adv_dvc_var)
2278#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev)
2279
2280#ifdef ADVANSYS_DEBUG
2281static int asc_dbglvl = 3;
2282
2283/*
2284 * asc_prt_asc_dvc_var()
2285 */
2286static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h)
2287{
2288        printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h);
2289
2290        printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl "
2291               "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl);
2292
2293        printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type,
2294                (unsigned)h->init_sdtr);
2295
2296        printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, "
2297               "chip_no 0x%x,\n", (unsigned)h->sdtr_done,
2298               (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready,
2299               (unsigned)h->chip_no);
2300
2301        printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait "
2302               "%u,\n", (unsigned)h->queue_full_or_busy,
2303               (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2304
2305        printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, "
2306               "in_critical_cnt %u,\n", (unsigned)h->is_in_int,
2307               (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng,
2308               (unsigned)h->in_critical_cnt);
2309
2310        printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, "
2311               "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage,
2312               (unsigned)h->init_state, (unsigned)h->no_scam,
2313               (unsigned)h->pci_fix_asyn_xfer);
2314
2315        printk(" cfg 0x%lx\n", (ulong)h->cfg);
2316}
2317
2318/*
2319 * asc_prt_asc_dvc_cfg()
2320 */
2321static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h)
2322{
2323        printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h);
2324
2325        printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n",
2326               h->can_tagged_qng, h->cmd_qng_enabled);
2327        printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n",
2328               h->disc_enable, h->sdtr_enable);
2329
2330        printk(" chip_scsi_id %d, chip_version %d,\n",
2331               h->chip_scsi_id, h->chip_version);
2332
2333        printk(" mcode_date 0x%x, mcode_version %d\n",
2334                h->mcode_date, h->mcode_version);
2335}
2336
2337/*
2338 * asc_prt_adv_dvc_var()
2339 *
2340 * Display an ADV_DVC_VAR structure.
2341 */
2342static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h)
2343{
2344        printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h);
2345
2346        printk("  iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n",
2347               (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able);
2348
2349        printk("  sdtr_able 0x%x, wdtr_able 0x%x\n",
2350               (unsigned)h->sdtr_able, (unsigned)h->wdtr_able);
2351
2352        printk("  start_motor 0x%x, scsi_reset_wait 0x%x\n",
2353               (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait);
2354
2355        printk("  max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%p\n",
2356               (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng,
2357               h->carr_freelist);
2358
2359        printk("  icq_sp 0x%p, irq_sp 0x%p\n", h->icq_sp, h->irq_sp);
2360
2361        printk("  no_scam 0x%x, tagqng_able 0x%x\n",
2362               (unsigned)h->no_scam, (unsigned)h->tagqng_able);
2363
2364        printk("  chip_scsi_id 0x%x, cfg 0x%lx\n",
2365               (unsigned)h->chip_scsi_id, (ulong)h->cfg);
2366}
2367
2368/*
2369 * asc_prt_adv_dvc_cfg()
2370 *
2371 * Display an ADV_DVC_CFG structure.
2372 */
2373static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h)
2374{
2375        printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h);
2376
2377        printk("  disc_enable 0x%x, termination 0x%x\n",
2378               h->disc_enable, h->termination);
2379
2380        printk("  chip_version 0x%x, mcode_date 0x%x\n",
2381               h->chip_version, h->mcode_date);
2382
2383        printk("  mcode_version 0x%x, control_flag 0x%x\n",
2384               h->mcode_version, h->control_flag);
2385}
2386
2387/*
2388 * asc_prt_scsi_host()
2389 */
2390static void asc_prt_scsi_host(struct Scsi_Host *s)
2391{
2392        struct asc_board *boardp = shost_priv(s);
2393
2394        printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev));
2395        printk(" host_busy %d, host_no %d,\n",
2396               scsi_host_busy(s), s->host_no);
2397
2398        printk(" base 0x%lx, io_port 0x%lx, irq %d,\n",
2399               (ulong)s->base, (ulong)s->io_port, boardp->irq);
2400
2401        printk(" dma_channel %d, this_id %d, can_queue %d,\n",
2402               s->dma_channel, s->this_id, s->can_queue);
2403
2404        printk(" cmd_per_lun %d, sg_tablesize %d\n",
2405               s->cmd_per_lun, s->sg_tablesize);
2406
2407        if (ASC_NARROW_BOARD(boardp)) {
2408                asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var);
2409                asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg);
2410        } else {
2411                asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var);
2412                asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg);
2413        }
2414}
2415
2416/*
2417 * asc_prt_hex()
2418 *
2419 * Print hexadecimal output in 4 byte groupings 32 bytes
2420 * or 8 double-words per line.
2421 */
2422static void asc_prt_hex(char *f, uchar *s, int l)
2423{
2424        int i;
2425        int j;
2426        int k;
2427        int m;
2428
2429        printk("%s: (%d bytes)\n", f, l);
2430
2431        for (i = 0; i < l; i += 32) {
2432
2433                /* Display a maximum of 8 double-words per line. */
2434                if ((k = (l - i) / 4) >= 8) {
2435                        k = 8;
2436                        m = 0;
2437                } else {
2438                        m = (l - i) % 4;
2439                }
2440
2441                for (j = 0; j < k; j++) {
2442                        printk(" %2.2X%2.2X%2.2X%2.2X",
2443                               (unsigned)s[i + (j * 4)],
2444                               (unsigned)s[i + (j * 4) + 1],
2445                               (unsigned)s[i + (j * 4) + 2],
2446                               (unsigned)s[i + (j * 4) + 3]);
2447                }
2448
2449                switch (m) {
2450                case 0:
2451                default:
2452                        break;
2453                case 1:
2454                        printk(" %2.2X", (unsigned)s[i + (j * 4)]);
2455                        break;
2456                case 2:
2457                        printk(" %2.2X%2.2X",
2458                               (unsigned)s[i + (j * 4)],
2459                               (unsigned)s[i + (j * 4) + 1]);
2460                        break;
2461                case 3:
2462                        printk(" %2.2X%2.2X%2.2X",
2463                               (unsigned)s[i + (j * 4) + 1],
2464                               (unsigned)s[i + (j * 4) + 2],
2465                               (unsigned)s[i + (j * 4) + 3]);
2466                        break;
2467                }
2468
2469                printk("\n");
2470        }
2471}
2472
2473/*
2474 * asc_prt_asc_scsi_q()
2475 */
2476static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q)
2477{
2478        ASC_SG_HEAD *sgp;
2479        int i;
2480
2481        printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q);
2482
2483        printk
2484            (" target_ix 0x%x, target_lun %u, srb_tag 0x%x, tag_code 0x%x,\n",
2485             q->q2.target_ix, q->q1.target_lun, q->q2.srb_tag,
2486             q->q2.tag_code);
2487
2488        printk
2489            (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2490             (ulong)le32_to_cpu(q->q1.data_addr),
2491             (ulong)le32_to_cpu(q->q1.data_cnt),
2492             (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len);
2493
2494        printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n",
2495               (ulong)q->cdbptr, q->q2.cdb_len,
2496               (ulong)q->sg_head, q->q1.sg_queue_cnt);
2497
2498        if (q->sg_head) {
2499                sgp = q->sg_head;
2500                printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp);
2501                printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt,
2502                       sgp->queue_cnt);
2503                for (i = 0; i < sgp->entry_cnt; i++) {
2504                        printk(" [%u]: addr 0x%lx, bytes %lu\n",
2505                               i, (ulong)le32_to_cpu(sgp->sg_list[i].addr),
2506                               (ulong)le32_to_cpu(sgp->sg_list[i].bytes));
2507                }
2508
2509        }
2510}
2511
2512/*
2513 * asc_prt_asc_qdone_info()
2514 */
2515static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q)
2516{
2517        printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q);
2518        printk(" srb_tag 0x%x, target_ix %u, cdb_len %u, tag_code %u,\n",
2519               q->d2.srb_tag, q->d2.target_ix, q->d2.cdb_len,
2520               q->d2.tag_code);
2521        printk
2522            (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n",
2523             q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg);
2524}
2525
2526/*
2527 * asc_prt_adv_sgblock()
2528 *
2529 * Display an ADV_SG_BLOCK structure.
2530 */
2531static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b)
2532{
2533        int i;
2534
2535        printk(" ADV_SG_BLOCK at addr 0x%lx (sgblockno %d)\n",
2536               (ulong)b, sgblockno);
2537        printk("  sg_cnt %u, sg_ptr 0x%x\n",
2538               b->sg_cnt, (u32)le32_to_cpu(b->sg_ptr));
2539        BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK);
2540        if (b->sg_ptr != 0)
2541                BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK);
2542        for (i = 0; i < b->sg_cnt; i++) {
2543                printk("  [%u]: sg_addr 0x%x, sg_count 0x%x\n",
2544                       i, (u32)le32_to_cpu(b->sg_list[i].sg_addr),
2545                       (u32)le32_to_cpu(b->sg_list[i].sg_count));
2546        }
2547}
2548
2549/*
2550 * asc_prt_adv_scsi_req_q()
2551 *
2552 * Display an ADV_SCSI_REQ_Q structure.
2553 */
2554static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q)
2555{
2556        int sg_blk_cnt;
2557        struct adv_sg_block *sg_ptr;
2558        adv_sgblk_t *sgblkp;
2559
2560        printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q);
2561
2562        printk("  target_id %u, target_lun %u, srb_tag 0x%x\n",
2563               q->target_id, q->target_lun, q->srb_tag);
2564
2565        printk("  cntl 0x%x, data_addr 0x%lx\n",
2566               q->cntl, (ulong)le32_to_cpu(q->data_addr));
2567
2568        printk("  data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n",
2569               (ulong)le32_to_cpu(q->data_cnt),
2570               (ulong)le32_to_cpu(q->sense_addr), q->sense_len);
2571
2572        printk
2573            ("  cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n",
2574             q->cdb_len, q->done_status, q->host_status, q->scsi_status);
2575
2576        printk("  sg_working_ix 0x%x, target_cmd %u\n",
2577               q->sg_working_ix, q->target_cmd);
2578
2579        printk("  scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n",
2580               (ulong)le32_to_cpu(q->scsiq_rptr),
2581               (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr);
2582
2583        /* Display the request's ADV_SG_BLOCK structures. */
2584        if (q->sg_list_ptr != NULL) {
2585                sgblkp = container_of(q->sg_list_ptr, adv_sgblk_t, sg_block);
2586                sg_blk_cnt = 0;
2587                while (sgblkp) {
2588                        sg_ptr = &sgblkp->sg_block;
2589                        asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr);
2590                        if (sg_ptr->sg_ptr == 0) {
2591                                break;
2592                        }
2593                        sgblkp = sgblkp->next_sgblkp;
2594                        sg_blk_cnt++;
2595                }
2596        }
2597}
2598#endif /* ADVANSYS_DEBUG */
2599
2600/*
2601 * advansys_info()
2602 *
2603 * Return suitable for printing on the console with the argument
2604 * adapter's configuration information.
2605 *
2606 * Note: The information line should not exceed ASC_INFO_SIZE bytes,
2607 * otherwise the static 'info' array will be overrun.
2608 */
2609static const char *advansys_info(struct Scsi_Host *shost)
2610{
2611        static char info[ASC_INFO_SIZE];
2612        struct asc_board *boardp = shost_priv(shost);
2613        ASC_DVC_VAR *asc_dvc_varp;
2614        ADV_DVC_VAR *adv_dvc_varp;
2615        char *busname;
2616        char *widename = NULL;
2617
2618        if (ASC_NARROW_BOARD(boardp)) {
2619                asc_dvc_varp = &boardp->dvc_var.asc_dvc_var;
2620                ASC_DBG(1, "begin\n");
2621
2622                if (asc_dvc_varp->bus_type & ASC_IS_VL) {
2623                        busname = "VL";
2624                } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) {
2625                        busname = "EISA";
2626                } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) {
2627                        if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA)
2628                            == ASC_IS_PCI_ULTRA) {
2629                                busname = "PCI Ultra";
2630                        } else {
2631                                busname = "PCI";
2632                        }
2633                } else {
2634                        busname = "?";
2635                        shost_printk(KERN_ERR, shost, "unknown bus "
2636                                "type %d\n", asc_dvc_varp->bus_type);
2637                }
2638                sprintf(info,
2639                        "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X",
2640                        ASC_VERSION, busname, (ulong)shost->io_port,
2641                        (ulong)shost->io_port + ASC_IOADR_GAP - 1,
2642                        boardp->irq);
2643        } else {
2644                /*
2645                 * Wide Adapter Information
2646                 *
2647                 * Memory-mapped I/O is used instead of I/O space to access
2648                 * the adapter, but display the I/O Port range. The Memory
2649                 * I/O address is displayed through the driver /proc file.
2650                 */
2651                adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2652                if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2653                        widename = "Ultra-Wide";
2654                } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2655                        widename = "Ultra2-Wide";
2656                } else {
2657                        widename = "Ultra3-Wide";
2658                }
2659                sprintf(info,
2660                        "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X",
2661                        ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base,
2662                        (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq);
2663        }
2664        BUG_ON(strlen(info) >= ASC_INFO_SIZE);
2665        ASC_DBG(1, "end\n");
2666        return info;
2667}
2668
2669#ifdef CONFIG_PROC_FS
2670
2671/*
2672 * asc_prt_board_devices()
2673 *
2674 * Print driver information for devices attached to the board.
2675 */
2676static void asc_prt_board_devices(struct seq_file *m, struct Scsi_Host *shost)
2677{
2678        struct asc_board *boardp = shost_priv(shost);
2679        int chip_scsi_id;
2680        int i;
2681
2682        seq_printf(m,
2683                   "\nDevice Information for AdvanSys SCSI Host %d:\n",
2684                   shost->host_no);
2685
2686        if (ASC_NARROW_BOARD(boardp)) {
2687                chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id;
2688        } else {
2689                chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id;
2690        }
2691
2692        seq_puts(m, "Target IDs Detected:");
2693        for (i = 0; i <= ADV_MAX_TID; i++) {
2694                if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i))
2695                        seq_printf(m, " %X,", i);
2696        }
2697        seq_printf(m, " (%X=Host Adapter)\n", chip_scsi_id);
2698}
2699
2700/*
2701 * Display Wide Board BIOS Information.
2702 */
2703static void asc_prt_adv_bios(struct seq_file *m, struct Scsi_Host *shost)
2704{
2705        struct asc_board *boardp = shost_priv(shost);
2706        ushort major, minor, letter;
2707
2708        seq_puts(m, "\nROM BIOS Version: ");
2709
2710        /*
2711         * If the BIOS saved a valid signature, then fill in
2712         * the BIOS code segment base address.
2713         */
2714        if (boardp->bios_signature != 0x55AA) {
2715                seq_puts(m, "Disabled or Pre-3.1\n"
2716                        "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"
2717                        "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n");
2718        } else {
2719                major = (boardp->bios_version >> 12) & 0xF;
2720                minor = (boardp->bios_version >> 8) & 0xF;
2721                letter = (boardp->bios_version & 0xFF);
2722
2723                seq_printf(m, "%d.%d%c\n",
2724                                   major, minor,
2725                                   letter >= 26 ? '?' : letter + 'A');
2726                /*
2727                 * Current available ROM BIOS release is 3.1I for UW
2728                 * and 3.2I for U2W. This code doesn't differentiate
2729                 * UW and U2W boards.
2730                 */
2731                if (major < 3 || (major <= 3 && minor < 1) ||
2732                    (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) {
2733                        seq_puts(m, "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"
2734                                "ftp://ftp.connectcom.net/pub\n");
2735                }
2736        }
2737}
2738
2739/*
2740 * Add serial number to information bar if signature AAh
2741 * is found in at bit 15-9 (7 bits) of word 1.
2742 *
2743 * Serial Number consists fo 12 alpha-numeric digits.
2744 *
2745 *       1 - Product type (A,B,C,D..)  Word0: 15-13 (3 bits)
2746 *       2 - MFG Location (A,B,C,D..)  Word0: 12-10 (3 bits)
2747 *     3-4 - Product ID (0-99)         Word0: 9-0 (10 bits)
2748 *       5 - Product revision (A-J)    Word0:  "         "
2749 *
2750 *           Signature                 Word1: 15-9 (7 bits)
2751 *       6 - Year (0-9)                Word1: 8-6 (3 bits) & Word2: 15 (1 bit)
2752 *     7-8 - Week of the year (1-52)   Word1: 5-0 (6 bits)
2753 *
2754 *    9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits)
2755 *
2756 * Note 1: Only production cards will have a serial number.
2757 *
2758 * Note 2: Signature is most significant 7 bits (0xFE).
2759 *
2760 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE.
2761 */
2762static int asc_get_eeprom_string(ushort *serialnum, uchar *cp)
2763{
2764        ushort w, num;
2765
2766        if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) {
2767                return ASC_FALSE;
2768        } else {
2769                /*
2770                 * First word - 6 digits.
2771                 */
2772                w = serialnum[0];
2773
2774                /* Product type - 1st digit. */
2775                if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') {
2776                        /* Product type is P=Prototype */
2777                        *cp += 0x8;
2778                }
2779                cp++;
2780
2781                /* Manufacturing location - 2nd digit. */
2782                *cp++ = 'A' + ((w & 0x1C00) >> 10);
2783
2784                /* Product ID - 3rd, 4th digits. */
2785                num = w & 0x3FF;
2786                *cp++ = '0' + (num / 100);
2787                num %= 100;
2788                *cp++ = '0' + (num / 10);
2789
2790                /* Product revision - 5th digit. */
2791                *cp++ = 'A' + (num % 10);
2792
2793                /*
2794                 * Second word
2795                 */
2796                w = serialnum[1];
2797
2798                /*
2799                 * Year - 6th digit.
2800                 *
2801                 * If bit 15 of third word is set, then the
2802                 * last digit of the year is greater than 7.
2803                 */
2804                if (serialnum[2] & 0x8000) {
2805                        *cp++ = '8' + ((w & 0x1C0) >> 6);
2806                } else {
2807                        *cp++ = '0' + ((w & 0x1C0) >> 6);
2808                }
2809
2810                /* Week of year - 7th, 8th digits. */
2811                num = w & 0x003F;
2812                *cp++ = '0' + num / 10;
2813                num %= 10;
2814                *cp++ = '0' + num;
2815
2816                /*
2817                 * Third word
2818                 */
2819                w = serialnum[2] & 0x7FFF;
2820
2821                /* Serial number - 9th digit. */
2822                *cp++ = 'A' + (w / 1000);
2823
2824                /* 10th, 11th, 12th digits. */
2825                num = w % 1000;
2826                *cp++ = '0' + num / 100;
2827                num %= 100;
2828                *cp++ = '0' + num / 10;
2829                num %= 10;
2830                *cp++ = '0' + num;
2831
2832                *cp = '\0';     /* Null Terminate the string. */
2833                return ASC_TRUE;
2834        }
2835}
2836
2837/*
2838 * asc_prt_asc_board_eeprom()
2839 *
2840 * Print board EEPROM configuration.
2841 */
2842static void asc_prt_asc_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2843{
2844        struct asc_board *boardp = shost_priv(shost);
2845        ASCEEP_CONFIG *ep;
2846        int i;
2847        uchar serialstr[13];
2848
2849        ep = &boardp->eep_config.asc_eep;
2850
2851        seq_printf(m,
2852                   "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2853                   shost->host_no);
2854
2855        if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr)
2856            == ASC_TRUE)
2857                seq_printf(m, " Serial Number: %s\n", serialstr);
2858        else if (ep->adapter_info[5] == 0xBB)
2859                seq_puts(m,
2860                         " Default Settings Used for EEPROM-less Adapter.\n");
2861        else
2862                seq_puts(m, " Serial Number Signature Not Present.\n");
2863
2864        seq_printf(m,
2865                   " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2866                   ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng,
2867                   ep->max_tag_qng);
2868
2869        seq_printf(m,
2870                   " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam);
2871
2872        seq_puts(m, " Target ID:           ");
2873        for (i = 0; i <= ASC_MAX_TID; i++)
2874                seq_printf(m, " %d", i);
2875
2876        seq_puts(m, "\n Disconnects:         ");
2877        for (i = 0; i <= ASC_MAX_TID; i++)
2878                seq_printf(m, " %c",
2879                           (ep->disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2880
2881        seq_puts(m, "\n Command Queuing:     ");
2882        for (i = 0; i <= ASC_MAX_TID; i++)
2883                seq_printf(m, " %c",
2884                           (ep->use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2885
2886        seq_puts(m, "\n Start Motor:         ");
2887        for (i = 0; i <= ASC_MAX_TID; i++)
2888                seq_printf(m, " %c",
2889                           (ep->start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2890
2891        seq_puts(m, "\n Synchronous Transfer:");
2892        for (i = 0; i <= ASC_MAX_TID; i++)
2893                seq_printf(m, " %c",
2894                           (ep->init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
2895        seq_putc(m, '\n');
2896}
2897
2898/*
2899 * asc_prt_adv_board_eeprom()
2900 *
2901 * Print board EEPROM configuration.
2902 */
2903static void asc_prt_adv_board_eeprom(struct seq_file *m, struct Scsi_Host *shost)
2904{
2905        struct asc_board *boardp = shost_priv(shost);
2906        ADV_DVC_VAR *adv_dvc_varp;
2907        int i;
2908        char *termstr;
2909        uchar serialstr[13];
2910        ADVEEP_3550_CONFIG *ep_3550 = NULL;
2911        ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL;
2912        ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL;
2913        ushort word;
2914        ushort *wordp;
2915        ushort sdtr_speed = 0;
2916
2917        adv_dvc_varp = &boardp->dvc_var.adv_dvc_var;
2918        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2919                ep_3550 = &boardp->eep_config.adv_3550_eep;
2920        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2921                ep_38C0800 = &boardp->eep_config.adv_38C0800_eep;
2922        } else {
2923                ep_38C1600 = &boardp->eep_config.adv_38C1600_eep;
2924        }
2925
2926        seq_printf(m,
2927                   "\nEEPROM Settings for AdvanSys SCSI Host %d:\n",
2928                   shost->host_no);
2929
2930        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2931                wordp = &ep_3550->serial_number_word1;
2932        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2933                wordp = &ep_38C0800->serial_number_word1;
2934        } else {
2935                wordp = &ep_38C1600->serial_number_word1;
2936        }
2937
2938        if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE)
2939                seq_printf(m, " Serial Number: %s\n", serialstr);
2940        else
2941                seq_puts(m, " Serial Number Signature Not Present.\n");
2942
2943        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
2944                seq_printf(m,
2945                           " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2946                           ep_3550->adapter_scsi_id,
2947                           ep_3550->max_host_qng, ep_3550->max_dvc_qng);
2948        else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
2949                seq_printf(m,
2950                           " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2951                           ep_38C0800->adapter_scsi_id,
2952                           ep_38C0800->max_host_qng,
2953                           ep_38C0800->max_dvc_qng);
2954        else
2955                seq_printf(m,
2956                           " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n",
2957                           ep_38C1600->adapter_scsi_id,
2958                           ep_38C1600->max_host_qng,
2959                           ep_38C1600->max_dvc_qng);
2960        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
2961                word = ep_3550->termination;
2962        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
2963                word = ep_38C0800->termination_lvd;
2964        } else {
2965                word = ep_38C1600->termination_lvd;
2966        }
2967        switch (word) {
2968        case 1:
2969                termstr = "Low Off/High Off";
2970                break;
2971        case 2:
2972                termstr = "Low Off/High On";
2973                break;
2974        case 3:
2975                termstr = "Low On/High On";
2976                break;
2977        default:
2978        case 0:
2979                termstr = "Automatic";
2980                break;
2981        }
2982
2983        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550)
2984                seq_printf(m,
2985                           " termination: %u (%s), bios_ctrl: 0x%x\n",
2986                           ep_3550->termination, termstr,
2987                           ep_3550->bios_ctrl);
2988        else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800)
2989                seq_printf(m,
2990                           " termination: %u (%s), bios_ctrl: 0x%x\n",
2991                           ep_38C0800->termination_lvd, termstr,
2992                           ep_38C0800->bios_ctrl);
2993        else
2994                seq_printf(m,
2995                           " termination: %u (%s), bios_ctrl: 0x%x\n",
2996                           ep_38C1600->termination_lvd, termstr,
2997                           ep_38C1600->bios_ctrl);
2998
2999        seq_puts(m, " Target ID:           ");
3000        for (i = 0; i <= ADV_MAX_TID; i++)
3001                seq_printf(m, " %X", i);
3002        seq_putc(m, '\n');
3003
3004        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3005                word = ep_3550->disc_enable;
3006        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3007                word = ep_38C0800->disc_enable;
3008        } else {
3009                word = ep_38C1600->disc_enable;
3010        }
3011        seq_puts(m, " Disconnects:         ");
3012        for (i = 0; i <= ADV_MAX_TID; i++)
3013                seq_printf(m, " %c",
3014                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3015        seq_putc(m, '\n');
3016
3017        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3018                word = ep_3550->tagqng_able;
3019        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3020                word = ep_38C0800->tagqng_able;
3021        } else {
3022                word = ep_38C1600->tagqng_able;
3023        }
3024        seq_puts(m, " Command Queuing:     ");
3025        for (i = 0; i <= ADV_MAX_TID; i++)
3026                seq_printf(m, " %c",
3027                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3028        seq_putc(m, '\n');
3029
3030        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3031                word = ep_3550->start_motor;
3032        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3033                word = ep_38C0800->start_motor;
3034        } else {
3035                word = ep_38C1600->start_motor;
3036        }
3037        seq_puts(m, " Start Motor:         ");
3038        for (i = 0; i <= ADV_MAX_TID; i++)
3039                seq_printf(m, " %c",
3040                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3041        seq_putc(m, '\n');
3042
3043        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3044                seq_puts(m, " Synchronous Transfer:");
3045                for (i = 0; i <= ADV_MAX_TID; i++)
3046                        seq_printf(m, " %c",
3047                                   (ep_3550->sdtr_able & ADV_TID_TO_TIDMASK(i)) ?
3048                                   'Y' : 'N');
3049                seq_putc(m, '\n');
3050        }
3051
3052        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3053                seq_puts(m, " Ultra Transfer:      ");
3054                for (i = 0; i <= ADV_MAX_TID; i++)
3055                        seq_printf(m, " %c",
3056                                   (ep_3550->ultra_able & ADV_TID_TO_TIDMASK(i))
3057                                   ? 'Y' : 'N');
3058                seq_putc(m, '\n');
3059        }
3060
3061        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) {
3062                word = ep_3550->wdtr_able;
3063        } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) {
3064                word = ep_38C0800->wdtr_able;
3065        } else {
3066                word = ep_38C1600->wdtr_able;
3067        }
3068        seq_puts(m, " Wide Transfer:       ");
3069        for (i = 0; i <= ADV_MAX_TID; i++)
3070                seq_printf(m, " %c",
3071                           (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3072        seq_putc(m, '\n');
3073
3074        if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 ||
3075            adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) {
3076                seq_puts(m, " Synchronous Transfer Speed (Mhz):\n  ");
3077                for (i = 0; i <= ADV_MAX_TID; i++) {
3078                        char *speed_str;
3079
3080                        if (i == 0) {
3081                                sdtr_speed = adv_dvc_varp->sdtr_speed1;
3082                        } else if (i == 4) {
3083                                sdtr_speed = adv_dvc_varp->sdtr_speed2;
3084                        } else if (i == 8) {
3085                                sdtr_speed = adv_dvc_varp->sdtr_speed3;
3086                        } else if (i == 12) {
3087                                sdtr_speed = adv_dvc_varp->sdtr_speed4;
3088                        }
3089                        switch (sdtr_speed & ADV_MAX_TID) {
3090                        case 0:
3091                                speed_str = "Off";
3092                                break;
3093                        case 1:
3094                                speed_str = "  5";
3095                                break;
3096                        case 2:
3097                                speed_str = " 10";
3098                                break;
3099                        case 3:
3100                                speed_str = " 20";
3101                                break;
3102                        case 4:
3103                                speed_str = " 40";
3104                                break;
3105                        case 5:
3106                                speed_str = " 80";
3107                                break;
3108                        default:
3109                                speed_str = "Unk";
3110                                break;
3111                        }
3112                        seq_printf(m, "%X:%s ", i, speed_str);
3113                        if (i == 7)
3114                                seq_puts(m, "\n  ");
3115                        sdtr_speed >>= 4;
3116                }
3117                seq_putc(m, '\n');
3118        }
3119}
3120
3121/*
3122 * asc_prt_driver_conf()
3123 */
3124static void asc_prt_driver_conf(struct seq_file *m, struct Scsi_Host *shost)
3125{
3126        struct asc_board *boardp = shost_priv(shost);
3127
3128        seq_printf(m,
3129                "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n",
3130                shost->host_no);
3131
3132        seq_printf(m,
3133                   " host_busy %d, max_id %u, max_lun %llu, max_channel %u\n",
3134                   scsi_host_busy(shost), shost->max_id,
3135                   shost->max_lun, shost->max_channel);
3136
3137        seq_printf(m,
3138                   " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n",
3139                   shost->unique_id, shost->can_queue, shost->this_id,
3140                   shost->sg_tablesize, shost->cmd_per_lun);
3141
3142        seq_printf(m,
3143                   " flags 0x%x, last_reset 0x%lx, jiffies 0x%lx, asc_n_io_port 0x%x\n",
3144                   boardp->flags, shost->last_reset, jiffies,
3145                   boardp->asc_n_io_port);
3146
3147        seq_printf(m, " io_port 0x%lx\n", shost->io_port);
3148}
3149
3150/*
3151 * asc_prt_asc_board_info()
3152 *
3153 * Print dynamic board configuration information.
3154 */
3155static void asc_prt_asc_board_info(struct seq_file *m, struct Scsi_Host *shost)
3156{
3157        struct asc_board *boardp = shost_priv(shost);
3158        int chip_scsi_id;
3159        ASC_DVC_VAR *v;
3160        ASC_DVC_CFG *c;
3161        int i;
3162        int renegotiate = 0;
3163
3164        v = &boardp->dvc_var.asc_dvc_var;
3165        c = &boardp->dvc_cfg.asc_dvc_cfg;
3166        chip_scsi_id = c->chip_scsi_id;
3167
3168        seq_printf(m,
3169                   "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3170                   shost->host_no);
3171
3172        seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3173                   "mcode_version 0x%x, err_code %u\n",
3174                   c->chip_version, c->mcode_date, c->mcode_version,
3175                   v->err_code);
3176
3177        /* Current number of commands waiting for the host. */
3178        seq_printf(m,
3179                   " Total Command Pending: %d\n", v->cur_total_qng);
3180
3181        seq_puts(m, " Command Queuing:");
3182        for (i = 0; i <= ASC_MAX_TID; i++) {
3183                if ((chip_scsi_id == i) ||
3184                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3185                        continue;
3186                }
3187                seq_printf(m, " %X:%c",
3188                           i,
3189                           (v->use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3190        }
3191
3192        /* Current number of commands waiting for a device. */
3193        seq_puts(m, "\n Command Queue Pending:");
3194        for (i = 0; i <= ASC_MAX_TID; i++) {
3195                if ((chip_scsi_id == i) ||
3196                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3197                        continue;
3198                }
3199                seq_printf(m, " %X:%u", i, v->cur_dvc_qng[i]);
3200        }
3201
3202        /* Current limit on number of commands that can be sent to a device. */
3203        seq_puts(m, "\n Command Queue Limit:");
3204        for (i = 0; i <= ASC_MAX_TID; i++) {
3205                if ((chip_scsi_id == i) ||
3206                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3207                        continue;
3208                }
3209                seq_printf(m, " %X:%u", i, v->max_dvc_qng[i]);
3210        }
3211
3212        /* Indicate whether the device has returned queue full status. */
3213        seq_puts(m, "\n Command Queue Full:");
3214        for (i = 0; i <= ASC_MAX_TID; i++) {
3215                if ((chip_scsi_id == i) ||
3216                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3217                        continue;
3218                }
3219                if (boardp->queue_full & ADV_TID_TO_TIDMASK(i))
3220                        seq_printf(m, " %X:Y-%d",
3221                                   i, boardp->queue_full_cnt[i]);
3222                else
3223                        seq_printf(m, " %X:N", i);
3224        }
3225
3226        seq_puts(m, "\n Synchronous Transfer:");
3227        for (i = 0; i <= ASC_MAX_TID; i++) {
3228                if ((chip_scsi_id == i) ||
3229                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3230                        continue;
3231                }
3232                seq_printf(m, " %X:%c",
3233                           i,
3234                           (v->sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3235        }
3236        seq_putc(m, '\n');
3237
3238        for (i = 0; i <= ASC_MAX_TID; i++) {
3239                uchar syn_period_ix;
3240
3241                if ((chip_scsi_id == i) ||
3242                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3243                    ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) {
3244                        continue;
3245                }
3246
3247                seq_printf(m, "  %X:", i);
3248
3249                if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) {
3250                        seq_puts(m, " Asynchronous");
3251                } else {
3252                        syn_period_ix =
3253                            (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index -
3254                                                           1);
3255
3256                        seq_printf(m,
3257                                   " Transfer Period Factor: %d (%d.%d Mhz),",
3258                                   v->sdtr_period_tbl[syn_period_ix],
3259                                   250 / v->sdtr_period_tbl[syn_period_ix],
3260                                   ASC_TENTHS(250,
3261                                              v->sdtr_period_tbl[syn_period_ix]));
3262
3263                        seq_printf(m, " REQ/ACK Offset: %d",
3264                                   boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET);
3265                }
3266
3267                if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3268                        seq_puts(m, "*\n");
3269                        renegotiate = 1;
3270                } else {
3271                        seq_putc(m, '\n');
3272                }
3273        }
3274
3275        if (renegotiate) {
3276                seq_puts(m, " * = Re-negotiation pending before next command.\n");
3277        }
3278}
3279
3280/*
3281 * asc_prt_adv_board_info()
3282 *
3283 * Print dynamic board configuration information.
3284 */
3285static void asc_prt_adv_board_info(struct seq_file *m, struct Scsi_Host *shost)
3286{
3287        struct asc_board *boardp = shost_priv(shost);
3288        int i;
3289        ADV_DVC_VAR *v;
3290        ADV_DVC_CFG *c;
3291        AdvPortAddr iop_base;
3292        ushort chip_scsi_id;
3293        ushort lramword;
3294        uchar lrambyte;
3295        ushort tagqng_able;
3296        ushort sdtr_able, wdtr_able;
3297        ushort wdtr_done, sdtr_done;
3298        ushort period = 0;
3299        int renegotiate = 0;
3300
3301        v = &boardp->dvc_var.adv_dvc_var;
3302        c = &boardp->dvc_cfg.adv_dvc_cfg;
3303        iop_base = v->iop_base;
3304        chip_scsi_id = v->chip_scsi_id;
3305
3306        seq_printf(m,
3307                   "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n",
3308                   shost->host_no);
3309
3310        seq_printf(m,
3311                   " iop_base 0x%lx, cable_detect: %X, err_code %u\n",
3312                   (unsigned long)v->iop_base,
3313                   AdvReadWordRegister(iop_base,IOPW_SCSI_CFG1) & CABLE_DETECT,
3314                   v->err_code);
3315
3316        seq_printf(m, " chip_version %u, mcode_date 0x%x, "
3317                   "mcode_version 0x%x\n", c->chip_version,
3318                   c->mcode_date, c->mcode_version);
3319
3320        AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able);
3321        seq_puts(m, " Queuing Enabled:");
3322        for (i = 0; i <= ADV_MAX_TID; i++) {
3323                if ((chip_scsi_id == i) ||
3324                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3325                        continue;
3326                }
3327
3328                seq_printf(m, " %X:%c",
3329                           i,
3330                           (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3331        }
3332
3333        seq_puts(m, "\n Queue Limit:");
3334        for (i = 0; i <= ADV_MAX_TID; i++) {
3335                if ((chip_scsi_id == i) ||
3336                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3337                        continue;
3338                }
3339
3340                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i,
3341                                lrambyte);
3342
3343                seq_printf(m, " %X:%d", i, lrambyte);
3344        }
3345
3346        seq_puts(m, "\n Command Pending:");
3347        for (i = 0; i <= ADV_MAX_TID; i++) {
3348                if ((chip_scsi_id == i) ||
3349                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3350                        continue;
3351                }
3352
3353                AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i,
3354                                lrambyte);
3355
3356                seq_printf(m, " %X:%d", i, lrambyte);
3357        }
3358        seq_putc(m, '\n');
3359
3360        AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able);
3361        seq_puts(m, " Wide Enabled:");
3362        for (i = 0; i <= ADV_MAX_TID; i++) {
3363                if ((chip_scsi_id == i) ||
3364                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3365                        continue;
3366                }
3367
3368                seq_printf(m, " %X:%c",
3369                           i,
3370                           (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3371        }
3372        seq_putc(m, '\n');
3373
3374        AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done);
3375        seq_puts(m, " Transfer Bit Width:");
3376        for (i = 0; i <= ADV_MAX_TID; i++) {
3377                if ((chip_scsi_id == i) ||
3378                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3379                        continue;
3380                }
3381
3382                AdvReadWordLram(iop_base,
3383                                ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3384                                lramword);
3385
3386                seq_printf(m, " %X:%d",
3387                           i, (lramword & 0x8000) ? 16 : 8);
3388
3389                if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) &&
3390                    (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3391                        seq_putc(m, '*');
3392                        renegotiate = 1;
3393                }
3394        }
3395        seq_putc(m, '\n');
3396
3397        AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able);
3398        seq_puts(m, " Synchronous Enabled:");
3399        for (i = 0; i <= ADV_MAX_TID; i++) {
3400                if ((chip_scsi_id == i) ||
3401                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) {
3402                        continue;
3403                }
3404
3405                seq_printf(m, " %X:%c",
3406                           i,
3407                           (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N');
3408        }
3409        seq_putc(m, '\n');
3410
3411        AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done);
3412        for (i = 0; i <= ADV_MAX_TID; i++) {
3413
3414                AdvReadWordLram(iop_base,
3415                                ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i),
3416                                lramword);
3417                lramword &= ~0x8000;
3418
3419                if ((chip_scsi_id == i) ||
3420                    ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) ||
3421                    ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) {
3422                        continue;
3423                }
3424
3425                seq_printf(m, "  %X:", i);
3426
3427                if ((lramword & 0x1F) == 0) {   /* Check for REQ/ACK Offset 0. */
3428                        seq_puts(m, " Asynchronous");
3429                } else {
3430                        seq_puts(m, " Transfer Period Factor: ");
3431
3432                        if ((lramword & 0x1F00) == 0x1100) {    /* 80 Mhz */
3433                                seq_puts(m, "9 (80.0 Mhz),");
3434                        } else if ((lramword & 0x1F00) == 0x1000) {     /* 40 Mhz */
3435                                seq_puts(m, "10 (40.0 Mhz),");
3436                        } else {        /* 20 Mhz or below. */
3437
3438                                period = (((lramword >> 8) * 25) + 50) / 4;
3439
3440                                if (period == 0) {      /* Should never happen. */
3441                                        seq_printf(m, "%d (? Mhz), ", period);
3442                                } else {
3443                                        seq_printf(m,
3444                                                   "%d (%d.%d Mhz),",
3445                                                   period, 250 / period,
3446                                                   ASC_TENTHS(250, period));
3447                                }
3448                        }
3449
3450                        seq_printf(m, " REQ/ACK Offset: %d",
3451                                   lramword & 0x1F);
3452                }
3453
3454                if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) {
3455                        seq_puts(m, "*\n");
3456                        renegotiate = 1;
3457                } else {
3458                        seq_putc(m, '\n');
3459                }
3460        }
3461
3462        if (renegotiate) {
3463                seq_puts(m, " * = Re-negotiation pending before next command.\n");
3464        }
3465}
3466
3467#ifdef ADVANSYS_STATS
3468/*
3469 * asc_prt_board_stats()
3470 */
3471static void asc_prt_board_stats(struct seq_file *m, struct Scsi_Host *shost)
3472{
3473        struct asc_board *boardp = shost_priv(shost);
3474        struct asc_stats *s = &boardp->asc_stats;
3475
3476        seq_printf(m,
3477                   "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n",
3478                   shost->host_no);
3479
3480        seq_printf(m,
3481                   " queuecommand %u, reset %u, biosparam %u, interrupt %u\n",
3482                   s->queuecommand, s->reset, s->biosparam,
3483                   s->interrupt);
3484
3485        seq_printf(m,
3486                   " callback %u, done %u, build_error %u, build_noreq %u, build_nosg %u\n",
3487                   s->callback, s->done, s->build_error,
3488                   s->adv_build_noreq, s->adv_build_nosg);
3489
3490        seq_printf(m,
3491                   " exe_noerror %u, exe_busy %u, exe_error %u, exe_unknown %u\n",
3492                   s->exe_noerror, s->exe_busy, s->exe_error,
3493                   s->exe_unknown);
3494
3495        /*
3496         * Display data transfer statistics.
3497         */
3498        if (s->xfer_cnt > 0) {
3499                seq_printf(m, " xfer_cnt %u, xfer_elem %u, ",
3500                           s->xfer_cnt, s->xfer_elem);
3501
3502                seq_printf(m, "xfer_bytes %u.%01u kb\n",
3503                           s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2));
3504
3505                /* Scatter gather transfer statistics */
3506                seq_printf(m, " avg_num_elem %u.%01u, ",
3507                           s->xfer_elem / s->xfer_cnt,
3508                           ASC_TENTHS(s->xfer_elem, s->xfer_cnt));
3509
3510                seq_printf(m, "avg_elem_size %u.%01u kb, ",
3511                           (s->xfer_sect / 2) / s->xfer_elem,
3512                           ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem));
3513
3514                seq_printf(m, "avg_xfer_size %u.%01u kb\n",
3515                           (s->xfer_sect / 2) / s->xfer_cnt,
3516                           ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt));
3517        }
3518}
3519#endif /* ADVANSYS_STATS */
3520
3521/*
3522 * advansys_show_info() - /proc/scsi/advansys/{0,1,2,3,...}
3523 *
3524 * m: seq_file to print into
3525 * shost: Scsi_Host
3526 *
3527 * Return the number of bytes read from or written to a
3528 * /proc/scsi/advansys/[0...] file.
3529 */
3530static int
3531advansys_show_info(struct seq_file *m, struct Scsi_Host *shost)
3532{
3533        struct asc_board *boardp = shost_priv(shost);
3534
3535        ASC_DBG(1, "begin\n");
3536
3537        /*
3538         * User read of /proc/scsi/advansys/[0...] file.
3539         */
3540
3541        /*
3542         * Get board configuration information.
3543         *
3544         * advansys_info() returns the board string from its own static buffer.
3545         */
3546        /* Copy board information. */
3547        seq_printf(m, "%s\n", (char *)advansys_info(shost));
3548        /*
3549         * Display Wide Board BIOS Information.
3550         */
3551        if (!ASC_NARROW_BOARD(boardp))
3552                asc_prt_adv_bios(m, shost);
3553
3554        /*
3555         * Display driver information for each device attached to the board.
3556         */
3557        asc_prt_board_devices(m, shost);
3558
3559        /*
3560         * Display EEPROM configuration for the board.
3561         */
3562        if (ASC_NARROW_BOARD(boardp))
3563                asc_prt_asc_board_eeprom(m, shost);
3564        else
3565                asc_prt_adv_board_eeprom(m, shost);
3566
3567        /*
3568         * Display driver configuration and information for the board.
3569         */
3570        asc_prt_driver_conf(m, shost);
3571
3572#ifdef ADVANSYS_STATS
3573        /*
3574         * Display driver statistics for the board.
3575         */
3576        asc_prt_board_stats(m, shost);
3577#endif /* ADVANSYS_STATS */
3578
3579        /*
3580         * Display Asc Library dynamic configuration information
3581         * for the board.
3582         */
3583        if (ASC_NARROW_BOARD(boardp))
3584                asc_prt_asc_board_info(m, shost);
3585        else
3586                asc_prt_adv_board_info(m, shost);
3587        return 0;
3588}
3589#endif /* CONFIG_PROC_FS */
3590
3591static void asc_scsi_done(struct scsi_cmnd *scp)
3592{
3593        scsi_dma_unmap(scp);
3594        ASC_STATS(scp->device->host, done);
3595        scp->scsi_done(scp);
3596}
3597
3598static void AscSetBank(PortAddr iop_base, uchar bank)
3599{
3600        uchar val;
3601
3602        val = AscGetChipControl(iop_base) &
3603            (~
3604             (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET |
3605              CC_CHIP_RESET));
3606        if (bank == 1) {
3607                val |= CC_BANK_ONE;
3608        } else if (bank == 2) {
3609                val |= CC_DIAG | CC_BANK_ONE;
3610        } else {
3611                val &= ~CC_BANK_ONE;
3612        }
3613        AscSetChipControl(iop_base, val);
3614}
3615
3616static void AscSetChipIH(PortAddr iop_base, ushort ins_code)
3617{
3618        AscSetBank(iop_base, 1);
3619        AscWriteChipIH(iop_base, ins_code);
3620        AscSetBank(iop_base, 0);
3621}
3622
3623static int AscStartChip(PortAddr iop_base)
3624{
3625        AscSetChipControl(iop_base, 0);
3626        if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3627                return (0);
3628        }
3629        return (1);
3630}
3631
3632static bool AscStopChip(PortAddr iop_base)
3633{
3634        uchar cc_val;
3635
3636        cc_val =
3637            AscGetChipControl(iop_base) &
3638            (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG));
3639        AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT));
3640        AscSetChipIH(iop_base, INS_HALT);
3641        AscSetChipIH(iop_base, INS_RFLAG_WTM);
3642        if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) {
3643                return false;
3644        }
3645        return true;
3646}
3647
3648static bool AscIsChipHalted(PortAddr iop_base)
3649{
3650        if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) {
3651                if ((AscGetChipControl(iop_base) & CC_HALT) != 0) {
3652                        return true;
3653                }
3654        }
3655        return false;
3656}
3657
3658static bool AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc)
3659{
3660        PortAddr iop_base;
3661        int i = 10;
3662
3663        iop_base = asc_dvc->iop_base;
3664        while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE)
3665               && (i-- > 0)) {
3666                mdelay(100);
3667        }
3668        AscStopChip(iop_base);
3669        AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT);
3670        udelay(60);
3671        AscSetChipIH(iop_base, INS_RFLAG_WTM);
3672        AscSetChipIH(iop_base, INS_HALT);
3673        AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT);
3674        AscSetChipControl(iop_base, CC_HALT);
3675        mdelay(200);
3676        AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT);
3677        AscSetChipStatus(iop_base, 0);
3678        return (AscIsChipHalted(iop_base));
3679}
3680
3681static int AscFindSignature(PortAddr iop_base)
3682{
3683        ushort sig_word;
3684
3685        ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n",
3686                 iop_base, AscGetChipSignatureByte(iop_base));
3687        if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) {
3688                ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n",
3689                         iop_base, AscGetChipSignatureWord(iop_base));
3690                sig_word = AscGetChipSignatureWord(iop_base);
3691                if ((sig_word == (ushort)ASC_1000_ID0W) ||
3692                    (sig_word == (ushort)ASC_1000_ID0W_FIX)) {
3693                        return (1);
3694                }
3695        }
3696        return (0);
3697}
3698
3699static void AscEnableInterrupt(PortAddr iop_base)
3700{
3701        ushort cfg;
3702
3703        cfg = AscGetChipCfgLsw(iop_base);
3704        AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON);
3705}
3706
3707static void AscDisableInterrupt(PortAddr iop_base)
3708{
3709        ushort cfg;
3710
3711        cfg = AscGetChipCfgLsw(iop_base);
3712        AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON));
3713}
3714
3715static uchar AscReadLramByte(PortAddr iop_base, ushort addr)
3716{
3717        unsigned char byte_data;
3718        unsigned short word_data;
3719
3720        if (isodd_word(addr)) {
3721                AscSetChipLramAddr(iop_base, addr - 1);
3722                word_data = AscGetChipLramData(iop_base);
3723                byte_data = (word_data >> 8) & 0xFF;
3724        } else {
3725                AscSetChipLramAddr(iop_base, addr);
3726                word_data = AscGetChipLramData(iop_base);
3727                byte_data = word_data & 0xFF;
3728        }
3729        return byte_data;
3730}
3731
3732static ushort AscReadLramWord(PortAddr iop_base, ushort addr)
3733{
3734        ushort word_data;
3735
3736        AscSetChipLramAddr(iop_base, addr);
3737        word_data = AscGetChipLramData(iop_base);
3738        return (word_data);
3739}
3740
3741static void
3742AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words)
3743{
3744        int i;
3745
3746        AscSetChipLramAddr(iop_base, s_addr);
3747        for (i = 0; i < words; i++) {
3748                AscSetChipLramData(iop_base, set_wval);
3749        }
3750}
3751
3752static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val)
3753{
3754        AscSetChipLramAddr(iop_base, addr);
3755        AscSetChipLramData(iop_base, word_val);
3756}
3757
3758static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val)
3759{
3760        ushort word_data;
3761
3762        if (isodd_word(addr)) {
3763                addr--;
3764                word_data = AscReadLramWord(iop_base, addr);
3765                word_data &= 0x00FF;
3766                word_data |= (((ushort)byte_val << 8) & 0xFF00);
3767        } else {
3768                word_data = AscReadLramWord(iop_base, addr);
3769                word_data &= 0xFF00;
3770                word_data |= ((ushort)byte_val & 0x00FF);
3771        }
3772        AscWriteLramWord(iop_base, addr, word_data);
3773}
3774
3775/*
3776 * Copy 2 bytes to LRAM.
3777 *
3778 * The source data is assumed to be in little-endian order in memory
3779 * and is maintained in little-endian order when written to LRAM.
3780 */
3781static void
3782AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr,
3783                        const uchar *s_buffer, int words)
3784{
3785        int i;
3786
3787        AscSetChipLramAddr(iop_base, s_addr);
3788        for (i = 0; i < 2 * words; i += 2) {
3789                /*
3790                 * On a little-endian system the second argument below
3791                 * produces a little-endian ushort which is written to
3792                 * LRAM in little-endian order. On a big-endian system
3793                 * the second argument produces a big-endian ushort which
3794                 * is "transparently" byte-swapped by outpw() and written
3795                 * in little-endian order to LRAM.
3796                 */
3797                outpw(iop_base + IOP_RAM_DATA,
3798                      ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);
3799        }
3800}
3801
3802/*
3803 * Copy 4 bytes to LRAM.
3804 *
3805 * The source data is assumed to be in little-endian order in memory
3806 * and is maintained in little-endian order when written to LRAM.
3807 */
3808static void
3809AscMemDWordCopyPtrToLram(PortAddr iop_base,
3810                         ushort s_addr, uchar *s_buffer, int dwords)
3811{
3812        int i;
3813
3814        AscSetChipLramAddr(iop_base, s_addr);
3815        for (i = 0; i < 4 * dwords; i += 4) {
3816                outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]);   /* LSW */
3817                outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]);       /* MSW */
3818        }
3819}
3820
3821/*
3822 * Copy 2 bytes from LRAM.
3823 *
3824 * The source data is assumed to be in little-endian order in LRAM
3825 * and is maintained in little-endian order when written to memory.
3826 */
3827static void
3828AscMemWordCopyPtrFromLram(PortAddr iop_base,
3829                          ushort s_addr, uchar *d_buffer, int words)
3830{
3831        int i;
3832        ushort word;
3833
3834        AscSetChipLramAddr(iop_base, s_addr);
3835        for (i = 0; i < 2 * words; i += 2) {
3836                word = inpw(iop_base + IOP_RAM_DATA);
3837                d_buffer[i] = word & 0xff;
3838                d_buffer[i + 1] = (word >> 8) & 0xff;
3839        }
3840}
3841
3842static u32 AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words)
3843{
3844        u32 sum = 0;
3845        int i;
3846
3847        for (i = 0; i < words; i++, s_addr += 2) {
3848                sum += AscReadLramWord(iop_base, s_addr);
3849        }
3850        return (sum);
3851}
3852
3853static void AscInitLram(ASC_DVC_VAR *asc_dvc)
3854{
3855        uchar i;
3856        ushort s_addr;
3857        PortAddr iop_base;
3858
3859        iop_base = asc_dvc->iop_base;
3860        AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0,
3861                          (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) *
3862                                    64) >> 1));
3863        i = ASC_MIN_ACTIVE_QNO;
3864        s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE;
3865        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3866                         (uchar)(i + 1));
3867        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3868                         (uchar)(asc_dvc->max_total_qng));
3869        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3870                         (uchar)i);
3871        i++;
3872        s_addr += ASC_QBLK_SIZE;
3873        for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) {
3874                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3875                                 (uchar)(i + 1));
3876                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3877                                 (uchar)(i - 1));
3878                AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3879                                 (uchar)i);
3880        }
3881        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD),
3882                         (uchar)ASC_QLINK_END);
3883        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD),
3884                         (uchar)(asc_dvc->max_total_qng - 1));
3885        AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO),
3886                         (uchar)asc_dvc->max_total_qng);
3887        i++;
3888        s_addr += ASC_QBLK_SIZE;
3889        for (; i <= (uchar)(asc_dvc->max_total_qng + 3);
3890             i++, s_addr += ASC_QBLK_SIZE) {
3891                AscWriteLramByte(iop_base,
3892                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i);
3893                AscWriteLramByte(iop_base,
3894                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i);
3895                AscWriteLramByte(iop_base,
3896                                 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i);
3897        }
3898}
3899
3900static u32
3901AscLoadMicroCode(PortAddr iop_base, ushort s_addr,
3902                 const uchar *mcode_buf, ushort mcode_size)
3903{
3904        u32 chksum;
3905        ushort mcode_word_size;
3906        ushort mcode_chksum;
3907
3908        /* Write the microcode buffer starting at LRAM address 0. */
3909        mcode_word_size = (ushort)(mcode_size >> 1);
3910        AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size);
3911        AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size);
3912
3913        chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size);
3914        ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum);
3915        mcode_chksum = (ushort)AscMemSumLramWord(iop_base,
3916                                                 (ushort)ASC_CODE_SEC_BEG,
3917                                                 (ushort)((mcode_size -
3918                                                           s_addr - (ushort)
3919                                                           ASC_CODE_SEC_BEG) /
3920                                                          2));
3921        ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum);
3922        AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum);
3923        AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size);
3924        return chksum;
3925}
3926
3927static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc)
3928{
3929        PortAddr iop_base;
3930        int i;
3931        ushort lram_addr;
3932
3933        iop_base = asc_dvc->iop_base;
3934        AscPutRiscVarFreeQHead(iop_base, 1);
3935        AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng);
3936        AscPutVarFreeQHead(iop_base, 1);
3937        AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng);
3938        AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B,
3939                         (uchar)((int)asc_dvc->max_total_qng + 1));
3940        AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B,
3941                         (uchar)((int)asc_dvc->max_total_qng + 2));
3942        AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B,
3943                         asc_dvc->max_total_qng);
3944        AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0);
3945        AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0);
3946        AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0);
3947        AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0);
3948        AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0);
3949        AscPutQDoneInProgress(iop_base, 0);
3950        lram_addr = ASC_QADR_BEG;
3951        for (i = 0; i < 32; i++, lram_addr += 2) {
3952                AscWriteLramWord(iop_base, lram_addr, 0);
3953        }
3954}
3955
3956static int AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc)
3957{
3958        int i;
3959        int warn_code;
3960        PortAddr iop_base;
3961        __le32 phy_addr;
3962        __le32 phy_size;
3963        struct asc_board *board = asc_dvc_to_board(asc_dvc);
3964
3965        iop_base = asc_dvc->iop_base;
3966        warn_code = 0;
3967        for (i = 0; i <= ASC_MAX_TID; i++) {
3968                AscPutMCodeInitSDTRAtID(iop_base, i,
3969                                        asc_dvc->cfg->sdtr_period_offset[i]);
3970        }
3971
3972        AscInitQLinkVar(asc_dvc);
3973        AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B,
3974                         asc_dvc->cfg->disc_enable);
3975        AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B,
3976                         ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id));
3977
3978        /* Ensure overrun buffer is aligned on an 8 byte boundary. */
3979        BUG_ON((unsigned long)asc_dvc->overrun_buf & 7);
3980        asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf,
3981                                        ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
3982        if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) {
3983                warn_code = -ENOMEM;
3984                goto err_dma_map;
3985        }
3986        phy_addr = cpu_to_le32(asc_dvc->overrun_dma);
3987        AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D,
3988                                 (uchar *)&phy_addr, 1);
3989        phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE);
3990        AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D,
3991                                 (uchar *)&phy_size, 1);
3992
3993        asc_dvc->cfg->mcode_date =
3994            AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W);
3995        asc_dvc->cfg->mcode_version =
3996            AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W);
3997
3998        AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR);
3999        if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) {
4000                asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR;
4001                warn_code = -EINVAL;
4002                goto err_mcode_start;
4003        }
4004        if (AscStartChip(iop_base) != 1) {
4005                asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP;
4006                warn_code = -EIO;
4007                goto err_mcode_start;
4008        }
4009
4010        return warn_code;
4011
4012err_mcode_start:
4013        dma_unmap_single(board->dev, asc_dvc->overrun_dma,
4014                         ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE);
4015err_dma_map:
4016        asc_dvc->overrun_dma = 0;
4017        return warn_code;
4018}
4019
4020static int AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc)
4021{
4022        const struct firmware *fw;
4023        const char fwname[] = "advansys/mcode.bin";
4024        int err;
4025        unsigned long chksum;
4026        int warn_code;
4027        PortAddr iop_base;
4028
4029        iop_base = asc_dvc->iop_base;
4030        warn_code = 0;
4031        if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) &&
4032            !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) {
4033                AscResetChipAndScsiBus(asc_dvc);
4034                mdelay(asc_dvc->scsi_reset_wait * 1000); /* XXX: msleep? */
4035        }
4036        asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC;
4037        if (asc_dvc->err_code != 0)
4038                return ASC_ERROR;
4039        if (!AscFindSignature(asc_dvc->iop_base)) {
4040                asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE;
4041                return warn_code;
4042        }
4043        AscDisableInterrupt(iop_base);
4044        AscInitLram(asc_dvc);
4045
4046        err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev);
4047        if (err) {
4048                printk(KERN_ERR "Failed to load image \"%s\" err %d\n",
4049                       fwname, err);
4050                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4051                return err;
4052        }
4053        if (fw->size < 4) {
4054                printk(KERN_ERR "Bogus length %zu in image \"%s\"\n",
4055                       fw->size, fwname);
4056                release_firmware(fw);
4057                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4058                return -EINVAL;
4059        }
4060        chksum = (fw->data[3] << 24) | (fw->data[2] << 16) |
4061                 (fw->data[1] << 8) | fw->data[0];
4062        ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum);
4063        if (AscLoadMicroCode(iop_base, 0, &fw->data[4],
4064                             fw->size - 4) != chksum) {
4065                asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM;
4066                release_firmware(fw);
4067                return warn_code;
4068        }
4069        release_firmware(fw);
4070        warn_code |= AscInitMicroCodeVar(asc_dvc);
4071        if (!asc_dvc->overrun_dma)
4072                return warn_code;
4073        asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC;
4074        AscEnableInterrupt(iop_base);
4075        return warn_code;
4076}
4077
4078/*
4079 * Load the Microcode
4080 *
4081 * Write the microcode image to RISC memory starting at address 0.
4082 *
4083 * The microcode is stored compressed in the following format:
4084 *
4085 *  254 word (508 byte) table indexed by byte code followed
4086 *  by the following byte codes:
4087 *
4088 *    1-Byte Code:
4089 *      00: Emit word 0 in table.
4090 *      01: Emit word 1 in table.
4091 *      .
4092 *      FD: Emit word 253 in table.
4093 *
4094 *    Multi-Byte Code:
4095 *      FE WW WW: (3 byte code) Word to emit is the next word WW WW.
4096 *      FF BB WW WW: (4 byte code) Emit BB count times next word WW WW.
4097 *
4098 * Returns 0 or an error if the checksum doesn't match
4099 */
4100static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf,
4101                            int size, int memsize, int chksum)
4102{
4103        int i, j, end, len = 0;
4104        u32 sum;
4105
4106        AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4107
4108        for (i = 253 * 2; i < size; i++) {
4109                if (buf[i] == 0xff) {
4110                        unsigned short word = (buf[i + 3] << 8) | buf[i + 2];
4111                        for (j = 0; j < buf[i + 1]; j++) {
4112                                AdvWriteWordAutoIncLram(iop_base, word);
4113                                len += 2;
4114                        }
4115                        i += 3;
4116                } else if (buf[i] == 0xfe) {
4117                        unsigned short word = (buf[i + 2] << 8) | buf[i + 1];
4118                        AdvWriteWordAutoIncLram(iop_base, word);
4119                        i += 2;
4120                        len += 2;
4121                } else {
4122                        unsigned int off = buf[i] * 2;
4123                        unsigned short word = (buf[off + 1] << 8) | buf[off];
4124                        AdvWriteWordAutoIncLram(iop_base, word);
4125                        len += 2;
4126                }
4127        }
4128
4129        end = len;
4130
4131        while (len < memsize) {
4132                AdvWriteWordAutoIncLram(iop_base, 0);
4133                len += 2;
4134        }
4135
4136        /* Verify the microcode checksum. */
4137        sum = 0;
4138        AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0);
4139
4140        for (len = 0; len < end; len += 2) {
4141                sum += AdvReadWordAutoIncLram(iop_base);
4142        }
4143
4144        if (sum != chksum)
4145                return ASC_IERR_MCODE_CHKSUM;
4146
4147        return 0;
4148}
4149
4150static void AdvBuildCarrierFreelist(struct adv_dvc_var *adv_dvc)
4151{
4152        off_t carr_offset = 0, next_offset;
4153        dma_addr_t carr_paddr;
4154        int carr_num = ADV_CARRIER_BUFSIZE / sizeof(ADV_CARR_T), i;
4155
4156        for (i = 0; i < carr_num; i++) {
4157                carr_offset = i * sizeof(ADV_CARR_T);
4158                /* Get physical address of the carrier 'carrp'. */
4159                carr_paddr = adv_dvc->carrier_addr + carr_offset;
4160
4161                adv_dvc->carrier[i].carr_pa = cpu_to_le32(carr_paddr);
4162                adv_dvc->carrier[i].carr_va = cpu_to_le32(carr_offset);
4163                adv_dvc->carrier[i].areq_vpa = 0;
4164                next_offset = carr_offset + sizeof(ADV_CARR_T);
4165                if (i == carr_num)
4166                        next_offset = ~0;
4167                adv_dvc->carrier[i].next_vpa = cpu_to_le32(next_offset);
4168        }
4169        /*
4170         * We cannot have a carrier with 'carr_va' of '0', as
4171         * a reference to this carrier would be interpreted as
4172         * list termination.
4173         * So start at carrier 1 with the freelist.
4174         */
4175        adv_dvc->carr_freelist = &adv_dvc->carrier[1];
4176}
4177
4178static ADV_CARR_T *adv_get_carrier(struct adv_dvc_var *adv_dvc, u32 offset)
4179{
4180        int index;
4181
4182        BUG_ON(offset > ADV_CARRIER_BUFSIZE);
4183
4184        index = offset / sizeof(ADV_CARR_T);
4185        return &adv_dvc->carrier[index];
4186}
4187
4188static ADV_CARR_T *adv_get_next_carrier(struct adv_dvc_var *adv_dvc)
4189{
4190        ADV_CARR_T *carrp = adv_dvc->carr_freelist;
4191        u32 next_vpa = le32_to_cpu(carrp->next_vpa);
4192
4193        if (next_vpa == 0 || next_vpa == ~0) {
4194                ASC_DBG(1, "invalid vpa offset 0x%x\n", next_vpa);
4195                return NULL;
4196        }
4197
4198        adv_dvc->carr_freelist = adv_get_carrier(adv_dvc, next_vpa);
4199        /*
4200         * insert stopper carrier to terminate list
4201         */
4202        carrp->next_vpa = cpu_to_le32(ADV_CQ_STOPPER);
4203
4204        return carrp;
4205}
4206
4207/*
4208 * 'offset' is the index in the request pointer array
4209 */
4210static adv_req_t * adv_get_reqp(struct adv_dvc_var *adv_dvc, u32 offset)
4211{
4212        struct asc_board *boardp = adv_dvc->drv_ptr;
4213
4214        BUG_ON(offset > adv_dvc->max_host_qng);
4215        return &boardp->adv_reqp[offset];
4216}
4217
4218/*
4219 * Send an idle command to the chip and wait for completion.
4220 *
4221 * Command completion is polled for once per microsecond.
4222 *
4223 * The function can be called from anywhere including an interrupt handler.
4224 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical()
4225 * functions to prevent reentrancy.
4226 *
4227 * Return Values:
4228 *   ADV_TRUE - command completed successfully
4229 *   ADV_FALSE - command failed
4230 *   ADV_ERROR - command timed out
4231 */
4232static int
4233AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc,
4234               ushort idle_cmd, u32 idle_cmd_parameter)
4235{
4236        int result, i, j;
4237        AdvPortAddr iop_base;
4238
4239        iop_base = asc_dvc->iop_base;
4240
4241        /*
4242         * Clear the idle command status which is set by the microcode
4243         * to a non-zero value to indicate when the command is completed.
4244         * The non-zero result is one of the IDLE_CMD_STATUS_* values
4245         */
4246        AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0);
4247
4248        /*
4249         * Write the idle command value after the idle command parameter
4250         * has been written to avoid a race condition. If the order is not
4251         * followed, the microcode may process the idle command before the
4252         * parameters have been written to LRAM.
4253         */
4254        AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER,
4255                                cpu_to_le32(idle_cmd_parameter));
4256        AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd);
4257
4258        /*
4259         * Tickle the RISC to tell it to process the idle command.
4260         */
4261        AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B);
4262        if (asc_dvc->chip_type == ADV_CHIP_ASC3550) {
4263                /*
4264                 * Clear the tickle value. In the ASC-3550 the RISC flag
4265                 * command 'clr_tickle_b' does not work unless the host
4266                 * value is cleared.
4267                 */
4268                AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP);
4269        }
4270
4271        /* Wait for up to 100 millisecond for the idle command to timeout. */
4272        for (i = 0; i < SCSI_WAIT_100_MSEC; i++) {
4273                /* Poll once each microsecond for command completion. */
4274                for (j = 0; j < SCSI_US_PER_MSEC; j++) {
4275                        AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS,
4276                                        result);
4277                        if (result != 0)
4278                                return result;
4279                        udelay(1);
4280                }
4281        }
4282
4283        BUG();          /* The idle command should never timeout. */
4284        return ADV_ERROR;
4285}
4286
4287/*
4288 * Reset SCSI Bus and purge all outstanding requests.
4289 *
4290 * Return Value:
4291 *      ADV_TRUE(1) -   All requests are purged and SCSI Bus is reset.
4292 *      ADV_FALSE(0) -  Microcode command failed.
4293 *      ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC
4294 *                      may be hung which requires driver recovery.
4295 */
4296static int AdvResetSB(ADV_DVC_VAR *asc_dvc)
4297{
4298        int status;
4299
4300        /*
4301         * Send the SCSI Bus Reset idle start idle command which asserts
4302         * the SCSI Bus Reset signal.
4303         */
4304        status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L);
4305        if (status != ADV_TRUE) {
4306                return status;
4307        }
4308
4309        /*
4310         * Delay for the specified SCSI Bus Reset hold time.
4311         *
4312         * The hold time delay is done on the host because the RISC has no
4313         * microsecond accurate timer.
4314         */
4315        udelay(ASC_SCSI_RESET_HOLD_TIME_US);
4316
4317        /*
4318         * Send the SCSI Bus Reset end idle command which de-asserts
4319         * the SCSI Bus Reset signal and purges any pending requests.
4320         */
4321        status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L);
4322        if (status != ADV_TRUE) {
4323                return status;
4324        }
4325
4326        mdelay(asc_dvc->scsi_reset_wait * 1000);        /* XXX: msleep? */
4327
4328        return status;
4329}
4330
4331/*
4332 * Initialize the ASC-3550.
4333 *
4334 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR.
4335 *
4336 * For a non-fatal error return a warning code. If there are no warnings
4337 * then 0 is returned.
4338 *
4339 * Needed after initialization for error recovery.
4340 */
4341static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc)
4342{
4343        const struct firmware *fw;
4344        const char fwname[] = "advansys/3550.bin";
4345        AdvPortAddr iop_base;
4346        ushort warn_code;
4347        int begin_addr;
4348        int end_addr;
4349        ushort code_sum;
4350        int word;
4351        int i;
4352        int err;
4353        unsigned long chksum;
4354        ushort scsi_cfg1;
4355        uchar tid;
4356        ushort bios_mem[ASC_MC_BIOSLEN / 2];    /* BIOS RISC Memory 0x40-0x8F. */
4357        ushort wdtr_able = 0, sdtr_able, tagqng_able;
4358        uchar max_cmd[ADV_MAX_TID + 1];
4359
4360        /* If there is already an error, don't continue. */
4361        if (asc_dvc->err_code != 0)
4362                return ADV_ERROR;
4363
4364        /*
4365         * The caller must set 'chip_type' to ADV_CHIP_ASC3550.
4366         */
4367        if (asc_dvc->chip_type != ADV_CHIP_ASC3550) {
4368                asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE;
4369                return ADV_ERROR;
4370        }
4371
4372        warn_code = 0;
4373        iop_base = asc_dvc->iop_base;
4374
4375        /*
4376         * Save the RISC memory BIOS region before writing the microcode.
4377         * The BIOS may already be loaded and using its RISC LRAM region
4378         * so its region must be saved and restored.
4379         *
4380         * Note: This code makes the assumption, which is currently true,
4381         * that a chip reset does not clear RISC LRAM.
4382         */
4383        for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) {
4384                AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i),