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7#include <linux/delay.h>
8#include <linux/err.h>
9#include <linux/io.h>
10#include <linux/module.h>
11#include <linux/of.h>
12#include <linux/platform_device.h>
13#include <linux/pinctrl/machine.h>
14#include <linux/pinctrl/pinctrl.h>
15#include <linux/pinctrl/pinmux.h>
16#include <linux/pinctrl/pinconf.h>
17#include <linux/pinctrl/pinconf-generic.h>
18#include <linux/slab.h>
19#include <linux/gpio/driver.h>
20#include <linux/interrupt.h>
21#include <linux/spinlock.h>
22#include <linux/reboot.h>
23#include <linux/pm.h>
24#include <linux/log2.h>
25#include <linux/qcom_scm.h>
26
27#include <linux/soc/qcom/irq.h>
28
29#include "../core.h"
30#include "../pinconf.h"
31#include "pinctrl-msm.h"
32#include "../pinctrl-utils.h"
33
34#define MAX_NR_GPIO 300
35#define MAX_NR_TILES 4
36#define PS_HOLD_OFFSET 0x820
37
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58
59struct msm_pinctrl {
60 struct device *dev;
61 struct pinctrl_dev *pctrl;
62 struct gpio_chip chip;
63 struct pinctrl_desc desc;
64 struct notifier_block restart_nb;
65
66 struct irq_chip irq_chip;
67 int irq;
68
69 bool intr_target_use_scm;
70
71 raw_spinlock_t lock;
72
73 DECLARE_BITMAP(dual_edge_irqs, MAX_NR_GPIO);
74 DECLARE_BITMAP(enabled_irqs, MAX_NR_GPIO);
75 DECLARE_BITMAP(skip_wake_irqs, MAX_NR_GPIO);
76 DECLARE_BITMAP(disabled_for_mux, MAX_NR_GPIO);
77
78 const struct msm_pinctrl_soc_data *soc;
79 void __iomem *regs[MAX_NR_TILES];
80 u32 phys_base[MAX_NR_TILES];
81};
82
83#define MSM_ACCESSOR(name) \
84static u32 msm_readl_##name(struct msm_pinctrl *pctrl, \
85 const struct msm_pingroup *g) \
86{ \
87 return readl(pctrl->regs[g->tile] + g->name##_reg); \
88} \
89static void msm_writel_##name(u32 val, struct msm_pinctrl *pctrl, \
90 const struct msm_pingroup *g) \
91{ \
92 writel(val, pctrl->regs[g->tile] + g->name##_reg); \
93}
94
95MSM_ACCESSOR(ctl)
96MSM_ACCESSOR(io)
97MSM_ACCESSOR(intr_cfg)
98MSM_ACCESSOR(intr_status)
99MSM_ACCESSOR(intr_target)
100
101static void msm_ack_intr_status(struct msm_pinctrl *pctrl,
102 const struct msm_pingroup *g)
103{
104 u32 val = g->intr_ack_high ? BIT(g->intr_status_bit) : 0;
105
106 msm_writel_intr_status(val, pctrl, g);
107}
108
109static int msm_get_groups_count(struct pinctrl_dev *pctldev)
110{
111 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
112
113 return pctrl->soc->ngroups;
114}
115
116static const char *msm_get_group_name(struct pinctrl_dev *pctldev,
117 unsigned group)
118{
119 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
120
121 return pctrl->soc->groups[group].name;
122}
123
124static int msm_get_group_pins(struct pinctrl_dev *pctldev,
125 unsigned group,
126 const unsigned **pins,
127 unsigned *num_pins)
128{
129 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
130
131 *pins = pctrl->soc->groups[group].pins;
132 *num_pins = pctrl->soc->groups[group].npins;
133 return 0;
134}
135
136static const struct pinctrl_ops msm_pinctrl_ops = {
137 .get_groups_count = msm_get_groups_count,
138 .get_group_name = msm_get_group_name,
139 .get_group_pins = msm_get_group_pins,
140 .dt_node_to_map = pinconf_generic_dt_node_to_map_group,
141 .dt_free_map = pinctrl_utils_free_map,
142};
143
144static int msm_pinmux_request(struct pinctrl_dev *pctldev, unsigned offset)
145{
146 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
147 struct gpio_chip *chip = &pctrl->chip;
148
149 return gpiochip_line_is_valid(chip, offset) ? 0 : -EINVAL;
150}
151
152static int msm_get_functions_count(struct pinctrl_dev *pctldev)
153{
154 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
155
156 return pctrl->soc->nfunctions;
157}
158
159static const char *msm_get_function_name(struct pinctrl_dev *pctldev,
160 unsigned function)
161{
162 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
163
164 return pctrl->soc->functions[function].name;
165}
166
167static int msm_get_function_groups(struct pinctrl_dev *pctldev,
168 unsigned function,
169 const char * const **groups,
170 unsigned * const num_groups)
171{
172 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
173
174 *groups = pctrl->soc->functions[function].groups;
175 *num_groups = pctrl->soc->functions[function].ngroups;
176 return 0;
177}
178
179static int msm_pinmux_set_mux(struct pinctrl_dev *pctldev,
180 unsigned function,
181 unsigned group)
182{
183 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
184 struct gpio_chip *gc = &pctrl->chip;
185 unsigned int irq = irq_find_mapping(gc->irq.domain, group);
186 struct irq_data *d = irq_get_irq_data(irq);
187 unsigned int gpio_func = pctrl->soc->gpio_func;
188 const struct msm_pingroup *g;
189 unsigned long flags;
190 u32 val, mask;
191 int i;
192
193 g = &pctrl->soc->groups[group];
194 mask = GENMASK(g->mux_bit + order_base_2(g->nfuncs) - 1, g->mux_bit);
195
196 for (i = 0; i < g->nfuncs; i++) {
197 if (g->funcs[i] == function)
198 break;
199 }
200
201 if (WARN_ON(i == g->nfuncs))
202 return -EINVAL;
203
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210
211
212
213
214 if (d && i != gpio_func &&
215 !test_and_set_bit(d->hwirq, pctrl->disabled_for_mux))
216 disable_irq(irq);
217
218 raw_spin_lock_irqsave(&pctrl->lock, flags);
219
220 val = msm_readl_ctl(pctrl, g);
221 val &= ~mask;
222 val |= i << g->mux_bit;
223 msm_writel_ctl(val, pctrl, g);
224
225 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
226
227 if (d && i == gpio_func &&
228 test_and_clear_bit(d->hwirq, pctrl->disabled_for_mux)) {
229
230
231
232
233 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
234 irq_chip_set_parent_state(d, IRQCHIP_STATE_PENDING, false);
235 else
236 msm_ack_intr_status(pctrl, g);
237
238 enable_irq(irq);
239 }
240
241 return 0;
242}
243
244static int msm_pinmux_request_gpio(struct pinctrl_dev *pctldev,
245 struct pinctrl_gpio_range *range,
246 unsigned offset)
247{
248 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
249 const struct msm_pingroup *g = &pctrl->soc->groups[offset];
250
251
252 if (!g->nfuncs)
253 return 0;
254
255 return msm_pinmux_set_mux(pctldev, g->funcs[pctrl->soc->gpio_func], offset);
256}
257
258static const struct pinmux_ops msm_pinmux_ops = {
259 .request = msm_pinmux_request,
260 .get_functions_count = msm_get_functions_count,
261 .get_function_name = msm_get_function_name,
262 .get_function_groups = msm_get_function_groups,
263 .gpio_request_enable = msm_pinmux_request_gpio,
264 .set_mux = msm_pinmux_set_mux,
265};
266
267static int msm_config_reg(struct msm_pinctrl *pctrl,
268 const struct msm_pingroup *g,
269 unsigned param,
270 unsigned *mask,
271 unsigned *bit)
272{
273 switch (param) {
274 case PIN_CONFIG_BIAS_DISABLE:
275 case PIN_CONFIG_BIAS_PULL_DOWN:
276 case PIN_CONFIG_BIAS_BUS_HOLD:
277 case PIN_CONFIG_BIAS_PULL_UP:
278 *bit = g->pull_bit;
279 *mask = 3;
280 break;
281 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
282 *bit = g->od_bit;
283 *mask = 1;
284 break;
285 case PIN_CONFIG_DRIVE_STRENGTH:
286 *bit = g->drv_bit;
287 *mask = 7;
288 break;
289 case PIN_CONFIG_OUTPUT:
290 case PIN_CONFIG_INPUT_ENABLE:
291 *bit = g->oe_bit;
292 *mask = 1;
293 break;
294 default:
295 return -ENOTSUPP;
296 }
297
298 return 0;
299}
300
301#define MSM_NO_PULL 0
302#define MSM_PULL_DOWN 1
303#define MSM_KEEPER 2
304#define MSM_PULL_UP_NO_KEEPER 2
305#define MSM_PULL_UP 3
306
307static unsigned msm_regval_to_drive(u32 val)
308{
309 return (val + 1) * 2;
310}
311
312static int msm_config_group_get(struct pinctrl_dev *pctldev,
313 unsigned int group,
314 unsigned long *config)
315{
316 const struct msm_pingroup *g;
317 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
318 unsigned param = pinconf_to_config_param(*config);
319 unsigned mask;
320 unsigned arg;
321 unsigned bit;
322 int ret;
323 u32 val;
324
325 g = &pctrl->soc->groups[group];
326
327 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
328 if (ret < 0)
329 return ret;
330
331 val = msm_readl_ctl(pctrl, g);
332 arg = (val >> bit) & mask;
333
334
335 switch (param) {
336 case PIN_CONFIG_BIAS_DISABLE:
337 if (arg != MSM_NO_PULL)
338 return -EINVAL;
339 arg = 1;
340 break;
341 case PIN_CONFIG_BIAS_PULL_DOWN:
342 if (arg != MSM_PULL_DOWN)
343 return -EINVAL;
344 arg = 1;
345 break;
346 case PIN_CONFIG_BIAS_BUS_HOLD:
347 if (pctrl->soc->pull_no_keeper)
348 return -ENOTSUPP;
349
350 if (arg != MSM_KEEPER)
351 return -EINVAL;
352 arg = 1;
353 break;
354 case PIN_CONFIG_BIAS_PULL_UP:
355 if (pctrl->soc->pull_no_keeper)
356 arg = arg == MSM_PULL_UP_NO_KEEPER;
357 else
358 arg = arg == MSM_PULL_UP;
359 if (!arg)
360 return -EINVAL;
361 break;
362 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
363
364 if (!arg)
365 return -EINVAL;
366 arg = 1;
367 break;
368 case PIN_CONFIG_DRIVE_STRENGTH:
369 arg = msm_regval_to_drive(arg);
370 break;
371 case PIN_CONFIG_OUTPUT:
372
373 if (!arg)
374 return -EINVAL;
375
376 val = msm_readl_io(pctrl, g);
377 arg = !!(val & BIT(g->in_bit));
378 break;
379 case PIN_CONFIG_INPUT_ENABLE:
380
381 if (arg)
382 return -EINVAL;
383 arg = 1;
384 break;
385 default:
386 return -ENOTSUPP;
387 }
388
389 *config = pinconf_to_config_packed(param, arg);
390
391 return 0;
392}
393
394static int msm_config_group_set(struct pinctrl_dev *pctldev,
395 unsigned group,
396 unsigned long *configs,
397 unsigned num_configs)
398{
399 const struct msm_pingroup *g;
400 struct msm_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
401 unsigned long flags;
402 unsigned param;
403 unsigned mask;
404 unsigned arg;
405 unsigned bit;
406 int ret;
407 u32 val;
408 int i;
409
410 g = &pctrl->soc->groups[group];
411
412 for (i = 0; i < num_configs; i++) {
413 param = pinconf_to_config_param(configs[i]);
414 arg = pinconf_to_config_argument(configs[i]);
415
416 ret = msm_config_reg(pctrl, g, param, &mask, &bit);
417 if (ret < 0)
418 return ret;
419
420
421 switch (param) {
422 case PIN_CONFIG_BIAS_DISABLE:
423 arg = MSM_NO_PULL;
424 break;
425 case PIN_CONFIG_BIAS_PULL_DOWN:
426 arg = MSM_PULL_DOWN;
427 break;
428 case PIN_CONFIG_BIAS_BUS_HOLD:
429 if (pctrl->soc->pull_no_keeper)
430 return -ENOTSUPP;
431
432 arg = MSM_KEEPER;
433 break;
434 case PIN_CONFIG_BIAS_PULL_UP:
435 if (pctrl->soc->pull_no_keeper)
436 arg = MSM_PULL_UP_NO_KEEPER;
437 else
438 arg = MSM_PULL_UP;
439 break;
440 case PIN_CONFIG_DRIVE_OPEN_DRAIN:
441 arg = 1;
442 break;
443 case PIN_CONFIG_DRIVE_STRENGTH:
444
445 if (arg > 16 || arg < 2 || (arg % 2) != 0)
446 arg = -1;
447 else
448 arg = (arg / 2) - 1;
449 break;
450 case PIN_CONFIG_OUTPUT:
451
452 raw_spin_lock_irqsave(&pctrl->lock, flags);
453 val = msm_readl_io(pctrl, g);
454 if (arg)
455 val |= BIT(g->out_bit);
456 else
457 val &= ~BIT(g->out_bit);
458 msm_writel_io(val, pctrl, g);
459 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
460
461
462 arg = 1;
463 break;
464 case PIN_CONFIG_INPUT_ENABLE:
465
466 arg = 0;
467 break;
468 default:
469 dev_err(pctrl->dev, "Unsupported config parameter: %x\n",
470 param);
471 return -EINVAL;
472 }
473
474
475 if (arg & ~mask) {
476 dev_err(pctrl->dev, "config %x: %x is invalid\n", param, arg);
477 return -EINVAL;
478 }
479
480 raw_spin_lock_irqsave(&pctrl->lock, flags);
481 val = msm_readl_ctl(pctrl, g);
482 val &= ~(mask << bit);
483 val |= arg << bit;
484 msm_writel_ctl(val, pctrl, g);
485 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
486 }
487
488 return 0;
489}
490
491static const struct pinconf_ops msm_pinconf_ops = {
492 .is_generic = true,
493 .pin_config_group_get = msm_config_group_get,
494 .pin_config_group_set = msm_config_group_set,
495};
496
497static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
498{
499 const struct msm_pingroup *g;
500 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
501 unsigned long flags;
502 u32 val;
503
504 g = &pctrl->soc->groups[offset];
505
506 raw_spin_lock_irqsave(&pctrl->lock, flags);
507
508 val = msm_readl_ctl(pctrl, g);
509 val &= ~BIT(g->oe_bit);
510 msm_writel_ctl(val, pctrl, g);
511
512 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
513
514 return 0;
515}
516
517static int msm_gpio_direction_output(struct gpio_chip *chip, unsigned offset, int value)
518{
519 const struct msm_pingroup *g;
520 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
521 unsigned long flags;
522 u32 val;
523
524 g = &pctrl->soc->groups[offset];
525
526 raw_spin_lock_irqsave(&pctrl->lock, flags);
527
528 val = msm_readl_io(pctrl, g);
529 if (value)
530 val |= BIT(g->out_bit);
531 else
532 val &= ~BIT(g->out_bit);
533 msm_writel_io(val, pctrl, g);
534
535 val = msm_readl_ctl(pctrl, g);
536 val |= BIT(g->oe_bit);
537 msm_writel_ctl(val, pctrl, g);
538
539 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
540
541 return 0;
542}
543
544static int msm_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
545{
546 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
547 const struct msm_pingroup *g;
548 u32 val;
549
550 g = &pctrl->soc->groups[offset];
551
552 val = msm_readl_ctl(pctrl, g);
553
554 return val & BIT(g->oe_bit) ? GPIO_LINE_DIRECTION_OUT :
555 GPIO_LINE_DIRECTION_IN;
556}
557
558static int msm_gpio_get(struct gpio_chip *chip, unsigned offset)
559{
560 const struct msm_pingroup *g;
561 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
562 u32 val;
563
564 g = &pctrl->soc->groups[offset];
565
566 val = msm_readl_io(pctrl, g);
567 return !!(val & BIT(g->in_bit));
568}
569
570static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
571{
572 const struct msm_pingroup *g;
573 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
574 unsigned long flags;
575 u32 val;
576
577 g = &pctrl->soc->groups[offset];
578
579 raw_spin_lock_irqsave(&pctrl->lock, flags);
580
581 val = msm_readl_io(pctrl, g);
582 if (value)
583 val |= BIT(g->out_bit);
584 else
585 val &= ~BIT(g->out_bit);
586 msm_writel_io(val, pctrl, g);
587
588 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
589}
590
591#ifdef CONFIG_DEBUG_FS
592#include <linux/seq_file.h>
593
594static void msm_gpio_dbg_show_one(struct seq_file *s,
595 struct pinctrl_dev *pctldev,
596 struct gpio_chip *chip,
597 unsigned offset,
598 unsigned gpio)
599{
600 const struct msm_pingroup *g;
601 struct msm_pinctrl *pctrl = gpiochip_get_data(chip);
602 unsigned func;
603 int is_out;
604 int drive;
605 int pull;
606 int val;
607 u32 ctl_reg, io_reg;
608
609 static const char * const pulls_keeper[] = {
610 "no pull",
611 "pull down",
612 "keeper",
613 "pull up"
614 };
615
616 static const char * const pulls_no_keeper[] = {
617 "no pull",
618 "pull down",
619 "pull up",
620 };
621
622 if (!gpiochip_line_is_valid(chip, offset))
623 return;
624
625 g = &pctrl->soc->groups[offset];
626 ctl_reg = msm_readl_ctl(pctrl, g);
627 io_reg = msm_readl_io(pctrl, g);
628
629 is_out = !!(ctl_reg & BIT(g->oe_bit));
630 func = (ctl_reg >> g->mux_bit) & 7;
631 drive = (ctl_reg >> g->drv_bit) & 7;
632 pull = (ctl_reg >> g->pull_bit) & 3;
633
634 if (is_out)
635 val = !!(io_reg & BIT(g->out_bit));
636 else
637 val = !!(io_reg & BIT(g->in_bit));
638
639 seq_printf(s, " %-8s: %-3s", g->name, is_out ? "out" : "in");
640 seq_printf(s, " %-4s func%d", val ? "high" : "low", func);
641 seq_printf(s, " %dmA", msm_regval_to_drive(drive));
642 if (pctrl->soc->pull_no_keeper)
643 seq_printf(s, " %s", pulls_no_keeper[pull]);
644 else
645 seq_printf(s, " %s", pulls_keeper[pull]);
646 seq_puts(s, "\n");
647}
648
649static void msm_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
650{
651 unsigned gpio = chip->base;
652 unsigned i;
653
654 for (i = 0; i < chip->ngpio; i++, gpio++)
655 msm_gpio_dbg_show_one(s, NULL, chip, i, gpio);
656}
657
658#else
659#define msm_gpio_dbg_show NULL
660#endif
661
662static int msm_gpio_init_valid_mask(struct gpio_chip *gc,
663 unsigned long *valid_mask,
664 unsigned int ngpios)
665{
666 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
667 int ret;
668 unsigned int len, i;
669 const int *reserved = pctrl->soc->reserved_gpios;
670 u16 *tmp;
671
672
673 if (reserved) {
674 bitmap_fill(valid_mask, ngpios);
675 for (i = 0; reserved[i] >= 0; i++) {
676 if (i >= ngpios || reserved[i] >= ngpios) {
677 dev_err(pctrl->dev, "invalid list of reserved GPIOs\n");
678 return -EINVAL;
679 }
680 clear_bit(reserved[i], valid_mask);
681 }
682
683 return 0;
684 }
685
686
687 len = ret = device_property_count_u16(pctrl->dev, "gpios");
688 if (ret < 0)
689 return 0;
690
691 if (ret > ngpios)
692 return -EINVAL;
693
694 tmp = kmalloc_array(len, sizeof(*tmp), GFP_KERNEL);
695 if (!tmp)
696 return -ENOMEM;
697
698 ret = device_property_read_u16_array(pctrl->dev, "gpios", tmp, len);
699 if (ret < 0) {
700 dev_err(pctrl->dev, "could not read list of GPIOs\n");
701 goto out;
702 }
703
704 bitmap_zero(valid_mask, ngpios);
705 for (i = 0; i < len; i++)
706 set_bit(tmp[i], valid_mask);
707
708out:
709 kfree(tmp);
710 return ret;
711}
712
713static const struct gpio_chip msm_gpio_template = {
714 .direction_input = msm_gpio_direction_input,
715 .direction_output = msm_gpio_direction_output,
716 .get_direction = msm_gpio_get_direction,
717 .get = msm_gpio_get,
718 .set = msm_gpio_set,
719 .request = gpiochip_generic_request,
720 .free = gpiochip_generic_free,
721 .dbg_show = msm_gpio_dbg_show,
722};
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744static void msm_gpio_update_dual_edge_pos(struct msm_pinctrl *pctrl,
745 const struct msm_pingroup *g,
746 struct irq_data *d)
747{
748 int loop_limit = 100;
749 unsigned val, val2, intstat;
750 unsigned pol;
751
752 do {
753 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
754
755 pol = msm_readl_intr_cfg(pctrl, g);
756 pol ^= BIT(g->intr_polarity_bit);
757 msm_writel_intr_cfg(pol, pctrl, g);
758
759 val2 = msm_readl_io(pctrl, g) & BIT(g->in_bit);
760 intstat = msm_readl_intr_status(pctrl, g);
761 if (intstat || (val == val2))
762 return;
763 } while (loop_limit-- > 0);
764 dev_err(pctrl->dev, "dual-edge irq failed to stabilize, %#08x != %#08x\n",
765 val, val2);
766}
767
768static void msm_gpio_irq_mask(struct irq_data *d)
769{
770 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
771 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
772 const struct msm_pingroup *g;
773 unsigned long flags;
774 u32 val;
775
776 if (d->parent_data)
777 irq_chip_mask_parent(d);
778
779 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
780 return;
781
782 g = &pctrl->soc->groups[d->hwirq];
783
784 raw_spin_lock_irqsave(&pctrl->lock, flags);
785
786 val = msm_readl_intr_cfg(pctrl, g);
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807 if (irqd_get_trigger_type(d) & IRQ_TYPE_LEVEL_MASK)
808 val &= ~BIT(g->intr_raw_status_bit);
809
810 val &= ~BIT(g->intr_enable_bit);
811 msm_writel_intr_cfg(val, pctrl, g);
812
813 clear_bit(d->hwirq, pctrl->enabled_irqs);
814
815 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
816}
817
818static void msm_gpio_irq_unmask(struct irq_data *d)
819{
820 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
821 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
822 const struct msm_pingroup *g;
823 unsigned long flags;
824 u32 val;
825
826 if (d->parent_data)
827 irq_chip_unmask_parent(d);
828
829 if (test_bit(d->hwirq, pctrl->skip_wake_irqs))
830 return;
831
832 g = &pctrl->soc->groups[d->hwirq];
833
834 raw_spin_lock_irqsave(&pctrl->lock, flags);
835
836 val = msm_readl_intr_cfg(pctrl, g);
837 val |= BIT(g->intr_raw_status_bit);
838 val |= BIT(g->intr_enable_bit);
839 msm_writel_intr_cfg(val, pctrl, g);
840
841 set_bit(d->hwirq, pctrl->enabled_irqs);
842
843 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
844}
845
846static void msm_gpio_irq_enable(struct irq_data *d)
847{
848 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
849 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
850
851 if (d->parent_data)
852 irq_chip_enable_parent(d);
853
854 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
855 msm_gpio_irq_unmask(d);
856}
857
858static void msm_gpio_irq_disable(struct irq_data *d)
859{
860 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
861 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
862
863 if (d->parent_data)
864 irq_chip_disable_parent(d);
865
866 if (!test_bit(d->hwirq, pctrl->skip_wake_irqs))
867 msm_gpio_irq_mask(d);
868}
869
870
871
872
873
874
875
876
877
878
879static void msm_gpio_update_dual_edge_parent(struct irq_data *d)
880{
881 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
882 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
883 const struct msm_pingroup *g = &pctrl->soc->groups[d->hwirq];
884 int loop_limit = 100;
885 unsigned int val;
886 unsigned int type;
887
888
889 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
890 type = val ? IRQ_TYPE_EDGE_FALLING : IRQ_TYPE_EDGE_RISING;
891
892 do {
893
894 irq_chip_set_type_parent(d, type);
895
896
897
898
899
900
901
902 val = msm_readl_io(pctrl, g) & BIT(g->in_bit);
903 if (type == IRQ_TYPE_EDGE_RISING) {
904 if (!val)
905 return;
906 type = IRQ_TYPE_EDGE_FALLING;
907 } else if (type == IRQ_TYPE_EDGE_FALLING) {
908 if (val)
909 return;
910 type = IRQ_TYPE_EDGE_RISING;
911 }
912 } while (loop_limit-- > 0);
913 dev_warn_once(pctrl->dev, "dual-edge irq failed to stabilize\n");
914}
915
916static void msm_gpio_irq_ack(struct irq_data *d)
917{
918 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
919 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
920 const struct msm_pingroup *g;
921 unsigned long flags;
922
923 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
924 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
925 msm_gpio_update_dual_edge_parent(d);
926 return;
927 }
928
929 g = &pctrl->soc->groups[d->hwirq];
930
931 raw_spin_lock_irqsave(&pctrl->lock, flags);
932
933 msm_ack_intr_status(pctrl, g);
934
935 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
936 msm_gpio_update_dual_edge_pos(pctrl, g, d);
937
938 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
939}
940
941static bool msm_gpio_needs_dual_edge_parent_workaround(struct irq_data *d,
942 unsigned int type)
943{
944 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
945 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
946
947 return type == IRQ_TYPE_EDGE_BOTH &&
948 pctrl->soc->wakeirq_dual_edge_errata && d->parent_data &&
949 test_bit(d->hwirq, pctrl->skip_wake_irqs);
950}
951
952static int msm_gpio_irq_set_type(struct irq_data *d, unsigned int type)
953{
954 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
955 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
956 const struct msm_pingroup *g;
957 unsigned long flags;
958 bool was_enabled;
959 u32 val;
960
961 if (msm_gpio_needs_dual_edge_parent_workaround(d, type)) {
962 set_bit(d->hwirq, pctrl->dual_edge_irqs);
963 irq_set_handler_locked(d, handle_fasteoi_ack_irq);
964 msm_gpio_update_dual_edge_parent(d);
965 return 0;
966 }
967
968 if (d->parent_data)
969 irq_chip_set_type_parent(d, type);
970
971 if (test_bit(d->hwirq, pctrl->skip_wake_irqs)) {
972 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
973 irq_set_handler_locked(d, handle_fasteoi_irq);
974 return 0;
975 }
976
977 g = &pctrl->soc->groups[d->hwirq];
978
979 raw_spin_lock_irqsave(&pctrl->lock, flags);
980
981
982
983
984 if (g->intr_detection_width == 1 && type == IRQ_TYPE_EDGE_BOTH)
985 set_bit(d->hwirq, pctrl->dual_edge_irqs);
986 else
987 clear_bit(d->hwirq, pctrl->dual_edge_irqs);
988
989
990
991
992
993 if (pctrl->intr_target_use_scm) {
994 u32 addr = pctrl->phys_base[0] + g->intr_target_reg;
995 int ret;
996
997 qcom_scm_io_readl(addr, &val);
998
999 val &= ~(7 << g->intr_target_bit);
1000 val |= g->intr_target_kpss_val << g->intr_target_bit;
1001
1002 ret = qcom_scm_io_writel(addr, val);
1003 if (ret)
1004 dev_err(pctrl->dev,
1005 "Failed routing %lu interrupt to Apps proc",
1006 d->hwirq);
1007 } else {
1008 val = msm_readl_intr_target(pctrl, g);
1009 val &= ~(7 << g->intr_target_bit);
1010 val |= g->intr_target_kpss_val << g->intr_target_bit;
1011 msm_writel_intr_target(val, pctrl, g);
1012 }
1013
1014
1015
1016
1017
1018
1019 val = msm_readl_intr_cfg(pctrl, g);
1020 was_enabled = val & BIT(g->intr_raw_status_bit);
1021 val |= BIT(g->intr_raw_status_bit);
1022 if (g->intr_detection_width == 2) {
1023 val &= ~(3 << g->intr_detection_bit);
1024 val &= ~(1 << g->intr_polarity_bit);
1025 switch (type) {
1026 case IRQ_TYPE_EDGE_RISING:
1027 val |= 1 << g->intr_detection_bit;
1028 val |= BIT(g->intr_polarity_bit);
1029 break;
1030 case IRQ_TYPE_EDGE_FALLING:
1031 val |= 2 << g->intr_detection_bit;
1032 val |= BIT(g->intr_polarity_bit);
1033 break;
1034 case IRQ_TYPE_EDGE_BOTH:
1035 val |= 3 << g->intr_detection_bit;
1036 val |= BIT(g->intr_polarity_bit);
1037 break;
1038 case IRQ_TYPE_LEVEL_LOW:
1039 break;
1040 case IRQ_TYPE_LEVEL_HIGH:
1041 val |= BIT(g->intr_polarity_bit);
1042 break;
1043 }
1044 } else if (g->intr_detection_width == 1) {
1045 val &= ~(1 << g->intr_detection_bit);
1046 val &= ~(1 << g->intr_polarity_bit);
1047 switch (type) {
1048 case IRQ_TYPE_EDGE_RISING:
1049 val |= BIT(g->intr_detection_bit);
1050 val |= BIT(g->intr_polarity_bit);
1051 break;
1052 case IRQ_TYPE_EDGE_FALLING:
1053 val |= BIT(g->intr_detection_bit);
1054 break;
1055 case IRQ_TYPE_EDGE_BOTH:
1056 val |= BIT(g->intr_detection_bit);
1057 val |= BIT(g->intr_polarity_bit);
1058 break;
1059 case IRQ_TYPE_LEVEL_LOW:
1060 break;
1061 case IRQ_TYPE_LEVEL_HIGH:
1062 val |= BIT(g->intr_polarity_bit);
1063 break;
1064 }
1065 } else {
1066 BUG();
1067 }
1068 msm_writel_intr_cfg(val, pctrl, g);
1069
1070
1071
1072
1073
1074
1075 if (!was_enabled)
1076 msm_ack_intr_status(pctrl, g);
1077
1078 if (test_bit(d->hwirq, pctrl->dual_edge_irqs))
1079 msm_gpio_update_dual_edge_pos(pctrl, g, d);
1080
1081 raw_spin_unlock_irqrestore(&pctrl->lock, flags);
1082
1083 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
1084 irq_set_handler_locked(d, handle_level_irq);
1085 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
1086 irq_set_handler_locked(d, handle_edge_irq);
1087
1088 return 0;
1089}
1090
1091static int msm_gpio_irq_set_wake(struct irq_data *d, unsigned int on)
1092{
1093 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1094 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1095
1096
1097
1098
1099
1100
1101
1102 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1103 return irq_chip_set_wake_parent(d, on);
1104
1105 return irq_set_irq_wake(pctrl->irq, on);
1106}
1107
1108static int msm_gpio_irq_reqres(struct irq_data *d)
1109{
1110 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1111 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1112 int ret;
1113
1114 if (!try_module_get(gc->owner))
1115 return -ENODEV;
1116
1117 ret = msm_pinmux_request_gpio(pctrl->pctrl, NULL, d->hwirq);
1118 if (ret)
1119 goto out;
1120 msm_gpio_direction_input(gc, d->hwirq);
1121
1122 if (gpiochip_lock_as_irq(gc, d->hwirq)) {
1123 dev_err(gc->parent,
1124 "unable to lock HW IRQ %lu for IRQ\n",
1125 d->hwirq);
1126 ret = -EINVAL;
1127 goto out;
1128 }
1129
1130
1131
1132
1133
1134
1135 irq_set_status_flags(d->irq, IRQ_DISABLE_UNLAZY);
1136
1137 return 0;
1138out:
1139 module_put(gc->owner);
1140 return ret;
1141}
1142
1143static void msm_gpio_irq_relres(struct irq_data *d)
1144{
1145 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1146
1147 gpiochip_unlock_as_irq(gc, d->hwirq);
1148 module_put(gc->owner);
1149}
1150
1151static int msm_gpio_irq_set_affinity(struct irq_data *d,
1152 const struct cpumask *dest, bool force)
1153{
1154 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1155 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1156
1157 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1158 return irq_chip_set_affinity_parent(d, dest, force);
1159
1160 return 0;
1161}
1162
1163static int msm_gpio_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu_info)
1164{
1165 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1166 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1167
1168 if (d->parent_data && test_bit(d->hwirq, pctrl->skip_wake_irqs))
1169 return irq_chip_set_vcpu_affinity_parent(d, vcpu_info);
1170
1171 return 0;
1172}
1173
1174static void msm_gpio_irq_handler(struct irq_desc *desc)
1175{
1176 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
1177 const struct msm_pingroup *g;
1178 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1179 struct irq_chip *chip = irq_desc_get_chip(desc);
1180 int irq_pin;
1181 int handled = 0;
1182 u32 val;
1183 int i;
1184
1185 chained_irq_enter(chip, desc);
1186
1187
1188
1189
1190
1191 for_each_set_bit(i, pctrl->enabled_irqs, pctrl->chip.ngpio) {
1192 g = &pctrl->soc->groups[i];
1193 val = msm_readl_intr_status(pctrl, g);
1194 if (val & BIT(g->intr_status_bit)) {
1195 irq_pin = irq_find_mapping(gc->irq.domain, i);
1196 generic_handle_irq(irq_pin);
1197 handled++;
1198 }
1199 }
1200
1201
1202 if (handled == 0)
1203 handle_bad_irq(desc);
1204
1205 chained_irq_exit(chip, desc);
1206}
1207
1208static int msm_gpio_wakeirq(struct gpio_chip *gc,
1209 unsigned int child,
1210 unsigned int child_type,
1211 unsigned int *parent,
1212 unsigned int *parent_type)
1213{
1214 struct msm_pinctrl *pctrl = gpiochip_get_data(gc);
1215 const struct msm_gpio_wakeirq_map *map;
1216 int i;
1217
1218 *parent = GPIO_NO_WAKE_IRQ;
1219 *parent_type = IRQ_TYPE_EDGE_RISING;
1220
1221 for (i = 0; i < pctrl->soc->nwakeirq_map; i++) {
1222 map = &pctrl->soc->wakeirq_map[i];
1223 if (map->gpio == child) {
1224 *parent = map->wakeirq;
1225 break;
1226 }
1227 }
1228
1229 return 0;
1230}
1231
1232static bool msm_gpio_needs_valid_mask(struct msm_pinctrl *pctrl)
1233{
1234 if (pctrl->soc->reserved_gpios)
1235 return true;
1236
1237 return device_property_count_u16(pctrl->dev, "gpios") > 0;
1238}
1239
1240static int msm_gpio_init(struct msm_pinctrl *pctrl)
1241{
1242 struct gpio_chip *chip;
1243 struct gpio_irq_chip *girq;
1244 int i, ret;
1245 unsigned gpio, ngpio = pctrl->soc->ngpios;
1246 struct device_node *np;
1247 bool skip;
1248
1249 if (WARN_ON(ngpio > MAX_NR_GPIO))
1250 return -EINVAL;
1251
1252 chip = &pctrl->chip;
1253 chip->base = -1;
1254 chip->ngpio = ngpio;
1255 chip->label = dev_name(pctrl->dev);
1256 chip->parent = pctrl->dev;
1257 chip->owner = THIS_MODULE;
1258 chip->of_node = pctrl->dev->of_node;
1259 if (msm_gpio_needs_valid_mask(pctrl))
1260 chip->init_valid_mask = msm_gpio_init_valid_mask;
1261
1262 pctrl->irq_chip.name = "msmgpio";
1263 pctrl->irq_chip.irq_enable = msm_gpio_irq_enable;
1264 pctrl->irq_chip.irq_disable = msm_gpio_irq_disable;
1265 pctrl->irq_chip.irq_mask = msm_gpio_irq_mask;
1266 pctrl->irq_chip.irq_unmask = msm_gpio_irq_unmask;
1267 pctrl->irq_chip.irq_ack = msm_gpio_irq_ack;
1268 pctrl->irq_chip.irq_set_type = msm_gpio_irq_set_type;
1269 pctrl->irq_chip.irq_set_wake = msm_gpio_irq_set_wake;
1270 pctrl->irq_chip.irq_request_resources = msm_gpio_irq_reqres;
1271 pctrl->irq_chip.irq_release_resources = msm_gpio_irq_relres;
1272 pctrl->irq_chip.irq_set_affinity = msm_gpio_irq_set_affinity;
1273 pctrl->irq_chip.irq_set_vcpu_affinity = msm_gpio_irq_set_vcpu_affinity;
1274 pctrl->irq_chip.flags = IRQCHIP_MASK_ON_SUSPEND |
1275 IRQCHIP_SET_TYPE_MASKED |
1276 IRQCHIP_ENABLE_WAKEUP_ON_SUSPEND;
1277
1278 np = of_parse_phandle(pctrl->dev->of_node, "wakeup-parent", 0);
1279 if (np) {
1280 chip->irq.parent_domain = irq_find_matching_host(np,
1281 DOMAIN_BUS_WAKEUP);
1282 of_node_put(np);
1283 if (!chip->irq.parent_domain)
1284 return -EPROBE_DEFER;
1285 chip->irq.child_to_parent_hwirq = msm_gpio_wakeirq;
1286 pctrl->irq_chip.irq_eoi = irq_chip_eoi_parent;
1287
1288
1289
1290
1291 skip = irq_domain_qcom_handle_wakeup(chip->irq.parent_domain);
1292 for (i = 0; skip && i < pctrl->soc->nwakeirq_map; i++) {
1293 gpio = pctrl->soc->wakeirq_map[i].gpio;
1294 set_bit(gpio, pctrl->skip_wake_irqs);
1295 }
1296 }
1297
1298 girq = &chip->irq;
1299 girq->chip = &pctrl->irq_chip;
1300 girq->parent_handler = msm_gpio_irq_handler;
1301 girq->fwnode = pctrl->dev->fwnode;
1302 girq->num_parents = 1;
1303 girq->parents = devm_kcalloc(pctrl->dev, 1, sizeof(*girq->parents),
1304 GFP_KERNEL);
1305 if (!girq->parents)
1306 return -ENOMEM;
1307 girq->default_type = IRQ_TYPE_NONE;
1308 girq->handler = handle_bad_irq;
1309 girq->parents[0] = pctrl->irq;
1310
1311 ret = gpiochip_add_data(&pctrl->chip, pctrl);
1312 if (ret) {
1313 dev_err(pctrl->dev, "Failed register gpiochip\n");
1314 return ret;
1315 }
1316
1317
1318
1319
1320
1321
1322
1323
1324
1325
1326
1327 if (!of_property_read_bool(pctrl->dev->of_node, "gpio-ranges")) {
1328 ret = gpiochip_add_pin_range(&pctrl->chip,
1329 dev_name(pctrl->dev), 0, 0, chip->ngpio);
1330 if (ret) {
1331 dev_err(pctrl->dev, "Failed to add pin range\n");
1332 gpiochip_remove(&pctrl->chip);
1333 return ret;
1334 }
1335 }
1336
1337 return 0;
1338}
1339
1340static int msm_ps_hold_restart(struct notifier_block *nb, unsigned long action,
1341 void *data)
1342{
1343 struct msm_pinctrl *pctrl = container_of(nb, struct msm_pinctrl, restart_nb);
1344
1345 writel(0, pctrl->regs[0] + PS_HOLD_OFFSET);
1346 mdelay(1000);
1347 return NOTIFY_DONE;
1348}
1349
1350static struct msm_pinctrl *poweroff_pctrl;
1351
1352static void msm_ps_hold_poweroff(void)
1353{
1354 msm_ps_hold_restart(&poweroff_pctrl->restart_nb, 0, NULL);
1355}
1356
1357static void msm_pinctrl_setup_pm_reset(struct msm_pinctrl *pctrl)
1358{
1359 int i;
1360 const struct msm_function *func = pctrl->soc->functions;
1361
1362 for (i = 0; i < pctrl->soc->nfunctions; i++)
1363 if (!strcmp(func[i].name, "ps_hold")) {
1364 pctrl->restart_nb.notifier_call = msm_ps_hold_restart;
1365 pctrl->restart_nb.priority = 128;
1366 if (register_restart_handler(&pctrl->restart_nb))
1367 dev_err(pctrl->dev,
1368 "failed to setup restart handler.\n");
1369 poweroff_pctrl = pctrl;
1370 pm_power_off = msm_ps_hold_poweroff;
1371 break;
1372 }
1373}
1374
1375static __maybe_unused int msm_pinctrl_suspend(struct device *dev)
1376{
1377 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1378
1379 return pinctrl_force_sleep(pctrl->pctrl);
1380}
1381
1382static __maybe_unused int msm_pinctrl_resume(struct device *dev)
1383{
1384 struct msm_pinctrl *pctrl = dev_get_drvdata(dev);
1385
1386 return pinctrl_force_default(pctrl->pctrl);
1387}
1388
1389SIMPLE_DEV_PM_OPS(msm_pinctrl_dev_pm_ops, msm_pinctrl_suspend,
1390 msm_pinctrl_resume);
1391
1392EXPORT_SYMBOL(msm_pinctrl_dev_pm_ops);
1393
1394int msm_pinctrl_probe(struct platform_device *pdev,
1395 const struct msm_pinctrl_soc_data *soc_data)
1396{
1397 struct msm_pinctrl *pctrl;
1398 struct resource *res;
1399 int ret;
1400 int i;
1401
1402 pctrl = devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL);
1403 if (!pctrl)
1404 return -ENOMEM;
1405
1406 pctrl->dev = &pdev->dev;
1407 pctrl->soc = soc_data;
1408 pctrl->chip = msm_gpio_template;
1409 pctrl->intr_target_use_scm = of_device_is_compatible(
1410 pctrl->dev->of_node,
1411 "qcom,ipq8064-pinctrl");
1412
1413 raw_spin_lock_init(&pctrl->lock);
1414
1415 if (soc_data->tiles) {
1416 for (i = 0; i < soc_data->ntiles; i++) {
1417 res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1418 soc_data->tiles[i]);
1419 pctrl->regs[i] = devm_ioremap_resource(&pdev->dev, res);
1420 if (IS_ERR(pctrl->regs[i]))
1421 return PTR_ERR(pctrl->regs[i]);
1422 }
1423 } else {
1424 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1425 pctrl->regs[0] = devm_ioremap_resource(&pdev->dev, res);
1426 if (IS_ERR(pctrl->regs[0]))
1427 return PTR_ERR(pctrl->regs[0]);
1428
1429 pctrl->phys_base[0] = res->start;
1430 }
1431
1432 msm_pinctrl_setup_pm_reset(pctrl);
1433
1434 pctrl->irq = platform_get_irq(pdev, 0);
1435 if (pctrl->irq < 0)
1436 return pctrl->irq;
1437
1438 pctrl->desc.owner = THIS_MODULE;
1439 pctrl->desc.pctlops = &msm_pinctrl_ops;
1440 pctrl->desc.pmxops = &msm_pinmux_ops;
1441 pctrl->desc.confops = &msm_pinconf_ops;
1442 pctrl->desc.name = dev_name(&pdev->dev);
1443 pctrl->desc.pins = pctrl->soc->pins;
1444 pctrl->desc.npins = pctrl->soc->npins;
1445
1446 pctrl->pctrl = devm_pinctrl_register(&pdev->dev, &pctrl->desc, pctrl);
1447 if (IS_ERR(pctrl->pctrl)) {
1448 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
1449 return PTR_ERR(pctrl->pctrl);
1450 }
1451
1452 ret = msm_gpio_init(pctrl);
1453 if (ret)
1454 return ret;
1455
1456 platform_set_drvdata(pdev, pctrl);
1457
1458 dev_dbg(&pdev->dev, "Probed Qualcomm pinctrl driver\n");
1459
1460 return 0;
1461}
1462EXPORT_SYMBOL(msm_pinctrl_probe);
1463
1464int msm_pinctrl_remove(struct platform_device *pdev)
1465{
1466 struct msm_pinctrl *pctrl = platform_get_drvdata(pdev);
1467
1468 gpiochip_remove(&pctrl->chip);
1469
1470 unregister_restart_handler(&pctrl->restart_nb);
1471
1472 return 0;
1473}
1474EXPORT_SYMBOL(msm_pinctrl_remove);
1475
1476MODULE_DESCRIPTION("Qualcomm Technologies, Inc. TLMM driver");
1477MODULE_LICENSE("GPL v2");
1478