linux/drivers/pinctrl/pinctrl-sx150x.c
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   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Copyright (c) 2016, BayLibre, SAS. All rights reserved.
   4 * Author: Neil Armstrong <narmstrong@baylibre.com>
   5 *
   6 * Copyright (c) 2010, Code Aurora Forum. All rights reserved.
   7 *
   8 * Driver for Semtech SX150X I2C GPIO Expanders
   9 * The handling of the 4-bit chips (SX1501/SX1504/SX1507) is untested.
  10 *
  11 * Author: Gregory Bean <gbean@codeaurora.org>
  12 */
  13
  14#include <linux/regmap.h>
  15#include <linux/i2c.h>
  16#include <linux/init.h>
  17#include <linux/interrupt.h>
  18#include <linux/irq.h>
  19#include <linux/mutex.h>
  20#include <linux/slab.h>
  21#include <linux/of.h>
  22#include <linux/of_device.h>
  23#include <linux/gpio/driver.h>
  24#include <linux/pinctrl/pinconf.h>
  25#include <linux/pinctrl/pinctrl.h>
  26#include <linux/pinctrl/pinmux.h>
  27#include <linux/pinctrl/pinconf-generic.h>
  28
  29#include "core.h"
  30#include "pinconf.h"
  31#include "pinctrl-utils.h"
  32
  33/* The chip models of sx150x */
  34enum {
  35        SX150X_123 = 0,
  36        SX150X_456,
  37        SX150X_789,
  38};
  39enum {
  40        SX150X_789_REG_MISC_AUTOCLEAR_OFF = 1 << 0,
  41        SX150X_MAX_REGISTER = 0xad,
  42        SX150X_IRQ_TYPE_EDGE_RISING = 0x1,
  43        SX150X_IRQ_TYPE_EDGE_FALLING = 0x2,
  44        SX150X_789_RESET_KEY1 = 0x12,
  45        SX150X_789_RESET_KEY2 = 0x34,
  46};
  47
  48struct sx150x_123_pri {
  49        u8 reg_pld_mode;
  50        u8 reg_pld_table0;
  51        u8 reg_pld_table1;
  52        u8 reg_pld_table2;
  53        u8 reg_pld_table3;
  54        u8 reg_pld_table4;
  55        u8 reg_advanced;
  56};
  57
  58struct sx150x_456_pri {
  59        u8 reg_pld_mode;
  60        u8 reg_pld_table0;
  61        u8 reg_pld_table1;
  62        u8 reg_pld_table2;
  63        u8 reg_pld_table3;
  64        u8 reg_pld_table4;
  65        u8 reg_advanced;
  66};
  67
  68struct sx150x_789_pri {
  69        u8 reg_drain;
  70        u8 reg_polarity;
  71        u8 reg_clock;
  72        u8 reg_misc;
  73        u8 reg_reset;
  74        u8 ngpios;
  75};
  76
  77struct sx150x_device_data {
  78        u8 model;
  79        u8 reg_pullup;
  80        u8 reg_pulldn;
  81        u8 reg_dir;
  82        u8 reg_data;
  83        u8 reg_irq_mask;
  84        u8 reg_irq_src;
  85        u8 reg_sense;
  86        u8 ngpios;
  87        union {
  88                struct sx150x_123_pri x123;
  89                struct sx150x_456_pri x456;
  90                struct sx150x_789_pri x789;
  91        } pri;
  92        const struct pinctrl_pin_desc *pins;
  93        unsigned int npins;
  94};
  95
  96struct sx150x_pinctrl {
  97        struct device *dev;
  98        struct i2c_client *client;
  99        struct pinctrl_dev *pctldev;
 100        struct pinctrl_desc pinctrl_desc;
 101        struct gpio_chip gpio;
 102        struct irq_chip irq_chip;
 103        struct regmap *regmap;
 104        struct {
 105                u32 sense;
 106                u32 masked;
 107        } irq;
 108        struct mutex lock;
 109        const struct sx150x_device_data *data;
 110};
 111
 112static const struct pinctrl_pin_desc sx150x_4_pins[] = {
 113        PINCTRL_PIN(0, "gpio0"),
 114        PINCTRL_PIN(1, "gpio1"),
 115        PINCTRL_PIN(2, "gpio2"),
 116        PINCTRL_PIN(3, "gpio3"),
 117        PINCTRL_PIN(4, "oscio"),
 118};
 119
 120static const struct pinctrl_pin_desc sx150x_8_pins[] = {
 121        PINCTRL_PIN(0, "gpio0"),
 122        PINCTRL_PIN(1, "gpio1"),
 123        PINCTRL_PIN(2, "gpio2"),
 124        PINCTRL_PIN(3, "gpio3"),
 125        PINCTRL_PIN(4, "gpio4"),
 126        PINCTRL_PIN(5, "gpio5"),
 127        PINCTRL_PIN(6, "gpio6"),
 128        PINCTRL_PIN(7, "gpio7"),
 129        PINCTRL_PIN(8, "oscio"),
 130};
 131
 132static const struct pinctrl_pin_desc sx150x_16_pins[] = {
 133        PINCTRL_PIN(0, "gpio0"),
 134        PINCTRL_PIN(1, "gpio1"),
 135        PINCTRL_PIN(2, "gpio2"),
 136        PINCTRL_PIN(3, "gpio3"),
 137        PINCTRL_PIN(4, "gpio4"),
 138        PINCTRL_PIN(5, "gpio5"),
 139        PINCTRL_PIN(6, "gpio6"),
 140        PINCTRL_PIN(7, "gpio7"),
 141        PINCTRL_PIN(8, "gpio8"),
 142        PINCTRL_PIN(9, "gpio9"),
 143        PINCTRL_PIN(10, "gpio10"),
 144        PINCTRL_PIN(11, "gpio11"),
 145        PINCTRL_PIN(12, "gpio12"),
 146        PINCTRL_PIN(13, "gpio13"),
 147        PINCTRL_PIN(14, "gpio14"),
 148        PINCTRL_PIN(15, "gpio15"),
 149        PINCTRL_PIN(16, "oscio"),
 150};
 151
 152static const struct sx150x_device_data sx1501q_device_data = {
 153        .model = SX150X_123,
 154        .reg_pullup     = 0x02,
 155        .reg_pulldn     = 0x03,
 156        .reg_dir        = 0x01,
 157        .reg_data       = 0x00,
 158        .reg_irq_mask   = 0x05,
 159        .reg_irq_src    = 0x08,
 160        .reg_sense      = 0x07,
 161        .pri.x123 = {
 162                .reg_pld_mode   = 0x10,
 163                .reg_pld_table0 = 0x11,
 164                .reg_pld_table2 = 0x13,
 165                .reg_advanced   = 0xad,
 166        },
 167        .ngpios = 4,
 168        .pins = sx150x_4_pins,
 169        .npins = 4, /* oscio not available */
 170};
 171
 172static const struct sx150x_device_data sx1502q_device_data = {
 173        .model = SX150X_123,
 174        .reg_pullup     = 0x02,
 175        .reg_pulldn     = 0x03,
 176        .reg_dir        = 0x01,
 177        .reg_data       = 0x00,
 178        .reg_irq_mask   = 0x05,
 179        .reg_irq_src    = 0x08,
 180        .reg_sense      = 0x06,
 181        .pri.x123 = {
 182                .reg_pld_mode   = 0x10,
 183                .reg_pld_table0 = 0x11,
 184                .reg_pld_table1 = 0x12,
 185                .reg_pld_table2 = 0x13,
 186                .reg_pld_table3 = 0x14,
 187                .reg_pld_table4 = 0x15,
 188                .reg_advanced   = 0xad,
 189        },
 190        .ngpios = 8,
 191        .pins = sx150x_8_pins,
 192        .npins = 8, /* oscio not available */
 193};
 194
 195static const struct sx150x_device_data sx1503q_device_data = {
 196        .model = SX150X_123,
 197        .reg_pullup     = 0x04,
 198        .reg_pulldn     = 0x06,
 199        .reg_dir        = 0x02,
 200        .reg_data       = 0x00,
 201        .reg_irq_mask   = 0x08,
 202        .reg_irq_src    = 0x0e,
 203        .reg_sense      = 0x0a,
 204        .pri.x123 = {
 205                .reg_pld_mode   = 0x20,
 206                .reg_pld_table0 = 0x22,
 207                .reg_pld_table1 = 0x24,
 208                .reg_pld_table2 = 0x26,
 209                .reg_pld_table3 = 0x28,
 210                .reg_pld_table4 = 0x2a,
 211                .reg_advanced   = 0xad,
 212        },
 213        .ngpios = 16,
 214        .pins = sx150x_16_pins,
 215        .npins  = 16, /* oscio not available */
 216};
 217
 218static const struct sx150x_device_data sx1504q_device_data = {
 219        .model = SX150X_456,
 220        .reg_pullup     = 0x02,
 221        .reg_pulldn     = 0x03,
 222        .reg_dir        = 0x01,
 223        .reg_data       = 0x00,
 224        .reg_irq_mask   = 0x05,
 225        .reg_irq_src    = 0x08,
 226        .reg_sense      = 0x07,
 227        .pri.x456 = {
 228                .reg_pld_mode   = 0x10,
 229                .reg_pld_table0 = 0x11,
 230                .reg_pld_table2 = 0x13,
 231        },
 232        .ngpios = 4,
 233        .pins = sx150x_4_pins,
 234        .npins = 4, /* oscio not available */
 235};
 236
 237static const struct sx150x_device_data sx1505q_device_data = {
 238        .model = SX150X_456,
 239        .reg_pullup     = 0x02,
 240        .reg_pulldn     = 0x03,
 241        .reg_dir        = 0x01,
 242        .reg_data       = 0x00,
 243        .reg_irq_mask   = 0x05,
 244        .reg_irq_src    = 0x08,
 245        .reg_sense      = 0x06,
 246        .pri.x456 = {
 247                .reg_pld_mode   = 0x10,
 248                .reg_pld_table0 = 0x11,
 249                .reg_pld_table1 = 0x12,
 250                .reg_pld_table2 = 0x13,
 251                .reg_pld_table3 = 0x14,
 252                .reg_pld_table4 = 0x15,
 253        },
 254        .ngpios = 8,
 255        .pins = sx150x_8_pins,
 256        .npins = 8, /* oscio not available */
 257};
 258
 259static const struct sx150x_device_data sx1506q_device_data = {
 260        .model = SX150X_456,
 261        .reg_pullup     = 0x04,
 262        .reg_pulldn     = 0x06,
 263        .reg_dir        = 0x02,
 264        .reg_data       = 0x00,
 265        .reg_irq_mask   = 0x08,
 266        .reg_irq_src    = 0x0e,
 267        .reg_sense      = 0x0a,
 268        .pri.x456 = {
 269                .reg_pld_mode   = 0x20,
 270                .reg_pld_table0 = 0x22,
 271                .reg_pld_table1 = 0x24,
 272                .reg_pld_table2 = 0x26,
 273                .reg_pld_table3 = 0x28,
 274                .reg_pld_table4 = 0x2a,
 275                .reg_advanced   = 0xad,
 276        },
 277        .ngpios = 16,
 278        .pins = sx150x_16_pins,
 279        .npins = 16, /* oscio not available */
 280};
 281
 282static const struct sx150x_device_data sx1507q_device_data = {
 283        .model = SX150X_789,
 284        .reg_pullup     = 0x03,
 285        .reg_pulldn     = 0x04,
 286        .reg_dir        = 0x07,
 287        .reg_data       = 0x08,
 288        .reg_irq_mask   = 0x09,
 289        .reg_irq_src    = 0x0b,
 290        .reg_sense      = 0x0a,
 291        .pri.x789 = {
 292                .reg_drain      = 0x05,
 293                .reg_polarity   = 0x06,
 294                .reg_clock      = 0x0d,
 295                .reg_misc       = 0x0e,
 296                .reg_reset      = 0x7d,
 297        },
 298        .ngpios = 4,
 299        .pins = sx150x_4_pins,
 300        .npins = ARRAY_SIZE(sx150x_4_pins),
 301};
 302
 303static const struct sx150x_device_data sx1508q_device_data = {
 304        .model = SX150X_789,
 305        .reg_pullup     = 0x03,
 306        .reg_pulldn     = 0x04,
 307        .reg_dir        = 0x07,
 308        .reg_data       = 0x08,
 309        .reg_irq_mask   = 0x09,
 310        .reg_irq_src    = 0x0c,
 311        .reg_sense      = 0x0a,
 312        .pri.x789 = {
 313                .reg_drain      = 0x05,
 314                .reg_polarity   = 0x06,
 315                .reg_clock      = 0x0f,
 316                .reg_misc       = 0x10,
 317                .reg_reset      = 0x7d,
 318        },
 319        .ngpios = 8,
 320        .pins = sx150x_8_pins,
 321        .npins = ARRAY_SIZE(sx150x_8_pins),
 322};
 323
 324static const struct sx150x_device_data sx1509q_device_data = {
 325        .model = SX150X_789,
 326        .reg_pullup     = 0x06,
 327        .reg_pulldn     = 0x08,
 328        .reg_dir        = 0x0e,
 329        .reg_data       = 0x10,
 330        .reg_irq_mask   = 0x12,
 331        .reg_irq_src    = 0x18,
 332        .reg_sense      = 0x14,
 333        .pri.x789 = {
 334                .reg_drain      = 0x0a,
 335                .reg_polarity   = 0x0c,
 336                .reg_clock      = 0x1e,
 337                .reg_misc       = 0x1f,
 338                .reg_reset      = 0x7d,
 339        },
 340        .ngpios = 16,
 341        .pins = sx150x_16_pins,
 342        .npins = ARRAY_SIZE(sx150x_16_pins),
 343};
 344
 345static int sx150x_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 346{
 347        return 0;
 348}
 349
 350static const char *sx150x_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
 351                                                unsigned int group)
 352{
 353        return NULL;
 354}
 355
 356static int sx150x_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
 357                                        unsigned int group,
 358                                        const unsigned int **pins,
 359                                        unsigned int *num_pins)
 360{
 361        return -ENOTSUPP;
 362}
 363
 364static const struct pinctrl_ops sx150x_pinctrl_ops = {
 365        .get_groups_count = sx150x_pinctrl_get_groups_count,
 366        .get_group_name = sx150x_pinctrl_get_group_name,
 367        .get_group_pins = sx150x_pinctrl_get_group_pins,
 368#ifdef CONFIG_OF
 369        .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
 370        .dt_free_map = pinctrl_utils_free_map,
 371#endif
 372};
 373
 374static bool sx150x_pin_is_oscio(struct sx150x_pinctrl *pctl, unsigned int pin)
 375{
 376        if (pin >= pctl->data->npins)
 377                return false;
 378
 379        /* OSCIO pin is only present in 789 devices */
 380        if (pctl->data->model != SX150X_789)
 381                return false;
 382
 383        return !strcmp(pctl->data->pins[pin].name, "oscio");
 384}
 385
 386static int sx150x_gpio_get_direction(struct gpio_chip *chip,
 387                                      unsigned int offset)
 388{
 389        struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
 390        unsigned int value;
 391        int ret;
 392
 393        if (sx150x_pin_is_oscio(pctl, offset))
 394                return GPIO_LINE_DIRECTION_OUT;
 395
 396        ret = regmap_read(pctl->regmap, pctl->data->reg_dir, &value);
 397        if (ret < 0)
 398                return ret;
 399
 400        if (value & BIT(offset))
 401                return GPIO_LINE_DIRECTION_IN;
 402
 403        return GPIO_LINE_DIRECTION_OUT;
 404}
 405
 406static int sx150x_gpio_get(struct gpio_chip *chip, unsigned int offset)
 407{
 408        struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
 409        unsigned int value;
 410        int ret;
 411
 412        if (sx150x_pin_is_oscio(pctl, offset))
 413                return -EINVAL;
 414
 415        ret = regmap_read(pctl->regmap, pctl->data->reg_data, &value);
 416        if (ret < 0)
 417                return ret;
 418
 419        return !!(value & BIT(offset));
 420}
 421
 422static int __sx150x_gpio_set(struct sx150x_pinctrl *pctl, unsigned int offset,
 423                             int value)
 424{
 425        return regmap_write_bits(pctl->regmap, pctl->data->reg_data,
 426                                 BIT(offset), value ? BIT(offset) : 0);
 427}
 428
 429static int sx150x_gpio_oscio_set(struct sx150x_pinctrl *pctl,
 430                                 int value)
 431{
 432        return regmap_write(pctl->regmap,
 433                            pctl->data->pri.x789.reg_clock,
 434                            (value ? 0x1f : 0x10));
 435}
 436
 437static void sx150x_gpio_set(struct gpio_chip *chip, unsigned int offset,
 438                            int value)
 439{
 440        struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
 441
 442        if (sx150x_pin_is_oscio(pctl, offset))
 443                sx150x_gpio_oscio_set(pctl, value);
 444        else
 445                __sx150x_gpio_set(pctl, offset, value);
 446}
 447
 448static void sx150x_gpio_set_multiple(struct gpio_chip *chip,
 449                                     unsigned long *mask,
 450                                     unsigned long *bits)
 451{
 452        struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
 453
 454        regmap_write_bits(pctl->regmap, pctl->data->reg_data, *mask, *bits);
 455}
 456
 457static int sx150x_gpio_direction_input(struct gpio_chip *chip,
 458                                       unsigned int offset)
 459{
 460        struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
 461
 462        if (sx150x_pin_is_oscio(pctl, offset))
 463                return -EINVAL;
 464
 465        return regmap_write_bits(pctl->regmap,
 466                                 pctl->data->reg_dir,
 467                                 BIT(offset), BIT(offset));
 468}
 469
 470static int sx150x_gpio_direction_output(struct gpio_chip *chip,
 471                                        unsigned int offset, int value)
 472{
 473        struct sx150x_pinctrl *pctl = gpiochip_get_data(chip);
 474        int ret;
 475
 476        if (sx150x_pin_is_oscio(pctl, offset))
 477                return sx150x_gpio_oscio_set(pctl, value);
 478
 479        ret = __sx150x_gpio_set(pctl, offset, value);
 480        if (ret < 0)
 481                return ret;
 482
 483        return regmap_write_bits(pctl->regmap,
 484                                 pctl->data->reg_dir,
 485                                 BIT(offset), 0);
 486}
 487
 488static void sx150x_irq_mask(struct irq_data *d)
 489{
 490        struct sx150x_pinctrl *pctl =
 491                        gpiochip_get_data(irq_data_get_irq_chip_data(d));
 492        unsigned int n = d->hwirq;
 493
 494        pctl->irq.masked |= BIT(n);
 495}
 496
 497static void sx150x_irq_unmask(struct irq_data *d)
 498{
 499        struct sx150x_pinctrl *pctl =
 500                        gpiochip_get_data(irq_data_get_irq_chip_data(d));
 501        unsigned int n = d->hwirq;
 502
 503        pctl->irq.masked &= ~BIT(n);
 504}
 505
 506static void sx150x_irq_set_sense(struct sx150x_pinctrl *pctl,
 507                                 unsigned int line, unsigned int sense)
 508{
 509        /*
 510         * Every interrupt line is represented by two bits shifted
 511         * proportionally to the line number
 512         */
 513        const unsigned int n = line * 2;
 514        const unsigned int mask = ~((SX150X_IRQ_TYPE_EDGE_RISING |
 515                                     SX150X_IRQ_TYPE_EDGE_FALLING) << n);
 516
 517        pctl->irq.sense &= mask;
 518        pctl->irq.sense |= sense << n;
 519}
 520
 521static int sx150x_irq_set_type(struct irq_data *d, unsigned int flow_type)
 522{
 523        struct sx150x_pinctrl *pctl =
 524                        gpiochip_get_data(irq_data_get_irq_chip_data(d));
 525        unsigned int n, val = 0;
 526
 527        if (flow_type & (IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
 528                return -EINVAL;
 529
 530        n = d->hwirq;
 531
 532        if (flow_type & IRQ_TYPE_EDGE_RISING)
 533                val |= SX150X_IRQ_TYPE_EDGE_RISING;
 534        if (flow_type & IRQ_TYPE_EDGE_FALLING)
 535                val |= SX150X_IRQ_TYPE_EDGE_FALLING;
 536
 537        sx150x_irq_set_sense(pctl, n, val);
 538        return 0;
 539}
 540
 541static irqreturn_t sx150x_irq_thread_fn(int irq, void *dev_id)
 542{
 543        struct sx150x_pinctrl *pctl = (struct sx150x_pinctrl *)dev_id;
 544        unsigned long n, status;
 545        unsigned int val;
 546        int err;
 547
 548        err = regmap_read(pctl->regmap, pctl->data->reg_irq_src, &val);
 549        if (err < 0)
 550                return IRQ_NONE;
 551
 552        err = regmap_write(pctl->regmap, pctl->data->reg_irq_src, val);
 553        if (err < 0)
 554                return IRQ_NONE;
 555
 556        status = val;
 557        for_each_set_bit(n, &status, pctl->data->ngpios)
 558                handle_nested_irq(irq_find_mapping(pctl->gpio.irq.domain, n));
 559
 560        return IRQ_HANDLED;
 561}
 562
 563static void sx150x_irq_bus_lock(struct irq_data *d)
 564{
 565        struct sx150x_pinctrl *pctl =
 566                        gpiochip_get_data(irq_data_get_irq_chip_data(d));
 567
 568        mutex_lock(&pctl->lock);
 569}
 570
 571static void sx150x_irq_bus_sync_unlock(struct irq_data *d)
 572{
 573        struct sx150x_pinctrl *pctl =
 574                        gpiochip_get_data(irq_data_get_irq_chip_data(d));
 575
 576        regmap_write(pctl->regmap, pctl->data->reg_irq_mask, pctl->irq.masked);
 577        regmap_write(pctl->regmap, pctl->data->reg_sense, pctl->irq.sense);
 578        mutex_unlock(&pctl->lock);
 579}
 580
 581static int sx150x_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 582                              unsigned long *config)
 583{
 584        struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 585        unsigned int param = pinconf_to_config_param(*config);
 586        int ret;
 587        u32 arg;
 588        unsigned int data;
 589
 590        if (sx150x_pin_is_oscio(pctl, pin)) {
 591                switch (param) {
 592                case PIN_CONFIG_DRIVE_PUSH_PULL:
 593                case PIN_CONFIG_OUTPUT:
 594                        ret = regmap_read(pctl->regmap,
 595                                          pctl->data->pri.x789.reg_clock,
 596                                          &data);
 597                        if (ret < 0)
 598                                return ret;
 599
 600                        if (param == PIN_CONFIG_DRIVE_PUSH_PULL)
 601                                arg = (data & 0x1f) ? 1 : 0;
 602                        else {
 603                                if ((data & 0x1f) == 0x1f)
 604                                        arg = 1;
 605                                else if ((data & 0x1f) == 0x10)
 606                                        arg = 0;
 607                                else
 608                                        return -EINVAL;
 609                        }
 610
 611                        break;
 612                default:
 613                        return -ENOTSUPP;
 614                }
 615
 616                goto out;
 617        }
 618
 619        switch (param) {
 620        case PIN_CONFIG_BIAS_PULL_DOWN:
 621                ret = regmap_read(pctl->regmap,
 622                                  pctl->data->reg_pulldn,
 623                                  &data);
 624                data &= BIT(pin);
 625
 626                if (ret < 0)
 627                        return ret;
 628
 629                if (!ret)
 630                        return -EINVAL;
 631
 632                arg = 1;
 633                break;
 634
 635        case PIN_CONFIG_BIAS_PULL_UP:
 636                ret = regmap_read(pctl->regmap,
 637                                  pctl->data->reg_pullup,
 638                                  &data);
 639                data &= BIT(pin);
 640
 641                if (ret < 0)
 642                        return ret;
 643
 644                if (!ret)
 645                        return -EINVAL;
 646
 647                arg = 1;
 648                break;
 649
 650        case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 651                if (pctl->data->model != SX150X_789)
 652                        return -ENOTSUPP;
 653
 654                ret = regmap_read(pctl->regmap,
 655                                  pctl->data->pri.x789.reg_drain,
 656                                  &data);
 657                data &= BIT(pin);
 658
 659                if (ret < 0)
 660                        return ret;
 661
 662                if (!data)
 663                        return -EINVAL;
 664
 665                arg = 1;
 666                break;
 667
 668        case PIN_CONFIG_DRIVE_PUSH_PULL:
 669                if (pctl->data->model != SX150X_789)
 670                        arg = true;
 671                else {
 672                        ret = regmap_read(pctl->regmap,
 673                                          pctl->data->pri.x789.reg_drain,
 674                                          &data);
 675                        data &= BIT(pin);
 676
 677                        if (ret < 0)
 678                                return ret;
 679
 680                        if (data)
 681                                return -EINVAL;
 682
 683                        arg = 1;
 684                }
 685                break;
 686
 687        case PIN_CONFIG_OUTPUT:
 688                ret = sx150x_gpio_get_direction(&pctl->gpio, pin);
 689                if (ret < 0)
 690                        return ret;
 691
 692                if (ret == GPIO_LINE_DIRECTION_IN)
 693                        return -EINVAL;
 694
 695                ret = sx150x_gpio_get(&pctl->gpio, pin);
 696                if (ret < 0)
 697                        return ret;
 698
 699                arg = ret;
 700                break;
 701
 702        default:
 703                return -ENOTSUPP;
 704        }
 705
 706out:
 707        *config = pinconf_to_config_packed(param, arg);
 708
 709        return 0;
 710}
 711
 712static int sx150x_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 713                              unsigned long *configs, unsigned int num_configs)
 714{
 715        struct sx150x_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
 716        enum pin_config_param param;
 717        u32 arg;
 718        int i;
 719        int ret;
 720
 721        for (i = 0; i < num_configs; i++) {
 722                param = pinconf_to_config_param(configs[i]);
 723                arg = pinconf_to_config_argument(configs[i]);
 724
 725                if (sx150x_pin_is_oscio(pctl, pin)) {
 726                        if (param == PIN_CONFIG_OUTPUT) {
 727                                ret = sx150x_gpio_direction_output(&pctl->gpio,
 728                                                                   pin, arg);
 729                                if (ret < 0)
 730                                        return ret;
 731
 732                                continue;
 733                        } else
 734                                return -ENOTSUPP;
 735                }
 736
 737                switch (param) {
 738                case PIN_CONFIG_BIAS_PULL_PIN_DEFAULT:
 739                case PIN_CONFIG_BIAS_DISABLE:
 740                        ret = regmap_write_bits(pctl->regmap,
 741                                                pctl->data->reg_pulldn,
 742                                                BIT(pin), 0);
 743                        if (ret < 0)
 744                                return ret;
 745
 746                        ret = regmap_write_bits(pctl->regmap,
 747                                                pctl->data->reg_pullup,
 748                                                BIT(pin), 0);
 749                        if (ret < 0)
 750                                return ret;
 751
 752                        break;
 753
 754                case PIN_CONFIG_BIAS_PULL_UP:
 755                        ret = regmap_write_bits(pctl->regmap,
 756                                                pctl->data->reg_pullup,
 757                                                BIT(pin), BIT(pin));
 758                        if (ret < 0)
 759                                return ret;
 760
 761                        break;
 762
 763                case PIN_CONFIG_BIAS_PULL_DOWN:
 764                        ret = regmap_write_bits(pctl->regmap,
 765                                                pctl->data->reg_pulldn,
 766                                                BIT(pin), BIT(pin));
 767                        if (ret < 0)
 768                                return ret;
 769
 770                        break;
 771
 772                case PIN_CONFIG_DRIVE_OPEN_DRAIN:
 773                        if (pctl->data->model != SX150X_789 ||
 774                            sx150x_pin_is_oscio(pctl, pin))
 775                                return -ENOTSUPP;
 776
 777                        ret = regmap_write_bits(pctl->regmap,
 778                                                pctl->data->pri.x789.reg_drain,
 779                                                BIT(pin), BIT(pin));
 780                        if (ret < 0)
 781                                return ret;
 782
 783                        break;
 784
 785                case PIN_CONFIG_DRIVE_PUSH_PULL:
 786                        if (pctl->data->model != SX150X_789 ||
 787                            sx150x_pin_is_oscio(pctl, pin))
 788                                return 0;
 789
 790                        ret = regmap_write_bits(pctl->regmap,
 791                                                pctl->data->pri.x789.reg_drain,
 792                                                BIT(pin), 0);
 793                        if (ret < 0)
 794                                return ret;
 795
 796                        break;
 797
 798                case PIN_CONFIG_OUTPUT:
 799                        ret = sx150x_gpio_direction_output(&pctl->gpio,
 800                                                           pin, arg);
 801                        if (ret < 0)
 802                                return ret;
 803
 804                        break;
 805
 806                default:
 807                        return -ENOTSUPP;
 808                }
 809        } /* for each config */
 810
 811        return 0;
 812}
 813
 814static const struct pinconf_ops sx150x_pinconf_ops = {
 815        .pin_config_get = sx150x_pinconf_get,
 816        .pin_config_set = sx150x_pinconf_set,
 817        .is_generic = true,
 818};
 819
 820static const struct i2c_device_id sx150x_id[] = {
 821        {"sx1501q", (kernel_ulong_t) &sx1501q_device_data },
 822        {"sx1502q", (kernel_ulong_t) &sx1502q_device_data },
 823        {"sx1503q", (kernel_ulong_t) &sx1503q_device_data },
 824        {"sx1504q", (kernel_ulong_t) &sx1504q_device_data },
 825        {"sx1505q", (kernel_ulong_t) &sx1505q_device_data },
 826        {"sx1506q", (kernel_ulong_t) &sx1506q_device_data },
 827        {"sx1507q", (kernel_ulong_t) &sx1507q_device_data },
 828        {"sx1508q", (kernel_ulong_t) &sx1508q_device_data },
 829        {"sx1509q", (kernel_ulong_t) &sx1509q_device_data },
 830        {}
 831};
 832
 833static const struct of_device_id sx150x_of_match[] = {
 834        { .compatible = "semtech,sx1501q", .data = &sx1501q_device_data },
 835        { .compatible = "semtech,sx1502q", .data = &sx1502q_device_data },
 836        { .compatible = "semtech,sx1503q", .data = &sx1503q_device_data },
 837        { .compatible = "semtech,sx1504q", .data = &sx1504q_device_data },
 838        { .compatible = "semtech,sx1505q", .data = &sx1505q_device_data },
 839        { .compatible = "semtech,sx1506q", .data = &sx1506q_device_data },
 840        { .compatible = "semtech,sx1507q", .data = &sx1507q_device_data },
 841        { .compatible = "semtech,sx1508q", .data = &sx1508q_device_data },
 842        { .compatible = "semtech,sx1509q", .data = &sx1509q_device_data },
 843        {},
 844};
 845
 846static int sx150x_reset(struct sx150x_pinctrl *pctl)
 847{
 848        int err;
 849
 850        err = i2c_smbus_write_byte_data(pctl->client,
 851                                        pctl->data->pri.x789.reg_reset,
 852                                        SX150X_789_RESET_KEY1);
 853        if (err < 0)
 854                return err;
 855
 856        err = i2c_smbus_write_byte_data(pctl->client,
 857                                        pctl->data->pri.x789.reg_reset,
 858                                        SX150X_789_RESET_KEY2);
 859        return err;
 860}
 861
 862static int sx150x_init_misc(struct sx150x_pinctrl *pctl)
 863{
 864        u8 reg, value;
 865
 866        switch (pctl->data->model) {
 867        case SX150X_789:
 868                reg   = pctl->data->pri.x789.reg_misc;
 869                value = SX150X_789_REG_MISC_AUTOCLEAR_OFF;
 870                break;
 871        case SX150X_456:
 872                reg   = pctl->data->pri.x456.reg_advanced;
 873                value = 0x00;
 874
 875                /*
 876                 * Only SX1506 has RegAdvanced, SX1504/5 are expected
 877                 * to initialize this offset to zero
 878                 */
 879                if (!reg)
 880                        return 0;
 881                break;
 882        case SX150X_123:
 883                reg   = pctl->data->pri.x123.reg_advanced;
 884                value = 0x00;
 885                break;
 886        default:
 887                WARN(1, "Unknown chip model %d\n", pctl->data->model);
 888                return -EINVAL;
 889        }
 890
 891        return regmap_write(pctl->regmap, reg, value);
 892}
 893
 894static int sx150x_init_hw(struct sx150x_pinctrl *pctl)
 895{
 896        const u8 reg[] = {
 897                [SX150X_789] = pctl->data->pri.x789.reg_polarity,
 898                [SX150X_456] = pctl->data->pri.x456.reg_pld_mode,
 899                [SX150X_123] = pctl->data->pri.x123.reg_pld_mode,
 900        };
 901        int err;
 902
 903        if (pctl->data->model == SX150X_789 &&
 904            of_property_read_bool(pctl->dev->of_node, "semtech,probe-reset")) {
 905                err = sx150x_reset(pctl);
 906                if (err < 0)
 907                        return err;
 908        }
 909
 910        err = sx150x_init_misc(pctl);
 911        if (err < 0)
 912                return err;
 913
 914        /* Set all pins to work in normal mode */
 915        return regmap_write(pctl->regmap, reg[pctl->data->model], 0);
 916}
 917
 918static int sx150x_regmap_reg_width(struct sx150x_pinctrl *pctl,
 919                                   unsigned int reg)
 920{
 921        const struct sx150x_device_data *data = pctl->data;
 922
 923        if (reg == data->reg_sense) {
 924                /*
 925                 * RegSense packs two bits of configuration per GPIO,
 926                 * so we'd need to read twice as many bits as there
 927                 * are GPIO in our chip
 928                 */
 929                return 2 * data->ngpios;
 930        } else if ((data->model == SX150X_789 &&
 931                    (reg == data->pri.x789.reg_misc ||
 932                     reg == data->pri.x789.reg_clock ||
 933                     reg == data->pri.x789.reg_reset))
 934                   ||
 935                   (data->model == SX150X_123 &&
 936                    reg == data->pri.x123.reg_advanced)
 937                   ||
 938                   (data->model == SX150X_456 &&
 939                    data->pri.x456.reg_advanced &&
 940                    reg == data->pri.x456.reg_advanced)) {
 941                return 8;
 942        } else {
 943                return data->ngpios;
 944        }
 945}
 946
 947static unsigned int sx150x_maybe_swizzle(struct sx150x_pinctrl *pctl,
 948                                         unsigned int reg, unsigned int val)
 949{
 950        unsigned int a, b;
 951        const struct sx150x_device_data *data = pctl->data;
 952
 953        /*
 954         * Whereas SX1509 presents RegSense in a simple layout as such:
 955         *      reg     [ f f e e d d c c ]
 956         *      reg + 1 [ b b a a 9 9 8 8 ]
 957         *      reg + 2 [ 7 7 6 6 5 5 4 4 ]
 958         *      reg + 3 [ 3 3 2 2 1 1 0 0 ]
 959         *
 960         * SX1503 and SX1506 deviate from that data layout, instead storing
 961         * their contents as follows:
 962         *
 963         *      reg     [ f f e e d d c c ]
 964         *      reg + 1 [ 7 7 6 6 5 5 4 4 ]
 965         *      reg + 2 [ b b a a 9 9 8 8 ]
 966         *      reg + 3 [ 3 3 2 2 1 1 0 0 ]
 967         *
 968         * so, taking that into account, we swap two
 969         * inner bytes of a 4-byte result
 970         */
 971
 972        if (reg == data->reg_sense &&
 973            data->ngpios == 16 &&
 974            (data->model == SX150X_123 ||
 975             data->model == SX150X_456)) {
 976                a = val & 0x00ff0000;
 977                b = val & 0x0000ff00;
 978
 979                val &= 0xff0000ff;
 980                val |= b << 8;
 981                val |= a >> 8;
 982        }
 983
 984        return val;
 985}
 986
 987/*
 988 * In order to mask the differences between 16 and 8 bit expander
 989 * devices we set up a sligthly ficticious regmap that pretends to be
 990 * a set of 32-bit (to accommodate RegSenseLow/RegSenseHigh
 991 * pair/quartet) registers and transparently reconstructs those
 992 * registers via multiple I2C/SMBus reads
 993 *
 994 * This way the rest of the driver code, interfacing with the chip via
 995 * regmap API, can work assuming that each GPIO pin is represented by
 996 * a group of bits at an offset proportional to GPIO number within a
 997 * given register.
 998 */
 999static int sx150x_regmap_reg_read(void *context, unsigned int reg,
1000                                  unsigned int *result)
1001{
1002        int ret, n;
1003        struct sx150x_pinctrl *pctl = context;
1004        struct i2c_client *i2c = pctl->client;
1005        const int width = sx150x_regmap_reg_width(pctl, reg);
1006        unsigned int idx, val;
1007
1008        /*
1009         * There are four potential cases covered by this function:
1010         *
1011         * 1) 8-pin chip, single configuration bit register
1012         *
1013         *      This is trivial the code below just needs to read:
1014         *              reg  [ 7 6 5 4 3 2 1 0 ]
1015         *
1016         * 2) 8-pin chip, double configuration bit register (RegSense)
1017         *
1018         *      The read will be done as follows:
1019         *              reg      [ 7 7 6 6 5 5 4 4 ]
1020         *              reg + 1  [ 3 3 2 2 1 1 0 0 ]
1021         *
1022         * 3) 16-pin chip, single configuration bit register
1023         *
1024         *      The read will be done as follows:
1025         *              reg     [ f e d c b a 9 8 ]
1026         *              reg + 1 [ 7 6 5 4 3 2 1 0 ]
1027         *
1028         * 4) 16-pin chip, double configuration bit register (RegSense)
1029         *
1030         *      The read will be done as follows:
1031         *              reg     [ f f e e d d c c ]
1032         *              reg + 1 [ b b a a 9 9 8 8 ]
1033         *              reg + 2 [ 7 7 6 6 5 5 4 4 ]
1034         *              reg + 3 [ 3 3 2 2 1 1 0 0 ]
1035         */
1036
1037        for (n = width, val = 0, idx = reg; n > 0; n -= 8, idx++) {
1038                val <<= 8;
1039
1040                ret = i2c_smbus_read_byte_data(i2c, idx);
1041                if (ret < 0)
1042                        return ret;
1043
1044                val |= ret;
1045        }
1046
1047        *result = sx150x_maybe_swizzle(pctl, reg, val);
1048
1049        return 0;
1050}
1051
1052static int sx150x_regmap_reg_write(void *context, unsigned int reg,
1053                                   unsigned int val)
1054{
1055        int ret, n;
1056        struct sx150x_pinctrl *pctl = context;
1057        struct i2c_client *i2c = pctl->client;
1058        const int width = sx150x_regmap_reg_width(pctl, reg);
1059
1060        val = sx150x_maybe_swizzle(pctl, reg, val);
1061
1062        n = (width - 1) & ~7;
1063        do {
1064                const u8 byte = (val >> n) & 0xff;
1065
1066                ret = i2c_smbus_write_byte_data(i2c, reg, byte);
1067                if (ret < 0)
1068                        return ret;
1069
1070                reg++;
1071                n -= 8;
1072        } while (n >= 0);
1073
1074        return 0;
1075}
1076
1077static bool sx150x_reg_volatile(struct device *dev, unsigned int reg)
1078{
1079        struct sx150x_pinctrl *pctl = i2c_get_clientdata(to_i2c_client(dev));
1080
1081        return reg == pctl->data->reg_irq_src || reg == pctl->data->reg_data;
1082}
1083
1084static const struct regmap_config sx150x_regmap_config = {
1085        .reg_bits = 8,
1086        .val_bits = 32,
1087
1088        .cache_type = REGCACHE_RBTREE,
1089
1090        .reg_read = sx150x_regmap_reg_read,
1091        .reg_write = sx150x_regmap_reg_write,
1092
1093        .max_register = SX150X_MAX_REGISTER,
1094        .volatile_reg = sx150x_reg_volatile,
1095};
1096
1097static int sx150x_probe(struct i2c_client *client,
1098                        const struct i2c_device_id *id)
1099{
1100        static const u32 i2c_funcs = I2C_FUNC_SMBUS_BYTE_DATA |
1101                                     I2C_FUNC_SMBUS_WRITE_WORD_DATA;
1102        struct device *dev = &client->dev;
1103        struct sx150x_pinctrl *pctl;
1104        int ret;
1105
1106        if (!i2c_check_functionality(client->adapter, i2c_funcs))
1107                return -ENOSYS;
1108
1109        pctl = devm_kzalloc(dev, sizeof(*pctl), GFP_KERNEL);
1110        if (!pctl)
1111                return -ENOMEM;
1112
1113        i2c_set_clientdata(client, pctl);
1114
1115        pctl->dev = dev;
1116        pctl->client = client;
1117
1118        if (dev->of_node)
1119                pctl->data = of_device_get_match_data(dev);
1120        else
1121                pctl->data = (struct sx150x_device_data *)id->driver_data;
1122
1123        if (!pctl->data)
1124                return -EINVAL;
1125
1126        pctl->regmap = devm_regmap_init(dev, NULL, pctl,
1127                                        &sx150x_regmap_config);
1128        if (IS_ERR(pctl->regmap)) {
1129                ret = PTR_ERR(pctl->regmap);
1130                dev_err(dev, "Failed to allocate register map: %d\n",
1131                        ret);
1132                return ret;
1133        }
1134
1135        mutex_init(&pctl->lock);
1136
1137        ret = sx150x_init_hw(pctl);
1138        if (ret)
1139                return ret;
1140
1141        /* Pinctrl_desc */
1142        pctl->pinctrl_desc.name = "sx150x-pinctrl";
1143        pctl->pinctrl_desc.pctlops = &sx150x_pinctrl_ops;
1144        pctl->pinctrl_desc.confops = &sx150x_pinconf_ops;
1145        pctl->pinctrl_desc.pins = pctl->data->pins;
1146        pctl->pinctrl_desc.npins = pctl->data->npins;
1147        pctl->pinctrl_desc.owner = THIS_MODULE;
1148
1149        ret = devm_pinctrl_register_and_init(dev, &pctl->pinctrl_desc,
1150                                             pctl, &pctl->pctldev);
1151        if (ret) {
1152                dev_err(dev, "Failed to register pinctrl device\n");
1153                return ret;
1154        }
1155
1156        /* Register GPIO controller */
1157        pctl->gpio.base = -1;
1158        pctl->gpio.ngpio = pctl->data->npins;
1159        pctl->gpio.get_direction = sx150x_gpio_get_direction;
1160        pctl->gpio.direction_input = sx150x_gpio_direction_input;
1161        pctl->gpio.direction_output = sx150x_gpio_direction_output;
1162        pctl->gpio.get = sx150x_gpio_get;
1163        pctl->gpio.set = sx150x_gpio_set;
1164        pctl->gpio.set_config = gpiochip_generic_config;
1165        pctl->gpio.parent = dev;
1166#ifdef CONFIG_OF_GPIO
1167        pctl->gpio.of_node = dev->of_node;
1168#endif
1169        pctl->gpio.can_sleep = true;
1170        pctl->gpio.label = devm_kstrdup(dev, client->name, GFP_KERNEL);
1171        if (!pctl->gpio.label)
1172                return -ENOMEM;
1173
1174        /*
1175         * Setting multiple pins is not safe when all pins are not
1176         * handled by the same regmap register. The oscio pin (present
1177         * on the SX150X_789 chips) lives in its own register, so
1178         * would require locking that is not in place at this time.
1179         */
1180        if (pctl->data->model != SX150X_789)
1181                pctl->gpio.set_multiple = sx150x_gpio_set_multiple;
1182
1183        /* Add Interrupt support if an irq is specified */
1184        if (client->irq > 0) {
1185                struct gpio_irq_chip *girq;
1186
1187                pctl->irq_chip.irq_mask = sx150x_irq_mask;
1188                pctl->irq_chip.irq_unmask = sx150x_irq_unmask;
1189                pctl->irq_chip.irq_set_type = sx150x_irq_set_type;
1190                pctl->irq_chip.irq_bus_lock = sx150x_irq_bus_lock;
1191                pctl->irq_chip.irq_bus_sync_unlock = sx150x_irq_bus_sync_unlock;
1192                pctl->irq_chip.name = devm_kstrdup(dev, client->name,
1193                                                   GFP_KERNEL);
1194                if (!pctl->irq_chip.name)
1195                        return -ENOMEM;
1196
1197                pctl->irq.masked = ~0;
1198                pctl->irq.sense = 0;
1199
1200                /*
1201                 * Because sx150x_irq_threaded_fn invokes all of the
1202                 * nested interrupt handlers via handle_nested_irq,
1203                 * any "handler" assigned to struct gpio_irq_chip
1204                 * below is going to be ignored, so the choice of the
1205                 * function does not matter that much.
1206                 *
1207                 * We set it to handle_bad_irq to avoid confusion,
1208                 * plus it will be instantly noticeable if it is ever
1209                 * called (should not happen)
1210                 */
1211                girq = &pctl->gpio.irq;
1212                girq->chip = &pctl->irq_chip;
1213                /* This will let us handle the parent IRQ in the driver */
1214                girq->parent_handler = NULL;
1215                girq->num_parents = 0;
1216                girq->parents = NULL;
1217                girq->default_type = IRQ_TYPE_NONE;
1218                girq->handler = handle_bad_irq;
1219                girq->threaded = true;
1220
1221                ret = devm_request_threaded_irq(dev, client->irq, NULL,
1222                                                sx150x_irq_thread_fn,
1223                                                IRQF_ONESHOT | IRQF_SHARED |
1224                                                IRQF_TRIGGER_FALLING,
1225                                                pctl->irq_chip.name, pctl);
1226                if (ret < 0)
1227                        return ret;
1228        }
1229
1230        ret = devm_gpiochip_add_data(dev, &pctl->gpio, pctl);
1231        if (ret)
1232                return ret;
1233
1234        /*
1235         * Pin control functions need to be enabled AFTER registering the
1236         * GPIO chip because sx150x_pinconf_set() calls
1237         * sx150x_gpio_direction_output().
1238         */
1239        ret = pinctrl_enable(pctl->pctldev);
1240        if (ret) {
1241                dev_err(dev, "Failed to enable pinctrl device\n");
1242                return ret;
1243        }
1244
1245        ret = gpiochip_add_pin_range(&pctl->gpio, dev_name(dev),
1246                                     0, 0, pctl->data->npins);
1247        if (ret)
1248                return ret;
1249
1250        return 0;
1251}
1252
1253static struct i2c_driver sx150x_driver = {
1254        .driver = {
1255                .name = "sx150x-pinctrl",
1256                .of_match_table = of_match_ptr(sx150x_of_match),
1257        },
1258        .probe    = sx150x_probe,
1259        .id_table = sx150x_id,
1260};
1261
1262static int __init sx150x_init(void)
1263{
1264        return i2c_add_driver(&sx150x_driver);
1265}
1266subsys_initcall(sx150x_init);
1267