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19#include <linux/kernel.h>
20#include <linux/slab.h>
21#include <linux/interrupt.h>
22#include <linux/io.h>
23#include <linux/gpio/driver.h>
24#include <linux/ioport.h>
25#include <linux/of_device.h>
26#include <linux/of_irq.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinconf.h>
29#include <linux/pinctrl/pinconf-generic.h>
30
31#include "../pinctrl-utils.h"
32
33#define IPROC_GPIO_DATA_IN_OFFSET 0x00
34#define IPROC_GPIO_DATA_OUT_OFFSET 0x04
35#define IPROC_GPIO_OUT_EN_OFFSET 0x08
36#define IPROC_GPIO_INT_TYPE_OFFSET 0x0c
37#define IPROC_GPIO_INT_DE_OFFSET 0x10
38#define IPROC_GPIO_INT_EDGE_OFFSET 0x14
39#define IPROC_GPIO_INT_MSK_OFFSET 0x18
40#define IPROC_GPIO_INT_STAT_OFFSET 0x1c
41#define IPROC_GPIO_INT_MSTAT_OFFSET 0x20
42#define IPROC_GPIO_INT_CLR_OFFSET 0x24
43#define IPROC_GPIO_PAD_RES_OFFSET 0x34
44#define IPROC_GPIO_RES_EN_OFFSET 0x38
45
46
47#define IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET 0x58
48
49
50#define IPROC_GPIO_PULL_DN_OFFSET 0x10
51#define IPROC_GPIO_PULL_UP_OFFSET 0x14
52
53
54#define IPROC_GPIO_DRV_CTRL_OFFSET 0x00
55
56#define GPIO_BANK_SIZE 0x200
57#define NGPIOS_PER_BANK 32
58#define GPIO_BANK(pin) ((pin) / NGPIOS_PER_BANK)
59
60#define IPROC_GPIO_REG(pin, reg) (GPIO_BANK(pin) * GPIO_BANK_SIZE + (reg))
61#define IPROC_GPIO_SHIFT(pin) ((pin) % NGPIOS_PER_BANK)
62
63#define GPIO_DRV_STRENGTH_BIT_SHIFT 20
64#define GPIO_DRV_STRENGTH_BITS 3
65#define GPIO_DRV_STRENGTH_BIT_MASK ((1 << GPIO_DRV_STRENGTH_BITS) - 1)
66
67enum iproc_pinconf_param {
68 IPROC_PINCONF_DRIVE_STRENGTH = 0,
69 IPROC_PINCONF_BIAS_DISABLE,
70 IPROC_PINCONF_BIAS_PULL_UP,
71 IPROC_PINCONF_BIAS_PULL_DOWN,
72 IPROC_PINCON_MAX,
73};
74
75enum iproc_pinconf_ctrl_type {
76 IOCTRL_TYPE_AON = 1,
77 IOCTRL_TYPE_CDRU,
78 IOCTRL_TYPE_INVALID,
79};
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100struct iproc_gpio {
101 struct device *dev;
102
103 void __iomem *base;
104 void __iomem *io_ctrl;
105 enum iproc_pinconf_ctrl_type io_ctrl_type;
106
107 raw_spinlock_t lock;
108
109 struct irq_chip irqchip;
110 struct gpio_chip gc;
111 unsigned num_banks;
112
113 bool pinmux_is_supported;
114
115 enum pin_config_param *pinconf_disable;
116 unsigned int nr_pinconf_disable;
117
118 struct pinctrl_dev *pctl;
119 struct pinctrl_desc pctldesc;
120};
121
122
123
124
125static inline unsigned iproc_pin_to_gpio(unsigned pin)
126{
127 return pin;
128}
129
130
131
132
133
134
135
136
137
138
139static inline void iproc_set_bit(struct iproc_gpio *chip, unsigned int reg,
140 unsigned gpio, bool set)
141{
142 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
143 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
144 u32 val;
145
146 val = readl(chip->base + offset);
147 if (set)
148 val |= BIT(shift);
149 else
150 val &= ~BIT(shift);
151 writel(val, chip->base + offset);
152}
153
154static inline bool iproc_get_bit(struct iproc_gpio *chip, unsigned int reg,
155 unsigned gpio)
156{
157 unsigned int offset = IPROC_GPIO_REG(gpio, reg);
158 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
159
160 return !!(readl(chip->base + offset) & BIT(shift));
161}
162
163static void iproc_gpio_irq_handler(struct irq_desc *desc)
164{
165 struct gpio_chip *gc = irq_desc_get_handler_data(desc);
166 struct iproc_gpio *chip = gpiochip_get_data(gc);
167 struct irq_chip *irq_chip = irq_desc_get_chip(desc);
168 int i, bit;
169
170 chained_irq_enter(irq_chip, desc);
171
172
173 for (i = 0; i < chip->num_banks; i++) {
174 unsigned long val = readl(chip->base + (i * GPIO_BANK_SIZE) +
175 IPROC_GPIO_INT_MSTAT_OFFSET);
176
177 for_each_set_bit(bit, &val, NGPIOS_PER_BANK) {
178 unsigned pin = NGPIOS_PER_BANK * i + bit;
179 int child_irq = irq_find_mapping(gc->irq.domain, pin);
180
181
182
183
184
185 writel(BIT(bit), chip->base + (i * GPIO_BANK_SIZE) +
186 IPROC_GPIO_INT_CLR_OFFSET);
187
188 generic_handle_irq(child_irq);
189 }
190 }
191
192 chained_irq_exit(irq_chip, desc);
193}
194
195
196static void iproc_gpio_irq_ack(struct irq_data *d)
197{
198 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
199 struct iproc_gpio *chip = gpiochip_get_data(gc);
200 unsigned gpio = d->hwirq;
201 unsigned int offset = IPROC_GPIO_REG(gpio,
202 IPROC_GPIO_INT_CLR_OFFSET);
203 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
204 u32 val = BIT(shift);
205
206 writel(val, chip->base + offset);
207}
208
209
210
211
212
213
214
215static void iproc_gpio_irq_set_mask(struct irq_data *d, bool unmask)
216{
217 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
218 struct iproc_gpio *chip = gpiochip_get_data(gc);
219 unsigned gpio = d->hwirq;
220
221 iproc_set_bit(chip, IPROC_GPIO_INT_MSK_OFFSET, gpio, unmask);
222}
223
224static void iproc_gpio_irq_mask(struct irq_data *d)
225{
226 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
227 struct iproc_gpio *chip = gpiochip_get_data(gc);
228 unsigned long flags;
229
230 raw_spin_lock_irqsave(&chip->lock, flags);
231 iproc_gpio_irq_set_mask(d, false);
232 raw_spin_unlock_irqrestore(&chip->lock, flags);
233}
234
235static void iproc_gpio_irq_unmask(struct irq_data *d)
236{
237 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
238 struct iproc_gpio *chip = gpiochip_get_data(gc);
239 unsigned long flags;
240
241 raw_spin_lock_irqsave(&chip->lock, flags);
242 iproc_gpio_irq_set_mask(d, true);
243 raw_spin_unlock_irqrestore(&chip->lock, flags);
244}
245
246static int iproc_gpio_irq_set_type(struct irq_data *d, unsigned int type)
247{
248 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
249 struct iproc_gpio *chip = gpiochip_get_data(gc);
250 unsigned gpio = d->hwirq;
251 bool level_triggered = false;
252 bool dual_edge = false;
253 bool rising_or_high = false;
254 unsigned long flags;
255
256 switch (type & IRQ_TYPE_SENSE_MASK) {
257 case IRQ_TYPE_EDGE_RISING:
258 rising_or_high = true;
259 break;
260
261 case IRQ_TYPE_EDGE_FALLING:
262 break;
263
264 case IRQ_TYPE_EDGE_BOTH:
265 dual_edge = true;
266 break;
267
268 case IRQ_TYPE_LEVEL_HIGH:
269 level_triggered = true;
270 rising_or_high = true;
271 break;
272
273 case IRQ_TYPE_LEVEL_LOW:
274 level_triggered = true;
275 break;
276
277 default:
278 dev_err(chip->dev, "invalid GPIO IRQ type 0x%x\n",
279 type);
280 return -EINVAL;
281 }
282
283 raw_spin_lock_irqsave(&chip->lock, flags);
284 iproc_set_bit(chip, IPROC_GPIO_INT_TYPE_OFFSET, gpio,
285 level_triggered);
286 iproc_set_bit(chip, IPROC_GPIO_INT_DE_OFFSET, gpio, dual_edge);
287 iproc_set_bit(chip, IPROC_GPIO_INT_EDGE_OFFSET, gpio,
288 rising_or_high);
289
290 if (type & IRQ_TYPE_EDGE_BOTH)
291 irq_set_handler_locked(d, handle_edge_irq);
292 else
293 irq_set_handler_locked(d, handle_level_irq);
294
295 raw_spin_unlock_irqrestore(&chip->lock, flags);
296
297 dev_dbg(chip->dev,
298 "gpio:%u level_triggered:%d dual_edge:%d rising_or_high:%d\n",
299 gpio, level_triggered, dual_edge, rising_or_high);
300
301 return 0;
302}
303
304
305
306
307static int iproc_gpio_request(struct gpio_chip *gc, unsigned offset)
308{
309 struct iproc_gpio *chip = gpiochip_get_data(gc);
310 unsigned gpio = gc->base + offset;
311
312
313 if (!chip->pinmux_is_supported)
314 return 0;
315
316 return pinctrl_gpio_request(gpio);
317}
318
319static void iproc_gpio_free(struct gpio_chip *gc, unsigned offset)
320{
321 struct iproc_gpio *chip = gpiochip_get_data(gc);
322 unsigned gpio = gc->base + offset;
323
324 if (!chip->pinmux_is_supported)
325 return;
326
327 pinctrl_gpio_free(gpio);
328}
329
330static int iproc_gpio_direction_input(struct gpio_chip *gc, unsigned gpio)
331{
332 struct iproc_gpio *chip = gpiochip_get_data(gc);
333 unsigned long flags;
334
335 raw_spin_lock_irqsave(&chip->lock, flags);
336 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, false);
337 raw_spin_unlock_irqrestore(&chip->lock, flags);
338
339 dev_dbg(chip->dev, "gpio:%u set input\n", gpio);
340
341 return 0;
342}
343
344static int iproc_gpio_direction_output(struct gpio_chip *gc, unsigned gpio,
345 int val)
346{
347 struct iproc_gpio *chip = gpiochip_get_data(gc);
348 unsigned long flags;
349
350 raw_spin_lock_irqsave(&chip->lock, flags);
351 iproc_set_bit(chip, IPROC_GPIO_OUT_EN_OFFSET, gpio, true);
352 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
353 raw_spin_unlock_irqrestore(&chip->lock, flags);
354
355 dev_dbg(chip->dev, "gpio:%u set output, value:%d\n", gpio, val);
356
357 return 0;
358}
359
360static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
361{
362 struct iproc_gpio *chip = gpiochip_get_data(gc);
363 unsigned int offset = IPROC_GPIO_REG(gpio, IPROC_GPIO_OUT_EN_OFFSET);
364 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
365
366 if (readl(chip->base + offset) & BIT(shift))
367 return GPIO_LINE_DIRECTION_OUT;
368
369 return GPIO_LINE_DIRECTION_IN;
370}
371
372static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
373{
374 struct iproc_gpio *chip = gpiochip_get_data(gc);
375 unsigned long flags;
376
377 raw_spin_lock_irqsave(&chip->lock, flags);
378 iproc_set_bit(chip, IPROC_GPIO_DATA_OUT_OFFSET, gpio, !!(val));
379 raw_spin_unlock_irqrestore(&chip->lock, flags);
380
381 dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
382}
383
384static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
385{
386 struct iproc_gpio *chip = gpiochip_get_data(gc);
387 unsigned int offset = IPROC_GPIO_REG(gpio,
388 IPROC_GPIO_DATA_IN_OFFSET);
389 unsigned int shift = IPROC_GPIO_SHIFT(gpio);
390
391 return !!(readl(chip->base + offset) & BIT(shift));
392}
393
394
395
396
397
398static const enum pin_config_param iproc_pinconf_disable_map[] = {
399 [IPROC_PINCONF_DRIVE_STRENGTH] = PIN_CONFIG_DRIVE_STRENGTH,
400 [IPROC_PINCONF_BIAS_DISABLE] = PIN_CONFIG_BIAS_DISABLE,
401 [IPROC_PINCONF_BIAS_PULL_UP] = PIN_CONFIG_BIAS_PULL_UP,
402 [IPROC_PINCONF_BIAS_PULL_DOWN] = PIN_CONFIG_BIAS_PULL_DOWN,
403};
404
405static bool iproc_pinconf_param_is_disabled(struct iproc_gpio *chip,
406 enum pin_config_param param)
407{
408 unsigned int i;
409
410 if (!chip->nr_pinconf_disable)
411 return false;
412
413 for (i = 0; i < chip->nr_pinconf_disable; i++)
414 if (chip->pinconf_disable[i] == param)
415 return true;
416
417 return false;
418}
419
420static int iproc_pinconf_disable_map_create(struct iproc_gpio *chip,
421 unsigned long disable_mask)
422{
423 unsigned int map_size = ARRAY_SIZE(iproc_pinconf_disable_map);
424 unsigned int bit, nbits = 0;
425
426
427 for_each_set_bit(bit, &disable_mask, map_size)
428 nbits++;
429
430 if (!nbits)
431 return 0;
432
433
434
435
436
437 chip->pinconf_disable = devm_kcalloc(chip->dev, nbits,
438 sizeof(*chip->pinconf_disable),
439 GFP_KERNEL);
440 if (!chip->pinconf_disable)
441 return -ENOMEM;
442
443 chip->nr_pinconf_disable = nbits;
444
445
446 nbits = 0;
447 for_each_set_bit(bit, &disable_mask, map_size)
448 chip->pinconf_disable[nbits++] = iproc_pinconf_disable_map[bit];
449
450 return 0;
451}
452
453static int iproc_get_groups_count(struct pinctrl_dev *pctldev)
454{
455 return 1;
456}
457
458
459
460
461
462static const char *iproc_get_group_name(struct pinctrl_dev *pctldev,
463 unsigned selector)
464{
465 return "gpio_grp";
466}
467
468static const struct pinctrl_ops iproc_pctrl_ops = {
469 .get_groups_count = iproc_get_groups_count,
470 .get_group_name = iproc_get_group_name,
471 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
472 .dt_free_map = pinctrl_utils_free_map,
473};
474
475static int iproc_gpio_set_pull(struct iproc_gpio *chip, unsigned gpio,
476 bool disable, bool pull_up)
477{
478 void __iomem *base;
479 unsigned long flags;
480 unsigned int shift;
481 u32 val_1, val_2;
482
483 raw_spin_lock_irqsave(&chip->lock, flags);
484 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
485 base = chip->io_ctrl;
486 shift = IPROC_GPIO_SHIFT(gpio);
487
488 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET);
489 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET);
490 if (disable) {
491
492 val_1 &= ~BIT(shift);
493 val_2 &= ~BIT(shift);
494 } else if (pull_up) {
495 val_1 |= BIT(shift);
496 val_2 &= ~BIT(shift);
497 } else {
498 val_1 &= ~BIT(shift);
499 val_2 |= BIT(shift);
500 }
501 writel(val_1, base + IPROC_GPIO_PULL_UP_OFFSET);
502 writel(val_2, base + IPROC_GPIO_PULL_DN_OFFSET);
503 } else {
504 if (disable) {
505 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
506 false);
507 } else {
508 iproc_set_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio,
509 pull_up);
510 iproc_set_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio,
511 true);
512 }
513 }
514
515 raw_spin_unlock_irqrestore(&chip->lock, flags);
516 dev_dbg(chip->dev, "gpio:%u set pullup:%d\n", gpio, pull_up);
517
518 return 0;
519}
520
521static void iproc_gpio_get_pull(struct iproc_gpio *chip, unsigned gpio,
522 bool *disable, bool *pull_up)
523{
524 void __iomem *base;
525 unsigned long flags;
526 unsigned int shift;
527 u32 val_1, val_2;
528
529 raw_spin_lock_irqsave(&chip->lock, flags);
530 if (chip->io_ctrl_type == IOCTRL_TYPE_CDRU) {
531 base = chip->io_ctrl;
532 shift = IPROC_GPIO_SHIFT(gpio);
533
534 val_1 = readl(base + IPROC_GPIO_PULL_UP_OFFSET) & BIT(shift);
535 val_2 = readl(base + IPROC_GPIO_PULL_DN_OFFSET) & BIT(shift);
536
537 *pull_up = val_1 ? true : false;
538 *disable = (val_1 | val_2) ? false : true;
539
540 } else {
541 *disable = !iproc_get_bit(chip, IPROC_GPIO_RES_EN_OFFSET, gpio);
542 *pull_up = iproc_get_bit(chip, IPROC_GPIO_PAD_RES_OFFSET, gpio);
543 }
544 raw_spin_unlock_irqrestore(&chip->lock, flags);
545}
546
547#define DRV_STRENGTH_OFFSET(gpio, bit, type) ((type) == IOCTRL_TYPE_AON ? \
548 ((2 - (bit)) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
549 ((type) == IOCTRL_TYPE_CDRU) ? \
550 ((bit) * 4 + IPROC_GPIO_DRV_CTRL_OFFSET) : \
551 ((bit) * 4 + IPROC_GPIO_REG(gpio, IPROC_GPIO_ASIU_DRV0_CTRL_OFFSET)))
552
553static int iproc_gpio_set_strength(struct iproc_gpio *chip, unsigned gpio,
554 unsigned strength)
555{
556 void __iomem *base;
557 unsigned int i, offset, shift;
558 u32 val;
559 unsigned long flags;
560
561
562 if (strength < 2 || strength > 16 || (strength % 2))
563 return -ENOTSUPP;
564
565 if (chip->io_ctrl) {
566 base = chip->io_ctrl;
567 } else {
568 base = chip->base;
569 }
570
571 shift = IPROC_GPIO_SHIFT(gpio);
572
573 dev_dbg(chip->dev, "gpio:%u set drive strength:%d mA\n", gpio,
574 strength);
575
576 raw_spin_lock_irqsave(&chip->lock, flags);
577 strength = (strength / 2) - 1;
578 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
579 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
580 val = readl(base + offset);
581 val &= ~BIT(shift);
582 val |= ((strength >> i) & 0x1) << shift;
583 writel(val, base + offset);
584 }
585 raw_spin_unlock_irqrestore(&chip->lock, flags);
586
587 return 0;
588}
589
590static int iproc_gpio_get_strength(struct iproc_gpio *chip, unsigned gpio,
591 u16 *strength)
592{
593 void __iomem *base;
594 unsigned int i, offset, shift;
595 u32 val;
596 unsigned long flags;
597
598 if (chip->io_ctrl) {
599 base = chip->io_ctrl;
600 } else {
601 base = chip->base;
602 }
603
604 shift = IPROC_GPIO_SHIFT(gpio);
605
606 raw_spin_lock_irqsave(&chip->lock, flags);
607 *strength = 0;
608 for (i = 0; i < GPIO_DRV_STRENGTH_BITS; i++) {
609 offset = DRV_STRENGTH_OFFSET(gpio, i, chip->io_ctrl_type);
610 val = readl(base + offset) & BIT(shift);
611 val >>= shift;
612 *strength += (val << i);
613 }
614
615
616 *strength = (*strength + 1) * 2;
617 raw_spin_unlock_irqrestore(&chip->lock, flags);
618
619 return 0;
620}
621
622static int iproc_pin_config_get(struct pinctrl_dev *pctldev, unsigned pin,
623 unsigned long *config)
624{
625 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
626 enum pin_config_param param = pinconf_to_config_param(*config);
627 unsigned gpio = iproc_pin_to_gpio(pin);
628 u16 arg;
629 bool disable, pull_up;
630 int ret;
631
632 if (iproc_pinconf_param_is_disabled(chip, param))
633 return -ENOTSUPP;
634
635 switch (param) {
636 case PIN_CONFIG_BIAS_DISABLE:
637 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
638 if (disable)
639 return 0;
640 else
641 return -EINVAL;
642
643 case PIN_CONFIG_BIAS_PULL_UP:
644 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
645 if (!disable && pull_up)
646 return 0;
647 else
648 return -EINVAL;
649
650 case PIN_CONFIG_BIAS_PULL_DOWN:
651 iproc_gpio_get_pull(chip, gpio, &disable, &pull_up);
652 if (!disable && !pull_up)
653 return 0;
654 else
655 return -EINVAL;
656
657 case PIN_CONFIG_DRIVE_STRENGTH:
658 ret = iproc_gpio_get_strength(chip, gpio, &arg);
659 if (ret)
660 return ret;
661 *config = pinconf_to_config_packed(param, arg);
662
663 return 0;
664
665 default:
666 return -ENOTSUPP;
667 }
668
669 return -ENOTSUPP;
670}
671
672static int iproc_pin_config_set(struct pinctrl_dev *pctldev, unsigned pin,
673 unsigned long *configs, unsigned num_configs)
674{
675 struct iproc_gpio *chip = pinctrl_dev_get_drvdata(pctldev);
676 enum pin_config_param param;
677 u32 arg;
678 unsigned i, gpio = iproc_pin_to_gpio(pin);
679 int ret = -ENOTSUPP;
680
681 for (i = 0; i < num_configs; i++) {
682 param = pinconf_to_config_param(configs[i]);
683
684 if (iproc_pinconf_param_is_disabled(chip, param))
685 return -ENOTSUPP;
686
687 arg = pinconf_to_config_argument(configs[i]);
688
689 switch (param) {
690 case PIN_CONFIG_BIAS_DISABLE:
691 ret = iproc_gpio_set_pull(chip, gpio, true, false);
692 if (ret < 0)
693 goto out;
694 break;
695
696 case PIN_CONFIG_BIAS_PULL_UP:
697 ret = iproc_gpio_set_pull(chip, gpio, false, true);
698 if (ret < 0)
699 goto out;
700 break;
701
702 case PIN_CONFIG_BIAS_PULL_DOWN:
703 ret = iproc_gpio_set_pull(chip, gpio, false, false);
704 if (ret < 0)
705 goto out;
706 break;
707
708 case PIN_CONFIG_DRIVE_STRENGTH:
709 ret = iproc_gpio_set_strength(chip, gpio, arg);
710 if (ret < 0)
711 goto out;
712 break;
713
714 default:
715 dev_err(chip->dev, "invalid configuration\n");
716 return -ENOTSUPP;
717 }
718 }
719
720out:
721 return ret;
722}
723
724static const struct pinconf_ops iproc_pconf_ops = {
725 .is_generic = true,
726 .pin_config_get = iproc_pin_config_get,
727 .pin_config_set = iproc_pin_config_set,
728};
729
730
731
732
733
734
735
736
737static int iproc_gpio_register_pinconf(struct iproc_gpio *chip)
738{
739 struct pinctrl_desc *pctldesc = &chip->pctldesc;
740 struct pinctrl_pin_desc *pins;
741 struct gpio_chip *gc = &chip->gc;
742 int i;
743
744 pins = devm_kcalloc(chip->dev, gc->ngpio, sizeof(*pins), GFP_KERNEL);
745 if (!pins)
746 return -ENOMEM;
747
748 for (i = 0; i < gc->ngpio; i++) {
749 pins[i].number = i;
750 pins[i].name = devm_kasprintf(chip->dev, GFP_KERNEL,
751 "gpio-%d", i);
752 if (!pins[i].name)
753 return -ENOMEM;
754 }
755
756 pctldesc->name = dev_name(chip->dev);
757 pctldesc->pctlops = &iproc_pctrl_ops;
758 pctldesc->pins = pins;
759 pctldesc->npins = gc->ngpio;
760 pctldesc->confops = &iproc_pconf_ops;
761
762 chip->pctl = devm_pinctrl_register(chip->dev, pctldesc, chip);
763 if (IS_ERR(chip->pctl)) {
764 dev_err(chip->dev, "unable to register pinctrl device\n");
765 return PTR_ERR(chip->pctl);
766 }
767
768 return 0;
769}
770
771static const struct of_device_id iproc_gpio_of_match[] = {
772 { .compatible = "brcm,iproc-gpio" },
773 { .compatible = "brcm,cygnus-ccm-gpio" },
774 { .compatible = "brcm,cygnus-asiu-gpio" },
775 { .compatible = "brcm,cygnus-crmu-gpio" },
776 { .compatible = "brcm,iproc-nsp-gpio" },
777 { .compatible = "brcm,iproc-stingray-gpio" },
778 { }
779};
780
781static int iproc_gpio_probe(struct platform_device *pdev)
782{
783 struct device *dev = &pdev->dev;
784 struct resource *res;
785 struct iproc_gpio *chip;
786 struct gpio_chip *gc;
787 u32 ngpios, pinconf_disable_mask = 0;
788 int irq, ret;
789 bool no_pinconf = false;
790 enum iproc_pinconf_ctrl_type io_ctrl_type = IOCTRL_TYPE_INVALID;
791
792
793 if (of_device_is_compatible(dev->of_node, "brcm,iproc-nsp-gpio"))
794 pinconf_disable_mask = BIT(IPROC_PINCONF_DRIVE_STRENGTH);
795
796 else if (of_device_is_compatible(dev->of_node,
797 "brcm,iproc-stingray-gpio"))
798 no_pinconf = true;
799
800 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
801 if (!chip)
802 return -ENOMEM;
803
804 chip->dev = dev;
805 platform_set_drvdata(pdev, chip);
806
807 chip->base = devm_platform_ioremap_resource(pdev, 0);
808 if (IS_ERR(chip->base)) {
809 dev_err(dev, "unable to map I/O memory\n");
810 return PTR_ERR(chip->base);
811 }
812
813 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
814 if (res) {
815 chip->io_ctrl = devm_ioremap_resource(dev, res);
816 if (IS_ERR(chip->io_ctrl))
817 return PTR_ERR(chip->io_ctrl);
818 if (of_device_is_compatible(dev->of_node,
819 "brcm,cygnus-ccm-gpio"))
820 io_ctrl_type = IOCTRL_TYPE_CDRU;
821 else
822 io_ctrl_type = IOCTRL_TYPE_AON;
823 }
824
825 chip->io_ctrl_type = io_ctrl_type;
826
827 if (of_property_read_u32(dev->of_node, "ngpios", &ngpios)) {
828 dev_err(&pdev->dev, "missing ngpios DT property\n");
829 return -ENODEV;
830 }
831
832 raw_spin_lock_init(&chip->lock);
833
834 gc = &chip->gc;
835 gc->base = -1;
836 gc->ngpio = ngpios;
837 chip->num_banks = (ngpios + NGPIOS_PER_BANK - 1) / NGPIOS_PER_BANK;
838 gc->label = dev_name(dev);
839 gc->parent = dev;
840 gc->of_node = dev->of_node;
841 gc->request = iproc_gpio_request;
842 gc->free = iproc_gpio_free;
843 gc->direction_input = iproc_gpio_direction_input;
844 gc->direction_output = iproc_gpio_direction_output;
845 gc->get_direction = iproc_gpio_get_direction;
846 gc->set = iproc_gpio_set;
847 gc->get = iproc_gpio_get;
848
849 chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
850 "gpio-ranges");
851
852
853 irq = platform_get_irq_optional(pdev, 0);
854 if (irq > 0) {
855 struct irq_chip *irqc;
856 struct gpio_irq_chip *girq;
857
858 irqc = &chip->irqchip;
859 irqc->name = dev_name(dev);
860 irqc->irq_ack = iproc_gpio_irq_ack;
861 irqc->irq_mask = iproc_gpio_irq_mask;
862 irqc->irq_unmask = iproc_gpio_irq_unmask;
863 irqc->irq_set_type = iproc_gpio_irq_set_type;
864 irqc->irq_enable = iproc_gpio_irq_unmask;
865 irqc->irq_disable = iproc_gpio_irq_mask;
866
867 girq = &gc->irq;
868 girq->chip = irqc;
869 girq->parent_handler = iproc_gpio_irq_handler;
870 girq->num_parents = 1;
871 girq->parents = devm_kcalloc(dev, 1,
872 sizeof(*girq->parents),
873 GFP_KERNEL);
874 if (!girq->parents)
875 return -ENOMEM;
876 girq->parents[0] = irq;
877 girq->default_type = IRQ_TYPE_NONE;
878 girq->handler = handle_bad_irq;
879 }
880
881 ret = gpiochip_add_data(gc, chip);
882 if (ret < 0) {
883 dev_err(dev, "unable to add GPIO chip\n");
884 return ret;
885 }
886
887 if (!no_pinconf) {
888 ret = iproc_gpio_register_pinconf(chip);
889 if (ret) {
890 dev_err(dev, "unable to register pinconf\n");
891 goto err_rm_gpiochip;
892 }
893
894 if (pinconf_disable_mask) {
895 ret = iproc_pinconf_disable_map_create(chip,
896 pinconf_disable_mask);
897 if (ret) {
898 dev_err(dev,
899 "unable to create pinconf disable map\n");
900 goto err_rm_gpiochip;
901 }
902 }
903 }
904
905 return 0;
906
907err_rm_gpiochip:
908 gpiochip_remove(gc);
909
910 return ret;
911}
912
913static struct platform_driver iproc_gpio_driver = {
914 .driver = {
915 .name = "iproc-gpio",
916 .of_match_table = iproc_gpio_of_match,
917 },
918 .probe = iproc_gpio_probe,
919};
920
921static int __init iproc_gpio_init(void)
922{
923 return platform_driver_register(&iproc_gpio_driver);
924}
925arch_initcall_sync(iproc_gpio_init);
926
