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8#include <linux/bitops.h>
9#include <linux/bitfield.h>
10#include <linux/clk.h>
11#include <linux/iopoll.h>
12#include <linux/mfd/syscon.h>
13#include <linux/module.h>
14#include <linux/of_device.h>
15#include <linux/phy/phy.h>
16#include <linux/platform_device.h>
17#include <linux/regmap.h>
18#include <linux/reset.h>
19#include <linux/resource.h>
20
21
22#define PCL_PHY_CLKCTRL 0x0000
23#define PORT_SEL_MASK GENMASK(11, 9)
24#define PORT_SEL_1 FIELD_PREP(PORT_SEL_MASK, 1)
25
26#define PCL_PHY_TEST_I 0x2000
27#define TESTI_DAT_MASK GENMASK(13, 6)
28#define TESTI_ADR_MASK GENMASK(5, 1)
29#define TESTI_WR_EN BIT(0)
30
31#define PCL_PHY_TEST_O 0x2004
32#define TESTO_DAT_MASK GENMASK(7, 0)
33
34#define PCL_PHY_RESET 0x200c
35#define PCL_PHY_RESET_N_MNMODE BIT(8)
36#define PCL_PHY_RESET_N BIT(0)
37
38
39#define SG_USBPCIESEL 0x590
40#define SG_USBPCIESEL_PCIE BIT(0)
41
42#define PCL_PHY_R00 0
43#define RX_EQ_ADJ_EN BIT(3)
44#define PCL_PHY_R06 6
45#define RX_EQ_ADJ GENMASK(5, 0)
46#define RX_EQ_ADJ_VAL 0
47#define PCL_PHY_R26 26
48#define VCO_CTRL GENMASK(7, 4)
49#define VCO_CTRL_INIT_VAL 5
50
51struct uniphier_pciephy_priv {
52 void __iomem *base;
53 struct device *dev;
54 struct clk *clk, *clk_gio;
55 struct reset_control *rst, *rst_gio;
56 const struct uniphier_pciephy_soc_data *data;
57};
58
59struct uniphier_pciephy_soc_data {
60 bool is_legacy;
61 void (*set_phymode)(struct regmap *regmap);
62};
63
64static void uniphier_pciephy_testio_write(struct uniphier_pciephy_priv *priv,
65 u32 data)
66{
67
68 writel(data, priv->base + PCL_PHY_TEST_I);
69 readl(priv->base + PCL_PHY_TEST_O);
70 readl(priv->base + PCL_PHY_TEST_O);
71}
72
73static void uniphier_pciephy_set_param(struct uniphier_pciephy_priv *priv,
74 u32 reg, u32 mask, u32 param)
75{
76 u32 val;
77
78
79 val = FIELD_PREP(TESTI_DAT_MASK, 1);
80 val |= FIELD_PREP(TESTI_ADR_MASK, reg);
81 uniphier_pciephy_testio_write(priv, val);
82 val = readl(priv->base + PCL_PHY_TEST_O) & TESTO_DAT_MASK;
83
84
85 val &= ~mask;
86 val |= mask & param;
87 val = FIELD_PREP(TESTI_DAT_MASK, val);
88 val |= FIELD_PREP(TESTI_ADR_MASK, reg);
89 uniphier_pciephy_testio_write(priv, val);
90 uniphier_pciephy_testio_write(priv, val | TESTI_WR_EN);
91 uniphier_pciephy_testio_write(priv, val);
92
93
94 val = FIELD_PREP(TESTI_DAT_MASK, 1);
95 val |= FIELD_PREP(TESTI_ADR_MASK, reg);
96 uniphier_pciephy_testio_write(priv, val);
97 readl(priv->base + PCL_PHY_TEST_O);
98}
99
100static void uniphier_pciephy_assert(struct uniphier_pciephy_priv *priv)
101{
102 u32 val;
103
104 val = readl(priv->base + PCL_PHY_RESET);
105 val &= ~PCL_PHY_RESET_N;
106 val |= PCL_PHY_RESET_N_MNMODE;
107 writel(val, priv->base + PCL_PHY_RESET);
108}
109
110static void uniphier_pciephy_deassert(struct uniphier_pciephy_priv *priv)
111{
112 u32 val;
113
114 val = readl(priv->base + PCL_PHY_RESET);
115 val |= PCL_PHY_RESET_N_MNMODE | PCL_PHY_RESET_N;
116 writel(val, priv->base + PCL_PHY_RESET);
117}
118
119static int uniphier_pciephy_init(struct phy *phy)
120{
121 struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
122 u32 val;
123 int ret;
124
125 ret = clk_prepare_enable(priv->clk);
126 if (ret)
127 return ret;
128
129 ret = clk_prepare_enable(priv->clk_gio);
130 if (ret)
131 goto out_clk_disable;
132
133 ret = reset_control_deassert(priv->rst);
134 if (ret)
135 goto out_clk_gio_disable;
136
137 ret = reset_control_deassert(priv->rst_gio);
138 if (ret)
139 goto out_rst_assert;
140
141
142 val = readl(priv->base + PCL_PHY_CLKCTRL);
143 val &= ~PORT_SEL_MASK;
144 val |= PORT_SEL_1;
145 writel(val, priv->base + PCL_PHY_CLKCTRL);
146
147
148 if (priv->data->is_legacy)
149 return 0;
150
151 uniphier_pciephy_set_param(priv, PCL_PHY_R00,
152 RX_EQ_ADJ_EN, RX_EQ_ADJ_EN);
153 uniphier_pciephy_set_param(priv, PCL_PHY_R06, RX_EQ_ADJ,
154 FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL));
155 uniphier_pciephy_set_param(priv, PCL_PHY_R26, VCO_CTRL,
156 FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL));
157 usleep_range(1, 10);
158
159 uniphier_pciephy_deassert(priv);
160 usleep_range(1, 10);
161
162 return 0;
163
164out_rst_assert:
165 reset_control_assert(priv->rst);
166out_clk_gio_disable:
167 clk_disable_unprepare(priv->clk_gio);
168out_clk_disable:
169 clk_disable_unprepare(priv->clk);
170
171 return ret;
172}
173
174static int uniphier_pciephy_exit(struct phy *phy)
175{
176 struct uniphier_pciephy_priv *priv = phy_get_drvdata(phy);
177
178 if (!priv->data->is_legacy)
179 uniphier_pciephy_assert(priv);
180 reset_control_assert(priv->rst_gio);
181 reset_control_assert(priv->rst);
182 clk_disable_unprepare(priv->clk_gio);
183 clk_disable_unprepare(priv->clk);
184
185 return 0;
186}
187
188static const struct phy_ops uniphier_pciephy_ops = {
189 .init = uniphier_pciephy_init,
190 .exit = uniphier_pciephy_exit,
191 .owner = THIS_MODULE,
192};
193
194static int uniphier_pciephy_probe(struct platform_device *pdev)
195{
196 struct uniphier_pciephy_priv *priv;
197 struct phy_provider *phy_provider;
198 struct device *dev = &pdev->dev;
199 struct regmap *regmap;
200 struct phy *phy;
201
202 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
203 if (!priv)
204 return -ENOMEM;
205
206 priv->data = of_device_get_match_data(dev);
207 if (WARN_ON(!priv->data))
208 return -EINVAL;
209
210 priv->dev = dev;
211
212 priv->base = devm_platform_ioremap_resource(pdev, 0);
213 if (IS_ERR(priv->base))
214 return PTR_ERR(priv->base);
215
216 if (priv->data->is_legacy) {
217 priv->clk_gio = devm_clk_get(dev, "gio");
218 if (IS_ERR(priv->clk_gio))
219 return PTR_ERR(priv->clk_gio);
220
221 priv->rst_gio =
222 devm_reset_control_get_shared(dev, "gio");
223 if (IS_ERR(priv->rst_gio))
224 return PTR_ERR(priv->rst_gio);
225
226 priv->clk = devm_clk_get(dev, "link");
227 if (IS_ERR(priv->clk))
228 return PTR_ERR(priv->clk);
229
230 priv->rst = devm_reset_control_get_shared(dev, "link");
231 if (IS_ERR(priv->rst))
232 return PTR_ERR(priv->rst);
233 } else {
234 priv->clk = devm_clk_get(dev, NULL);
235 if (IS_ERR(priv->clk))
236 return PTR_ERR(priv->clk);
237
238 priv->rst = devm_reset_control_get_shared(dev, NULL);
239 if (IS_ERR(priv->rst))
240 return PTR_ERR(priv->rst);
241 }
242
243 phy = devm_phy_create(dev, dev->of_node, &uniphier_pciephy_ops);
244 if (IS_ERR(phy))
245 return PTR_ERR(phy);
246
247 regmap = syscon_regmap_lookup_by_phandle(dev->of_node,
248 "socionext,syscon");
249 if (!IS_ERR(regmap) && priv->data->set_phymode)
250 priv->data->set_phymode(regmap);
251
252 phy_set_drvdata(phy, priv);
253 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
254
255 return PTR_ERR_OR_ZERO(phy_provider);
256}
257
258static void uniphier_pciephy_ld20_setmode(struct regmap *regmap)
259{
260 regmap_update_bits(regmap, SG_USBPCIESEL,
261 SG_USBPCIESEL_PCIE, SG_USBPCIESEL_PCIE);
262}
263
264static const struct uniphier_pciephy_soc_data uniphier_pro5_data = {
265 .is_legacy = true,
266};
267
268static const struct uniphier_pciephy_soc_data uniphier_ld20_data = {
269 .is_legacy = false,
270 .set_phymode = uniphier_pciephy_ld20_setmode,
271};
272
273static const struct uniphier_pciephy_soc_data uniphier_pxs3_data = {
274 .is_legacy = false,
275};
276
277static const struct of_device_id uniphier_pciephy_match[] = {
278 {
279 .compatible = "socionext,uniphier-pro5-pcie-phy",
280 .data = &uniphier_pro5_data,
281 },
282 {
283 .compatible = "socionext,uniphier-ld20-pcie-phy",
284 .data = &uniphier_ld20_data,
285 },
286 {
287 .compatible = "socionext,uniphier-pxs3-pcie-phy",
288 .data = &uniphier_pxs3_data,
289 },
290 { },
291};
292MODULE_DEVICE_TABLE(of, uniphier_pciephy_match);
293
294static struct platform_driver uniphier_pciephy_driver = {
295 .probe = uniphier_pciephy_probe,
296 .driver = {
297 .name = "uniphier-pcie-phy",
298 .of_match_table = uniphier_pciephy_match,
299 },
300};
301module_platform_driver(uniphier_pciephy_driver);
302
303MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>");
304MODULE_DESCRIPTION("UniPhier PHY driver for PCIe controller");
305MODULE_LICENSE("GPL v2");
306
