1/* SPDX-License-Identifier: GPL-2.0 */ 2/* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6#ifndef QCOM_PHY_QMP_H_ 7#define QCOM_PHY_QMP_H_ 8 9/* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 10 11#define QSERDES_PLL_BG_TIMER 0x00c 12#define QSERDES_PLL_SSC_PER1 0x01c 13#define QSERDES_PLL_SSC_PER2 0x020 14#define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 15#define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 16#define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 17#define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 18#define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 19#define QSERDES_PLL_CLK_ENABLE1 0x040 20#define QSERDES_PLL_SYS_CLK_CTRL 0x044 21#define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 22#define QSERDES_PLL_PLL_IVCO 0x050 23#define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 24#define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 25#define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 26#define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 27#define QSERDES_PLL_BG_TRIM 0x074 28#define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 29#define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 30#define QSERDES_PLL_CP_CTRL_MODE0 0x080 31#define QSERDES_PLL_CP_CTRL_MODE1 0x084 32#define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 33#define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C 34#define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 35#define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 36#define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 37#define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 38#define QSERDES_PLL_RESETSM_CNTRL 0x0b0 39#define QSERDES_PLL_LOCK_CMP_EN 0x0c4 40#define QSERDES_PLL_DEC_START_MODE0 0x0cc 41#define QSERDES_PLL_DEC_START_MODE1 0x0d0 42#define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 43#define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 44#define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 45#define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 46#define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 47#define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC 48#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 49#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 50#define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 51#define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 52#define QSERDES_PLL_VCO_TUNE_MAP 0x120 53#define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 54#define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 55#define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 56#define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 57#define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 58#define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 59#define QSERDES_PLL_CLK_SELECT 0x16c 60#define QSERDES_PLL_HSCLK_SEL 0x170 61#define QSERDES_PLL_CORECLK_DIV 0x17c 62#define QSERDES_PLL_CORE_CLK_EN 0x184 63#define QSERDES_PLL_CMN_CONFIG 0x18c 64#define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 65#define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 66 67/* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */ 68 69#define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c 70#define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 71#define QSERDES_TX0_LANE_MODE_1 0x084 72#define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c 73 74/* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */ 75 76#define QSERDES_RX0_UCDR_FO_GAIN 0x008 77#define QSERDES_RX0_UCDR_SO_GAIN 0x014 78#define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 79#define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 80#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec 81#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 82#define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 83#define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 84#define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc 85#define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 86#define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 87#define QSERDES_RX0_SIGDET_ENABLES 0x118 88#define QSERDES_RX0_SIGDET_CNTRL 0x11c 89#define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 90#define QSERDES_RX0_RX_MODE_00_LOW 0x170 91#define QSERDES_RX0_RX_MODE_00_HIGH 0x174 92#define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 93#define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c 94#define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 95#define QSERDES_RX0_RX_MODE_01_LOW 0x184 96#define QSERDES_RX0_RX_MODE_01_HIGH 0x188 97#define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c 98#define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 99#define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 100#define QSERDES_RX0_RX_MODE_10_LOW 0x198 101#define QSERDES_RX0_RX_MODE_10_HIGH 0x19c 102#define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 103#define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 104#define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 105#define QSERDES_RX0_DFE_EN_TIMER 0x1b4 106 107/* QMP V2 PHY for PCIE gen3 ports - PCS registers */ 108 109#define PCS_COM_FLL_CNTRL1 0x098 110#define PCS_COM_FLL_CNTRL2 0x09c 111#define PCS_COM_FLL_CNT_VAL_L 0x0a0 112#define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 113#define PCS_COM_FLL_MAN_CODE 0x0a8 114#define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc 115#define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c 116#define PCS_COM_RX_SIGDET_LVL 0x188 117#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 118#define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 119#define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 120#define PCS_COM_EQ_CONFIG5 0x1ec 121 122/* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */ 123 124#define PCS_PCIE_POWER_STATE_CONFIG2 0x40c 125#define PCS_PCIE_POWER_STATE_CONFIG4 0x414 126#define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c 127#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 128#define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 129#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 130#define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c 131#define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c 132#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 133#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 134#define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 135#define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 136#define PCS_PCIE_EQ_CONFIG1 0x4a0 137#define PCS_PCIE_EQ_CONFIG2 0x4a4 138#define PCS_PCIE_PRESET_P10_PRE 0x4bc 139#define PCS_PCIE_PRESET_P10_POST 0x4e0 140 141/* Only for QMP V2 PHY - QSERDES COM registers */ 142#define QSERDES_COM_BG_TIMER 0x00c 143#define QSERDES_COM_SSC_EN_CENTER 0x010 144#define QSERDES_COM_SSC_ADJ_PER1 0x014 145#define QSERDES_COM_SSC_ADJ_PER2 0x018 146#define QSERDES_COM_SSC_PER1 0x01c 147#define QSERDES_COM_SSC_PER2 0x020 148#define QSERDES_COM_SSC_STEP_SIZE1 0x024 149#define QSERDES_COM_SSC_STEP_SIZE2 0x028 150#define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 151#define QSERDES_COM_CLK_ENABLE1 0x038 152#define QSERDES_COM_SYS_CLK_CTRL 0x03c 153#define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 154#define QSERDES_COM_PLL_IVCO 0x048 155#define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 156#define QSERDES_COM_LOCK_CMP2_MODE0 0x050 157#define QSERDES_COM_LOCK_CMP3_MODE0 0x054 158#define QSERDES_COM_LOCK_CMP1_MODE1 0x058 159#define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 160#define QSERDES_COM_LOCK_CMP3_MODE1 0x060 161#define QSERDES_COM_BG_TRIM 0x070 162#define QSERDES_COM_CLK_EP_DIV 0x074 163#define QSERDES_COM_CP_CTRL_MODE0 0x078 164#define QSERDES_COM_CP_CTRL_MODE1 0x07c 165#define QSERDES_COM_PLL_RCTRL_MODE0 0x084 166#define QSERDES_COM_PLL_RCTRL_MODE1 0x088 167#define QSERDES_COM_PLL_CCTRL_MODE0 0x090 168#define QSERDES_COM_PLL_CCTRL_MODE1 0x094 169#define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 170#define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 171#define QSERDES_COM_RESETSM_CNTRL 0x0b4 172#define QSERDES_COM_RESTRIM_CTRL 0x0bc 173#define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 174#define QSERDES_COM_LOCK_CMP_EN 0x0c8 175#define QSERDES_COM_LOCK_CMP_CFG 0x0cc 176#define QSERDES_COM_DEC_START_MODE0 0x0d0 177#define QSERDES_COM_DEC_START_MODE1 0x0d4 178#define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 179#define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 180#define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 181#define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 182#define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 183#define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 184#define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 185#define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 186#define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 187#define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 188#define QSERDES_COM_VCO_TUNE_CTRL 0x124 189#define QSERDES_COM_VCO_TUNE_MAP 0x128 190#define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 191#define QSERDES_COM_VCO_TUNE2_MODE0 0x130 192#define QSERDES_COM_VCO_TUNE1_MODE1 0x134 193#define QSERDES_COM_VCO_TUNE2_MODE1 0x138 194#define QSERDES_COM_VCO_TUNE_TIMER1 0x144 195#define QSERDES_COM_VCO_TUNE_TIMER2 0x148 196#define QSERDES_COM_BG_CTRL 0x170 197#define QSERDES_COM_CLK_SELECT 0x174 198#define QSERDES_COM_HSCLK_SEL 0x178 199#define QSERDES_COM_CORECLK_DIV 0x184 200#define QSERDES_COM_CORE_CLK_EN 0x18c 201#define QSERDES_COM_C_READY_STATUS 0x190 202#define QSERDES_COM_CMN_CONFIG 0x194 203#define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 204#define QSERDES_COM_DEBUG_BUS0 0x1a0 205#define QSERDES_COM_DEBUG_BUS1 0x1a4 206#define QSERDES_COM_DEBUG_BUS2 0x1a8 207#define QSERDES_COM_DEBUG_BUS3 0x1ac 208#define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 209#define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 210 211/* Only for QMP V2 PHY - TX registers */ 212#define QSERDES_TX_EMP_POST1_LVL 0x018 213#define QSERDES_TX_SLEW_CNTL 0x040 214#define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 215#define QSERDES_TX_DEBUG_BUS_SEL 0x064 216#define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 217#define QSERDES_TX_LANE_MODE 0x094 218#define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 219 220/* Only for QMP V2 PHY - RX registers */ 221#define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 222#define QSERDES_RX_UCDR_SO_GAIN 0x01c 223#define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 224#define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 225#define QSERDES_RX_RX_TERM_BW 0x090 226#define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 227#define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 228#define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 229#define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 230#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 231#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 232#define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 233#define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 234#define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 235#define QSERDES_RX_SIGDET_ENABLES 0x110 236#define QSERDES_RX_SIGDET_CNTRL 0x114 237#define QSERDES_RX_SIGDET_LVL 0x118 238#define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 239#define QSERDES_RX_RX_BAND 0x120 240#define QSERDES_RX_RX_INTERFACE_MODE 0x12c 241 242/* Only for QMP V2 PHY - PCS registers */ 243#define QPHY_POWER_DOWN_CONTROL 0x04 244#define QPHY_TXDEEMPH_M6DB_V0 0x24 245#define QPHY_TXDEEMPH_M3P5DB_V0 0x28 246#define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 247#define QPHY_RX_IDLE_DTCT_CNTRL 0x58 248#define QPHY_POWER_STATE_CONFIG1 0x60 249#define QPHY_POWER_STATE_CONFIG2 0x64 250#define QPHY_POWER_STATE_CONFIG4 0x6c 251#define QPHY_LOCK_DETECT_CONFIG1 0x80 252#define QPHY_LOCK_DETECT_CONFIG2 0x84 253#define QPHY_LOCK_DETECT_CONFIG3 0x88 254#define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 255#define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 256#define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 257#define QPHY_OSC_DTCT_ACTIONS 0x1AC 258#define QPHY_RX_SIGDET_LVL 0x1D8 259#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 260#define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 261 262/* Only for QMP V3 & V4 PHY - DP COM registers */ 263#define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 264#define QPHY_V3_DP_COM_SW_RESET 0x04 265#define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 266#define QPHY_V3_DP_COM_SWI_CTRL 0x0c 267#define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 268#define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 269#define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 270 271/* Only for QMP V3 PHY - QSERDES COM registers */ 272#define QSERDES_V3_COM_ATB_SEL1 0x000 273#define QSERDES_V3_COM_ATB_SEL2 0x004 274#define QSERDES_V3_COM_FREQ_UPDATE 0x008 275#define QSERDES_V3_COM_BG_TIMER 0x00c 276#define QSERDES_V3_COM_SSC_EN_CENTER 0x010 277#define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 278#define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 279#define QSERDES_V3_COM_SSC_PER1 0x01c 280#define QSERDES_V3_COM_SSC_PER2 0x020 281#define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 282#define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 283#define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 284# define QSERDES_V3_COM_BIAS_EN 0x0001 285# define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 286# define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 287# define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 288# define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 289# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 290# define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 291#define QSERDES_V3_COM_CLK_ENABLE1 0x038 292#define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 293#define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 294#define QSERDES_V3_COM_PLL_IVCO 0x048 295#define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 296#define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 297#define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 298#define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 299#define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 300#define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 301#define QSERDES_V3_COM_CLK_EP_DIV 0x05c 302#define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 303#define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 304#define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 305#define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 306#define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 307#define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 308#define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 309#define QSERDES_V3_COM_RESETSM_CNTRL 0x088 310#define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 311#define QSERDES_V3_COM_LOCK_CMP_EN 0x090 312#define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 313#define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 314#define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 315#define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 316#define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 317#define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 318#define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 319#define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 320#define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 321#define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 322#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 323#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 324#define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 325#define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 326#define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 327#define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 328#define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 329#define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 330#define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 331#define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 332#define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 333#define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 334#define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 335#define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 336#define QSERDES_V3_COM_CLK_SELECT 0x138 337#define QSERDES_V3_COM_HSCLK_SEL 0x13c 338#define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 339#define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 340#define QSERDES_V3_COM_CORE_CLK_EN 0x154 341#define QSERDES_V3_COM_C_READY_STATUS 0x158 342#define QSERDES_V3_COM_CMN_CONFIG 0x15c 343#define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 344#define QSERDES_V3_COM_DEBUG_BUS0 0x168 345#define QSERDES_V3_COM_DEBUG_BUS1 0x16c 346#define QSERDES_V3_COM_DEBUG_BUS2 0x170 347#define QSERDES_V3_COM_DEBUG_BUS3 0x174 348#define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 349#define QSERDES_V3_COM_CMN_MODE 0x184 350 351/* Only for QMP V3 PHY - TX registers */ 352#define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 353#define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 354#define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 355# define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 356# define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 357 358#define QSERDES_V3_TX_TX_DRV_LVL 0x01c 359# define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 360# define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 361 362#define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 363#define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 364 365#define QSERDES_V3_TX_TX_BAND 0x02c 366#define QSERDES_V3_TX_SLEW_CNTL 0x030 367#define QSERDES_V3_TX_INTERFACE_SELECT 0x034 368#define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 369#define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 370#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 371#define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 372#define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 373#define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 374#define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 375#define QSERDES_V3_TX_TX_POL_INV 0x064 376#define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 377#define QSERDES_V3_TX_LANE_MODE_1 0x08c 378#define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 379#define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 380#define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 381#define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 382 383/* Only for QMP V3 PHY - RX registers */ 384#define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 385#define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 386#define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 387#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 388#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 389#define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 390#define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 391#define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 392#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 393#define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 394#define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 395#define QSERDES_V3_RX_RX_TERM_BW 0x07c 396#define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 397#define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 398#define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 399#define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 400#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 401#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 402#define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 403#define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 404#define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 405#define QSERDES_V3_RX_SIGDET_ENABLES 0x100 406#define QSERDES_V3_RX_SIGDET_CNTRL 0x104 407#define QSERDES_V3_RX_SIGDET_LVL 0x108 408#define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 409#define QSERDES_V3_RX_RX_BAND 0x110 410#define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 411#define QSERDES_V3_RX_RX_MODE_00 0x164 412#define QSERDES_V3_RX_RX_MODE_01 0x168 413 414/* Only for QMP V3 PHY - PCS registers */ 415#define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 416#define QPHY_V3_PCS_TXMGN_V0 0x00c 417#define QPHY_V3_PCS_TXMGN_V1 0x010 418#define QPHY_V3_PCS_TXMGN_V2 0x014 419#define QPHY_V3_PCS_TXMGN_V3 0x018 420#define QPHY_V3_PCS_TXMGN_V4 0x01c 421#define QPHY_V3_PCS_TXMGN_LS 0x020 422#define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 423#define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 424#define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 425#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 426#define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 427#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 428#define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 429#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 430#define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 431#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 432#define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 433#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 434#define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 435#define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 436#define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 437#define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 438#define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 439#define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 440#define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 441#define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 442#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 443#define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 444#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 445#define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 446#define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 447#define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 448#define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 449#define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 450#define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 451#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 452#define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 453#define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 454#define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 455#define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 456#define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 457#define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 458#define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 459#define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 460#define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 461#define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 462#define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 463#define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 464#define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 465#define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 466#define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 467#define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 468#define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 469#define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 470#define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 471#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 472#define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 473#define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 474#define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 475 476/* Only for QMP V3 PHY - PCS_MISC registers */ 477#define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 478#define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 479#define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 480#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 481#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 482#define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 483 484/* QMP PHY - DP PHY registers */ 485#define QSERDES_DP_PHY_REVISION_ID0 0x000 486#define QSERDES_DP_PHY_REVISION_ID1 0x004 487#define QSERDES_DP_PHY_REVISION_ID2 0x008 488#define QSERDES_DP_PHY_REVISION_ID3 0x00c 489#define QSERDES_DP_PHY_CFG 0x010 490#define QSERDES_DP_PHY_PD_CTL 0x018 491# define DP_PHY_PD_CTL_PWRDN 0x001 492# define DP_PHY_PD_CTL_PSR_PWRDN 0x002 493# define DP_PHY_PD_CTL_AUX_PWRDN 0x004 494# define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 495# define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 496# define DP_PHY_PD_CTL_PLL_PWRDN 0x020 497# define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 498#define QSERDES_DP_PHY_MODE 0x01c 499#define QSERDES_DP_PHY_AUX_CFG0 0x020 500#define QSERDES_DP_PHY_AUX_CFG1 0x024 501#define QSERDES_DP_PHY_AUX_CFG2 0x028 502#define QSERDES_DP_PHY_AUX_CFG3 0x02c 503#define QSERDES_DP_PHY_AUX_CFG4 0x030 504#define QSERDES_DP_PHY_AUX_CFG5 0x034 505#define QSERDES_DP_PHY_AUX_CFG6 0x038 506#define QSERDES_DP_PHY_AUX_CFG7 0x03c 507#define QSERDES_DP_PHY_AUX_CFG8 0x040 508#define QSERDES_DP_PHY_AUX_CFG9 0x044 509 510/* Only for QMP V3 PHY - DP PHY registers */ 511#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 512# define PHY_AUX_STOP_ERR_MASK 0x01 513# define PHY_AUX_DEC_ERR_MASK 0x02 514# define PHY_AUX_SYNC_ERR_MASK 0x04 515# define PHY_AUX_ALIGN_ERR_MASK 0x08 516# define PHY_AUX_REQ_ERR_MASK 0x10 517 518#define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 519#define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 520 521#define QSERDES_V3_DP_PHY_VCO_DIV 0x064 522#define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 523#define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 524 525#define QSERDES_V3_DP_PHY_SPARE0 0x0ac 526#define DP_PHY_SPARE0_MASK 0x0f 527#define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 528 529#define QSERDES_V3_DP_PHY_STATUS 0x0c0 530 531/* Only for QMP V4 PHY - QSERDES COM registers */ 532#define QSERDES_V4_COM_BG_TIMER 0x00c 533#define QSERDES_V4_COM_SSC_EN_CENTER 0x010 534#define QSERDES_V4_COM_SSC_PER1 0x01c 535#define QSERDES_V4_COM_SSC_PER2 0x020 536#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 537#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 538#define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 539#define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 540#define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 541#define QSERDES_V4_COM_CLK_ENABLE1 0x048 542#define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 543#define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 544#define QSERDES_V4_COM_PLL_IVCO 0x058 545#define QSERDES_V4_COM_CMN_IPTRIM 0x060 546#define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 547#define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 548#define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 549#define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 550#define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 551#define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 552#define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 553#define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 554#define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 555#define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 556#define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 557#define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 558#define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 559#define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 560#define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 561#define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 562#define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 563#define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 564#define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 565#define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 566#define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 567#define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 568#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 569#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 570#define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 571#define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 572#define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 573#define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 574#define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 575#define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 576#define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 577#define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 578#define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 579#define QSERDES_V4_COM_CMN_STATUS 0x140 580#define QSERDES_V4_COM_CLK_SELECT 0x154 581#define QSERDES_V4_COM_HSCLK_SEL 0x158 582#define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 583#define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 584#define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 585#define QSERDES_V4_COM_CORE_CLK_EN 0x174 586#define QSERDES_V4_COM_C_READY_STATUS 0x178 587#define QSERDES_V4_COM_CMN_CONFIG 0x17c 588#define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 589#define QSERDES_V4_COM_CMN_MISC1 0x19c 590#define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 591#define QSERDES_V4_COM_CMN_MODE 0x1a4 592#define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 593#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 594#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 595#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 596#define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 597#define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 598 599/* Only for QMP V4 PHY - TX registers */ 600#define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 601#define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 602#define QSERDES_V4_TX_TX_DRV_LVL 0x14 603#define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 604#define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 605#define QSERDES_V4_TX_TX_BAND 0x24 606#define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 607#define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 608#define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 609#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 610#define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 611#define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 612#define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 613#define QSERDES_V4_TX_TX_POL_INV 0x5c 614#define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 615#define QSERDES_V4_TX_LANE_MODE_1 0x84 616#define QSERDES_V4_TX_LANE_MODE_2 0x88 617#define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 618#define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 619#define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 620#define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 621#define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 622#define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 623#define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 624#define QSERDES_V4_TX_VMODE_CTRL1 0xe8 625#define QSERDES_V4_TX_PI_QEC_CTRL 0x104 626 627/* Only for QMP V4_20 PHY - TX registers */ 628#define QSERDES_V4_20_TX_LANE_MODE_1 0x88 629#define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 630#define QSERDES_V4_20_TX_LANE_MODE_3 0x90 631#define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 632#define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 633 634/* Only for QMP V4 PHY - RX registers */ 635#define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 636#define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 637#define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 638#define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 639#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 640#define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 641#define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 642#define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 643#define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 644#define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 645#define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 646#define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 647#define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 648#define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 649#define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 650#define QSERDES_V4_RX_AC_JTAG_MODE 0x078 651#define QSERDES_V4_RX_RX_TERM_BW 0x080 652#define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 653#define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 654#define QSERDES_V4_RX_GM_CAL 0x0dc 655#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 656#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 657#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 658#define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 659#define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 660#define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 661#define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 662#define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 663#define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 664#define QSERDES_V4_RX_SIGDET_ENABLES 0x118 665#define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 666#define QSERDES_V4_RX_SIGDET_LVL 0x120 667#define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 668#define QSERDES_V4_RX_RX_BAND 0x128 669#define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 670#define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 671#define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 672#define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 673#define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 674#define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 675#define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 676#define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 677#define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 678#define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 679#define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 680#define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 681#define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 682#define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 683#define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 684#define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 685#define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 686#define QSERDES_V4_RX_DCC_CTRL1 0x1bc 687#define QSERDES_V4_RX_VTH_CODE 0x1c4 688 689/* Only for QMP V4 PHY - DP PHY registers */ 690#define QSERDES_V4_DP_PHY_CFG_1 0x014 691#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 692#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 693#define QSERDES_V4_DP_PHY_VCO_DIV 0x070 694#define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 695#define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 696#define QSERDES_V4_DP_PHY_SPARE0 0x0c8 697#define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 698#define QSERDES_V4_DP_PHY_STATUS 0x0dc 699 700/* Only for QMP V4_20 PHY - RX registers */ 701#define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 702#define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 703#define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 704#define QSERDES_V4_20_RX_DFE_3 0x110 705#define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 706#define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 707#define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 708#define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 709#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 710#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 711#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 712#define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 713#define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 714#define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 715#define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 716#define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 717#define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 718#define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 719#define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 720#define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 721#define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 722#define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 723#define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 724#define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 725#define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 726 727/* Only for QMP V4 PHY - UFS PCS registers */ 728#define QPHY_V4_PCS_UFS_PHY_START 0x000 729#define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 730#define QPHY_V4_PCS_UFS_SW_RESET 0x008 731#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 732#define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 733#define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 734#define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 735#define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 736#define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 737#define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 738#define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 739#define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 740#define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 741#define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 742#define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 743#define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 744#define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 745#define QPHY_V4_PCS_UFS_READY_STATUS 0x180 746#define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 747#define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 748 749/* PCIE GEN3 COM registers */ 750#define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 751#define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 752#define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 753#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 754#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 755#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 756#define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 757#define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 758#define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 759#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 760#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 761#define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 762#define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 763#define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 764#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 765#define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 766#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 767#define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 768#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 769#define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 770#define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 771#define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 772#define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 773#define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 774#define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 775#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 776#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 777#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 778#define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 779#define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 780#define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 781#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 782#define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 783#define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 784#define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 785#define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 786#define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 787#define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 788#define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 789#define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 790#define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 791#define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 792#define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 793#define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 794#define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 795 796/* PCIE GEN3 QHP Lane registers */ 797#define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 798#define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 799#define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 800#define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 801#define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 802#define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 803#define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 804#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 805#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 806#define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 807#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 808#define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 809#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 810#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 811#define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 812#define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 813#define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 814#define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 815#define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 816#define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 817#define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 818#define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 819#define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 820#define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 821#define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 822#define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 823#define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 824#define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 825#define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 826#define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 827#define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 828#define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 829#define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 830#define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 831#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 832#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 833#define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 834#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 835#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 836#define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 837#define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 838#define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 839#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 840#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 841#define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 842#define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 843#define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 844#define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 845#define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 846#define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 847#define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 848#define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 849#define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 850#define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 851#define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 852#define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 853 854/* PCIE GEN3 PCS registers */ 855#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 856#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 857#define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 858#define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 859#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 860#define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 861#define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 862 863/* Only for QMP V4 PHY - USB/PCIe PCS registers */ 864#define QPHY_V4_PCS_SW_RESET 0x000 865#define QPHY_V4_PCS_REVISION_ID0 0x004 866#define QPHY_V4_PCS_REVISION_ID1 0x008 867#define QPHY_V4_PCS_REVISION_ID2 0x00c 868#define QPHY_V4_PCS_REVISION_ID3 0x010 869#define QPHY_V4_PCS_PCS_STATUS1 0x014 870#define QPHY_V4_PCS_PCS_STATUS2 0x018 871#define QPHY_V4_PCS_PCS_STATUS3 0x01c 872#define QPHY_V4_PCS_PCS_STATUS4 0x020 873#define QPHY_V4_PCS_PCS_STATUS5 0x024 874#define QPHY_V4_PCS_PCS_STATUS6 0x028 875#define QPHY_V4_PCS_PCS_STATUS7 0x02c 876#define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 877#define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 878#define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 879#define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 880#define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 881#define QPHY_V4_PCS_START_CONTROL 0x044 882#define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 883#define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 884#define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 885#define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 886#define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 887#define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 888#define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 889#define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 890#define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 891#define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 892#define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 893#define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 894#define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 895#define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 896#define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 897#define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 898#define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 899#define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 900#define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 901#define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 902#define QPHY_V4_PCS_FLL_CNTRL1 0x098 903#define QPHY_V4_PCS_FLL_CNTRL2 0x09c 904#define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 905#define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 906#define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 907#define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 908#define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 909#define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 910#define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 911#define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 912#define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 913#define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 914#define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 915#define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 916#define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 917#define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 918#define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 919#define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 920#define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 921#define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 922#define QPHY_V4_PCS_BIST_CTRL 0x0e8 923#define QPHY_V4_PCS_PRBS_POLY0 0x0ec 924#define QPHY_V4_PCS_PRBS_POLY1 0x0f0 925#define QPHY_V4_PCS_FIXED_PAT0 0x0f4 926#define QPHY_V4_PCS_FIXED_PAT1 0x0f8 927#define QPHY_V4_PCS_FIXED_PAT2 0x0fc 928#define QPHY_V4_PCS_FIXED_PAT3 0x100 929#define QPHY_V4_PCS_FIXED_PAT4 0x104 930#define QPHY_V4_PCS_FIXED_PAT5 0x108 931#define QPHY_V4_PCS_FIXED_PAT6 0x10c 932#define QPHY_V4_PCS_FIXED_PAT7 0x110 933#define QPHY_V4_PCS_FIXED_PAT8 0x114 934#define QPHY_V4_PCS_FIXED_PAT9 0x118 935#define QPHY_V4_PCS_FIXED_PAT10 0x11c 936#define QPHY_V4_PCS_FIXED_PAT11 0x120 937#define QPHY_V4_PCS_FIXED_PAT12 0x124 938#define QPHY_V4_PCS_FIXED_PAT13 0x128 939#define QPHY_V4_PCS_FIXED_PAT14 0x12c 940#define QPHY_V4_PCS_FIXED_PAT15 0x130 941#define QPHY_V4_PCS_TXMGN_CONFIG 0x134 942#define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 943#define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 944#define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 945#define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 946#define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 947#define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 948#define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 949#define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 950#define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 951#define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 952#define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 953#define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 954#define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 955#define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 956#define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 957#define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 958#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 959#define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 960#define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 961#define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 962#define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 963#define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 964#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 965#define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 966#define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 967#define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 968#define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 969#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 970#define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 971#define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 972#define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 973#define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 974#define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 975#define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 976#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 977#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 978#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 979#define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 980#define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 981#define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 982#define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 983#define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 984#define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 985#define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 986#define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 987#define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 988#define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 989#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 990#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 991#define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 992#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 993#define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 994#define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 995#define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 996#define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 997#define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 998#define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 999#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 1000#define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330
1001#define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 1002#define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 1003#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 1004#define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 1005#define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 1006#define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 1007#define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 1008#define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 1009#define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 1010#define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 1011 1012/* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 1013#define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 1014#define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 1015#define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 1016#define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 1017 1018/* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 1019#define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 1020#define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 1021 1022/* Only for QMP V4 PHY - PCS_MISC registers */ 1023#define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 1024#define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 1025#define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 1026#define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 1027#define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 1028#define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 1029 1030/* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 1031#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 1032#define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 1033#define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 1034#define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 1035#define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 1036#define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 1037#define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 1038#define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 1039#define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 1040#define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 1041#define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 1042 1043#define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 1044#define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 1045#define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 1046#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 1047#define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1048#define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 1049#define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 1050 1051/* Only for QMP V5 PHY - QSERDES COM registers */ 1052#define QSERDES_V5_COM_PLL_IVCO 0x058 1053#define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 1054#define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 1055#define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 1056#define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 1057#define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 1058#define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 1059#define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 1060#define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 1061#define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 1062#define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 1063#define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 1064#define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 1065#define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 1066#define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 1067#define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 1068#define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 1069#define QSERDES_V5_COM_HSCLK_SEL 0x158 1070#define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 1071#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 1072#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 1073#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 1074#define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 1075#define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 1076 1077/* Only for QMP V5 PHY - TX registers */ 1078#define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 1079#define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 1080#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 1081#define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 1082#define QSERDES_V5_TX_LANE_MODE_1 0x84 1083#define QSERDES_V5_TX_LANE_MODE_2 0x88 1084#define QSERDES_V5_TX_LANE_MODE_3 0x8c 1085#define QSERDES_V5_TX_LANE_MODE_4 0x90 1086#define QSERDES_V5_TX_LANE_MODE_5 0x94 1087#define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 1088#define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 1089#define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 1090#define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 1091#define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 1092#define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 1093#define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 1094 1095/* Only for QMP V5 PHY - RX registers */ 1096#define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 1097#define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 1098#define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 1099#define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 1100#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 1101#define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 1102#define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 1103#define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 1104#define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 1105#define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 1106#define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 1107#define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 1108#define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 1109#define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 1110#define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 1111#define QSERDES_V5_RX_AC_JTAG_MODE 0x078 1112#define QSERDES_V5_RX_RX_TERM_BW 0x080 1113#define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 1114#define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 1115#define QSERDES_V5_RX_GM_CAL 0x0dc 1116#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 1117#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 1118#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 1119#define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 1120#define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 1121#define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 1122#define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 1123#define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 1124#define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 1125#define QSERDES_V5_RX_SIGDET_ENABLES 0x118 1126#define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 1127#define QSERDES_V5_RX_SIGDET_LVL 0x120 1128#define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 1129#define QSERDES_V5_RX_RX_BAND 0x128 1130#define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 1131#define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 1132#define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 1133#define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 1134#define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 1135#define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 1136#define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 1137#define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 1138#define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 1139#define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 1140#define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 1141#define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 1142#define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 1143#define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 1144#define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 1145#define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 1146#define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 1147#define QSERDES_V5_RX_DCC_CTRL1 0x1a8 1148#define QSERDES_V5_RX_VTH_CODE 0x1b0 1149 1150/* Only for QMP V5 PHY - UFS PCS registers */ 1151#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 1152#define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 1153#define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 1154#define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 1155#define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 1156#define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 1157#define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 1158#define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 1159#define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 1160#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 1161#define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 1162#define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 1163#define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 1164#define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 1165#define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 1166 1167/* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 1168#define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 1169#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 1170#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 1171#define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 1172#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 1173#define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 1174#define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 1175#define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c 1176#define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 1177#define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 1178#define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328 1179#define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c 1180#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330 1181#define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334 1182#define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338 1183#define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c 1184#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340 1185#define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344 1186#define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348 1187#define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c 1188#define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350 1189#define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354 1190#define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358 1191#define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c 1192#define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360 1193 1194/* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */ 1195#define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018 1196#define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c 1197 1198#endif 1199