linux/drivers/pci/controller/pcie-mediatek.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * MediaTek PCIe host controller driver.
   4 *
   5 * Copyright (c) 2017 MediaTek Inc.
   6 * Author: Ryder Lee <ryder.lee@mediatek.com>
   7 *         Honghui Zhang <honghui.zhang@mediatek.com>
   8 */
   9
  10#include <linux/clk.h>
  11#include <linux/delay.h>
  12#include <linux/iopoll.h>
  13#include <linux/irq.h>
  14#include <linux/irqchip/chained_irq.h>
  15#include <linux/irqdomain.h>
  16#include <linux/kernel.h>
  17#include <linux/msi.h>
  18#include <linux/module.h>
  19#include <linux/of_address.h>
  20#include <linux/of_pci.h>
  21#include <linux/of_platform.h>
  22#include <linux/pci.h>
  23#include <linux/phy/phy.h>
  24#include <linux/platform_device.h>
  25#include <linux/pm_runtime.h>
  26#include <linux/reset.h>
  27
  28#include "../pci.h"
  29
  30/* PCIe shared registers */
  31#define PCIE_SYS_CFG            0x00
  32#define PCIE_INT_ENABLE         0x0c
  33#define PCIE_CFG_ADDR           0x20
  34#define PCIE_CFG_DATA           0x24
  35
  36/* PCIe per port registers */
  37#define PCIE_BAR0_SETUP         0x10
  38#define PCIE_CLASS              0x34
  39#define PCIE_LINK_STATUS        0x50
  40
  41#define PCIE_PORT_INT_EN(x)     BIT(20 + (x))
  42#define PCIE_PORT_PERST(x)      BIT(1 + (x))
  43#define PCIE_PORT_LINKUP        BIT(0)
  44#define PCIE_BAR_MAP_MAX        GENMASK(31, 16)
  45
  46#define PCIE_BAR_ENABLE         BIT(0)
  47#define PCIE_REVISION_ID        BIT(0)
  48#define PCIE_CLASS_CODE         (0x60400 << 8)
  49#define PCIE_CONF_REG(regn)     (((regn) & GENMASK(7, 2)) | \
  50                                ((((regn) >> 8) & GENMASK(3, 0)) << 24))
  51#define PCIE_CONF_FUN(fun)      (((fun) << 8) & GENMASK(10, 8))
  52#define PCIE_CONF_DEV(dev)      (((dev) << 11) & GENMASK(15, 11))
  53#define PCIE_CONF_BUS(bus)      (((bus) << 16) & GENMASK(23, 16))
  54#define PCIE_CONF_ADDR(regn, fun, dev, bus) \
  55        (PCIE_CONF_REG(regn) | PCIE_CONF_FUN(fun) | \
  56         PCIE_CONF_DEV(dev) | PCIE_CONF_BUS(bus))
  57
  58/* MediaTek specific configuration registers */
  59#define PCIE_FTS_NUM            0x70c
  60#define PCIE_FTS_NUM_MASK       GENMASK(15, 8)
  61#define PCIE_FTS_NUM_L0(x)      ((x) & 0xff << 8)
  62
  63#define PCIE_FC_CREDIT          0x73c
  64#define PCIE_FC_CREDIT_MASK     (GENMASK(31, 31) | GENMASK(28, 16))
  65#define PCIE_FC_CREDIT_VAL(x)   ((x) << 16)
  66
  67/* PCIe V2 share registers */
  68#define PCIE_SYS_CFG_V2         0x0
  69#define PCIE_CSR_LTSSM_EN(x)    BIT(0 + (x) * 8)
  70#define PCIE_CSR_ASPM_L1_EN(x)  BIT(1 + (x) * 8)
  71
  72/* PCIe V2 per-port registers */
  73#define PCIE_MSI_VECTOR         0x0c0
  74
  75#define PCIE_CONF_VEND_ID       0x100
  76#define PCIE_CONF_DEVICE_ID     0x102
  77#define PCIE_CONF_CLASS_ID      0x106
  78
  79#define PCIE_INT_MASK           0x420
  80#define INTX_MASK               GENMASK(19, 16)
  81#define INTX_SHIFT              16
  82#define PCIE_INT_STATUS         0x424
  83#define MSI_STATUS              BIT(23)
  84#define PCIE_IMSI_STATUS        0x42c
  85#define PCIE_IMSI_ADDR          0x430
  86#define MSI_MASK                BIT(23)
  87#define MTK_MSI_IRQS_NUM        32
  88
  89#define PCIE_AHB_TRANS_BASE0_L  0x438
  90#define PCIE_AHB_TRANS_BASE0_H  0x43c
  91#define AHB2PCIE_SIZE(x)        ((x) & GENMASK(4, 0))
  92#define PCIE_AXI_WINDOW0        0x448
  93#define WIN_ENABLE              BIT(7)
  94/*
  95 * Define PCIe to AHB window size as 2^33 to support max 8GB address space
  96 * translate, support least 4GB DRAM size access from EP DMA(physical DRAM
  97 * start from 0x40000000).
  98 */
  99#define PCIE2AHB_SIZE   0x21
 100
 101/* PCIe V2 configuration transaction header */
 102#define PCIE_CFG_HEADER0        0x460
 103#define PCIE_CFG_HEADER1        0x464
 104#define PCIE_CFG_HEADER2        0x468
 105#define PCIE_CFG_WDATA          0x470
 106#define PCIE_APP_TLP_REQ        0x488
 107#define PCIE_CFG_RDATA          0x48c
 108#define APP_CFG_REQ             BIT(0)
 109#define APP_CPL_STATUS          GENMASK(7, 5)
 110
 111#define CFG_WRRD_TYPE_0         4
 112#define CFG_WR_FMT              2
 113#define CFG_RD_FMT              0
 114
 115#define CFG_DW0_LENGTH(length)  ((length) & GENMASK(9, 0))
 116#define CFG_DW0_TYPE(type)      (((type) << 24) & GENMASK(28, 24))
 117#define CFG_DW0_FMT(fmt)        (((fmt) << 29) & GENMASK(31, 29))
 118#define CFG_DW2_REGN(regn)      ((regn) & GENMASK(11, 2))
 119#define CFG_DW2_FUN(fun)        (((fun) << 16) & GENMASK(18, 16))
 120#define CFG_DW2_DEV(dev)        (((dev) << 19) & GENMASK(23, 19))
 121#define CFG_DW2_BUS(bus)        (((bus) << 24) & GENMASK(31, 24))
 122#define CFG_HEADER_DW0(type, fmt) \
 123        (CFG_DW0_LENGTH(1) | CFG_DW0_TYPE(type) | CFG_DW0_FMT(fmt))
 124#define CFG_HEADER_DW1(where, size) \
 125        (GENMASK(((size) - 1), 0) << ((where) & 0x3))
 126#define CFG_HEADER_DW2(regn, fun, dev, bus) \
 127        (CFG_DW2_REGN(regn) | CFG_DW2_FUN(fun) | \
 128        CFG_DW2_DEV(dev) | CFG_DW2_BUS(bus))
 129
 130#define PCIE_RST_CTRL           0x510
 131#define PCIE_PHY_RSTB           BIT(0)
 132#define PCIE_PIPE_SRSTB         BIT(1)
 133#define PCIE_MAC_SRSTB          BIT(2)
 134#define PCIE_CRSTB              BIT(3)
 135#define PCIE_PERSTB             BIT(8)
 136#define PCIE_LINKDOWN_RST_EN    GENMASK(15, 13)
 137#define PCIE_LINK_STATUS_V2     0x804
 138#define PCIE_PORT_LINKUP_V2     BIT(10)
 139
 140struct mtk_pcie_port;
 141
 142/**
 143 * struct mtk_pcie_soc - differentiate between host generations
 144 * @need_fix_class_id: whether this host's class ID needed to be fixed or not
 145 * @need_fix_device_id: whether this host's device ID needed to be fixed or not
 146 * @no_msi: Bridge has no MSI support, and relies on an external block
 147 * @device_id: device ID which this host need to be fixed
 148 * @ops: pointer to configuration access functions
 149 * @startup: pointer to controller setting functions
 150 * @setup_irq: pointer to initialize IRQ functions
 151 */
 152struct mtk_pcie_soc {
 153        bool need_fix_class_id;
 154        bool need_fix_device_id;
 155        bool no_msi;
 156        unsigned int device_id;
 157        struct pci_ops *ops;
 158        int (*startup)(struct mtk_pcie_port *port);
 159        int (*setup_irq)(struct mtk_pcie_port *port, struct device_node *node);
 160};
 161
 162/**
 163 * struct mtk_pcie_port - PCIe port information
 164 * @base: IO mapped register base
 165 * @list: port list
 166 * @pcie: pointer to PCIe host info
 167 * @reset: pointer to port reset control
 168 * @sys_ck: pointer to transaction/data link layer clock
 169 * @ahb_ck: pointer to AHB slave interface operating clock for CSR access
 170 *          and RC initiated MMIO access
 171 * @axi_ck: pointer to application layer MMIO channel operating clock
 172 * @aux_ck: pointer to pe2_mac_bridge and pe2_mac_core operating clock
 173 *          when pcie_mac_ck/pcie_pipe_ck is turned off
 174 * @obff_ck: pointer to OBFF functional block operating clock
 175 * @pipe_ck: pointer to LTSSM and PHY/MAC layer operating clock
 176 * @phy: pointer to PHY control block
 177 * @slot: port slot
 178 * @irq: GIC irq
 179 * @irq_domain: legacy INTx IRQ domain
 180 * @inner_domain: inner IRQ domain
 181 * @msi_domain: MSI IRQ domain
 182 * @lock: protect the msi_irq_in_use bitmap
 183 * @msi_irq_in_use: bit map for assigned MSI IRQ
 184 */
 185struct mtk_pcie_port {
 186        void __iomem *base;
 187        struct list_head list;
 188        struct mtk_pcie *pcie;
 189        struct reset_control *reset;
 190        struct clk *sys_ck;
 191        struct clk *ahb_ck;
 192        struct clk *axi_ck;
 193        struct clk *aux_ck;
 194        struct clk *obff_ck;
 195        struct clk *pipe_ck;
 196        struct phy *phy;
 197        u32 slot;
 198        int irq;
 199        struct irq_domain *irq_domain;
 200        struct irq_domain *inner_domain;
 201        struct irq_domain *msi_domain;
 202        struct mutex lock;
 203        DECLARE_BITMAP(msi_irq_in_use, MTK_MSI_IRQS_NUM);
 204};
 205
 206/**
 207 * struct mtk_pcie - PCIe host information
 208 * @dev: pointer to PCIe device
 209 * @base: IO mapped register base
 210 * @free_ck: free-run reference clock
 211 * @mem: non-prefetchable memory resource
 212 * @ports: pointer to PCIe port information
 213 * @soc: pointer to SoC-dependent operations
 214 */
 215struct mtk_pcie {
 216        struct device *dev;
 217        void __iomem *base;
 218        struct clk *free_ck;
 219
 220        struct list_head ports;
 221        const struct mtk_pcie_soc *soc;
 222};
 223
 224static void mtk_pcie_subsys_powerdown(struct mtk_pcie *pcie)
 225{
 226        struct device *dev = pcie->dev;
 227
 228        clk_disable_unprepare(pcie->free_ck);
 229
 230        pm_runtime_put_sync(dev);
 231        pm_runtime_disable(dev);
 232}
 233
 234static void mtk_pcie_port_free(struct mtk_pcie_port *port)
 235{
 236        struct mtk_pcie *pcie = port->pcie;
 237        struct device *dev = pcie->dev;
 238
 239        devm_iounmap(dev, port->base);
 240        list_del(&port->list);
 241        devm_kfree(dev, port);
 242}
 243
 244static void mtk_pcie_put_resources(struct mtk_pcie *pcie)
 245{
 246        struct mtk_pcie_port *port, *tmp;
 247
 248        list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 249                phy_power_off(port->phy);
 250                phy_exit(port->phy);
 251                clk_disable_unprepare(port->pipe_ck);
 252                clk_disable_unprepare(port->obff_ck);
 253                clk_disable_unprepare(port->axi_ck);
 254                clk_disable_unprepare(port->aux_ck);
 255                clk_disable_unprepare(port->ahb_ck);
 256                clk_disable_unprepare(port->sys_ck);
 257                mtk_pcie_port_free(port);
 258        }
 259
 260        mtk_pcie_subsys_powerdown(pcie);
 261}
 262
 263static int mtk_pcie_check_cfg_cpld(struct mtk_pcie_port *port)
 264{
 265        u32 val;
 266        int err;
 267
 268        err = readl_poll_timeout_atomic(port->base + PCIE_APP_TLP_REQ, val,
 269                                        !(val & APP_CFG_REQ), 10,
 270                                        100 * USEC_PER_MSEC);
 271        if (err)
 272                return PCIBIOS_SET_FAILED;
 273
 274        if (readl(port->base + PCIE_APP_TLP_REQ) & APP_CPL_STATUS)
 275                return PCIBIOS_SET_FAILED;
 276
 277        return PCIBIOS_SUCCESSFUL;
 278}
 279
 280static int mtk_pcie_hw_rd_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
 281                              int where, int size, u32 *val)
 282{
 283        u32 tmp;
 284
 285        /* Write PCIe configuration transaction header for Cfgrd */
 286        writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_RD_FMT),
 287               port->base + PCIE_CFG_HEADER0);
 288        writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
 289        writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
 290               port->base + PCIE_CFG_HEADER2);
 291
 292        /* Trigger h/w to transmit Cfgrd TLP */
 293        tmp = readl(port->base + PCIE_APP_TLP_REQ);
 294        tmp |= APP_CFG_REQ;
 295        writel(tmp, port->base + PCIE_APP_TLP_REQ);
 296
 297        /* Check completion status */
 298        if (mtk_pcie_check_cfg_cpld(port))
 299                return PCIBIOS_SET_FAILED;
 300
 301        /* Read cpld payload of Cfgrd */
 302        *val = readl(port->base + PCIE_CFG_RDATA);
 303
 304        if (size == 1)
 305                *val = (*val >> (8 * (where & 3))) & 0xff;
 306        else if (size == 2)
 307                *val = (*val >> (8 * (where & 3))) & 0xffff;
 308
 309        return PCIBIOS_SUCCESSFUL;
 310}
 311
 312static int mtk_pcie_hw_wr_cfg(struct mtk_pcie_port *port, u32 bus, u32 devfn,
 313                              int where, int size, u32 val)
 314{
 315        /* Write PCIe configuration transaction header for Cfgwr */
 316        writel(CFG_HEADER_DW0(CFG_WRRD_TYPE_0, CFG_WR_FMT),
 317               port->base + PCIE_CFG_HEADER0);
 318        writel(CFG_HEADER_DW1(where, size), port->base + PCIE_CFG_HEADER1);
 319        writel(CFG_HEADER_DW2(where, PCI_FUNC(devfn), PCI_SLOT(devfn), bus),
 320               port->base + PCIE_CFG_HEADER2);
 321
 322        /* Write Cfgwr data */
 323        val = val << 8 * (where & 3);
 324        writel(val, port->base + PCIE_CFG_WDATA);
 325
 326        /* Trigger h/w to transmit Cfgwr TLP */
 327        val = readl(port->base + PCIE_APP_TLP_REQ);
 328        val |= APP_CFG_REQ;
 329        writel(val, port->base + PCIE_APP_TLP_REQ);
 330
 331        /* Check completion status */
 332        return mtk_pcie_check_cfg_cpld(port);
 333}
 334
 335static struct mtk_pcie_port *mtk_pcie_find_port(struct pci_bus *bus,
 336                                                unsigned int devfn)
 337{
 338        struct mtk_pcie *pcie = bus->sysdata;
 339        struct mtk_pcie_port *port;
 340        struct pci_dev *dev = NULL;
 341
 342        /*
 343         * Walk the bus hierarchy to get the devfn value
 344         * of the port in the root bus.
 345         */
 346        while (bus && bus->number) {
 347                dev = bus->self;
 348                bus = dev->bus;
 349                devfn = dev->devfn;
 350        }
 351
 352        list_for_each_entry(port, &pcie->ports, list)
 353                if (port->slot == PCI_SLOT(devfn))
 354                        return port;
 355
 356        return NULL;
 357}
 358
 359static int mtk_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
 360                                int where, int size, u32 *val)
 361{
 362        struct mtk_pcie_port *port;
 363        u32 bn = bus->number;
 364        int ret;
 365
 366        port = mtk_pcie_find_port(bus, devfn);
 367        if (!port) {
 368                *val = ~0;
 369                return PCIBIOS_DEVICE_NOT_FOUND;
 370        }
 371
 372        ret = mtk_pcie_hw_rd_cfg(port, bn, devfn, where, size, val);
 373        if (ret)
 374                *val = ~0;
 375
 376        return ret;
 377}
 378
 379static int mtk_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
 380                                 int where, int size, u32 val)
 381{
 382        struct mtk_pcie_port *port;
 383        u32 bn = bus->number;
 384
 385        port = mtk_pcie_find_port(bus, devfn);
 386        if (!port)
 387                return PCIBIOS_DEVICE_NOT_FOUND;
 388
 389        return mtk_pcie_hw_wr_cfg(port, bn, devfn, where, size, val);
 390}
 391
 392static struct pci_ops mtk_pcie_ops_v2 = {
 393        .read  = mtk_pcie_config_read,
 394        .write = mtk_pcie_config_write,
 395};
 396
 397static void mtk_compose_msi_msg(struct irq_data *data, struct msi_msg *msg)
 398{
 399        struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
 400        phys_addr_t addr;
 401
 402        /* MT2712/MT7622 only support 32-bit MSI addresses */
 403        addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
 404        msg->address_hi = 0;
 405        msg->address_lo = lower_32_bits(addr);
 406
 407        msg->data = data->hwirq;
 408
 409        dev_dbg(port->pcie->dev, "msi#%d address_hi %#x address_lo %#x\n",
 410                (int)data->hwirq, msg->address_hi, msg->address_lo);
 411}
 412
 413static int mtk_msi_set_affinity(struct irq_data *irq_data,
 414                                const struct cpumask *mask, bool force)
 415{
 416         return -EINVAL;
 417}
 418
 419static void mtk_msi_ack_irq(struct irq_data *data)
 420{
 421        struct mtk_pcie_port *port = irq_data_get_irq_chip_data(data);
 422        u32 hwirq = data->hwirq;
 423
 424        writel(1 << hwirq, port->base + PCIE_IMSI_STATUS);
 425}
 426
 427static struct irq_chip mtk_msi_bottom_irq_chip = {
 428        .name                   = "MTK MSI",
 429        .irq_compose_msi_msg    = mtk_compose_msi_msg,
 430        .irq_set_affinity       = mtk_msi_set_affinity,
 431        .irq_ack                = mtk_msi_ack_irq,
 432};
 433
 434static int mtk_pcie_irq_domain_alloc(struct irq_domain *domain, unsigned int virq,
 435                                     unsigned int nr_irqs, void *args)
 436{
 437        struct mtk_pcie_port *port = domain->host_data;
 438        unsigned long bit;
 439
 440        WARN_ON(nr_irqs != 1);
 441        mutex_lock(&port->lock);
 442
 443        bit = find_first_zero_bit(port->msi_irq_in_use, MTK_MSI_IRQS_NUM);
 444        if (bit >= MTK_MSI_IRQS_NUM) {
 445                mutex_unlock(&port->lock);
 446                return -ENOSPC;
 447        }
 448
 449        __set_bit(bit, port->msi_irq_in_use);
 450
 451        mutex_unlock(&port->lock);
 452
 453        irq_domain_set_info(domain, virq, bit, &mtk_msi_bottom_irq_chip,
 454                            domain->host_data, handle_edge_irq,
 455                            NULL, NULL);
 456
 457        return 0;
 458}
 459
 460static void mtk_pcie_irq_domain_free(struct irq_domain *domain,
 461                                     unsigned int virq, unsigned int nr_irqs)
 462{
 463        struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 464        struct mtk_pcie_port *port = irq_data_get_irq_chip_data(d);
 465
 466        mutex_lock(&port->lock);
 467
 468        if (!test_bit(d->hwirq, port->msi_irq_in_use))
 469                dev_err(port->pcie->dev, "trying to free unused MSI#%lu\n",
 470                        d->hwirq);
 471        else
 472                __clear_bit(d->hwirq, port->msi_irq_in_use);
 473
 474        mutex_unlock(&port->lock);
 475
 476        irq_domain_free_irqs_parent(domain, virq, nr_irqs);
 477}
 478
 479static const struct irq_domain_ops msi_domain_ops = {
 480        .alloc  = mtk_pcie_irq_domain_alloc,
 481        .free   = mtk_pcie_irq_domain_free,
 482};
 483
 484static struct irq_chip mtk_msi_irq_chip = {
 485        .name           = "MTK PCIe MSI",
 486        .irq_ack        = irq_chip_ack_parent,
 487        .irq_mask       = pci_msi_mask_irq,
 488        .irq_unmask     = pci_msi_unmask_irq,
 489};
 490
 491static struct msi_domain_info mtk_msi_domain_info = {
 492        .flags  = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 493                   MSI_FLAG_PCI_MSIX),
 494        .chip   = &mtk_msi_irq_chip,
 495};
 496
 497static int mtk_pcie_allocate_msi_domains(struct mtk_pcie_port *port)
 498{
 499        struct fwnode_handle *fwnode = of_node_to_fwnode(port->pcie->dev->of_node);
 500
 501        mutex_init(&port->lock);
 502
 503        port->inner_domain = irq_domain_create_linear(fwnode, MTK_MSI_IRQS_NUM,
 504                                                      &msi_domain_ops, port);
 505        if (!port->inner_domain) {
 506                dev_err(port->pcie->dev, "failed to create IRQ domain\n");
 507                return -ENOMEM;
 508        }
 509
 510        port->msi_domain = pci_msi_create_irq_domain(fwnode, &mtk_msi_domain_info,
 511                                                     port->inner_domain);
 512        if (!port->msi_domain) {
 513                dev_err(port->pcie->dev, "failed to create MSI domain\n");
 514                irq_domain_remove(port->inner_domain);
 515                return -ENOMEM;
 516        }
 517
 518        return 0;
 519}
 520
 521static void mtk_pcie_enable_msi(struct mtk_pcie_port *port)
 522{
 523        u32 val;
 524        phys_addr_t msg_addr;
 525
 526        msg_addr = virt_to_phys(port->base + PCIE_MSI_VECTOR);
 527        val = lower_32_bits(msg_addr);
 528        writel(val, port->base + PCIE_IMSI_ADDR);
 529
 530        val = readl(port->base + PCIE_INT_MASK);
 531        val &= ~MSI_MASK;
 532        writel(val, port->base + PCIE_INT_MASK);
 533}
 534
 535static void mtk_pcie_irq_teardown(struct mtk_pcie *pcie)
 536{
 537        struct mtk_pcie_port *port, *tmp;
 538
 539        list_for_each_entry_safe(port, tmp, &pcie->ports, list) {
 540                irq_set_chained_handler_and_data(port->irq, NULL, NULL);
 541
 542                if (port->irq_domain)
 543                        irq_domain_remove(port->irq_domain);
 544
 545                if (IS_ENABLED(CONFIG_PCI_MSI)) {
 546                        if (port->msi_domain)
 547                                irq_domain_remove(port->msi_domain);
 548                        if (port->inner_domain)
 549                                irq_domain_remove(port->inner_domain);
 550                }
 551
 552                irq_dispose_mapping(port->irq);
 553        }
 554}
 555
 556static int mtk_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
 557                             irq_hw_number_t hwirq)
 558{
 559        irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
 560        irq_set_chip_data(irq, domain->host_data);
 561
 562        return 0;
 563}
 564
 565static const struct irq_domain_ops intx_domain_ops = {
 566        .map = mtk_pcie_intx_map,
 567};
 568
 569static int mtk_pcie_init_irq_domain(struct mtk_pcie_port *port,
 570                                    struct device_node *node)
 571{
 572        struct device *dev = port->pcie->dev;
 573        struct device_node *pcie_intc_node;
 574        int ret;
 575
 576        /* Setup INTx */
 577        pcie_intc_node = of_get_next_child(node, NULL);
 578        if (!pcie_intc_node) {
 579                dev_err(dev, "no PCIe Intc node found\n");
 580                return -ENODEV;
 581        }
 582
 583        port->irq_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
 584                                                 &intx_domain_ops, port);
 585        of_node_put(pcie_intc_node);
 586        if (!port->irq_domain) {
 587                dev_err(dev, "failed to get INTx IRQ domain\n");
 588                return -ENODEV;
 589        }
 590
 591        if (IS_ENABLED(CONFIG_PCI_MSI)) {
 592                ret = mtk_pcie_allocate_msi_domains(port);
 593                if (ret)
 594                        return ret;
 595        }
 596
 597        return 0;
 598}
 599
 600static void mtk_pcie_intr_handler(struct irq_desc *desc)
 601{
 602        struct mtk_pcie_port *port = irq_desc_get_handler_data(desc);
 603        struct irq_chip *irqchip = irq_desc_get_chip(desc);
 604        unsigned long status;
 605        u32 virq;
 606        u32 bit = INTX_SHIFT;
 607
 608        chained_irq_enter(irqchip, desc);
 609
 610        status = readl(port->base + PCIE_INT_STATUS);
 611        if (status & INTX_MASK) {
 612                for_each_set_bit_from(bit, &status, PCI_NUM_INTX + INTX_SHIFT) {
 613                        /* Clear the INTx */
 614                        writel(1 << bit, port->base + PCIE_INT_STATUS);
 615                        virq = irq_find_mapping(port->irq_domain,
 616                                                bit - INTX_SHIFT);
 617                        generic_handle_irq(virq);
 618                }
 619        }
 620
 621        if (IS_ENABLED(CONFIG_PCI_MSI)) {
 622                if (status & MSI_STATUS){
 623                        unsigned long imsi_status;
 624
 625                        while ((imsi_status = readl(port->base + PCIE_IMSI_STATUS))) {
 626                                for_each_set_bit(bit, &imsi_status, MTK_MSI_IRQS_NUM) {
 627                                        virq = irq_find_mapping(port->inner_domain, bit);
 628                                        generic_handle_irq(virq);
 629                                }
 630                        }
 631                        /* Clear MSI interrupt status */
 632                        writel(MSI_STATUS, port->base + PCIE_INT_STATUS);
 633                }
 634        }
 635
 636        chained_irq_exit(irqchip, desc);
 637}
 638
 639static int mtk_pcie_setup_irq(struct mtk_pcie_port *port,
 640                              struct device_node *node)
 641{
 642        struct mtk_pcie *pcie = port->pcie;
 643        struct device *dev = pcie->dev;
 644        struct platform_device *pdev = to_platform_device(dev);
 645        int err;
 646
 647        err = mtk_pcie_init_irq_domain(port, node);
 648        if (err) {
 649                dev_err(dev, "failed to init PCIe IRQ domain\n");
 650                return err;
 651        }
 652
 653        port->irq = platform_get_irq(pdev, port->slot);
 654        if (port->irq < 0)
 655                return port->irq;
 656
 657        irq_set_chained_handler_and_data(port->irq,
 658                                         mtk_pcie_intr_handler, port);
 659
 660        return 0;
 661}
 662
 663static int mtk_pcie_startup_port_v2(struct mtk_pcie_port *port)
 664{
 665        struct mtk_pcie *pcie = port->pcie;
 666        struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
 667        struct resource *mem = NULL;
 668        struct resource_entry *entry;
 669        const struct mtk_pcie_soc *soc = port->pcie->soc;
 670        u32 val;
 671        int err;
 672
 673        entry = resource_list_first_type(&host->windows, IORESOURCE_MEM);
 674        if (entry)
 675                mem = entry->res;
 676        if (!mem)
 677                return -EINVAL;
 678
 679        /* MT7622 platforms need to enable LTSSM and ASPM from PCIe subsys */
 680        if (pcie->base) {
 681                val = readl(pcie->base + PCIE_SYS_CFG_V2);
 682                val |= PCIE_CSR_LTSSM_EN(port->slot) |
 683                       PCIE_CSR_ASPM_L1_EN(port->slot);
 684                writel(val, pcie->base + PCIE_SYS_CFG_V2);
 685        }
 686
 687        /* Assert all reset signals */
 688        writel(0, port->base + PCIE_RST_CTRL);
 689
 690        /*
 691         * Enable PCIe link down reset, if link status changed from link up to
 692         * link down, this will reset MAC control registers and configuration
 693         * space.
 694         */
 695        writel(PCIE_LINKDOWN_RST_EN, port->base + PCIE_RST_CTRL);
 696
 697        /* De-assert PHY, PE, PIPE, MAC and configuration reset */
 698        val = readl(port->base + PCIE_RST_CTRL);
 699        val |= PCIE_PHY_RSTB | PCIE_PERSTB | PCIE_PIPE_SRSTB |
 700               PCIE_MAC_SRSTB | PCIE_CRSTB;
 701        writel(val, port->base + PCIE_RST_CTRL);
 702
 703        /* Set up vendor ID and class code */
 704        if (soc->need_fix_class_id) {
 705                val = PCI_VENDOR_ID_MEDIATEK;
 706                writew(val, port->base + PCIE_CONF_VEND_ID);
 707
 708                val = PCI_CLASS_BRIDGE_PCI;
 709                writew(val, port->base + PCIE_CONF_CLASS_ID);
 710        }
 711
 712        if (soc->need_fix_device_id)
 713                writew(soc->device_id, port->base + PCIE_CONF_DEVICE_ID);
 714
 715        /* 100ms timeout value should be enough for Gen1/2 training */
 716        err = readl_poll_timeout(port->base + PCIE_LINK_STATUS_V2, val,
 717                                 !!(val & PCIE_PORT_LINKUP_V2), 20,
 718                                 100 * USEC_PER_MSEC);
 719        if (err)
 720                return -ETIMEDOUT;
 721
 722        /* Set INTx mask */
 723        val = readl(port->base + PCIE_INT_MASK);
 724        val &= ~INTX_MASK;
 725        writel(val, port->base + PCIE_INT_MASK);
 726
 727        if (IS_ENABLED(CONFIG_PCI_MSI))
 728                mtk_pcie_enable_msi(port);
 729
 730        /* Set AHB to PCIe translation windows */
 731        val = lower_32_bits(mem->start) |
 732              AHB2PCIE_SIZE(fls(resource_size(mem)));
 733        writel(val, port->base + PCIE_AHB_TRANS_BASE0_L);
 734
 735        val = upper_32_bits(mem->start);
 736        writel(val, port->base + PCIE_AHB_TRANS_BASE0_H);
 737
 738        /* Set PCIe to AXI translation memory space.*/
 739        val = PCIE2AHB_SIZE | WIN_ENABLE;
 740        writel(val, port->base + PCIE_AXI_WINDOW0);
 741
 742        return 0;
 743}
 744
 745static void __iomem *mtk_pcie_map_bus(struct pci_bus *bus,
 746                                      unsigned int devfn, int where)
 747{
 748        struct mtk_pcie *pcie = bus->sysdata;
 749
 750        writel(PCIE_CONF_ADDR(where, PCI_FUNC(devfn), PCI_SLOT(devfn),
 751                              bus->number), pcie->base + PCIE_CFG_ADDR);
 752
 753        return pcie->base + PCIE_CFG_DATA + (where & 3);
 754}
 755
 756static struct pci_ops mtk_pcie_ops = {
 757        .map_bus = mtk_pcie_map_bus,
 758        .read  = pci_generic_config_read,
 759        .write = pci_generic_config_write,
 760};
 761
 762static int mtk_pcie_startup_port(struct mtk_pcie_port *port)
 763{
 764        struct mtk_pcie *pcie = port->pcie;
 765        u32 func = PCI_FUNC(port->slot);
 766        u32 slot = PCI_SLOT(port->slot << 3);
 767        u32 val;
 768        int err;
 769
 770        /* assert port PERST_N */
 771        val = readl(pcie->base + PCIE_SYS_CFG);
 772        val |= PCIE_PORT_PERST(port->slot);
 773        writel(val, pcie->base + PCIE_SYS_CFG);
 774
 775        /* de-assert port PERST_N */
 776        val = readl(pcie->base + PCIE_SYS_CFG);
 777        val &= ~PCIE_PORT_PERST(port->slot);
 778        writel(val, pcie->base + PCIE_SYS_CFG);
 779
 780        /* 100ms timeout value should be enough for Gen1/2 training */
 781        err = readl_poll_timeout(port->base + PCIE_LINK_STATUS, val,
 782                                 !!(val & PCIE_PORT_LINKUP), 20,
 783                                 100 * USEC_PER_MSEC);
 784        if (err)
 785                return -ETIMEDOUT;
 786
 787        /* enable interrupt */
 788        val = readl(pcie->base + PCIE_INT_ENABLE);
 789        val |= PCIE_PORT_INT_EN(port->slot);
 790        writel(val, pcie->base + PCIE_INT_ENABLE);
 791
 792        /* map to all DDR region. We need to set it before cfg operation. */
 793        writel(PCIE_BAR_MAP_MAX | PCIE_BAR_ENABLE,
 794               port->base + PCIE_BAR0_SETUP);
 795
 796        /* configure class code and revision ID */
 797        writel(PCIE_CLASS_CODE | PCIE_REVISION_ID, port->base + PCIE_CLASS);
 798
 799        /* configure FC credit */
 800        writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
 801               pcie->base + PCIE_CFG_ADDR);
 802        val = readl(pcie->base + PCIE_CFG_DATA);
 803        val &= ~PCIE_FC_CREDIT_MASK;
 804        val |= PCIE_FC_CREDIT_VAL(0x806c);
 805        writel(PCIE_CONF_ADDR(PCIE_FC_CREDIT, func, slot, 0),
 806               pcie->base + PCIE_CFG_ADDR);
 807        writel(val, pcie->base + PCIE_CFG_DATA);
 808
 809        /* configure RC FTS number to 250 when it leaves L0s */
 810        writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
 811               pcie->base + PCIE_CFG_ADDR);
 812        val = readl(pcie->base + PCIE_CFG_DATA);
 813        val &= ~PCIE_FTS_NUM_MASK;
 814        val |= PCIE_FTS_NUM_L0(0x50);
 815        writel(PCIE_CONF_ADDR(PCIE_FTS_NUM, func, slot, 0),
 816               pcie->base + PCIE_CFG_ADDR);
 817        writel(val, pcie->base + PCIE_CFG_DATA);
 818
 819        return 0;
 820}
 821
 822static void mtk_pcie_enable_port(struct mtk_pcie_port *port)
 823{
 824        struct mtk_pcie *pcie = port->pcie;
 825        struct device *dev = pcie->dev;
 826        int err;
 827
 828        err = clk_prepare_enable(port->sys_ck);
 829        if (err) {
 830                dev_err(dev, "failed to enable sys_ck%d clock\n", port->slot);
 831                goto err_sys_clk;
 832        }
 833
 834        err = clk_prepare_enable(port->ahb_ck);
 835        if (err) {
 836                dev_err(dev, "failed to enable ahb_ck%d\n", port->slot);
 837                goto err_ahb_clk;
 838        }
 839
 840        err = clk_prepare_enable(port->aux_ck);
 841        if (err) {
 842                dev_err(dev, "failed to enable aux_ck%d\n", port->slot);
 843                goto err_aux_clk;
 844        }
 845
 846        err = clk_prepare_enable(port->axi_ck);
 847        if (err) {
 848                dev_err(dev, "failed to enable axi_ck%d\n", port->slot);
 849                goto err_axi_clk;
 850        }
 851
 852        err = clk_prepare_enable(port->obff_ck);
 853        if (err) {
 854                dev_err(dev, "failed to enable obff_ck%d\n", port->slot);
 855                goto err_obff_clk;
 856        }
 857
 858        err = clk_prepare_enable(port->pipe_ck);
 859        if (err) {
 860                dev_err(dev, "failed to enable pipe_ck%d\n", port->slot);
 861                goto err_pipe_clk;
 862        }
 863
 864        reset_control_assert(port->reset);
 865        reset_control_deassert(port->reset);
 866
 867        err = phy_init(port->phy);
 868        if (err) {
 869                dev_err(dev, "failed to initialize port%d phy\n", port->slot);
 870                goto err_phy_init;
 871        }
 872
 873        err = phy_power_on(port->phy);
 874        if (err) {
 875                dev_err(dev, "failed to power on port%d phy\n", port->slot);
 876                goto err_phy_on;
 877        }
 878
 879        if (!pcie->soc->startup(port))
 880                return;
 881
 882        dev_info(dev, "Port%d link down\n", port->slot);
 883
 884        phy_power_off(port->phy);
 885err_phy_on:
 886        phy_exit(port->phy);
 887err_phy_init:
 888        clk_disable_unprepare(port->pipe_ck);
 889err_pipe_clk:
 890        clk_disable_unprepare(port->obff_ck);
 891err_obff_clk:
 892        clk_disable_unprepare(port->axi_ck);
 893err_axi_clk:
 894        clk_disable_unprepare(port->aux_ck);
 895err_aux_clk:
 896        clk_disable_unprepare(port->ahb_ck);
 897err_ahb_clk:
 898        clk_disable_unprepare(port->sys_ck);
 899err_sys_clk:
 900        mtk_pcie_port_free(port);
 901}
 902
 903static int mtk_pcie_parse_port(struct mtk_pcie *pcie,
 904                               struct device_node *node,
 905                               int slot)
 906{
 907        struct mtk_pcie_port *port;
 908        struct device *dev = pcie->dev;
 909        struct platform_device *pdev = to_platform_device(dev);
 910        char name[10];
 911        int err;
 912
 913        port = devm_kzalloc(dev, sizeof(*port), GFP_KERNEL);
 914        if (!port)
 915                return -ENOMEM;
 916
 917        snprintf(name, sizeof(name), "port%d", slot);
 918        port->base = devm_platform_ioremap_resource_byname(pdev, name);
 919        if (IS_ERR(port->base)) {
 920                dev_err(dev, "failed to map port%d base\n", slot);
 921                return PTR_ERR(port->base);
 922        }
 923
 924        snprintf(name, sizeof(name), "sys_ck%d", slot);
 925        port->sys_ck = devm_clk_get(dev, name);
 926        if (IS_ERR(port->sys_ck)) {
 927                dev_err(dev, "failed to get sys_ck%d clock\n", slot);
 928                return PTR_ERR(port->sys_ck);
 929        }
 930
 931        /* sys_ck might be divided into the following parts in some chips */
 932        snprintf(name, sizeof(name), "ahb_ck%d", slot);
 933        port->ahb_ck = devm_clk_get_optional(dev, name);
 934        if (IS_ERR(port->ahb_ck))
 935                return PTR_ERR(port->ahb_ck);
 936
 937        snprintf(name, sizeof(name), "axi_ck%d", slot);
 938        port->axi_ck = devm_clk_get_optional(dev, name);
 939        if (IS_ERR(port->axi_ck))
 940                return PTR_ERR(port->axi_ck);
 941
 942        snprintf(name, sizeof(name), "aux_ck%d", slot);
 943        port->aux_ck = devm_clk_get_optional(dev, name);
 944        if (IS_ERR(port->aux_ck))
 945                return PTR_ERR(port->aux_ck);
 946
 947        snprintf(name, sizeof(name), "obff_ck%d", slot);
 948        port->obff_ck = devm_clk_get_optional(dev, name);
 949        if (IS_ERR(port->obff_ck))
 950                return PTR_ERR(port->obff_ck);
 951
 952        snprintf(name, sizeof(name), "pipe_ck%d", slot);
 953        port->pipe_ck = devm_clk_get_optional(dev, name);
 954        if (IS_ERR(port->pipe_ck))
 955                return PTR_ERR(port->pipe_ck);
 956
 957        snprintf(name, sizeof(name), "pcie-rst%d", slot);
 958        port->reset = devm_reset_control_get_optional_exclusive(dev, name);
 959        if (PTR_ERR(port->reset) == -EPROBE_DEFER)
 960                return PTR_ERR(port->reset);
 961
 962        /* some platforms may use default PHY setting */
 963        snprintf(name, sizeof(name), "pcie-phy%d", slot);
 964        port->phy = devm_phy_optional_get(dev, name);
 965        if (IS_ERR(port->phy))
 966                return PTR_ERR(port->phy);
 967
 968        port->slot = slot;
 969        port->pcie = pcie;
 970
 971        if (pcie->soc->setup_irq) {
 972                err = pcie->soc->setup_irq(port, node);
 973                if (err)
 974                        return err;
 975        }
 976
 977        INIT_LIST_HEAD(&port->list);
 978        list_add_tail(&port->list, &pcie->ports);
 979
 980        return 0;
 981}
 982
 983static int mtk_pcie_subsys_powerup(struct mtk_pcie *pcie)
 984{
 985        struct device *dev = pcie->dev;
 986        struct platform_device *pdev = to_platform_device(dev);
 987        struct resource *regs;
 988        int err;
 989
 990        /* get shared registers, which are optional */
 991        regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "subsys");
 992        if (regs) {
 993                pcie->base = devm_ioremap_resource(dev, regs);
 994                if (IS_ERR(pcie->base))
 995                        return PTR_ERR(pcie->base);
 996        }
 997
 998        pcie->free_ck = devm_clk_get(dev, "free_ck");
 999        if (IS_ERR(pcie->free_ck)) {
1000                if (PTR_ERR(pcie->free_ck) == -EPROBE_DEFER)
1001                        return -EPROBE_DEFER;
1002
1003                pcie->free_ck = NULL;
1004        }
1005
1006        pm_runtime_enable(dev);
1007        pm_runtime_get_sync(dev);
1008
1009        /* enable top level clock */
1010        err = clk_prepare_enable(pcie->free_ck);
1011        if (err) {
1012                dev_err(dev, "failed to enable free_ck\n");
1013                goto err_free_ck;
1014        }
1015
1016        return 0;
1017
1018err_free_ck:
1019        pm_runtime_put_sync(dev);
1020        pm_runtime_disable(dev);
1021
1022        return err;
1023}
1024
1025static int mtk_pcie_setup(struct mtk_pcie *pcie)
1026{
1027        struct device *dev = pcie->dev;
1028        struct device_node *node = dev->of_node, *child;
1029        struct mtk_pcie_port *port, *tmp;
1030        int err;
1031
1032        for_each_available_child_of_node(node, child) {
1033                int slot;
1034
1035                err = of_pci_get_devfn(child);
1036                if (err < 0) {
1037                        dev_err(dev, "failed to parse devfn: %d\n", err);
1038                        goto error_put_node;
1039                }
1040
1041                slot = PCI_SLOT(err);
1042
1043                err = mtk_pcie_parse_port(pcie, child, slot);
1044                if (err)
1045                        goto error_put_node;
1046        }
1047
1048        err = mtk_pcie_subsys_powerup(pcie);
1049        if (err)
1050                return err;
1051
1052        /* enable each port, and then check link status */
1053        list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1054                mtk_pcie_enable_port(port);
1055
1056        /* power down PCIe subsys if slots are all empty (link down) */
1057        if (list_empty(&pcie->ports))
1058                mtk_pcie_subsys_powerdown(pcie);
1059
1060        return 0;
1061error_put_node:
1062        of_node_put(child);
1063        return err;
1064}
1065
1066static int mtk_pcie_probe(struct platform_device *pdev)
1067{
1068        struct device *dev = &pdev->dev;
1069        struct mtk_pcie *pcie;
1070        struct pci_host_bridge *host;
1071        int err;
1072
1073        host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));
1074        if (!host)
1075                return -ENOMEM;
1076
1077        pcie = pci_host_bridge_priv(host);
1078
1079        pcie->dev = dev;
1080        pcie->soc = of_device_get_match_data(dev);
1081        platform_set_drvdata(pdev, pcie);
1082        INIT_LIST_HEAD(&pcie->ports);
1083
1084        err = mtk_pcie_setup(pcie);
1085        if (err)
1086                return err;
1087
1088        host->ops = pcie->soc->ops;
1089        host->sysdata = pcie;
1090        host->msi_domain = pcie->soc->no_msi;
1091
1092        err = pci_host_probe(host);
1093        if (err)
1094                goto put_resources;
1095
1096        return 0;
1097
1098put_resources:
1099        if (!list_empty(&pcie->ports))
1100                mtk_pcie_put_resources(pcie);
1101
1102        return err;
1103}
1104
1105
1106static void mtk_pcie_free_resources(struct mtk_pcie *pcie)
1107{
1108        struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1109        struct list_head *windows = &host->windows;
1110
1111        pci_free_resource_list(windows);
1112}
1113
1114static int mtk_pcie_remove(struct platform_device *pdev)
1115{
1116        struct mtk_pcie *pcie = platform_get_drvdata(pdev);
1117        struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1118
1119        pci_stop_root_bus(host->bus);
1120        pci_remove_root_bus(host->bus);
1121        mtk_pcie_free_resources(pcie);
1122
1123        mtk_pcie_irq_teardown(pcie);
1124
1125        mtk_pcie_put_resources(pcie);
1126
1127        return 0;
1128}
1129
1130static int __maybe_unused mtk_pcie_suspend_noirq(struct device *dev)
1131{
1132        struct mtk_pcie *pcie = dev_get_drvdata(dev);
1133        struct mtk_pcie_port *port;
1134
1135        if (list_empty(&pcie->ports))
1136                return 0;
1137
1138        list_for_each_entry(port, &pcie->ports, list) {
1139                clk_disable_unprepare(port->pipe_ck);
1140                clk_disable_unprepare(port->obff_ck);
1141                clk_disable_unprepare(port->axi_ck);
1142                clk_disable_unprepare(port->aux_ck);
1143                clk_disable_unprepare(port->ahb_ck);
1144                clk_disable_unprepare(port->sys_ck);
1145                phy_power_off(port->phy);
1146                phy_exit(port->phy);
1147        }
1148
1149        clk_disable_unprepare(pcie->free_ck);
1150
1151        return 0;
1152}
1153
1154static int __maybe_unused mtk_pcie_resume_noirq(struct device *dev)
1155{
1156        struct mtk_pcie *pcie = dev_get_drvdata(dev);
1157        struct mtk_pcie_port *port, *tmp;
1158
1159        if (list_empty(&pcie->ports))
1160                return 0;
1161
1162        clk_prepare_enable(pcie->free_ck);
1163
1164        list_for_each_entry_safe(port, tmp, &pcie->ports, list)
1165                mtk_pcie_enable_port(port);
1166
1167        /* In case of EP was removed while system suspend. */
1168        if (list_empty(&pcie->ports))
1169                clk_disable_unprepare(pcie->free_ck);
1170
1171        return 0;
1172}
1173
1174static const struct dev_pm_ops mtk_pcie_pm_ops = {
1175        SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(mtk_pcie_suspend_noirq,
1176                                      mtk_pcie_resume_noirq)
1177};
1178
1179static const struct mtk_pcie_soc mtk_pcie_soc_v1 = {
1180        .no_msi = true,
1181        .ops = &mtk_pcie_ops,
1182        .startup = mtk_pcie_startup_port,
1183};
1184
1185static const struct mtk_pcie_soc mtk_pcie_soc_mt2712 = {
1186        .ops = &mtk_pcie_ops_v2,
1187        .startup = mtk_pcie_startup_port_v2,
1188        .setup_irq = mtk_pcie_setup_irq,
1189};
1190
1191static const struct mtk_pcie_soc mtk_pcie_soc_mt7622 = {
1192        .need_fix_class_id = true,
1193        .ops = &mtk_pcie_ops_v2,
1194        .startup = mtk_pcie_startup_port_v2,
1195        .setup_irq = mtk_pcie_setup_irq,
1196};
1197
1198static const struct mtk_pcie_soc mtk_pcie_soc_mt7629 = {
1199        .need_fix_class_id = true,
1200        .need_fix_device_id = true,
1201        .device_id = PCI_DEVICE_ID_MEDIATEK_7629,
1202        .ops = &mtk_pcie_ops_v2,
1203        .startup = mtk_pcie_startup_port_v2,
1204        .setup_irq = mtk_pcie_setup_irq,
1205};
1206
1207static const struct of_device_id mtk_pcie_ids[] = {
1208        { .compatible = "mediatek,mt2701-pcie", .data = &mtk_pcie_soc_v1 },
1209        { .compatible = "mediatek,mt7623-pcie", .data = &mtk_pcie_soc_v1 },
1210        { .compatible = "mediatek,mt2712-pcie", .data = &mtk_pcie_soc_mt2712 },
1211        { .compatible = "mediatek,mt7622-pcie", .data = &mtk_pcie_soc_mt7622 },
1212        { .compatible = "mediatek,mt7629-pcie", .data = &mtk_pcie_soc_mt7629 },
1213        {},
1214};
1215MODULE_DEVICE_TABLE(of, mtk_pcie_ids);
1216
1217static struct platform_driver mtk_pcie_driver = {
1218        .probe = mtk_pcie_probe,
1219        .remove = mtk_pcie_remove,
1220        .driver = {
1221                .name = "mtk-pcie",
1222                .of_match_table = mtk_pcie_ids,
1223                .suppress_bind_attrs = true,
1224                .pm = &mtk_pcie_pm_ops,
1225        },
1226};
1227module_platform_driver(mtk_pcie_driver);
1228MODULE_LICENSE("GPL v2");
1229