linux/drivers/pci/controller/pci-aardvark.c
<<
>>
Prefs
   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * Driver for the Aardvark PCIe controller, used on Marvell Armada
   4 * 3700.
   5 *
   6 * Copyright (C) 2016 Marvell
   7 *
   8 * Author: Hezi Shahmoon <hezi.shahmoon@marvell.com>
   9 */
  10
  11#include <linux/delay.h>
  12#include <linux/gpio/consumer.h>
  13#include <linux/interrupt.h>
  14#include <linux/irq.h>
  15#include <linux/irqdomain.h>
  16#include <linux/kernel.h>
  17#include <linux/module.h>
  18#include <linux/pci.h>
  19#include <linux/pci-ecam.h>
  20#include <linux/init.h>
  21#include <linux/phy/phy.h>
  22#include <linux/platform_device.h>
  23#include <linux/msi.h>
  24#include <linux/of_address.h>
  25#include <linux/of_gpio.h>
  26#include <linux/of_pci.h>
  27
  28#include "../pci.h"
  29#include "../pci-bridge-emul.h"
  30
  31/* PCIe core registers */
  32#define PCIE_CORE_DEV_ID_REG                                    0x0
  33#define PCIE_CORE_CMD_STATUS_REG                                0x4
  34#define     PCIE_CORE_CMD_IO_ACCESS_EN                          BIT(0)
  35#define     PCIE_CORE_CMD_MEM_ACCESS_EN                         BIT(1)
  36#define     PCIE_CORE_CMD_MEM_IO_REQ_EN                         BIT(2)
  37#define PCIE_CORE_DEV_REV_REG                                   0x8
  38#define PCIE_CORE_PCIEXP_CAP                                    0xc0
  39#define PCIE_CORE_ERR_CAPCTL_REG                                0x118
  40#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX                    BIT(5)
  41#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN                 BIT(6)
  42#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK                      BIT(7)
  43#define     PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV                  BIT(8)
  44#define     PCIE_CORE_INT_A_ASSERT_ENABLE                       1
  45#define     PCIE_CORE_INT_B_ASSERT_ENABLE                       2
  46#define     PCIE_CORE_INT_C_ASSERT_ENABLE                       3
  47#define     PCIE_CORE_INT_D_ASSERT_ENABLE                       4
  48/* PIO registers base address and register offsets */
  49#define PIO_BASE_ADDR                           0x4000
  50#define PIO_CTRL                                (PIO_BASE_ADDR + 0x0)
  51#define   PIO_CTRL_TYPE_MASK                    GENMASK(3, 0)
  52#define   PIO_CTRL_ADDR_WIN_DISABLE             BIT(24)
  53#define PIO_STAT                                (PIO_BASE_ADDR + 0x4)
  54#define   PIO_COMPLETION_STATUS_SHIFT           7
  55#define   PIO_COMPLETION_STATUS_MASK            GENMASK(9, 7)
  56#define   PIO_COMPLETION_STATUS_OK              0
  57#define   PIO_COMPLETION_STATUS_UR              1
  58#define   PIO_COMPLETION_STATUS_CRS             2
  59#define   PIO_COMPLETION_STATUS_CA              4
  60#define   PIO_NON_POSTED_REQ                    BIT(10)
  61#define PIO_ADDR_LS                             (PIO_BASE_ADDR + 0x8)
  62#define PIO_ADDR_MS                             (PIO_BASE_ADDR + 0xc)
  63#define PIO_WR_DATA                             (PIO_BASE_ADDR + 0x10)
  64#define PIO_WR_DATA_STRB                        (PIO_BASE_ADDR + 0x14)
  65#define PIO_RD_DATA                             (PIO_BASE_ADDR + 0x18)
  66#define PIO_START                               (PIO_BASE_ADDR + 0x1c)
  67#define PIO_ISR                                 (PIO_BASE_ADDR + 0x20)
  68#define PIO_ISRM                                (PIO_BASE_ADDR + 0x24)
  69
  70/* Aardvark Control registers */
  71#define CONTROL_BASE_ADDR                       0x4800
  72#define PCIE_CORE_CTRL0_REG                     (CONTROL_BASE_ADDR + 0x0)
  73#define     PCIE_GEN_SEL_MSK                    0x3
  74#define     PCIE_GEN_SEL_SHIFT                  0x0
  75#define     SPEED_GEN_1                         0
  76#define     SPEED_GEN_2                         1
  77#define     SPEED_GEN_3                         2
  78#define     IS_RC_MSK                           1
  79#define     IS_RC_SHIFT                         2
  80#define     LANE_CNT_MSK                        0x18
  81#define     LANE_CNT_SHIFT                      0x3
  82#define     LANE_COUNT_1                        (0 << LANE_CNT_SHIFT)
  83#define     LANE_COUNT_2                        (1 << LANE_CNT_SHIFT)
  84#define     LANE_COUNT_4                        (2 << LANE_CNT_SHIFT)
  85#define     LANE_COUNT_8                        (3 << LANE_CNT_SHIFT)
  86#define     LINK_TRAINING_EN                    BIT(6)
  87#define     LEGACY_INTA                         BIT(28)
  88#define     LEGACY_INTB                         BIT(29)
  89#define     LEGACY_INTC                         BIT(30)
  90#define     LEGACY_INTD                         BIT(31)
  91#define PCIE_CORE_CTRL1_REG                     (CONTROL_BASE_ADDR + 0x4)
  92#define     HOT_RESET_GEN                       BIT(0)
  93#define PCIE_CORE_CTRL2_REG                     (CONTROL_BASE_ADDR + 0x8)
  94#define     PCIE_CORE_CTRL2_RESERVED            0x7
  95#define     PCIE_CORE_CTRL2_TD_ENABLE           BIT(4)
  96#define     PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE BIT(5)
  97#define     PCIE_CORE_CTRL2_OB_WIN_ENABLE       BIT(6)
  98#define     PCIE_CORE_CTRL2_MSI_ENABLE          BIT(10)
  99#define PCIE_CORE_REF_CLK_REG                   (CONTROL_BASE_ADDR + 0x14)
 100#define     PCIE_CORE_REF_CLK_TX_ENABLE         BIT(1)
 101#define PCIE_MSG_LOG_REG                        (CONTROL_BASE_ADDR + 0x30)
 102#define PCIE_ISR0_REG                           (CONTROL_BASE_ADDR + 0x40)
 103#define PCIE_MSG_PM_PME_MASK                    BIT(7)
 104#define PCIE_ISR0_MASK_REG                      (CONTROL_BASE_ADDR + 0x44)
 105#define     PCIE_ISR0_MSI_INT_PENDING           BIT(24)
 106#define     PCIE_ISR0_INTX_ASSERT(val)          BIT(16 + (val))
 107#define     PCIE_ISR0_INTX_DEASSERT(val)        BIT(20 + (val))
 108#define     PCIE_ISR0_ALL_MASK                  GENMASK(26, 0)
 109#define PCIE_ISR1_REG                           (CONTROL_BASE_ADDR + 0x48)
 110#define PCIE_ISR1_MASK_REG                      (CONTROL_BASE_ADDR + 0x4C)
 111#define     PCIE_ISR1_POWER_STATE_CHANGE        BIT(4)
 112#define     PCIE_ISR1_FLUSH                     BIT(5)
 113#define     PCIE_ISR1_INTX_ASSERT(val)          BIT(8 + (val))
 114#define     PCIE_ISR1_ALL_MASK                  GENMASK(11, 4)
 115#define PCIE_MSI_ADDR_LOW_REG                   (CONTROL_BASE_ADDR + 0x50)
 116#define PCIE_MSI_ADDR_HIGH_REG                  (CONTROL_BASE_ADDR + 0x54)
 117#define PCIE_MSI_STATUS_REG                     (CONTROL_BASE_ADDR + 0x58)
 118#define PCIE_MSI_MASK_REG                       (CONTROL_BASE_ADDR + 0x5C)
 119#define PCIE_MSI_PAYLOAD_REG                    (CONTROL_BASE_ADDR + 0x9C)
 120
 121/* LMI registers base address and register offsets */
 122#define LMI_BASE_ADDR                           0x6000
 123#define CFG_REG                                 (LMI_BASE_ADDR + 0x0)
 124#define     LTSSM_SHIFT                         24
 125#define     LTSSM_MASK                          0x3f
 126#define     LTSSM_L0                            0x10
 127#define     RC_BAR_CONFIG                       0x300
 128#define VENDOR_ID_REG                           (LMI_BASE_ADDR + 0x44)
 129
 130/* PCIe core controller registers */
 131#define CTRL_CORE_BASE_ADDR                     0x18000
 132#define CTRL_CONFIG_REG                         (CTRL_CORE_BASE_ADDR + 0x0)
 133#define     CTRL_MODE_SHIFT                     0x0
 134#define     CTRL_MODE_MASK                      0x1
 135#define     PCIE_CORE_MODE_DIRECT               0x0
 136#define     PCIE_CORE_MODE_COMMAND              0x1
 137
 138/* PCIe Central Interrupts Registers */
 139#define CENTRAL_INT_BASE_ADDR                   0x1b000
 140#define HOST_CTRL_INT_STATUS_REG                (CENTRAL_INT_BASE_ADDR + 0x0)
 141#define HOST_CTRL_INT_MASK_REG                  (CENTRAL_INT_BASE_ADDR + 0x4)
 142#define     PCIE_IRQ_CMDQ_INT                   BIT(0)
 143#define     PCIE_IRQ_MSI_STATUS_INT             BIT(1)
 144#define     PCIE_IRQ_CMD_SENT_DONE              BIT(3)
 145#define     PCIE_IRQ_DMA_INT                    BIT(4)
 146#define     PCIE_IRQ_IB_DXFERDONE               BIT(5)
 147#define     PCIE_IRQ_OB_DXFERDONE               BIT(6)
 148#define     PCIE_IRQ_OB_RXFERDONE               BIT(7)
 149#define     PCIE_IRQ_COMPQ_INT                  BIT(12)
 150#define     PCIE_IRQ_DIR_RD_DDR_DET             BIT(13)
 151#define     PCIE_IRQ_DIR_WR_DDR_DET             BIT(14)
 152#define     PCIE_IRQ_CORE_INT                   BIT(16)
 153#define     PCIE_IRQ_CORE_INT_PIO               BIT(17)
 154#define     PCIE_IRQ_DPMU_INT                   BIT(18)
 155#define     PCIE_IRQ_PCIE_MIS_INT               BIT(19)
 156#define     PCIE_IRQ_MSI_INT1_DET               BIT(20)
 157#define     PCIE_IRQ_MSI_INT2_DET               BIT(21)
 158#define     PCIE_IRQ_RC_DBELL_DET               BIT(22)
 159#define     PCIE_IRQ_EP_STATUS                  BIT(23)
 160#define     PCIE_IRQ_ALL_MASK                   0xfff0fb
 161#define     PCIE_IRQ_ENABLE_INTS_MASK           PCIE_IRQ_CORE_INT
 162
 163/* Transaction types */
 164#define PCIE_CONFIG_RD_TYPE0                    0x8
 165#define PCIE_CONFIG_RD_TYPE1                    0x9
 166#define PCIE_CONFIG_WR_TYPE0                    0xa
 167#define PCIE_CONFIG_WR_TYPE1                    0xb
 168
 169#define PIO_RETRY_CNT                   500
 170#define PIO_RETRY_DELAY                 2 /* 2 us*/
 171
 172#define LINK_WAIT_MAX_RETRIES           10
 173#define LINK_WAIT_USLEEP_MIN            90000
 174#define LINK_WAIT_USLEEP_MAX            100000
 175#define RETRAIN_WAIT_MAX_RETRIES        10
 176#define RETRAIN_WAIT_USLEEP_US          2000
 177
 178#define MSI_IRQ_NUM                     32
 179
 180struct advk_pcie {
 181        struct platform_device *pdev;
 182        void __iomem *base;
 183        struct irq_domain *irq_domain;
 184        struct irq_chip irq_chip;
 185        struct irq_domain *msi_domain;
 186        struct irq_domain *msi_inner_domain;
 187        struct irq_chip msi_bottom_irq_chip;
 188        struct irq_chip msi_irq_chip;
 189        struct msi_domain_info msi_domain_info;
 190        DECLARE_BITMAP(msi_used, MSI_IRQ_NUM);
 191        struct mutex msi_used_lock;
 192        u16 msi_msg;
 193        int link_gen;
 194        struct pci_bridge_emul bridge;
 195        struct gpio_desc *reset_gpio;
 196        struct phy *phy;
 197};
 198
 199static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64 reg)
 200{
 201        writel(val, pcie->base + reg);
 202}
 203
 204static inline u32 advk_readl(struct advk_pcie *pcie, u64 reg)
 205{
 206        return readl(pcie->base + reg);
 207}
 208
 209static inline u16 advk_read16(struct advk_pcie *pcie, u64 reg)
 210{
 211        return advk_readl(pcie, (reg & ~0x3)) >> ((reg & 0x3) * 8);
 212}
 213
 214static int advk_pcie_link_up(struct advk_pcie *pcie)
 215{
 216        u32 val, ltssm_state;
 217
 218        val = advk_readl(pcie, CFG_REG);
 219        ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
 220        return ltssm_state >= LTSSM_L0;
 221}
 222
 223static int advk_pcie_wait_for_link(struct advk_pcie *pcie)
 224{
 225        int retries;
 226
 227        /* check if the link is up or not */
 228        for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) {
 229                if (advk_pcie_link_up(pcie))
 230                        return 0;
 231
 232                usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX);
 233        }
 234
 235        return -ETIMEDOUT;
 236}
 237
 238static void advk_pcie_wait_for_retrain(struct advk_pcie *pcie)
 239{
 240        size_t retries;
 241
 242        for (retries = 0; retries < RETRAIN_WAIT_MAX_RETRIES; ++retries) {
 243                if (!advk_pcie_link_up(pcie))
 244                        break;
 245                udelay(RETRAIN_WAIT_USLEEP_US);
 246        }
 247}
 248
 249static void advk_pcie_issue_perst(struct advk_pcie *pcie)
 250{
 251        u32 reg;
 252
 253        if (!pcie->reset_gpio)
 254                return;
 255
 256        /*
 257         * As required by PCI Express spec (PCI Express Base Specification, REV.
 258         * 4.0 PCI Express, February 19 2014, 6.6.1 Conventional Reset) a delay
 259         * for at least 100ms after de-asserting PERST# signal is needed before
 260         * link training is enabled. So ensure that link training is disabled
 261         * prior de-asserting PERST# signal to fulfill that PCI Express spec
 262         * requirement.
 263         */
 264        reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
 265        reg &= ~LINK_TRAINING_EN;
 266        advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
 267
 268        /* 10ms delay is needed for some cards */
 269        dev_info(&pcie->pdev->dev, "issuing PERST via reset GPIO for 10ms\n");
 270        gpiod_set_value_cansleep(pcie->reset_gpio, 1);
 271        usleep_range(10000, 11000);
 272        gpiod_set_value_cansleep(pcie->reset_gpio, 0);
 273}
 274
 275static int advk_pcie_train_at_gen(struct advk_pcie *pcie, int gen)
 276{
 277        int ret, neg_gen;
 278        u32 reg;
 279
 280        /* Setup link speed */
 281        reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
 282        reg &= ~PCIE_GEN_SEL_MSK;
 283        if (gen == 3)
 284                reg |= SPEED_GEN_3;
 285        else if (gen == 2)
 286                reg |= SPEED_GEN_2;
 287        else
 288                reg |= SPEED_GEN_1;
 289        advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
 290
 291        /*
 292         * Enable link training. This is not needed in every call to this
 293         * function, just once suffices, but it does not break anything either.
 294         */
 295        reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
 296        reg |= LINK_TRAINING_EN;
 297        advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
 298
 299        /*
 300         * Start link training immediately after enabling it.
 301         * This solves problems for some buggy cards.
 302         */
 303        reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
 304        reg |= PCI_EXP_LNKCTL_RL;
 305        advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKCTL);
 306
 307        ret = advk_pcie_wait_for_link(pcie);
 308        if (ret)
 309                return ret;
 310
 311        reg = advk_read16(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_LNKSTA);
 312        neg_gen = reg & PCI_EXP_LNKSTA_CLS;
 313
 314        return neg_gen;
 315}
 316
 317static void advk_pcie_train_link(struct advk_pcie *pcie)
 318{
 319        struct device *dev = &pcie->pdev->dev;
 320        int neg_gen = -1, gen;
 321
 322        /*
 323         * Reset PCIe card via PERST# signal. Some cards are not detected
 324         * during link training when they are in some non-initial state.
 325         */
 326        advk_pcie_issue_perst(pcie);
 327
 328        /*
 329         * PERST# signal could have been asserted by pinctrl subsystem before
 330         * probe() callback has been called or issued explicitly by reset gpio
 331         * function advk_pcie_issue_perst(), making the endpoint going into
 332         * fundamental reset. As required by PCI Express spec a delay for at
 333         * least 100ms after such a reset before link training is needed.
 334         */
 335        msleep(PCI_PM_D3COLD_WAIT);
 336
 337        /*
 338         * Try link training at link gen specified by device tree property
 339         * 'max-link-speed'. If this fails, iteratively train at lower gen.
 340         */
 341        for (gen = pcie->link_gen; gen > 0; --gen) {
 342                neg_gen = advk_pcie_train_at_gen(pcie, gen);
 343                if (neg_gen > 0)
 344                        break;
 345        }
 346
 347        if (neg_gen < 0)
 348                goto err;
 349
 350        /*
 351         * After successful training if negotiated gen is lower than requested,
 352         * train again on negotiated gen. This solves some stability issues for
 353         * some buggy gen1 cards.
 354         */
 355        if (neg_gen < gen) {
 356                gen = neg_gen;
 357                neg_gen = advk_pcie_train_at_gen(pcie, gen);
 358        }
 359
 360        if (neg_gen == gen) {
 361                dev_info(dev, "link up at gen %i\n", gen);
 362                return;
 363        }
 364
 365err:
 366        dev_err(dev, "link never came up\n");
 367}
 368
 369static void advk_pcie_setup_hw(struct advk_pcie *pcie)
 370{
 371        u32 reg;
 372
 373        /* Enable TX */
 374        reg = advk_readl(pcie, PCIE_CORE_REF_CLK_REG);
 375        reg |= PCIE_CORE_REF_CLK_TX_ENABLE;
 376        advk_writel(pcie, reg, PCIE_CORE_REF_CLK_REG);
 377
 378        /* Set to Direct mode */
 379        reg = advk_readl(pcie, CTRL_CONFIG_REG);
 380        reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
 381        reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
 382        advk_writel(pcie, reg, CTRL_CONFIG_REG);
 383
 384        /* Set PCI global control register to RC mode */
 385        reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
 386        reg |= (IS_RC_MSK << IS_RC_SHIFT);
 387        advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
 388
 389        /*
 390         * Replace incorrect PCI vendor id value 0x1b4b by correct value 0x11ab.
 391         * VENDOR_ID_REG contains vendor id in low 16 bits and subsystem vendor
 392         * id in high 16 bits. Updating this register changes readback value of
 393         * read-only vendor id bits in PCIE_CORE_DEV_ID_REG register. Workaround
 394         * for erratum 4.1: "The value of device and vendor ID is incorrect".
 395         */
 396        reg = (PCI_VENDOR_ID_MARVELL << 16) | PCI_VENDOR_ID_MARVELL;
 397        advk_writel(pcie, reg, VENDOR_ID_REG);
 398
 399        /* Set Advanced Error Capabilities and Control PF0 register */
 400        reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
 401                PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
 402                PCIE_CORE_ERR_CAPCTL_ECRC_CHCK |
 403                PCIE_CORE_ERR_CAPCTL_ECRC_CHCK_RCV;
 404        advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
 405
 406        /* Set PCIe Device Control register */
 407        reg = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
 408        reg &= ~PCI_EXP_DEVCTL_RELAX_EN;
 409        reg &= ~PCI_EXP_DEVCTL_NOSNOOP_EN;
 410        reg &= ~PCI_EXP_DEVCTL_READRQ;
 411        reg |= PCI_EXP_DEVCTL_PAYLOAD; /* Set max payload size */
 412        reg |= PCI_EXP_DEVCTL_READRQ_512B;
 413        advk_writel(pcie, reg, PCIE_CORE_PCIEXP_CAP + PCI_EXP_DEVCTL);
 414
 415        /* Program PCIe Control 2 to disable strict ordering */
 416        reg = PCIE_CORE_CTRL2_RESERVED |
 417                PCIE_CORE_CTRL2_TD_ENABLE;
 418        advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
 419
 420        /* Set lane X1 */
 421        reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
 422        reg &= ~LANE_CNT_MSK;
 423        reg |= LANE_COUNT_1;
 424        advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
 425
 426        /* Enable MSI */
 427        reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
 428        reg |= PCIE_CORE_CTRL2_MSI_ENABLE;
 429        advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
 430
 431        /* Clear all interrupts */
 432        advk_writel(pcie, PCIE_ISR0_ALL_MASK, PCIE_ISR0_REG);
 433        advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_REG);
 434        advk_writel(pcie, PCIE_IRQ_ALL_MASK, HOST_CTRL_INT_STATUS_REG);
 435
 436        /* Disable All ISR0/1 Sources */
 437        reg = PCIE_ISR0_ALL_MASK;
 438        reg &= ~PCIE_ISR0_MSI_INT_PENDING;
 439        advk_writel(pcie, reg, PCIE_ISR0_MASK_REG);
 440
 441        advk_writel(pcie, PCIE_ISR1_ALL_MASK, PCIE_ISR1_MASK_REG);
 442
 443        /* Unmask all MSIs */
 444        advk_writel(pcie, 0, PCIE_MSI_MASK_REG);
 445
 446        /* Enable summary interrupt for GIC SPI source */
 447        reg = PCIE_IRQ_ALL_MASK & (~PCIE_IRQ_ENABLE_INTS_MASK);
 448        advk_writel(pcie, reg, HOST_CTRL_INT_MASK_REG);
 449
 450        reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
 451        reg |= PCIE_CORE_CTRL2_OB_WIN_ENABLE;
 452        advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
 453
 454        /* Bypass the address window mapping for PIO */
 455        reg = advk_readl(pcie, PIO_CTRL);
 456        reg |= PIO_CTRL_ADDR_WIN_DISABLE;
 457        advk_writel(pcie, reg, PIO_CTRL);
 458
 459        advk_pcie_train_link(pcie);
 460
 461        /*
 462         * FIXME: The following register update is suspicious. This register is
 463         * applicable only when the PCI controller is configured for Endpoint
 464         * mode, not as a Root Complex. But apparently when this code is
 465         * removed, some cards stop working. This should be investigated and
 466         * a comment explaining this should be put here.
 467         */
 468        reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
 469        reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
 470                PCIE_CORE_CMD_IO_ACCESS_EN |
 471                PCIE_CORE_CMD_MEM_IO_REQ_EN;
 472        advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
 473}
 474
 475static void advk_pcie_check_pio_status(struct advk_pcie *pcie)
 476{
 477        struct device *dev = &pcie->pdev->dev;
 478        u32 reg;
 479        unsigned int status;
 480        char *strcomp_status, *str_posted;
 481
 482        reg = advk_readl(pcie, PIO_STAT);
 483        status = (reg & PIO_COMPLETION_STATUS_MASK) >>
 484                PIO_COMPLETION_STATUS_SHIFT;
 485
 486        if (!status)
 487                return;
 488
 489        switch (status) {
 490        case PIO_COMPLETION_STATUS_UR:
 491                strcomp_status = "UR";
 492                break;
 493        case PIO_COMPLETION_STATUS_CRS:
 494                strcomp_status = "CRS";
 495                break;
 496        case PIO_COMPLETION_STATUS_CA:
 497                strcomp_status = "CA";
 498                break;
 499        default:
 500                strcomp_status = "Unknown";
 501                break;
 502        }
 503
 504        if (reg & PIO_NON_POSTED_REQ)
 505                str_posted = "Non-posted";
 506        else
 507                str_posted = "Posted";
 508
 509        dev_err(dev, "%s PIO Response Status: %s, %#x @ %#x\n",
 510                str_posted, strcomp_status, reg, advk_readl(pcie, PIO_ADDR_LS));
 511}
 512
 513static int advk_pcie_wait_pio(struct advk_pcie *pcie)
 514{
 515        struct device *dev = &pcie->pdev->dev;
 516        int i;
 517
 518        for (i = 0; i < PIO_RETRY_CNT; i++) {
 519                u32 start, isr;
 520
 521                start = advk_readl(pcie, PIO_START);
 522                isr = advk_readl(pcie, PIO_ISR);
 523                if (!start && isr)
 524                        return 0;
 525                udelay(PIO_RETRY_DELAY);
 526        }
 527
 528        dev_err(dev, "PIO read/write transfer time out\n");
 529        return -ETIMEDOUT;
 530}
 531
 532
 533static pci_bridge_emul_read_status_t
 534advk_pci_bridge_emul_pcie_conf_read(struct pci_bridge_emul *bridge,
 535                                    int reg, u32 *value)
 536{
 537        struct advk_pcie *pcie = bridge->data;
 538
 539
 540        switch (reg) {
 541        case PCI_EXP_SLTCTL:
 542                *value = PCI_EXP_SLTSTA_PDS << 16;
 543                return PCI_BRIDGE_EMUL_HANDLED;
 544
 545        case PCI_EXP_RTCTL: {
 546                u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG);
 547                *value = (val & PCIE_MSG_PM_PME_MASK) ? 0 : PCI_EXP_RTCTL_PMEIE;
 548                return PCI_BRIDGE_EMUL_HANDLED;
 549        }
 550
 551        case PCI_EXP_RTSTA: {
 552                u32 isr0 = advk_readl(pcie, PCIE_ISR0_REG);
 553                u32 msglog = advk_readl(pcie, PCIE_MSG_LOG_REG);
 554                *value = (isr0 & PCIE_MSG_PM_PME_MASK) << 16 | (msglog >> 16);
 555                return PCI_BRIDGE_EMUL_HANDLED;
 556        }
 557
 558        case PCI_EXP_LNKCTL: {
 559                /* u32 contains both PCI_EXP_LNKCTL and PCI_EXP_LNKSTA */
 560                u32 val = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg) &
 561                        ~(PCI_EXP_LNKSTA_LT << 16);
 562                if (!advk_pcie_link_up(pcie))
 563                        val |= (PCI_EXP_LNKSTA_LT << 16);
 564                *value = val;
 565                return PCI_BRIDGE_EMUL_HANDLED;
 566        }
 567
 568        case PCI_CAP_LIST_ID:
 569        case PCI_EXP_DEVCAP:
 570        case PCI_EXP_DEVCTL:
 571        case PCI_EXP_LNKCAP:
 572                *value = advk_readl(pcie, PCIE_CORE_PCIEXP_CAP + reg);
 573                return PCI_BRIDGE_EMUL_HANDLED;
 574        default:
 575                return PCI_BRIDGE_EMUL_NOT_HANDLED;
 576        }
 577
 578}
 579
 580static void
 581advk_pci_bridge_emul_pcie_conf_write(struct pci_bridge_emul *bridge,
 582                                     int reg, u32 old, u32 new, u32 mask)
 583{
 584        struct advk_pcie *pcie = bridge->data;
 585
 586        switch (reg) {
 587        case PCI_EXP_DEVCTL:
 588                advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
 589                break;
 590
 591        case PCI_EXP_LNKCTL:
 592                advk_writel(pcie, new, PCIE_CORE_PCIEXP_CAP + reg);
 593                if (new & PCI_EXP_LNKCTL_RL)
 594                        advk_pcie_wait_for_retrain(pcie);
 595                break;
 596
 597        case PCI_EXP_RTCTL: {
 598                /* Only mask/unmask PME interrupt */
 599                u32 val = advk_readl(pcie, PCIE_ISR0_MASK_REG) &
 600                        ~PCIE_MSG_PM_PME_MASK;
 601                if ((new & PCI_EXP_RTCTL_PMEIE) == 0)
 602                        val |= PCIE_MSG_PM_PME_MASK;
 603                advk_writel(pcie, val, PCIE_ISR0_MASK_REG);
 604                break;
 605        }
 606
 607        case PCI_EXP_RTSTA:
 608                new = (new & PCI_EXP_RTSTA_PME) >> 9;
 609                advk_writel(pcie, new, PCIE_ISR0_REG);
 610                break;
 611
 612        default:
 613                break;
 614        }
 615}
 616
 617static struct pci_bridge_emul_ops advk_pci_bridge_emul_ops = {
 618        .read_pcie = advk_pci_bridge_emul_pcie_conf_read,
 619        .write_pcie = advk_pci_bridge_emul_pcie_conf_write,
 620};
 621
 622/*
 623 * Initialize the configuration space of the PCI-to-PCI bridge
 624 * associated with the given PCIe interface.
 625 */
 626static int advk_sw_pci_bridge_init(struct advk_pcie *pcie)
 627{
 628        struct pci_bridge_emul *bridge = &pcie->bridge;
 629
 630        bridge->conf.vendor =
 631                cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) & 0xffff);
 632        bridge->conf.device =
 633                cpu_to_le16(advk_readl(pcie, PCIE_CORE_DEV_ID_REG) >> 16);
 634        bridge->conf.class_revision =
 635                cpu_to_le32(advk_readl(pcie, PCIE_CORE_DEV_REV_REG) & 0xff);
 636
 637        /* Support 32 bits I/O addressing */
 638        bridge->conf.iobase = PCI_IO_RANGE_TYPE_32;
 639        bridge->conf.iolimit = PCI_IO_RANGE_TYPE_32;
 640
 641        /* Support 64 bits memory pref */
 642        bridge->conf.pref_mem_base = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
 643        bridge->conf.pref_mem_limit = cpu_to_le16(PCI_PREF_RANGE_TYPE_64);
 644
 645        /* Support interrupt A for MSI feature */
 646        bridge->conf.intpin = PCIE_CORE_INT_A_ASSERT_ENABLE;
 647
 648        bridge->has_pcie = true;
 649        bridge->data = pcie;
 650        bridge->ops = &advk_pci_bridge_emul_ops;
 651
 652        return pci_bridge_emul_init(bridge, 0);
 653}
 654
 655static bool advk_pcie_valid_device(struct advk_pcie *pcie, struct pci_bus *bus,
 656                                  int devfn)
 657{
 658        if (pci_is_root_bus(bus) && PCI_SLOT(devfn) != 0)
 659                return false;
 660
 661        /*
 662         * If the link goes down after we check for link-up, nothing bad
 663         * happens but the config access times out.
 664         */
 665        if (!pci_is_root_bus(bus) && !advk_pcie_link_up(pcie))
 666                return false;
 667
 668        return true;
 669}
 670
 671static bool advk_pcie_pio_is_running(struct advk_pcie *pcie)
 672{
 673        struct device *dev = &pcie->pdev->dev;
 674
 675        /*
 676         * Trying to start a new PIO transfer when previous has not completed
 677         * cause External Abort on CPU which results in kernel panic:
 678         *
 679         *     SError Interrupt on CPU0, code 0xbf000002 -- SError
 680         *     Kernel panic - not syncing: Asynchronous SError Interrupt
 681         *
 682         * Functions advk_pcie_rd_conf() and advk_pcie_wr_conf() are protected
 683         * by raw_spin_lock_irqsave() at pci_lock_config() level to prevent
 684         * concurrent calls at the same time. But because PIO transfer may take
 685         * about 1.5s when link is down or card is disconnected, it means that
 686         * advk_pcie_wait_pio() does not always have to wait for completion.
 687         *
 688         * Some versions of ARM Trusted Firmware handles this External Abort at
 689         * EL3 level and mask it to prevent kernel panic. Relevant TF-A commit:
 690         * https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50
 691         */
 692        if (advk_readl(pcie, PIO_START)) {
 693                dev_err(dev, "Previous PIO read/write transfer is still running\n");
 694                return true;
 695        }
 696
 697        return false;
 698}
 699
 700static int advk_pcie_rd_conf(struct pci_bus *bus, u32 devfn,
 701                             int where, int size, u32 *val)
 702{
 703        struct advk_pcie *pcie = bus->sysdata;
 704        u32 reg;
 705        int ret;
 706
 707        if (!advk_pcie_valid_device(pcie, bus, devfn)) {
 708                *val = 0xffffffff;
 709                return PCIBIOS_DEVICE_NOT_FOUND;
 710        }
 711
 712        if (pci_is_root_bus(bus))
 713                return pci_bridge_emul_conf_read(&pcie->bridge, where,
 714                                                 size, val);
 715
 716        if (advk_pcie_pio_is_running(pcie)) {
 717                *val = 0xffffffff;
 718                return PCIBIOS_SET_FAILED;
 719        }
 720
 721        /* Program the control register */
 722        reg = advk_readl(pcie, PIO_CTRL);
 723        reg &= ~PIO_CTRL_TYPE_MASK;
 724        if (pci_is_root_bus(bus->parent))
 725                reg |= PCIE_CONFIG_RD_TYPE0;
 726        else
 727                reg |= PCIE_CONFIG_RD_TYPE1;
 728        advk_writel(pcie, reg, PIO_CTRL);
 729
 730        /* Program the address registers */
 731        reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4);
 732        advk_writel(pcie, reg, PIO_ADDR_LS);
 733        advk_writel(pcie, 0, PIO_ADDR_MS);
 734
 735        /* Program the data strobe */
 736        advk_writel(pcie, 0xf, PIO_WR_DATA_STRB);
 737
 738        /* Clear PIO DONE ISR and start the transfer */
 739        advk_writel(pcie, 1, PIO_ISR);
 740        advk_writel(pcie, 1, PIO_START);
 741
 742        ret = advk_pcie_wait_pio(pcie);
 743        if (ret < 0) {
 744                *val = 0xffffffff;
 745                return PCIBIOS_SET_FAILED;
 746        }
 747
 748        advk_pcie_check_pio_status(pcie);
 749
 750        /* Get the read result */
 751        *val = advk_readl(pcie, PIO_RD_DATA);
 752        if (size == 1)
 753                *val = (*val >> (8 * (where & 3))) & 0xff;
 754        else if (size == 2)
 755                *val = (*val >> (8 * (where & 3))) & 0xffff;
 756
 757        return PCIBIOS_SUCCESSFUL;
 758}
 759
 760static int advk_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
 761                                int where, int size, u32 val)
 762{
 763        struct advk_pcie *pcie = bus->sysdata;
 764        u32 reg;
 765        u32 data_strobe = 0x0;
 766        int offset;
 767        int ret;
 768
 769        if (!advk_pcie_valid_device(pcie, bus, devfn))
 770                return PCIBIOS_DEVICE_NOT_FOUND;
 771
 772        if (pci_is_root_bus(bus))
 773                return pci_bridge_emul_conf_write(&pcie->bridge, where,
 774                                                  size, val);
 775
 776        if (where % size)
 777                return PCIBIOS_SET_FAILED;
 778
 779        if (advk_pcie_pio_is_running(pcie))
 780                return PCIBIOS_SET_FAILED;
 781
 782        /* Program the control register */
 783        reg = advk_readl(pcie, PIO_CTRL);
 784        reg &= ~PIO_CTRL_TYPE_MASK;
 785        if (pci_is_root_bus(bus->parent))
 786                reg |= PCIE_CONFIG_WR_TYPE0;
 787        else
 788                reg |= PCIE_CONFIG_WR_TYPE1;
 789        advk_writel(pcie, reg, PIO_CTRL);
 790
 791        /* Program the address registers */
 792        reg = ALIGN_DOWN(PCIE_ECAM_OFFSET(bus->number, devfn, where), 4);
 793        advk_writel(pcie, reg, PIO_ADDR_LS);
 794        advk_writel(pcie, 0, PIO_ADDR_MS);
 795
 796        /* Calculate the write strobe */
 797        offset      = where & 0x3;
 798        reg         = val << (8 * offset);
 799        data_strobe = GENMASK(size - 1, 0) << offset;
 800
 801        /* Program the data register */
 802        advk_writel(pcie, reg, PIO_WR_DATA);
 803
 804        /* Program the data strobe */
 805        advk_writel(pcie, data_strobe, PIO_WR_DATA_STRB);
 806
 807        /* Clear PIO DONE ISR and start the transfer */
 808        advk_writel(pcie, 1, PIO_ISR);
 809        advk_writel(pcie, 1, PIO_START);
 810
 811        ret = advk_pcie_wait_pio(pcie);
 812        if (ret < 0)
 813                return PCIBIOS_SET_FAILED;
 814
 815        advk_pcie_check_pio_status(pcie);
 816
 817        return PCIBIOS_SUCCESSFUL;
 818}
 819
 820static struct pci_ops advk_pcie_ops = {
 821        .read = advk_pcie_rd_conf,
 822        .write = advk_pcie_wr_conf,
 823};
 824
 825static void advk_msi_irq_compose_msi_msg(struct irq_data *data,
 826                                         struct msi_msg *msg)
 827{
 828        struct advk_pcie *pcie = irq_data_get_irq_chip_data(data);
 829        phys_addr_t msi_msg = virt_to_phys(&pcie->msi_msg);
 830
 831        msg->address_lo = lower_32_bits(msi_msg);
 832        msg->address_hi = upper_32_bits(msi_msg);
 833        msg->data = data->irq;
 834}
 835
 836static int advk_msi_set_affinity(struct irq_data *irq_data,
 837                                 const struct cpumask *mask, bool force)
 838{
 839        return -EINVAL;
 840}
 841
 842static int advk_msi_irq_domain_alloc(struct irq_domain *domain,
 843                                     unsigned int virq,
 844                                     unsigned int nr_irqs, void *args)
 845{
 846        struct advk_pcie *pcie = domain->host_data;
 847        int hwirq, i;
 848
 849        mutex_lock(&pcie->msi_used_lock);
 850        hwirq = bitmap_find_next_zero_area(pcie->msi_used, MSI_IRQ_NUM,
 851                                           0, nr_irqs, 0);
 852        if (hwirq >= MSI_IRQ_NUM) {
 853                mutex_unlock(&pcie->msi_used_lock);
 854                return -ENOSPC;
 855        }
 856
 857        bitmap_set(pcie->msi_used, hwirq, nr_irqs);
 858        mutex_unlock(&pcie->msi_used_lock);
 859
 860        for (i = 0; i < nr_irqs; i++)
 861                irq_domain_set_info(domain, virq + i, hwirq + i,
 862                                    &pcie->msi_bottom_irq_chip,
 863                                    domain->host_data, handle_simple_irq,
 864                                    NULL, NULL);
 865
 866        return hwirq;
 867}
 868
 869static void advk_msi_irq_domain_free(struct irq_domain *domain,
 870                                     unsigned int virq, unsigned int nr_irqs)
 871{
 872        struct irq_data *d = irq_domain_get_irq_data(domain, virq);
 873        struct advk_pcie *pcie = domain->host_data;
 874
 875        mutex_lock(&pcie->msi_used_lock);
 876        bitmap_clear(pcie->msi_used, d->hwirq, nr_irqs);
 877        mutex_unlock(&pcie->msi_used_lock);
 878}
 879
 880static const struct irq_domain_ops advk_msi_domain_ops = {
 881        .alloc = advk_msi_irq_domain_alloc,
 882        .free = advk_msi_irq_domain_free,
 883};
 884
 885static void advk_pcie_irq_mask(struct irq_data *d)
 886{
 887        struct advk_pcie *pcie = d->domain->host_data;
 888        irq_hw_number_t hwirq = irqd_to_hwirq(d);
 889        u32 mask;
 890
 891        mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
 892        mask |= PCIE_ISR1_INTX_ASSERT(hwirq);
 893        advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
 894}
 895
 896static void advk_pcie_irq_unmask(struct irq_data *d)
 897{
 898        struct advk_pcie *pcie = d->domain->host_data;
 899        irq_hw_number_t hwirq = irqd_to_hwirq(d);
 900        u32 mask;
 901
 902        mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
 903        mask &= ~PCIE_ISR1_INTX_ASSERT(hwirq);
 904        advk_writel(pcie, mask, PCIE_ISR1_MASK_REG);
 905}
 906
 907static int advk_pcie_irq_map(struct irq_domain *h,
 908                             unsigned int virq, irq_hw_number_t hwirq)
 909{
 910        struct advk_pcie *pcie = h->host_data;
 911
 912        advk_pcie_irq_mask(irq_get_irq_data(virq));
 913        irq_set_status_flags(virq, IRQ_LEVEL);
 914        irq_set_chip_and_handler(virq, &pcie->irq_chip,
 915                                 handle_level_irq);
 916        irq_set_chip_data(virq, pcie);
 917
 918        return 0;
 919}
 920
 921static const struct irq_domain_ops advk_pcie_irq_domain_ops = {
 922        .map = advk_pcie_irq_map,
 923        .xlate = irq_domain_xlate_onecell,
 924};
 925
 926static int advk_pcie_init_msi_irq_domain(struct advk_pcie *pcie)
 927{
 928        struct device *dev = &pcie->pdev->dev;
 929        struct device_node *node = dev->of_node;
 930        struct irq_chip *bottom_ic, *msi_ic;
 931        struct msi_domain_info *msi_di;
 932        phys_addr_t msi_msg_phys;
 933
 934        mutex_init(&pcie->msi_used_lock);
 935
 936        bottom_ic = &pcie->msi_bottom_irq_chip;
 937
 938        bottom_ic->name = "MSI";
 939        bottom_ic->irq_compose_msi_msg = advk_msi_irq_compose_msi_msg;
 940        bottom_ic->irq_set_affinity = advk_msi_set_affinity;
 941
 942        msi_ic = &pcie->msi_irq_chip;
 943        msi_ic->name = "advk-MSI";
 944
 945        msi_di = &pcie->msi_domain_info;
 946        msi_di->flags = MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS |
 947                MSI_FLAG_MULTI_PCI_MSI;
 948        msi_di->chip = msi_ic;
 949
 950        msi_msg_phys = virt_to_phys(&pcie->msi_msg);
 951
 952        advk_writel(pcie, lower_32_bits(msi_msg_phys),
 953                    PCIE_MSI_ADDR_LOW_REG);
 954        advk_writel(pcie, upper_32_bits(msi_msg_phys),
 955                    PCIE_MSI_ADDR_HIGH_REG);
 956
 957        pcie->msi_inner_domain =
 958                irq_domain_add_linear(NULL, MSI_IRQ_NUM,
 959                                      &advk_msi_domain_ops, pcie);
 960        if (!pcie->msi_inner_domain)
 961                return -ENOMEM;
 962
 963        pcie->msi_domain =
 964                pci_msi_create_irq_domain(of_node_to_fwnode(node),
 965                                          msi_di, pcie->msi_inner_domain);
 966        if (!pcie->msi_domain) {
 967                irq_domain_remove(pcie->msi_inner_domain);
 968                return -ENOMEM;
 969        }
 970
 971        return 0;
 972}
 973
 974static void advk_pcie_remove_msi_irq_domain(struct advk_pcie *pcie)
 975{
 976        irq_domain_remove(pcie->msi_domain);
 977        irq_domain_remove(pcie->msi_inner_domain);
 978}
 979
 980static int advk_pcie_init_irq_domain(struct advk_pcie *pcie)
 981{
 982        struct device *dev = &pcie->pdev->dev;
 983        struct device_node *node = dev->of_node;
 984        struct device_node *pcie_intc_node;
 985        struct irq_chip *irq_chip;
 986        int ret = 0;
 987
 988        pcie_intc_node =  of_get_next_child(node, NULL);
 989        if (!pcie_intc_node) {
 990                dev_err(dev, "No PCIe Intc node found\n");
 991                return -ENODEV;
 992        }
 993
 994        irq_chip = &pcie->irq_chip;
 995
 996        irq_chip->name = devm_kasprintf(dev, GFP_KERNEL, "%s-irq",
 997                                        dev_name(dev));
 998        if (!irq_chip->name) {
 999                ret = -ENOMEM;
1000                goto out_put_node;
1001        }
1002
1003        irq_chip->irq_mask = advk_pcie_irq_mask;
1004        irq_chip->irq_mask_ack = advk_pcie_irq_mask;
1005        irq_chip->irq_unmask = advk_pcie_irq_unmask;
1006
1007        pcie->irq_domain =
1008                irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,
1009                                      &advk_pcie_irq_domain_ops, pcie);
1010        if (!pcie->irq_domain) {
1011                dev_err(dev, "Failed to get a INTx IRQ domain\n");
1012                ret = -ENOMEM;
1013                goto out_put_node;
1014        }
1015
1016out_put_node:
1017        of_node_put(pcie_intc_node);
1018        return ret;
1019}
1020
1021static void advk_pcie_remove_irq_domain(struct advk_pcie *pcie)
1022{
1023        irq_domain_remove(pcie->irq_domain);
1024}
1025
1026static void advk_pcie_handle_msi(struct advk_pcie *pcie)
1027{
1028        u32 msi_val, msi_mask, msi_status, msi_idx;
1029        u16 msi_data;
1030
1031        msi_mask = advk_readl(pcie, PCIE_MSI_MASK_REG);
1032        msi_val = advk_readl(pcie, PCIE_MSI_STATUS_REG);
1033        msi_status = msi_val & ~msi_mask;
1034
1035        for (msi_idx = 0; msi_idx < MSI_IRQ_NUM; msi_idx++) {
1036                if (!(BIT(msi_idx) & msi_status))
1037                        continue;
1038
1039                advk_writel(pcie, BIT(msi_idx), PCIE_MSI_STATUS_REG);
1040                msi_data = advk_readl(pcie, PCIE_MSI_PAYLOAD_REG) & 0xFF;
1041                generic_handle_irq(msi_data);
1042        }
1043
1044        advk_writel(pcie, PCIE_ISR0_MSI_INT_PENDING,
1045                    PCIE_ISR0_REG);
1046}
1047
1048static void advk_pcie_handle_int(struct advk_pcie *pcie)
1049{
1050        u32 isr0_val, isr0_mask, isr0_status;
1051        u32 isr1_val, isr1_mask, isr1_status;
1052        int i, virq;
1053
1054        isr0_val = advk_readl(pcie, PCIE_ISR0_REG);
1055        isr0_mask = advk_readl(pcie, PCIE_ISR0_MASK_REG);
1056        isr0_status = isr0_val & ((~isr0_mask) & PCIE_ISR0_ALL_MASK);
1057
1058        isr1_val = advk_readl(pcie, PCIE_ISR1_REG);
1059        isr1_mask = advk_readl(pcie, PCIE_ISR1_MASK_REG);
1060        isr1_status = isr1_val & ((~isr1_mask) & PCIE_ISR1_ALL_MASK);
1061
1062        if (!isr0_status && !isr1_status) {
1063                advk_writel(pcie, isr0_val, PCIE_ISR0_REG);
1064                advk_writel(pcie, isr1_val, PCIE_ISR1_REG);
1065                return;
1066        }
1067
1068        /* Process MSI interrupts */
1069        if (isr0_status & PCIE_ISR0_MSI_INT_PENDING)
1070                advk_pcie_handle_msi(pcie);
1071
1072        /* Process legacy interrupts */
1073        for (i = 0; i < PCI_NUM_INTX; i++) {
1074                if (!(isr1_status & PCIE_ISR1_INTX_ASSERT(i)))
1075                        continue;
1076
1077                advk_writel(pcie, PCIE_ISR1_INTX_ASSERT(i),
1078                            PCIE_ISR1_REG);
1079
1080                virq = irq_find_mapping(pcie->irq_domain, i);
1081                generic_handle_irq(virq);
1082        }
1083}
1084
1085static irqreturn_t advk_pcie_irq_handler(int irq, void *arg)
1086{
1087        struct advk_pcie *pcie = arg;
1088        u32 status;
1089
1090        status = advk_readl(pcie, HOST_CTRL_INT_STATUS_REG);
1091        if (!(status & PCIE_IRQ_CORE_INT))
1092                return IRQ_NONE;
1093
1094        advk_pcie_handle_int(pcie);
1095
1096        /* Clear interrupt */
1097        advk_writel(pcie, PCIE_IRQ_CORE_INT, HOST_CTRL_INT_STATUS_REG);
1098
1099        return IRQ_HANDLED;
1100}
1101
1102static void __maybe_unused advk_pcie_disable_phy(struct advk_pcie *pcie)
1103{
1104        phy_power_off(pcie->phy);
1105        phy_exit(pcie->phy);
1106}
1107
1108static int advk_pcie_enable_phy(struct advk_pcie *pcie)
1109{
1110        int ret;
1111
1112        if (!pcie->phy)
1113                return 0;
1114
1115        ret = phy_init(pcie->phy);
1116        if (ret)
1117                return ret;
1118
1119        ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
1120        if (ret) {
1121                phy_exit(pcie->phy);
1122                return ret;
1123        }
1124
1125        ret = phy_power_on(pcie->phy);
1126        if (ret == -EOPNOTSUPP) {
1127                dev_warn(&pcie->pdev->dev, "PHY unsupported by firmware\n");
1128        } else if (ret) {
1129                phy_exit(pcie->phy);
1130                return ret;
1131        }
1132
1133        return 0;
1134}
1135
1136static int advk_pcie_setup_phy(struct advk_pcie *pcie)
1137{
1138        struct device *dev = &pcie->pdev->dev;
1139        struct device_node *node = dev->of_node;
1140        int ret = 0;
1141
1142        pcie->phy = devm_of_phy_get(dev, node, NULL);
1143        if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) == -EPROBE_DEFER))
1144                return PTR_ERR(pcie->phy);
1145
1146        /* Old bindings miss the PHY handle */
1147        if (IS_ERR(pcie->phy)) {
1148                dev_warn(dev, "PHY unavailable (%ld)\n", PTR_ERR(pcie->phy));
1149                pcie->phy = NULL;
1150                return 0;
1151        }
1152
1153        ret = advk_pcie_enable_phy(pcie);
1154        if (ret)
1155                dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
1156
1157        return ret;
1158}
1159
1160static int advk_pcie_probe(struct platform_device *pdev)
1161{
1162        struct device *dev = &pdev->dev;
1163        struct advk_pcie *pcie;
1164        struct pci_host_bridge *bridge;
1165        int ret, irq;
1166
1167        bridge = devm_pci_alloc_host_bridge(dev, sizeof(struct advk_pcie));
1168        if (!bridge)
1169                return -ENOMEM;
1170
1171        pcie = pci_host_bridge_priv(bridge);
1172        pcie->pdev = pdev;
1173        platform_set_drvdata(pdev, pcie);
1174
1175        pcie->base = devm_platform_ioremap_resource(pdev, 0);
1176        if (IS_ERR(pcie->base))
1177                return PTR_ERR(pcie->base);
1178
1179        irq = platform_get_irq(pdev, 0);
1180        if (irq < 0)
1181                return irq;
1182
1183        ret = devm_request_irq(dev, irq, advk_pcie_irq_handler,
1184                               IRQF_SHARED | IRQF_NO_THREAD, "advk-pcie",
1185                               pcie);
1186        if (ret) {
1187                dev_err(dev, "Failed to register interrupt\n");
1188                return ret;
1189        }
1190
1191        pcie->reset_gpio = devm_gpiod_get_from_of_node(dev, dev->of_node,
1192                                                       "reset-gpios", 0,
1193                                                       GPIOD_OUT_LOW,
1194                                                       "pcie1-reset");
1195        ret = PTR_ERR_OR_ZERO(pcie->reset_gpio);
1196        if (ret) {
1197                if (ret == -ENOENT) {
1198                        pcie->reset_gpio = NULL;
1199                } else {
1200                        if (ret != -EPROBE_DEFER)
1201                                dev_err(dev, "Failed to get reset-gpio: %i\n",
1202                                        ret);
1203                        return ret;
1204                }
1205        }
1206
1207        ret = of_pci_get_max_link_speed(dev->of_node);
1208        if (ret <= 0 || ret > 3)
1209                pcie->link_gen = 3;
1210        else
1211                pcie->link_gen = ret;
1212
1213        ret = advk_pcie_setup_phy(pcie);
1214        if (ret)
1215                return ret;
1216
1217        advk_pcie_setup_hw(pcie);
1218
1219        ret = advk_sw_pci_bridge_init(pcie);
1220        if (ret) {
1221                dev_err(dev, "Failed to register emulated root PCI bridge\n");
1222                return ret;
1223        }
1224
1225        ret = advk_pcie_init_irq_domain(pcie);
1226        if (ret) {
1227                dev_err(dev, "Failed to initialize irq\n");
1228                return ret;
1229        }
1230
1231        ret = advk_pcie_init_msi_irq_domain(pcie);
1232        if (ret) {
1233                dev_err(dev, "Failed to initialize irq\n");
1234                advk_pcie_remove_irq_domain(pcie);
1235                return ret;
1236        }
1237
1238        bridge->sysdata = pcie;
1239        bridge->ops = &advk_pcie_ops;
1240
1241        ret = pci_host_probe(bridge);
1242        if (ret < 0) {
1243                advk_pcie_remove_msi_irq_domain(pcie);
1244                advk_pcie_remove_irq_domain(pcie);
1245                return ret;
1246        }
1247
1248        return 0;
1249}
1250
1251static int advk_pcie_remove(struct platform_device *pdev)
1252{
1253        struct advk_pcie *pcie = platform_get_drvdata(pdev);
1254        struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie);
1255
1256        pci_lock_rescan_remove();
1257        pci_stop_root_bus(bridge->bus);
1258        pci_remove_root_bus(bridge->bus);
1259        pci_unlock_rescan_remove();
1260
1261        advk_pcie_remove_msi_irq_domain(pcie);
1262        advk_pcie_remove_irq_domain(pcie);
1263
1264        return 0;
1265}
1266
1267static const struct of_device_id advk_pcie_of_match_table[] = {
1268        { .compatible = "marvell,armada-3700-pcie", },
1269        {},
1270};
1271MODULE_DEVICE_TABLE(of, advk_pcie_of_match_table);
1272
1273static struct platform_driver advk_pcie_driver = {
1274        .driver = {
1275                .name = "advk-pcie",
1276                .of_match_table = advk_pcie_of_match_table,
1277        },
1278        .probe = advk_pcie_probe,
1279        .remove = advk_pcie_remove,
1280};
1281module_platform_driver(advk_pcie_driver);
1282
1283MODULE_DESCRIPTION("Aardvark PCIe controller");
1284MODULE_LICENSE("GPL v2");
1285