linux/drivers/pci/controller/dwc/pci-imx6.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * PCIe host controller driver for Freescale i.MX6 SoCs
   4 *
   5 * Copyright (C) 2013 Kosagi
   6 *              https://www.kosagi.com
   7 *
   8 * Author: Sean Cross <xobs@kosagi.com>
   9 */
  10
  11#include <linux/bitfield.h>
  12#include <linux/clk.h>
  13#include <linux/delay.h>
  14#include <linux/gpio.h>
  15#include <linux/kernel.h>
  16#include <linux/mfd/syscon.h>
  17#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
  18#include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
  19#include <linux/module.h>
  20#include <linux/of_gpio.h>
  21#include <linux/of_device.h>
  22#include <linux/of_address.h>
  23#include <linux/pci.h>
  24#include <linux/platform_device.h>
  25#include <linux/regmap.h>
  26#include <linux/regulator/consumer.h>
  27#include <linux/resource.h>
  28#include <linux/signal.h>
  29#include <linux/types.h>
  30#include <linux/interrupt.h>
  31#include <linux/reset.h>
  32#include <linux/pm_domain.h>
  33#include <linux/pm_runtime.h>
  34
  35#include "pcie-designware.h"
  36
  37#define IMX8MQ_GPR_PCIE_REF_USE_PAD             BIT(9)
  38#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN     BIT(10)
  39#define IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE        BIT(11)
  40#define IMX8MQ_GPR_PCIE_VREG_BYPASS             BIT(12)
  41#define IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE     GENMASK(11, 8)
  42#define IMX8MQ_PCIE2_BASE_ADDR                  0x33c00000
  43
  44#define to_imx6_pcie(x) dev_get_drvdata((x)->dev)
  45
  46enum imx6_pcie_variants {
  47        IMX6Q,
  48        IMX6SX,
  49        IMX6QP,
  50        IMX7D,
  51        IMX8MQ,
  52};
  53
  54#define IMX6_PCIE_FLAG_IMX6_PHY                 BIT(0)
  55#define IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE        BIT(1)
  56#define IMX6_PCIE_FLAG_SUPPORTS_SUSPEND         BIT(2)
  57
  58struct imx6_pcie_drvdata {
  59        enum imx6_pcie_variants variant;
  60        u32 flags;
  61        int dbi_length;
  62};
  63
  64struct imx6_pcie {
  65        struct dw_pcie          *pci;
  66        int                     reset_gpio;
  67        bool                    gpio_active_high;
  68        struct clk              *pcie_bus;
  69        struct clk              *pcie_phy;
  70        struct clk              *pcie_inbound_axi;
  71        struct clk              *pcie;
  72        struct clk              *pcie_aux;
  73        struct regmap           *iomuxc_gpr;
  74        u32                     controller_id;
  75        struct reset_control    *pciephy_reset;
  76        struct reset_control    *apps_reset;
  77        struct reset_control    *turnoff_reset;
  78        u32                     tx_deemph_gen1;
  79        u32                     tx_deemph_gen2_3p5db;
  80        u32                     tx_deemph_gen2_6db;
  81        u32                     tx_swing_full;
  82        u32                     tx_swing_low;
  83        struct regulator        *vpcie;
  84        struct regulator        *vph;
  85        void __iomem            *phy_base;
  86
  87        /* power domain for pcie */
  88        struct device           *pd_pcie;
  89        /* power domain for pcie phy */
  90        struct device           *pd_pcie_phy;
  91        const struct imx6_pcie_drvdata *drvdata;
  92};
  93
  94/* Parameters for the waiting for PCIe PHY PLL to lock on i.MX7 */
  95#define PHY_PLL_LOCK_WAIT_USLEEP_MAX    200
  96#define PHY_PLL_LOCK_WAIT_TIMEOUT       (2000 * PHY_PLL_LOCK_WAIT_USLEEP_MAX)
  97
  98/* PCIe Port Logic registers (memory-mapped) */
  99#define PL_OFFSET 0x700
 100
 101#define PCIE_PHY_CTRL (PL_OFFSET + 0x114)
 102#define PCIE_PHY_CTRL_DATA(x)           FIELD_PREP(GENMASK(15, 0), (x))
 103#define PCIE_PHY_CTRL_CAP_ADR           BIT(16)
 104#define PCIE_PHY_CTRL_CAP_DAT           BIT(17)
 105#define PCIE_PHY_CTRL_WR                BIT(18)
 106#define PCIE_PHY_CTRL_RD                BIT(19)
 107
 108#define PCIE_PHY_STAT (PL_OFFSET + 0x110)
 109#define PCIE_PHY_STAT_ACK               BIT(16)
 110
 111/* PHY registers (not memory-mapped) */
 112#define PCIE_PHY_ATEOVRD                        0x10
 113#define  PCIE_PHY_ATEOVRD_EN                    BIT(2)
 114#define  PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT      0
 115#define  PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK       0x1
 116
 117#define PCIE_PHY_MPLL_OVRD_IN_LO                0x11
 118#define  PCIE_PHY_MPLL_MULTIPLIER_SHIFT         2
 119#define  PCIE_PHY_MPLL_MULTIPLIER_MASK          0x7f
 120#define  PCIE_PHY_MPLL_MULTIPLIER_OVRD          BIT(9)
 121
 122#define PCIE_PHY_RX_ASIC_OUT 0x100D
 123#define PCIE_PHY_RX_ASIC_OUT_VALID      (1 << 0)
 124
 125/* iMX7 PCIe PHY registers */
 126#define PCIE_PHY_CMN_REG4               0x14
 127/* These are probably the bits that *aren't* DCC_FB_EN */
 128#define PCIE_PHY_CMN_REG4_DCC_FB_EN     0x29
 129
 130#define PCIE_PHY_CMN_REG15              0x54
 131#define PCIE_PHY_CMN_REG15_DLY_4        BIT(2)
 132#define PCIE_PHY_CMN_REG15_PLL_PD       BIT(5)
 133#define PCIE_PHY_CMN_REG15_OVRD_PLL_PD  BIT(7)
 134
 135#define PCIE_PHY_CMN_REG24              0x90
 136#define PCIE_PHY_CMN_REG24_RX_EQ        BIT(6)
 137#define PCIE_PHY_CMN_REG24_RX_EQ_SEL    BIT(3)
 138
 139#define PCIE_PHY_CMN_REG26              0x98
 140#define PCIE_PHY_CMN_REG26_ATT_MODE     0xBC
 141
 142#define PHY_RX_OVRD_IN_LO 0x1005
 143#define PHY_RX_OVRD_IN_LO_RX_DATA_EN            BIT(5)
 144#define PHY_RX_OVRD_IN_LO_RX_PLL_EN             BIT(3)
 145
 146static int pcie_phy_poll_ack(struct imx6_pcie *imx6_pcie, bool exp_val)
 147{
 148        struct dw_pcie *pci = imx6_pcie->pci;
 149        bool val;
 150        u32 max_iterations = 10;
 151        u32 wait_counter = 0;
 152
 153        do {
 154                val = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT) &
 155                        PCIE_PHY_STAT_ACK;
 156                wait_counter++;
 157
 158                if (val == exp_val)
 159                        return 0;
 160
 161                udelay(1);
 162        } while (wait_counter < max_iterations);
 163
 164        return -ETIMEDOUT;
 165}
 166
 167static int pcie_phy_wait_ack(struct imx6_pcie *imx6_pcie, int addr)
 168{
 169        struct dw_pcie *pci = imx6_pcie->pci;
 170        u32 val;
 171        int ret;
 172
 173        val = PCIE_PHY_CTRL_DATA(addr);
 174        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 175
 176        val |= PCIE_PHY_CTRL_CAP_ADR;
 177        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 178
 179        ret = pcie_phy_poll_ack(imx6_pcie, true);
 180        if (ret)
 181                return ret;
 182
 183        val = PCIE_PHY_CTRL_DATA(addr);
 184        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, val);
 185
 186        return pcie_phy_poll_ack(imx6_pcie, false);
 187}
 188
 189/* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
 190static int pcie_phy_read(struct imx6_pcie *imx6_pcie, int addr, u16 *data)
 191{
 192        struct dw_pcie *pci = imx6_pcie->pci;
 193        u32 phy_ctl;
 194        int ret;
 195
 196        ret = pcie_phy_wait_ack(imx6_pcie, addr);
 197        if (ret)
 198                return ret;
 199
 200        /* assert Read signal */
 201        phy_ctl = PCIE_PHY_CTRL_RD;
 202        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, phy_ctl);
 203
 204        ret = pcie_phy_poll_ack(imx6_pcie, true);
 205        if (ret)
 206                return ret;
 207
 208        *data = dw_pcie_readl_dbi(pci, PCIE_PHY_STAT);
 209
 210        /* deassert Read signal */
 211        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x00);
 212
 213        return pcie_phy_poll_ack(imx6_pcie, false);
 214}
 215
 216static int pcie_phy_write(struct imx6_pcie *imx6_pcie, int addr, u16 data)
 217{
 218        struct dw_pcie *pci = imx6_pcie->pci;
 219        u32 var;
 220        int ret;
 221
 222        /* write addr */
 223        /* cap addr */
 224        ret = pcie_phy_wait_ack(imx6_pcie, addr);
 225        if (ret)
 226                return ret;
 227
 228        var = PCIE_PHY_CTRL_DATA(data);
 229        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 230
 231        /* capture data */
 232        var |= PCIE_PHY_CTRL_CAP_DAT;
 233        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 234
 235        ret = pcie_phy_poll_ack(imx6_pcie, true);
 236        if (ret)
 237                return ret;
 238
 239        /* deassert cap data */
 240        var = PCIE_PHY_CTRL_DATA(data);
 241        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 242
 243        /* wait for ack de-assertion */
 244        ret = pcie_phy_poll_ack(imx6_pcie, false);
 245        if (ret)
 246                return ret;
 247
 248        /* assert wr signal */
 249        var = PCIE_PHY_CTRL_WR;
 250        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 251
 252        /* wait for ack */
 253        ret = pcie_phy_poll_ack(imx6_pcie, true);
 254        if (ret)
 255                return ret;
 256
 257        /* deassert wr signal */
 258        var = PCIE_PHY_CTRL_DATA(data);
 259        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, var);
 260
 261        /* wait for ack de-assertion */
 262        ret = pcie_phy_poll_ack(imx6_pcie, false);
 263        if (ret)
 264                return ret;
 265
 266        dw_pcie_writel_dbi(pci, PCIE_PHY_CTRL, 0x0);
 267
 268        return 0;
 269}
 270
 271static void imx6_pcie_reset_phy(struct imx6_pcie *imx6_pcie)
 272{
 273        u16 tmp;
 274
 275        if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
 276                return;
 277
 278        pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 279        tmp |= (PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 280                PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 281        pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
 282
 283        usleep_range(2000, 3000);
 284
 285        pcie_phy_read(imx6_pcie, PHY_RX_OVRD_IN_LO, &tmp);
 286        tmp &= ~(PHY_RX_OVRD_IN_LO_RX_DATA_EN |
 287                  PHY_RX_OVRD_IN_LO_RX_PLL_EN);
 288        pcie_phy_write(imx6_pcie, PHY_RX_OVRD_IN_LO, tmp);
 289}
 290
 291#ifdef CONFIG_ARM
 292/*  Added for PCI abort handling */
 293static int imx6q_pcie_abort_handler(unsigned long addr,
 294                unsigned int fsr, struct pt_regs *regs)
 295{
 296        unsigned long pc = instruction_pointer(regs);
 297        unsigned long instr = *(unsigned long *)pc;
 298        int reg = (instr >> 12) & 15;
 299
 300        /*
 301         * If the instruction being executed was a read,
 302         * make it look like it read all-ones.
 303         */
 304        if ((instr & 0x0c100000) == 0x04100000) {
 305                unsigned long val;
 306
 307                if (instr & 0x00400000)
 308                        val = 255;
 309                else
 310                        val = -1;
 311
 312                regs->uregs[reg] = val;
 313                regs->ARM_pc += 4;
 314                return 0;
 315        }
 316
 317        if ((instr & 0x0e100090) == 0x00100090) {
 318                regs->uregs[reg] = -1;
 319                regs->ARM_pc += 4;
 320                return 0;
 321        }
 322
 323        return 1;
 324}
 325#endif
 326
 327static int imx6_pcie_attach_pd(struct device *dev)
 328{
 329        struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 330        struct device_link *link;
 331
 332        /* Do nothing when in a single power domain */
 333        if (dev->pm_domain)
 334                return 0;
 335
 336        imx6_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie");
 337        if (IS_ERR(imx6_pcie->pd_pcie))
 338                return PTR_ERR(imx6_pcie->pd_pcie);
 339        /* Do nothing when power domain missing */
 340        if (!imx6_pcie->pd_pcie)
 341                return 0;
 342        link = device_link_add(dev, imx6_pcie->pd_pcie,
 343                        DL_FLAG_STATELESS |
 344                        DL_FLAG_PM_RUNTIME |
 345                        DL_FLAG_RPM_ACTIVE);
 346        if (!link) {
 347                dev_err(dev, "Failed to add device_link to pcie pd.\n");
 348                return -EINVAL;
 349        }
 350
 351        imx6_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy");
 352        if (IS_ERR(imx6_pcie->pd_pcie_phy))
 353                return PTR_ERR(imx6_pcie->pd_pcie_phy);
 354
 355        link = device_link_add(dev, imx6_pcie->pd_pcie_phy,
 356                        DL_FLAG_STATELESS |
 357                        DL_FLAG_PM_RUNTIME |
 358                        DL_FLAG_RPM_ACTIVE);
 359        if (!link) {
 360                dev_err(dev, "Failed to add device_link to pcie_phy pd.\n");
 361                return -EINVAL;
 362        }
 363
 364        return 0;
 365}
 366
 367static void imx6_pcie_assert_core_reset(struct imx6_pcie *imx6_pcie)
 368{
 369        struct device *dev = imx6_pcie->pci->dev;
 370
 371        switch (imx6_pcie->drvdata->variant) {
 372        case IMX7D:
 373        case IMX8MQ:
 374                reset_control_assert(imx6_pcie->pciephy_reset);
 375                reset_control_assert(imx6_pcie->apps_reset);
 376                break;
 377        case IMX6SX:
 378                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 379                                   IMX6SX_GPR12_PCIE_TEST_POWERDOWN,
 380                                   IMX6SX_GPR12_PCIE_TEST_POWERDOWN);
 381                /* Force PCIe PHY reset */
 382                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
 383                                   IMX6SX_GPR5_PCIE_BTNRST_RESET,
 384                                   IMX6SX_GPR5_PCIE_BTNRST_RESET);
 385                break;
 386        case IMX6QP:
 387                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 388                                   IMX6Q_GPR1_PCIE_SW_RST,
 389                                   IMX6Q_GPR1_PCIE_SW_RST);
 390                break;
 391        case IMX6Q:
 392                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 393                                   IMX6Q_GPR1_PCIE_TEST_PD, 1 << 18);
 394                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 395                                   IMX6Q_GPR1_PCIE_REF_CLK_EN, 0 << 16);
 396                break;
 397        }
 398
 399        if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
 400                int ret = regulator_disable(imx6_pcie->vpcie);
 401
 402                if (ret)
 403                        dev_err(dev, "failed to disable vpcie regulator: %d\n",
 404                                ret);
 405        }
 406}
 407
 408static unsigned int imx6_pcie_grp_offset(const struct imx6_pcie *imx6_pcie)
 409{
 410        WARN_ON(imx6_pcie->drvdata->variant != IMX8MQ);
 411        return imx6_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14;
 412}
 413
 414static int imx6_pcie_enable_ref_clk(struct imx6_pcie *imx6_pcie)
 415{
 416        struct dw_pcie *pci = imx6_pcie->pci;
 417        struct device *dev = pci->dev;
 418        unsigned int offset;
 419        int ret = 0;
 420
 421        switch (imx6_pcie->drvdata->variant) {
 422        case IMX6SX:
 423                ret = clk_prepare_enable(imx6_pcie->pcie_inbound_axi);
 424                if (ret) {
 425                        dev_err(dev, "unable to enable pcie_axi clock\n");
 426                        break;
 427                }
 428
 429                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 430                                   IMX6SX_GPR12_PCIE_TEST_POWERDOWN, 0);
 431                break;
 432        case IMX6QP:
 433        case IMX6Q:
 434                /* power up core phy and enable ref clock */
 435                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 436                                   IMX6Q_GPR1_PCIE_TEST_PD, 0 << 18);
 437                /*
 438                 * the async reset input need ref clock to sync internally,
 439                 * when the ref clock comes after reset, internal synced
 440                 * reset time is too short, cannot meet the requirement.
 441                 * add one ~10us delay here.
 442                 */
 443                usleep_range(10, 100);
 444                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 445                                   IMX6Q_GPR1_PCIE_REF_CLK_EN, 1 << 16);
 446                break;
 447        case IMX7D:
 448                break;
 449        case IMX8MQ:
 450                ret = clk_prepare_enable(imx6_pcie->pcie_aux);
 451                if (ret) {
 452                        dev_err(dev, "unable to enable pcie_aux clock\n");
 453                        break;
 454                }
 455
 456                offset = imx6_pcie_grp_offset(imx6_pcie);
 457                /*
 458                 * Set the over ride low and enabled
 459                 * make sure that REF_CLK is turned on.
 460                 */
 461                regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
 462                                   IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE,
 463                                   0);
 464                regmap_update_bits(imx6_pcie->iomuxc_gpr, offset,
 465                                   IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN,
 466                                   IMX8MQ_GPR_PCIE_CLK_REQ_OVERRIDE_EN);
 467                break;
 468        }
 469
 470        return ret;
 471}
 472
 473static void imx7d_pcie_wait_for_phy_pll_lock(struct imx6_pcie *imx6_pcie)
 474{
 475        u32 val;
 476        struct device *dev = imx6_pcie->pci->dev;
 477
 478        if (regmap_read_poll_timeout(imx6_pcie->iomuxc_gpr,
 479                                     IOMUXC_GPR22, val,
 480                                     val & IMX7D_GPR22_PCIE_PHY_PLL_LOCKED,
 481                                     PHY_PLL_LOCK_WAIT_USLEEP_MAX,
 482                                     PHY_PLL_LOCK_WAIT_TIMEOUT))
 483                dev_err(dev, "PCIe PLL lock timeout\n");
 484}
 485
 486static void imx6_pcie_deassert_core_reset(struct imx6_pcie *imx6_pcie)
 487{
 488        struct dw_pcie *pci = imx6_pcie->pci;
 489        struct device *dev = pci->dev;
 490        int ret;
 491
 492        if (imx6_pcie->vpcie && !regulator_is_enabled(imx6_pcie->vpcie)) {
 493                ret = regulator_enable(imx6_pcie->vpcie);
 494                if (ret) {
 495                        dev_err(dev, "failed to enable vpcie regulator: %d\n",
 496                                ret);
 497                        return;
 498                }
 499        }
 500
 501        ret = clk_prepare_enable(imx6_pcie->pcie_phy);
 502        if (ret) {
 503                dev_err(dev, "unable to enable pcie_phy clock\n");
 504                goto err_pcie_phy;
 505        }
 506
 507        ret = clk_prepare_enable(imx6_pcie->pcie_bus);
 508        if (ret) {
 509                dev_err(dev, "unable to enable pcie_bus clock\n");
 510                goto err_pcie_bus;
 511        }
 512
 513        ret = clk_prepare_enable(imx6_pcie->pcie);
 514        if (ret) {
 515                dev_err(dev, "unable to enable pcie clock\n");
 516                goto err_pcie;
 517        }
 518
 519        ret = imx6_pcie_enable_ref_clk(imx6_pcie);
 520        if (ret) {
 521                dev_err(dev, "unable to enable pcie ref clock\n");
 522                goto err_ref_clk;
 523        }
 524
 525        /* allow the clocks to stabilize */
 526        usleep_range(200, 500);
 527
 528        /* Some boards don't have PCIe reset GPIO. */
 529        if (gpio_is_valid(imx6_pcie->reset_gpio)) {
 530                gpio_set_value_cansleep(imx6_pcie->reset_gpio,
 531                                        imx6_pcie->gpio_active_high);
 532                msleep(100);
 533                gpio_set_value_cansleep(imx6_pcie->reset_gpio,
 534                                        !imx6_pcie->gpio_active_high);
 535        }
 536
 537        switch (imx6_pcie->drvdata->variant) {
 538        case IMX8MQ:
 539                reset_control_deassert(imx6_pcie->pciephy_reset);
 540                break;
 541        case IMX7D:
 542                reset_control_deassert(imx6_pcie->pciephy_reset);
 543
 544                /* Workaround for ERR010728, failure of PCI-e PLL VCO to
 545                 * oscillate, especially when cold.  This turns off "Duty-cycle
 546                 * Corrector" and other mysterious undocumented things.
 547                 */
 548                if (likely(imx6_pcie->phy_base)) {
 549                        /* De-assert DCC_FB_EN */
 550                        writel(PCIE_PHY_CMN_REG4_DCC_FB_EN,
 551                               imx6_pcie->phy_base + PCIE_PHY_CMN_REG4);
 552                        /* Assert RX_EQS and RX_EQS_SEL */
 553                        writel(PCIE_PHY_CMN_REG24_RX_EQ_SEL
 554                                | PCIE_PHY_CMN_REG24_RX_EQ,
 555                               imx6_pcie->phy_base + PCIE_PHY_CMN_REG24);
 556                        /* Assert ATT_MODE */
 557                        writel(PCIE_PHY_CMN_REG26_ATT_MODE,
 558                               imx6_pcie->phy_base + PCIE_PHY_CMN_REG26);
 559                } else {
 560                        dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n");
 561                }
 562
 563                imx7d_pcie_wait_for_phy_pll_lock(imx6_pcie);
 564                break;
 565        case IMX6SX:
 566                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR5,
 567                                   IMX6SX_GPR5_PCIE_BTNRST_RESET, 0);
 568                break;
 569        case IMX6QP:
 570                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR1,
 571                                   IMX6Q_GPR1_PCIE_SW_RST, 0);
 572
 573                usleep_range(200, 500);
 574                break;
 575        case IMX6Q:             /* Nothing to do */
 576                break;
 577        }
 578
 579        return;
 580
 581err_ref_clk:
 582        clk_disable_unprepare(imx6_pcie->pcie);
 583err_pcie:
 584        clk_disable_unprepare(imx6_pcie->pcie_bus);
 585err_pcie_bus:
 586        clk_disable_unprepare(imx6_pcie->pcie_phy);
 587err_pcie_phy:
 588        if (imx6_pcie->vpcie && regulator_is_enabled(imx6_pcie->vpcie) > 0) {
 589                ret = regulator_disable(imx6_pcie->vpcie);
 590                if (ret)
 591                        dev_err(dev, "failed to disable vpcie regulator: %d\n",
 592                                ret);
 593        }
 594}
 595
 596static void imx6_pcie_configure_type(struct imx6_pcie *imx6_pcie)
 597{
 598        unsigned int mask, val;
 599
 600        if (imx6_pcie->drvdata->variant == IMX8MQ &&
 601            imx6_pcie->controller_id == 1) {
 602                mask   = IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE;
 603                val    = FIELD_PREP(IMX8MQ_GPR12_PCIE2_CTRL_DEVICE_TYPE,
 604                                    PCI_EXP_TYPE_ROOT_PORT);
 605        } else {
 606                mask = IMX6Q_GPR12_DEVICE_TYPE;
 607                val  = FIELD_PREP(IMX6Q_GPR12_DEVICE_TYPE,
 608                                  PCI_EXP_TYPE_ROOT_PORT);
 609        }
 610
 611        regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, mask, val);
 612}
 613
 614static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie)
 615{
 616        switch (imx6_pcie->drvdata->variant) {
 617        case IMX8MQ:
 618                /*
 619                 * TODO: Currently this code assumes external
 620                 * oscillator is being used
 621                 */
 622                regmap_update_bits(imx6_pcie->iomuxc_gpr,
 623                                   imx6_pcie_grp_offset(imx6_pcie),
 624                                   IMX8MQ_GPR_PCIE_REF_USE_PAD,
 625                                   IMX8MQ_GPR_PCIE_REF_USE_PAD);
 626                /*
 627                 * Regarding the datasheet, the PCIE_VPH is suggested
 628                 * to be 1.8V. If the PCIE_VPH is supplied by 3.3V, the
 629                 * VREG_BYPASS should be cleared to zero.
 630                 */
 631                if (imx6_pcie->vph &&
 632                    regulator_get_voltage(imx6_pcie->vph) > 3000000)
 633                        regmap_update_bits(imx6_pcie->iomuxc_gpr,
 634                                           imx6_pcie_grp_offset(imx6_pcie),
 635                                           IMX8MQ_GPR_PCIE_VREG_BYPASS,
 636                                           0);
 637                break;
 638        case IMX7D:
 639                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 640                                   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0);
 641                break;
 642        case IMX6SX:
 643                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 644                                   IMX6SX_GPR12_PCIE_RX_EQ_MASK,
 645                                   IMX6SX_GPR12_PCIE_RX_EQ_2);
 646                fallthrough;
 647        default:
 648                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 649                                   IMX6Q_GPR12_PCIE_CTL_2, 0 << 10);
 650
 651                /* configure constant input signal to the pcie ctrl and phy */
 652                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 653                                   IMX6Q_GPR12_LOS_LEVEL, 9 << 4);
 654
 655                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 656                                   IMX6Q_GPR8_TX_DEEMPH_GEN1,
 657                                   imx6_pcie->tx_deemph_gen1 << 0);
 658                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 659                                   IMX6Q_GPR8_TX_DEEMPH_GEN2_3P5DB,
 660                                   imx6_pcie->tx_deemph_gen2_3p5db << 6);
 661                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 662                                   IMX6Q_GPR8_TX_DEEMPH_GEN2_6DB,
 663                                   imx6_pcie->tx_deemph_gen2_6db << 12);
 664                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 665                                   IMX6Q_GPR8_TX_SWING_FULL,
 666                                   imx6_pcie->tx_swing_full << 18);
 667                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR8,
 668                                   IMX6Q_GPR8_TX_SWING_LOW,
 669                                   imx6_pcie->tx_swing_low << 25);
 670                break;
 671        }
 672
 673        imx6_pcie_configure_type(imx6_pcie);
 674}
 675
 676static int imx6_setup_phy_mpll(struct imx6_pcie *imx6_pcie)
 677{
 678        unsigned long phy_rate = clk_get_rate(imx6_pcie->pcie_phy);
 679        int mult, div;
 680        u16 val;
 681
 682        if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_IMX6_PHY))
 683                return 0;
 684
 685        switch (phy_rate) {
 686        case 125000000:
 687                /*
 688                 * The default settings of the MPLL are for a 125MHz input
 689                 * clock, so no need to reconfigure anything in that case.
 690                 */
 691                return 0;
 692        case 100000000:
 693                mult = 25;
 694                div = 0;
 695                break;
 696        case 200000000:
 697                mult = 25;
 698                div = 1;
 699                break;
 700        default:
 701                dev_err(imx6_pcie->pci->dev,
 702                        "Unsupported PHY reference clock rate %lu\n", phy_rate);
 703                return -EINVAL;
 704        }
 705
 706        pcie_phy_read(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, &val);
 707        val &= ~(PCIE_PHY_MPLL_MULTIPLIER_MASK <<
 708                 PCIE_PHY_MPLL_MULTIPLIER_SHIFT);
 709        val |= mult << PCIE_PHY_MPLL_MULTIPLIER_SHIFT;
 710        val |= PCIE_PHY_MPLL_MULTIPLIER_OVRD;
 711        pcie_phy_write(imx6_pcie, PCIE_PHY_MPLL_OVRD_IN_LO, val);
 712
 713        pcie_phy_read(imx6_pcie, PCIE_PHY_ATEOVRD, &val);
 714        val &= ~(PCIE_PHY_ATEOVRD_REF_CLKDIV_MASK <<
 715                 PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT);
 716        val |= div << PCIE_PHY_ATEOVRD_REF_CLKDIV_SHIFT;
 717        val |= PCIE_PHY_ATEOVRD_EN;
 718        pcie_phy_write(imx6_pcie, PCIE_PHY_ATEOVRD, val);
 719
 720        return 0;
 721}
 722
 723static int imx6_pcie_wait_for_speed_change(struct imx6_pcie *imx6_pcie)
 724{
 725        struct dw_pcie *pci = imx6_pcie->pci;
 726        struct device *dev = pci->dev;
 727        u32 tmp;
 728        unsigned int retries;
 729
 730        for (retries = 0; retries < 200; retries++) {
 731                tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 732                /* Test if the speed change finished. */
 733                if (!(tmp & PORT_LOGIC_SPEED_CHANGE))
 734                        return 0;
 735                usleep_range(100, 1000);
 736        }
 737
 738        dev_err(dev, "Speed change timeout\n");
 739        return -ETIMEDOUT;
 740}
 741
 742static void imx6_pcie_ltssm_enable(struct device *dev)
 743{
 744        struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 745
 746        switch (imx6_pcie->drvdata->variant) {
 747        case IMX6Q:
 748        case IMX6SX:
 749        case IMX6QP:
 750                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 751                                   IMX6Q_GPR12_PCIE_CTL_2,
 752                                   IMX6Q_GPR12_PCIE_CTL_2);
 753                break;
 754        case IMX7D:
 755        case IMX8MQ:
 756                reset_control_deassert(imx6_pcie->apps_reset);
 757                break;
 758        }
 759}
 760
 761static int imx6_pcie_start_link(struct dw_pcie *pci)
 762{
 763        struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
 764        struct device *dev = pci->dev;
 765        u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP);
 766        u32 tmp;
 767        int ret;
 768
 769        /*
 770         * Force Gen1 operation when starting the link.  In case the link is
 771         * started in Gen2 mode, there is a possibility the devices on the
 772         * bus will not be detected at all.  This happens with PCIe switches.
 773         */
 774        tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 775        tmp &= ~PCI_EXP_LNKCAP_SLS;
 776        tmp |= PCI_EXP_LNKCAP_SLS_2_5GB;
 777        dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
 778
 779        /* Start LTSSM. */
 780        imx6_pcie_ltssm_enable(dev);
 781
 782        ret = dw_pcie_wait_for_link(pci);
 783        if (ret)
 784                goto err_reset_phy;
 785
 786        if (pci->link_gen == 2) {
 787                /* Allow Gen2 mode after the link is up. */
 788                tmp = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP);
 789                tmp &= ~PCI_EXP_LNKCAP_SLS;
 790                tmp |= PCI_EXP_LNKCAP_SLS_5_0GB;
 791                dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, tmp);
 792
 793                /*
 794                 * Start Directed Speed Change so the best possible
 795                 * speed both link partners support can be negotiated.
 796                 */
 797                tmp = dw_pcie_readl_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL);
 798                tmp |= PORT_LOGIC_SPEED_CHANGE;
 799                dw_pcie_writel_dbi(pci, PCIE_LINK_WIDTH_SPEED_CONTROL, tmp);
 800
 801                if (imx6_pcie->drvdata->flags &
 802                    IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE) {
 803                        /*
 804                         * On i.MX7, DIRECT_SPEED_CHANGE behaves differently
 805                         * from i.MX6 family when no link speed transition
 806                         * occurs and we go Gen1 -> yep, Gen1. The difference
 807                         * is that, in such case, it will not be cleared by HW
 808                         * which will cause the following code to report false
 809                         * failure.
 810                         */
 811
 812                        ret = imx6_pcie_wait_for_speed_change(imx6_pcie);
 813                        if (ret) {
 814                                dev_err(dev, "Failed to bring link up!\n");
 815                                goto err_reset_phy;
 816                        }
 817                }
 818
 819                /* Make sure link training is finished as well! */
 820                ret = dw_pcie_wait_for_link(pci);
 821                if (ret) {
 822                        dev_err(dev, "Failed to bring link up!\n");
 823                        goto err_reset_phy;
 824                }
 825        } else {
 826                dev_info(dev, "Link: Gen2 disabled\n");
 827        }
 828
 829        tmp = dw_pcie_readw_dbi(pci, offset + PCI_EXP_LNKSTA);
 830        dev_info(dev, "Link up, Gen%i\n", tmp & PCI_EXP_LNKSTA_CLS);
 831        return 0;
 832
 833err_reset_phy:
 834        dev_dbg(dev, "PHY DEBUG_R0=0x%08x DEBUG_R1=0x%08x\n",
 835                dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG0),
 836                dw_pcie_readl_dbi(pci, PCIE_PORT_DEBUG1));
 837        imx6_pcie_reset_phy(imx6_pcie);
 838        return ret;
 839}
 840
 841static int imx6_pcie_host_init(struct pcie_port *pp)
 842{
 843        struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
 844        struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
 845
 846        imx6_pcie_assert_core_reset(imx6_pcie);
 847        imx6_pcie_init_phy(imx6_pcie);
 848        imx6_pcie_deassert_core_reset(imx6_pcie);
 849        imx6_setup_phy_mpll(imx6_pcie);
 850
 851        return 0;
 852}
 853
 854static const struct dw_pcie_host_ops imx6_pcie_host_ops = {
 855        .host_init = imx6_pcie_host_init,
 856};
 857
 858static const struct dw_pcie_ops dw_pcie_ops = {
 859        .start_link = imx6_pcie_start_link,
 860};
 861
 862#ifdef CONFIG_PM_SLEEP
 863static void imx6_pcie_ltssm_disable(struct device *dev)
 864{
 865        struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 866
 867        switch (imx6_pcie->drvdata->variant) {
 868        case IMX6SX:
 869        case IMX6QP:
 870                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 871                                   IMX6Q_GPR12_PCIE_CTL_2, 0);
 872                break;
 873        case IMX7D:
 874                reset_control_assert(imx6_pcie->apps_reset);
 875                break;
 876        default:
 877                dev_err(dev, "ltssm_disable not supported\n");
 878        }
 879}
 880
 881static void imx6_pcie_pm_turnoff(struct imx6_pcie *imx6_pcie)
 882{
 883        struct device *dev = imx6_pcie->pci->dev;
 884
 885        /* Some variants have a turnoff reset in DT */
 886        if (imx6_pcie->turnoff_reset) {
 887                reset_control_assert(imx6_pcie->turnoff_reset);
 888                reset_control_deassert(imx6_pcie->turnoff_reset);
 889                goto pm_turnoff_sleep;
 890        }
 891
 892        /* Others poke directly at IOMUXC registers */
 893        switch (imx6_pcie->drvdata->variant) {
 894        case IMX6SX:
 895                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 896                                IMX6SX_GPR12_PCIE_PM_TURN_OFF,
 897                                IMX6SX_GPR12_PCIE_PM_TURN_OFF);
 898                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 899                                IMX6SX_GPR12_PCIE_PM_TURN_OFF, 0);
 900                break;
 901        default:
 902                dev_err(dev, "PME_Turn_Off not implemented\n");
 903                return;
 904        }
 905
 906        /*
 907         * Components with an upstream port must respond to
 908         * PME_Turn_Off with PME_TO_Ack but we can't check.
 909         *
 910         * The standard recommends a 1-10ms timeout after which to
 911         * proceed anyway as if acks were received.
 912         */
 913pm_turnoff_sleep:
 914        usleep_range(1000, 10000);
 915}
 916
 917static void imx6_pcie_clk_disable(struct imx6_pcie *imx6_pcie)
 918{
 919        clk_disable_unprepare(imx6_pcie->pcie);
 920        clk_disable_unprepare(imx6_pcie->pcie_phy);
 921        clk_disable_unprepare(imx6_pcie->pcie_bus);
 922
 923        switch (imx6_pcie->drvdata->variant) {
 924        case IMX6SX:
 925                clk_disable_unprepare(imx6_pcie->pcie_inbound_axi);
 926                break;
 927        case IMX7D:
 928                regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12,
 929                                   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL,
 930                                   IMX7D_GPR12_PCIE_PHY_REFCLK_SEL);
 931                break;
 932        case IMX8MQ:
 933                clk_disable_unprepare(imx6_pcie->pcie_aux);
 934                break;
 935        default:
 936                break;
 937        }
 938}
 939
 940static int imx6_pcie_suspend_noirq(struct device *dev)
 941{
 942        struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 943
 944        if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
 945                return 0;
 946
 947        imx6_pcie_pm_turnoff(imx6_pcie);
 948        imx6_pcie_clk_disable(imx6_pcie);
 949        imx6_pcie_ltssm_disable(dev);
 950
 951        return 0;
 952}
 953
 954static int imx6_pcie_resume_noirq(struct device *dev)
 955{
 956        int ret;
 957        struct imx6_pcie *imx6_pcie = dev_get_drvdata(dev);
 958        struct pcie_port *pp = &imx6_pcie->pci->pp;
 959
 960        if (!(imx6_pcie->drvdata->flags & IMX6_PCIE_FLAG_SUPPORTS_SUSPEND))
 961                return 0;
 962
 963        imx6_pcie_assert_core_reset(imx6_pcie);
 964        imx6_pcie_init_phy(imx6_pcie);
 965        imx6_pcie_deassert_core_reset(imx6_pcie);
 966        dw_pcie_setup_rc(pp);
 967
 968        ret = imx6_pcie_start_link(imx6_pcie->pci);
 969        if (ret < 0)
 970                dev_info(dev, "pcie link is down after resume.\n");
 971
 972        return 0;
 973}
 974#endif
 975
 976static const struct dev_pm_ops imx6_pcie_pm_ops = {
 977        SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(imx6_pcie_suspend_noirq,
 978                                      imx6_pcie_resume_noirq)
 979};
 980
 981static int imx6_pcie_probe(struct platform_device *pdev)
 982{
 983        struct device *dev = &pdev->dev;
 984        struct dw_pcie *pci;
 985        struct imx6_pcie *imx6_pcie;
 986        struct device_node *np;
 987        struct resource *dbi_base;
 988        struct device_node *node = dev->of_node;
 989        int ret;
 990        u16 val;
 991
 992        imx6_pcie = devm_kzalloc(dev, sizeof(*imx6_pcie), GFP_KERNEL);
 993        if (!imx6_pcie)
 994                return -ENOMEM;
 995
 996        pci = devm_kzalloc(dev, sizeof(*pci), GFP_KERNEL);
 997        if (!pci)
 998                return -ENOMEM;
 999
1000        pci->dev = dev;
1001        pci->ops = &dw_pcie_ops;
1002        pci->pp.ops = &imx6_pcie_host_ops;
1003
1004        imx6_pcie->pci = pci;
1005        imx6_pcie->drvdata = of_device_get_match_data(dev);
1006
1007        /* Find the PHY if one is defined, only imx7d uses it */
1008        np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0);
1009        if (np) {
1010                struct resource res;
1011
1012                ret = of_address_to_resource(np, 0, &res);
1013                if (ret) {
1014                        dev_err(dev, "Unable to map PCIe PHY\n");
1015                        return ret;
1016                }
1017                imx6_pcie->phy_base = devm_ioremap_resource(dev, &res);
1018                if (IS_ERR(imx6_pcie->phy_base))
1019                        return PTR_ERR(imx6_pcie->phy_base);
1020        }
1021
1022        dbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1023        pci->dbi_base = devm_ioremap_resource(dev, dbi_base);
1024        if (IS_ERR(pci->dbi_base))
1025                return PTR_ERR(pci->dbi_base);
1026
1027        /* Fetch GPIOs */
1028        imx6_pcie->reset_gpio = of_get_named_gpio(node, "reset-gpio", 0);
1029        imx6_pcie->gpio_active_high = of_property_read_bool(node,
1030                                                "reset-gpio-active-high");
1031        if (gpio_is_valid(imx6_pcie->reset_gpio)) {
1032                ret = devm_gpio_request_one(dev, imx6_pcie->reset_gpio,
1033                                imx6_pcie->gpio_active_high ?
1034                                        GPIOF_OUT_INIT_HIGH :
1035                                        GPIOF_OUT_INIT_LOW,
1036                                "PCIe reset");
1037                if (ret) {
1038                        dev_err(dev, "unable to get reset gpio\n");
1039                        return ret;
1040                }
1041        } else if (imx6_pcie->reset_gpio == -EPROBE_DEFER) {
1042                return imx6_pcie->reset_gpio;
1043        }
1044
1045        /* Fetch clocks */
1046        imx6_pcie->pcie_phy = devm_clk_get(dev, "pcie_phy");
1047        if (IS_ERR(imx6_pcie->pcie_phy))
1048                return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_phy),
1049                                     "pcie_phy clock source missing or invalid\n");
1050
1051        imx6_pcie->pcie_bus = devm_clk_get(dev, "pcie_bus");
1052        if (IS_ERR(imx6_pcie->pcie_bus))
1053                return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_bus),
1054                                     "pcie_bus clock source missing or invalid\n");
1055
1056        imx6_pcie->pcie = devm_clk_get(dev, "pcie");
1057        if (IS_ERR(imx6_pcie->pcie))
1058                return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie),
1059                                     "pcie clock source missing or invalid\n");
1060
1061        switch (imx6_pcie->drvdata->variant) {
1062        case IMX6SX:
1063                imx6_pcie->pcie_inbound_axi = devm_clk_get(dev,
1064                                                           "pcie_inbound_axi");
1065                if (IS_ERR(imx6_pcie->pcie_inbound_axi))
1066                        return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_inbound_axi),
1067                                             "pcie_inbound_axi clock missing or invalid\n");
1068                break;
1069        case IMX8MQ:
1070                imx6_pcie->pcie_aux = devm_clk_get(dev, "pcie_aux");
1071                if (IS_ERR(imx6_pcie->pcie_aux))
1072                        return dev_err_probe(dev, PTR_ERR(imx6_pcie->pcie_aux),
1073                                             "pcie_aux clock source missing or invalid\n");
1074                fallthrough;
1075        case IMX7D:
1076                if (dbi_base->start == IMX8MQ_PCIE2_BASE_ADDR)
1077                        imx6_pcie->controller_id = 1;
1078
1079                imx6_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev,
1080                                                                            "pciephy");
1081                if (IS_ERR(imx6_pcie->pciephy_reset)) {
1082                        dev_err(dev, "Failed to get PCIEPHY reset control\n");
1083                        return PTR_ERR(imx6_pcie->pciephy_reset);
1084                }
1085
1086                imx6_pcie->apps_reset = devm_reset_control_get_exclusive(dev,
1087                                                                         "apps");
1088                if (IS_ERR(imx6_pcie->apps_reset)) {
1089                        dev_err(dev, "Failed to get PCIE APPS reset control\n");
1090                        return PTR_ERR(imx6_pcie->apps_reset);
1091                }
1092                break;
1093        default:
1094                break;
1095        }
1096
1097        /* Grab turnoff reset */
1098        imx6_pcie->turnoff_reset = devm_reset_control_get_optional_exclusive(dev, "turnoff");
1099        if (IS_ERR(imx6_pcie->turnoff_reset)) {
1100                dev_err(dev, "Failed to get TURNOFF reset control\n");
1101                return PTR_ERR(imx6_pcie->turnoff_reset);
1102        }
1103
1104        /* Grab GPR config register range */
1105        imx6_pcie->iomuxc_gpr =
1106                 syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
1107        if (IS_ERR(imx6_pcie->iomuxc_gpr)) {
1108                dev_err(dev, "unable to find iomuxc registers\n");
1109                return PTR_ERR(imx6_pcie->iomuxc_gpr);
1110        }
1111
1112        /* Grab PCIe PHY Tx Settings */
1113        if (of_property_read_u32(node, "fsl,tx-deemph-gen1",
1114                                 &imx6_pcie->tx_deemph_gen1))
1115                imx6_pcie->tx_deemph_gen1 = 0;
1116
1117        if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db",
1118                                 &imx6_pcie->tx_deemph_gen2_3p5db))
1119                imx6_pcie->tx_deemph_gen2_3p5db = 0;
1120
1121        if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db",
1122                                 &imx6_pcie->tx_deemph_gen2_6db))
1123                imx6_pcie->tx_deemph_gen2_6db = 20;
1124
1125        if (of_property_read_u32(node, "fsl,tx-swing-full",
1126                                 &imx6_pcie->tx_swing_full))
1127                imx6_pcie->tx_swing_full = 127;
1128
1129        if (of_property_read_u32(node, "fsl,tx-swing-low",
1130                                 &imx6_pcie->tx_swing_low))
1131                imx6_pcie->tx_swing_low = 127;
1132
1133        /* Limit link speed */
1134        pci->link_gen = 1;
1135        ret = of_property_read_u32(node, "fsl,max-link-speed", &pci->link_gen);
1136
1137        imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie");
1138        if (IS_ERR(imx6_pcie->vpcie)) {
1139                if (PTR_ERR(imx6_pcie->vpcie) != -ENODEV)
1140                        return PTR_ERR(imx6_pcie->vpcie);
1141                imx6_pcie->vpcie = NULL;
1142        }
1143
1144        imx6_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph");
1145        if (IS_ERR(imx6_pcie->vph)) {
1146                if (PTR_ERR(imx6_pcie->vph) != -ENODEV)
1147                        return PTR_ERR(imx6_pcie->vph);
1148                imx6_pcie->vph = NULL;
1149        }
1150
1151        platform_set_drvdata(pdev, imx6_pcie);
1152
1153        ret = imx6_pcie_attach_pd(dev);
1154        if (ret)
1155                return ret;
1156
1157        ret = dw_pcie_host_init(&pci->pp);
1158        if (ret < 0)
1159                return ret;
1160
1161        if (pci_msi_enabled()) {
1162                u8 offset = dw_pcie_find_capability(pci, PCI_CAP_ID_MSI);
1163                val = dw_pcie_readw_dbi(pci, offset + PCI_MSI_FLAGS);
1164                val |= PCI_MSI_FLAGS_ENABLE;
1165                dw_pcie_writew_dbi(pci, offset + PCI_MSI_FLAGS, val);
1166        }
1167
1168        return 0;
1169}
1170
1171static void imx6_pcie_shutdown(struct platform_device *pdev)
1172{
1173        struct imx6_pcie *imx6_pcie = platform_get_drvdata(pdev);
1174
1175        /* bring down link, so bootloader gets clean state in case of reboot */
1176        imx6_pcie_assert_core_reset(imx6_pcie);
1177}
1178
1179static const struct imx6_pcie_drvdata drvdata[] = {
1180        [IMX6Q] = {
1181                .variant = IMX6Q,
1182                .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1183                         IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1184                .dbi_length = 0x200,
1185        },
1186        [IMX6SX] = {
1187                .variant = IMX6SX,
1188                .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1189                         IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE |
1190                         IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1191        },
1192        [IMX6QP] = {
1193                .variant = IMX6QP,
1194                .flags = IMX6_PCIE_FLAG_IMX6_PHY |
1195                         IMX6_PCIE_FLAG_IMX6_SPEED_CHANGE,
1196                .dbi_length = 0x200,
1197        },
1198        [IMX7D] = {
1199                .variant = IMX7D,
1200                .flags = IMX6_PCIE_FLAG_SUPPORTS_SUSPEND,
1201        },
1202        [IMX8MQ] = {
1203                .variant = IMX8MQ,
1204        },
1205};
1206
1207static const struct of_device_id imx6_pcie_of_match[] = {
1208        { .compatible = "fsl,imx6q-pcie",  .data = &drvdata[IMX6Q],  },
1209        { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1210        { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1211        { .compatible = "fsl,imx7d-pcie",  .data = &drvdata[IMX7D],  },
1212        { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], } ,
1213        {},
1214};
1215
1216static struct platform_driver imx6_pcie_driver = {
1217        .driver = {
1218                .name   = "imx6q-pcie",
1219                .of_match_table = imx6_pcie_of_match,
1220                .suppress_bind_attrs = true,
1221                .pm = &imx6_pcie_pm_ops,
1222                .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1223        },
1224        .probe    = imx6_pcie_probe,
1225        .shutdown = imx6_pcie_shutdown,
1226};
1227
1228static void imx6_pcie_quirk(struct pci_dev *dev)
1229{
1230        struct pci_bus *bus = dev->bus;
1231        struct pcie_port *pp = bus->sysdata;
1232
1233        /* Bus parent is the PCI bridge, its parent is this platform driver */
1234        if (!bus->dev.parent || !bus->dev.parent->parent)
1235                return;
1236
1237        /* Make sure we only quirk devices associated with this driver */
1238        if (bus->dev.parent->parent->driver != &imx6_pcie_driver.driver)
1239                return;
1240
1241        if (pci_is_root_bus(bus)) {
1242                struct dw_pcie *pci = to_dw_pcie_from_pp(pp);
1243                struct imx6_pcie *imx6_pcie = to_imx6_pcie(pci);
1244
1245                /*
1246                 * Limit config length to avoid the kernel reading beyond
1247                 * the register set and causing an abort on i.MX 6Quad
1248                 */
1249                if (imx6_pcie->drvdata->dbi_length) {
1250                        dev->cfg_size = imx6_pcie->drvdata->dbi_length;
1251                        dev_info(&dev->dev, "Limiting cfg_size to %d\n",
1252                                        dev->cfg_size);
1253                }
1254        }
1255}
1256DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_SYNOPSYS, 0xabcd,
1257                        PCI_CLASS_BRIDGE_PCI, 8, imx6_pcie_quirk);
1258
1259static int __init imx6_pcie_init(void)
1260{
1261#ifdef CONFIG_ARM
1262        /*
1263         * Since probe() can be deferred we need to make sure that
1264         * hook_fault_code is not called after __init memory is freed
1265         * by kernel and since imx6q_pcie_abort_handler() is a no-op,
1266         * we can install the handler here without risking it
1267         * accessing some uninitialized driver state.
1268         */
1269        hook_fault_code(8, imx6q_pcie_abort_handler, SIGBUS, 0,
1270                        "external abort on non-linefetch");
1271#endif
1272
1273        return platform_driver_register(&imx6_pcie_driver);
1274}
1275device_initcall(imx6_pcie_init);
1276