linux/drivers/nvme/host/pci.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/*
   3 * NVM Express device driver
   4 * Copyright (c) 2011-2014, Intel Corporation.
   5 */
   6
   7#include <linux/acpi.h>
   8#include <linux/aer.h>
   9#include <linux/async.h>
  10#include <linux/blkdev.h>
  11#include <linux/blk-mq.h>
  12#include <linux/blk-mq-pci.h>
  13#include <linux/dmi.h>
  14#include <linux/init.h>
  15#include <linux/interrupt.h>
  16#include <linux/io.h>
  17#include <linux/mm.h>
  18#include <linux/module.h>
  19#include <linux/mutex.h>
  20#include <linux/once.h>
  21#include <linux/pci.h>
  22#include <linux/suspend.h>
  23#include <linux/t10-pi.h>
  24#include <linux/types.h>
  25#include <linux/io-64-nonatomic-lo-hi.h>
  26#include <linux/io-64-nonatomic-hi-lo.h>
  27#include <linux/sed-opal.h>
  28#include <linux/pci-p2pdma.h>
  29
  30#include "trace.h"
  31#include "nvme.h"
  32
  33#define SQ_SIZE(q)      ((q)->q_depth << (q)->sqes)
  34#define CQ_SIZE(q)      ((q)->q_depth * sizeof(struct nvme_completion))
  35
  36#define SGES_PER_PAGE   (PAGE_SIZE / sizeof(struct nvme_sgl_desc))
  37
  38/*
  39 * These can be higher, but we need to ensure that any command doesn't
  40 * require an sg allocation that needs more than a page of data.
  41 */
  42#define NVME_MAX_KB_SZ  4096
  43#define NVME_MAX_SEGS   127
  44
  45static int use_threaded_interrupts;
  46module_param(use_threaded_interrupts, int, 0);
  47
  48static bool use_cmb_sqes = true;
  49module_param(use_cmb_sqes, bool, 0444);
  50MODULE_PARM_DESC(use_cmb_sqes, "use controller's memory buffer for I/O SQes");
  51
  52static unsigned int max_host_mem_size_mb = 128;
  53module_param(max_host_mem_size_mb, uint, 0444);
  54MODULE_PARM_DESC(max_host_mem_size_mb,
  55        "Maximum Host Memory Buffer (HMB) size per controller (in MiB)");
  56
  57static unsigned int sgl_threshold = SZ_32K;
  58module_param(sgl_threshold, uint, 0644);
  59MODULE_PARM_DESC(sgl_threshold,
  60                "Use SGLs when average request segment size is larger or equal to "
  61                "this size. Use 0 to disable SGLs.");
  62
  63static int io_queue_depth_set(const char *val, const struct kernel_param *kp);
  64static const struct kernel_param_ops io_queue_depth_ops = {
  65        .set = io_queue_depth_set,
  66        .get = param_get_uint,
  67};
  68
  69static unsigned int io_queue_depth = 1024;
  70module_param_cb(io_queue_depth, &io_queue_depth_ops, &io_queue_depth, 0644);
  71MODULE_PARM_DESC(io_queue_depth, "set io queue depth, should >= 2");
  72
  73static int io_queue_count_set(const char *val, const struct kernel_param *kp)
  74{
  75        unsigned int n;
  76        int ret;
  77
  78        ret = kstrtouint(val, 10, &n);
  79        if (ret != 0 || n > num_possible_cpus())
  80                return -EINVAL;
  81        return param_set_uint(val, kp);
  82}
  83
  84static const struct kernel_param_ops io_queue_count_ops = {
  85        .set = io_queue_count_set,
  86        .get = param_get_uint,
  87};
  88
  89static unsigned int write_queues;
  90module_param_cb(write_queues, &io_queue_count_ops, &write_queues, 0644);
  91MODULE_PARM_DESC(write_queues,
  92        "Number of queues to use for writes. If not set, reads and writes "
  93        "will share a queue set.");
  94
  95static unsigned int poll_queues;
  96module_param_cb(poll_queues, &io_queue_count_ops, &poll_queues, 0644);
  97MODULE_PARM_DESC(poll_queues, "Number of queues to use for polled IO.");
  98
  99static bool noacpi;
 100module_param(noacpi, bool, 0444);
 101MODULE_PARM_DESC(noacpi, "disable acpi bios quirks");
 102
 103struct nvme_dev;
 104struct nvme_queue;
 105
 106static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown);
 107static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode);
 108
 109/*
 110 * Represents an NVM Express device.  Each nvme_dev is a PCI function.
 111 */
 112struct nvme_dev {
 113        struct nvme_queue *queues;
 114        struct blk_mq_tag_set tagset;
 115        struct blk_mq_tag_set admin_tagset;
 116        u32 __iomem *dbs;
 117        struct device *dev;
 118        struct dma_pool *prp_page_pool;
 119        struct dma_pool *prp_small_pool;
 120        unsigned online_queues;
 121        unsigned max_qid;
 122        unsigned io_queues[HCTX_MAX_TYPES];
 123        unsigned int num_vecs;
 124        u32 q_depth;
 125        int io_sqes;
 126        u32 db_stride;
 127        void __iomem *bar;
 128        unsigned long bar_mapped_size;
 129        struct work_struct remove_work;
 130        struct mutex shutdown_lock;
 131        bool subsystem;
 132        u64 cmb_size;
 133        bool cmb_use_sqes;
 134        u32 cmbsz;
 135        u32 cmbloc;
 136        struct nvme_ctrl ctrl;
 137        u32 last_ps;
 138
 139        mempool_t *iod_mempool;
 140
 141        /* shadow doorbell buffer support: */
 142        u32 *dbbuf_dbs;
 143        dma_addr_t dbbuf_dbs_dma_addr;
 144        u32 *dbbuf_eis;
 145        dma_addr_t dbbuf_eis_dma_addr;
 146
 147        /* host memory buffer support: */
 148        u64 host_mem_size;
 149        u32 nr_host_mem_descs;
 150        dma_addr_t host_mem_descs_dma;
 151        struct nvme_host_mem_buf_desc *host_mem_descs;
 152        void **host_mem_desc_bufs;
 153        unsigned int nr_allocated_queues;
 154        unsigned int nr_write_queues;
 155        unsigned int nr_poll_queues;
 156};
 157
 158static int io_queue_depth_set(const char *val, const struct kernel_param *kp)
 159{
 160        int ret;
 161        u32 n;
 162
 163        ret = kstrtou32(val, 10, &n);
 164        if (ret != 0 || n < 2)
 165                return -EINVAL;
 166
 167        return param_set_uint(val, kp);
 168}
 169
 170static inline unsigned int sq_idx(unsigned int qid, u32 stride)
 171{
 172        return qid * 2 * stride;
 173}
 174
 175static inline unsigned int cq_idx(unsigned int qid, u32 stride)
 176{
 177        return (qid * 2 + 1) * stride;
 178}
 179
 180static inline struct nvme_dev *to_nvme_dev(struct nvme_ctrl *ctrl)
 181{
 182        return container_of(ctrl, struct nvme_dev, ctrl);
 183}
 184
 185/*
 186 * An NVM Express queue.  Each device has at least two (one for admin
 187 * commands and one for I/O commands).
 188 */
 189struct nvme_queue {
 190        struct nvme_dev *dev;
 191        spinlock_t sq_lock;
 192        void *sq_cmds;
 193         /* only used for poll queues: */
 194        spinlock_t cq_poll_lock ____cacheline_aligned_in_smp;
 195        struct nvme_completion *cqes;
 196        dma_addr_t sq_dma_addr;
 197        dma_addr_t cq_dma_addr;
 198        u32 __iomem *q_db;
 199        u32 q_depth;
 200        u16 cq_vector;
 201        u16 sq_tail;
 202        u16 last_sq_tail;
 203        u16 cq_head;
 204        u16 qid;
 205        u8 cq_phase;
 206        u8 sqes;
 207        unsigned long flags;
 208#define NVMEQ_ENABLED           0
 209#define NVMEQ_SQ_CMB            1
 210#define NVMEQ_DELETE_ERROR      2
 211#define NVMEQ_POLLED            3
 212        u32 *dbbuf_sq_db;
 213        u32 *dbbuf_cq_db;
 214        u32 *dbbuf_sq_ei;
 215        u32 *dbbuf_cq_ei;
 216        struct completion delete_done;
 217};
 218
 219/*
 220 * The nvme_iod describes the data in an I/O.
 221 *
 222 * The sg pointer contains the list of PRP/SGL chunk allocations in addition
 223 * to the actual struct scatterlist.
 224 */
 225struct nvme_iod {
 226        struct nvme_request req;
 227        struct nvme_command cmd;
 228        struct nvme_queue *nvmeq;
 229        bool use_sgl;
 230        int aborted;
 231        int npages;             /* In the PRP list. 0 means small pool in use */
 232        int nents;              /* Used in scatterlist */
 233        dma_addr_t first_dma;
 234        unsigned int dma_len;   /* length of single DMA segment mapping */
 235        dma_addr_t meta_dma;
 236        struct scatterlist *sg;
 237};
 238
 239static inline unsigned int nvme_dbbuf_size(struct nvme_dev *dev)
 240{
 241        return dev->nr_allocated_queues * 8 * dev->db_stride;
 242}
 243
 244static int nvme_dbbuf_dma_alloc(struct nvme_dev *dev)
 245{
 246        unsigned int mem_size = nvme_dbbuf_size(dev);
 247
 248        if (dev->dbbuf_dbs)
 249                return 0;
 250
 251        dev->dbbuf_dbs = dma_alloc_coherent(dev->dev, mem_size,
 252                                            &dev->dbbuf_dbs_dma_addr,
 253                                            GFP_KERNEL);
 254        if (!dev->dbbuf_dbs)
 255                return -ENOMEM;
 256        dev->dbbuf_eis = dma_alloc_coherent(dev->dev, mem_size,
 257                                            &dev->dbbuf_eis_dma_addr,
 258                                            GFP_KERNEL);
 259        if (!dev->dbbuf_eis) {
 260                dma_free_coherent(dev->dev, mem_size,
 261                                  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 262                dev->dbbuf_dbs = NULL;
 263                return -ENOMEM;
 264        }
 265
 266        return 0;
 267}
 268
 269static void nvme_dbbuf_dma_free(struct nvme_dev *dev)
 270{
 271        unsigned int mem_size = nvme_dbbuf_size(dev);
 272
 273        if (dev->dbbuf_dbs) {
 274                dma_free_coherent(dev->dev, mem_size,
 275                                  dev->dbbuf_dbs, dev->dbbuf_dbs_dma_addr);
 276                dev->dbbuf_dbs = NULL;
 277        }
 278        if (dev->dbbuf_eis) {
 279                dma_free_coherent(dev->dev, mem_size,
 280                                  dev->dbbuf_eis, dev->dbbuf_eis_dma_addr);
 281                dev->dbbuf_eis = NULL;
 282        }
 283}
 284
 285static void nvme_dbbuf_init(struct nvme_dev *dev,
 286                            struct nvme_queue *nvmeq, int qid)
 287{
 288        if (!dev->dbbuf_dbs || !qid)
 289                return;
 290
 291        nvmeq->dbbuf_sq_db = &dev->dbbuf_dbs[sq_idx(qid, dev->db_stride)];
 292        nvmeq->dbbuf_cq_db = &dev->dbbuf_dbs[cq_idx(qid, dev->db_stride)];
 293        nvmeq->dbbuf_sq_ei = &dev->dbbuf_eis[sq_idx(qid, dev->db_stride)];
 294        nvmeq->dbbuf_cq_ei = &dev->dbbuf_eis[cq_idx(qid, dev->db_stride)];
 295}
 296
 297static void nvme_dbbuf_free(struct nvme_queue *nvmeq)
 298{
 299        if (!nvmeq->qid)
 300                return;
 301
 302        nvmeq->dbbuf_sq_db = NULL;
 303        nvmeq->dbbuf_cq_db = NULL;
 304        nvmeq->dbbuf_sq_ei = NULL;
 305        nvmeq->dbbuf_cq_ei = NULL;
 306}
 307
 308static void nvme_dbbuf_set(struct nvme_dev *dev)
 309{
 310        struct nvme_command c = { };
 311        unsigned int i;
 312
 313        if (!dev->dbbuf_dbs)
 314                return;
 315
 316        c.dbbuf.opcode = nvme_admin_dbbuf;
 317        c.dbbuf.prp1 = cpu_to_le64(dev->dbbuf_dbs_dma_addr);
 318        c.dbbuf.prp2 = cpu_to_le64(dev->dbbuf_eis_dma_addr);
 319
 320        if (nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0)) {
 321                dev_warn(dev->ctrl.device, "unable to set dbbuf\n");
 322                /* Free memory and continue on */
 323                nvme_dbbuf_dma_free(dev);
 324
 325                for (i = 1; i <= dev->online_queues; i++)
 326                        nvme_dbbuf_free(&dev->queues[i]);
 327        }
 328}
 329
 330static inline int nvme_dbbuf_need_event(u16 event_idx, u16 new_idx, u16 old)
 331{
 332        return (u16)(new_idx - event_idx - 1) < (u16)(new_idx - old);
 333}
 334
 335/* Update dbbuf and return true if an MMIO is required */
 336static bool nvme_dbbuf_update_and_check_event(u16 value, u32 *dbbuf_db,
 337                                              volatile u32 *dbbuf_ei)
 338{
 339        if (dbbuf_db) {
 340                u16 old_value;
 341
 342                /*
 343                 * Ensure that the queue is written before updating
 344                 * the doorbell in memory
 345                 */
 346                wmb();
 347
 348                old_value = *dbbuf_db;
 349                *dbbuf_db = value;
 350
 351                /*
 352                 * Ensure that the doorbell is updated before reading the event
 353                 * index from memory.  The controller needs to provide similar
 354                 * ordering to ensure the envent index is updated before reading
 355                 * the doorbell.
 356                 */
 357                mb();
 358
 359                if (!nvme_dbbuf_need_event(*dbbuf_ei, value, old_value))
 360                        return false;
 361        }
 362
 363        return true;
 364}
 365
 366/*
 367 * Will slightly overestimate the number of pages needed.  This is OK
 368 * as it only leads to a small amount of wasted memory for the lifetime of
 369 * the I/O.
 370 */
 371static int nvme_pci_npages_prp(void)
 372{
 373        unsigned nprps = DIV_ROUND_UP(NVME_MAX_KB_SZ + NVME_CTRL_PAGE_SIZE,
 374                                      NVME_CTRL_PAGE_SIZE);
 375        return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
 376}
 377
 378/*
 379 * Calculates the number of pages needed for the SGL segments. For example a 4k
 380 * page can accommodate 256 SGL descriptors.
 381 */
 382static int nvme_pci_npages_sgl(void)
 383{
 384        return DIV_ROUND_UP(NVME_MAX_SEGS * sizeof(struct nvme_sgl_desc),
 385                        PAGE_SIZE);
 386}
 387
 388static size_t nvme_pci_iod_alloc_size(void)
 389{
 390        size_t npages = max(nvme_pci_npages_prp(), nvme_pci_npages_sgl());
 391
 392        return sizeof(__le64 *) * npages +
 393                sizeof(struct scatterlist) * NVME_MAX_SEGS;
 394}
 395
 396static int nvme_admin_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 397                                unsigned int hctx_idx)
 398{
 399        struct nvme_dev *dev = data;
 400        struct nvme_queue *nvmeq = &dev->queues[0];
 401
 402        WARN_ON(hctx_idx != 0);
 403        WARN_ON(dev->admin_tagset.tags[0] != hctx->tags);
 404
 405        hctx->driver_data = nvmeq;
 406        return 0;
 407}
 408
 409static int nvme_init_hctx(struct blk_mq_hw_ctx *hctx, void *data,
 410                          unsigned int hctx_idx)
 411{
 412        struct nvme_dev *dev = data;
 413        struct nvme_queue *nvmeq = &dev->queues[hctx_idx + 1];
 414
 415        WARN_ON(dev->tagset.tags[hctx_idx] != hctx->tags);
 416        hctx->driver_data = nvmeq;
 417        return 0;
 418}
 419
 420static int nvme_init_request(struct blk_mq_tag_set *set, struct request *req,
 421                unsigned int hctx_idx, unsigned int numa_node)
 422{
 423        struct nvme_dev *dev = set->driver_data;
 424        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 425        int queue_idx = (set == &dev->tagset) ? hctx_idx + 1 : 0;
 426        struct nvme_queue *nvmeq = &dev->queues[queue_idx];
 427
 428        BUG_ON(!nvmeq);
 429        iod->nvmeq = nvmeq;
 430
 431        nvme_req(req)->ctrl = &dev->ctrl;
 432        nvme_req(req)->cmd = &iod->cmd;
 433        return 0;
 434}
 435
 436static int queue_irq_offset(struct nvme_dev *dev)
 437{
 438        /* if we have more than 1 vec, admin queue offsets us by 1 */
 439        if (dev->num_vecs > 1)
 440                return 1;
 441
 442        return 0;
 443}
 444
 445static int nvme_pci_map_queues(struct blk_mq_tag_set *set)
 446{
 447        struct nvme_dev *dev = set->driver_data;
 448        int i, qoff, offset;
 449
 450        offset = queue_irq_offset(dev);
 451        for (i = 0, qoff = 0; i < set->nr_maps; i++) {
 452                struct blk_mq_queue_map *map = &set->map[i];
 453
 454                map->nr_queues = dev->io_queues[i];
 455                if (!map->nr_queues) {
 456                        BUG_ON(i == HCTX_TYPE_DEFAULT);
 457                        continue;
 458                }
 459
 460                /*
 461                 * The poll queue(s) doesn't have an IRQ (and hence IRQ
 462                 * affinity), so use the regular blk-mq cpu mapping
 463                 */
 464                map->queue_offset = qoff;
 465                if (i != HCTX_TYPE_POLL && offset)
 466                        blk_mq_pci_map_queues(map, to_pci_dev(dev->dev), offset);
 467                else
 468                        blk_mq_map_queues(map);
 469                qoff += map->nr_queues;
 470                offset += map->nr_queues;
 471        }
 472
 473        return 0;
 474}
 475
 476/*
 477 * Write sq tail if we are asked to, or if the next command would wrap.
 478 */
 479static inline void nvme_write_sq_db(struct nvme_queue *nvmeq, bool write_sq)
 480{
 481        if (!write_sq) {
 482                u16 next_tail = nvmeq->sq_tail + 1;
 483
 484                if (next_tail == nvmeq->q_depth)
 485                        next_tail = 0;
 486                if (next_tail != nvmeq->last_sq_tail)
 487                        return;
 488        }
 489
 490        if (nvme_dbbuf_update_and_check_event(nvmeq->sq_tail,
 491                        nvmeq->dbbuf_sq_db, nvmeq->dbbuf_sq_ei))
 492                writel(nvmeq->sq_tail, nvmeq->q_db);
 493        nvmeq->last_sq_tail = nvmeq->sq_tail;
 494}
 495
 496/**
 497 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
 498 * @nvmeq: The queue to use
 499 * @cmd: The command to send
 500 * @write_sq: whether to write to the SQ doorbell
 501 */
 502static void nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd,
 503                            bool write_sq)
 504{
 505        spin_lock(&nvmeq->sq_lock);
 506        memcpy(nvmeq->sq_cmds + (nvmeq->sq_tail << nvmeq->sqes),
 507               cmd, sizeof(*cmd));
 508        if (++nvmeq->sq_tail == nvmeq->q_depth)
 509                nvmeq->sq_tail = 0;
 510        nvme_write_sq_db(nvmeq, write_sq);
 511        spin_unlock(&nvmeq->sq_lock);
 512}
 513
 514static void nvme_commit_rqs(struct blk_mq_hw_ctx *hctx)
 515{
 516        struct nvme_queue *nvmeq = hctx->driver_data;
 517
 518        spin_lock(&nvmeq->sq_lock);
 519        if (nvmeq->sq_tail != nvmeq->last_sq_tail)
 520                nvme_write_sq_db(nvmeq, true);
 521        spin_unlock(&nvmeq->sq_lock);
 522}
 523
 524static void **nvme_pci_iod_list(struct request *req)
 525{
 526        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 527        return (void **)(iod->sg + blk_rq_nr_phys_segments(req));
 528}
 529
 530static inline bool nvme_pci_use_sgls(struct nvme_dev *dev, struct request *req)
 531{
 532        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 533        int nseg = blk_rq_nr_phys_segments(req);
 534        unsigned int avg_seg_size;
 535
 536        avg_seg_size = DIV_ROUND_UP(blk_rq_payload_bytes(req), nseg);
 537
 538        if (!nvme_ctrl_sgl_supported(&dev->ctrl))
 539                return false;
 540        if (!iod->nvmeq->qid)
 541                return false;
 542        if (!sgl_threshold || avg_seg_size < sgl_threshold)
 543                return false;
 544        return true;
 545}
 546
 547static void nvme_free_prps(struct nvme_dev *dev, struct request *req)
 548{
 549        const int last_prp = NVME_CTRL_PAGE_SIZE / sizeof(__le64) - 1;
 550        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 551        dma_addr_t dma_addr = iod->first_dma;
 552        int i;
 553
 554        for (i = 0; i < iod->npages; i++) {
 555                __le64 *prp_list = nvme_pci_iod_list(req)[i];
 556                dma_addr_t next_dma_addr = le64_to_cpu(prp_list[last_prp]);
 557
 558                dma_pool_free(dev->prp_page_pool, prp_list, dma_addr);
 559                dma_addr = next_dma_addr;
 560        }
 561}
 562
 563static void nvme_free_sgls(struct nvme_dev *dev, struct request *req)
 564{
 565        const int last_sg = SGES_PER_PAGE - 1;
 566        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 567        dma_addr_t dma_addr = iod->first_dma;
 568        int i;
 569
 570        for (i = 0; i < iod->npages; i++) {
 571                struct nvme_sgl_desc *sg_list = nvme_pci_iod_list(req)[i];
 572                dma_addr_t next_dma_addr = le64_to_cpu((sg_list[last_sg]).addr);
 573
 574                dma_pool_free(dev->prp_page_pool, sg_list, dma_addr);
 575                dma_addr = next_dma_addr;
 576        }
 577}
 578
 579static void nvme_unmap_sg(struct nvme_dev *dev, struct request *req)
 580{
 581        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 582
 583        if (is_pci_p2pdma_page(sg_page(iod->sg)))
 584                pci_p2pdma_unmap_sg(dev->dev, iod->sg, iod->nents,
 585                                    rq_dma_dir(req));
 586        else
 587                dma_unmap_sg(dev->dev, iod->sg, iod->nents, rq_dma_dir(req));
 588}
 589
 590static void nvme_unmap_data(struct nvme_dev *dev, struct request *req)
 591{
 592        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 593
 594        if (iod->dma_len) {
 595                dma_unmap_page(dev->dev, iod->first_dma, iod->dma_len,
 596                               rq_dma_dir(req));
 597                return;
 598        }
 599
 600        WARN_ON_ONCE(!iod->nents);
 601
 602        nvme_unmap_sg(dev, req);
 603        if (iod->npages == 0)
 604                dma_pool_free(dev->prp_small_pool, nvme_pci_iod_list(req)[0],
 605                              iod->first_dma);
 606        else if (iod->use_sgl)
 607                nvme_free_sgls(dev, req);
 608        else
 609                nvme_free_prps(dev, req);
 610        mempool_free(iod->sg, dev->iod_mempool);
 611}
 612
 613static void nvme_print_sgl(struct scatterlist *sgl, int nents)
 614{
 615        int i;
 616        struct scatterlist *sg;
 617
 618        for_each_sg(sgl, sg, nents, i) {
 619                dma_addr_t phys = sg_phys(sg);
 620                pr_warn("sg[%d] phys_addr:%pad offset:%d length:%d "
 621                        "dma_address:%pad dma_length:%d\n",
 622                        i, &phys, sg->offset, sg->length, &sg_dma_address(sg),
 623                        sg_dma_len(sg));
 624        }
 625}
 626
 627static blk_status_t nvme_pci_setup_prps(struct nvme_dev *dev,
 628                struct request *req, struct nvme_rw_command *cmnd)
 629{
 630        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 631        struct dma_pool *pool;
 632        int length = blk_rq_payload_bytes(req);
 633        struct scatterlist *sg = iod->sg;
 634        int dma_len = sg_dma_len(sg);
 635        u64 dma_addr = sg_dma_address(sg);
 636        int offset = dma_addr & (NVME_CTRL_PAGE_SIZE - 1);
 637        __le64 *prp_list;
 638        void **list = nvme_pci_iod_list(req);
 639        dma_addr_t prp_dma;
 640        int nprps, i;
 641
 642        length -= (NVME_CTRL_PAGE_SIZE - offset);
 643        if (length <= 0) {
 644                iod->first_dma = 0;
 645                goto done;
 646        }
 647
 648        dma_len -= (NVME_CTRL_PAGE_SIZE - offset);
 649        if (dma_len) {
 650                dma_addr += (NVME_CTRL_PAGE_SIZE - offset);
 651        } else {
 652                sg = sg_next(sg);
 653                dma_addr = sg_dma_address(sg);
 654                dma_len = sg_dma_len(sg);
 655        }
 656
 657        if (length <= NVME_CTRL_PAGE_SIZE) {
 658                iod->first_dma = dma_addr;
 659                goto done;
 660        }
 661
 662        nprps = DIV_ROUND_UP(length, NVME_CTRL_PAGE_SIZE);
 663        if (nprps <= (256 / 8)) {
 664                pool = dev->prp_small_pool;
 665                iod->npages = 0;
 666        } else {
 667                pool = dev->prp_page_pool;
 668                iod->npages = 1;
 669        }
 670
 671        prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 672        if (!prp_list) {
 673                iod->first_dma = dma_addr;
 674                iod->npages = -1;
 675                return BLK_STS_RESOURCE;
 676        }
 677        list[0] = prp_list;
 678        iod->first_dma = prp_dma;
 679        i = 0;
 680        for (;;) {
 681                if (i == NVME_CTRL_PAGE_SIZE >> 3) {
 682                        __le64 *old_prp_list = prp_list;
 683                        prp_list = dma_pool_alloc(pool, GFP_ATOMIC, &prp_dma);
 684                        if (!prp_list)
 685                                goto free_prps;
 686                        list[iod->npages++] = prp_list;
 687                        prp_list[0] = old_prp_list[i - 1];
 688                        old_prp_list[i - 1] = cpu_to_le64(prp_dma);
 689                        i = 1;
 690                }
 691                prp_list[i++] = cpu_to_le64(dma_addr);
 692                dma_len -= NVME_CTRL_PAGE_SIZE;
 693                dma_addr += NVME_CTRL_PAGE_SIZE;
 694                length -= NVME_CTRL_PAGE_SIZE;
 695                if (length <= 0)
 696                        break;
 697                if (dma_len > 0)
 698                        continue;
 699                if (unlikely(dma_len < 0))
 700                        goto bad_sgl;
 701                sg = sg_next(sg);
 702                dma_addr = sg_dma_address(sg);
 703                dma_len = sg_dma_len(sg);
 704        }
 705done:
 706        cmnd->dptr.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
 707        cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma);
 708        return BLK_STS_OK;
 709free_prps:
 710        nvme_free_prps(dev, req);
 711        return BLK_STS_RESOURCE;
 712bad_sgl:
 713        WARN(DO_ONCE(nvme_print_sgl, iod->sg, iod->nents),
 714                        "Invalid SGL for payload:%d nents:%d\n",
 715                        blk_rq_payload_bytes(req), iod->nents);
 716        return BLK_STS_IOERR;
 717}
 718
 719static void nvme_pci_sgl_set_data(struct nvme_sgl_desc *sge,
 720                struct scatterlist *sg)
 721{
 722        sge->addr = cpu_to_le64(sg_dma_address(sg));
 723        sge->length = cpu_to_le32(sg_dma_len(sg));
 724        sge->type = NVME_SGL_FMT_DATA_DESC << 4;
 725}
 726
 727static void nvme_pci_sgl_set_seg(struct nvme_sgl_desc *sge,
 728                dma_addr_t dma_addr, int entries)
 729{
 730        sge->addr = cpu_to_le64(dma_addr);
 731        if (entries < SGES_PER_PAGE) {
 732                sge->length = cpu_to_le32(entries * sizeof(*sge));
 733                sge->type = NVME_SGL_FMT_LAST_SEG_DESC << 4;
 734        } else {
 735                sge->length = cpu_to_le32(PAGE_SIZE);
 736                sge->type = NVME_SGL_FMT_SEG_DESC << 4;
 737        }
 738}
 739
 740static blk_status_t nvme_pci_setup_sgls(struct nvme_dev *dev,
 741                struct request *req, struct nvme_rw_command *cmd, int entries)
 742{
 743        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 744        struct dma_pool *pool;
 745        struct nvme_sgl_desc *sg_list;
 746        struct scatterlist *sg = iod->sg;
 747        dma_addr_t sgl_dma;
 748        int i = 0;
 749
 750        /* setting the transfer type as SGL */
 751        cmd->flags = NVME_CMD_SGL_METABUF;
 752
 753        if (entries == 1) {
 754                nvme_pci_sgl_set_data(&cmd->dptr.sgl, sg);
 755                return BLK_STS_OK;
 756        }
 757
 758        if (entries <= (256 / sizeof(struct nvme_sgl_desc))) {
 759                pool = dev->prp_small_pool;
 760                iod->npages = 0;
 761        } else {
 762                pool = dev->prp_page_pool;
 763                iod->npages = 1;
 764        }
 765
 766        sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 767        if (!sg_list) {
 768                iod->npages = -1;
 769                return BLK_STS_RESOURCE;
 770        }
 771
 772        nvme_pci_iod_list(req)[0] = sg_list;
 773        iod->first_dma = sgl_dma;
 774
 775        nvme_pci_sgl_set_seg(&cmd->dptr.sgl, sgl_dma, entries);
 776
 777        do {
 778                if (i == SGES_PER_PAGE) {
 779                        struct nvme_sgl_desc *old_sg_desc = sg_list;
 780                        struct nvme_sgl_desc *link = &old_sg_desc[i - 1];
 781
 782                        sg_list = dma_pool_alloc(pool, GFP_ATOMIC, &sgl_dma);
 783                        if (!sg_list)
 784                                goto free_sgls;
 785
 786                        i = 0;
 787                        nvme_pci_iod_list(req)[iod->npages++] = sg_list;
 788                        sg_list[i++] = *link;
 789                        nvme_pci_sgl_set_seg(link, sgl_dma, entries);
 790                }
 791
 792                nvme_pci_sgl_set_data(&sg_list[i++], sg);
 793                sg = sg_next(sg);
 794        } while (--entries > 0);
 795
 796        return BLK_STS_OK;
 797free_sgls:
 798        nvme_free_sgls(dev, req);
 799        return BLK_STS_RESOURCE;
 800}
 801
 802static blk_status_t nvme_setup_prp_simple(struct nvme_dev *dev,
 803                struct request *req, struct nvme_rw_command *cmnd,
 804                struct bio_vec *bv)
 805{
 806        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 807        unsigned int offset = bv->bv_offset & (NVME_CTRL_PAGE_SIZE - 1);
 808        unsigned int first_prp_len = NVME_CTRL_PAGE_SIZE - offset;
 809
 810        iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 811        if (dma_mapping_error(dev->dev, iod->first_dma))
 812                return BLK_STS_RESOURCE;
 813        iod->dma_len = bv->bv_len;
 814
 815        cmnd->dptr.prp1 = cpu_to_le64(iod->first_dma);
 816        if (bv->bv_len > first_prp_len)
 817                cmnd->dptr.prp2 = cpu_to_le64(iod->first_dma + first_prp_len);
 818        return BLK_STS_OK;
 819}
 820
 821static blk_status_t nvme_setup_sgl_simple(struct nvme_dev *dev,
 822                struct request *req, struct nvme_rw_command *cmnd,
 823                struct bio_vec *bv)
 824{
 825        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 826
 827        iod->first_dma = dma_map_bvec(dev->dev, bv, rq_dma_dir(req), 0);
 828        if (dma_mapping_error(dev->dev, iod->first_dma))
 829                return BLK_STS_RESOURCE;
 830        iod->dma_len = bv->bv_len;
 831
 832        cmnd->flags = NVME_CMD_SGL_METABUF;
 833        cmnd->dptr.sgl.addr = cpu_to_le64(iod->first_dma);
 834        cmnd->dptr.sgl.length = cpu_to_le32(iod->dma_len);
 835        cmnd->dptr.sgl.type = NVME_SGL_FMT_DATA_DESC << 4;
 836        return BLK_STS_OK;
 837}
 838
 839static blk_status_t nvme_map_data(struct nvme_dev *dev, struct request *req,
 840                struct nvme_command *cmnd)
 841{
 842        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 843        blk_status_t ret = BLK_STS_RESOURCE;
 844        int nr_mapped;
 845
 846        if (blk_rq_nr_phys_segments(req) == 1) {
 847                struct bio_vec bv = req_bvec(req);
 848
 849                if (!is_pci_p2pdma_page(bv.bv_page)) {
 850                        if (bv.bv_offset + bv.bv_len <= NVME_CTRL_PAGE_SIZE * 2)
 851                                return nvme_setup_prp_simple(dev, req,
 852                                                             &cmnd->rw, &bv);
 853
 854                        if (iod->nvmeq->qid && sgl_threshold &&
 855                            nvme_ctrl_sgl_supported(&dev->ctrl))
 856                                return nvme_setup_sgl_simple(dev, req,
 857                                                             &cmnd->rw, &bv);
 858                }
 859        }
 860
 861        iod->dma_len = 0;
 862        iod->sg = mempool_alloc(dev->iod_mempool, GFP_ATOMIC);
 863        if (!iod->sg)
 864                return BLK_STS_RESOURCE;
 865        sg_init_table(iod->sg, blk_rq_nr_phys_segments(req));
 866        iod->nents = blk_rq_map_sg(req->q, req, iod->sg);
 867        if (!iod->nents)
 868                goto out_free_sg;
 869
 870        if (is_pci_p2pdma_page(sg_page(iod->sg)))
 871                nr_mapped = pci_p2pdma_map_sg_attrs(dev->dev, iod->sg,
 872                                iod->nents, rq_dma_dir(req), DMA_ATTR_NO_WARN);
 873        else
 874                nr_mapped = dma_map_sg_attrs(dev->dev, iod->sg, iod->nents,
 875                                             rq_dma_dir(req), DMA_ATTR_NO_WARN);
 876        if (!nr_mapped)
 877                goto out_free_sg;
 878
 879        iod->use_sgl = nvme_pci_use_sgls(dev, req);
 880        if (iod->use_sgl)
 881                ret = nvme_pci_setup_sgls(dev, req, &cmnd->rw, nr_mapped);
 882        else
 883                ret = nvme_pci_setup_prps(dev, req, &cmnd->rw);
 884        if (ret != BLK_STS_OK)
 885                goto out_unmap_sg;
 886        return BLK_STS_OK;
 887
 888out_unmap_sg:
 889        nvme_unmap_sg(dev, req);
 890out_free_sg:
 891        mempool_free(iod->sg, dev->iod_mempool);
 892        return ret;
 893}
 894
 895static blk_status_t nvme_map_metadata(struct nvme_dev *dev, struct request *req,
 896                struct nvme_command *cmnd)
 897{
 898        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 899
 900        iod->meta_dma = dma_map_bvec(dev->dev, rq_integrity_vec(req),
 901                        rq_dma_dir(req), 0);
 902        if (dma_mapping_error(dev->dev, iod->meta_dma))
 903                return BLK_STS_IOERR;
 904        cmnd->rw.metadata = cpu_to_le64(iod->meta_dma);
 905        return BLK_STS_OK;
 906}
 907
 908/*
 909 * NOTE: ns is NULL when called on the admin queue.
 910 */
 911static blk_status_t nvme_queue_rq(struct blk_mq_hw_ctx *hctx,
 912                         const struct blk_mq_queue_data *bd)
 913{
 914        struct nvme_ns *ns = hctx->queue->queuedata;
 915        struct nvme_queue *nvmeq = hctx->driver_data;
 916        struct nvme_dev *dev = nvmeq->dev;
 917        struct request *req = bd->rq;
 918        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 919        struct nvme_command *cmnd = &iod->cmd;
 920        blk_status_t ret;
 921
 922        iod->aborted = 0;
 923        iod->npages = -1;
 924        iod->nents = 0;
 925
 926        /*
 927         * We should not need to do this, but we're still using this to
 928         * ensure we can drain requests on a dying queue.
 929         */
 930        if (unlikely(!test_bit(NVMEQ_ENABLED, &nvmeq->flags)))
 931                return BLK_STS_IOERR;
 932
 933        if (!nvme_check_ready(&dev->ctrl, req, true))
 934                return nvme_fail_nonready_command(&dev->ctrl, req);
 935
 936        ret = nvme_setup_cmd(ns, req);
 937        if (ret)
 938                return ret;
 939
 940        if (blk_rq_nr_phys_segments(req)) {
 941                ret = nvme_map_data(dev, req, cmnd);
 942                if (ret)
 943                        goto out_free_cmd;
 944        }
 945
 946        if (blk_integrity_rq(req)) {
 947                ret = nvme_map_metadata(dev, req, cmnd);
 948                if (ret)
 949                        goto out_unmap_data;
 950        }
 951
 952        blk_mq_start_request(req);
 953        nvme_submit_cmd(nvmeq, cmnd, bd->last);
 954        return BLK_STS_OK;
 955out_unmap_data:
 956        nvme_unmap_data(dev, req);
 957out_free_cmd:
 958        nvme_cleanup_cmd(req);
 959        return ret;
 960}
 961
 962static void nvme_pci_complete_rq(struct request *req)
 963{
 964        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
 965        struct nvme_dev *dev = iod->nvmeq->dev;
 966
 967        if (blk_integrity_rq(req))
 968                dma_unmap_page(dev->dev, iod->meta_dma,
 969                               rq_integrity_vec(req)->bv_len, rq_data_dir(req));
 970        if (blk_rq_nr_phys_segments(req))
 971                nvme_unmap_data(dev, req);
 972        nvme_complete_rq(req);
 973}
 974
 975/* We read the CQE phase first to check if the rest of the entry is valid */
 976static inline bool nvme_cqe_pending(struct nvme_queue *nvmeq)
 977{
 978        struct nvme_completion *hcqe = &nvmeq->cqes[nvmeq->cq_head];
 979
 980        return (le16_to_cpu(READ_ONCE(hcqe->status)) & 1) == nvmeq->cq_phase;
 981}
 982
 983static inline void nvme_ring_cq_doorbell(struct nvme_queue *nvmeq)
 984{
 985        u16 head = nvmeq->cq_head;
 986
 987        if (nvme_dbbuf_update_and_check_event(head, nvmeq->dbbuf_cq_db,
 988                                              nvmeq->dbbuf_cq_ei))
 989                writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
 990}
 991
 992static inline struct blk_mq_tags *nvme_queue_tagset(struct nvme_queue *nvmeq)
 993{
 994        if (!nvmeq->qid)
 995                return nvmeq->dev->admin_tagset.tags[0];
 996        return nvmeq->dev->tagset.tags[nvmeq->qid - 1];
 997}
 998
 999static inline void nvme_handle_cqe(struct nvme_queue *nvmeq, u16 idx)
1000{
1001        struct nvme_completion *cqe = &nvmeq->cqes[idx];
1002        __u16 command_id = READ_ONCE(cqe->command_id);
1003        struct request *req;
1004
1005        /*
1006         * AEN requests are special as they don't time out and can
1007         * survive any kind of queue freeze and often don't respond to
1008         * aborts.  We don't even bother to allocate a struct request
1009         * for them but rather special case them here.
1010         */
1011        if (unlikely(nvme_is_aen_req(nvmeq->qid, command_id))) {
1012                nvme_complete_async_event(&nvmeq->dev->ctrl,
1013                                cqe->status, &cqe->result);
1014                return;
1015        }
1016
1017        req = blk_mq_tag_to_rq(nvme_queue_tagset(nvmeq), command_id);
1018        if (unlikely(!req)) {
1019                dev_warn(nvmeq->dev->ctrl.device,
1020                        "invalid id %d completed on queue %d\n",
1021                        command_id, le16_to_cpu(cqe->sq_id));
1022                return;
1023        }
1024
1025        trace_nvme_sq(req, cqe->sq_head, nvmeq->sq_tail);
1026        if (!nvme_try_complete_req(req, cqe->status, cqe->result))
1027                nvme_pci_complete_rq(req);
1028}
1029
1030static inline void nvme_update_cq_head(struct nvme_queue *nvmeq)
1031{
1032        u32 tmp = nvmeq->cq_head + 1;
1033
1034        if (tmp == nvmeq->q_depth) {
1035                nvmeq->cq_head = 0;
1036                nvmeq->cq_phase ^= 1;
1037        } else {
1038                nvmeq->cq_head = tmp;
1039        }
1040}
1041
1042static inline int nvme_process_cq(struct nvme_queue *nvmeq)
1043{
1044        int found = 0;
1045
1046        while (nvme_cqe_pending(nvmeq)) {
1047                found++;
1048                /*
1049                 * load-load control dependency between phase and the rest of
1050                 * the cqe requires a full read memory barrier
1051                 */
1052                dma_rmb();
1053                nvme_handle_cqe(nvmeq, nvmeq->cq_head);
1054                nvme_update_cq_head(nvmeq);
1055        }
1056
1057        if (found)
1058                nvme_ring_cq_doorbell(nvmeq);
1059        return found;
1060}
1061
1062static irqreturn_t nvme_irq(int irq, void *data)
1063{
1064        struct nvme_queue *nvmeq = data;
1065
1066        if (nvme_process_cq(nvmeq))
1067                return IRQ_HANDLED;
1068        return IRQ_NONE;
1069}
1070
1071static irqreturn_t nvme_irq_check(int irq, void *data)
1072{
1073        struct nvme_queue *nvmeq = data;
1074
1075        if (nvme_cqe_pending(nvmeq))
1076                return IRQ_WAKE_THREAD;
1077        return IRQ_NONE;
1078}
1079
1080/*
1081 * Poll for completions for any interrupt driven queue
1082 * Can be called from any context.
1083 */
1084static void nvme_poll_irqdisable(struct nvme_queue *nvmeq)
1085{
1086        struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1087
1088        WARN_ON_ONCE(test_bit(NVMEQ_POLLED, &nvmeq->flags));
1089
1090        disable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1091        nvme_process_cq(nvmeq);
1092        enable_irq(pci_irq_vector(pdev, nvmeq->cq_vector));
1093}
1094
1095static int nvme_poll(struct blk_mq_hw_ctx *hctx)
1096{
1097        struct nvme_queue *nvmeq = hctx->driver_data;
1098        bool found;
1099
1100        if (!nvme_cqe_pending(nvmeq))
1101                return 0;
1102
1103        spin_lock(&nvmeq->cq_poll_lock);
1104        found = nvme_process_cq(nvmeq);
1105        spin_unlock(&nvmeq->cq_poll_lock);
1106
1107        return found;
1108}
1109
1110static void nvme_pci_submit_async_event(struct nvme_ctrl *ctrl)
1111{
1112        struct nvme_dev *dev = to_nvme_dev(ctrl);
1113        struct nvme_queue *nvmeq = &dev->queues[0];
1114        struct nvme_command c = { };
1115
1116        c.common.opcode = nvme_admin_async_event;
1117        c.common.command_id = NVME_AQ_BLK_MQ_DEPTH;
1118        nvme_submit_cmd(nvmeq, &c, true);
1119}
1120
1121static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
1122{
1123        struct nvme_command c = { };
1124
1125        c.delete_queue.opcode = opcode;
1126        c.delete_queue.qid = cpu_to_le16(id);
1127
1128        return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1129}
1130
1131static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1132                struct nvme_queue *nvmeq, s16 vector)
1133{
1134        struct nvme_command c = { };
1135        int flags = NVME_QUEUE_PHYS_CONTIG;
1136
1137        if (!test_bit(NVMEQ_POLLED, &nvmeq->flags))
1138                flags |= NVME_CQ_IRQ_ENABLED;
1139
1140        /*
1141         * Note: we (ab)use the fact that the prp fields survive if no data
1142         * is attached to the request.
1143         */
1144        c.create_cq.opcode = nvme_admin_create_cq;
1145        c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1146        c.create_cq.cqid = cpu_to_le16(qid);
1147        c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1148        c.create_cq.cq_flags = cpu_to_le16(flags);
1149        c.create_cq.irq_vector = cpu_to_le16(vector);
1150
1151        return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1152}
1153
1154static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1155                                                struct nvme_queue *nvmeq)
1156{
1157        struct nvme_ctrl *ctrl = &dev->ctrl;
1158        struct nvme_command c = { };
1159        int flags = NVME_QUEUE_PHYS_CONTIG;
1160
1161        /*
1162         * Some drives have a bug that auto-enables WRRU if MEDIUM isn't
1163         * set. Since URGENT priority is zeroes, it makes all queues
1164         * URGENT.
1165         */
1166        if (ctrl->quirks & NVME_QUIRK_MEDIUM_PRIO_SQ)
1167                flags |= NVME_SQ_PRIO_MEDIUM;
1168
1169        /*
1170         * Note: we (ab)use the fact that the prp fields survive if no data
1171         * is attached to the request.
1172         */
1173        c.create_sq.opcode = nvme_admin_create_sq;
1174        c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1175        c.create_sq.sqid = cpu_to_le16(qid);
1176        c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1177        c.create_sq.sq_flags = cpu_to_le16(flags);
1178        c.create_sq.cqid = cpu_to_le16(qid);
1179
1180        return nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1181}
1182
1183static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1184{
1185        return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1186}
1187
1188static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1189{
1190        return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1191}
1192
1193static void abort_endio(struct request *req, blk_status_t error)
1194{
1195        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1196        struct nvme_queue *nvmeq = iod->nvmeq;
1197
1198        dev_warn(nvmeq->dev->ctrl.device,
1199                 "Abort status: 0x%x", nvme_req(req)->status);
1200        atomic_inc(&nvmeq->dev->ctrl.abort_limit);
1201        blk_mq_free_request(req);
1202}
1203
1204static bool nvme_should_reset(struct nvme_dev *dev, u32 csts)
1205{
1206        /* If true, indicates loss of adapter communication, possibly by a
1207         * NVMe Subsystem reset.
1208         */
1209        bool nssro = dev->subsystem && (csts & NVME_CSTS_NSSRO);
1210
1211        /* If there is a reset/reinit ongoing, we shouldn't reset again. */
1212        switch (dev->ctrl.state) {
1213        case NVME_CTRL_RESETTING:
1214        case NVME_CTRL_CONNECTING:
1215                return false;
1216        default:
1217                break;
1218        }
1219
1220        /* We shouldn't reset unless the controller is on fatal error state
1221         * _or_ if we lost the communication with it.
1222         */
1223        if (!(csts & NVME_CSTS_CFS) && !nssro)
1224                return false;
1225
1226        return true;
1227}
1228
1229static void nvme_warn_reset(struct nvme_dev *dev, u32 csts)
1230{
1231        /* Read a config register to help see what died. */
1232        u16 pci_status;
1233        int result;
1234
1235        result = pci_read_config_word(to_pci_dev(dev->dev), PCI_STATUS,
1236                                      &pci_status);
1237        if (result == PCIBIOS_SUCCESSFUL)
1238                dev_warn(dev->ctrl.device,
1239                         "controller is down; will reset: CSTS=0x%x, PCI_STATUS=0x%hx\n",
1240                         csts, pci_status);
1241        else
1242                dev_warn(dev->ctrl.device,
1243                         "controller is down; will reset: CSTS=0x%x, PCI_STATUS read failed (%d)\n",
1244                         csts, result);
1245}
1246
1247static enum blk_eh_timer_return nvme_timeout(struct request *req, bool reserved)
1248{
1249        struct nvme_iod *iod = blk_mq_rq_to_pdu(req);
1250        struct nvme_queue *nvmeq = iod->nvmeq;
1251        struct nvme_dev *dev = nvmeq->dev;
1252        struct request *abort_req;
1253        struct nvme_command cmd = { };
1254        u32 csts = readl(dev->bar + NVME_REG_CSTS);
1255
1256        /* If PCI error recovery process is happening, we cannot reset or
1257         * the recovery mechanism will surely fail.
1258         */
1259        mb();
1260        if (pci_channel_offline(to_pci_dev(dev->dev)))
1261                return BLK_EH_RESET_TIMER;
1262
1263        /*
1264         * Reset immediately if the controller is failed
1265         */
1266        if (nvme_should_reset(dev, csts)) {
1267                nvme_warn_reset(dev, csts);
1268                nvme_dev_disable(dev, false);
1269                nvme_reset_ctrl(&dev->ctrl);
1270                return BLK_EH_DONE;
1271        }
1272
1273        /*
1274         * Did we miss an interrupt?
1275         */
1276        if (test_bit(NVMEQ_POLLED, &nvmeq->flags))
1277                nvme_poll(req->mq_hctx);
1278        else
1279                nvme_poll_irqdisable(nvmeq);
1280
1281        if (blk_mq_request_completed(req)) {
1282                dev_warn(dev->ctrl.device,
1283                         "I/O %d QID %d timeout, completion polled\n",
1284                         req->tag, nvmeq->qid);
1285                return BLK_EH_DONE;
1286        }
1287
1288        /*
1289         * Shutdown immediately if controller times out while starting. The
1290         * reset work will see the pci device disabled when it gets the forced
1291         * cancellation error. All outstanding requests are completed on
1292         * shutdown, so we return BLK_EH_DONE.
1293         */
1294        switch (dev->ctrl.state) {
1295        case NVME_CTRL_CONNECTING:
1296                nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
1297                fallthrough;
1298        case NVME_CTRL_DELETING:
1299                dev_warn_ratelimited(dev->ctrl.device,
1300                         "I/O %d QID %d timeout, disable controller\n",
1301                         req->tag, nvmeq->qid);
1302                nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1303                nvme_dev_disable(dev, true);
1304                return BLK_EH_DONE;
1305        case NVME_CTRL_RESETTING:
1306                return BLK_EH_RESET_TIMER;
1307        default:
1308                break;
1309        }
1310
1311        /*
1312         * Shutdown the controller immediately and schedule a reset if the
1313         * command was already aborted once before and still hasn't been
1314         * returned to the driver, or if this is the admin queue.
1315         */
1316        if (!nvmeq->qid || iod->aborted) {
1317                dev_warn(dev->ctrl.device,
1318                         "I/O %d QID %d timeout, reset controller\n",
1319                         req->tag, nvmeq->qid);
1320                nvme_req(req)->flags |= NVME_REQ_CANCELLED;
1321                nvme_dev_disable(dev, false);
1322                nvme_reset_ctrl(&dev->ctrl);
1323
1324                return BLK_EH_DONE;
1325        }
1326
1327        if (atomic_dec_return(&dev->ctrl.abort_limit) < 0) {
1328                atomic_inc(&dev->ctrl.abort_limit);
1329                return BLK_EH_RESET_TIMER;
1330        }
1331        iod->aborted = 1;
1332
1333        cmd.abort.opcode = nvme_admin_abort_cmd;
1334        cmd.abort.cid = req->tag;
1335        cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1336
1337        dev_warn(nvmeq->dev->ctrl.device,
1338                "I/O %d QID %d timeout, aborting\n",
1339                 req->tag, nvmeq->qid);
1340
1341        abort_req = nvme_alloc_request(dev->ctrl.admin_q, &cmd,
1342                        BLK_MQ_REQ_NOWAIT);
1343        if (IS_ERR(abort_req)) {
1344                atomic_inc(&dev->ctrl.abort_limit);
1345                return BLK_EH_RESET_TIMER;
1346        }
1347
1348        abort_req->end_io_data = NULL;
1349        blk_execute_rq_nowait(NULL, abort_req, 0, abort_endio);
1350
1351        /*
1352         * The aborted req will be completed on receiving the abort req.
1353         * We enable the timer again. If hit twice, it'll cause a device reset,
1354         * as the device then is in a faulty state.
1355         */
1356        return BLK_EH_RESET_TIMER;
1357}
1358
1359static void nvme_free_queue(struct nvme_queue *nvmeq)
1360{
1361        dma_free_coherent(nvmeq->dev->dev, CQ_SIZE(nvmeq),
1362                                (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1363        if (!nvmeq->sq_cmds)
1364                return;
1365
1366        if (test_and_clear_bit(NVMEQ_SQ_CMB, &nvmeq->flags)) {
1367                pci_free_p2pmem(to_pci_dev(nvmeq->dev->dev),
1368                                nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1369        } else {
1370                dma_free_coherent(nvmeq->dev->dev, SQ_SIZE(nvmeq),
1371                                nvmeq->sq_cmds, nvmeq->sq_dma_addr);
1372        }
1373}
1374
1375static void nvme_free_queues(struct nvme_dev *dev, int lowest)
1376{
1377        int i;
1378
1379        for (i = dev->ctrl.queue_count - 1; i >= lowest; i--) {
1380                dev->ctrl.queue_count--;
1381                nvme_free_queue(&dev->queues[i]);
1382        }
1383}
1384
1385/**
1386 * nvme_suspend_queue - put queue into suspended state
1387 * @nvmeq: queue to suspend
1388 */
1389static int nvme_suspend_queue(struct nvme_queue *nvmeq)
1390{
1391        if (!test_and_clear_bit(NVMEQ_ENABLED, &nvmeq->flags))
1392                return 1;
1393
1394        /* ensure that nvme_queue_rq() sees NVMEQ_ENABLED cleared */
1395        mb();
1396
1397        nvmeq->dev->online_queues--;
1398        if (!nvmeq->qid && nvmeq->dev->ctrl.admin_q)
1399                blk_mq_quiesce_queue(nvmeq->dev->ctrl.admin_q);
1400        if (!test_and_clear_bit(NVMEQ_POLLED, &nvmeq->flags))
1401                pci_free_irq(to_pci_dev(nvmeq->dev->dev), nvmeq->cq_vector, nvmeq);
1402        return 0;
1403}
1404
1405static void nvme_suspend_io_queues(struct nvme_dev *dev)
1406{
1407        int i;
1408
1409        for (i = dev->ctrl.queue_count - 1; i > 0; i--)
1410                nvme_suspend_queue(&dev->queues[i]);
1411}
1412
1413static void nvme_disable_admin_queue(struct nvme_dev *dev, bool shutdown)
1414{
1415        struct nvme_queue *nvmeq = &dev->queues[0];
1416
1417        if (shutdown)
1418                nvme_shutdown_ctrl(&dev->ctrl);
1419        else
1420                nvme_disable_ctrl(&dev->ctrl);
1421
1422        nvme_poll_irqdisable(nvmeq);
1423}
1424
1425/*
1426 * Called only on a device that has been disabled and after all other threads
1427 * that can check this device's completion queues have synced, except
1428 * nvme_poll(). This is the last chance for the driver to see a natural
1429 * completion before nvme_cancel_request() terminates all incomplete requests.
1430 */
1431static void nvme_reap_pending_cqes(struct nvme_dev *dev)
1432{
1433        int i;
1434
1435        for (i = dev->ctrl.queue_count - 1; i > 0; i--) {
1436                spin_lock(&dev->queues[i].cq_poll_lock);
1437                nvme_process_cq(&dev->queues[i]);
1438                spin_unlock(&dev->queues[i].cq_poll_lock);
1439        }
1440}
1441
1442static int nvme_cmb_qdepth(struct nvme_dev *dev, int nr_io_queues,
1443                                int entry_size)
1444{
1445        int q_depth = dev->q_depth;
1446        unsigned q_size_aligned = roundup(q_depth * entry_size,
1447                                          NVME_CTRL_PAGE_SIZE);
1448
1449        if (q_size_aligned * nr_io_queues > dev->cmb_size) {
1450                u64 mem_per_q = div_u64(dev->cmb_size, nr_io_queues);
1451
1452                mem_per_q = round_down(mem_per_q, NVME_CTRL_PAGE_SIZE);
1453                q_depth = div_u64(mem_per_q, entry_size);
1454
1455                /*
1456                 * Ensure the reduced q_depth is above some threshold where it
1457                 * would be better to map queues in system memory with the
1458                 * original depth
1459                 */
1460                if (q_depth < 64)
1461                        return -ENOMEM;
1462        }
1463
1464        return q_depth;
1465}
1466
1467static int nvme_alloc_sq_cmds(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1468                                int qid)
1469{
1470        struct pci_dev *pdev = to_pci_dev(dev->dev);
1471
1472        if (qid && dev->cmb_use_sqes && (dev->cmbsz & NVME_CMBSZ_SQS)) {
1473                nvmeq->sq_cmds = pci_alloc_p2pmem(pdev, SQ_SIZE(nvmeq));
1474                if (nvmeq->sq_cmds) {
1475                        nvmeq->sq_dma_addr = pci_p2pmem_virt_to_bus(pdev,
1476                                                        nvmeq->sq_cmds);
1477                        if (nvmeq->sq_dma_addr) {
1478                                set_bit(NVMEQ_SQ_CMB, &nvmeq->flags);
1479                                return 0;
1480                        }
1481
1482                        pci_free_p2pmem(pdev, nvmeq->sq_cmds, SQ_SIZE(nvmeq));
1483                }
1484        }
1485
1486        nvmeq->sq_cmds = dma_alloc_coherent(dev->dev, SQ_SIZE(nvmeq),
1487                                &nvmeq->sq_dma_addr, GFP_KERNEL);
1488        if (!nvmeq->sq_cmds)
1489                return -ENOMEM;
1490        return 0;
1491}
1492
1493static int nvme_alloc_queue(struct nvme_dev *dev, int qid, int depth)
1494{
1495        struct nvme_queue *nvmeq = &dev->queues[qid];
1496
1497        if (dev->ctrl.queue_count > qid)
1498                return 0;
1499
1500        nvmeq->sqes = qid ? dev->io_sqes : NVME_ADM_SQES;
1501        nvmeq->q_depth = depth;
1502        nvmeq->cqes = dma_alloc_coherent(dev->dev, CQ_SIZE(nvmeq),
1503                                         &nvmeq->cq_dma_addr, GFP_KERNEL);
1504        if (!nvmeq->cqes)
1505                goto free_nvmeq;
1506
1507        if (nvme_alloc_sq_cmds(dev, nvmeq, qid))
1508                goto free_cqdma;
1509
1510        nvmeq->dev = dev;
1511        spin_lock_init(&nvmeq->sq_lock);
1512        spin_lock_init(&nvmeq->cq_poll_lock);
1513        nvmeq->cq_head = 0;
1514        nvmeq->cq_phase = 1;
1515        nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1516        nvmeq->qid = qid;
1517        dev->ctrl.queue_count++;
1518
1519        return 0;
1520
1521 free_cqdma:
1522        dma_free_coherent(dev->dev, CQ_SIZE(nvmeq), (void *)nvmeq->cqes,
1523                          nvmeq->cq_dma_addr);
1524 free_nvmeq:
1525        return -ENOMEM;
1526}
1527
1528static int queue_request_irq(struct nvme_queue *nvmeq)
1529{
1530        struct pci_dev *pdev = to_pci_dev(nvmeq->dev->dev);
1531        int nr = nvmeq->dev->ctrl.instance;
1532
1533        if (use_threaded_interrupts) {
1534                return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq_check,
1535                                nvme_irq, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1536        } else {
1537                return pci_request_irq(pdev, nvmeq->cq_vector, nvme_irq,
1538                                NULL, nvmeq, "nvme%dq%d", nr, nvmeq->qid);
1539        }
1540}
1541
1542static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
1543{
1544        struct nvme_dev *dev = nvmeq->dev;
1545
1546        nvmeq->sq_tail = 0;
1547        nvmeq->last_sq_tail = 0;
1548        nvmeq->cq_head = 0;
1549        nvmeq->cq_phase = 1;
1550        nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
1551        memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq));
1552        nvme_dbbuf_init(dev, nvmeq, qid);
1553        dev->online_queues++;
1554        wmb(); /* ensure the first interrupt sees the initialization */
1555}
1556
1557/*
1558 * Try getting shutdown_lock while setting up IO queues.
1559 */
1560static int nvme_setup_io_queues_trylock(struct nvme_dev *dev)
1561{
1562        /*
1563         * Give up if the lock is being held by nvme_dev_disable.
1564         */
1565        if (!mutex_trylock(&dev->shutdown_lock))
1566                return -ENODEV;
1567
1568        /*
1569         * Controller is in wrong state, fail early.
1570         */
1571        if (dev->ctrl.state != NVME_CTRL_CONNECTING) {
1572                mutex_unlock(&dev->shutdown_lock);
1573                return -ENODEV;
1574        }
1575
1576        return 0;
1577}
1578
1579static int nvme_create_queue(struct nvme_queue *nvmeq, int qid, bool polled)
1580{
1581        struct nvme_dev *dev = nvmeq->dev;
1582        int result;
1583        u16 vector = 0;
1584
1585        clear_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
1586
1587        /*
1588         * A queue's vector matches the queue identifier unless the controller
1589         * has only one vector available.
1590         */
1591        if (!polled)
1592                vector = dev->num_vecs == 1 ? 0 : qid;
1593        else
1594                set_bit(NVMEQ_POLLED, &nvmeq->flags);
1595
1596        result = adapter_alloc_cq(dev, qid, nvmeq, vector);
1597        if (result)
1598                return result;
1599
1600        result = adapter_alloc_sq(dev, qid, nvmeq);
1601        if (result < 0)
1602                return result;
1603        if (result)
1604                goto release_cq;
1605
1606        nvmeq->cq_vector = vector;
1607
1608        result = nvme_setup_io_queues_trylock(dev);
1609        if (result)
1610                return result;
1611        nvme_init_queue(nvmeq, qid);
1612        if (!polled) {
1613                result = queue_request_irq(nvmeq);
1614                if (result < 0)
1615                        goto release_sq;
1616        }
1617
1618        set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1619        mutex_unlock(&dev->shutdown_lock);
1620        return result;
1621
1622release_sq:
1623        dev->online_queues--;
1624        mutex_unlock(&dev->shutdown_lock);
1625        adapter_delete_sq(dev, qid);
1626release_cq:
1627        adapter_delete_cq(dev, qid);
1628        return result;
1629}
1630
1631static const struct blk_mq_ops nvme_mq_admin_ops = {
1632        .queue_rq       = nvme_queue_rq,
1633        .complete       = nvme_pci_complete_rq,
1634        .init_hctx      = nvme_admin_init_hctx,
1635        .init_request   = nvme_init_request,
1636        .timeout        = nvme_timeout,
1637};
1638
1639static const struct blk_mq_ops nvme_mq_ops = {
1640        .queue_rq       = nvme_queue_rq,
1641        .complete       = nvme_pci_complete_rq,
1642        .commit_rqs     = nvme_commit_rqs,
1643        .init_hctx      = nvme_init_hctx,
1644        .init_request   = nvme_init_request,
1645        .map_queues     = nvme_pci_map_queues,
1646        .timeout        = nvme_timeout,
1647        .poll           = nvme_poll,
1648};
1649
1650static void nvme_dev_remove_admin(struct nvme_dev *dev)
1651{
1652        if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q)) {
1653                /*
1654                 * If the controller was reset during removal, it's possible
1655                 * user requests may be waiting on a stopped queue. Start the
1656                 * queue to flush these to completion.
1657                 */
1658                blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1659                blk_cleanup_queue(dev->ctrl.admin_q);
1660                blk_mq_free_tag_set(&dev->admin_tagset);
1661        }
1662}
1663
1664static int nvme_alloc_admin_tags(struct nvme_dev *dev)
1665{
1666        if (!dev->ctrl.admin_q) {
1667                dev->admin_tagset.ops = &nvme_mq_admin_ops;
1668                dev->admin_tagset.nr_hw_queues = 1;
1669
1670                dev->admin_tagset.queue_depth = NVME_AQ_MQ_TAG_DEPTH;
1671                dev->admin_tagset.timeout = NVME_ADMIN_TIMEOUT;
1672                dev->admin_tagset.numa_node = dev->ctrl.numa_node;
1673                dev->admin_tagset.cmd_size = sizeof(struct nvme_iod);
1674                dev->admin_tagset.flags = BLK_MQ_F_NO_SCHED;
1675                dev->admin_tagset.driver_data = dev;
1676
1677                if (blk_mq_alloc_tag_set(&dev->admin_tagset))
1678                        return -ENOMEM;
1679                dev->ctrl.admin_tagset = &dev->admin_tagset;
1680
1681                dev->ctrl.admin_q = blk_mq_init_queue(&dev->admin_tagset);
1682                if (IS_ERR(dev->ctrl.admin_q)) {
1683                        blk_mq_free_tag_set(&dev->admin_tagset);
1684                        return -ENOMEM;
1685                }
1686                if (!blk_get_queue(dev->ctrl.admin_q)) {
1687                        nvme_dev_remove_admin(dev);
1688                        dev->ctrl.admin_q = NULL;
1689                        return -ENODEV;
1690                }
1691        } else
1692                blk_mq_unquiesce_queue(dev->ctrl.admin_q);
1693
1694        return 0;
1695}
1696
1697static unsigned long db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
1698{
1699        return NVME_REG_DBS + ((nr_io_queues + 1) * 8 * dev->db_stride);
1700}
1701
1702static int nvme_remap_bar(struct nvme_dev *dev, unsigned long size)
1703{
1704        struct pci_dev *pdev = to_pci_dev(dev->dev);
1705
1706        if (size <= dev->bar_mapped_size)
1707                return 0;
1708        if (size > pci_resource_len(pdev, 0))
1709                return -ENOMEM;
1710        if (dev->bar)
1711                iounmap(dev->bar);
1712        dev->bar = ioremap(pci_resource_start(pdev, 0), size);
1713        if (!dev->bar) {
1714                dev->bar_mapped_size = 0;
1715                return -ENOMEM;
1716        }
1717        dev->bar_mapped_size = size;
1718        dev->dbs = dev->bar + NVME_REG_DBS;
1719
1720        return 0;
1721}
1722
1723static int nvme_pci_configure_admin_queue(struct nvme_dev *dev)
1724{
1725        int result;
1726        u32 aqa;
1727        struct nvme_queue *nvmeq;
1728
1729        result = nvme_remap_bar(dev, db_bar_size(dev, 0));
1730        if (result < 0)
1731                return result;
1732
1733        dev->subsystem = readl(dev->bar + NVME_REG_VS) >= NVME_VS(1, 1, 0) ?
1734                                NVME_CAP_NSSRC(dev->ctrl.cap) : 0;
1735
1736        if (dev->subsystem &&
1737            (readl(dev->bar + NVME_REG_CSTS) & NVME_CSTS_NSSRO))
1738                writel(NVME_CSTS_NSSRO, dev->bar + NVME_REG_CSTS);
1739
1740        result = nvme_disable_ctrl(&dev->ctrl);
1741        if (result < 0)
1742                return result;
1743
1744        result = nvme_alloc_queue(dev, 0, NVME_AQ_DEPTH);
1745        if (result)
1746                return result;
1747
1748        dev->ctrl.numa_node = dev_to_node(dev->dev);
1749
1750        nvmeq = &dev->queues[0];
1751        aqa = nvmeq->q_depth - 1;
1752        aqa |= aqa << 16;
1753
1754        writel(aqa, dev->bar + NVME_REG_AQA);
1755        lo_hi_writeq(nvmeq->sq_dma_addr, dev->bar + NVME_REG_ASQ);
1756        lo_hi_writeq(nvmeq->cq_dma_addr, dev->bar + NVME_REG_ACQ);
1757
1758        result = nvme_enable_ctrl(&dev->ctrl);
1759        if (result)
1760                return result;
1761
1762        nvmeq->cq_vector = 0;
1763        nvme_init_queue(nvmeq, 0);
1764        result = queue_request_irq(nvmeq);
1765        if (result) {
1766                dev->online_queues--;
1767                return result;
1768        }
1769
1770        set_bit(NVMEQ_ENABLED, &nvmeq->flags);
1771        return result;
1772}
1773
1774static int nvme_create_io_queues(struct nvme_dev *dev)
1775{
1776        unsigned i, max, rw_queues;
1777        int ret = 0;
1778
1779        for (i = dev->ctrl.queue_count; i <= dev->max_qid; i++) {
1780                if (nvme_alloc_queue(dev, i, dev->q_depth)) {
1781                        ret = -ENOMEM;
1782                        break;
1783                }
1784        }
1785
1786        max = min(dev->max_qid, dev->ctrl.queue_count - 1);
1787        if (max != 1 && dev->io_queues[HCTX_TYPE_POLL]) {
1788                rw_queues = dev->io_queues[HCTX_TYPE_DEFAULT] +
1789                                dev->io_queues[HCTX_TYPE_READ];
1790        } else {
1791                rw_queues = max;
1792        }
1793
1794        for (i = dev->online_queues; i <= max; i++) {
1795                bool polled = i > rw_queues;
1796
1797                ret = nvme_create_queue(&dev->queues[i], i, polled);
1798                if (ret)
1799                        break;
1800        }
1801
1802        /*
1803         * Ignore failing Create SQ/CQ commands, we can continue with less
1804         * than the desired amount of queues, and even a controller without
1805         * I/O queues can still be used to issue admin commands.  This might
1806         * be useful to upgrade a buggy firmware for example.
1807         */
1808        return ret >= 0 ? 0 : ret;
1809}
1810
1811static ssize_t nvme_cmb_show(struct device *dev,
1812                             struct device_attribute *attr,
1813                             char *buf)
1814{
1815        struct nvme_dev *ndev = to_nvme_dev(dev_get_drvdata(dev));
1816
1817        return scnprintf(buf, PAGE_SIZE, "cmbloc : x%08x\ncmbsz  : x%08x\n",
1818                       ndev->cmbloc, ndev->cmbsz);
1819}
1820static DEVICE_ATTR(cmb, S_IRUGO, nvme_cmb_show, NULL);
1821
1822static u64 nvme_cmb_size_unit(struct nvme_dev *dev)
1823{
1824        u8 szu = (dev->cmbsz >> NVME_CMBSZ_SZU_SHIFT) & NVME_CMBSZ_SZU_MASK;
1825
1826        return 1ULL << (12 + 4 * szu);
1827}
1828
1829static u32 nvme_cmb_size(struct nvme_dev *dev)
1830{
1831        return (dev->cmbsz >> NVME_CMBSZ_SZ_SHIFT) & NVME_CMBSZ_SZ_MASK;
1832}
1833
1834static void nvme_map_cmb(struct nvme_dev *dev)
1835{
1836        u64 size, offset;
1837        resource_size_t bar_size;
1838        struct pci_dev *pdev = to_pci_dev(dev->dev);
1839        int bar;
1840
1841        if (dev->cmb_size)
1842                return;
1843
1844        if (NVME_CAP_CMBS(dev->ctrl.cap))
1845                writel(NVME_CMBMSC_CRE, dev->bar + NVME_REG_CMBMSC);
1846
1847        dev->cmbsz = readl(dev->bar + NVME_REG_CMBSZ);
1848        if (!dev->cmbsz)
1849                return;
1850        dev->cmbloc = readl(dev->bar + NVME_REG_CMBLOC);
1851
1852        size = nvme_cmb_size_unit(dev) * nvme_cmb_size(dev);
1853        offset = nvme_cmb_size_unit(dev) * NVME_CMB_OFST(dev->cmbloc);
1854        bar = NVME_CMB_BIR(dev->cmbloc);
1855        bar_size = pci_resource_len(pdev, bar);
1856
1857        if (offset > bar_size)
1858                return;
1859
1860        /*
1861         * Tell the controller about the host side address mapping the CMB,
1862         * and enable CMB decoding for the NVMe 1.4+ scheme:
1863         */
1864        if (NVME_CAP_CMBS(dev->ctrl.cap)) {
1865                hi_lo_writeq(NVME_CMBMSC_CRE | NVME_CMBMSC_CMSE |
1866                             (pci_bus_address(pdev, bar) + offset),
1867                             dev->bar + NVME_REG_CMBMSC);
1868        }
1869
1870        /*
1871         * Controllers may support a CMB size larger than their BAR,
1872         * for example, due to being behind a bridge. Reduce the CMB to
1873         * the reported size of the BAR
1874         */
1875        if (size > bar_size - offset)
1876                size = bar_size - offset;
1877
1878        if (pci_p2pdma_add_resource(pdev, bar, size, offset)) {
1879                dev_warn(dev->ctrl.device,
1880                         "failed to register the CMB\n");
1881                return;
1882        }
1883
1884        dev->cmb_size = size;
1885        dev->cmb_use_sqes = use_cmb_sqes && (dev->cmbsz & NVME_CMBSZ_SQS);
1886
1887        if ((dev->cmbsz & (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS)) ==
1888                        (NVME_CMBSZ_WDS | NVME_CMBSZ_RDS))
1889                pci_p2pmem_publish(pdev, true);
1890
1891        if (sysfs_add_file_to_group(&dev->ctrl.device->kobj,
1892                                    &dev_attr_cmb.attr, NULL))
1893                dev_warn(dev->ctrl.device,
1894                         "failed to add sysfs attribute for CMB\n");
1895}
1896
1897static inline void nvme_release_cmb(struct nvme_dev *dev)
1898{
1899        if (dev->cmb_size) {
1900                sysfs_remove_file_from_group(&dev->ctrl.device->kobj,
1901                                             &dev_attr_cmb.attr, NULL);
1902                dev->cmb_size = 0;
1903        }
1904}
1905
1906static int nvme_set_host_mem(struct nvme_dev *dev, u32 bits)
1907{
1908        u32 host_mem_size = dev->host_mem_size >> NVME_CTRL_PAGE_SHIFT;
1909        u64 dma_addr = dev->host_mem_descs_dma;
1910        struct nvme_command c = { };
1911        int ret;
1912
1913        c.features.opcode       = nvme_admin_set_features;
1914        c.features.fid          = cpu_to_le32(NVME_FEAT_HOST_MEM_BUF);
1915        c.features.dword11      = cpu_to_le32(bits);
1916        c.features.dword12      = cpu_to_le32(host_mem_size);
1917        c.features.dword13      = cpu_to_le32(lower_32_bits(dma_addr));
1918        c.features.dword14      = cpu_to_le32(upper_32_bits(dma_addr));
1919        c.features.dword15      = cpu_to_le32(dev->nr_host_mem_descs);
1920
1921        ret = nvme_submit_sync_cmd(dev->ctrl.admin_q, &c, NULL, 0);
1922        if (ret) {
1923                dev_warn(dev->ctrl.device,
1924                         "failed to set host mem (err %d, flags %#x).\n",
1925                         ret, bits);
1926        }
1927        return ret;
1928}
1929
1930static void nvme_free_host_mem(struct nvme_dev *dev)
1931{
1932        int i;
1933
1934        for (i = 0; i < dev->nr_host_mem_descs; i++) {
1935                struct nvme_host_mem_buf_desc *desc = &dev->host_mem_descs[i];
1936                size_t size = le32_to_cpu(desc->size) * NVME_CTRL_PAGE_SIZE;
1937
1938                dma_free_attrs(dev->dev, size, dev->host_mem_desc_bufs[i],
1939                               le64_to_cpu(desc->addr),
1940                               DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1941        }
1942
1943        kfree(dev->host_mem_desc_bufs);
1944        dev->host_mem_desc_bufs = NULL;
1945        dma_free_coherent(dev->dev,
1946                        dev->nr_host_mem_descs * sizeof(*dev->host_mem_descs),
1947                        dev->host_mem_descs, dev->host_mem_descs_dma);
1948        dev->host_mem_descs = NULL;
1949        dev->nr_host_mem_descs = 0;
1950}
1951
1952static int __nvme_alloc_host_mem(struct nvme_dev *dev, u64 preferred,
1953                u32 chunk_size)
1954{
1955        struct nvme_host_mem_buf_desc *descs;
1956        u32 max_entries, len;
1957        dma_addr_t descs_dma;
1958        int i = 0;
1959        void **bufs;
1960        u64 size, tmp;
1961
1962        tmp = (preferred + chunk_size - 1);
1963        do_div(tmp, chunk_size);
1964        max_entries = tmp;
1965
1966        if (dev->ctrl.hmmaxd && dev->ctrl.hmmaxd < max_entries)
1967                max_entries = dev->ctrl.hmmaxd;
1968
1969        descs = dma_alloc_coherent(dev->dev, max_entries * sizeof(*descs),
1970                                   &descs_dma, GFP_KERNEL);
1971        if (!descs)
1972                goto out;
1973
1974        bufs = kcalloc(max_entries, sizeof(*bufs), GFP_KERNEL);
1975        if (!bufs)
1976                goto out_free_descs;
1977
1978        for (size = 0; size < preferred && i < max_entries; size += len) {
1979                dma_addr_t dma_addr;
1980
1981                len = min_t(u64, chunk_size, preferred - size);
1982                bufs[i] = dma_alloc_attrs(dev->dev, len, &dma_addr, GFP_KERNEL,
1983                                DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
1984                if (!bufs[i])
1985                        break;
1986
1987                descs[i].addr = cpu_to_le64(dma_addr);
1988                descs[i].size = cpu_to_le32(len / NVME_CTRL_PAGE_SIZE);
1989                i++;
1990        }
1991
1992        if (!size)
1993                goto out_free_bufs;
1994
1995        dev->nr_host_mem_descs = i;
1996        dev->host_mem_size = size;
1997        dev->host_mem_descs = descs;
1998        dev->host_mem_descs_dma = descs_dma;
1999        dev->host_mem_desc_bufs = bufs;
2000        return 0;
2001
2002out_free_bufs:
2003        while (--i >= 0) {
2004                size_t size = le32_to_cpu(descs[i].size) * NVME_CTRL_PAGE_SIZE;
2005
2006                dma_free_attrs(dev->dev, size, bufs[i],
2007                               le64_to_cpu(descs[i].addr),
2008                               DMA_ATTR_NO_KERNEL_MAPPING | DMA_ATTR_NO_WARN);
2009        }
2010
2011        kfree(bufs);
2012out_free_descs:
2013        dma_free_coherent(dev->dev, max_entries * sizeof(*descs), descs,
2014                        descs_dma);
2015out:
2016        dev->host_mem_descs = NULL;
2017        return -ENOMEM;
2018}
2019
2020static int nvme_alloc_host_mem(struct nvme_dev *dev, u64 min, u64 preferred)
2021{
2022        u64 min_chunk = min_t(u64, preferred, PAGE_SIZE * MAX_ORDER_NR_PAGES);
2023        u64 hmminds = max_t(u32, dev->ctrl.hmminds * 4096, PAGE_SIZE * 2);
2024        u64 chunk_size;
2025
2026        /* start big and work our way down */
2027        for (chunk_size = min_chunk; chunk_size >= hmminds; chunk_size /= 2) {
2028                if (!__nvme_alloc_host_mem(dev, preferred, chunk_size)) {
2029                        if (!min || dev->host_mem_size >= min)
2030                                return 0;
2031                        nvme_free_host_mem(dev);
2032                }
2033        }
2034
2035        return -ENOMEM;
2036}
2037
2038static int nvme_setup_host_mem(struct nvme_dev *dev)
2039{
2040        u64 max = (u64)max_host_mem_size_mb * SZ_1M;
2041        u64 preferred = (u64)dev->ctrl.hmpre * 4096;
2042        u64 min = (u64)dev->ctrl.hmmin * 4096;
2043        u32 enable_bits = NVME_HOST_MEM_ENABLE;
2044        int ret;
2045
2046        preferred = min(preferred, max);
2047        if (min > max) {
2048                dev_warn(dev->ctrl.device,
2049                        "min host memory (%lld MiB) above limit (%d MiB).\n",
2050                        min >> ilog2(SZ_1M), max_host_mem_size_mb);
2051                nvme_free_host_mem(dev);
2052                return 0;
2053        }
2054
2055        /*
2056         * If we already have a buffer allocated check if we can reuse it.
2057         */
2058        if (dev->host_mem_descs) {
2059                if (dev->host_mem_size >= min)
2060                        enable_bits |= NVME_HOST_MEM_RETURN;
2061                else
2062                        nvme_free_host_mem(dev);
2063        }
2064
2065        if (!dev->host_mem_descs) {
2066                if (nvme_alloc_host_mem(dev, min, preferred)) {
2067                        dev_warn(dev->ctrl.device,
2068                                "failed to allocate host memory buffer.\n");
2069                        return 0; /* controller must work without HMB */
2070                }
2071
2072                dev_info(dev->ctrl.device,
2073                        "allocated %lld MiB host memory buffer.\n",
2074                        dev->host_mem_size >> ilog2(SZ_1M));
2075        }
2076
2077        ret = nvme_set_host_mem(dev, enable_bits);
2078        if (ret)
2079                nvme_free_host_mem(dev);
2080        return ret;
2081}
2082
2083/*
2084 * nirqs is the number of interrupts available for write and read
2085 * queues. The core already reserved an interrupt for the admin queue.
2086 */
2087static void nvme_calc_irq_sets(struct irq_affinity *affd, unsigned int nrirqs)
2088{
2089        struct nvme_dev *dev = affd->priv;
2090        unsigned int nr_read_queues, nr_write_queues = dev->nr_write_queues;
2091
2092        /*
2093         * If there is no interrupt available for queues, ensure that
2094         * the default queue is set to 1. The affinity set size is
2095         * also set to one, but the irq core ignores it for this case.
2096         *
2097         * If only one interrupt is available or 'write_queue' == 0, combine
2098         * write and read queues.
2099         *
2100         * If 'write_queues' > 0, ensure it leaves room for at least one read
2101         * queue.
2102         */
2103        if (!nrirqs) {
2104                nrirqs = 1;
2105                nr_read_queues = 0;
2106        } else if (nrirqs == 1 || !nr_write_queues) {
2107                nr_read_queues = 0;
2108        } else if (nr_write_queues >= nrirqs) {
2109                nr_read_queues = 1;
2110        } else {
2111                nr_read_queues = nrirqs - nr_write_queues;
2112        }
2113
2114        dev->io_queues[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2115        affd->set_size[HCTX_TYPE_DEFAULT] = nrirqs - nr_read_queues;
2116        dev->io_queues[HCTX_TYPE_READ] = nr_read_queues;
2117        affd->set_size[HCTX_TYPE_READ] = nr_read_queues;
2118        affd->nr_sets = nr_read_queues ? 2 : 1;
2119}
2120
2121static int nvme_setup_irqs(struct nvme_dev *dev, unsigned int nr_io_queues)
2122{
2123        struct pci_dev *pdev = to_pci_dev(dev->dev);
2124        struct irq_affinity affd = {
2125                .pre_vectors    = 1,
2126                .calc_sets      = nvme_calc_irq_sets,
2127                .priv           = dev,
2128        };
2129        unsigned int irq_queues, poll_queues;
2130
2131        /*
2132         * Poll queues don't need interrupts, but we need at least one I/O queue
2133         * left over for non-polled I/O.
2134         */
2135        poll_queues = min(dev->nr_poll_queues, nr_io_queues - 1);
2136        dev->io_queues[HCTX_TYPE_POLL] = poll_queues;
2137
2138        /*
2139         * Initialize for the single interrupt case, will be updated in
2140         * nvme_calc_irq_sets().
2141         */
2142        dev->io_queues[HCTX_TYPE_DEFAULT] = 1;
2143        dev->io_queues[HCTX_TYPE_READ] = 0;
2144
2145        /*
2146         * We need interrupts for the admin queue and each non-polled I/O queue,
2147         * but some Apple controllers require all queues to use the first
2148         * vector.
2149         */
2150        irq_queues = 1;
2151        if (!(dev->ctrl.quirks & NVME_QUIRK_SINGLE_VECTOR))
2152                irq_queues += (nr_io_queues - poll_queues);
2153        return pci_alloc_irq_vectors_affinity(pdev, 1, irq_queues,
2154                              PCI_IRQ_ALL_TYPES | PCI_IRQ_AFFINITY, &affd);
2155}
2156
2157static void nvme_disable_io_queues(struct nvme_dev *dev)
2158{
2159        if (__nvme_disable_io_queues(dev, nvme_admin_delete_sq))
2160                __nvme_disable_io_queues(dev, nvme_admin_delete_cq);
2161}
2162
2163static unsigned int nvme_max_io_queues(struct nvme_dev *dev)
2164{
2165        /*
2166         * If tags are shared with admin queue (Apple bug), then
2167         * make sure we only use one IO queue.
2168         */
2169        if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2170                return 1;
2171        return num_possible_cpus() + dev->nr_write_queues + dev->nr_poll_queues;
2172}
2173
2174static int nvme_setup_io_queues(struct nvme_dev *dev)
2175{
2176        struct nvme_queue *adminq = &dev->queues[0];
2177        struct pci_dev *pdev = to_pci_dev(dev->dev);
2178        unsigned int nr_io_queues;
2179        unsigned long size;
2180        int result;
2181
2182        /*
2183         * Sample the module parameters once at reset time so that we have
2184         * stable values to work with.
2185         */
2186        dev->nr_write_queues = write_queues;
2187        dev->nr_poll_queues = poll_queues;
2188
2189        nr_io_queues = dev->nr_allocated_queues - 1;
2190        result = nvme_set_queue_count(&dev->ctrl, &nr_io_queues);
2191        if (result < 0)
2192                return result;
2193
2194        if (nr_io_queues == 0)
2195                return 0;
2196
2197        /*
2198         * Free IRQ resources as soon as NVMEQ_ENABLED bit transitions
2199         * from set to unset. If there is a window to it is truely freed,
2200         * pci_free_irq_vectors() jumping into this window will crash.
2201         * And take lock to avoid racing with pci_free_irq_vectors() in
2202         * nvme_dev_disable() path.
2203         */
2204        result = nvme_setup_io_queues_trylock(dev);
2205        if (result)
2206                return result;
2207        if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2208                pci_free_irq(pdev, 0, adminq);
2209
2210        if (dev->cmb_use_sqes) {
2211                result = nvme_cmb_qdepth(dev, nr_io_queues,
2212                                sizeof(struct nvme_command));
2213                if (result > 0)
2214                        dev->q_depth = result;
2215                else
2216                        dev->cmb_use_sqes = false;
2217        }
2218
2219        do {
2220                size = db_bar_size(dev, nr_io_queues);
2221                result = nvme_remap_bar(dev, size);
2222                if (!result)
2223                        break;
2224                if (!--nr_io_queues) {
2225                        result = -ENOMEM;
2226                        goto out_unlock;
2227                }
2228        } while (1);
2229        adminq->q_db = dev->dbs;
2230
2231 retry:
2232        /* Deregister the admin queue's interrupt */
2233        if (test_and_clear_bit(NVMEQ_ENABLED, &adminq->flags))
2234                pci_free_irq(pdev, 0, adminq);
2235
2236        /*
2237         * If we enable msix early due to not intx, disable it again before
2238         * setting up the full range we need.
2239         */
2240        pci_free_irq_vectors(pdev);
2241
2242        result = nvme_setup_irqs(dev, nr_io_queues);
2243        if (result <= 0) {
2244                result = -EIO;
2245                goto out_unlock;
2246        }
2247
2248        dev->num_vecs = result;
2249        result = max(result - 1, 1);
2250        dev->max_qid = result + dev->io_queues[HCTX_TYPE_POLL];
2251
2252        /*
2253         * Should investigate if there's a performance win from allocating
2254         * more queues than interrupt vectors; it might allow the submission
2255         * path to scale better, even if the receive path is limited by the
2256         * number of interrupts.
2257         */
2258        result = queue_request_irq(adminq);
2259        if (result)
2260                goto out_unlock;
2261        set_bit(NVMEQ_ENABLED, &adminq->flags);
2262        mutex_unlock(&dev->shutdown_lock);
2263
2264        result = nvme_create_io_queues(dev);
2265        if (result || dev->online_queues < 2)
2266                return result;
2267
2268        if (dev->online_queues - 1 < dev->max_qid) {
2269                nr_io_queues = dev->online_queues - 1;
2270                nvme_disable_io_queues(dev);
2271                result = nvme_setup_io_queues_trylock(dev);
2272                if (result)
2273                        return result;
2274                nvme_suspend_io_queues(dev);
2275                goto retry;
2276        }
2277        dev_info(dev->ctrl.device, "%d/%d/%d default/read/poll queues\n",
2278                                        dev->io_queues[HCTX_TYPE_DEFAULT],
2279                                        dev->io_queues[HCTX_TYPE_READ],
2280                                        dev->io_queues[HCTX_TYPE_POLL]);
2281        return 0;
2282out_unlock:
2283        mutex_unlock(&dev->shutdown_lock);
2284        return result;
2285}
2286
2287static void nvme_del_queue_end(struct request *req, blk_status_t error)
2288{
2289        struct nvme_queue *nvmeq = req->end_io_data;
2290
2291        blk_mq_free_request(req);
2292        complete(&nvmeq->delete_done);
2293}
2294
2295static void nvme_del_cq_end(struct request *req, blk_status_t error)
2296{
2297        struct nvme_queue *nvmeq = req->end_io_data;
2298
2299        if (error)
2300                set_bit(NVMEQ_DELETE_ERROR, &nvmeq->flags);
2301
2302        nvme_del_queue_end(req, error);
2303}
2304
2305static int nvme_delete_queue(struct nvme_queue *nvmeq, u8 opcode)
2306{
2307        struct request_queue *q = nvmeq->dev->ctrl.admin_q;
2308        struct request *req;
2309        struct nvme_command cmd = { };
2310
2311        cmd.delete_queue.opcode = opcode;
2312        cmd.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2313
2314        req = nvme_alloc_request(q, &cmd, BLK_MQ_REQ_NOWAIT);
2315        if (IS_ERR(req))
2316                return PTR_ERR(req);
2317
2318        req->end_io_data = nvmeq;
2319
2320        init_completion(&nvmeq->delete_done);
2321        blk_execute_rq_nowait(NULL, req, false,
2322                        opcode == nvme_admin_delete_cq ?
2323                                nvme_del_cq_end : nvme_del_queue_end);
2324        return 0;
2325}
2326
2327static bool __nvme_disable_io_queues(struct nvme_dev *dev, u8 opcode)
2328{
2329        int nr_queues = dev->online_queues - 1, sent = 0;
2330        unsigned long timeout;
2331
2332 retry:
2333        timeout = NVME_ADMIN_TIMEOUT;
2334        while (nr_queues > 0) {
2335                if (nvme_delete_queue(&dev->queues[nr_queues], opcode))
2336                        break;
2337                nr_queues--;
2338                sent++;
2339        }
2340        while (sent) {
2341                struct nvme_queue *nvmeq = &dev->queues[nr_queues + sent];
2342
2343                timeout = wait_for_completion_io_timeout(&nvmeq->delete_done,
2344                                timeout);
2345                if (timeout == 0)
2346                        return false;
2347
2348                sent--;
2349                if (nr_queues)
2350                        goto retry;
2351        }
2352        return true;
2353}
2354
2355static void nvme_dev_add(struct nvme_dev *dev)
2356{
2357        int ret;
2358
2359        if (!dev->ctrl.tagset) {
2360                dev->tagset.ops = &nvme_mq_ops;
2361                dev->tagset.nr_hw_queues = dev->online_queues - 1;
2362                dev->tagset.nr_maps = 2; /* default + read */
2363                if (dev->io_queues[HCTX_TYPE_POLL])
2364                        dev->tagset.nr_maps++;
2365                dev->tagset.timeout = NVME_IO_TIMEOUT;
2366                dev->tagset.numa_node = dev->ctrl.numa_node;
2367                dev->tagset.queue_depth = min_t(unsigned int, dev->q_depth,
2368                                                BLK_MQ_MAX_DEPTH) - 1;
2369                dev->tagset.cmd_size = sizeof(struct nvme_iod);
2370                dev->tagset.flags = BLK_MQ_F_SHOULD_MERGE;
2371                dev->tagset.driver_data = dev;
2372
2373                /*
2374                 * Some Apple controllers requires tags to be unique
2375                 * across admin and IO queue, so reserve the first 32
2376                 * tags of the IO queue.
2377                 */
2378                if (dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS)
2379                        dev->tagset.reserved_tags = NVME_AQ_DEPTH;
2380
2381                ret = blk_mq_alloc_tag_set(&dev->tagset);
2382                if (ret) {
2383                        dev_warn(dev->ctrl.device,
2384                                "IO queues tagset allocation failed %d\n", ret);
2385                        return;
2386                }
2387                dev->ctrl.tagset = &dev->tagset;
2388        } else {
2389                blk_mq_update_nr_hw_queues(&dev->tagset, dev->online_queues - 1);
2390
2391                /* Free previously allocated queues that are no longer usable */
2392                nvme_free_queues(dev, dev->online_queues);
2393        }
2394
2395        nvme_dbbuf_set(dev);
2396}
2397
2398static int nvme_pci_enable(struct nvme_dev *dev)
2399{
2400        int result = -ENOMEM;
2401        struct pci_dev *pdev = to_pci_dev(dev->dev);
2402        int dma_address_bits = 64;
2403
2404        if (pci_enable_device_mem(pdev))
2405                return result;
2406
2407        pci_set_master(pdev);
2408
2409        if (dev->ctrl.quirks & NVME_QUIRK_DMA_ADDRESS_BITS_48)
2410                dma_address_bits = 48;
2411        if (dma_set_mask_and_coherent(dev->dev, DMA_BIT_MASK(dma_address_bits)))
2412                goto disable;
2413
2414        if (readl(dev->bar + NVME_REG_CSTS) == -1) {
2415                result = -ENODEV;
2416                goto disable;
2417        }
2418
2419        /*
2420         * Some devices and/or platforms don't advertise or work with INTx
2421         * interrupts. Pre-enable a single MSIX or MSI vec for setup. We'll
2422         * adjust this later.
2423         */
2424        result = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
2425        if (result < 0)
2426                return result;
2427
2428        dev->ctrl.cap = lo_hi_readq(dev->bar + NVME_REG_CAP);
2429
2430        dev->q_depth = min_t(u32, NVME_CAP_MQES(dev->ctrl.cap) + 1,
2431                                io_queue_depth);
2432        dev->ctrl.sqsize = dev->q_depth - 1; /* 0's based queue depth */
2433        dev->db_stride = 1 << NVME_CAP_STRIDE(dev->ctrl.cap);
2434        dev->dbs = dev->bar + 4096;
2435
2436        /*
2437         * Some Apple controllers require a non-standard SQE size.
2438         * Interestingly they also seem to ignore the CC:IOSQES register
2439         * so we don't bother updating it here.
2440         */
2441        if (dev->ctrl.quirks & NVME_QUIRK_128_BYTES_SQES)
2442                dev->io_sqes = 7;
2443        else
2444                dev->io_sqes = NVME_NVM_IOSQES;
2445
2446        /*
2447         * Temporary fix for the Apple controller found in the MacBook8,1 and
2448         * some MacBook7,1 to avoid controller resets and data loss.
2449         */
2450        if (pdev->vendor == PCI_VENDOR_ID_APPLE && pdev->device == 0x2001) {
2451                dev->q_depth = 2;
2452                dev_warn(dev->ctrl.device, "detected Apple NVMe controller, "
2453                        "set queue depth=%u to work around controller resets\n",
2454                        dev->q_depth);
2455        } else if (pdev->vendor == PCI_VENDOR_ID_SAMSUNG &&
2456                   (pdev->device == 0xa821 || pdev->device == 0xa822) &&
2457                   NVME_CAP_MQES(dev->ctrl.cap) == 0) {
2458                dev->q_depth = 64;
2459                dev_err(dev->ctrl.device, "detected PM1725 NVMe controller, "
2460                        "set queue depth=%u\n", dev->q_depth);
2461        }
2462
2463        /*
2464         * Controllers with the shared tags quirk need the IO queue to be
2465         * big enough so that we get 32 tags for the admin queue
2466         */
2467        if ((dev->ctrl.quirks & NVME_QUIRK_SHARED_TAGS) &&
2468            (dev->q_depth < (NVME_AQ_DEPTH + 2))) {
2469                dev->q_depth = NVME_AQ_DEPTH + 2;
2470                dev_warn(dev->ctrl.device, "IO queue depth clamped to %d\n",
2471                         dev->q_depth);
2472        }
2473
2474
2475        nvme_map_cmb(dev);
2476
2477        pci_enable_pcie_error_reporting(pdev);
2478        pci_save_state(pdev);
2479        return 0;
2480
2481 disable:
2482        pci_disable_device(pdev);
2483        return result;
2484}
2485
2486static void nvme_dev_unmap(struct nvme_dev *dev)
2487{
2488        if (dev->bar)
2489                iounmap(dev->bar);
2490        pci_release_mem_regions(to_pci_dev(dev->dev));
2491}
2492
2493static void nvme_pci_disable(struct nvme_dev *dev)
2494{
2495        struct pci_dev *pdev = to_pci_dev(dev->dev);
2496
2497        pci_free_irq_vectors(pdev);
2498
2499        if (pci_is_enabled(pdev)) {
2500                pci_disable_pcie_error_reporting(pdev);
2501                pci_disable_device(pdev);
2502        }
2503}
2504
2505static void nvme_dev_disable(struct nvme_dev *dev, bool shutdown)
2506{
2507        bool dead = true, freeze = false;
2508        struct pci_dev *pdev = to_pci_dev(dev->dev);
2509
2510        mutex_lock(&dev->shutdown_lock);
2511        if (pci_is_enabled(pdev)) {
2512                u32 csts = readl(dev->bar + NVME_REG_CSTS);
2513
2514                if (dev->ctrl.state == NVME_CTRL_LIVE ||
2515                    dev->ctrl.state == NVME_CTRL_RESETTING) {
2516                        freeze = true;
2517                        nvme_start_freeze(&dev->ctrl);
2518                }
2519                dead = !!((csts & NVME_CSTS_CFS) || !(csts & NVME_CSTS_RDY) ||
2520                        pdev->error_state  != pci_channel_io_normal);
2521        }
2522
2523        /*
2524         * Give the controller a chance to complete all entered requests if
2525         * doing a safe shutdown.
2526         */
2527        if (!dead && shutdown && freeze)
2528                nvme_wait_freeze_timeout(&dev->ctrl, NVME_IO_TIMEOUT);
2529
2530        nvme_stop_queues(&dev->ctrl);
2531
2532        if (!dead && dev->ctrl.queue_count > 0) {
2533                nvme_disable_io_queues(dev);
2534                nvme_disable_admin_queue(dev, shutdown);
2535        }
2536        nvme_suspend_io_queues(dev);
2537        nvme_suspend_queue(&dev->queues[0]);
2538        nvme_pci_disable(dev);
2539        nvme_reap_pending_cqes(dev);
2540
2541        blk_mq_tagset_busy_iter(&dev->tagset, nvme_cancel_request, &dev->ctrl);
2542        blk_mq_tagset_busy_iter(&dev->admin_tagset, nvme_cancel_request, &dev->ctrl);
2543        blk_mq_tagset_wait_completed_request(&dev->tagset);
2544        blk_mq_tagset_wait_completed_request(&dev->admin_tagset);
2545
2546        /*
2547         * The driver will not be starting up queues again if shutting down so
2548         * must flush all entered requests to their failed completion to avoid
2549         * deadlocking blk-mq hot-cpu notifier.
2550         */
2551        if (shutdown) {
2552                nvme_start_queues(&dev->ctrl);
2553                if (dev->ctrl.admin_q && !blk_queue_dying(dev->ctrl.admin_q))
2554                        blk_mq_unquiesce_queue(dev->ctrl.admin_q);
2555        }
2556        mutex_unlock(&dev->shutdown_lock);
2557}
2558
2559static int nvme_disable_prepare_reset(struct nvme_dev *dev, bool shutdown)
2560{
2561        if (!nvme_wait_reset(&dev->ctrl))
2562                return -EBUSY;
2563        nvme_dev_disable(dev, shutdown);
2564        return 0;
2565}
2566
2567static int nvme_setup_prp_pools(struct nvme_dev *dev)
2568{
2569        dev->prp_page_pool = dma_pool_create("prp list page", dev->dev,
2570                                                NVME_CTRL_PAGE_SIZE,
2571                                                NVME_CTRL_PAGE_SIZE, 0);
2572        if (!dev->prp_page_pool)
2573                return -ENOMEM;
2574
2575        /* Optimisation for I/Os between 4k and 128k */
2576        dev->prp_small_pool = dma_pool_create("prp list 256", dev->dev,
2577                                                256, 256, 0);
2578        if (!dev->prp_small_pool) {
2579                dma_pool_destroy(dev->prp_page_pool);
2580                return -ENOMEM;
2581        }
2582        return 0;
2583}
2584
2585static void nvme_release_prp_pools(struct nvme_dev *dev)
2586{
2587        dma_pool_destroy(dev->prp_page_pool);
2588        dma_pool_destroy(dev->prp_small_pool);
2589}
2590
2591static void nvme_free_tagset(struct nvme_dev *dev)
2592{
2593        if (dev->tagset.tags)
2594                blk_mq_free_tag_set(&dev->tagset);
2595        dev->ctrl.tagset = NULL;
2596}
2597
2598static void nvme_pci_free_ctrl(struct nvme_ctrl *ctrl)
2599{
2600        struct nvme_dev *dev = to_nvme_dev(ctrl);
2601
2602        nvme_dbbuf_dma_free(dev);
2603        nvme_free_tagset(dev);
2604        if (dev->ctrl.admin_q)
2605                blk_put_queue(dev->ctrl.admin_q);
2606        free_opal_dev(dev->ctrl.opal_dev);
2607        mempool_destroy(dev->iod_mempool);
2608        put_device(dev->dev);
2609        kfree(dev->queues);
2610        kfree(dev);
2611}
2612
2613static void nvme_remove_dead_ctrl(struct nvme_dev *dev)
2614{
2615        /*
2616         * Set state to deleting now to avoid blocking nvme_wait_reset(), which
2617         * may be holding this pci_dev's device lock.
2618         */
2619        nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
2620        nvme_get_ctrl(&dev->ctrl);
2621        nvme_dev_disable(dev, false);
2622        nvme_kill_queues(&dev->ctrl);
2623        if (!queue_work(nvme_wq, &dev->remove_work))
2624                nvme_put_ctrl(&dev->ctrl);
2625}
2626
2627static void nvme_reset_work(struct work_struct *work)
2628{
2629        struct nvme_dev *dev =
2630                container_of(work, struct nvme_dev, ctrl.reset_work);
2631        bool was_suspend = !!(dev->ctrl.ctrl_config & NVME_CC_SHN_NORMAL);
2632        int result;
2633
2634        if (dev->ctrl.state != NVME_CTRL_RESETTING) {
2635                dev_warn(dev->ctrl.device, "ctrl state %d is not RESETTING\n",
2636                         dev->ctrl.state);
2637                result = -ENODEV;
2638                goto out;
2639        }
2640
2641        /*
2642         * If we're called to reset a live controller first shut it down before
2643         * moving on.
2644         */
2645        if (dev->ctrl.ctrl_config & NVME_CC_ENABLE)
2646                nvme_dev_disable(dev, false);
2647        nvme_sync_queues(&dev->ctrl);
2648
2649        mutex_lock(&dev->shutdown_lock);
2650        result = nvme_pci_enable(dev);
2651        if (result)
2652                goto out_unlock;
2653
2654        result = nvme_pci_configure_admin_queue(dev);
2655        if (result)
2656                goto out_unlock;
2657
2658        result = nvme_alloc_admin_tags(dev);
2659        if (result)
2660                goto out_unlock;
2661
2662        /*
2663         * Limit the max command size to prevent iod->sg allocations going
2664         * over a single page.
2665         */
2666        dev->ctrl.max_hw_sectors = min_t(u32,
2667                NVME_MAX_KB_SZ << 1, dma_max_mapping_size(dev->dev) >> 9);
2668        dev->ctrl.max_segments = NVME_MAX_SEGS;
2669
2670        /*
2671         * Don't limit the IOMMU merged segment size.
2672         */
2673        dma_set_max_seg_size(dev->dev, 0xffffffff);
2674        dma_set_min_align_mask(dev->dev, NVME_CTRL_PAGE_SIZE - 1);
2675
2676        mutex_unlock(&dev->shutdown_lock);
2677
2678        /*
2679         * Introduce CONNECTING state from nvme-fc/rdma transports to mark the
2680         * initializing procedure here.
2681         */
2682        if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_CONNECTING)) {
2683                dev_warn(dev->ctrl.device,
2684                        "failed to mark controller CONNECTING\n");
2685                result = -EBUSY;
2686                goto out;
2687        }
2688
2689        /*
2690         * We do not support an SGL for metadata (yet), so we are limited to a
2691         * single integrity segment for the separate metadata pointer.
2692         */
2693        dev->ctrl.max_integrity_segments = 1;
2694
2695        result = nvme_init_ctrl_finish(&dev->ctrl);
2696        if (result)
2697                goto out;
2698
2699        if (dev->ctrl.oacs & NVME_CTRL_OACS_SEC_SUPP) {
2700                if (!dev->ctrl.opal_dev)
2701                        dev->ctrl.opal_dev =
2702                                init_opal_dev(&dev->ctrl, &nvme_sec_submit);
2703                else if (was_suspend)
2704                        opal_unlock_from_suspend(dev->ctrl.opal_dev);
2705        } else {
2706                free_opal_dev(dev->ctrl.opal_dev);
2707                dev->ctrl.opal_dev = NULL;
2708        }
2709
2710        if (dev->ctrl.oacs & NVME_CTRL_OACS_DBBUF_SUPP) {
2711                result = nvme_dbbuf_dma_alloc(dev);
2712                if (result)
2713                        dev_warn(dev->dev,
2714                                 "unable to allocate dma for dbbuf\n");
2715        }
2716
2717        if (dev->ctrl.hmpre) {
2718                result = nvme_setup_host_mem(dev);
2719                if (result < 0)
2720                        goto out;
2721        }
2722
2723        result = nvme_setup_io_queues(dev);
2724        if (result)
2725                goto out;
2726
2727        /*
2728         * Keep the controller around but remove all namespaces if we don't have
2729         * any working I/O queue.
2730         */
2731        if (dev->online_queues < 2) {
2732                dev_warn(dev->ctrl.device, "IO queues not created\n");
2733                nvme_kill_queues(&dev->ctrl);
2734                nvme_remove_namespaces(&dev->ctrl);
2735                nvme_free_tagset(dev);
2736        } else {
2737                nvme_start_queues(&dev->ctrl);
2738                nvme_wait_freeze(&dev->ctrl);
2739                nvme_dev_add(dev);
2740                nvme_unfreeze(&dev->ctrl);
2741        }
2742
2743        /*
2744         * If only admin queue live, keep it to do further investigation or
2745         * recovery.
2746         */
2747        if (!nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_LIVE)) {
2748                dev_warn(dev->ctrl.device,
2749                        "failed to mark controller live state\n");
2750                result = -ENODEV;
2751                goto out;
2752        }
2753
2754        nvme_start_ctrl(&dev->ctrl);
2755        return;
2756
2757 out_unlock:
2758        mutex_unlock(&dev->shutdown_lock);
2759 out:
2760        if (result)
2761                dev_warn(dev->ctrl.device,
2762                         "Removing after probe failure status: %d\n", result);
2763        nvme_remove_dead_ctrl(dev);
2764}
2765
2766static void nvme_remove_dead_ctrl_work(struct work_struct *work)
2767{
2768        struct nvme_dev *dev = container_of(work, struct nvme_dev, remove_work);
2769        struct pci_dev *pdev = to_pci_dev(dev->dev);
2770
2771        if (pci_get_drvdata(pdev))
2772                device_release_driver(&pdev->dev);
2773        nvme_put_ctrl(&dev->ctrl);
2774}
2775
2776static int nvme_pci_reg_read32(struct nvme_ctrl *ctrl, u32 off, u32 *val)
2777{
2778        *val = readl(to_nvme_dev(ctrl)->bar + off);
2779        return 0;
2780}
2781
2782static int nvme_pci_reg_write32(struct nvme_ctrl *ctrl, u32 off, u32 val)
2783{
2784        writel(val, to_nvme_dev(ctrl)->bar + off);
2785        return 0;
2786}
2787
2788static int nvme_pci_reg_read64(struct nvme_ctrl *ctrl, u32 off, u64 *val)
2789{
2790        *val = lo_hi_readq(to_nvme_dev(ctrl)->bar + off);
2791        return 0;
2792}
2793
2794static int nvme_pci_get_address(struct nvme_ctrl *ctrl, char *buf, int size)
2795{
2796        struct pci_dev *pdev = to_pci_dev(to_nvme_dev(ctrl)->dev);
2797
2798        return snprintf(buf, size, "%s\n", dev_name(&pdev->dev));
2799}
2800
2801static const struct nvme_ctrl_ops nvme_pci_ctrl_ops = {
2802        .name                   = "pcie",
2803        .module                 = THIS_MODULE,
2804        .flags                  = NVME_F_METADATA_SUPPORTED |
2805                                  NVME_F_PCI_P2PDMA,
2806        .reg_read32             = nvme_pci_reg_read32,
2807        .reg_write32            = nvme_pci_reg_write32,
2808        .reg_read64             = nvme_pci_reg_read64,
2809        .free_ctrl              = nvme_pci_free_ctrl,
2810        .submit_async_event     = nvme_pci_submit_async_event,
2811        .get_address            = nvme_pci_get_address,
2812};
2813
2814static int nvme_dev_map(struct nvme_dev *dev)
2815{
2816        struct pci_dev *pdev = to_pci_dev(dev->dev);
2817
2818        if (pci_request_mem_regions(pdev, "nvme"))
2819                return -ENODEV;
2820
2821        if (nvme_remap_bar(dev, NVME_REG_DBS + 4096))
2822                goto release;
2823
2824        return 0;
2825  release:
2826        pci_release_mem_regions(pdev);
2827        return -ENODEV;
2828}
2829
2830static unsigned long check_vendor_combination_bug(struct pci_dev *pdev)
2831{
2832        if (pdev->vendor == 0x144d && pdev->device == 0xa802) {
2833                /*
2834                 * Several Samsung devices seem to drop off the PCIe bus
2835                 * randomly when APST is on and uses the deepest sleep state.
2836                 * This has been observed on a Samsung "SM951 NVMe SAMSUNG
2837                 * 256GB", a "PM951 NVMe SAMSUNG 512GB", and a "Samsung SSD
2838                 * 950 PRO 256GB", but it seems to be restricted to two Dell
2839                 * laptops.
2840                 */
2841                if (dmi_match(DMI_SYS_VENDOR, "Dell Inc.") &&
2842                    (dmi_match(DMI_PRODUCT_NAME, "XPS 15 9550") ||
2843                     dmi_match(DMI_PRODUCT_NAME, "Precision 5510")))
2844                        return NVME_QUIRK_NO_DEEPEST_PS;
2845        } else if (pdev->vendor == 0x144d && pdev->device == 0xa804) {
2846                /*
2847                 * Samsung SSD 960 EVO drops off the PCIe bus after system
2848                 * suspend on a Ryzen board, ASUS PRIME B350M-A, as well as
2849                 * within few minutes after bootup on a Coffee Lake board -
2850                 * ASUS PRIME Z370-A
2851                 */
2852                if (dmi_match(DMI_BOARD_VENDOR, "ASUSTeK COMPUTER INC.") &&
2853                    (dmi_match(DMI_BOARD_NAME, "PRIME B350M-A") ||
2854                     dmi_match(DMI_BOARD_NAME, "PRIME Z370-A")))
2855                        return NVME_QUIRK_NO_APST;
2856        } else if ((pdev->vendor == 0x144d && (pdev->device == 0xa801 ||
2857                    pdev->device == 0xa808 || pdev->device == 0xa809)) ||
2858                   (pdev->vendor == 0x1e0f && pdev->device == 0x0001)) {
2859                /*
2860                 * Forcing to use host managed nvme power settings for
2861                 * lowest idle power with quick resume latency on
2862                 * Samsung and Toshiba SSDs based on suspend behavior
2863                 * on Coffee Lake board for LENOVO C640
2864                 */
2865                if ((dmi_match(DMI_BOARD_VENDOR, "LENOVO")) &&
2866                     dmi_match(DMI_BOARD_NAME, "LNVNB161216"))
2867                        return NVME_QUIRK_SIMPLE_SUSPEND;
2868        }
2869
2870        return 0;
2871}
2872
2873static void nvme_async_probe(void *data, async_cookie_t cookie)
2874{
2875        struct nvme_dev *dev = data;
2876
2877        flush_work(&dev->ctrl.reset_work);
2878        flush_work(&dev->ctrl.scan_work);
2879        nvme_put_ctrl(&dev->ctrl);
2880}
2881
2882static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2883{
2884        int node, result = -ENOMEM;
2885        struct nvme_dev *dev;
2886        unsigned long quirks = id->driver_data;
2887        size_t alloc_size;
2888
2889        node = dev_to_node(&pdev->dev);
2890        if (node == NUMA_NO_NODE)
2891                set_dev_node(&pdev->dev, first_memory_node);
2892
2893        dev = kzalloc_node(sizeof(*dev), GFP_KERNEL, node);
2894        if (!dev)
2895                return -ENOMEM;
2896
2897        dev->nr_write_queues = write_queues;
2898        dev->nr_poll_queues = poll_queues;
2899        dev->nr_allocated_queues = nvme_max_io_queues(dev) + 1;
2900        dev->queues = kcalloc_node(dev->nr_allocated_queues,
2901                        sizeof(struct nvme_queue), GFP_KERNEL, node);
2902        if (!dev->queues)
2903                goto free;
2904
2905        dev->dev = get_device(&pdev->dev);
2906        pci_set_drvdata(pdev, dev);
2907
2908        result = nvme_dev_map(dev);
2909        if (result)
2910                goto put_pci;
2911
2912        INIT_WORK(&dev->ctrl.reset_work, nvme_reset_work);
2913        INIT_WORK(&dev->remove_work, nvme_remove_dead_ctrl_work);
2914        mutex_init(&dev->shutdown_lock);
2915
2916        result = nvme_setup_prp_pools(dev);
2917        if (result)
2918                goto unmap;
2919
2920        quirks |= check_vendor_combination_bug(pdev);
2921
2922        if (!noacpi && acpi_storage_d3(&pdev->dev)) {
2923                /*
2924                 * Some systems use a bios work around to ask for D3 on
2925                 * platforms that support kernel managed suspend.
2926                 */
2927                dev_info(&pdev->dev,
2928                         "platform quirk: setting simple suspend\n");
2929                quirks |= NVME_QUIRK_SIMPLE_SUSPEND;
2930        }
2931
2932        /*
2933         * Double check that our mempool alloc size will cover the biggest
2934         * command we support.
2935         */
2936        alloc_size = nvme_pci_iod_alloc_size();
2937        WARN_ON_ONCE(alloc_size > PAGE_SIZE);
2938
2939        dev->iod_mempool = mempool_create_node(1, mempool_kmalloc,
2940                                                mempool_kfree,
2941                                                (void *) alloc_size,
2942                                                GFP_KERNEL, node);
2943        if (!dev->iod_mempool) {
2944                result = -ENOMEM;
2945                goto release_pools;
2946        }
2947
2948        result = nvme_init_ctrl(&dev->ctrl, &pdev->dev, &nvme_pci_ctrl_ops,
2949                        quirks);
2950        if (result)
2951                goto release_mempool;
2952
2953        dev_info(dev->ctrl.device, "pci function %s\n", dev_name(&pdev->dev));
2954
2955        nvme_reset_ctrl(&dev->ctrl);
2956        async_schedule(nvme_async_probe, dev);
2957
2958        return 0;
2959
2960 release_mempool:
2961        mempool_destroy(dev->iod_mempool);
2962 release_pools:
2963        nvme_release_prp_pools(dev);
2964 unmap:
2965        nvme_dev_unmap(dev);
2966 put_pci:
2967        put_device(dev->dev);
2968 free:
2969        kfree(dev->queues);
2970        kfree(dev);
2971        return result;
2972}
2973
2974static void nvme_reset_prepare(struct pci_dev *pdev)
2975{
2976        struct nvme_dev *dev = pci_get_drvdata(pdev);
2977
2978        /*
2979         * We don't need to check the return value from waiting for the reset
2980         * state as pci_dev device lock is held, making it impossible to race
2981         * with ->remove().
2982         */
2983        nvme_disable_prepare_reset(dev, false);
2984        nvme_sync_queues(&dev->ctrl);
2985}
2986
2987static void nvme_reset_done(struct pci_dev *pdev)
2988{
2989        struct nvme_dev *dev = pci_get_drvdata(pdev);
2990
2991        if (!nvme_try_sched_reset(&dev->ctrl))
2992                flush_work(&dev->ctrl.reset_work);
2993}
2994
2995static void nvme_shutdown(struct pci_dev *pdev)
2996{
2997        struct nvme_dev *dev = pci_get_drvdata(pdev);
2998
2999        nvme_disable_prepare_reset(dev, true);
3000}
3001
3002/*
3003 * The driver's remove may be called on a device in a partially initialized
3004 * state. This function must not have any dependencies on the device state in
3005 * order to proceed.
3006 */
3007static void nvme_remove(struct pci_dev *pdev)
3008{
3009        struct nvme_dev *dev = pci_get_drvdata(pdev);
3010
3011        nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DELETING);
3012        pci_set_drvdata(pdev, NULL);
3013
3014        if (!pci_device_is_present(pdev)) {
3015                nvme_change_ctrl_state(&dev->ctrl, NVME_CTRL_DEAD);
3016                nvme_dev_disable(dev, true);
3017        }
3018
3019        flush_work(&dev->ctrl.reset_work);
3020        nvme_stop_ctrl(&dev->ctrl);
3021        nvme_remove_namespaces(&dev->ctrl);
3022        nvme_dev_disable(dev, true);
3023        nvme_release_cmb(dev);
3024        nvme_free_host_mem(dev);
3025        nvme_dev_remove_admin(dev);
3026        nvme_free_queues(dev, 0);
3027        nvme_release_prp_pools(dev);
3028        nvme_dev_unmap(dev);
3029        nvme_uninit_ctrl(&dev->ctrl);
3030}
3031
3032#ifdef CONFIG_PM_SLEEP
3033static int nvme_get_power_state(struct nvme_ctrl *ctrl, u32 *ps)
3034{
3035        return nvme_get_features(ctrl, NVME_FEAT_POWER_MGMT, 0, NULL, 0, ps);
3036}
3037
3038static int nvme_set_power_state(struct nvme_ctrl *ctrl, u32 ps)
3039{
3040        return nvme_set_features(ctrl, NVME_FEAT_POWER_MGMT, ps, NULL, 0, NULL);
3041}
3042
3043static int nvme_resume(struct device *dev)
3044{
3045        struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3046        struct nvme_ctrl *ctrl = &ndev->ctrl;
3047
3048        if (ndev->last_ps == U32_MAX ||
3049            nvme_set_power_state(ctrl, ndev->last_ps) != 0)
3050                return nvme_try_sched_reset(&ndev->ctrl);
3051        return 0;
3052}
3053
3054static int nvme_suspend(struct device *dev)
3055{
3056        struct pci_dev *pdev = to_pci_dev(dev);
3057        struct nvme_dev *ndev = pci_get_drvdata(pdev);
3058        struct nvme_ctrl *ctrl = &ndev->ctrl;
3059        int ret = -EBUSY;
3060
3061        ndev->last_ps = U32_MAX;
3062
3063        /*
3064         * The platform does not remove power for a kernel managed suspend so
3065         * use host managed nvme power settings for lowest idle power if
3066         * possible. This should have quicker resume latency than a full device
3067         * shutdown.  But if the firmware is involved after the suspend or the
3068         * device does not support any non-default power states, shut down the
3069         * device fully.
3070         *
3071         * If ASPM is not enabled for the device, shut down the device and allow
3072         * the PCI bus layer to put it into D3 in order to take the PCIe link
3073         * down, so as to allow the platform to achieve its minimum low-power
3074         * state (which may not be possible if the link is up).
3075         *
3076         * If a host memory buffer is enabled, shut down the device as the NVMe
3077         * specification allows the device to access the host memory buffer in
3078         * host DRAM from all power states, but hosts will fail access to DRAM
3079         * during S3.
3080         */
3081        if (pm_suspend_via_firmware() || !ctrl->npss ||
3082            !pcie_aspm_enabled(pdev) ||
3083            ndev->nr_host_mem_descs ||
3084            (ndev->ctrl.quirks & NVME_QUIRK_SIMPLE_SUSPEND))
3085                return nvme_disable_prepare_reset(ndev, true);
3086
3087        nvme_start_freeze(ctrl);
3088        nvme_wait_freeze(ctrl);
3089        nvme_sync_queues(ctrl);
3090
3091        if (ctrl->state != NVME_CTRL_LIVE)
3092                goto unfreeze;
3093
3094        ret = nvme_get_power_state(ctrl, &ndev->last_ps);
3095        if (ret < 0)
3096                goto unfreeze;
3097
3098        /*
3099         * A saved state prevents pci pm from generically controlling the
3100         * device's power. If we're using protocol specific settings, we don't
3101         * want pci interfering.
3102         */
3103        pci_save_state(pdev);
3104
3105        ret = nvme_set_power_state(ctrl, ctrl->npss);
3106        if (ret < 0)
3107                goto unfreeze;
3108
3109        if (ret) {
3110                /* discard the saved state */
3111                pci_load_saved_state(pdev, NULL);
3112
3113                /*
3114                 * Clearing npss forces a controller reset on resume. The
3115                 * correct value will be rediscovered then.
3116                 */
3117                ret = nvme_disable_prepare_reset(ndev, true);
3118                ctrl->npss = 0;
3119        }
3120unfreeze:
3121        nvme_unfreeze(ctrl);
3122        return ret;
3123}
3124
3125static int nvme_simple_suspend(struct device *dev)
3126{
3127        struct nvme_dev *ndev = pci_get_drvdata(to_pci_dev(dev));
3128
3129        return nvme_disable_prepare_reset(ndev, true);
3130}
3131
3132static int nvme_simple_resume(struct device *dev)
3133{
3134        struct pci_dev *pdev = to_pci_dev(dev);
3135        struct nvme_dev *ndev = pci_get_drvdata(pdev);
3136
3137        return nvme_try_sched_reset(&ndev->ctrl);
3138}
3139
3140static const struct dev_pm_ops nvme_dev_pm_ops = {
3141        .suspend        = nvme_suspend,
3142        .resume         = nvme_resume,
3143        .freeze         = nvme_simple_suspend,
3144        .thaw           = nvme_simple_resume,
3145        .poweroff       = nvme_simple_suspend,
3146        .restore        = nvme_simple_resume,
3147};
3148#endif /* CONFIG_PM_SLEEP */
3149
3150static pci_ers_result_t nvme_error_detected(struct pci_dev *pdev,
3151                                                pci_channel_state_t state)
3152{
3153        struct nvme_dev *dev = pci_get_drvdata(pdev);
3154
3155        /*
3156         * A frozen channel requires a reset. When detected, this method will
3157         * shutdown the controller to quiesce. The controller will be restarted
3158         * after the slot reset through driver's slot_reset callback.
3159         */
3160        switch (state) {
3161        case pci_channel_io_normal:
3162                return PCI_ERS_RESULT_CAN_RECOVER;
3163        case pci_channel_io_frozen:
3164                dev_warn(dev->ctrl.device,
3165                        "frozen state error detected, reset controller\n");
3166                nvme_dev_disable(dev, false);
3167                return PCI_ERS_RESULT_NEED_RESET;
3168        case pci_channel_io_perm_failure:
3169                dev_warn(dev->ctrl.device,
3170                        "failure state error detected, request disconnect\n");
3171                return PCI_ERS_RESULT_DISCONNECT;
3172        }
3173        return PCI_ERS_RESULT_NEED_RESET;
3174}
3175
3176static pci_ers_result_t nvme_slot_reset(struct pci_dev *pdev)
3177{
3178        struct nvme_dev *dev = pci_get_drvdata(pdev);
3179
3180        dev_info(dev->ctrl.device, "restart after slot reset\n");
3181        pci_restore_state(pdev);
3182        nvme_reset_ctrl(&dev->ctrl);
3183        return PCI_ERS_RESULT_RECOVERED;
3184}
3185
3186static void nvme_error_resume(struct pci_dev *pdev)
3187{
3188        struct nvme_dev *dev = pci_get_drvdata(pdev);
3189
3190        flush_work(&dev->ctrl.reset_work);
3191}
3192
3193static const struct pci_error_handlers nvme_err_handler = {
3194        .error_detected = nvme_error_detected,
3195        .slot_reset     = nvme_slot_reset,
3196        .resume         = nvme_error_resume,
3197        .reset_prepare  = nvme_reset_prepare,
3198        .reset_done     = nvme_reset_done,
3199};
3200
3201static const struct pci_device_id nvme_id_table[] = {
3202        { PCI_VDEVICE(INTEL, 0x0953),   /* Intel 750/P3500/P3600/P3700 */
3203                .driver_data = NVME_QUIRK_STRIPE_SIZE |
3204                                NVME_QUIRK_DEALLOCATE_ZEROES, },
3205        { PCI_VDEVICE(INTEL, 0x0a53),   /* Intel P3520 */
3206                .driver_data = NVME_QUIRK_STRIPE_SIZE |
3207                                NVME_QUIRK_DEALLOCATE_ZEROES, },
3208        { PCI_VDEVICE(INTEL, 0x0a54),   /* Intel P4500/P4600 */
3209                .driver_data = NVME_QUIRK_STRIPE_SIZE |
3210                                NVME_QUIRK_DEALLOCATE_ZEROES, },
3211        { PCI_VDEVICE(INTEL, 0x0a55),   /* Dell Express Flash P4600 */
3212                .driver_data = NVME_QUIRK_STRIPE_SIZE |
3213                                NVME_QUIRK_DEALLOCATE_ZEROES, },
3214        { PCI_VDEVICE(INTEL, 0xf1a5),   /* Intel 600P/P3100 */
3215                .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3216                                NVME_QUIRK_MEDIUM_PRIO_SQ |
3217                                NVME_QUIRK_NO_TEMP_THRESH_CHANGE |
3218                                NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3219        { PCI_VDEVICE(INTEL, 0xf1a6),   /* Intel 760p/Pro 7600p */
3220                .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3221        { PCI_VDEVICE(INTEL, 0x5845),   /* Qemu emulated controller */
3222                .driver_data = NVME_QUIRK_IDENTIFY_CNS |
3223                                NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3224        { PCI_DEVICE(0x126f, 0x2263),   /* Silicon Motion unidentified */
3225                .driver_data = NVME_QUIRK_NO_NS_DESC_LIST, },
3226        { PCI_DEVICE(0x1bb1, 0x0100),   /* Seagate Nytro Flash Storage */
3227                .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3228                                NVME_QUIRK_NO_NS_DESC_LIST, },
3229        { PCI_DEVICE(0x1c58, 0x0003),   /* HGST adapter */
3230                .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3231        { PCI_DEVICE(0x1c58, 0x0023),   /* WDC SN200 adapter */
3232                .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3233        { PCI_DEVICE(0x1c5f, 0x0540),   /* Memblaze Pblaze4 adapter */
3234                .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3235        { PCI_DEVICE(0x144d, 0xa821),   /* Samsung PM1725 */
3236                .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY, },
3237        { PCI_DEVICE(0x144d, 0xa822),   /* Samsung PM1725a */
3238                .driver_data = NVME_QUIRK_DELAY_BEFORE_CHK_RDY |
3239                                NVME_QUIRK_DISABLE_WRITE_ZEROES|
3240                                NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3241        { PCI_DEVICE(0x1987, 0x5016),   /* Phison E16 */
3242                .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3243        { PCI_DEVICE(0x1b4b, 0x1092),   /* Lexar 256 GB SSD */
3244                .driver_data = NVME_QUIRK_NO_NS_DESC_LIST |
3245                                NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3246        { PCI_DEVICE(0x1d1d, 0x1f1f),   /* LighNVM qemu device */
3247                .driver_data = NVME_QUIRK_LIGHTNVM, },
3248        { PCI_DEVICE(0x1d1d, 0x2807),   /* CNEX WL */
3249                .driver_data = NVME_QUIRK_LIGHTNVM, },
3250        { PCI_DEVICE(0x1d1d, 0x2601),   /* CNEX Granby */
3251                .driver_data = NVME_QUIRK_LIGHTNVM, },
3252        { PCI_DEVICE(0x10ec, 0x5762),   /* ADATA SX6000LNP */
3253                .driver_data = NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3254        { PCI_DEVICE(0x1cc1, 0x8201),   /* ADATA SX8200PNP 512GB */
3255                .driver_data = NVME_QUIRK_NO_DEEPEST_PS |
3256                                NVME_QUIRK_IGNORE_DEV_SUBNQN, },
3257        { PCI_DEVICE(0x1c5c, 0x1504),   /* SK Hynix PC400 */
3258                .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3259        { PCI_DEVICE(0x15b7, 0x2001),   /*  Sandisk Skyhawk */
3260                .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3261        { PCI_DEVICE(0x1d97, 0x2263),   /* SPCC */
3262                .driver_data = NVME_QUIRK_DISABLE_WRITE_ZEROES, },
3263        { PCI_DEVICE(0x2646, 0x2262),   /* KINGSTON SKC2000 NVMe SSD */
3264                .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3265        { PCI_DEVICE(0x2646, 0x2263),   /* KINGSTON A2000 NVMe SSD  */
3266                .driver_data = NVME_QUIRK_NO_DEEPEST_PS, },
3267        { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0061),
3268                .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3269        { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x0065),
3270                .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3271        { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0x8061),
3272                .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3273        { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd00),
3274                .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3275        { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd01),
3276                .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3277        { PCI_DEVICE(PCI_VENDOR_ID_AMAZON, 0xcd02),
3278                .driver_data = NVME_QUIRK_DMA_ADDRESS_BITS_48, },
3279        { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2001),
3280                .driver_data = NVME_QUIRK_SINGLE_VECTOR },
3281        { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2003) },
3282        { PCI_DEVICE(PCI_VENDOR_ID_APPLE, 0x2005),
3283                .driver_data = NVME_QUIRK_SINGLE_VECTOR |
3284                                NVME_QUIRK_128_BYTES_SQES |
3285                                NVME_QUIRK_SHARED_TAGS },
3286
3287        { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
3288        { 0, }
3289};
3290MODULE_DEVICE_TABLE(pci, nvme_id_table);
3291
3292static struct pci_driver nvme_driver = {
3293        .name           = "nvme",
3294        .id_table       = nvme_id_table,
3295        .probe          = nvme_probe,
3296        .remove         = nvme_remove,
3297        .shutdown       = nvme_shutdown,
3298#ifdef CONFIG_PM_SLEEP
3299        .driver         = {
3300                .pm     = &nvme_dev_pm_ops,
3301        },
3302#endif
3303        .sriov_configure = pci_sriov_configure_simple,
3304        .err_handler    = &nvme_err_handler,
3305};
3306
3307static int __init nvme_init(void)
3308{
3309        BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
3310        BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
3311        BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
3312        BUILD_BUG_ON(IRQ_AFFINITY_MAX_SETS < 2);
3313
3314        return pci_register_driver(&nvme_driver);
3315}
3316
3317static void __exit nvme_exit(void)
3318{
3319        pci_unregister_driver(&nvme_driver);
3320        flush_workqueue(nvme_wq);
3321}
3322
3323MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3324MODULE_LICENSE("GPL");
3325MODULE_VERSION("1.0");
3326module_init(nvme_init);
3327module_exit(nvme_exit);
3328