linux/drivers/net/wireless/realtek/rtw88/rtw8822c.c
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   1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
   2/* Copyright(c) 2018-2019  Realtek Corporation
   3 */
   4
   5#include <linux/module.h>
   6#include "main.h"
   7#include "coex.h"
   8#include "fw.h"
   9#include "tx.h"
  10#include "rx.h"
  11#include "phy.h"
  12#include "rtw8822c.h"
  13#include "rtw8822c_table.h"
  14#include "mac.h"
  15#include "reg.h"
  16#include "debug.h"
  17#include "util.h"
  18#include "bf.h"
  19#include "efuse.h"
  20
  21#define IQK_DONE_8822C 0xaa
  22
  23static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
  24                                     u8 rx_path, bool is_tx2_path);
  25
  26static void rtw8822ce_efuse_parsing(struct rtw_efuse *efuse,
  27                                    struct rtw8822c_efuse *map)
  28{
  29        ether_addr_copy(efuse->addr, map->e.mac_addr);
  30}
  31
  32static int rtw8822c_read_efuse(struct rtw_dev *rtwdev, u8 *log_map)
  33{
  34        struct rtw_efuse *efuse = &rtwdev->efuse;
  35        struct rtw8822c_efuse *map;
  36        int i;
  37
  38        map = (struct rtw8822c_efuse *)log_map;
  39
  40        efuse->rfe_option = map->rfe_option;
  41        efuse->rf_board_option = map->rf_board_option;
  42        efuse->crystal_cap = map->xtal_k & XCAP_MASK;
  43        efuse->channel_plan = map->channel_plan;
  44        efuse->country_code[0] = map->country_code[0];
  45        efuse->country_code[1] = map->country_code[1];
  46        efuse->bt_setting = map->rf_bt_setting;
  47        efuse->regd = map->rf_board_option & 0x7;
  48        efuse->thermal_meter[RF_PATH_A] = map->path_a_thermal;
  49        efuse->thermal_meter[RF_PATH_B] = map->path_b_thermal;
  50        efuse->thermal_meter_k =
  51                        (map->path_a_thermal + map->path_b_thermal) >> 1;
  52        efuse->power_track_type = (map->tx_pwr_calibrate_rate >> 4) & 0xf;
  53
  54        for (i = 0; i < 4; i++)
  55                efuse->txpwr_idx_table[i] = map->txpwr_idx_table[i];
  56
  57        switch (rtw_hci_type(rtwdev)) {
  58        case RTW_HCI_TYPE_PCIE:
  59                rtw8822ce_efuse_parsing(efuse, map);
  60                break;
  61        default:
  62                /* unsupported now */
  63                return -ENOTSUPP;
  64        }
  65
  66        return 0;
  67}
  68
  69static void rtw8822c_header_file_init(struct rtw_dev *rtwdev, bool pre)
  70{
  71        rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
  72        rtw_write32_set(rtwdev, REG_3WIRE, BIT_3WIRE_PI_ON);
  73        rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_TX_EN | BIT_3WIRE_RX_EN);
  74        rtw_write32_set(rtwdev, REG_3WIRE2, BIT_3WIRE_PI_ON);
  75
  76        if (pre)
  77                rtw_write32_clr(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
  78        else
  79                rtw_write32_set(rtwdev, REG_ENCCK, BIT_CCK_OFDM_BLK_EN);
  80}
  81
  82static void rtw8822c_bb_reset(struct rtw_dev *rtwdev)
  83{
  84        rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
  85        rtw_write16_clr(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
  86        rtw_write16_set(rtwdev, REG_SYS_FUNC_EN, BIT_FEN_BB_RSTB);
  87}
  88
  89static void rtw8822c_dac_backup_reg(struct rtw_dev *rtwdev,
  90                                    struct rtw_backup_info *backup,
  91                                    struct rtw_backup_info *backup_rf)
  92{
  93        u32 path, i;
  94        u32 val;
  95        u32 reg;
  96        u32 rf_addr[DACK_RF_8822C] = {0x8f};
  97        u32 addrs[DACK_REG_8822C] = {0x180c, 0x1810, 0x410c, 0x4110,
  98                                     0x1c3c, 0x1c24, 0x1d70, 0x9b4,
  99                                     0x1a00, 0x1a14, 0x1d58, 0x1c38,
 100                                     0x1e24, 0x1e28, 0x1860, 0x4160};
 101
 102        for (i = 0; i < DACK_REG_8822C; i++) {
 103                backup[i].len = 4;
 104                backup[i].reg = addrs[i];
 105                backup[i].val = rtw_read32(rtwdev, addrs[i]);
 106        }
 107
 108        for (path = 0; path < DACK_PATH_8822C; path++) {
 109                for (i = 0; i < DACK_RF_8822C; i++) {
 110                        reg = rf_addr[i];
 111                        val = rtw_read_rf(rtwdev, path, reg, RFREG_MASK);
 112                        backup_rf[path * i + i].reg = reg;
 113                        backup_rf[path * i + i].val = val;
 114                }
 115        }
 116}
 117
 118static void rtw8822c_dac_restore_reg(struct rtw_dev *rtwdev,
 119                                     struct rtw_backup_info *backup,
 120                                     struct rtw_backup_info *backup_rf)
 121{
 122        u32 path, i;
 123        u32 val;
 124        u32 reg;
 125
 126        rtw_restore_reg(rtwdev, backup, DACK_REG_8822C);
 127
 128        for (path = 0; path < DACK_PATH_8822C; path++) {
 129                for (i = 0; i < DACK_RF_8822C; i++) {
 130                        val = backup_rf[path * i + i].val;
 131                        reg = backup_rf[path * i + i].reg;
 132                        rtw_write_rf(rtwdev, path, reg, RFREG_MASK, val);
 133                }
 134        }
 135}
 136
 137static void rtw8822c_rf_minmax_cmp(struct rtw_dev *rtwdev, u32 value,
 138                                   u32 *min, u32 *max)
 139{
 140        if (value >= 0x200) {
 141                if (*min >= 0x200) {
 142                        if (*min > value)
 143                                *min = value;
 144                } else {
 145                        *min = value;
 146                }
 147                if (*max >= 0x200) {
 148                        if (*max < value)
 149                                *max = value;
 150                }
 151        } else {
 152                if (*min < 0x200) {
 153                        if (*min > value)
 154                                *min = value;
 155                }
 156
 157                if (*max  >= 0x200) {
 158                        *max = value;
 159                } else {
 160                        if (*max < value)
 161                                *max = value;
 162                }
 163        }
 164}
 165
 166static void __rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *v1, u32 *v2)
 167{
 168        if (*v1 >= 0x200 && *v2 >= 0x200) {
 169                if (*v1 > *v2)
 170                        swap(*v1, *v2);
 171        } else if (*v1 < 0x200 && *v2 < 0x200) {
 172                if (*v1 > *v2)
 173                        swap(*v1, *v2);
 174        } else if (*v1 < 0x200 && *v2 >= 0x200) {
 175                swap(*v1, *v2);
 176        }
 177}
 178
 179static void rtw8822c_dac_iq_sort(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
 180{
 181        u32 i, j;
 182
 183        for (i = 0; i < DACK_SN_8822C - 1; i++) {
 184                for (j = 0; j < (DACK_SN_8822C - 1 - i) ; j++) {
 185                        __rtw8822c_dac_iq_sort(rtwdev, &iv[j], &iv[j + 1]);
 186                        __rtw8822c_dac_iq_sort(rtwdev, &qv[j], &qv[j + 1]);
 187                }
 188        }
 189}
 190
 191static void rtw8822c_dac_iq_offset(struct rtw_dev *rtwdev, u32 *vec, u32 *val)
 192{
 193        u32 p, m, t, i;
 194
 195        m = 0;
 196        p = 0;
 197        for (i = 10; i < DACK_SN_8822C - 10; i++) {
 198                if (vec[i] > 0x200)
 199                        m = (0x400 - vec[i]) + m;
 200                else
 201                        p = vec[i] + p;
 202        }
 203
 204        if (p > m) {
 205                t = p - m;
 206                t = t / (DACK_SN_8822C - 20);
 207        } else {
 208                t = m - p;
 209                t = t / (DACK_SN_8822C - 20);
 210                if (t != 0x0)
 211                        t = 0x400 - t;
 212        }
 213
 214        *val = t;
 215}
 216
 217static u32 rtw8822c_get_path_write_addr(u8 path)
 218{
 219        u32 base_addr;
 220
 221        switch (path) {
 222        case RF_PATH_A:
 223                base_addr = 0x1800;
 224                break;
 225        case RF_PATH_B:
 226                base_addr = 0x4100;
 227                break;
 228        default:
 229                WARN_ON(1);
 230                return -1;
 231        }
 232
 233        return base_addr;
 234}
 235
 236static u32 rtw8822c_get_path_read_addr(u8 path)
 237{
 238        u32 base_addr;
 239
 240        switch (path) {
 241        case RF_PATH_A:
 242                base_addr = 0x2800;
 243                break;
 244        case RF_PATH_B:
 245                base_addr = 0x4500;
 246                break;
 247        default:
 248                WARN_ON(1);
 249                return -1;
 250        }
 251
 252        return base_addr;
 253}
 254
 255static bool rtw8822c_dac_iq_check(struct rtw_dev *rtwdev, u32 value)
 256{
 257        bool ret = true;
 258
 259        if ((value >= 0x200 && (0x400 - value) > 0x64) ||
 260            (value < 0x200 && value > 0x64)) {
 261                ret = false;
 262                rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] Error overflow\n");
 263        }
 264
 265        return ret;
 266}
 267
 268static void rtw8822c_dac_cal_iq_sample(struct rtw_dev *rtwdev, u32 *iv, u32 *qv)
 269{
 270        u32 temp;
 271        int i = 0, cnt = 0;
 272
 273        while (i < DACK_SN_8822C && cnt < 10000) {
 274                cnt++;
 275                temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
 276                iv[i] = (temp & 0x3ff000) >> 12;
 277                qv[i] = temp & 0x3ff;
 278
 279                if (rtw8822c_dac_iq_check(rtwdev, iv[i]) &&
 280                    rtw8822c_dac_iq_check(rtwdev, qv[i]))
 281                        i++;
 282        }
 283}
 284
 285static void rtw8822c_dac_cal_iq_search(struct rtw_dev *rtwdev,
 286                                       u32 *iv, u32 *qv,
 287                                       u32 *i_value, u32 *q_value)
 288{
 289        u32 i_max = 0, q_max = 0, i_min = 0, q_min = 0;
 290        u32 i_delta, q_delta;
 291        u32 temp;
 292        int i, cnt = 0;
 293
 294        do {
 295                i_min = iv[0];
 296                i_max = iv[0];
 297                q_min = qv[0];
 298                q_max = qv[0];
 299                for (i = 0; i < DACK_SN_8822C; i++) {
 300                        rtw8822c_rf_minmax_cmp(rtwdev, iv[i], &i_min, &i_max);
 301                        rtw8822c_rf_minmax_cmp(rtwdev, qv[i], &q_min, &q_max);
 302                }
 303
 304                if (i_max < 0x200 && i_min < 0x200)
 305                        i_delta = i_max - i_min;
 306                else if (i_max >= 0x200 && i_min >= 0x200)
 307                        i_delta = i_max - i_min;
 308                else
 309                        i_delta = i_max + (0x400 - i_min);
 310
 311                if (q_max < 0x200 && q_min < 0x200)
 312                        q_delta = q_max - q_min;
 313                else if (q_max >= 0x200 && q_min >= 0x200)
 314                        q_delta = q_max - q_min;
 315                else
 316                        q_delta = q_max + (0x400 - q_min);
 317
 318                rtw_dbg(rtwdev, RTW_DBG_RFK,
 319                        "[DACK] i: min=0x%08x, max=0x%08x, delta=0x%08x\n",
 320                        i_min, i_max, i_delta);
 321                rtw_dbg(rtwdev, RTW_DBG_RFK,
 322                        "[DACK] q: min=0x%08x, max=0x%08x, delta=0x%08x\n",
 323                        q_min, q_max, q_delta);
 324
 325                rtw8822c_dac_iq_sort(rtwdev, iv, qv);
 326
 327                if (i_delta > 5 || q_delta > 5) {
 328                        temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
 329                        iv[0] = (temp & 0x3ff000) >> 12;
 330                        qv[0] = temp & 0x3ff;
 331                        temp = rtw_read32_mask(rtwdev, 0x2dbc, 0x3fffff);
 332                        iv[DACK_SN_8822C - 1] = (temp & 0x3ff000) >> 12;
 333                        qv[DACK_SN_8822C - 1] = temp & 0x3ff;
 334                } else {
 335                        break;
 336                }
 337        } while (cnt++ < 100);
 338
 339        rtw8822c_dac_iq_offset(rtwdev, iv, i_value);
 340        rtw8822c_dac_iq_offset(rtwdev, qv, q_value);
 341}
 342
 343static void rtw8822c_dac_cal_rf_mode(struct rtw_dev *rtwdev,
 344                                     u32 *i_value, u32 *q_value)
 345{
 346        u32 iv[DACK_SN_8822C], qv[DACK_SN_8822C];
 347        u32 rf_a, rf_b;
 348
 349        rf_a = rtw_read_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK);
 350        rf_b = rtw_read_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK);
 351
 352        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-A=0x%05x\n", rf_a);
 353        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] RF path-B=0x%05x\n", rf_b);
 354
 355        rtw8822c_dac_cal_iq_sample(rtwdev, iv, qv);
 356        rtw8822c_dac_cal_iq_search(rtwdev, iv, qv, i_value, q_value);
 357}
 358
 359static void rtw8822c_dac_bb_setting(struct rtw_dev *rtwdev)
 360{
 361        rtw_write32_mask(rtwdev, 0x1d58, 0xff8, 0x1ff);
 362        rtw_write32_mask(rtwdev, 0x1a00, 0x3, 0x2);
 363        rtw_write32_mask(rtwdev, 0x1a14, 0x300, 0x3);
 364        rtw_write32(rtwdev, 0x1d70, 0x7e7e7e7e);
 365        rtw_write32_mask(rtwdev, 0x180c, 0x3, 0x0);
 366        rtw_write32_mask(rtwdev, 0x410c, 0x3, 0x0);
 367        rtw_write32(rtwdev, 0x1b00, 0x00000008);
 368        rtw_write8(rtwdev, 0x1bcc, 0x3f);
 369        rtw_write32(rtwdev, 0x1b00, 0x0000000a);
 370        rtw_write8(rtwdev, 0x1bcc, 0x3f);
 371        rtw_write32_mask(rtwdev, 0x1e24, BIT(31), 0x0);
 372        rtw_write32_mask(rtwdev, 0x1e28, 0xf, 0x3);
 373}
 374
 375static void rtw8822c_dac_cal_adc(struct rtw_dev *rtwdev,
 376                                 u8 path, u32 *adc_ic, u32 *adc_qc)
 377{
 378        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 379        u32 ic = 0, qc = 0, temp = 0;
 380        u32 base_addr;
 381        u32 path_sel;
 382        int i;
 383
 384        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK path(%d)\n", path);
 385
 386        base_addr = rtw8822c_get_path_write_addr(path);
 387        switch (path) {
 388        case RF_PATH_A:
 389                path_sel = 0xa0000;
 390                break;
 391        case RF_PATH_B:
 392                path_sel = 0x80000;
 393                break;
 394        default:
 395                WARN_ON(1);
 396                return;
 397        }
 398
 399        /* ADCK step1 */
 400        rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x0);
 401        if (path == RF_PATH_B)
 402                rtw_write32(rtwdev, base_addr + 0x30, 0x30db8041);
 403        rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
 404        rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
 405        rtw_write32(rtwdev, base_addr + 0x10, 0x02dd08c4);
 406        rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
 407        rtw_write_rf(rtwdev, RF_PATH_A, 0x0, RFREG_MASK, 0x10000);
 408        rtw_write_rf(rtwdev, RF_PATH_B, 0x0, RFREG_MASK, 0x10000);
 409        for (i = 0; i < 10; i++) {
 410                rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK count=%d\n", i);
 411                rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8003);
 412                rtw_write32(rtwdev, 0x1c24, 0x00010002);
 413                rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
 414                rtw_dbg(rtwdev, RTW_DBG_RFK,
 415                        "[DACK] before: i=0x%x, q=0x%x\n", ic, qc);
 416
 417                /* compensation value */
 418                if (ic != 0x0) {
 419                        ic = 0x400 - ic;
 420                        *adc_ic = ic;
 421                }
 422                if (qc != 0x0) {
 423                        qc = 0x400 - qc;
 424                        *adc_qc = qc;
 425                }
 426                temp = (ic & 0x3ff) | ((qc & 0x3ff) << 10);
 427                rtw_write32(rtwdev, base_addr + 0x68, temp);
 428                dm_info->dack_adck[path] = temp;
 429                rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] ADCK 0x%08x=0x08%x\n",
 430                        base_addr + 0x68, temp);
 431                /* check ADC DC offset */
 432                rtw_write32(rtwdev, 0x1c3c, path_sel + 0x8103);
 433                rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
 434                rtw_dbg(rtwdev, RTW_DBG_RFK,
 435                        "[DACK] after:  i=0x%08x, q=0x%08x\n", ic, qc);
 436                if (ic >= 0x200)
 437                        ic = 0x400 - ic;
 438                if (qc >= 0x200)
 439                        qc = 0x400 - qc;
 440                if (ic < 5 && qc < 5)
 441                        break;
 442        }
 443
 444        /* ADCK step2 */
 445        rtw_write32(rtwdev, 0x1c3c, 0x00000003);
 446        rtw_write32(rtwdev, base_addr + 0x0c, 0x10000260);
 447        rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
 448
 449        /* release pull low switch on IQ path */
 450        rtw_write_rf(rtwdev, path, 0x8f, BIT(13), 0x1);
 451}
 452
 453static void rtw8822c_dac_cal_step1(struct rtw_dev *rtwdev, u8 path)
 454{
 455        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 456        u32 base_addr;
 457        u32 read_addr;
 458
 459        base_addr = rtw8822c_get_path_write_addr(path);
 460        read_addr = rtw8822c_get_path_read_addr(path);
 461
 462        rtw_write32(rtwdev, base_addr + 0x68, dm_info->dack_adck[path]);
 463        rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
 464        if (path == RF_PATH_A) {
 465                rtw_write32(rtwdev, base_addr + 0x60, 0xf0040ff0);
 466                rtw_write32(rtwdev, 0x1c38, 0xffffffff);
 467        }
 468        rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
 469        rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
 470        rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
 471        rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff81);
 472        rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
 473        rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
 474        rtw_write32(rtwdev, base_addr + 0xd8, 0x0008ff81);
 475        rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
 476        rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
 477        mdelay(2);
 478        rtw_write32(rtwdev, base_addr + 0xbc, 0x000aff8d);
 479        mdelay(2);
 480        rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
 481        rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
 482        mdelay(1);
 483        rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
 484        rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
 485        mdelay(20);
 486        if (!check_hw_ready(rtwdev, read_addr + 0x08, 0x7fff80, 0xffff) ||
 487            !check_hw_ready(rtwdev, read_addr + 0x34, 0x7fff80, 0xffff))
 488                rtw_err(rtwdev, "failed to wait for dack ready\n");
 489        rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
 490        mdelay(1);
 491        rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
 492        rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
 493        rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
 494        rtw_write32(rtwdev, base_addr + 0xbc, 0x0008ff87);
 495        rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
 496}
 497
 498static void rtw8822c_dac_cal_step2(struct rtw_dev *rtwdev,
 499                                   u8 path, u32 *ic_out, u32 *qc_out)
 500{
 501        u32 base_addr;
 502        u32 ic, qc, ic_in, qc_in;
 503
 504        base_addr = rtw8822c_get_path_write_addr(path);
 505        rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, 0x0);
 506        rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, 0x8);
 507        rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, 0x0);
 508        rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, 0x8);
 509
 510        rtw_write32(rtwdev, 0x1b00, 0x00000008);
 511        rtw_write8(rtwdev, 0x1bcc, 0x03f);
 512        rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
 513        rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
 514        rtw_write32(rtwdev, 0x1c3c, 0x00088103);
 515
 516        rtw8822c_dac_cal_rf_mode(rtwdev, &ic_in, &qc_in);
 517        ic = ic_in;
 518        qc = qc_in;
 519
 520        /* compensation value */
 521        if (ic != 0x0)
 522                ic = 0x400 - ic;
 523        if (qc != 0x0)
 524                qc = 0x400 - qc;
 525        if (ic < 0x300) {
 526                ic = ic * 2 * 6 / 5;
 527                ic = ic + 0x80;
 528        } else {
 529                ic = (0x400 - ic) * 2 * 6 / 5;
 530                ic = 0x7f - ic;
 531        }
 532        if (qc < 0x300) {
 533                qc = qc * 2 * 6 / 5;
 534                qc = qc + 0x80;
 535        } else {
 536                qc = (0x400 - qc) * 2 * 6 / 5;
 537                qc = 0x7f - qc;
 538        }
 539
 540        *ic_out = ic;
 541        *qc_out = qc;
 542
 543        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] before i=0x%x, q=0x%x\n", ic_in, qc_in);
 544        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] after  i=0x%x, q=0x%x\n", ic, qc);
 545}
 546
 547static void rtw8822c_dac_cal_step3(struct rtw_dev *rtwdev, u8 path,
 548                                   u32 adc_ic, u32 adc_qc,
 549                                   u32 *ic_in, u32 *qc_in,
 550                                   u32 *i_out, u32 *q_out)
 551{
 552        u32 base_addr;
 553        u32 read_addr;
 554        u32 ic, qc;
 555        u32 temp;
 556
 557        base_addr = rtw8822c_get_path_write_addr(path);
 558        read_addr = rtw8822c_get_path_read_addr(path);
 559        ic = *ic_in;
 560        qc = *qc_in;
 561
 562        rtw_write32(rtwdev, base_addr + 0x0c, 0xdff00220);
 563        rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
 564        rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
 565        rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb88);
 566        rtw_write32(rtwdev, base_addr + 0xbc, 0xc008ff81);
 567        rtw_write32(rtwdev, base_addr + 0xc0, 0x0003d208);
 568        rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xf0000000, ic & 0xf);
 569        rtw_write32_mask(rtwdev, base_addr + 0xc0, 0xf, (ic & 0xf0) >> 4);
 570        rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb88);
 571        rtw_write32(rtwdev, base_addr + 0xd8, 0xe008ff81);
 572        rtw_write32(rtwdev, base_addr + 0xdc, 0x0003d208);
 573        rtw_write32_mask(rtwdev, base_addr + 0xd8, 0xf0000000, qc & 0xf);
 574        rtw_write32_mask(rtwdev, base_addr + 0xdc, 0xf, (qc & 0xf0) >> 4);
 575        rtw_write32(rtwdev, base_addr + 0xb8, 0x60000000);
 576        mdelay(2);
 577        rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x6);
 578        mdelay(2);
 579        rtw_write32(rtwdev, base_addr + 0xb0, 0x0a11fb89);
 580        rtw_write32(rtwdev, base_addr + 0xcc, 0x0a11fb89);
 581        mdelay(1);
 582        rtw_write32(rtwdev, base_addr + 0xb8, 0x62000000);
 583        rtw_write32(rtwdev, base_addr + 0xd4, 0x62000000);
 584        mdelay(20);
 585        if (!check_hw_ready(rtwdev, read_addr + 0x24, 0x07f80000, ic) ||
 586            !check_hw_ready(rtwdev, read_addr + 0x50, 0x07f80000, qc))
 587                rtw_err(rtwdev, "failed to write IQ vector to hardware\n");
 588        rtw_write32(rtwdev, base_addr + 0xb8, 0x02000000);
 589        mdelay(1);
 590        rtw_write32_mask(rtwdev, base_addr + 0xbc, 0xe, 0x3);
 591        rtw_write32(rtwdev, 0x9b4, 0xdb6db600);
 592
 593        /* check DAC DC offset */
 594        temp = ((adc_ic + 0x10) & 0x3ff) | (((adc_qc + 0x10) & 0x3ff) << 10);
 595        rtw_write32(rtwdev, base_addr + 0x68, temp);
 596        rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c5);
 597        rtw_write32(rtwdev, base_addr + 0x60, 0xf0000000);
 598        rtw8822c_dac_cal_rf_mode(rtwdev, &ic, &qc);
 599        if (ic >= 0x10)
 600                ic = ic - 0x10;
 601        else
 602                ic = 0x400 - (0x10 - ic);
 603
 604        if (qc >= 0x10)
 605                qc = qc - 0x10;
 606        else
 607                qc = 0x400 - (0x10 - qc);
 608
 609        *i_out = ic;
 610        *q_out = qc;
 611
 612        if (ic >= 0x200)
 613                ic = 0x400 - ic;
 614        if (qc >= 0x200)
 615                qc = 0x400 - qc;
 616
 617        *ic_in = ic;
 618        *qc_in = qc;
 619
 620        rtw_dbg(rtwdev, RTW_DBG_RFK,
 621                "[DACK] after  DACK i=0x%x, q=0x%x\n", *i_out, *q_out);
 622}
 623
 624static void rtw8822c_dac_cal_step4(struct rtw_dev *rtwdev, u8 path)
 625{
 626        u32 base_addr = rtw8822c_get_path_write_addr(path);
 627
 628        rtw_write32(rtwdev, base_addr + 0x68, 0x0);
 629        rtw_write32(rtwdev, base_addr + 0x10, 0x02d508c4);
 630        rtw_write32_mask(rtwdev, base_addr + 0xbc, 0x1, 0x0);
 631        rtw_write32_mask(rtwdev, base_addr + 0x30, BIT(30), 0x1);
 632}
 633
 634static void rtw8822c_dac_cal_backup_vec(struct rtw_dev *rtwdev,
 635                                        u8 path, u8 vec, u32 w_addr, u32 r_addr)
 636{
 637        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 638        u16 val;
 639        u32 i;
 640
 641        if (WARN_ON(vec >= 2))
 642                return;
 643
 644        for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
 645                rtw_write32_mask(rtwdev, w_addr, 0xf0000000, i);
 646                val = (u16)rtw_read32_mask(rtwdev, r_addr, 0x7fc0000);
 647                dm_info->dack_msbk[path][vec][i] = val;
 648        }
 649}
 650
 651static void rtw8822c_dac_cal_backup_path(struct rtw_dev *rtwdev, u8 path)
 652{
 653        u32 w_off = 0x1c;
 654        u32 r_off = 0x2c;
 655        u32 w_addr, r_addr;
 656
 657        if (WARN_ON(path >= 2))
 658                return;
 659
 660        /* backup I vector */
 661        w_addr = rtw8822c_get_path_write_addr(path) + 0xb0;
 662        r_addr = rtw8822c_get_path_read_addr(path) + 0x10;
 663        rtw8822c_dac_cal_backup_vec(rtwdev, path, 0, w_addr, r_addr);
 664
 665        /* backup Q vector */
 666        w_addr = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
 667        r_addr = rtw8822c_get_path_read_addr(path) + 0x10 + r_off;
 668        rtw8822c_dac_cal_backup_vec(rtwdev, path, 1, w_addr, r_addr);
 669}
 670
 671static void rtw8822c_dac_cal_backup_dck(struct rtw_dev *rtwdev)
 672{
 673        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 674        u8 val;
 675
 676        val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000);
 677        dm_info->dack_dck[RF_PATH_A][0][0] = val;
 678        val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_I_1, 0xf);
 679        dm_info->dack_dck[RF_PATH_A][0][1] = val;
 680        val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000);
 681        dm_info->dack_dck[RF_PATH_A][1][0] = val;
 682        val = (u8)rtw_read32_mask(rtwdev, REG_DCKA_Q_1, 0xf);
 683        dm_info->dack_dck[RF_PATH_A][1][1] = val;
 684
 685        val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000);
 686        dm_info->dack_dck[RF_PATH_B][0][0] = val;
 687        val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_I_1, 0xf);
 688        dm_info->dack_dck[RF_PATH_B][1][0] = val;
 689        val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000);
 690        dm_info->dack_dck[RF_PATH_B][0][1] = val;
 691        val = (u8)rtw_read32_mask(rtwdev, REG_DCKB_Q_1, 0xf);
 692        dm_info->dack_dck[RF_PATH_B][1][1] = val;
 693}
 694
 695static void rtw8822c_dac_cal_backup(struct rtw_dev *rtwdev)
 696{
 697        u32 temp[3];
 698
 699        temp[0] = rtw_read32(rtwdev, 0x1860);
 700        temp[1] = rtw_read32(rtwdev, 0x4160);
 701        temp[2] = rtw_read32(rtwdev, 0x9b4);
 702
 703        /* set clock */
 704        rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
 705
 706        /* backup path-A I/Q */
 707        rtw_write32_clr(rtwdev, 0x1830, BIT(30));
 708        rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
 709        rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_A);
 710
 711        /* backup path-B I/Q */
 712        rtw_write32_clr(rtwdev, 0x4130, BIT(30));
 713        rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
 714        rtw8822c_dac_cal_backup_path(rtwdev, RF_PATH_B);
 715
 716        rtw8822c_dac_cal_backup_dck(rtwdev);
 717        rtw_write32_set(rtwdev, 0x1830, BIT(30));
 718        rtw_write32_set(rtwdev, 0x4130, BIT(30));
 719
 720        rtw_write32(rtwdev, 0x1860, temp[0]);
 721        rtw_write32(rtwdev, 0x4160, temp[1]);
 722        rtw_write32(rtwdev, 0x9b4, temp[2]);
 723}
 724
 725static void rtw8822c_dac_cal_restore_dck(struct rtw_dev *rtwdev)
 726{
 727        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 728        u8 val;
 729
 730        rtw_write32_set(rtwdev, REG_DCKA_I_0, BIT(19));
 731        val = dm_info->dack_dck[RF_PATH_A][0][0];
 732        rtw_write32_mask(rtwdev, REG_DCKA_I_0, 0xf0000000, val);
 733        val = dm_info->dack_dck[RF_PATH_A][0][1];
 734        rtw_write32_mask(rtwdev, REG_DCKA_I_1, 0xf, val);
 735
 736        rtw_write32_set(rtwdev, REG_DCKA_Q_0, BIT(19));
 737        val = dm_info->dack_dck[RF_PATH_A][1][0];
 738        rtw_write32_mask(rtwdev, REG_DCKA_Q_0, 0xf0000000, val);
 739        val = dm_info->dack_dck[RF_PATH_A][1][1];
 740        rtw_write32_mask(rtwdev, REG_DCKA_Q_1, 0xf, val);
 741
 742        rtw_write32_set(rtwdev, REG_DCKB_I_0, BIT(19));
 743        val = dm_info->dack_dck[RF_PATH_B][0][0];
 744        rtw_write32_mask(rtwdev, REG_DCKB_I_0, 0xf0000000, val);
 745        val = dm_info->dack_dck[RF_PATH_B][0][1];
 746        rtw_write32_mask(rtwdev, REG_DCKB_I_1, 0xf, val);
 747
 748        rtw_write32_set(rtwdev, REG_DCKB_Q_0, BIT(19));
 749        val = dm_info->dack_dck[RF_PATH_B][1][0];
 750        rtw_write32_mask(rtwdev, REG_DCKB_Q_0, 0xf0000000, val);
 751        val = dm_info->dack_dck[RF_PATH_B][1][1];
 752        rtw_write32_mask(rtwdev, REG_DCKB_Q_1, 0xf, val);
 753}
 754
 755static void rtw8822c_dac_cal_restore_prepare(struct rtw_dev *rtwdev)
 756{
 757        rtw_write32(rtwdev, 0x9b4, 0xdb66db00);
 758
 759        rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x0);
 760        rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x0);
 761        rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x0);
 762        rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x0);
 763
 764        rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x0);
 765        rtw_write32_mask(rtwdev, 0x1860, 0xfc000000, 0x3c);
 766        rtw_write32_mask(rtwdev, 0x18b4, BIT(0), 0x1);
 767        rtw_write32_mask(rtwdev, 0x18d0, BIT(0), 0x1);
 768
 769        rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x0);
 770        rtw_write32_mask(rtwdev, 0x4160, 0xfc000000, 0x3c);
 771        rtw_write32_mask(rtwdev, 0x41b4, BIT(0), 0x1);
 772        rtw_write32_mask(rtwdev, 0x41d0, BIT(0), 0x1);
 773
 774        rtw_write32_mask(rtwdev, 0x18b0, 0xf00, 0x0);
 775        rtw_write32_mask(rtwdev, 0x18c0, BIT(14), 0x0);
 776        rtw_write32_mask(rtwdev, 0x18cc, 0xf00, 0x0);
 777        rtw_write32_mask(rtwdev, 0x18dc, BIT(14), 0x0);
 778
 779        rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x0);
 780        rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x0);
 781        rtw_write32_mask(rtwdev, 0x18b0, BIT(0), 0x1);
 782        rtw_write32_mask(rtwdev, 0x18cc, BIT(0), 0x1);
 783
 784        rtw8822c_dac_cal_restore_dck(rtwdev);
 785
 786        rtw_write32_mask(rtwdev, 0x18c0, 0x38000, 0x7);
 787        rtw_write32_mask(rtwdev, 0x18dc, 0x38000, 0x7);
 788        rtw_write32_mask(rtwdev, 0x41c0, 0x38000, 0x7);
 789        rtw_write32_mask(rtwdev, 0x41dc, 0x38000, 0x7);
 790
 791        rtw_write32_mask(rtwdev, 0x18b8, BIT(26) | BIT(25), 0x1);
 792        rtw_write32_mask(rtwdev, 0x18d4, BIT(26) | BIT(25), 0x1);
 793
 794        rtw_write32_mask(rtwdev, 0x41b0, 0xf00, 0x0);
 795        rtw_write32_mask(rtwdev, 0x41c0, BIT(14), 0x0);
 796        rtw_write32_mask(rtwdev, 0x41cc, 0xf00, 0x0);
 797        rtw_write32_mask(rtwdev, 0x41dc, BIT(14), 0x0);
 798
 799        rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x0);
 800        rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x0);
 801        rtw_write32_mask(rtwdev, 0x41b0, BIT(0), 0x1);
 802        rtw_write32_mask(rtwdev, 0x41cc, BIT(0), 0x1);
 803
 804        rtw_write32_mask(rtwdev, 0x41b8, BIT(26) | BIT(25), 0x1);
 805        rtw_write32_mask(rtwdev, 0x41d4, BIT(26) | BIT(25), 0x1);
 806}
 807
 808static bool rtw8822c_dac_cal_restore_wait(struct rtw_dev *rtwdev,
 809                                          u32 target_addr, u32 toggle_addr)
 810{
 811        u32 cnt = 0;
 812
 813        do {
 814                rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x0);
 815                rtw_write32_mask(rtwdev, toggle_addr, BIT(26) | BIT(25), 0x2);
 816
 817                if (rtw_read32_mask(rtwdev, target_addr, 0xf) == 0x6)
 818                        return true;
 819
 820        } while (cnt++ < 100);
 821
 822        return false;
 823}
 824
 825static bool rtw8822c_dac_cal_restore_path(struct rtw_dev *rtwdev, u8 path)
 826{
 827        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 828        u32 w_off = 0x1c;
 829        u32 r_off = 0x2c;
 830        u32 w_i, r_i, w_q, r_q;
 831        u32 value;
 832        u32 i;
 833
 834        w_i = rtw8822c_get_path_write_addr(path) + 0xb0;
 835        r_i = rtw8822c_get_path_read_addr(path) + 0x08;
 836        w_q = rtw8822c_get_path_write_addr(path) + 0xb0 + w_off;
 837        r_q = rtw8822c_get_path_read_addr(path) + 0x08 + r_off;
 838
 839        if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_i, w_i + 0x8))
 840                return false;
 841
 842        for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
 843                rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
 844                value = dm_info->dack_msbk[path][0][i];
 845                rtw_write32_mask(rtwdev, w_i + 0x4, 0xff8, value);
 846                rtw_write32_mask(rtwdev, w_i, 0xf0000000, i);
 847                rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x1);
 848        }
 849
 850        rtw_write32_mask(rtwdev, w_i + 0x4, BIT(2), 0x0);
 851
 852        if (!rtw8822c_dac_cal_restore_wait(rtwdev, r_q, w_q + 0x8))
 853                return false;
 854
 855        for (i = 0; i < DACK_MSBK_BACKUP_NUM; i++) {
 856                rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
 857                value = dm_info->dack_msbk[path][1][i];
 858                rtw_write32_mask(rtwdev, w_q + 0x4, 0xff8, value);
 859                rtw_write32_mask(rtwdev, w_q, 0xf0000000, i);
 860                rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x1);
 861        }
 862        rtw_write32_mask(rtwdev, w_q + 0x4, BIT(2), 0x0);
 863
 864        rtw_write32_mask(rtwdev, w_i + 0x8, BIT(26) | BIT(25), 0x0);
 865        rtw_write32_mask(rtwdev, w_q + 0x8, BIT(26) | BIT(25), 0x0);
 866        rtw_write32_mask(rtwdev, w_i + 0x4, BIT(0), 0x0);
 867        rtw_write32_mask(rtwdev, w_q + 0x4, BIT(0), 0x0);
 868
 869        return true;
 870}
 871
 872static bool __rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
 873{
 874        if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_A))
 875                return false;
 876
 877        if (!rtw8822c_dac_cal_restore_path(rtwdev, RF_PATH_B))
 878                return false;
 879
 880        return true;
 881}
 882
 883static bool rtw8822c_dac_cal_restore(struct rtw_dev *rtwdev)
 884{
 885        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
 886        u32 temp[3];
 887
 888        /* sample the first element for both path's IQ vector */
 889        if (dm_info->dack_msbk[RF_PATH_A][0][0] == 0 &&
 890            dm_info->dack_msbk[RF_PATH_A][1][0] == 0 &&
 891            dm_info->dack_msbk[RF_PATH_B][0][0] == 0 &&
 892            dm_info->dack_msbk[RF_PATH_B][1][0] == 0)
 893                return false;
 894
 895        temp[0] = rtw_read32(rtwdev, 0x1860);
 896        temp[1] = rtw_read32(rtwdev, 0x4160);
 897        temp[2] = rtw_read32(rtwdev, 0x9b4);
 898
 899        rtw8822c_dac_cal_restore_prepare(rtwdev);
 900        if (!check_hw_ready(rtwdev, 0x2808, 0x7fff80, 0xffff) ||
 901            !check_hw_ready(rtwdev, 0x2834, 0x7fff80, 0xffff) ||
 902            !check_hw_ready(rtwdev, 0x4508, 0x7fff80, 0xffff) ||
 903            !check_hw_ready(rtwdev, 0x4534, 0x7fff80, 0xffff))
 904                return false;
 905
 906        if (!__rtw8822c_dac_cal_restore(rtwdev)) {
 907                rtw_err(rtwdev, "failed to restore dack vectors\n");
 908                return false;
 909        }
 910
 911        rtw_write32_mask(rtwdev, 0x1830, BIT(30), 0x1);
 912        rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
 913        rtw_write32(rtwdev, 0x1860, temp[0]);
 914        rtw_write32(rtwdev, 0x4160, temp[1]);
 915        rtw_write32_mask(rtwdev, 0x18b0, BIT(27), 0x1);
 916        rtw_write32_mask(rtwdev, 0x18cc, BIT(27), 0x1);
 917        rtw_write32_mask(rtwdev, 0x41b0, BIT(27), 0x1);
 918        rtw_write32_mask(rtwdev, 0x41cc, BIT(27), 0x1);
 919        rtw_write32(rtwdev, 0x9b4, temp[2]);
 920
 921        return true;
 922}
 923
 924static void rtw8822c_rf_dac_cal(struct rtw_dev *rtwdev)
 925{
 926        struct rtw_backup_info backup_rf[DACK_RF_8822C * DACK_PATH_8822C];
 927        struct rtw_backup_info backup[DACK_REG_8822C];
 928        u32 ic = 0, qc = 0, i;
 929        u32 i_a = 0x0, q_a = 0x0, i_b = 0x0, q_b = 0x0;
 930        u32 ic_a = 0x0, qc_a = 0x0, ic_b = 0x0, qc_b = 0x0;
 931        u32 adc_ic_a = 0x0, adc_qc_a = 0x0, adc_ic_b = 0x0, adc_qc_b = 0x0;
 932
 933        if (rtw8822c_dac_cal_restore(rtwdev))
 934                return;
 935
 936        /* not able to restore, do it */
 937
 938        rtw8822c_dac_backup_reg(rtwdev, backup, backup_rf);
 939
 940        rtw8822c_dac_bb_setting(rtwdev);
 941
 942        /* path-A */
 943        rtw8822c_dac_cal_adc(rtwdev, RF_PATH_A, &adc_ic_a, &adc_qc_a);
 944        for (i = 0; i < 10; i++) {
 945                rtw8822c_dac_cal_step1(rtwdev, RF_PATH_A);
 946                rtw8822c_dac_cal_step2(rtwdev, RF_PATH_A, &ic, &qc);
 947                ic_a = ic;
 948                qc_a = qc;
 949
 950                rtw8822c_dac_cal_step3(rtwdev, RF_PATH_A, adc_ic_a, adc_qc_a,
 951                                       &ic, &qc, &i_a, &q_a);
 952
 953                if (ic < 5 && qc < 5)
 954                        break;
 955        }
 956        rtw8822c_dac_cal_step4(rtwdev, RF_PATH_A);
 957
 958        /* path-B */
 959        rtw8822c_dac_cal_adc(rtwdev, RF_PATH_B, &adc_ic_b, &adc_qc_b);
 960        for (i = 0; i < 10; i++) {
 961                rtw8822c_dac_cal_step1(rtwdev, RF_PATH_B);
 962                rtw8822c_dac_cal_step2(rtwdev, RF_PATH_B, &ic, &qc);
 963                ic_b = ic;
 964                qc_b = qc;
 965
 966                rtw8822c_dac_cal_step3(rtwdev, RF_PATH_B, adc_ic_b, adc_qc_b,
 967                                       &ic, &qc, &i_b, &q_b);
 968
 969                if (ic < 5 && qc < 5)
 970                        break;
 971        }
 972        rtw8822c_dac_cal_step4(rtwdev, RF_PATH_B);
 973
 974        rtw_write32(rtwdev, 0x1b00, 0x00000008);
 975        rtw_write32_mask(rtwdev, 0x4130, BIT(30), 0x1);
 976        rtw_write8(rtwdev, 0x1bcc, 0x0);
 977        rtw_write32(rtwdev, 0x1b00, 0x0000000a);
 978        rtw_write8(rtwdev, 0x1bcc, 0x0);
 979
 980        rtw8822c_dac_restore_reg(rtwdev, backup, backup_rf);
 981
 982        /* backup results to restore, saving a lot of time */
 983        rtw8822c_dac_cal_backup(rtwdev);
 984
 985        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: ic=0x%x, qc=0x%x\n", ic_a, qc_a);
 986        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: ic=0x%x, qc=0x%x\n", ic_b, qc_b);
 987        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path A: i=0x%x, q=0x%x\n", i_a, q_a);
 988        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DACK] path B: i=0x%x, q=0x%x\n", i_b, q_b);
 989}
 990
 991static void rtw8822c_rf_x2_check(struct rtw_dev *rtwdev)
 992{
 993        u8 x2k_busy;
 994
 995        mdelay(1);
 996        x2k_busy = rtw_read_rf(rtwdev, RF_PATH_A, 0xb8, BIT(15));
 997        if (x2k_busy == 1) {
 998                rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0xC4440);
 999                rtw_write_rf(rtwdev, RF_PATH_A, 0xba, RFREG_MASK, 0x6840D);
1000                rtw_write_rf(rtwdev, RF_PATH_A, 0xb8, RFREG_MASK, 0x80440);
1001                mdelay(1);
1002        }
1003}
1004
1005static void rtw8822c_set_power_trim(struct rtw_dev *rtwdev, s8 bb_gain[2][8])
1006{
1007#define RF_SET_POWER_TRIM(_path, _seq, _idx)                                    \
1008                do {                                                            \
1009                        rtw_write_rf(rtwdev, _path, 0x33, RFREG_MASK, _seq);    \
1010                        rtw_write_rf(rtwdev, _path, 0x3f, RFREG_MASK,           \
1011                                     bb_gain[_path][_idx]);                     \
1012                } while (0)
1013        u8 path;
1014
1015        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1016                rtw_write_rf(rtwdev, path, 0xee, BIT(19), 1);
1017                RF_SET_POWER_TRIM(path, 0x0, 0);
1018                RF_SET_POWER_TRIM(path, 0x1, 1);
1019                RF_SET_POWER_TRIM(path, 0x2, 2);
1020                RF_SET_POWER_TRIM(path, 0x3, 2);
1021                RF_SET_POWER_TRIM(path, 0x4, 3);
1022                RF_SET_POWER_TRIM(path, 0x5, 4);
1023                RF_SET_POWER_TRIM(path, 0x6, 5);
1024                RF_SET_POWER_TRIM(path, 0x7, 6);
1025                RF_SET_POWER_TRIM(path, 0x8, 7);
1026                RF_SET_POWER_TRIM(path, 0x9, 3);
1027                RF_SET_POWER_TRIM(path, 0xa, 4);
1028                RF_SET_POWER_TRIM(path, 0xb, 5);
1029                RF_SET_POWER_TRIM(path, 0xc, 6);
1030                RF_SET_POWER_TRIM(path, 0xd, 7);
1031                RF_SET_POWER_TRIM(path, 0xe, 7);
1032                rtw_write_rf(rtwdev, path, 0xee, BIT(19), 0);
1033        }
1034#undef RF_SET_POWER_TRIM
1035}
1036
1037static void rtw8822c_power_trim(struct rtw_dev *rtwdev)
1038{
1039        u8 pg_pwr = 0xff, i, path, idx;
1040        s8 bb_gain[2][8] = {};
1041        u16 rf_efuse_2g[3] = {PPG_2GL_TXAB, PPG_2GM_TXAB, PPG_2GH_TXAB};
1042        u16 rf_efuse_5g[2][5] = {{PPG_5GL1_TXA, PPG_5GL2_TXA, PPG_5GM1_TXA,
1043                                  PPG_5GM2_TXA, PPG_5GH1_TXA},
1044                                 {PPG_5GL1_TXB, PPG_5GL2_TXB, PPG_5GM1_TXB,
1045                                  PPG_5GM2_TXB, PPG_5GH1_TXB} };
1046        bool set = false;
1047
1048        for (i = 0; i < ARRAY_SIZE(rf_efuse_2g); i++) {
1049                rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[i], &pg_pwr);
1050                if (pg_pwr == EFUSE_READ_FAIL)
1051                        continue;
1052                set = true;
1053                bb_gain[RF_PATH_A][i] = FIELD_GET(PPG_2G_A_MASK, pg_pwr);
1054                bb_gain[RF_PATH_B][i] = FIELD_GET(PPG_2G_B_MASK, pg_pwr);
1055        }
1056
1057        for (i = 0; i < ARRAY_SIZE(rf_efuse_5g[0]); i++) {
1058                for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1059                        rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path][i],
1060                                                 &pg_pwr);
1061                        if (pg_pwr == EFUSE_READ_FAIL)
1062                                continue;
1063                        set = true;
1064                        idx = i + ARRAY_SIZE(rf_efuse_2g);
1065                        bb_gain[path][idx] = FIELD_GET(PPG_5G_MASK, pg_pwr);
1066                }
1067        }
1068        if (set)
1069                rtw8822c_set_power_trim(rtwdev, bb_gain);
1070
1071        rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1072}
1073
1074static void rtw8822c_thermal_trim(struct rtw_dev *rtwdev)
1075{
1076        u16 rf_efuse[2] = {PPG_THERMAL_A, PPG_THERMAL_B};
1077        u8 pg_therm = 0xff, thermal[2] = {0}, path;
1078
1079        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1080                rtw_read8_physical_efuse(rtwdev, rf_efuse[path], &pg_therm);
1081                if (pg_therm == EFUSE_READ_FAIL)
1082                        return;
1083                /* Efuse value of BIT(0) shall be move to BIT(3), and the value
1084                 * of BIT(1) to BIT(3) should be right shifted 1 bit.
1085                 */
1086                thermal[path] = FIELD_GET(GENMASK(3, 1), pg_therm);
1087                thermal[path] |= FIELD_PREP(BIT(3), pg_therm & BIT(0));
1088                rtw_write_rf(rtwdev, path, 0x43, RF_THEMAL_MASK, thermal[path]);
1089        }
1090}
1091
1092static void rtw8822c_pa_bias(struct rtw_dev *rtwdev)
1093{
1094        u16 rf_efuse_2g[2] = {PPG_PABIAS_2GA, PPG_PABIAS_2GB};
1095        u16 rf_efuse_5g[2] = {PPG_PABIAS_5GA, PPG_PABIAS_5GB};
1096        u8 pg_pa_bias = 0xff, path;
1097
1098        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1099                rtw_read8_physical_efuse(rtwdev, rf_efuse_2g[path],
1100                                         &pg_pa_bias);
1101                if (pg_pa_bias == EFUSE_READ_FAIL)
1102                        return;
1103                pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
1104                rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_2G_MASK, pg_pa_bias);
1105        }
1106        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1107                rtw_read8_physical_efuse(rtwdev, rf_efuse_5g[path],
1108                                         &pg_pa_bias);
1109                pg_pa_bias = FIELD_GET(PPG_PABIAS_MASK, pg_pa_bias);
1110                rtw_write_rf(rtwdev, path, RF_PA, RF_PABIAS_5G_MASK, pg_pa_bias);
1111        }
1112}
1113
1114static void rtw8822c_rfk_handshake(struct rtw_dev *rtwdev, bool is_before_k)
1115{
1116        struct rtw_dm_info *dm = &rtwdev->dm_info;
1117        u8 u1b_tmp;
1118        u8 u4b_tmp;
1119        int ret;
1120
1121        if (is_before_k) {
1122                rtw_dbg(rtwdev, RTW_DBG_RFK,
1123                        "[RFK] WiFi / BT RFK handshake start!!\n");
1124
1125                if (!dm->is_bt_iqk_timeout) {
1126                        ret = read_poll_timeout(rtw_read32_mask, u4b_tmp,
1127                                                u4b_tmp == 0, 20, 600000, false,
1128                                                rtwdev, REG_PMC_DBG_CTRL1,
1129                                                BITS_PMC_BT_IQK_STS);
1130                        if (ret) {
1131                                rtw_dbg(rtwdev, RTW_DBG_RFK,
1132                                        "[RFK] Wait BT IQK finish timeout!!\n");
1133                                dm->is_bt_iqk_timeout = true;
1134                        }
1135                }
1136
1137                rtw_fw_inform_rfk_status(rtwdev, true);
1138
1139                ret = read_poll_timeout(rtw_read8_mask, u1b_tmp,
1140                                        u1b_tmp == 1, 20, 100000, false,
1141                                        rtwdev, REG_ARFR4, BIT_WL_RFK);
1142                if (ret)
1143                        rtw_dbg(rtwdev, RTW_DBG_RFK,
1144                                "[RFK] Send WiFi RFK start H2C cmd FAIL!!\n");
1145        } else {
1146                rtw_fw_inform_rfk_status(rtwdev, false);
1147                ret = read_poll_timeout(rtw_read8_mask, u1b_tmp,
1148                                        u1b_tmp == 1, 20, 100000, false,
1149                                        rtwdev, REG_ARFR4,
1150                                        BIT_WL_RFK);
1151                if (ret)
1152                        rtw_dbg(rtwdev, RTW_DBG_RFK,
1153                                "[RFK] Send WiFi RFK finish H2C cmd FAIL!!\n");
1154
1155                rtw_dbg(rtwdev, RTW_DBG_RFK,
1156                        "[RFK] WiFi / BT RFK handshake finish!!\n");
1157        }
1158}
1159
1160static void rtw8822c_rfk_power_save(struct rtw_dev *rtwdev,
1161                                    bool is_power_save)
1162{
1163        u8 path;
1164
1165        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1166                rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1167                rtw_write32_mask(rtwdev, REG_DPD_CTL1_S0, BIT_PS_EN,
1168                                 is_power_save ? 0 : 1);
1169        }
1170}
1171
1172static void rtw8822c_txgapk_backup_bb_reg(struct rtw_dev *rtwdev, const u32 reg[],
1173                                          u32 reg_backup[], u32 reg_num)
1174{
1175        u32 i;
1176
1177        for (i = 0; i < reg_num; i++) {
1178                reg_backup[i] = rtw_read32(rtwdev, reg[i]);
1179
1180                rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Backup BB 0x%x = 0x%x\n",
1181                        reg[i], reg_backup[i]);
1182        }
1183}
1184
1185static void rtw8822c_txgapk_reload_bb_reg(struct rtw_dev *rtwdev,
1186                                          const u32 reg[], u32 reg_backup[],
1187                                          u32 reg_num)
1188{
1189        u32 i;
1190
1191        for (i = 0; i < reg_num; i++) {
1192                rtw_write32(rtwdev, reg[i], reg_backup[i]);
1193                rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Reload BB 0x%x = 0x%x\n",
1194                        reg[i], reg_backup[i]);
1195        }
1196}
1197
1198static bool check_rf_status(struct rtw_dev *rtwdev, u8 status)
1199{
1200        u8 reg_rf0_a, reg_rf0_b;
1201
1202        reg_rf0_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A,
1203                                    RF_MODE_TRXAGC, BIT_RF_MODE);
1204        reg_rf0_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B,
1205                                    RF_MODE_TRXAGC, BIT_RF_MODE);
1206
1207        if (reg_rf0_a == status || reg_rf0_b == status)
1208                return false;
1209
1210        return true;
1211}
1212
1213static void rtw8822c_txgapk_tx_pause(struct rtw_dev *rtwdev)
1214{
1215        bool status;
1216        int ret;
1217
1218        rtw_write8(rtwdev, REG_TXPAUSE, BIT_AC_QUEUE);
1219        rtw_write32_mask(rtwdev, REG_TX_FIFO, BIT_STOP_TX, 0x2);
1220
1221        ret = read_poll_timeout_atomic(check_rf_status, status, status,
1222                                       2, 5000, false, rtwdev, 2);
1223        if (ret)
1224                rtw_warn(rtwdev, "failed to pause TX\n");
1225
1226        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] Tx pause!!\n");
1227}
1228
1229static void rtw8822c_txgapk_bb_dpk(struct rtw_dev *rtwdev, u8 path)
1230{
1231        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1232
1233        rtw_write32_mask(rtwdev, REG_ENFN, BIT_IQK_DPK_EN, 0x1);
1234        rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2,
1235                         BIT_IQK_DPK_CLOCK_SRC, 0x1);
1236        rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2,
1237                         BIT_IQK_DPK_RESET_SRC, 0x1);
1238        rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_EN_IOQ_IQK_DPK, 0x1);
1239        rtw_write32_mask(rtwdev, REG_CH_DELAY_EXTR2, BIT_TST_IQK2SET_SRC, 0x0);
1240        rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x1ff);
1241
1242        if (path == RF_PATH_A) {
1243                rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A,
1244                                 BIT_RFTXEN_GCK_FORCE_ON, 0x1);
1245                rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x1);
1246                rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A,
1247                                 BIT_TX_SCALE_0DB, 0x1);
1248                rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x0);
1249        } else if (path == RF_PATH_B) {
1250                rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B,
1251                                 BIT_RFTXEN_GCK_FORCE_ON, 0x1);
1252                rtw_write32_mask(rtwdev, REG_3WIRE2,
1253                                 BIT_DIS_SHARERX_TXGAT, 0x1);
1254                rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B,
1255                                 BIT_TX_SCALE_0DB, 0x1);
1256                rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x0);
1257        }
1258        rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x2);
1259}
1260
1261static void rtw8822c_txgapk_afe_dpk(struct rtw_dev *rtwdev, u8 path)
1262{
1263        u32 reg;
1264
1265        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1266
1267        if (path == RF_PATH_A) {
1268                reg = REG_ANAPAR_A;
1269        } else if (path == RF_PATH_B) {
1270                reg = REG_ANAPAR_B;
1271        } else {
1272                rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1273                return;
1274        }
1275
1276        rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, MASKDWORD);
1277        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1278        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700f0001);
1279        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x701f0001);
1280        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x702f0001);
1281        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x703f0001);
1282        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x704f0001);
1283        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705f0001);
1284        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x706f0001);
1285        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707f0001);
1286        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708f0001);
1287        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709f0001);
1288        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70af0001);
1289        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bf0001);
1290        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cf0001);
1291        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70df0001);
1292        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ef0001);
1293        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1294        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ff0001);
1295}
1296
1297static void rtw8822c_txgapk_afe_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1298{
1299        u32 reg;
1300
1301        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1302
1303        if (path == RF_PATH_A) {
1304                reg = REG_ANAPAR_A;
1305        } else if (path == RF_PATH_B) {
1306                reg = REG_ANAPAR_B;
1307        } else {
1308                rtw_err(rtwdev, "[TXGAPK] unknown path %d!!\n", path);
1309                return;
1310        }
1311        rtw_write32_mask(rtwdev, REG_IQK_CTRL, MASKDWORD, 0xffa1005e);
1312        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x700b8041);
1313        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70144041);
1314        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70244041);
1315        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70344041);
1316        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70444041);
1317        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x705b8041);
1318        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70644041);
1319        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x707b8041);
1320        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x708b8041);
1321        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x709b8041);
1322        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70ab8041);
1323        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70bb8041);
1324        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70cb8041);
1325        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70db8041);
1326        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70eb8041);
1327        rtw_write32_mask(rtwdev, reg, MASKDWORD, 0x70fb8041);
1328}
1329
1330static void rtw8822c_txgapk_bb_dpk_restore(struct rtw_dev *rtwdev, u8 path)
1331{
1332        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1333
1334        rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x0);
1335        rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TIA_BYPASS, 0x0);
1336        rtw_write_rf(rtwdev, path, RF_DIS_BYPASS_TXBB, BIT_TXBB, 0x0);
1337
1338        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1339        rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1340        rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1341        rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1342        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x1);
1343        rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1344        rtw_write32_mask(rtwdev, REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1345        rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, 0x00);
1346        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, 0x0);
1347        rtw_write32_mask(rtwdev, REG_CCA_OFF, BIT_CCA_ON_BY_PW, 0x0);
1348
1349        if (path == RF_PATH_A) {
1350                rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_A,
1351                                 BIT_RFTXEN_GCK_FORCE_ON, 0x0);
1352                rtw_write32_mask(rtwdev, REG_3WIRE, BIT_DIS_SHARERX_TXGAT, 0x0);
1353                rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_A,
1354                                 BIT_TX_SCALE_0DB, 0x0);
1355                rtw_write32_mask(rtwdev, REG_3WIRE, BIT_3WIRE_EN, 0x3);
1356        } else if (path == RF_PATH_B) {
1357                rtw_write32_mask(rtwdev, REG_RFTXEN_GCK_B,
1358                                 BIT_RFTXEN_GCK_FORCE_ON, 0x0);
1359                rtw_write32_mask(rtwdev, REG_3WIRE2,
1360                                 BIT_DIS_SHARERX_TXGAT, 0x0);
1361                rtw_write32_mask(rtwdev, REG_DIS_SHARE_RX_B,
1362                                 BIT_TX_SCALE_0DB, 0x0);
1363                rtw_write32_mask(rtwdev, REG_3WIRE2, BIT_3WIRE_EN, 0x3);
1364        }
1365
1366        rtw_write32_mask(rtwdev, REG_CCKSB, BIT_BBMODE, 0x0);
1367        rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_CFIR_EN, 0x5);
1368}
1369
1370static bool _rtw8822c_txgapk_gain_valid(struct rtw_dev *rtwdev, u32 gain)
1371{
1372        if ((FIELD_GET(BIT_GAIN_TX_PAD_H, gain) >= 0xc) &&
1373            (FIELD_GET(BIT_GAIN_TX_PAD_L, gain) >= 0xe))
1374                return true;
1375
1376        return false;
1377}
1378
1379static void _rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev,
1380                                                 u8 band, u8 path)
1381{
1382        struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1383        u32 v, tmp_3f = 0;
1384        u8 gain, check_txgain;
1385
1386        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1387
1388        switch (band) {
1389        case RF_BAND_2G_OFDM:
1390                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1391                break;
1392        case RF_BAND_5G_L:
1393                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1394                break;
1395        case RF_BAND_5G_M:
1396                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1397                break;
1398        case RF_BAND_5G_H:
1399                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1400                break;
1401        default:
1402                break;
1403        }
1404
1405        rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, MASKBYTE0, 0x88);
1406
1407        check_txgain = 0;
1408        for (gain = 0; gain < RF_GAIN_NUM; gain++) {
1409                v = txgapk->rf3f_bp[band][gain][path];
1410                if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
1411                        if (!check_txgain) {
1412                                tmp_3f = txgapk->rf3f_bp[band][gain][path];
1413                                check_txgain = 1;
1414                        }
1415                        rtw_dbg(rtwdev, RTW_DBG_RFK,
1416                                "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
1417                                txgapk->rf3f_bp[band][gain][path]);
1418                } else {
1419                        tmp_3f = txgapk->rf3f_bp[band][gain][path];
1420                }
1421
1422                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN, tmp_3f);
1423                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_I_GAIN, gain);
1424                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x1);
1425                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_GAIN_RST, 0x0);
1426
1427                rtw_dbg(rtwdev, RTW_DBG_RFK,
1428                        "[TXGAPK] Band=%d 0x1b98[11:0]=0x%03X path=%d\n",
1429                        band, tmp_3f, path);
1430        }
1431}
1432
1433static void rtw8822c_txgapk_write_gain_bb_table(struct rtw_dev *rtwdev)
1434{
1435        u8 path, band;
1436
1437        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n",
1438                __func__, rtwdev->dm_info.gapk.channel);
1439
1440        for (band = 0; band < RF_BAND_MAX; band++) {
1441                for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1442                        _rtw8822c_txgapk_write_gain_bb_table(rtwdev,
1443                                                             band, path);
1444                }
1445        }
1446}
1447
1448static void rtw8822c_txgapk_read_offset(struct rtw_dev *rtwdev, u8 path)
1449{
1450        static const u32 cfg1_1b00[2] = {0x00000d18, 0x00000d2a};
1451        static const u32 cfg2_1b00[2] = {0x00000d19, 0x00000d2b};
1452        static const u32 set_pi[2] = {REG_RSV_CTRL, REG_WLRF1};
1453        static const u32 path_setting[2] = {REG_ORITXCODE, REG_ORITXCODE2};
1454        struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1455        u8 channel = txgapk->channel;
1456        u32 val;
1457        int i;
1458
1459        if (path >= ARRAY_SIZE(cfg1_1b00) ||
1460            path >= ARRAY_SIZE(cfg2_1b00) ||
1461            path >= ARRAY_SIZE(set_pi) ||
1462            path >= ARRAY_SIZE(path_setting)) {
1463                rtw_warn(rtwdev, "[TXGAPK] wrong path %d\n", path);
1464                return;
1465        }
1466
1467        rtw_write32_mask(rtwdev, REG_ANTMAP0, BIT_ANT_PATH, path + 1);
1468        rtw_write32_mask(rtwdev, REG_TXLGMAP, MASKDWORD, 0xe4e40000);
1469        rtw_write32_mask(rtwdev, REG_TXANTSEG, BIT_ANTSEG, 0x3);
1470        rtw_write32_mask(rtwdev, path_setting[path], MASK20BITS, 0x33312);
1471        rtw_write32_mask(rtwdev, path_setting[path], BIT_PATH_EN, 0x1);
1472        rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x0);
1473        rtw_write_rf(rtwdev, path, RF_LUTDBG, BIT_TXA_TANK, 0x1);
1474        rtw_write_rf(rtwdev, path, RF_IDAC, BIT_TX_MODE, 0x820);
1475        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1476        rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1477
1478        rtw_write32_mask(rtwdev, REG_TX_TONE_IDX, MASKBYTE0, 0x018);
1479        fsleep(1000);
1480        if (channel >= 1 && channel <= 14)
1481                rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_2G_SWING);
1482        else
1483                rtw_write32_mask(rtwdev, REG_R_CONFIG, MASKBYTE0, BIT_5G_SWING);
1484        fsleep(1000);
1485
1486        rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg1_1b00[path]);
1487        rtw_write32_mask(rtwdev, REG_NCTL0, MASKDWORD, cfg2_1b00[path]);
1488
1489        read_poll_timeout(rtw_read32_mask, val,
1490                          val == 0x55, 1000, 100000, false,
1491                          rtwdev, REG_RPT_CIP, BIT_RPT_CIP_STATUS);
1492
1493        rtw_write32_mask(rtwdev, set_pi[path], BITS_RFC_DIRECT, 0x2);
1494        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1495        rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_EN, 0x1);
1496        rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x12);
1497        rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x3);
1498        val = rtw_read32(rtwdev, REG_STAT_RPT);
1499
1500        txgapk->offset[0][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1501        txgapk->offset[1][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1502        txgapk->offset[2][path] = (s8)FIELD_GET(BIT_GAPK_RPT2, val);
1503        txgapk->offset[3][path] = (s8)FIELD_GET(BIT_GAPK_RPT3, val);
1504        txgapk->offset[4][path] = (s8)FIELD_GET(BIT_GAPK_RPT4, val);
1505        txgapk->offset[5][path] = (s8)FIELD_GET(BIT_GAPK_RPT5, val);
1506        txgapk->offset[6][path] = (s8)FIELD_GET(BIT_GAPK_RPT6, val);
1507        txgapk->offset[7][path] = (s8)FIELD_GET(BIT_GAPK_RPT7, val);
1508
1509        rtw_write32_mask(rtwdev, REG_TX_GAIN_SET, BIT_GAPK_RPT_IDX, 0x4);
1510        val = rtw_read32(rtwdev, REG_STAT_RPT);
1511
1512        txgapk->offset[8][path] = (s8)FIELD_GET(BIT_GAPK_RPT0, val);
1513        txgapk->offset[9][path] = (s8)FIELD_GET(BIT_GAPK_RPT1, val);
1514
1515        for (i = 0; i < RF_HW_OFFSET_NUM; i++)
1516                if (txgapk->offset[i][path] & BIT(3))
1517                        txgapk->offset[i][path] = txgapk->offset[i][path] |
1518                                                  0xf0;
1519        for (i = 0; i < RF_HW_OFFSET_NUM; i++)
1520                rtw_dbg(rtwdev, RTW_DBG_RFK,
1521                        "[TXGAPK] offset %d %d path=%d\n",
1522                        txgapk->offset[i][path], i, path);
1523}
1524
1525static void rtw8822c_txgapk_calculate_offset(struct rtw_dev *rtwdev, u8 path)
1526{
1527        static const u32 bb_reg[] = {REG_ANTMAP0, REG_TXLGMAP, REG_TXANTSEG,
1528                                     REG_ORITXCODE, REG_ORITXCODE2};
1529        struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1530        u8 channel = txgapk->channel;
1531        u32 reg_backup[ARRAY_SIZE(bb_reg)] = {0};
1532
1533        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s channel=%d\n",
1534                __func__, channel);
1535
1536        rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg,
1537                                      reg_backup, ARRAY_SIZE(bb_reg));
1538
1539        if (channel >= 1 && channel <= 14) {
1540                rtw_write32_mask(rtwdev,
1541                                 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1542                rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1543                rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1544                rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1545                rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1546                rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x5000f);
1547                rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x0);
1548                rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x1);
1549                rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x0f);
1550                rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1551                rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
1552                rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1553                rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1554
1555                rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x00);
1556                rtw_write32_mask(rtwdev, REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x0);
1557
1558                rtw8822c_txgapk_read_offset(rtwdev, path);
1559                rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n");
1560
1561        } else {
1562                rtw_write32_mask(rtwdev,
1563                                 REG_SINGLE_TONE_SW, BIT_IRQ_TEST_MODE, 0x0);
1564                rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SEL_PATH, path);
1565                rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x3f);
1566                rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x0);
1567                rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
1568                rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50011);
1569                rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x3);
1570                rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x3);
1571                rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
1572                rtw_write_rf(rtwdev, path,
1573                             RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0x2);
1574                rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0x12);
1575                rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
1576                rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
1577                rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x1);
1578                rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x5);
1579
1580                rtw_write32_mask(rtwdev, REG_IQKSTAT, MASKBYTE0, 0x0);
1581
1582                if (channel >= 36 && channel <= 64)
1583                        rtw_write32_mask(rtwdev,
1584                                         REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x2);
1585                else if (channel >= 100 && channel <= 144)
1586                        rtw_write32_mask(rtwdev,
1587                                         REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x3);
1588                else if (channel >= 149 && channel <= 177)
1589                        rtw_write32_mask(rtwdev,
1590                                         REG_TABLE_SEL, BIT_Q_GAIN_SEL, 0x4);
1591
1592                rtw8822c_txgapk_read_offset(rtwdev, path);
1593                rtw_dbg(rtwdev, RTW_DBG_RFK, "=============================\n");
1594        }
1595        rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg,
1596                                      reg_backup, ARRAY_SIZE(bb_reg));
1597}
1598
1599static void rtw8822c_txgapk_rf_restore(struct rtw_dev *rtwdev, u8 path)
1600{
1601        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1602
1603        if (path >= rtwdev->hal.rf_path_num)
1604                return;
1605
1606        rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RF_MODE, 0x3);
1607        rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x0);
1608        rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT_PW_EXT_TIA, 0x0);
1609}
1610
1611static u32 rtw8822c_txgapk_cal_gain(struct rtw_dev *rtwdev, u32 gain, s8 offset)
1612{
1613        u32 gain_x2, new_gain;
1614
1615        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1616
1617        if (_rtw8822c_txgapk_gain_valid(rtwdev, gain)) {
1618                new_gain = gain;
1619                rtw_dbg(rtwdev, RTW_DBG_RFK,
1620                        "[TXGAPK] gain=0x%03X(>=0xCEX) offset=%d new_gain=0x%03X\n",
1621                        gain, offset, new_gain);
1622                return new_gain;
1623        }
1624
1625        gain_x2 = (gain << 1) + offset;
1626        new_gain = (gain_x2 >> 1) | (gain_x2 & BIT(0) ? BIT_GAIN_EXT : 0);
1627
1628        rtw_dbg(rtwdev, RTW_DBG_RFK,
1629                "[TXGAPK] gain=0x%X offset=%d new_gain=0x%X\n",
1630                gain, offset, new_gain);
1631
1632        return new_gain;
1633}
1634
1635static void rtw8822c_txgapk_write_tx_gain(struct rtw_dev *rtwdev)
1636{
1637        struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1638        u32 i, j, tmp = 0x20, tmp_3f, v;
1639        s8 offset_tmp[RF_GAIN_NUM] = {0};
1640        u8 path, band = RF_BAND_2G_OFDM, channel = txgapk->channel;
1641
1642        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1643
1644        if (channel >= 1 && channel <= 14) {
1645                tmp = 0x20;
1646                band = RF_BAND_2G_OFDM;
1647        } else if (channel >= 36 && channel <= 64) {
1648                tmp = 0x200;
1649                band = RF_BAND_5G_L;
1650        } else if (channel >= 100 && channel <= 144) {
1651                tmp = 0x280;
1652                band = RF_BAND_5G_M;
1653        } else if (channel >= 149 && channel <= 177) {
1654                tmp = 0x300;
1655                band = RF_BAND_5G_H;
1656        } else {
1657                rtw_err(rtwdev, "[TXGAPK] unknown channel %d!!\n", channel);
1658                return;
1659        }
1660
1661        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1662                for (i = 0; i < RF_GAIN_NUM; i++) {
1663                        offset_tmp[i] = 0;
1664                        for (j = i; j < RF_GAIN_NUM; j++) {
1665                                v = txgapk->rf3f_bp[band][j][path];
1666                                if (_rtw8822c_txgapk_gain_valid(rtwdev, v))
1667                                        continue;
1668
1669                                offset_tmp[i] += txgapk->offset[j][path];
1670                                txgapk->fianl_offset[i][path] = offset_tmp[i];
1671                        }
1672
1673                        v = txgapk->rf3f_bp[band][i][path];
1674                        if (_rtw8822c_txgapk_gain_valid(rtwdev, v)) {
1675                                rtw_dbg(rtwdev, RTW_DBG_RFK,
1676                                        "[TXGAPK] tx_gain=0x%03X >= 0xCEX\n",
1677                                        txgapk->rf3f_bp[band][i][path]);
1678                        } else {
1679                                txgapk->rf3f_fs[path][i] = offset_tmp[i];
1680                                rtw_dbg(rtwdev, RTW_DBG_RFK,
1681                                        "[TXGAPK] offset %d %d\n",
1682                                        offset_tmp[i], i);
1683                        }
1684                }
1685
1686                rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x10000);
1687                for (i = 0; i < RF_GAIN_NUM; i++) {
1688                        rtw_write_rf(rtwdev, path,
1689                                     RF_LUTWA, RFREG_MASK, tmp + i);
1690
1691                        tmp_3f = rtw8822c_txgapk_cal_gain(rtwdev,
1692                                                          txgapk->rf3f_bp[band][i][path],
1693                                                          offset_tmp[i]);
1694                        rtw_write_rf(rtwdev, path, RF_LUTWD0,
1695                                     BIT_GAIN_EXT | BIT_DATA_L, tmp_3f);
1696
1697                        rtw_dbg(rtwdev, RTW_DBG_RFK,
1698                                "[TXGAPK] 0x33=0x%05X 0x3f=0x%04X\n",
1699                                tmp + i, tmp_3f);
1700                }
1701                rtw_write_rf(rtwdev, path, RF_LUTWE2, RFREG_MASK, 0x0);
1702        }
1703}
1704
1705static void rtw8822c_txgapk_save_all_tx_gain_table(struct rtw_dev *rtwdev)
1706{
1707        struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1708        static const u32 three_wire[2] = {REG_3WIRE, REG_3WIRE2};
1709        static const u8 ch_num[RF_BAND_MAX] = {1, 1, 36, 100, 149};
1710        static const u8 band_num[RF_BAND_MAX] = {0x0, 0x0, 0x1, 0x3, 0x5};
1711        static const u8 cck[RF_BAND_MAX] = {0x1, 0x0, 0x0, 0x0, 0x0};
1712        u8 path, band, gain, rf0_idx;
1713        u32 rf18, v;
1714
1715        if (rtwdev->dm_info.dm_flags & BIT(RTW_DM_CAP_TXGAPK))
1716                return;
1717
1718        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1719
1720        if (txgapk->read_txgain == 1) {
1721                rtw_dbg(rtwdev, RTW_DBG_RFK,
1722                        "[TXGAPK] Already Read txgapk->read_txgain return!!!\n");
1723                rtw8822c_txgapk_write_gain_bb_table(rtwdev);
1724                return;
1725        }
1726
1727        for (band = 0; band < RF_BAND_MAX; band++) {
1728                for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1729                        rf18 = rtw_read_rf(rtwdev, path, RF_CFGCH, RFREG_MASK);
1730
1731                        rtw_write32_mask(rtwdev,
1732                                         three_wire[path], BIT_3WIRE_EN, 0x0);
1733                        rtw_write_rf(rtwdev, path,
1734                                     RF_CFGCH, MASKBYTE0, ch_num[band]);
1735                        rtw_write_rf(rtwdev, path,
1736                                     RF_CFGCH, BIT_BAND, band_num[band]);
1737                        rtw_write_rf(rtwdev, path,
1738                                     RF_BW_TRXBB, BIT_DBG_CCK_CCA, cck[band]);
1739                        rtw_write_rf(rtwdev, path,
1740                                     RF_BW_TRXBB, BIT_TX_CCK_IND, cck[band]);
1741                        gain = 0;
1742                        for (rf0_idx = 1; rf0_idx < 32; rf0_idx += 3) {
1743                                rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC,
1744                                             MASKBYTE0, rf0_idx);
1745                                v = rtw_read_rf(rtwdev, path,
1746                                                RF_TX_RESULT, RFREG_MASK);
1747                                txgapk->rf3f_bp[band][gain][path] = v & BIT_DATA_L;
1748
1749                                rtw_dbg(rtwdev, RTW_DBG_RFK,
1750                                        "[TXGAPK] 0x5f=0x%03X band=%d path=%d\n",
1751                                        txgapk->rf3f_bp[band][gain][path],
1752                                        band, path);
1753                                gain++;
1754                        }
1755                        rtw_write_rf(rtwdev, path, RF_CFGCH, RFREG_MASK, rf18);
1756                        rtw_write32_mask(rtwdev,
1757                                         three_wire[path], BIT_3WIRE_EN, 0x3);
1758                }
1759        }
1760        rtw8822c_txgapk_write_gain_bb_table(rtwdev);
1761        txgapk->read_txgain = 1;
1762}
1763
1764static void rtw8822c_txgapk(struct rtw_dev *rtwdev)
1765{
1766        static const u32 bb_reg[2] = {REG_TX_PTCL_CTRL, REG_TX_FIFO};
1767        struct rtw_gapk_info *txgapk = &rtwdev->dm_info.gapk;
1768        u32 bb_reg_backup[2];
1769        u8 path;
1770
1771        rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] ======>%s\n", __func__);
1772
1773        rtw8822c_txgapk_save_all_tx_gain_table(rtwdev);
1774
1775        if (txgapk->read_txgain == 0) {
1776                rtw_dbg(rtwdev, RTW_DBG_RFK,
1777                        "[TXGAPK] txgapk->read_txgain == 0 return!!!\n");
1778                return;
1779        }
1780
1781        if (rtwdev->efuse.power_track_type >= 4 &&
1782            rtwdev->efuse.power_track_type <= 7) {
1783                rtw_dbg(rtwdev, RTW_DBG_RFK,
1784                        "[TXGAPK] Normal Mode in TSSI mode. return!!!\n");
1785                return;
1786        }
1787
1788        rtw8822c_txgapk_backup_bb_reg(rtwdev, bb_reg,
1789                                      bb_reg_backup, ARRAY_SIZE(bb_reg));
1790        rtw8822c_txgapk_tx_pause(rtwdev);
1791        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
1792                txgapk->channel = rtw_read_rf(rtwdev, path,
1793                                              RF_CFGCH, RFREG_MASK) & MASKBYTE0;
1794                rtw8822c_txgapk_bb_dpk(rtwdev, path);
1795                rtw8822c_txgapk_afe_dpk(rtwdev, path);
1796                rtw8822c_txgapk_calculate_offset(rtwdev, path);
1797                rtw8822c_txgapk_rf_restore(rtwdev, path);
1798                rtw8822c_txgapk_afe_dpk_restore(rtwdev, path);
1799                rtw8822c_txgapk_bb_dpk_restore(rtwdev, path);
1800        }
1801        rtw8822c_txgapk_write_tx_gain(rtwdev);
1802        rtw8822c_txgapk_reload_bb_reg(rtwdev, bb_reg,
1803                                      bb_reg_backup, ARRAY_SIZE(bb_reg));
1804}
1805
1806static void rtw8822c_do_gapk(struct rtw_dev *rtwdev)
1807{
1808        struct rtw_dm_info *dm = &rtwdev->dm_info;
1809
1810        if (dm->dm_flags & BIT(RTW_DM_CAP_TXGAPK)) {
1811                rtw_dbg(rtwdev, RTW_DBG_RFK, "[TXGAPK] feature disable!!!\n");
1812                return;
1813        }
1814        rtw8822c_rfk_handshake(rtwdev, true);
1815        rtw8822c_txgapk(rtwdev);
1816        rtw8822c_rfk_handshake(rtwdev, false);
1817}
1818
1819static void rtw8822c_rf_init(struct rtw_dev *rtwdev)
1820{
1821        rtw8822c_rf_dac_cal(rtwdev);
1822        rtw8822c_rf_x2_check(rtwdev);
1823        rtw8822c_thermal_trim(rtwdev);
1824        rtw8822c_power_trim(rtwdev);
1825        rtw8822c_pa_bias(rtwdev);
1826}
1827
1828static void rtw8822c_pwrtrack_init(struct rtw_dev *rtwdev)
1829{
1830        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1831        u8 path;
1832
1833        for (path = RF_PATH_A; path < RTW_RF_PATH_MAX; path++) {
1834                dm_info->delta_power_index[path] = 0;
1835                ewma_thermal_init(&dm_info->avg_thermal[path]);
1836                dm_info->thermal_avg[path] = 0xff;
1837        }
1838
1839        dm_info->pwr_trk_triggered = false;
1840        dm_info->thermal_meter_k = rtwdev->efuse.thermal_meter_k;
1841        dm_info->thermal_meter_lck = rtwdev->efuse.thermal_meter_k;
1842}
1843
1844static void rtw8822c_phy_set_param(struct rtw_dev *rtwdev)
1845{
1846        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
1847        struct rtw_hal *hal = &rtwdev->hal;
1848        u8 crystal_cap;
1849        u8 cck_gi_u_bnd_msb = 0;
1850        u8 cck_gi_u_bnd_lsb = 0;
1851        u8 cck_gi_l_bnd_msb = 0;
1852        u8 cck_gi_l_bnd_lsb = 0;
1853        bool is_tx2_path;
1854
1855        /* power on BB/RF domain */
1856        rtw_write8_set(rtwdev, REG_SYS_FUNC_EN,
1857                       BIT_FEN_BB_GLB_RST | BIT_FEN_BB_RSTB);
1858        rtw_write8_set(rtwdev, REG_RF_CTRL,
1859                       BIT_RF_EN | BIT_RF_RSTB | BIT_RF_SDM_RSTB);
1860        rtw_write32_set(rtwdev, REG_WLRF1, BIT_WLRF1_BBRF_EN);
1861
1862        /* disable low rate DPD */
1863        rtw_write32_mask(rtwdev, REG_DIS_DPD, DIS_DPD_MASK, DIS_DPD_RATEALL);
1864
1865        /* pre init before header files config */
1866        rtw8822c_header_file_init(rtwdev, true);
1867
1868        rtw_phy_load_tables(rtwdev);
1869
1870        crystal_cap = rtwdev->efuse.crystal_cap & 0x7f;
1871        rtw_write32_mask(rtwdev, REG_ANAPAR_XTAL_0, 0xfffc00,
1872                         crystal_cap | (crystal_cap << 7));
1873
1874        /* post init after header files config */
1875        rtw8822c_header_file_init(rtwdev, false);
1876
1877        is_tx2_path = false;
1878        rtw8822c_config_trx_mode(rtwdev, hal->antenna_tx, hal->antenna_rx,
1879                                 is_tx2_path);
1880        rtw_phy_init(rtwdev);
1881
1882        cck_gi_u_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc000);
1883        cck_gi_u_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1aa8, 0xf0000);
1884        cck_gi_l_bnd_msb = (u8)rtw_read32_mask(rtwdev, 0x1a98, 0xc0);
1885        cck_gi_l_bnd_lsb = (u8)rtw_read32_mask(rtwdev, 0x1a70, 0x0f000000);
1886
1887        dm_info->cck_gi_u_bnd = ((cck_gi_u_bnd_msb << 4) | (cck_gi_u_bnd_lsb));
1888        dm_info->cck_gi_l_bnd = ((cck_gi_l_bnd_msb << 4) | (cck_gi_l_bnd_lsb));
1889
1890        rtw8822c_rf_init(rtwdev);
1891        rtw8822c_pwrtrack_init(rtwdev);
1892
1893        rtw_bf_phy_init(rtwdev);
1894}
1895
1896#define WLAN_TXQ_RPT_EN         0x1F
1897#define WLAN_SLOT_TIME          0x09
1898#define WLAN_PIFS_TIME          0x1C
1899#define WLAN_SIFS_CCK_CONT_TX   0x0A
1900#define WLAN_SIFS_OFDM_CONT_TX  0x0E
1901#define WLAN_SIFS_CCK_TRX       0x0A
1902#define WLAN_SIFS_OFDM_TRX      0x10
1903#define WLAN_NAV_MAX            0xC8
1904#define WLAN_RDG_NAV            0x05
1905#define WLAN_TXOP_NAV           0x1B
1906#define WLAN_CCK_RX_TSF         0x30
1907#define WLAN_OFDM_RX_TSF        0x30
1908#define WLAN_TBTT_PROHIBIT      0x04 /* unit : 32us */
1909#define WLAN_TBTT_HOLD_TIME     0x064 /* unit : 32us */
1910#define WLAN_DRV_EARLY_INT      0x04
1911#define WLAN_BCN_CTRL_CLT0      0x10
1912#define WLAN_BCN_DMA_TIME       0x02
1913#define WLAN_BCN_MAX_ERR        0xFF
1914#define WLAN_SIFS_CCK_DUR_TUNE  0x0A
1915#define WLAN_SIFS_OFDM_DUR_TUNE 0x10
1916#define WLAN_SIFS_CCK_CTX       0x0A
1917#define WLAN_SIFS_CCK_IRX       0x0A
1918#define WLAN_SIFS_OFDM_CTX      0x0E
1919#define WLAN_SIFS_OFDM_IRX      0x0E
1920#define WLAN_EIFS_DUR_TUNE      0x40
1921#define WLAN_EDCA_VO_PARAM      0x002FA226
1922#define WLAN_EDCA_VI_PARAM      0x005EA328
1923#define WLAN_EDCA_BE_PARAM      0x005EA42B
1924#define WLAN_EDCA_BK_PARAM      0x0000A44F
1925
1926#define WLAN_RX_FILTER0         0xFFFFFFFF
1927#define WLAN_RX_FILTER2         0xFFFF
1928#define WLAN_RCR_CFG            0xE400220E
1929#define WLAN_RXPKT_MAX_SZ       12288
1930#define WLAN_RXPKT_MAX_SZ_512   (WLAN_RXPKT_MAX_SZ >> 9)
1931
1932#define WLAN_AMPDU_MAX_TIME             0x70
1933#define WLAN_RTS_LEN_TH                 0xFF
1934#define WLAN_RTS_TX_TIME_TH             0x08
1935#define WLAN_MAX_AGG_PKT_LIMIT          0x3f
1936#define WLAN_RTS_MAX_AGG_PKT_LIMIT      0x3f
1937#define WLAN_PRE_TXCNT_TIME_TH          0x1E0
1938#define FAST_EDCA_VO_TH         0x06
1939#define FAST_EDCA_VI_TH         0x06
1940#define FAST_EDCA_BE_TH         0x06
1941#define FAST_EDCA_BK_TH         0x06
1942#define WLAN_BAR_RETRY_LIMIT            0x01
1943#define WLAN_BAR_ACK_TYPE               0x05
1944#define WLAN_RA_TRY_RATE_AGG_LIMIT      0x08
1945#define WLAN_RESP_TXRATE                0x84
1946#define WLAN_ACK_TO                     0x21
1947#define WLAN_ACK_TO_CCK                 0x6A
1948#define WLAN_DATA_RATE_FB_CNT_1_4       0x01000000
1949#define WLAN_DATA_RATE_FB_CNT_5_8       0x08070504
1950#define WLAN_RTS_RATE_FB_CNT_5_8        0x08070504
1951#define WLAN_DATA_RATE_FB_RATE0         0xFE01F010
1952#define WLAN_DATA_RATE_FB_RATE0_H       0x40000000
1953#define WLAN_RTS_RATE_FB_RATE1          0x003FF010
1954#define WLAN_RTS_RATE_FB_RATE1_H        0x40000000
1955#define WLAN_RTS_RATE_FB_RATE4          0x0600F010
1956#define WLAN_RTS_RATE_FB_RATE4_H        0x400003E0
1957#define WLAN_RTS_RATE_FB_RATE5          0x0600F015
1958#define WLAN_RTS_RATE_FB_RATE5_H        0x000000E0
1959#define WLAN_MULTI_ADDR                 0xFFFFFFFF
1960
1961#define WLAN_TX_FUNC_CFG1               0x30
1962#define WLAN_TX_FUNC_CFG2               0x30
1963#define WLAN_MAC_OPT_NORM_FUNC1         0x98
1964#define WLAN_MAC_OPT_LB_FUNC1           0x80
1965#define WLAN_MAC_OPT_FUNC2              0x30810041
1966#define WLAN_MAC_INT_MIG_CFG            0x33330000
1967
1968#define WLAN_SIFS_CFG   (WLAN_SIFS_CCK_CONT_TX | \
1969                        (WLAN_SIFS_OFDM_CONT_TX << BIT_SHIFT_SIFS_OFDM_CTX) | \
1970                        (WLAN_SIFS_CCK_TRX << BIT_SHIFT_SIFS_CCK_TRX) | \
1971                        (WLAN_SIFS_OFDM_TRX << BIT_SHIFT_SIFS_OFDM_TRX))
1972
1973#define WLAN_SIFS_DUR_TUNE      (WLAN_SIFS_CCK_DUR_TUNE | \
1974                                (WLAN_SIFS_OFDM_DUR_TUNE << 8))
1975
1976#define WLAN_TBTT_TIME  (WLAN_TBTT_PROHIBIT |\
1977                        (WLAN_TBTT_HOLD_TIME << BIT_SHIFT_TBTT_HOLD_TIME_AP))
1978
1979#define WLAN_NAV_CFG            (WLAN_RDG_NAV | (WLAN_TXOP_NAV << 16))
1980#define WLAN_RX_TSF_CFG         (WLAN_CCK_RX_TSF | (WLAN_OFDM_RX_TSF) << 8)
1981
1982#define MAC_CLK_SPEED   80 /* 80M */
1983#define EFUSE_PCB_INFO_OFFSET   0xCA
1984
1985static int rtw8822c_mac_init(struct rtw_dev *rtwdev)
1986{
1987        u8 value8;
1988        u16 value16;
1989        u32 value32;
1990        u16 pre_txcnt;
1991
1992        /* txq control */
1993        value8 = rtw_read8(rtwdev, REG_FWHW_TXQ_CTRL);
1994        value8 |= (BIT(7) & ~BIT(1) & ~BIT(2));
1995        rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL, value8);
1996        rtw_write8(rtwdev, REG_FWHW_TXQ_CTRL + 1, WLAN_TXQ_RPT_EN);
1997        /* sifs control */
1998        rtw_write16(rtwdev, REG_SPEC_SIFS, WLAN_SIFS_DUR_TUNE);
1999        rtw_write32(rtwdev, REG_SIFS, WLAN_SIFS_CFG);
2000        rtw_write16(rtwdev, REG_RESP_SIFS_CCK,
2001                    WLAN_SIFS_CCK_CTX | WLAN_SIFS_CCK_IRX << 8);
2002        rtw_write16(rtwdev, REG_RESP_SIFS_OFDM,
2003                    WLAN_SIFS_OFDM_CTX | WLAN_SIFS_OFDM_IRX << 8);
2004        /* rate fallback control */
2005        rtw_write32(rtwdev, REG_DARFRC, WLAN_DATA_RATE_FB_CNT_1_4);
2006        rtw_write32(rtwdev, REG_DARFRCH, WLAN_DATA_RATE_FB_CNT_5_8);
2007        rtw_write32(rtwdev, REG_RARFRCH, WLAN_RTS_RATE_FB_CNT_5_8);
2008        rtw_write32(rtwdev, REG_ARFR0, WLAN_DATA_RATE_FB_RATE0);
2009        rtw_write32(rtwdev, REG_ARFRH0, WLAN_DATA_RATE_FB_RATE0_H);
2010        rtw_write32(rtwdev, REG_ARFR1_V1, WLAN_RTS_RATE_FB_RATE1);
2011        rtw_write32(rtwdev, REG_ARFRH1_V1, WLAN_RTS_RATE_FB_RATE1_H);
2012        rtw_write32(rtwdev, REG_ARFR4, WLAN_RTS_RATE_FB_RATE4);
2013        rtw_write32(rtwdev, REG_ARFRH4, WLAN_RTS_RATE_FB_RATE4_H);
2014        rtw_write32(rtwdev, REG_ARFR5, WLAN_RTS_RATE_FB_RATE5);
2015        rtw_write32(rtwdev, REG_ARFRH5, WLAN_RTS_RATE_FB_RATE5_H);
2016        /* protocol configuration */
2017        rtw_write8(rtwdev, REG_AMPDU_MAX_TIME_V1, WLAN_AMPDU_MAX_TIME);
2018        rtw_write8_set(rtwdev, REG_TX_HANG_CTRL, BIT_EN_EOF_V1);
2019        pre_txcnt = WLAN_PRE_TXCNT_TIME_TH | BIT_EN_PRECNT;
2020        rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF));
2021        rtw_write8(rtwdev, REG_PRECNT_CTRL + 1, (u8)(pre_txcnt >> 8));
2022        value32 = WLAN_RTS_LEN_TH | (WLAN_RTS_TX_TIME_TH << 8) |
2023                  (WLAN_MAX_AGG_PKT_LIMIT << 16) |
2024                  (WLAN_RTS_MAX_AGG_PKT_LIMIT << 24);
2025        rtw_write32(rtwdev, REG_PROT_MODE_CTRL, value32);
2026        rtw_write16(rtwdev, REG_BAR_MODE_CTRL + 2,
2027                    WLAN_BAR_RETRY_LIMIT | WLAN_RA_TRY_RATE_AGG_LIMIT << 8);
2028        rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING, FAST_EDCA_VO_TH);
2029        rtw_write8(rtwdev, REG_FAST_EDCA_VOVI_SETTING + 2, FAST_EDCA_VI_TH);
2030        rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING, FAST_EDCA_BE_TH);
2031        rtw_write8(rtwdev, REG_FAST_EDCA_BEBK_SETTING + 2, FAST_EDCA_BK_TH);
2032        /* close BA parser */
2033        rtw_write8_clr(rtwdev, REG_LIFETIME_EN, BIT_BA_PARSER_EN);
2034        rtw_write32_clr(rtwdev, REG_RRSR, BITS_RRSR_RSC);
2035
2036        /* EDCA configuration */
2037        rtw_write32(rtwdev, REG_EDCA_VO_PARAM, WLAN_EDCA_VO_PARAM);
2038        rtw_write32(rtwdev, REG_EDCA_VI_PARAM, WLAN_EDCA_VI_PARAM);
2039        rtw_write32(rtwdev, REG_EDCA_BE_PARAM, WLAN_EDCA_BE_PARAM);
2040        rtw_write32(rtwdev, REG_EDCA_BK_PARAM, WLAN_EDCA_BK_PARAM);
2041        rtw_write8(rtwdev, REG_PIFS, WLAN_PIFS_TIME);
2042        rtw_write8_clr(rtwdev, REG_TX_PTCL_CTRL + 1, BIT_SIFS_BK_EN >> 8);
2043        rtw_write8_set(rtwdev, REG_RD_CTRL + 1,
2044                       (BIT_DIS_TXOP_CFE | BIT_DIS_LSIG_CFE |
2045                        BIT_DIS_STBC_CFE) >> 8);
2046
2047        /* MAC clock configuration */
2048        rtw_write32_clr(rtwdev, REG_AFE_CTRL1, BIT_MAC_CLK_SEL);
2049        rtw_write8(rtwdev, REG_USTIME_TSF, MAC_CLK_SPEED);
2050        rtw_write8(rtwdev, REG_USTIME_EDCA, MAC_CLK_SPEED);
2051
2052        rtw_write8_set(rtwdev, REG_MISC_CTRL,
2053                       BIT_EN_FREE_CNT | BIT_DIS_SECOND_CCA);
2054        rtw_write8_clr(rtwdev, REG_TIMER0_SRC_SEL, BIT_TSFT_SEL_TIMER0);
2055        rtw_write16(rtwdev, REG_TXPAUSE, 0x0000);
2056        rtw_write8(rtwdev, REG_SLOT, WLAN_SLOT_TIME);
2057        rtw_write32(rtwdev, REG_RD_NAV_NXT, WLAN_NAV_CFG);
2058        rtw_write16(rtwdev, REG_RXTSF_OFFSET_CCK, WLAN_RX_TSF_CFG);
2059        /* Set beacon cotnrol - enable TSF and other related functions */
2060        rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2061        /* Set send beacon related registers */
2062        rtw_write32(rtwdev, REG_TBTT_PROHIBIT, WLAN_TBTT_TIME);
2063        rtw_write8(rtwdev, REG_DRVERLYINT, WLAN_DRV_EARLY_INT);
2064        rtw_write8(rtwdev, REG_BCN_CTRL_CLINT0, WLAN_BCN_CTRL_CLT0);
2065        rtw_write8(rtwdev, REG_BCNDMATIM, WLAN_BCN_DMA_TIME);
2066        rtw_write8(rtwdev, REG_BCN_MAX_ERR, WLAN_BCN_MAX_ERR);
2067
2068        /* WMAC configuration */
2069        rtw_write32(rtwdev, REG_MAR, WLAN_MULTI_ADDR);
2070        rtw_write32(rtwdev, REG_MAR + 4, WLAN_MULTI_ADDR);
2071        rtw_write8(rtwdev, REG_BBPSF_CTRL + 2, WLAN_RESP_TXRATE);
2072        rtw_write8(rtwdev, REG_ACKTO, WLAN_ACK_TO);
2073        rtw_write8(rtwdev, REG_ACKTO_CCK, WLAN_ACK_TO_CCK);
2074        rtw_write16(rtwdev, REG_EIFS, WLAN_EIFS_DUR_TUNE);
2075        rtw_write8(rtwdev, REG_NAV_CTRL + 2, WLAN_NAV_MAX);
2076        rtw_write8(rtwdev, REG_WMAC_TRXPTCL_CTL_H  + 2, WLAN_BAR_ACK_TYPE);
2077        rtw_write32(rtwdev, REG_RXFLTMAP0, WLAN_RX_FILTER0);
2078        rtw_write16(rtwdev, REG_RXFLTMAP2, WLAN_RX_FILTER2);
2079        rtw_write32(rtwdev, REG_RCR, WLAN_RCR_CFG);
2080        rtw_write8(rtwdev, REG_RX_PKT_LIMIT, WLAN_RXPKT_MAX_SZ_512);
2081        rtw_write8(rtwdev, REG_TCR + 2, WLAN_TX_FUNC_CFG2);
2082        rtw_write8(rtwdev, REG_TCR + 1, WLAN_TX_FUNC_CFG1);
2083        rtw_write32_set(rtwdev, REG_GENERAL_OPTION, BIT_DUMMY_FCS_READY_MASK_EN);
2084        rtw_write32(rtwdev, REG_WMAC_OPTION_FUNCTION + 8, WLAN_MAC_OPT_FUNC2);
2085        rtw_write8(rtwdev, REG_WMAC_OPTION_FUNCTION_1, WLAN_MAC_OPT_NORM_FUNC1);
2086
2087        /* init low power */
2088        value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL + 2) & 0xF00F;
2089        value16 |= (BIT_RXGCK_VHT_FIFOTHR(1) | BIT_RXGCK_HT_FIFOTHR(1) |
2090                    BIT_RXGCK_OFDM_FIFOTHR(1) | BIT_RXGCK_CCK_FIFOTHR(1)) >> 16;
2091        rtw_write16(rtwdev, REG_RXPSF_CTRL + 2, value16);
2092        value16 = 0;
2093        value16 = BIT_SET_RXPSF_PKTLENTHR(value16, 1);
2094        value16 |= BIT_RXPSF_CTRLEN | BIT_RXPSF_VHTCHKEN | BIT_RXPSF_HTCHKEN
2095                | BIT_RXPSF_OFDMCHKEN | BIT_RXPSF_CCKCHKEN
2096                | BIT_RXPSF_OFDMRST;
2097        rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
2098        rtw_write32(rtwdev, REG_RXPSF_TYPE_CTRL, 0xFFFFFFFF);
2099        /* rx ignore configuration */
2100        value16 = rtw_read16(rtwdev, REG_RXPSF_CTRL);
2101        value16 &= ~(BIT_RXPSF_MHCHKEN | BIT_RXPSF_CCKRST |
2102                     BIT_RXPSF_CONT_ERRCHKEN);
2103        value16 = BIT_SET_RXPSF_ERRTHR(value16, 0x07);
2104        rtw_write16(rtwdev, REG_RXPSF_CTRL, value16);
2105
2106        /* Interrupt migration configuration */
2107        rtw_write32(rtwdev, REG_INT_MIG, WLAN_MAC_INT_MIG_CFG);
2108
2109        return 0;
2110}
2111
2112#define FWCD_SIZE_REG_8822C 0x2000
2113#define FWCD_SIZE_DMEM_8822C 0x10000
2114#define FWCD_SIZE_IMEM_8822C 0x10000
2115#define FWCD_SIZE_EMEM_8822C 0x20000
2116#define FWCD_SIZE_ROM_8822C 0x10000
2117
2118static const u32 __fwcd_segs_8822c[] = {
2119        FWCD_SIZE_REG_8822C,
2120        FWCD_SIZE_DMEM_8822C,
2121        FWCD_SIZE_IMEM_8822C,
2122        FWCD_SIZE_EMEM_8822C,
2123        FWCD_SIZE_ROM_8822C,
2124};
2125
2126static const struct rtw_fwcd_segs rtw8822c_fwcd_segs = {
2127        .segs = __fwcd_segs_8822c,
2128        .num = ARRAY_SIZE(__fwcd_segs_8822c),
2129};
2130
2131static int rtw8822c_dump_fw_crash(struct rtw_dev *rtwdev)
2132{
2133#define __dump_fw_8822c(_dev, _mem) \
2134        rtw_dump_fw(_dev, OCPBASE_ ## _mem ## _88XX, \
2135                    FWCD_SIZE_ ## _mem ## _8822C, RTW_FWCD_ ## _mem)
2136        int ret;
2137
2138        ret = rtw_dump_reg(rtwdev, 0x0, FWCD_SIZE_REG_8822C);
2139        if (ret)
2140                return ret;
2141        ret = __dump_fw_8822c(rtwdev, DMEM);
2142        if (ret)
2143                return ret;
2144        ret = __dump_fw_8822c(rtwdev, IMEM);
2145        if (ret)
2146                return ret;
2147        ret = __dump_fw_8822c(rtwdev, EMEM);
2148        if (ret)
2149                return ret;
2150        ret = __dump_fw_8822c(rtwdev, ROM);
2151        if (ret)
2152                return ret;
2153
2154        return 0;
2155
2156#undef __dump_fw_8822c
2157}
2158
2159static void rtw8822c_rstb_3wire(struct rtw_dev *rtwdev, bool enable)
2160{
2161        if (enable) {
2162                rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x1);
2163                rtw_write32_mask(rtwdev, REG_ANAPAR_A, BIT_ANAPAR_UPDATE, 0x1);
2164                rtw_write32_mask(rtwdev, REG_ANAPAR_B, BIT_ANAPAR_UPDATE, 0x1);
2165        } else {
2166                rtw_write32_mask(rtwdev, REG_RSTB, BIT_RSTB_3WIRE, 0x0);
2167        }
2168}
2169
2170static void rtw8822c_set_channel_rf(struct rtw_dev *rtwdev, u8 channel, u8 bw)
2171{
2172#define RF18_BAND_MASK          (BIT(16) | BIT(9) | BIT(8))
2173#define RF18_BAND_2G            (0)
2174#define RF18_BAND_5G            (BIT(16) | BIT(8))
2175#define RF18_CHANNEL_MASK       (MASKBYTE0)
2176#define RF18_RFSI_MASK          (BIT(18) | BIT(17))
2177#define RF18_RFSI_GE_CH80       (BIT(17))
2178#define RF18_RFSI_GT_CH140      (BIT(18))
2179#define RF18_BW_MASK            (BIT(13) | BIT(12))
2180#define RF18_BW_20M             (BIT(13) | BIT(12))
2181#define RF18_BW_40M             (BIT(13))
2182#define RF18_BW_80M             (BIT(12))
2183
2184        u32 rf_reg18 = 0;
2185        u32 rf_rxbb = 0;
2186
2187        rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
2188
2189        rf_reg18 &= ~(RF18_BAND_MASK | RF18_CHANNEL_MASK | RF18_RFSI_MASK |
2190                      RF18_BW_MASK);
2191
2192        rf_reg18 |= (IS_CH_2G_BAND(channel) ? RF18_BAND_2G : RF18_BAND_5G);
2193        rf_reg18 |= (channel & RF18_CHANNEL_MASK);
2194        if (IS_CH_5G_BAND_4(channel))
2195                rf_reg18 |= RF18_RFSI_GT_CH140;
2196        else if (IS_CH_5G_BAND_3(channel))
2197                rf_reg18 |= RF18_RFSI_GE_CH80;
2198
2199        switch (bw) {
2200        case RTW_CHANNEL_WIDTH_5:
2201        case RTW_CHANNEL_WIDTH_10:
2202        case RTW_CHANNEL_WIDTH_20:
2203        default:
2204                rf_reg18 |= RF18_BW_20M;
2205                rf_rxbb = 0x18;
2206                break;
2207        case RTW_CHANNEL_WIDTH_40:
2208                /* RF bandwidth */
2209                rf_reg18 |= RF18_BW_40M;
2210                rf_rxbb = 0x10;
2211                break;
2212        case RTW_CHANNEL_WIDTH_80:
2213                rf_reg18 |= RF18_BW_80M;
2214                rf_rxbb = 0x8;
2215                break;
2216        }
2217
2218        rtw8822c_rstb_3wire(rtwdev, false);
2219
2220        rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x01);
2221        rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, 0x1f, 0x12);
2222        rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, 0xfffff, rf_rxbb);
2223        rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, 0x04, 0x00);
2224
2225        rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x01);
2226        rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWA, 0x1f, 0x12);
2227        rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWD0, 0xfffff, rf_rxbb);
2228        rtw_write_rf(rtwdev, RF_PATH_B, RF_LUTWE2, 0x04, 0x00);
2229
2230        rtw_write_rf(rtwdev, RF_PATH_A, RF_CFGCH, RFREG_MASK, rf_reg18);
2231        rtw_write_rf(rtwdev, RF_PATH_B, RF_CFGCH, RFREG_MASK, rf_reg18);
2232
2233        rtw8822c_rstb_3wire(rtwdev, true);
2234}
2235
2236static void rtw8822c_toggle_igi(struct rtw_dev *rtwdev)
2237{
2238        u32 igi;
2239
2240        igi = rtw_read32_mask(rtwdev, REG_RXIGI, 0x7f);
2241        rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi - 2);
2242        rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi - 2);
2243        rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f, igi);
2244        rtw_write32_mask(rtwdev, REG_RXIGI, 0x7f00, igi);
2245}
2246
2247static void rtw8822c_set_channel_bb(struct rtw_dev *rtwdev, u8 channel, u8 bw,
2248                                    u8 primary_ch_idx)
2249{
2250        if (IS_CH_2G_BAND(channel)) {
2251                rtw_write32_clr(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
2252                rtw_write32_set(rtwdev, REG_TXF4, BIT(20));
2253                rtw_write32_clr(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
2254                rtw_write32_clr(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
2255                rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0xF);
2256
2257                switch (bw) {
2258                case RTW_CHANNEL_WIDTH_20:
2259                        rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
2260                                         0x5);
2261                        rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
2262                                         0x5);
2263                        rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2264                                         0x6);
2265                        rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2266                                         0x6);
2267                        break;
2268                case RTW_CHANNEL_WIDTH_40:
2269                        rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_CCK,
2270                                         0x4);
2271                        rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_CCK,
2272                                         0x4);
2273                        rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2274                                         0x0);
2275                        rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2276                                         0x0);
2277                        break;
2278                }
2279                if (channel == 13 || channel == 14)
2280                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x969);
2281                else if (channel == 11 || channel == 12)
2282                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x96a);
2283                else
2284                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x9aa);
2285                if (channel == 14) {
2286                        rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x3da0);
2287                        rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
2288                                         0x4962c931);
2289                        rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x6aa3);
2290                        rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xaa7b);
2291                        rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xf3d7);
2292                        rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD, 0x0);
2293                        rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
2294                                         0xff012455);
2295                        rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD, 0xffff);
2296                } else {
2297                        rtw_write32_mask(rtwdev, REG_TXF0, MASKHWORD, 0x5284);
2298                        rtw_write32_mask(rtwdev, REG_TXF1, MASKDWORD,
2299                                         0x3e18fec8);
2300                        rtw_write32_mask(rtwdev, REG_TXF2, MASKLWORD, 0x0a88);
2301                        rtw_write32_mask(rtwdev, REG_TXF3, MASKHWORD, 0xacc4);
2302                        rtw_write32_mask(rtwdev, REG_TXF4, MASKLWORD, 0xc8b2);
2303                        rtw_write32_mask(rtwdev, REG_TXF5, MASKDWORD,
2304                                         0x00faf0de);
2305                        rtw_write32_mask(rtwdev, REG_TXF6, MASKDWORD,
2306                                         0x00122344);
2307                        rtw_write32_mask(rtwdev, REG_TXF7, MASKDWORD,
2308                                         0x0fffffff);
2309                }
2310                if (channel == 13)
2311                        rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2312                else
2313                        rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x1);
2314        } else if (IS_CH_5G_BAND(channel)) {
2315                rtw_write32_set(rtwdev, REG_CCKTXONLY, BIT_BB_CCK_CHECK_EN);
2316                rtw_write32_set(rtwdev, REG_CCK_CHECK, BIT_CHECK_CCK_EN);
2317                rtw_write32_set(rtwdev, REG_BGCTRL, BITS_RX_IQ_WEIGHT);
2318                rtw_write32_clr(rtwdev, REG_TXF4, BIT(20));
2319                rtw_write32_mask(rtwdev, REG_CCAMSK, 0x3F000000, 0x22);
2320                rtw_write32_mask(rtwdev, REG_TXDFIR0, 0x70, 0x3);
2321                if (IS_CH_5G_BAND_1(channel) || IS_CH_5G_BAND_2(channel)) {
2322                        rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2323                                         0x1);
2324                        rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2325                                         0x1);
2326                } else if (IS_CH_5G_BAND_3(channel)) {
2327                        rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2328                                         0x2);
2329                        rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2330                                         0x2);
2331                } else if (IS_CH_5G_BAND_4(channel)) {
2332                        rtw_write32_mask(rtwdev, REG_RXAGCCTL0, BITS_RXAGC_OFDM,
2333                                         0x3);
2334                        rtw_write32_mask(rtwdev, REG_RXAGCCTL, BITS_RXAGC_OFDM,
2335                                         0x3);
2336                }
2337
2338                if (channel >= 36 && channel <= 51)
2339                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x494);
2340                else if (channel >= 52 && channel <= 55)
2341                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x493);
2342                else if (channel >= 56 && channel <= 111)
2343                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x453);
2344                else if (channel >= 112 && channel <= 119)
2345                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x452);
2346                else if (channel >= 120 && channel <= 172)
2347                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x412);
2348                else if (channel >= 173 && channel <= 177)
2349                        rtw_write32_mask(rtwdev, REG_SCOTRK, 0xfff, 0x411);
2350        }
2351
2352        switch (bw) {
2353        case RTW_CHANNEL_WIDTH_20:
2354                rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x19B);
2355                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2356                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x0);
2357                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x7);
2358                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x6);
2359                rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2360                rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2361                rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2362                break;
2363        case RTW_CHANNEL_WIDTH_40:
2364                rtw_write32_mask(rtwdev, REG_CCKSB, BIT(4),
2365                                 (primary_ch_idx == RTW_SC_20_UPPER ? 1 : 0));
2366                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x5);
2367                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2368                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2369                                 (primary_ch_idx | (primary_ch_idx << 4)));
2370                rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x1);
2371                rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2372                rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2373                break;
2374        case RTW_CHANNEL_WIDTH_80:
2375                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0xa);
2376                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xc0, 0x0);
2377                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xff00,
2378                                 (primary_ch_idx | (primary_ch_idx << 4)));
2379                rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x6);
2380                rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x1);
2381                break;
2382        case RTW_CHANNEL_WIDTH_5:
2383                rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2384                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2385                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x1);
2386                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x4);
2387                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x4);
2388                rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2389                rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2390                rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2391                break;
2392        case RTW_CHANNEL_WIDTH_10:
2393                rtw_write32_mask(rtwdev, REG_DFIRBW, 0x3FF0, 0x2AB);
2394                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xf, 0x0);
2395                rtw_write32_mask(rtwdev, REG_TXBWCTL, 0xffc0, 0x2);
2396                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700, 0x6);
2397                rtw_write32_mask(rtwdev, REG_TXCLK, 0x700000, 0x5);
2398                rtw_write32_mask(rtwdev, REG_CCK_SOURCE, BIT_NBI_EN, 0x0);
2399                rtw_write32_mask(rtwdev, REG_SBD, BITS_SUBTUNE, 0x1);
2400                rtw_write32_mask(rtwdev, REG_PT_CHSMO, BIT_PT_OPT, 0x0);
2401                break;
2402        }
2403}
2404
2405static void rtw8822c_set_channel(struct rtw_dev *rtwdev, u8 channel, u8 bw,
2406                                 u8 primary_chan_idx)
2407{
2408        rtw8822c_set_channel_bb(rtwdev, channel, bw, primary_chan_idx);
2409        rtw_set_channel_mac(rtwdev, channel, bw, primary_chan_idx);
2410        rtw8822c_set_channel_rf(rtwdev, channel, bw);
2411        rtw8822c_toggle_igi(rtwdev);
2412}
2413
2414static void rtw8822c_config_cck_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2415{
2416        if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
2417                rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x0);
2418                rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x0);
2419        } else if (rx_path == BB_PATH_AB) {
2420                rtw_write32_mask(rtwdev, REG_CCANRX, 0x00600000, 0x1);
2421                rtw_write32_mask(rtwdev, REG_CCANRX, 0x00060000, 0x1);
2422        }
2423
2424        if (rx_path == BB_PATH_A)
2425                rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x0);
2426        else if (rx_path == BB_PATH_B)
2427                rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x5);
2428        else if (rx_path == BB_PATH_AB)
2429                rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0x0f000000, 0x1);
2430}
2431
2432static void rtw8822c_config_ofdm_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2433{
2434        if (rx_path == BB_PATH_A || rx_path == BB_PATH_B) {
2435                rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x0);
2436                rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x0);
2437                rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x0);
2438                rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x0);
2439                rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x0);
2440        } else if (rx_path == BB_PATH_AB) {
2441                rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x300, 0x1);
2442                rtw_write32_mask(rtwdev, REG_RXFNCTL, 0x600000, 0x1);
2443                rtw_write32_mask(rtwdev, REG_AGCSWSH, BIT(17), 0x1);
2444                rtw_write32_mask(rtwdev, REG_ANTWTPD, BIT(20), 0x1);
2445                rtw_write32_mask(rtwdev, REG_MRCM, BIT(24), 0x1);
2446        }
2447
2448        rtw_write32_mask(rtwdev, 0x824, 0x0f000000, rx_path);
2449        rtw_write32_mask(rtwdev, 0x824, 0x000f0000, rx_path);
2450}
2451
2452static void rtw8822c_config_rx_path(struct rtw_dev *rtwdev, u8 rx_path)
2453{
2454        rtw8822c_config_cck_rx_path(rtwdev, rx_path);
2455        rtw8822c_config_ofdm_rx_path(rtwdev, rx_path);
2456}
2457
2458static void rtw8822c_config_cck_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2459                                        bool is_tx2_path)
2460{
2461        if (tx_path == BB_PATH_A) {
2462                rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2463        } else if (tx_path == BB_PATH_B) {
2464                rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x4);
2465        } else {
2466                if (is_tx2_path)
2467                        rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0xc);
2468                else
2469                        rtw_write32_mask(rtwdev, REG_RXCCKSEL, 0xf0000000, 0x8);
2470        }
2471        rtw8822c_bb_reset(rtwdev);
2472}
2473
2474static void rtw8822c_config_ofdm_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2475                                         enum rtw_bb_path tx_path_sel_1ss)
2476{
2477        if (tx_path == BB_PATH_A) {
2478                rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x11);
2479                rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2480        } else if (tx_path == BB_PATH_B) {
2481                rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x12);
2482                rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xff, 0x0);
2483        } else {
2484                if (tx_path_sel_1ss == BB_PATH_AB) {
2485                        rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x33);
2486                        rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0404);
2487                } else if (tx_path_sel_1ss == BB_PATH_B) {
2488                        rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x32);
2489                        rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2490                } else if (tx_path_sel_1ss == BB_PATH_A) {
2491                        rtw_write32_mask(rtwdev, REG_ANTMAP0, 0xff, 0x31);
2492                        rtw_write32_mask(rtwdev, REG_TXLGMAP, 0xffff, 0x0400);
2493                }
2494        }
2495        rtw8822c_bb_reset(rtwdev);
2496}
2497
2498static void rtw8822c_config_tx_path(struct rtw_dev *rtwdev, u8 tx_path,
2499                                    enum rtw_bb_path tx_path_sel_1ss,
2500                                    enum rtw_bb_path tx_path_cck,
2501                                    bool is_tx2_path)
2502{
2503        rtw8822c_config_cck_tx_path(rtwdev, tx_path_cck, is_tx2_path);
2504        rtw8822c_config_ofdm_tx_path(rtwdev, tx_path, tx_path_sel_1ss);
2505        rtw8822c_bb_reset(rtwdev);
2506}
2507
2508static void rtw8822c_config_trx_mode(struct rtw_dev *rtwdev, u8 tx_path,
2509                                     u8 rx_path, bool is_tx2_path)
2510{
2511        if ((tx_path | rx_path) & BB_PATH_A)
2512                rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x33312);
2513        else
2514                rtw_write32_mask(rtwdev, REG_ORITXCODE, MASK20BITS, 0x11111);
2515        if ((tx_path | rx_path) & BB_PATH_B)
2516                rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x33312);
2517        else
2518                rtw_write32_mask(rtwdev, REG_ORITXCODE2, MASK20BITS, 0x11111);
2519
2520        rtw8822c_config_rx_path(rtwdev, rx_path);
2521        rtw8822c_config_tx_path(rtwdev, tx_path, BB_PATH_A, BB_PATH_A,
2522                                is_tx2_path);
2523
2524        rtw8822c_toggle_igi(rtwdev);
2525}
2526
2527static void query_phy_status_page0(struct rtw_dev *rtwdev, u8 *phy_status,
2528                                   struct rtw_rx_pkt_stat *pkt_stat)
2529{
2530        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2531        u8 l_bnd, u_bnd;
2532        u8 gain_a, gain_b;
2533        s8 rx_power[RTW_RF_PATH_MAX];
2534        s8 min_rx_power = -120;
2535        u8 rssi;
2536        int path;
2537
2538        rx_power[RF_PATH_A] = GET_PHY_STAT_P0_PWDB_A(phy_status);
2539        rx_power[RF_PATH_B] = GET_PHY_STAT_P0_PWDB_B(phy_status);
2540        l_bnd = dm_info->cck_gi_l_bnd;
2541        u_bnd = dm_info->cck_gi_u_bnd;
2542        gain_a = GET_PHY_STAT_P0_GAIN_A(phy_status);
2543        gain_b = GET_PHY_STAT_P0_GAIN_B(phy_status);
2544        if (gain_a < l_bnd)
2545                rx_power[RF_PATH_A] += (l_bnd - gain_a) << 1;
2546        else if (gain_a > u_bnd)
2547                rx_power[RF_PATH_A] -= (gain_a - u_bnd) << 1;
2548        if (gain_b < l_bnd)
2549                rx_power[RF_PATH_B] += (l_bnd - gain_b) << 1;
2550        else if (gain_b > u_bnd)
2551                rx_power[RF_PATH_B] -= (gain_b - u_bnd) << 1;
2552
2553        rx_power[RF_PATH_A] -= 110;
2554        rx_power[RF_PATH_B] -= 110;
2555
2556        pkt_stat->rx_power[RF_PATH_A] = rx_power[RF_PATH_A];
2557        pkt_stat->rx_power[RF_PATH_B] = rx_power[RF_PATH_B];
2558
2559        for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2560                rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2561                dm_info->rssi[path] = rssi;
2562        }
2563
2564        pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 1);
2565        pkt_stat->bw = RTW_CHANNEL_WIDTH_20;
2566        pkt_stat->signal_power = max(pkt_stat->rx_power[RF_PATH_A],
2567                                     min_rx_power);
2568}
2569
2570static void query_phy_status_page1(struct rtw_dev *rtwdev, u8 *phy_status,
2571                                   struct rtw_rx_pkt_stat *pkt_stat)
2572{
2573        struct rtw_path_div *p_div = &rtwdev->dm_path_div;
2574        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2575        u8 rxsc, bw;
2576        s8 min_rx_power = -120;
2577        s8 rx_evm;
2578        u8 evm_dbm = 0;
2579        u8 rssi;
2580        int path;
2581
2582        if (pkt_stat->rate > DESC_RATE11M && pkt_stat->rate < DESC_RATEMCS0)
2583                rxsc = GET_PHY_STAT_P1_L_RXSC(phy_status);
2584        else
2585                rxsc = GET_PHY_STAT_P1_HT_RXSC(phy_status);
2586
2587        if (rxsc >= 9 && rxsc <= 12)
2588                bw = RTW_CHANNEL_WIDTH_40;
2589        else if (rxsc >= 13)
2590                bw = RTW_CHANNEL_WIDTH_80;
2591        else
2592                bw = RTW_CHANNEL_WIDTH_20;
2593
2594        pkt_stat->rx_power[RF_PATH_A] = GET_PHY_STAT_P1_PWDB_A(phy_status) - 110;
2595        pkt_stat->rx_power[RF_PATH_B] = GET_PHY_STAT_P1_PWDB_B(phy_status) - 110;
2596        pkt_stat->rssi = rtw_phy_rf_power_2_rssi(pkt_stat->rx_power, 2);
2597        pkt_stat->bw = bw;
2598        pkt_stat->signal_power = max3(pkt_stat->rx_power[RF_PATH_A],
2599                                      pkt_stat->rx_power[RF_PATH_B],
2600                                      min_rx_power);
2601
2602        dm_info->curr_rx_rate = pkt_stat->rate;
2603
2604        pkt_stat->rx_evm[RF_PATH_A] = GET_PHY_STAT_P1_RXEVM_A(phy_status);
2605        pkt_stat->rx_evm[RF_PATH_B] = GET_PHY_STAT_P1_RXEVM_B(phy_status);
2606
2607        pkt_stat->rx_snr[RF_PATH_A] = GET_PHY_STAT_P1_RXSNR_A(phy_status);
2608        pkt_stat->rx_snr[RF_PATH_B] = GET_PHY_STAT_P1_RXSNR_B(phy_status);
2609
2610        pkt_stat->cfo_tail[RF_PATH_A] = GET_PHY_STAT_P1_CFO_TAIL_A(phy_status);
2611        pkt_stat->cfo_tail[RF_PATH_B] = GET_PHY_STAT_P1_CFO_TAIL_B(phy_status);
2612
2613        for (path = 0; path <= rtwdev->hal.rf_path_num; path++) {
2614                rssi = rtw_phy_rf_power_2_rssi(&pkt_stat->rx_power[path], 1);
2615                dm_info->rssi[path] = rssi;
2616                if (path == RF_PATH_A) {
2617                        p_div->path_a_sum += rssi;
2618                        p_div->path_a_cnt++;
2619                } else if (path == RF_PATH_B) {
2620                        p_div->path_b_sum += rssi;
2621                        p_div->path_b_cnt++;
2622                }
2623                dm_info->rx_snr[path] = pkt_stat->rx_snr[path] >> 1;
2624                dm_info->cfo_tail[path] = (pkt_stat->cfo_tail[path] * 5) >> 1;
2625
2626                rx_evm = pkt_stat->rx_evm[path];
2627
2628                if (rx_evm < 0) {
2629                        if (rx_evm == S8_MIN)
2630                                evm_dbm = 0;
2631                        else
2632                                evm_dbm = ((u8)-rx_evm >> 1);
2633                }
2634                dm_info->rx_evm_dbm[path] = evm_dbm;
2635        }
2636        rtw_phy_parsing_cfo(rtwdev, pkt_stat);
2637}
2638
2639static void query_phy_status(struct rtw_dev *rtwdev, u8 *phy_status,
2640                             struct rtw_rx_pkt_stat *pkt_stat)
2641{
2642        u8 page;
2643
2644        page = *phy_status & 0xf;
2645
2646        switch (page) {
2647        case 0:
2648                query_phy_status_page0(rtwdev, phy_status, pkt_stat);
2649                break;
2650        case 1:
2651                query_phy_status_page1(rtwdev, phy_status, pkt_stat);
2652                break;
2653        default:
2654                rtw_warn(rtwdev, "unused phy status page (%d)\n", page);
2655                return;
2656        }
2657}
2658
2659static void rtw8822c_query_rx_desc(struct rtw_dev *rtwdev, u8 *rx_desc,
2660                                   struct rtw_rx_pkt_stat *pkt_stat,
2661                                   struct ieee80211_rx_status *rx_status)
2662{
2663        struct ieee80211_hdr *hdr;
2664        u32 desc_sz = rtwdev->chip->rx_pkt_desc_sz;
2665        u8 *phy_status = NULL;
2666
2667        memset(pkt_stat, 0, sizeof(*pkt_stat));
2668
2669        pkt_stat->phy_status = GET_RX_DESC_PHYST(rx_desc);
2670        pkt_stat->icv_err = GET_RX_DESC_ICV_ERR(rx_desc);
2671        pkt_stat->crc_err = GET_RX_DESC_CRC32(rx_desc);
2672        pkt_stat->decrypted = !GET_RX_DESC_SWDEC(rx_desc) &&
2673                              GET_RX_DESC_ENC_TYPE(rx_desc) != RX_DESC_ENC_NONE;
2674        pkt_stat->is_c2h = GET_RX_DESC_C2H(rx_desc);
2675        pkt_stat->pkt_len = GET_RX_DESC_PKT_LEN(rx_desc);
2676        pkt_stat->drv_info_sz = GET_RX_DESC_DRV_INFO_SIZE(rx_desc);
2677        pkt_stat->shift = GET_RX_DESC_SHIFT(rx_desc);
2678        pkt_stat->rate = GET_RX_DESC_RX_RATE(rx_desc);
2679        pkt_stat->cam_id = GET_RX_DESC_MACID(rx_desc);
2680        pkt_stat->ppdu_cnt = GET_RX_DESC_PPDU_CNT(rx_desc);
2681        pkt_stat->tsf_low = GET_RX_DESC_TSFL(rx_desc);
2682
2683        /* drv_info_sz is in unit of 8-bytes */
2684        pkt_stat->drv_info_sz *= 8;
2685
2686        /* c2h cmd pkt's rx/phy status is not interested */
2687        if (pkt_stat->is_c2h)
2688                return;
2689
2690        hdr = (struct ieee80211_hdr *)(rx_desc + desc_sz + pkt_stat->shift +
2691                                       pkt_stat->drv_info_sz);
2692        pkt_stat->hdr = hdr;
2693        if (pkt_stat->phy_status) {
2694                phy_status = rx_desc + desc_sz + pkt_stat->shift;
2695                query_phy_status(rtwdev, phy_status, pkt_stat);
2696        }
2697
2698        rtw_rx_fill_rx_status(rtwdev, pkt_stat, hdr, rx_status, phy_status);
2699}
2700
2701static void
2702rtw8822c_set_write_tx_power_ref(struct rtw_dev *rtwdev, u8 *tx_pwr_ref_cck,
2703                                u8 *tx_pwr_ref_ofdm)
2704{
2705        struct rtw_hal *hal = &rtwdev->hal;
2706        u32 txref_cck[2] = {0x18a0, 0x41a0};
2707        u32 txref_ofdm[2] = {0x18e8, 0x41e8};
2708        u8 path;
2709
2710        for (path = 0; path < hal->rf_path_num; path++) {
2711                rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2712                rtw_write32_mask(rtwdev, txref_cck[path], 0x7f0000,
2713                                 tx_pwr_ref_cck[path]);
2714        }
2715        for (path = 0; path < hal->rf_path_num; path++) {
2716                rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0);
2717                rtw_write32_mask(rtwdev, txref_ofdm[path], 0x1fc00,
2718                                 tx_pwr_ref_ofdm[path]);
2719        }
2720}
2721
2722static void rtw8822c_set_tx_power_diff(struct rtw_dev *rtwdev, u8 rate,
2723                                       s8 *diff_idx)
2724{
2725        u32 offset_txagc = 0x3a00;
2726        u8 rate_idx = rate & 0xfc;
2727        u8 pwr_idx[4];
2728        u32 phy_pwr_idx;
2729        int i;
2730
2731        for (i = 0; i < 4; i++)
2732                pwr_idx[i] = diff_idx[i] & 0x7f;
2733
2734        phy_pwr_idx = pwr_idx[0] |
2735                      (pwr_idx[1] << 8) |
2736                      (pwr_idx[2] << 16) |
2737                      (pwr_idx[3] << 24);
2738
2739        rtw_write32_mask(rtwdev, 0x1c90, BIT(15), 0x0);
2740        rtw_write32_mask(rtwdev, offset_txagc + rate_idx, MASKDWORD,
2741                         phy_pwr_idx);
2742}
2743
2744static void rtw8822c_set_tx_power_index(struct rtw_dev *rtwdev)
2745{
2746        struct rtw_hal *hal = &rtwdev->hal;
2747        u8 rs, rate, j;
2748        u8 pwr_ref_cck[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATE11M],
2749                             hal->tx_pwr_tbl[RF_PATH_B][DESC_RATE11M]};
2750        u8 pwr_ref_ofdm[2] = {hal->tx_pwr_tbl[RF_PATH_A][DESC_RATEMCS7],
2751                              hal->tx_pwr_tbl[RF_PATH_B][DESC_RATEMCS7]};
2752        s8 diff_a, diff_b;
2753        u8 pwr_a, pwr_b;
2754        s8 diff_idx[4];
2755
2756        rtw8822c_set_write_tx_power_ref(rtwdev, pwr_ref_cck, pwr_ref_ofdm);
2757        for (rs = 0; rs < RTW_RATE_SECTION_MAX; rs++) {
2758                for (j = 0; j < rtw_rate_size[rs]; j++) {
2759                        rate = rtw_rate_section[rs][j];
2760                        pwr_a = hal->tx_pwr_tbl[RF_PATH_A][rate];
2761                        pwr_b = hal->tx_pwr_tbl[RF_PATH_B][rate];
2762                        if (rs == 0) {
2763                                diff_a = (s8)pwr_a - (s8)pwr_ref_cck[0];
2764                                diff_b = (s8)pwr_b - (s8)pwr_ref_cck[1];
2765                        } else {
2766                                diff_a = (s8)pwr_a - (s8)pwr_ref_ofdm[0];
2767                                diff_b = (s8)pwr_b - (s8)pwr_ref_ofdm[1];
2768                        }
2769                        diff_idx[rate % 4] = min(diff_a, diff_b);
2770                        if (rate % 4 == 3)
2771                                rtw8822c_set_tx_power_diff(rtwdev, rate - 3,
2772                                                           diff_idx);
2773                }
2774        }
2775}
2776
2777static int rtw8822c_set_antenna(struct rtw_dev *rtwdev,
2778                                u32 antenna_tx,
2779                                u32 antenna_rx)
2780{
2781        struct rtw_hal *hal = &rtwdev->hal;
2782
2783        switch (antenna_tx) {
2784        case BB_PATH_A:
2785        case BB_PATH_B:
2786        case BB_PATH_AB:
2787                break;
2788        default:
2789                rtw_info(rtwdev, "unsupported tx path 0x%x\n", antenna_tx);
2790                return -EINVAL;
2791        }
2792
2793        /* path B only is not available for RX */
2794        switch (antenna_rx) {
2795        case BB_PATH_A:
2796        case BB_PATH_AB:
2797                break;
2798        default:
2799                rtw_info(rtwdev, "unsupported rx path 0x%x\n", antenna_rx);
2800                return -EINVAL;
2801        }
2802
2803        hal->antenna_tx = antenna_tx;
2804        hal->antenna_rx = antenna_rx;
2805
2806        rtw8822c_config_trx_mode(rtwdev, antenna_tx, antenna_rx, false);
2807
2808        return 0;
2809}
2810
2811static void rtw8822c_cfg_ldo25(struct rtw_dev *rtwdev, bool enable)
2812{
2813        u8 ldo_pwr;
2814
2815        ldo_pwr = rtw_read8(rtwdev, REG_ANAPARLDO_POW_MAC);
2816        ldo_pwr = enable ? ldo_pwr | BIT_LDOE25_PON : ldo_pwr & ~BIT_LDOE25_PON;
2817        rtw_write8(rtwdev, REG_ANAPARLDO_POW_MAC, ldo_pwr);
2818}
2819
2820static void rtw8822c_false_alarm_statistics(struct rtw_dev *rtwdev)
2821{
2822        struct rtw_dm_info *dm_info = &rtwdev->dm_info;
2823        u32 cck_enable;
2824        u32 cck_fa_cnt;
2825        u32 crc32_cnt;
2826        u32 cca32_cnt;
2827        u32 ofdm_fa_cnt;
2828        u32 ofdm_fa_cnt1, ofdm_fa_cnt2, ofdm_fa_cnt3, ofdm_fa_cnt4, ofdm_fa_cnt5;
2829        u16 parity_fail, rate_illegal, crc8_fail, mcs_fail, sb_search_fail,
2830            fast_fsync, crc8_fail_vhta, mcs_fail_vht;
2831
2832        cck_enable = rtw_read32(rtwdev, REG_ENCCK) & BIT_CCK_BLK_EN;
2833        cck_fa_cnt = rtw_read16(rtwdev, REG_CCK_FACNT);
2834
2835        ofdm_fa_cnt1 = rtw_read32(rtwdev, REG_OFDM_FACNT1);
2836        ofdm_fa_cnt2 = rtw_read32(rtwdev, REG_OFDM_FACNT2);
2837        ofdm_fa_cnt3 = rtw_read32(rtwdev, REG_OFDM_FACNT3);
2838        ofdm_fa_cnt4 = rtw_read32(rtwdev, REG_OFDM_FACNT4);
2839        ofdm_fa_cnt5 = rtw_read32(rtwdev, REG_OFDM_FACNT5);
2840
2841        parity_fail     = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt1);
2842        rate_illegal    = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt2);
2843        crc8_fail       = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt2);
2844        crc8_fail_vhta  = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt3);
2845        mcs_fail        = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt4);
2846        mcs_fail_vht    = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt4);
2847        fast_fsync      = FIELD_GET(GENMASK(15, 0), ofdm_fa_cnt5);
2848        sb_search_fail  = FIELD_GET(GENMASK(31, 16), ofdm_fa_cnt5);
2849
2850        ofdm_fa_cnt = parity_fail + rate_illegal + crc8_fail + crc8_fail_vhta +
2851                      mcs_fail + mcs_fail_vht + fast_fsync + sb_search_fail;
2852
2853        dm_info->cck_fa_cnt = cck_fa_cnt;
2854        dm_info->ofdm_fa_cnt = ofdm_fa_cnt;
2855        dm_info->total_fa_cnt = ofdm_fa_cnt;
2856        dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0;
2857
2858        crc32_cnt = rtw_read32(rtwdev, 0x2c04);
2859        dm_info->cck_ok_cnt = crc32_cnt & 0xffff;
2860        dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2861        crc32_cnt = rtw_read32(rtwdev, 0x2c14);
2862        dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff;
2863        dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2864        crc32_cnt = rtw_read32(rtwdev, 0x2c10);
2865        dm_info->ht_ok_cnt = crc32_cnt & 0xffff;
2866        dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2867        crc32_cnt = rtw_read32(rtwdev, 0x2c0c);
2868        dm_info->vht_ok_cnt = crc32_cnt & 0xffff;
2869        dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16;
2870
2871        cca32_cnt = rtw_read32(rtwdev, 0x2c08);
2872        dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16);
2873        dm_info->cck_cca_cnt = cca32_cnt & 0xffff;
2874        dm_info->total_cca_cnt = dm_info->ofdm_cca_cnt;
2875        if (cck_enable)
2876                dm_info->total_cca_cnt += dm_info->cck_cca_cnt;
2877
2878        rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 0);
2879        rtw_write32_mask(rtwdev, REG_CCANRX, BIT_CCK_FA_RST, 2);
2880        rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 0);
2881        rtw_write32_mask(rtwdev, REG_CCANRX, BIT_OFDM_FA_RST, 2);
2882
2883        /* disable rx clk gating to reset counters */
2884        rtw_write32_clr(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2885        rtw_write32_set(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2886        rtw_write32_clr(rtwdev, REG_CNT_CTRL, BIT_ALL_CNT_RST);
2887        rtw_write32_set(rtwdev, REG_RX_BREAK, BIT_COM_RX_GCK_EN);
2888}
2889
2890static void rtw8822c_do_lck(struct rtw_dev *rtwdev)
2891{
2892        u32 val;
2893
2894        rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2895        rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0FA);
2896        fsleep(1);
2897        rtw_write_rf(rtwdev, RF_PATH_A, RF_AAC_CTRL, RFREG_MASK, 0x80000);
2898        rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_AAC, RFREG_MASK, 0x80001);
2899        read_poll_timeout(rtw_read_rf, val, val != 0x1, 1000, 100000,
2900                          true, rtwdev, RF_PATH_A, RF_AAC_CTRL, 0x1000);
2901        rtw_write_rf(rtwdev, RF_PATH_A, RF_SYN_PFD, RFREG_MASK, 0x1F0F8);
2902        rtw_write_rf(rtwdev, RF_PATH_B, RF_SYN_CTRL, RFREG_MASK, 0x80010);
2903
2904        rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2905        rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x4f000);
2906        fsleep(1);
2907        rtw_write_rf(rtwdev, RF_PATH_A, RF_FAST_LCK, RFREG_MASK, 0x0f000);
2908}
2909
2910static void rtw8822c_do_iqk(struct rtw_dev *rtwdev)
2911{
2912        struct rtw_iqk_para para = {0};
2913        u8 iqk_chk;
2914        int ret;
2915
2916        para.clear = 1;
2917        rtw_fw_do_iqk(rtwdev, &para);
2918
2919        ret = read_poll_timeout(rtw_read8, iqk_chk, iqk_chk == IQK_DONE_8822C,
2920                                20000, 300000, false, rtwdev, REG_RPT_CIP);
2921        if (ret)
2922                rtw_warn(rtwdev, "failed to poll iqk status bit\n");
2923
2924        rtw_write8(rtwdev, REG_IQKSTAT, 0x0);
2925}
2926
2927/* for coex */
2928static void rtw8822c_coex_cfg_init(struct rtw_dev *rtwdev)
2929{
2930        /* enable TBTT nterrupt */
2931        rtw_write8_set(rtwdev, REG_BCN_CTRL, BIT_EN_BCN_FUNCTION);
2932
2933        /* BT report packet sample rate */
2934        /* 0x790[5:0]=0x5 */
2935        rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5);
2936
2937        /* enable BT counter statistics */
2938        rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1);
2939
2940        /* enable PTA (3-wire function form BT side) */
2941        rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_BT_PTA_EN);
2942        rtw_write32_set(rtwdev, REG_GPIO_MUXCFG, BIT_PO_BT_PTA_PINS);
2943
2944        /* enable PTA (tx/rx signal form WiFi side) */
2945        rtw_write8_set(rtwdev, REG_QUEUE_CTRL, BIT_PTA_WL_TX_EN);
2946        /* wl tx signal to PTA not case EDCCA */
2947        rtw_write8_clr(rtwdev, REG_QUEUE_CTRL, BIT_PTA_EDCCA_EN);
2948        /* GNT_BT=1 while select both */
2949        rtw_write16_set(rtwdev, REG_BT_COEX_V2, BIT_GNT_BT_POLARITY);
2950        /* BT_CCA = ~GNT_WL_BB, not or GNT_BT_BB, LTE_Rx */
2951        rtw_write8_clr(rtwdev, REG_DUMMY_PAGE4_V1, BIT_BTCCA_CTRL);
2952
2953        /* to avoid RF parameter error */
2954        rtw_write_rf(rtwdev, RF_PATH_B, RF_MODOPT, 0xfffff, 0x40000);
2955}
2956
2957static void rtw8822c_coex_cfg_gnt_fix(struct rtw_dev *rtwdev)
2958{
2959        struct rtw_coex *coex = &rtwdev->coex;
2960        struct rtw_coex_stat *coex_stat = &coex->stat;
2961        struct rtw_efuse *efuse = &rtwdev->efuse;
2962        u32 rf_0x1;
2963
2964        if (coex_stat->gnt_workaround_state == coex_stat->wl_coex_mode)
2965                return;
2966
2967        coex_stat->gnt_workaround_state = coex_stat->wl_coex_mode;
2968
2969        if ((coex_stat->kt_ver == 0 && coex->under_5g) || coex->freerun)
2970                rf_0x1 = 0x40021;
2971        else
2972                rf_0x1 = 0x40000;
2973
2974        /* BT at S1 for Shared-Ant */
2975        if (efuse->share_ant)
2976                rf_0x1 |= BIT(13);
2977
2978        rtw_write_rf(rtwdev, RF_PATH_B, 0x1, 0xfffff, rf_0x1);
2979
2980        /* WL-S0 2G RF TRX cannot be masked by GNT_BT
2981         * enable "WLS0 BB chage RF mode if GNT_BT = 1" for shared-antenna type
2982         * disable:0x1860[3] = 1, enable:0x1860[3] = 0
2983         *
2984         * enable "DAC off if GNT_WL = 0" for non-shared-antenna
2985         * disable 0x1c30[22] = 0,
2986         * enable: 0x1c30[22] = 1, 0x1c38[12] = 0, 0x1c38[28] = 1
2987         *
2988         * disable WL-S1 BB chage RF mode if GNT_BT
2989         * since RF TRx mask can do it
2990         */
2991        rtw_write8_mask(rtwdev, REG_ANAPAR + 2, BIT_ANAPAR_BTPS >> 16, 1);
2992        rtw_write8_mask(rtwdev, REG_RSTB_SEL + 1, BIT_DAC_OFF_ENABLE, 0);
2993        rtw_write8_mask(rtwdev, REG_RSTB_SEL + 3, BIT_DAC_OFF_ENABLE, 1);
2994        rtw_write8_mask(rtwdev, REG_IGN_GNTBT4, BIT_PI_IGNORE_GNT_BT, 1);
2995
2996        /* disable WL-S0 BB chage RF mode if wifi is at 5G,
2997         * or antenna path is separated
2998         */
2999        if (coex_stat->wl_coex_mode == COEX_WLINK_5G ||
3000            coex->under_5g || !efuse->share_ant) {
3001                if (coex_stat->kt_ver >= 3) {
3002                        rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3003                                        BIT_PI_IGNORE_GNT_BT, 0);
3004                        rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3005                                        BIT_NOMASK_TXBT_ENABLE, 1);
3006                } else {
3007                        rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3008                                        BIT_PI_IGNORE_GNT_BT, 1);
3009                }
3010        } else {
3011                /* shared-antenna */
3012                rtw_write8_mask(rtwdev, REG_IGN_GNT_BT1,
3013                                BIT_PI_IGNORE_GNT_BT, 0);
3014                if (coex_stat->kt_ver >= 3) {
3015                        rtw_write8_mask(rtwdev, REG_NOMASK_TXBT,
3016                                        BIT_NOMASK_TXBT_ENABLE, 0);
3017                }
3018        }
3019}
3020
3021static void rtw8822c_coex_cfg_gnt_debug(struct rtw_dev *rtwdev)
3022{
3023        rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0);
3024        rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0);
3025        rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0);
3026        rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0);
3027        rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0);
3028}
3029
3030static void rtw8822c_coex_cfg_rfe_type(struct rtw_dev *rtwdev)
3031{
3032        struct rtw_coex *coex = &rtwdev->coex;
3033        struct rtw_coex_rfe *coex_rfe = &coex->rfe;
3034        struct rtw_efuse *efuse = &rtwdev->efuse;
3035
3036        coex_rfe->rfe_module_type = rtwdev->efuse.rfe_option;
3037        coex_rfe->ant_switch_polarity = 0;
3038        coex_rfe->ant_switch_exist = false;
3039        coex_rfe->ant_switch_with_bt = false;
3040        coex_rfe->ant_switch_diversity = false;
3041
3042        if (efuse->share_ant)
3043                coex_rfe->wlg_at_btg = true;
3044        else
3045                coex_rfe->wlg_at_btg = false;
3046
3047        /* disable LTE coex in wifi side */
3048        rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0x0);
3049        rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff);
3050        rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff);
3051}
3052
3053static void rtw8822c_coex_cfg_wl_tx_power(struct rtw_dev *rtwdev, u8 wl_pwr)
3054{
3055        struct rtw_coex *coex = &rtwdev->coex;
3056        struct rtw_coex_dm *coex_dm = &coex->dm;
3057
3058        if (wl_pwr == coex_dm->cur_wl_pwr_lvl)
3059                return;
3060
3061        coex_dm->cur_wl_pwr_lvl = wl_pwr;
3062}
3063
3064static void rtw8822c_coex_cfg_wl_rx_gain(struct rtw_dev *rtwdev, bool low_gain)
3065{
3066        struct rtw_coex *coex = &rtwdev->coex;
3067        struct rtw_coex_dm *coex_dm = &coex->dm;
3068
3069        if (low_gain == coex_dm->cur_wl_rx_low_gain_en)
3070                return;
3071
3072        coex_dm->cur_wl_rx_low_gain_en = low_gain;
3073
3074        if (coex_dm->cur_wl_rx_low_gain_en) {
3075                rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table On!\n");
3076
3077                /* set Rx filter corner RCK offset */
3078                rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x22);
3079                rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x36);
3080                rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x22);
3081                rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x36);
3082
3083        } else {
3084                rtw_dbg(rtwdev, RTW_DBG_COEX, "[BTCoex], Hi-Li Table Off!\n");
3085
3086                /* set Rx filter corner RCK offset */
3087                rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, RFREG_MASK, 0x20);
3088                rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, RFREG_MASK, 0x0);
3089                rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, RFREG_MASK, 0x20);
3090                rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, RFREG_MASK, 0x0);
3091        }
3092}
3093
3094static void rtw8822c_bf_enable_bfee_su(struct rtw_dev *rtwdev,
3095                                       struct rtw_vif *vif,
3096                                       struct rtw_bfee *bfee)
3097{
3098        u8 csi_rsc = 0;
3099        u32 tmp6dc;
3100
3101        rtw_bf_enable_bfee_su(rtwdev, vif, bfee);
3102
3103        tmp6dc = rtw_read32(rtwdev, REG_BBPSF_CTRL) |
3104                            BIT_WMAC_USE_NDPARATE |
3105                            (csi_rsc << 13);
3106        if (vif->net_type == RTW_NET_AP_MODE)
3107                rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc | BIT(12));
3108        else
3109                rtw_write32(rtwdev, REG_BBPSF_CTRL, tmp6dc & ~BIT(12));
3110
3111        rtw_write32(rtwdev, REG_CSI_RRSR, 0x550);
3112}
3113
3114static void rtw8822c_bf_config_bfee_su(struct rtw_dev *rtwdev,
3115                                       struct rtw_vif *vif,
3116                                       struct rtw_bfee *bfee, bool enable)
3117{
3118        if (enable)
3119                rtw8822c_bf_enable_bfee_su(rtwdev, vif, bfee);
3120        else
3121                rtw_bf_remove_bfee_su(rtwdev, bfee);
3122}
3123
3124static void rtw8822c_bf_config_bfee_mu(struct rtw_dev *rtwdev,
3125                                       struct rtw_vif *vif,
3126                                       struct rtw_bfee *bfee, bool enable)
3127{
3128        if (enable)
3129                rtw_bf_enable_bfee_mu(rtwdev, vif, bfee);
3130        else
3131                rtw_bf_remove_bfee_mu(rtwdev, bfee);
3132}
3133
3134static void rtw8822c_bf_config_bfee(struct rtw_dev *rtwdev, struct rtw_vif *vif,
3135                                    struct rtw_bfee *bfee, bool enable)
3136{
3137        if (bfee->role == RTW_BFEE_SU)
3138                rtw8822c_bf_config_bfee_su(rtwdev, vif, bfee, enable);
3139        else if (bfee->role == RTW_BFEE_MU)
3140                rtw8822c_bf_config_bfee_mu(rtwdev, vif, bfee, enable);
3141        else
3142                rtw_warn(rtwdev, "wrong bfee role\n");
3143}
3144
3145struct dpk_cfg_pair {
3146        u32 addr;
3147        u32 bitmask;
3148        u32 data;
3149};
3150
3151void rtw8822c_parse_tbl_dpk(struct rtw_dev *rtwdev,
3152                            const struct rtw_table *tbl)
3153{
3154        const struct dpk_cfg_pair *p = tbl->data;
3155        const struct dpk_cfg_pair *end = p + tbl->size / 3;
3156
3157        BUILD_BUG_ON(sizeof(struct dpk_cfg_pair) != sizeof(u32) * 3);
3158
3159        for (; p < end; p++)
3160                rtw_write32_mask(rtwdev, p->addr, p->bitmask, p->data);
3161}
3162
3163static void rtw8822c_dpk_set_gnt_wl(struct rtw_dev *rtwdev, bool is_before_k)
3164{
3165        struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3166
3167        if (is_before_k) {
3168                dpk_info->gnt_control = rtw_read32(rtwdev, 0x70);
3169                dpk_info->gnt_value = rtw_coex_read_indirect_reg(rtwdev, 0x38);
3170                rtw_write32_mask(rtwdev, 0x70, BIT(26), 0x1);
3171                rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKBYTE1, 0x77);
3172        } else {
3173                rtw_coex_write_indirect_reg(rtwdev, 0x38, MASKDWORD,
3174                                            dpk_info->gnt_value);
3175                rtw_write32(rtwdev, 0x70, dpk_info->gnt_control);
3176        }
3177}
3178
3179static void
3180rtw8822c_dpk_restore_registers(struct rtw_dev *rtwdev, u32 reg_num,
3181                               struct rtw_backup_info *bckp)
3182{
3183        rtw_restore_reg(rtwdev, bckp, reg_num);
3184        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3185        rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_DPD_CLK, 0x4);
3186}
3187
3188static void
3189rtw8822c_dpk_backup_registers(struct rtw_dev *rtwdev, u32 *reg,
3190                              u32 reg_num, struct rtw_backup_info *bckp)
3191{
3192        u32 i;
3193
3194        for (i = 0; i < reg_num; i++) {
3195                bckp[i].len = 4;
3196                bckp[i].reg = reg[i];
3197                bckp[i].val = rtw_read32(rtwdev, reg[i]);
3198        }
3199}
3200
3201static void rtw8822c_dpk_backup_rf_registers(struct rtw_dev *rtwdev,
3202                                             u32 *rf_reg,
3203                                             u32 rf_reg_bak[][2])
3204{
3205        u32 i;
3206
3207        for (i = 0; i < DPK_RF_REG_NUM; i++) {
3208                rf_reg_bak[i][RF_PATH_A] = rtw_read_rf(rtwdev, RF_PATH_A,
3209                                                       rf_reg[i], RFREG_MASK);
3210                rf_reg_bak[i][RF_PATH_B] = rtw_read_rf(rtwdev, RF_PATH_B,
3211                                                       rf_reg[i], RFREG_MASK);
3212        }
3213}
3214
3215static void rtw8822c_dpk_reload_rf_registers(struct rtw_dev *rtwdev,
3216                                             u32 *rf_reg,
3217                                             u32 rf_reg_bak[][2])
3218{
3219        u32 i;
3220
3221        for (i = 0; i < DPK_RF_REG_NUM; i++) {
3222                rtw_write_rf(rtwdev, RF_PATH_A, rf_reg[i], RFREG_MASK,
3223                             rf_reg_bak[i][RF_PATH_A]);
3224                rtw_write_rf(rtwdev, RF_PATH_B, rf_reg[i], RFREG_MASK,
3225                             rf_reg_bak[i][RF_PATH_B]);
3226        }
3227}
3228
3229static void rtw8822c_dpk_information(struct rtw_dev *rtwdev)
3230{
3231        struct rtw_dpk_info *dpk_info = &rtwdev->dm_info.dpk_info;
3232        u32  reg;
3233        u8 band_shift;
3234
3235        reg = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK);
3236
3237        band_shift = FIELD_GET(BIT(16), reg);
3238        dpk_info->dpk_band = 1 << band_shift;
3239        dpk_info->dpk_ch = FIELD_GET(0xff, reg);
3240        dpk_info->dpk_bw = FIELD_GET(0x3000, reg);
3241}
3242
3243static void rtw8822c_dpk_rxbb_dc_cal(struct rtw_dev *rtwdev, u8 path)
3244{
3245        rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3246        udelay(5);
3247        rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84801);
3248        usleep_range(600, 610);
3249        rtw_write_rf(rtwdev, path, 0x92, RFREG_MASK, 0x84800);
3250}
3251
3252static u8 rtw8822c_dpk_dc_corr_check(struct rtw_dev *rtwdev, u8 path)
3253{
3254        u16 dc_i, dc_q;
3255        u8 corr_idx;
3256
3257        rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000900f0);
3258        dc_i = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
3259        dc_q = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(11, 0));
3260
3261        if (dc_i & BIT(11))
3262                dc_i = 0x1000 - dc_i;
3263        if (dc_q & BIT(11))
3264                dc_q = 0x1000 - dc_q;
3265
3266        rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x000000f0);
3267        corr_idx = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(7, 0));
3268        rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(15, 8));
3269
3270        if (dc_i > 200 || dc_q > 200 || corr_idx < 40 || corr_idx > 65)
3271                return 1;
3272        else
3273                return 0;
3274
3275}
3276
3277static void rtw8822c_dpk_tx_pause(struct rtw_dev *rtwdev)
3278{
3279        u8 reg_a, reg_b;
3280        u16 count = 0;
3281
3282        rtw_write8(rtwdev, 0x522, 0xff);
3283        rtw_write32_mask(rtwdev, 0x1e70, 0xf, 0x2);
3284
3285        do {
3286                reg_a = (u8)rtw_read_rf(rtwdev, RF_PATH_A, 0x00, 0xf0000);
3287                reg_b = (u8)rtw_read_rf(rtwdev, RF_PATH_B, 0x00, 0xf0000);
3288                udelay(2);
3289                count++;
3290        } while ((reg_a == 2 || reg_b == 2) && count < 2500);
3291}
3292
3293static void rtw8822c_dpk_mac_bb_setting(struct rtw_dev *rtwdev)
3294{
3295        rtw8822c_dpk_tx_pause(rtwdev);
3296        rtw_load_table(rtwdev, &rtw8822c_dpk_mac_bb_tbl);
3297}
3298
3299static void rtw8822c_dpk_afe_setting(struct rtw_dev *rtwdev, bool is_do_dpk)
3300{
3301        if (is_do_dpk)
3302                rtw_load_table(rtwdev, &rtw8822c_dpk_afe_is_dpk_tbl);
3303        else
3304                rtw_load_table(rtwdev, &rtw8822c_dpk_afe_no_dpk_tbl);
3305}
3306
3307static void rtw8822c_dpk_pre_setting(struct rtw_dev *rtwdev)
3308{
3309        u8 path;
3310
3311        for (path = 0; path < rtwdev->hal.rf_path_num; path++) {
3312                rtw_write_rf(rtwdev, path, RF_RXAGC_OFFSET, RFREG_MASK, 0x0);
3313                rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3314                if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G)
3315                        rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f100000);
3316                else
3317                        rtw_write32(rtwdev, REG_DPD_CTL1_S1, 0x1f0d0000);
3318                rtw_write32_mask(rtwdev, REG_DPD_LUT0, BIT_GLOSS_DB, 0x4);
3319                rtw_write32_mask(rtwdev, REG_IQK_CTL1, BIT_TX_CFIR, 0x3);
3320        }
3321        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3322        rtw_write32(rtwdev, REG_DPD_CTL11, 0x3b23170b);
3323        rtw_write32(rtwdev, REG_DPD_CTL12, 0x775f5347);
3324}
3325
3326static u32 rtw8822c_dpk_rf_setting(struct rtw_dev *rtwdev, u8 path)
3327{
3328        u32 ori_txbb;
3329
3330        rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, RFREG_MASK, 0x50017);
3331        ori_txbb = rtw_read_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK);
3332
3333        rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TX_GAIN, 0x1);
3334        rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_PWR_TRIM, 0x1);
3335        rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_BB_GAIN, 0x0);
3336        rtw_write_rf(rtwdev, path, RF_TX_GAIN, RFREG_MASK, ori_txbb);
3337
3338        if (rtwdev->dm_info.dpk_info.dpk_band == RTW_BAND_2G) {
3339                rtw_write_rf(rtwdev, path, RF_TX_GAIN_OFFSET, BIT_RF_GAIN, 0x1);
3340                rtw_write_rf(rtwdev, path, RF_RXG_GAIN, BIT_RXG_GAIN, 0x0);
3341        } else {
3342                rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_TXA_LB_ATT, 0x0);
3343                rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_ATT, 0x6);
3344                rtw_write_rf(rtwdev, path, RF_TXA_LB_SW, BIT_LB_SW, 0x1);
3345                rtw_write_rf(rtwdev, path, RF_RXA_MIX_GAIN, BIT_RXA_MIX_GAIN, 0);
3346        }
3347
3348        rtw_write_rf(rtwdev, path, RF_MODE_TRXAGC, BIT_RXAGC, 0xf);
3349        rtw_write_rf(rtwdev, path, RF_DEBUG, BIT_DE_TRXBW, 0x1);
3350        rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_RXBB, 0x0);
3351
3352        if (rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80)
3353                rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x2);
3354        else
3355                rtw_write_rf(rtwdev, path, RF_BW_TRXBB, BIT_BW_TXBB, 0x1);
3356
3357        rtw_write_rf(rtwdev, path, RF_EXT_TIA_BW, BIT(1), 0x1);
3358
3359        usleep_range(100, 110);
3360
3361        return ori_txbb & 0x1f;
3362}
3363
3364static u16 rtw8822c_dpk_get_cmd(struct rtw_dev *rtwdev, u8 action, u8 path)
3365{
3366        u16 cmd;
3367        u8 bw = rtwdev->dm_info.dpk_info.dpk_bw == DPK_CHANNEL_WIDTH_80 ? 2 : 0;
3368
3369        switch (action) {
3370        case RTW_DPK_GAIN_LOSS:
3371                cmd = 0x14 + path;
3372                break;
3373        case RTW_DPK_DO_DPK:
3374                cmd = 0x16 + path + bw;
3375                break;
3376        case RTW_DPK_DPK_ON:
3377                cmd = 0x1a + path;
3378                break;
3379        case RTW_DPK_DAGC:
3380                cmd = 0x1c + path + bw;
3381                break;
3382        default:
3383                return 0;
3384        }
3385
3386        return (cmd << 8) | 0x48;
3387}
3388
3389static u8 rtw8822c_dpk_one_shot(struct rtw_dev *rtwdev, u8 path, u8 action)
3390{
3391        u16 dpk_cmd;
3392        u8 result = 0;
3393
3394        rtw8822c_dpk_set_gnt_wl(rtwdev, true);
3395
3396        if (action == RTW_DPK_CAL_PWR) {
3397                rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x1);
3398                rtw_write32_mask(rtwdev, REG_DPD_CTL0, BIT(12), 0x0);
3399                rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, BIT_RPT_SEL, 0x0);
3400                msleep(10);
3401                if (!check_hw_ready(rtwdev, REG_STAT_RPT, BIT(31), 0x1)) {
3402                        result = 1;
3403                        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3404                }
3405        } else {
3406                rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3407                                 0x8 | (path << 1));
3408                rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x9);
3409
3410                dpk_cmd = rtw8822c_dpk_get_cmd(rtwdev, action, path);
3411                rtw_write32(rtwdev, REG_NCTL0, dpk_cmd);
3412                rtw_write32(rtwdev, REG_NCTL0, dpk_cmd + 1);
3413                msleep(10);
3414                if (!check_hw_ready(rtwdev, 0x2d9c, 0xff, 0x55)) {
3415                        result = 1;
3416                        rtw_dbg(rtwdev, RTW_DBG_RFK, "[DPK] one-shot over 20ms\n");
3417                }
3418                rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE,
3419                                 0x8 | (path << 1));
3420                rtw_write32_mask(rtwdev, REG_R_CONFIG, BIT_IQ_SWITCH, 0x0);
3421        }
3422
3423        rtw8822c_dpk_set_gnt_wl(rtwdev, false);
3424
3425        rtw_write8(rtwdev, 0x1b10, 0x0);
3426
3427        return result;
3428}
3429
3430static u16 rtw8822c_dpk_dgain_read(struct rtw_dev *rtwdev, u8 path)
3431{
3432        u16 dgain;
3433
3434        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0xc);
3435        rtw_write32_mask(rtwdev, REG_RXSRAM_CTL, 0x00ff0000, 0x0);
3436
3437        dgain = (u16)rtw_read32_mask(rtwdev, REG_STAT_RPT, GENMASK(27, 16));
3438
3439        return dgain;
3440}
3441
3442static u8 rtw8822c_dpk_thermal_read(struct rtw_dev *rtwdev, u8 path)
3443{
3444        rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3445        rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x0);
3446        rtw_write_rf(rtwdev, path, RF_T_METER, BIT(19), 0x1);
3447        udelay(15);
3448
3449        return (u8)rtw_read_rf(rtwdev, path, RF_T_METER, 0x0007e);
3450}
3451
3452static u32 rtw8822c_dpk_pas_read(struct rtw_dev *rtwdev, u8 path)
3453{
3454        u32 i_val, q_val;
3455
3456        rtw_write32(rtwdev, REG_NCTL0, 0x8 | (path << 1));
3457        rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3458        rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060001);
3459        rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3460        rtw_write32(rtwdev, 0x1b4c, 0x00080000);
3461
3462        q_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKHWORD);
3463        i_val = rtw_read32_mask(rtwdev, REG_STAT_RPT, MASKLWORD);
3464
3465        if (i_val & BIT(15))
3466                i_val = 0x10000 - i_val;
3467        if (q_val & BIT(15))
3468                q_val = 0x10000 - q_val;
3469
3470        rtw_write32(rtwdev, 0x1b4c, 0x00000000);
3471
3472        return i_val * i_val + q_val * q_val;
3473}
3474
3475static u32 rtw8822c_psd_log2base(u32 val)
3476{
3477        u32 tmp, val_integerd_b, tindex;
3478        u32 result, val_fractiond_b;
3479        u32 table_fraction[21] = {0, 432, 332, 274, 232, 200, 174,
3480                                  151, 132, 115, 100, 86, 74, 62, 51,
3481                                  42, 32, 23, 15, 7, 0};
3482
3483        if (val == 0)
3484                return 0;
3485
3486        val_integerd_b = __fls(val) + 1;
3487
3488        tmp = (val * 100) / (1 << val_integerd_b);
3489        tindex = tmp / 5;
3490
3491        if (tindex >= ARRAY_SIZE(table_fraction))
3492                tindex = ARRAY_SIZE(table_fraction) - 1;
3493
3494        val_fractiond_b = table_fraction[tindex];
3495
3496        result = val_integerd_b * 100 - val_fractiond_b;
3497
3498        return result;
3499}
3500
3501static u8 rtw8822c_dpk_gainloss_result(struct rtw_dev *rtwdev, u8 path)
3502{
3503        u8 result;
3504
3505        rtw_write32_mask(rtwdev, REG_NCTL0, BIT_SUBPAGE, 0x8 | (path << 1));
3506        rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x1);
3507        rtw_write32(rtwdev, REG_RXSRAM_CTL, 0x00060000);
3508
3509        result = (u8)rtw_read32_mask(rtwdev, REG_STAT_RPT, 0x000000f0);
3510
3511        rtw_write32_mask(rtwdev, 0x1b48, BIT(14), 0x0);
3512
3513        return result;
3514}
3515
3516static u8 rtw8822c_dpk_agc_gain_chk(struct rtw_dev *rtwdev, u8 path,
3517                                    u8 limited_pga)
3518{
3519        u8 result = 0;
3520        u16 dgain;
3521
3522        rtw8822c_dpk_one_shot(rtwdev, path, RTW_DPK_DAGC);
3523        dgain = rtw8822c_dpk_dgain_read(rtwdev, path);
3524
3525        if (dgain > 1535 && !limited_pga)
3526                return RTW_DPK_GAIN_LESS;
3527        else if (dgain < 768 && !limited_pga)
3528                return RTW_DPK_GAIN_LARGE;
3529        else
3530                return result;
3531}
3532
3533static u8 rtw8822c_dpk_agc_loss_chk(struct rtw_dev *rtwdev, u8 path)
3534{
3535        u32 loss, loss_db;
3536
3537        loss = rtw8822c_dpk_pas_read(rtwdev, path);
3538        if (loss < 0x4000000)
3539                return RTW_DPK_GL_LESS;
3540        loss_db = 3 * rtw8822c_psd_log2base(loss<