1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
19
20#include <linux/pci_ids.h>
21#include <linux/if_ether.h>
22#include <net/cfg80211.h>
23#include <net/mac80211.h>
24#include <brcm_hw_ids.h>
25#include <aiutils.h>
26#include <chipcommon.h>
27#include "rate.h"
28#include "scb.h"
29#include "phy/phy_hal.h"
30#include "channel.h"
31#include "antsel.h"
32#include "stf.h"
33#include "ampdu.h"
34#include "mac80211_if.h"
35#include "ucode_loader.h"
36#include "main.h"
37#include "soc.h"
38#include "dma.h"
39#include "debug.h"
40#include "brcms_trace_events.h"
41
42
43#define TIMER_INTERVAL_WATCHDOG 1000
44
45#define TIMER_INTERVAL_RADIOCHK 800
46
47
48#define BEACON_INTERVAL_DEFAULT 100
49
50
51
52
53
54
55#define WL_11N_2x2 1
56#define WL_11N_3x3 3
57#define WL_11N_4x4 4
58
59#define EDCF_ACI_MASK 0x60
60#define EDCF_ACI_SHIFT 5
61#define EDCF_ECWMIN_MASK 0x0f
62#define EDCF_ECWMAX_SHIFT 4
63#define EDCF_AIFSN_MASK 0x0f
64#define EDCF_AIFSN_MAX 15
65#define EDCF_ECWMAX_MASK 0xf0
66
67#define EDCF_AC_BE_TXOP_STA 0x0000
68#define EDCF_AC_BK_TXOP_STA 0x0000
69#define EDCF_AC_VO_ACI_STA 0x62
70#define EDCF_AC_VO_ECW_STA 0x32
71#define EDCF_AC_VI_ACI_STA 0x42
72#define EDCF_AC_VI_ECW_STA 0x43
73#define EDCF_AC_BK_ECW_STA 0xA4
74#define EDCF_AC_VI_TXOP_STA 0x005e
75#define EDCF_AC_VO_TXOP_STA 0x002f
76#define EDCF_AC_BE_ACI_STA 0x03
77#define EDCF_AC_BE_ECW_STA 0xA4
78#define EDCF_AC_BK_ACI_STA 0x27
79#define EDCF_AC_VO_TXOP_AP 0x002f
80
81#define EDCF_TXOP2USEC(txop) ((txop) << 5)
82#define EDCF_ECW2CW(exp) ((1 << (exp)) - 1)
83
84#define APHY_SYMBOL_TIME 4
85#define APHY_PREAMBLE_TIME 16
86#define APHY_SIGNAL_TIME 4
87#define APHY_SIFS_TIME 16
88#define APHY_SERVICE_NBITS 16
89#define APHY_TAIL_NBITS 6
90#define BPHY_SIFS_TIME 10
91#define BPHY_PLCP_SHORT_TIME 96
92
93#define PREN_PREAMBLE 24
94#define PREN_MM_EXT 12
95#define PREN_PREAMBLE_EXT 4
96
97#define DOT11_MAC_HDR_LEN 24
98#define DOT11_ACK_LEN 10
99#define DOT11_BA_LEN 4
100#define DOT11_OFDM_SIGNAL_EXTENSION 6
101#define DOT11_MIN_FRAG_LEN 256
102#define DOT11_RTS_LEN 16
103#define DOT11_CTS_LEN 10
104#define DOT11_BA_BITMAP_LEN 128
105#define DOT11_MAXNUMFRAGS 16
106#define DOT11_MAX_FRAG_LEN 2346
107
108#define BPHY_PLCP_TIME 192
109#define RIFS_11N_TIME 2
110
111
112#define BCN_TMPL_LEN 512
113
114
115#define BRCMS_BSS_HT 0x0020
116
117
118#define BRCMS_HWRXOFF 38
119
120
121#define RFDISABLE_DEFAULT 10000000
122
123#define BRCMS_TEMPSENSE_PERIOD 10
124
125
126#define SYNTHPU_DLY_APHY_US 3700
127#define SYNTHPU_DLY_BPHY_US 1050
128#define SYNTHPU_DLY_NPHY_US 2048
129#define SYNTHPU_DLY_LPPHY_US 300
130
131#define ANTCNT 10
132
133
134#define EDCF_SHORT_S 0
135#define EDCF_SFB_S 4
136#define EDCF_LONG_S 8
137#define EDCF_LFB_S 12
138#define EDCF_SHORT_M BITFIELD_MASK(4)
139#define EDCF_SFB_M BITFIELD_MASK(4)
140#define EDCF_LONG_M BITFIELD_MASK(4)
141#define EDCF_LFB_M BITFIELD_MASK(4)
142
143#define RETRY_SHORT_DEF 7
144#define RETRY_SHORT_MAX 255
145#define RETRY_LONG_DEF 4
146#define RETRY_SHORT_FB 3
147#define RETRY_LONG_FB 2
148
149#define APHY_CWMIN 15
150#define PHY_CWMAX 1023
151
152#define EDCF_AIFSN_MIN 1
153
154#define FRAGNUM_MASK 0xF
155
156#define APHY_SLOT_TIME 9
157#define BPHY_SLOT_TIME 20
158
159#define WL_SPURAVOID_OFF 0
160#define WL_SPURAVOID_ON1 1
161#define WL_SPURAVOID_ON2 2
162
163
164#define BRCMS_USE_COREFLAGS 0xffffffff
165
166
167#define BRCMS_PLCP_AUTO -1
168#define BRCMS_PLCP_SHORT 0
169#define BRCMS_PLCP_LONG 1
170
171
172#define BRCMS_PROTECTION_AUTO -1
173#define BRCMS_PROTECTION_OFF 0
174#define BRCMS_PROTECTION_ON 1
175#define BRCMS_PROTECTION_MMHDR_ONLY 2
176#define BRCMS_PROTECTION_CTS_ONLY 3
177
178
179#define BRCMS_PROTECTION_CTL_OFF 0
180#define BRCMS_PROTECTION_CTL_LOCAL 1
181#define BRCMS_PROTECTION_CTL_OVERLAP 2
182
183
184#define BRCMS_N_PROTECTION_OFF 0
185#define BRCMS_N_PROTECTION_OPTIONAL 1
186#define BRCMS_N_PROTECTION_20IN40 2
187#define BRCMS_N_PROTECTION_MIXEDMODE 3
188
189
190#define BRCMS_N_BW_20ALL 0
191#define BRCMS_N_BW_40ALL 1
192#define BRCMS_N_BW_20IN2G_40IN5G 2
193
194
195#define BRCMS_N_SGI_20 0x01
196#define BRCMS_N_SGI_40 0x02
197
198
199
200#define NRATE_MCS_INUSE 0x00000080
201
202#define NRATE_RATE_MASK 0x0000007f
203
204#define NRATE_STF_MASK 0x0000ff00
205
206#define NRATE_STF_SHIFT 8
207
208#define NRATE_OVERRIDE_MCS_ONLY 0x40000000
209#define NRATE_SGI_MASK 0x00800000
210#define NRATE_SGI_SHIFT 23
211#define NRATE_LDPC_CODING 0x00400000
212#define NRATE_LDPC_SHIFT 22
213
214#define NRATE_STF_SISO 0
215#define NRATE_STF_CDD 1
216#define NRATE_STF_STBC 2
217#define NRATE_STF_SDM 3
218
219#define MAX_DMA_SEGS 4
220
221
222#define NTXD 64
223
224#define NRXD 256
225
226
227#define TX_HEADROOM 4
228
229
230#define NRXBUFPOST 32
231
232
233#define RXBND 8
234
235#define TXSBND 8
236
237
238struct brcms_c_bit_desc {
239 u32 bit;
240 const char *name;
241};
242
243
244
245
246
247
248
249
250
251
252
253#define XMTFIFOTBL_STARTREV 17
254
255struct d11init {
256 __le16 addr;
257 __le16 size;
258 __le32 value;
259};
260
261struct edcf_acparam {
262 u8 ACI;
263 u8 ECW;
264 u16 TXOP;
265} __packed;
266
267
268uint brcm_msg_level;
269
270
271static const u8 wme_fifo2ac[] = {
272 IEEE80211_AC_BK,
273 IEEE80211_AC_BE,
274 IEEE80211_AC_VI,
275 IEEE80211_AC_VO,
276 IEEE80211_AC_BE,
277 IEEE80211_AC_BE
278};
279
280
281static const u8 wme_ac2fifo[] = {
282 TX_AC_VO_FIFO,
283 TX_AC_VI_FIFO,
284 TX_AC_BE_FIFO,
285 TX_AC_BK_FIFO
286};
287
288static const u16 xmtfifo_sz[][NFIFO] = {
289
290 {20, 192, 192, 21, 17, 5},
291
292 {0, 0, 0, 0, 0, 0},
293
294 {0, 0, 0, 0, 0, 0},
295
296 {20, 192, 192, 21, 17, 5},
297
298 {9, 58, 22, 14, 14, 5},
299
300 {20, 192, 192, 21, 17, 5},
301
302 {20, 192, 192, 21, 17, 5},
303
304 {9, 58, 22, 14, 14, 5},
305
306 {0, 0, 0, 0, 0, 0},
307
308 {0, 0, 0, 0, 0, 0},
309
310 {0, 0, 0, 0, 0, 0},
311
312 {9, 58, 22, 14, 14, 5},
313};
314
315#ifdef DEBUG
316static const char * const fifo_names[] = {
317 "AC_BK", "AC_BE", "AC_VI", "AC_VO", "BCMC", "ATIM" };
318#else
319static const char fifo_names[6][1];
320#endif
321
322#ifdef DEBUG
323
324static struct brcms_c_info *wlc_info_dbg = (struct brcms_c_info *) (NULL);
325#endif
326
327
328static const u8 ac_to_fifo_mapping[IEEE80211_NUM_ACS] = {
329 [IEEE80211_AC_VO] = TX_AC_VO_FIFO,
330 [IEEE80211_AC_VI] = TX_AC_VI_FIFO,
331 [IEEE80211_AC_BE] = TX_AC_BE_FIFO,
332 [IEEE80211_AC_BK] = TX_AC_BK_FIFO,
333};
334
335
336static const u8 fifo_to_ac_mapping[IEEE80211_NUM_ACS] = {
337 [TX_AC_BK_FIFO] = IEEE80211_AC_BK,
338 [TX_AC_BE_FIFO] = IEEE80211_AC_BE,
339 [TX_AC_VI_FIFO] = IEEE80211_AC_VI,
340 [TX_AC_VO_FIFO] = IEEE80211_AC_VO,
341};
342
343static u8 brcms_ac_to_fifo(u8 ac)
344{
345 if (ac >= ARRAY_SIZE(ac_to_fifo_mapping))
346 return TX_AC_BE_FIFO;
347 return ac_to_fifo_mapping[ac];
348}
349
350static u8 brcms_fifo_to_ac(u8 fifo)
351{
352 if (fifo >= ARRAY_SIZE(fifo_to_ac_mapping))
353 return IEEE80211_AC_BE;
354 return fifo_to_ac_mapping[fifo];
355}
356
357
358static u8 brcms_basic_rate(struct brcms_c_info *wlc, u32 rspec)
359{
360 if (is_mcs_rate(rspec))
361 return wlc->band->basic_rate[mcs_table[rspec & RSPEC_RATE_MASK]
362 .leg_ofdm];
363 return wlc->band->basic_rate[rspec & RSPEC_RATE_MASK];
364}
365
366static u16 frametype(u32 rspec, u8 mimoframe)
367{
368 if (is_mcs_rate(rspec))
369 return mimoframe;
370 return is_cck_rate(rspec) ? FT_CCK : FT_OFDM;
371}
372
373
374static u16 get_sifs(struct brcms_band *band)
375{
376 return band->bandtype == BRCM_BAND_5G ? APHY_SIFS_TIME :
377 BPHY_SIFS_TIME;
378}
379
380
381
382
383
384
385
386
387
388
389static bool brcms_deviceremoved(struct brcms_c_info *wlc)
390{
391 u32 macctrl;
392
393 if (!wlc->hw->clk)
394 return ai_deviceremoved(wlc->hw->sih);
395 macctrl = bcma_read32(wlc->hw->d11core,
396 D11REGOFFS(maccontrol));
397 return (macctrl & (MCTL_PSM_JMP_0 | MCTL_IHR_EN)) != MCTL_IHR_EN;
398}
399
400
401static int brcms_txpktpendtot(struct brcms_c_info *wlc)
402{
403 int i;
404 int pending = 0;
405
406 for (i = 0; i < ARRAY_SIZE(wlc->hw->di); i++)
407 if (wlc->hw->di[i])
408 pending += dma_txpending(wlc->hw->di[i]);
409 return pending;
410}
411
412static bool brcms_is_mband_unlocked(struct brcms_c_info *wlc)
413{
414 return wlc->pub->_nbands > 1 && !wlc->bandlocked;
415}
416
417static int brcms_chspec_bw(u16 chanspec)
418{
419 if (CHSPEC_IS40(chanspec))
420 return BRCMS_40_MHZ;
421 if (CHSPEC_IS20(chanspec))
422 return BRCMS_20_MHZ;
423
424 return BRCMS_10_MHZ;
425}
426
427static void brcms_c_bsscfg_mfree(struct brcms_bss_cfg *cfg)
428{
429 if (cfg == NULL)
430 return;
431
432 kfree(cfg->current_bss);
433 kfree(cfg);
434}
435
436static void brcms_c_detach_mfree(struct brcms_c_info *wlc)
437{
438 if (wlc == NULL)
439 return;
440
441 brcms_c_bsscfg_mfree(wlc->bsscfg);
442 kfree(wlc->pub);
443 kfree(wlc->modulecb);
444 kfree(wlc->default_bss);
445 kfree(wlc->protection);
446 kfree(wlc->stf);
447 kfree(wlc->bandstate[0]);
448 if (wlc->corestate)
449 kfree(wlc->corestate->macstat_snapshot);
450 kfree(wlc->corestate);
451 if (wlc->hw)
452 kfree(wlc->hw->bandstate[0]);
453 kfree(wlc->hw);
454 if (wlc->beacon)
455 dev_kfree_skb_any(wlc->beacon);
456 if (wlc->probe_resp)
457 dev_kfree_skb_any(wlc->probe_resp);
458
459 kfree(wlc);
460}
461
462static struct brcms_bss_cfg *brcms_c_bsscfg_malloc(uint unit)
463{
464 struct brcms_bss_cfg *cfg;
465
466 cfg = kzalloc(sizeof(struct brcms_bss_cfg), GFP_ATOMIC);
467 if (cfg == NULL)
468 goto fail;
469
470 cfg->current_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
471 if (cfg->current_bss == NULL)
472 goto fail;
473
474 return cfg;
475
476 fail:
477 brcms_c_bsscfg_mfree(cfg);
478 return NULL;
479}
480
481static struct brcms_c_info *
482brcms_c_attach_malloc(uint unit, uint *err, uint devid)
483{
484 struct brcms_c_info *wlc;
485
486 wlc = kzalloc(sizeof(struct brcms_c_info), GFP_ATOMIC);
487 if (wlc == NULL) {
488 *err = 1002;
489 goto fail;
490 }
491
492
493 wlc->pub = kzalloc(sizeof(struct brcms_pub), GFP_ATOMIC);
494 if (wlc->pub == NULL) {
495 *err = 1003;
496 goto fail;
497 }
498 wlc->pub->wlc = wlc;
499
500
501
502 wlc->hw = kzalloc(sizeof(struct brcms_hardware), GFP_ATOMIC);
503 if (wlc->hw == NULL) {
504 *err = 1005;
505 goto fail;
506 }
507 wlc->hw->wlc = wlc;
508
509 wlc->hw->bandstate[0] =
510 kcalloc(MAXBANDS, sizeof(struct brcms_hw_band), GFP_ATOMIC);
511 if (wlc->hw->bandstate[0] == NULL) {
512 *err = 1006;
513 goto fail;
514 } else {
515 int i;
516
517 for (i = 1; i < MAXBANDS; i++)
518 wlc->hw->bandstate[i] = (struct brcms_hw_band *)
519 ((unsigned long)wlc->hw->bandstate[0] +
520 (sizeof(struct brcms_hw_band) * i));
521 }
522
523 wlc->modulecb =
524 kcalloc(BRCMS_MAXMODULES, sizeof(struct modulecb),
525 GFP_ATOMIC);
526 if (wlc->modulecb == NULL) {
527 *err = 1009;
528 goto fail;
529 }
530
531 wlc->default_bss = kzalloc(sizeof(struct brcms_bss_info), GFP_ATOMIC);
532 if (wlc->default_bss == NULL) {
533 *err = 1010;
534 goto fail;
535 }
536
537 wlc->bsscfg = brcms_c_bsscfg_malloc(unit);
538 if (wlc->bsscfg == NULL) {
539 *err = 1011;
540 goto fail;
541 }
542
543 wlc->protection = kzalloc(sizeof(struct brcms_protection),
544 GFP_ATOMIC);
545 if (wlc->protection == NULL) {
546 *err = 1016;
547 goto fail;
548 }
549
550 wlc->stf = kzalloc(sizeof(struct brcms_stf), GFP_ATOMIC);
551 if (wlc->stf == NULL) {
552 *err = 1017;
553 goto fail;
554 }
555
556 wlc->bandstate[0] =
557 kcalloc(MAXBANDS, sizeof(struct brcms_band), GFP_ATOMIC);
558 if (wlc->bandstate[0] == NULL) {
559 *err = 1025;
560 goto fail;
561 } else {
562 int i;
563
564 for (i = 1; i < MAXBANDS; i++)
565 wlc->bandstate[i] = (struct brcms_band *)
566 ((unsigned long)wlc->bandstate[0]
567 + (sizeof(struct brcms_band)*i));
568 }
569
570 wlc->corestate = kzalloc(sizeof(struct brcms_core), GFP_ATOMIC);
571 if (wlc->corestate == NULL) {
572 *err = 1026;
573 goto fail;
574 }
575
576 wlc->corestate->macstat_snapshot =
577 kzalloc(sizeof(struct macstat), GFP_ATOMIC);
578 if (wlc->corestate->macstat_snapshot == NULL) {
579 *err = 1027;
580 goto fail;
581 }
582
583 return wlc;
584
585 fail:
586 brcms_c_detach_mfree(wlc);
587 return NULL;
588}
589
590
591
592
593
594
595static void brcms_b_update_slot_timing(struct brcms_hardware *wlc_hw,
596 bool shortslot)
597{
598 struct bcma_device *core = wlc_hw->d11core;
599
600 if (shortslot) {
601
602 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0207);
603 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, APHY_SLOT_TIME);
604 } else {
605
606 bcma_write16(core, D11REGOFFS(ifs_slot), 0x0212);
607 brcms_b_write_shm(wlc_hw, M_DOT11_SLOT, BPHY_SLOT_TIME);
608 }
609}
610
611
612
613
614
615static uint brcms_c_calc_frame_time(struct brcms_c_info *wlc, u32 ratespec,
616 u8 preamble_type, uint mac_len)
617{
618 uint nsyms, dur = 0, Ndps, kNdps;
619 uint rate = rspec2rate(ratespec);
620
621 if (rate == 0) {
622 brcms_err(wlc->hw->d11core, "wl%d: WAR: using rate of 1 mbps\n",
623 wlc->pub->unit);
624 rate = BRCM_RATE_1M;
625 }
626
627 if (is_mcs_rate(ratespec)) {
628 uint mcs = ratespec & RSPEC_RATE_MASK;
629 int tot_streams = mcs_2_txstreams(mcs) + rspec_stc(ratespec);
630
631 dur = PREN_PREAMBLE + (tot_streams * PREN_PREAMBLE_EXT);
632 if (preamble_type == BRCMS_MM_PREAMBLE)
633 dur += PREN_MM_EXT;
634
635 kNdps = mcs_2_rate(mcs, rspec_is40mhz(ratespec),
636 rspec_issgi(ratespec)) * 4;
637
638 if (rspec_stc(ratespec) == 0)
639 nsyms =
640 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
641 APHY_TAIL_NBITS) * 1000, kNdps);
642 else
643
644 nsyms =
645 2 *
646 CEIL((APHY_SERVICE_NBITS + 8 * mac_len +
647 APHY_TAIL_NBITS) * 1000, 2 * kNdps);
648
649 dur += APHY_SYMBOL_TIME * nsyms;
650 if (wlc->band->bandtype == BRCM_BAND_2G)
651 dur += DOT11_OFDM_SIGNAL_EXTENSION;
652 } else if (is_ofdm_rate(rate)) {
653 dur = APHY_PREAMBLE_TIME;
654 dur += APHY_SIGNAL_TIME;
655
656 Ndps = rate * 2;
657
658 nsyms =
659 CEIL((APHY_SERVICE_NBITS + 8 * mac_len + APHY_TAIL_NBITS),
660 Ndps);
661 dur += APHY_SYMBOL_TIME * nsyms;
662 if (wlc->band->bandtype == BRCM_BAND_2G)
663 dur += DOT11_OFDM_SIGNAL_EXTENSION;
664 } else {
665
666
667
668
669 mac_len = mac_len * 8 * 2;
670
671 dur = (mac_len + rate - 1) / rate;
672 if (preamble_type & BRCMS_SHORT_PREAMBLE)
673 dur += BPHY_PLCP_SHORT_TIME;
674 else
675 dur += BPHY_PLCP_TIME;
676 }
677 return dur;
678}
679
680static void brcms_c_write_inits(struct brcms_hardware *wlc_hw,
681 const struct d11init *inits)
682{
683 struct bcma_device *core = wlc_hw->d11core;
684 int i;
685 uint offset;
686 u16 size;
687 u32 value;
688
689 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
690
691 for (i = 0; inits[i].addr != cpu_to_le16(0xffff); i++) {
692 size = le16_to_cpu(inits[i].size);
693 offset = le16_to_cpu(inits[i].addr);
694 value = le32_to_cpu(inits[i].value);
695 if (size == 2)
696 bcma_write16(core, offset, value);
697 else if (size == 4)
698 bcma_write32(core, offset, value);
699 else
700 break;
701 }
702}
703
704static void brcms_c_write_mhf(struct brcms_hardware *wlc_hw, u16 *mhfs)
705{
706 u8 idx;
707 u16 addr[] = {
708 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
709 M_HOST_FLAGS5
710 };
711
712 for (idx = 0; idx < MHFMAX; idx++)
713 brcms_b_write_shm(wlc_hw, addr[idx], mhfs[idx]);
714}
715
716static void brcms_c_ucode_bsinit(struct brcms_hardware *wlc_hw)
717{
718 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
719
720
721 brcms_c_write_mhf(wlc_hw, wlc_hw->band->mhfs);
722
723
724 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
725 if (BRCMS_ISNPHY(wlc_hw->band))
726 brcms_c_write_inits(wlc_hw, ucode->d11n0bsinitvals16);
727 else
728 brcms_err(wlc_hw->d11core,
729 "%s: wl%d: unsupported phy in corerev %d\n",
730 __func__, wlc_hw->unit,
731 wlc_hw->corerev);
732 } else {
733 if (D11REV_IS(wlc_hw->corerev, 24)) {
734 if (BRCMS_ISLCNPHY(wlc_hw->band))
735 brcms_c_write_inits(wlc_hw,
736 ucode->d11lcn0bsinitvals24);
737 else
738 brcms_err(wlc_hw->d11core,
739 "%s: wl%d: unsupported phy in core rev %d\n",
740 __func__, wlc_hw->unit,
741 wlc_hw->corerev);
742 } else {
743 brcms_err(wlc_hw->d11core,
744 "%s: wl%d: unsupported corerev %d\n",
745 __func__, wlc_hw->unit, wlc_hw->corerev);
746 }
747 }
748}
749
750static void brcms_b_core_ioctl(struct brcms_hardware *wlc_hw, u32 m, u32 v)
751{
752 struct bcma_device *core = wlc_hw->d11core;
753 u32 ioctl = bcma_aread32(core, BCMA_IOCTL) & ~m;
754
755 bcma_awrite32(core, BCMA_IOCTL, ioctl | v);
756}
757
758static void brcms_b_core_phy_clk(struct brcms_hardware *wlc_hw, bool clk)
759{
760 brcms_dbg_info(wlc_hw->d11core, "wl%d: clk %d\n", wlc_hw->unit, clk);
761
762 wlc_hw->phyclk = clk;
763
764 if (OFF == clk) {
765
766 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC | SICF_GMODE),
767 (SICF_PRST | SICF_FGC));
768 udelay(1);
769 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_PRST);
770 udelay(1);
771
772 } else {
773
774 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_FGC), SICF_FGC);
775 udelay(1);
776 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
777 udelay(1);
778
779 }
780}
781
782
783static void brcms_c_setxband(struct brcms_hardware *wlc_hw, uint bandunit)
784{
785 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
786 bandunit);
787
788 wlc_hw->band = wlc_hw->bandstate[bandunit];
789
790
791
792
793
794 wlc_hw->wlc->band = wlc_hw->wlc->bandstate[bandunit];
795
796
797 if (wlc_hw->sbclk && !wlc_hw->noreset) {
798 u32 gmode = 0;
799
800 if (bandunit == 0)
801 gmode = SICF_GMODE;
802
803 brcms_b_core_ioctl(wlc_hw, SICF_GMODE, gmode);
804 }
805}
806
807
808static u32 brcms_c_setband_inact(struct brcms_c_info *wlc, uint bandunit)
809{
810 struct brcms_hardware *wlc_hw = wlc->hw;
811 u32 macintmask;
812 u32 macctrl;
813
814 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
815 macctrl = bcma_read32(wlc_hw->d11core,
816 D11REGOFFS(maccontrol));
817 WARN_ON((macctrl & MCTL_EN_MAC) != 0);
818
819
820 macintmask = brcms_intrsoff(wlc->wl);
821
822
823 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
824
825 brcms_b_core_phy_clk(wlc_hw, OFF);
826
827 brcms_c_setxband(wlc_hw, bandunit);
828
829 return macintmask;
830}
831
832
833static bool
834brcms_c_dotxstatus(struct brcms_c_info *wlc, struct tx_status *txs)
835{
836 struct sk_buff *p = NULL;
837 uint queue = NFIFO;
838 struct dma_pub *dma = NULL;
839 struct d11txh *txh = NULL;
840 struct scb *scb = NULL;
841 int tx_frame_count;
842 uint supr_status;
843 bool lastframe;
844 struct ieee80211_hdr *h;
845 struct ieee80211_tx_info *tx_info;
846 struct ieee80211_tx_rate *txrate;
847 int i;
848 bool fatal = true;
849
850 trace_brcms_txstatus(&wlc->hw->d11core->dev, txs->framelen,
851 txs->frameid, txs->status, txs->lasttxtime,
852 txs->sequence, txs->phyerr, txs->ackphyrxsh);
853
854
855
856
857
858
859 if (!(txs->status & TX_STATUS_AMPDU)
860 && (txs->status & TX_STATUS_INTERMEDIATE)) {
861 brcms_dbg_tx(wlc->hw->d11core, "INTERMEDIATE but not AMPDU\n");
862 fatal = false;
863 goto out;
864 }
865
866 queue = txs->frameid & TXFID_QUEUE_MASK;
867 if (queue >= NFIFO) {
868 brcms_err(wlc->hw->d11core, "queue %u >= NFIFO\n", queue);
869 goto out;
870 }
871
872 dma = wlc->hw->di[queue];
873
874 p = dma_getnexttxp(wlc->hw->di[queue], DMA_RANGE_TRANSMITTED);
875 if (p == NULL) {
876 brcms_err(wlc->hw->d11core, "dma_getnexttxp returned null!\n");
877 goto out;
878 }
879
880 txh = (struct d11txh *) (p->data);
881
882 if (txs->phyerr)
883 brcms_dbg_tx(wlc->hw->d11core, "phyerr 0x%x, rate 0x%x\n",
884 txs->phyerr, txh->MainRates);
885
886 if (txs->frameid != le16_to_cpu(txh->TxFrameID)) {
887 brcms_err(wlc->hw->d11core, "frameid != txh->TxFrameID\n");
888 goto out;
889 }
890 tx_info = IEEE80211_SKB_CB(p);
891 h = (struct ieee80211_hdr *)((u8 *) (txh + 1) + D11_PHY_HDR_LEN);
892
893 if (tx_info->rate_driver_data[0])
894 scb = &wlc->pri_scb;
895
896 if (tx_info->flags & IEEE80211_TX_CTL_AMPDU) {
897 brcms_c_ampdu_dotxstatus(wlc->ampdu, scb, p, txs);
898 fatal = false;
899 goto out;
900 }
901
902
903
904
905
906 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh, sizeof(*txh));
907
908 supr_status = txs->status & TX_STATUS_SUPR_MASK;
909 if (supr_status == TX_STATUS_SUPR_BADCH) {
910 unsigned xfts = le16_to_cpu(txh->XtraFrameTypes);
911 brcms_dbg_tx(wlc->hw->d11core,
912 "Pkt tx suppressed, dest chan %u, current %d\n",
913 (xfts >> XFTS_CHANNEL_SHIFT) & 0xff,
914 CHSPEC_CHANNEL(wlc->default_bss->chanspec));
915 }
916
917 tx_frame_count =
918 (txs->status & TX_STATUS_FRM_RTX_MASK) >> TX_STATUS_FRM_RTX_SHIFT;
919
920 lastframe = !ieee80211_has_morefrags(h->frame_control);
921
922 if (!lastframe) {
923 brcms_err(wlc->hw->d11core, "Not last frame!\n");
924 } else {
925
926
927
928
929
930
931
932
933 u16 sfbl,
934 lfbl,
935 fbl;
936
937 if (queue < IEEE80211_NUM_ACS) {
938 sfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
939 EDCF_SFB);
940 lfbl = GFIELD(wlc->wme_retries[wme_fifo2ac[queue]],
941 EDCF_LFB);
942 } else {
943 sfbl = wlc->SFBL;
944 lfbl = wlc->LFBL;
945 }
946
947 txrate = tx_info->status.rates;
948 if (txrate[0].flags & IEEE80211_TX_RC_USE_RTS_CTS)
949 fbl = lfbl;
950 else
951 fbl = sfbl;
952
953 ieee80211_tx_info_clear_status(tx_info);
954
955 if ((tx_frame_count > fbl) && (txrate[1].idx >= 0)) {
956
957
958
959
960 txrate[0].count = fbl;
961 txrate[1].count = tx_frame_count - fbl;
962 } else {
963
964
965
966
967 txrate[0].count = tx_frame_count;
968
969
970
971
972 txrate[1].idx = -1;
973 txrate[1].count = 0;
974 }
975
976
977 for (i = 2; i < IEEE80211_TX_MAX_RATES; i++) {
978 txrate[i].idx = -1;
979 txrate[i].count = 0;
980 }
981
982 if (txs->status & TX_STATUS_ACK_RCV)
983 tx_info->flags |= IEEE80211_TX_STAT_ACK;
984 }
985
986 if (lastframe) {
987
988 skb_pull(p, D11_PHY_HDR_LEN);
989 skb_pull(p, D11_TXH_LEN);
990 ieee80211_tx_status_irqsafe(wlc->pub->ieee_hw, p);
991 } else {
992 brcms_err(wlc->hw->d11core,
993 "%s: Not last frame => not calling tx_status\n",
994 __func__);
995 }
996
997 fatal = false;
998
999 out:
1000 if (fatal) {
1001 if (txh)
1002 trace_brcms_txdesc(&wlc->hw->d11core->dev, txh,
1003 sizeof(*txh));
1004 brcmu_pkt_buf_free_skb(p);
1005 }
1006
1007 if (dma && queue < NFIFO) {
1008 u16 ac_queue = brcms_fifo_to_ac(queue);
1009 if (dma->txavail > TX_HEADROOM && queue < TX_BCMC_FIFO &&
1010 ieee80211_queue_stopped(wlc->pub->ieee_hw, ac_queue))
1011 ieee80211_wake_queue(wlc->pub->ieee_hw, ac_queue);
1012 dma_kick_tx(dma);
1013 }
1014
1015 return fatal;
1016}
1017
1018
1019
1020
1021static bool
1022brcms_b_txstatus(struct brcms_hardware *wlc_hw, bool bound, bool *fatal)
1023{
1024 struct bcma_device *core;
1025 struct tx_status txstatus, *txs;
1026 u32 s1, s2;
1027 uint n = 0;
1028
1029
1030
1031
1032 uint max_tx_num = bound ? TXSBND : -1;
1033
1034 txs = &txstatus;
1035 core = wlc_hw->d11core;
1036 *fatal = false;
1037
1038 while (n < max_tx_num) {
1039 s1 = bcma_read32(core, D11REGOFFS(frmtxstatus));
1040 if (s1 == 0xffffffff) {
1041 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
1042 __func__);
1043 *fatal = true;
1044 return false;
1045 }
1046
1047 if (!(s1 & TXS_V))
1048 break;
1049
1050 s2 = bcma_read32(core, D11REGOFFS(frmtxstatus2));
1051 txs->status = s1 & TXS_STATUS_MASK;
1052 txs->frameid = (s1 & TXS_FID_MASK) >> TXS_FID_SHIFT;
1053 txs->sequence = s2 & TXS_SEQ_MASK;
1054 txs->phyerr = (s2 & TXS_PTX_MASK) >> TXS_PTX_SHIFT;
1055 txs->lasttxtime = 0;
1056
1057 *fatal = brcms_c_dotxstatus(wlc_hw->wlc, txs);
1058 if (*fatal)
1059 return false;
1060 n++;
1061 }
1062
1063 return n >= max_tx_num;
1064}
1065
1066static void brcms_c_tbtt(struct brcms_c_info *wlc)
1067{
1068 if (wlc->bsscfg->type == BRCMS_TYPE_ADHOC)
1069
1070
1071
1072
1073 wlc->qvalid |= MCMD_DIRFRMQVAL;
1074}
1075
1076
1077static void
1078brcms_c_mhfdef(struct brcms_c_info *wlc, u16 *mhfs, u16 mhf2_init)
1079{
1080 struct brcms_hardware *wlc_hw = wlc->hw;
1081
1082 memset(mhfs, 0, MHFMAX * sizeof(u16));
1083
1084 mhfs[MHF2] |= mhf2_init;
1085
1086
1087 if (wlc_hw->boardflags & BFL_NOPLLDOWN)
1088 mhfs[MHF1] |= MHF1_FORCEFASTCLK;
1089
1090 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_LT(wlc_hw->band->phyrev, 2)) {
1091 mhfs[MHF2] |= MHF2_NPHY40MHZ_WAR;
1092 mhfs[MHF1] |= MHF1_IQSWAP_WAR;
1093 }
1094}
1095
1096static uint
1097dmareg(uint direction, uint fifonum)
1098{
1099 if (direction == DMA_TX)
1100 return offsetof(struct d11regs, fifo64regs[fifonum].dmaxmt);
1101 return offsetof(struct d11regs, fifo64regs[fifonum].dmarcv);
1102}
1103
1104static bool brcms_b_attach_dmapio(struct brcms_c_info *wlc, uint j, bool wme)
1105{
1106 uint i;
1107 char name[8];
1108
1109
1110
1111 u16 pio_mhf2 = 0;
1112 struct brcms_hardware *wlc_hw = wlc->hw;
1113 uint unit = wlc_hw->unit;
1114
1115
1116 snprintf(name, sizeof(name), "wl%d", unit);
1117
1118 if (wlc_hw->di[0] == NULL) {
1119 int dma_attach_err = 0;
1120
1121
1122
1123
1124
1125
1126 wlc_hw->di[0] = dma_attach(name, wlc,
1127 (wme ? dmareg(DMA_TX, 0) : 0),
1128 dmareg(DMA_RX, 0),
1129 (wme ? NTXD : 0), NRXD,
1130 RXBUFSZ, -1, NRXBUFPOST,
1131 BRCMS_HWRXOFF);
1132 dma_attach_err |= (NULL == wlc_hw->di[0]);
1133
1134
1135
1136
1137
1138
1139
1140 wlc_hw->di[1] = dma_attach(name, wlc,
1141 dmareg(DMA_TX, 1), 0,
1142 NTXD, 0, 0, -1, 0, 0);
1143 dma_attach_err |= (NULL == wlc_hw->di[1]);
1144
1145
1146
1147
1148
1149
1150 wlc_hw->di[2] = dma_attach(name, wlc,
1151 dmareg(DMA_TX, 2), 0,
1152 NTXD, 0, 0, -1, 0, 0);
1153 dma_attach_err |= (NULL == wlc_hw->di[2]);
1154
1155
1156
1157
1158
1159 wlc_hw->di[3] = dma_attach(name, wlc,
1160 dmareg(DMA_TX, 3),
1161 0, NTXD, 0, 0, -1,
1162 0, 0);
1163 dma_attach_err |= (NULL == wlc_hw->di[3]);
1164
1165
1166 if (dma_attach_err) {
1167 brcms_err(wlc_hw->d11core,
1168 "wl%d: wlc_attach: dma_attach failed\n",
1169 unit);
1170 return false;
1171 }
1172
1173
1174 for (i = 0; i < NFIFO; i++)
1175 if (wlc_hw->di[i])
1176 wlc_hw->txavail[i] =
1177 (uint *) dma_getvar(wlc_hw->di[i],
1178 "&txavail");
1179 }
1180
1181
1182 brcms_c_mhfdef(wlc, wlc_hw->band->mhfs, pio_mhf2);
1183
1184 return true;
1185}
1186
1187static void brcms_b_detach_dmapio(struct brcms_hardware *wlc_hw)
1188{
1189 uint j;
1190
1191 for (j = 0; j < NFIFO; j++) {
1192 if (wlc_hw->di[j]) {
1193 dma_detach(wlc_hw->di[j]);
1194 wlc_hw->di[j] = NULL;
1195 }
1196 }
1197}
1198
1199
1200
1201
1202
1203
1204static void brcms_b_info_init(struct brcms_hardware *wlc_hw)
1205{
1206 struct brcms_c_info *wlc = wlc_hw->wlc;
1207
1208
1209 wlc->defmacintmask = DEF_MACINTMASK;
1210
1211
1212 wlc_hw->shortslot = false;
1213
1214 wlc_hw->SFBL = RETRY_SHORT_FB;
1215 wlc_hw->LFBL = RETRY_LONG_FB;
1216
1217
1218 wlc_hw->SRL = RETRY_SHORT_DEF;
1219 wlc_hw->LRL = RETRY_LONG_DEF;
1220 wlc_hw->chanspec = ch20mhz_chspec(1);
1221}
1222
1223static void brcms_b_wait_for_wake(struct brcms_hardware *wlc_hw)
1224{
1225
1226 udelay(40);
1227
1228
1229 SPINWAIT((brcms_b_read_shm(wlc_hw, M_UCODE_DBGST) ==
1230 DBGST_ASLEEP), wlc_hw->wlc->fastpwrup_dly);
1231}
1232
1233
1234static void brcms_b_clkctl_clk(struct brcms_hardware *wlc_hw, enum bcma_clkmode mode)
1235{
1236 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU) {
1237
1238
1239
1240
1241
1242
1243 if (wlc_hw->clk) {
1244 if (mode == BCMA_CLKMODE_FAST) {
1245 bcma_set32(wlc_hw->d11core,
1246 D11REGOFFS(clk_ctl_st),
1247 CCS_FORCEHT);
1248
1249 udelay(64);
1250
1251 SPINWAIT(
1252 ((bcma_read32(wlc_hw->d11core,
1253 D11REGOFFS(clk_ctl_st)) &
1254 CCS_HTAVAIL) == 0),
1255 PMU_MAX_TRANSITION_DLY);
1256 WARN_ON(!(bcma_read32(wlc_hw->d11core,
1257 D11REGOFFS(clk_ctl_st)) &
1258 CCS_HTAVAIL));
1259 } else {
1260 if ((ai_get_pmurev(wlc_hw->sih) == 0) &&
1261 (bcma_read32(wlc_hw->d11core,
1262 D11REGOFFS(clk_ctl_st)) &
1263 (CCS_FORCEHT | CCS_HTAREQ)))
1264 SPINWAIT(
1265 ((bcma_read32(wlc_hw->d11core,
1266 offsetof(struct d11regs,
1267 clk_ctl_st)) &
1268 CCS_HTAVAIL) == 0),
1269 PMU_MAX_TRANSITION_DLY);
1270 bcma_mask32(wlc_hw->d11core,
1271 D11REGOFFS(clk_ctl_st),
1272 ~CCS_FORCEHT);
1273 }
1274 }
1275 wlc_hw->forcefastclk = (mode == BCMA_CLKMODE_FAST);
1276 } else {
1277
1278
1279
1280
1281
1282 wlc_hw->forcefastclk = ai_clkctl_cc(wlc_hw->sih, mode);
1283
1284
1285 if (wlc_hw->forcefastclk && wlc_hw->clk)
1286 WARN_ON(!(bcma_aread32(wlc_hw->d11core, BCMA_IOST) &
1287 SISF_FCLKA));
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299 if (wlc_hw->forcefastclk)
1300 mboolset(wlc_hw->wake_override,
1301 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1302 else
1303 mboolclr(wlc_hw->wake_override,
1304 BRCMS_WAKE_OVERRIDE_FORCEFAST);
1305 }
1306}
1307
1308
1309
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319void
1320brcms_b_mhf(struct brcms_hardware *wlc_hw, u8 idx, u16 mask, u16 val,
1321 int bands)
1322{
1323 u16 save;
1324 u16 addr[MHFMAX] = {
1325 M_HOST_FLAGS1, M_HOST_FLAGS2, M_HOST_FLAGS3, M_HOST_FLAGS4,
1326 M_HOST_FLAGS5
1327 };
1328 struct brcms_hw_band *band;
1329
1330 if ((val & ~mask) || idx >= MHFMAX)
1331 return;
1332
1333 switch (bands) {
1334
1335
1336
1337 case BRCM_BAND_AUTO:
1338 case BRCM_BAND_ALL:
1339 band = wlc_hw->band;
1340 break;
1341 case BRCM_BAND_5G:
1342 band = wlc_hw->bandstate[BAND_5G_INDEX];
1343 break;
1344 case BRCM_BAND_2G:
1345 band = wlc_hw->bandstate[BAND_2G_INDEX];
1346 break;
1347 default:
1348 band = NULL;
1349 }
1350
1351 if (band) {
1352 save = band->mhfs[idx];
1353 band->mhfs[idx] = (band->mhfs[idx] & ~mask) | val;
1354
1355
1356
1357
1358 if (wlc_hw->clk && (band->mhfs[idx] != save)
1359 && (band == wlc_hw->band))
1360 brcms_b_write_shm(wlc_hw, addr[idx],
1361 (u16) band->mhfs[idx]);
1362 }
1363
1364 if (bands == BRCM_BAND_ALL) {
1365 wlc_hw->bandstate[0]->mhfs[idx] =
1366 (wlc_hw->bandstate[0]->mhfs[idx] & ~mask) | val;
1367 wlc_hw->bandstate[1]->mhfs[idx] =
1368 (wlc_hw->bandstate[1]->mhfs[idx] & ~mask) | val;
1369 }
1370}
1371
1372
1373
1374
1375static void brcms_c_mctrl_reset(struct brcms_hardware *wlc_hw)
1376{
1377
1378 wlc_hw->maccontrol = 0;
1379 wlc_hw->suspended_fifos = 0;
1380 wlc_hw->wake_override = 0;
1381 wlc_hw->mute_override = 0;
1382 brcms_b_mctrl(wlc_hw, ~0, MCTL_IHR_EN | MCTL_WAKE);
1383}
1384
1385
1386
1387
1388
1389static void brcms_c_mctrl_write(struct brcms_hardware *wlc_hw)
1390{
1391 u32 maccontrol = wlc_hw->maccontrol;
1392
1393
1394 if (wlc_hw->wake_override)
1395 maccontrol |= MCTL_WAKE;
1396
1397
1398 if (wlc_hw->mute_override) {
1399 maccontrol &= ~(MCTL_AP);
1400 maccontrol |= MCTL_INFRA;
1401 }
1402
1403 bcma_write32(wlc_hw->d11core, D11REGOFFS(maccontrol),
1404 maccontrol);
1405}
1406
1407
1408void brcms_b_mctrl(struct brcms_hardware *wlc_hw, u32 mask, u32 val)
1409{
1410 u32 maccontrol;
1411 u32 new_maccontrol;
1412
1413 if (val & ~mask)
1414 return;
1415 maccontrol = wlc_hw->maccontrol;
1416 new_maccontrol = (maccontrol & ~mask) | val;
1417
1418
1419 if (new_maccontrol == maccontrol)
1420 return;
1421
1422
1423 wlc_hw->maccontrol = new_maccontrol;
1424
1425
1426 brcms_c_mctrl_write(wlc_hw);
1427}
1428
1429void brcms_c_ucode_wake_override_set(struct brcms_hardware *wlc_hw,
1430 u32 override_bit)
1431{
1432 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE)) {
1433 mboolset(wlc_hw->wake_override, override_bit);
1434 return;
1435 }
1436
1437 mboolset(wlc_hw->wake_override, override_bit);
1438
1439 brcms_c_mctrl_write(wlc_hw);
1440 brcms_b_wait_for_wake(wlc_hw);
1441}
1442
1443void brcms_c_ucode_wake_override_clear(struct brcms_hardware *wlc_hw,
1444 u32 override_bit)
1445{
1446 mboolclr(wlc_hw->wake_override, override_bit);
1447
1448 if (wlc_hw->wake_override || (wlc_hw->maccontrol & MCTL_WAKE))
1449 return;
1450
1451 brcms_c_mctrl_write(wlc_hw);
1452}
1453
1454
1455
1456
1457
1458
1459
1460
1461static void brcms_c_ucode_mute_override_set(struct brcms_hardware *wlc_hw)
1462{
1463 wlc_hw->mute_override = 1;
1464
1465
1466
1467
1468 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1469 return;
1470
1471 brcms_c_mctrl_write(wlc_hw);
1472}
1473
1474
1475static void brcms_c_ucode_mute_override_clear(struct brcms_hardware *wlc_hw)
1476{
1477 if (wlc_hw->mute_override == 0)
1478 return;
1479
1480 wlc_hw->mute_override = 0;
1481
1482
1483
1484
1485 if ((wlc_hw->maccontrol & (MCTL_AP | MCTL_INFRA)) == MCTL_INFRA)
1486 return;
1487
1488 brcms_c_mctrl_write(wlc_hw);
1489}
1490
1491
1492
1493
1494static void
1495brcms_b_set_addrmatch(struct brcms_hardware *wlc_hw, int match_reg_offset,
1496 const u8 *addr)
1497{
1498 struct bcma_device *core = wlc_hw->d11core;
1499 u16 mac_l;
1500 u16 mac_m;
1501 u16 mac_h;
1502
1503 brcms_dbg_rx(core, "wl%d: brcms_b_set_addrmatch\n", wlc_hw->unit);
1504
1505 mac_l = addr[0] | (addr[1] << 8);
1506 mac_m = addr[2] | (addr[3] << 8);
1507 mac_h = addr[4] | (addr[5] << 8);
1508
1509
1510 bcma_write16(core, D11REGOFFS(rcm_ctl),
1511 RCM_INC_DATA | match_reg_offset);
1512 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_l);
1513 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_m);
1514 bcma_write16(core, D11REGOFFS(rcm_mat_data), mac_h);
1515}
1516
1517void
1518brcms_b_write_template_ram(struct brcms_hardware *wlc_hw, int offset, int len,
1519 void *buf)
1520{
1521 struct bcma_device *core = wlc_hw->d11core;
1522 u32 word;
1523 __le32 word_le;
1524 __be32 word_be;
1525 bool be_bit;
1526 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
1527
1528 bcma_write32(core, D11REGOFFS(tplatewrptr), offset);
1529
1530
1531
1532
1533
1534 be_bit = (bcma_read32(core, D11REGOFFS(maccontrol)) & MCTL_BIGEND) != 0;
1535
1536 while (len > 0) {
1537 memcpy(&word, buf, sizeof(u32));
1538
1539 if (be_bit) {
1540 word_be = cpu_to_be32(word);
1541 word = *(u32 *)&word_be;
1542 } else {
1543 word_le = cpu_to_le32(word);
1544 word = *(u32 *)&word_le;
1545 }
1546
1547 bcma_write32(core, D11REGOFFS(tplatewrdata), word);
1548
1549 buf = (u8 *) buf + sizeof(u32);
1550 len -= sizeof(u32);
1551 }
1552}
1553
1554static void brcms_b_set_cwmin(struct brcms_hardware *wlc_hw, u16 newmin)
1555{
1556 wlc_hw->band->CWmin = newmin;
1557
1558 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1559 OBJADDR_SCR_SEL | S_DOT11_CWMIN);
1560 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1561 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmin);
1562}
1563
1564static void brcms_b_set_cwmax(struct brcms_hardware *wlc_hw, u16 newmax)
1565{
1566 wlc_hw->band->CWmax = newmax;
1567
1568 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
1569 OBJADDR_SCR_SEL | S_DOT11_CWMAX);
1570 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
1571 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), newmax);
1572}
1573
1574void brcms_b_bw_set(struct brcms_hardware *wlc_hw, u16 bw)
1575{
1576 bool fastclk;
1577
1578
1579 fastclk = wlc_hw->forcefastclk;
1580 if (!fastclk)
1581 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
1582
1583 wlc_phy_bw_state_set(wlc_hw->band->pi, bw);
1584
1585 brcms_b_phy_reset(wlc_hw);
1586 wlc_phy_init(wlc_hw->band->pi, wlc_phy_chanspec_get(wlc_hw->band->pi));
1587
1588
1589 if (!fastclk)
1590 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
1591}
1592
1593static void brcms_b_upd_synthpu(struct brcms_hardware *wlc_hw)
1594{
1595 u16 v;
1596 struct brcms_c_info *wlc = wlc_hw->wlc;
1597
1598
1599 if (BRCMS_ISLCNPHY(wlc->band))
1600 v = SYNTHPU_DLY_LPPHY_US;
1601 else if (BRCMS_ISNPHY(wlc->band) && (NREV_GE(wlc->band->phyrev, 3)))
1602 v = SYNTHPU_DLY_NPHY_US;
1603 else
1604 v = SYNTHPU_DLY_BPHY_US;
1605
1606 brcms_b_write_shm(wlc_hw, M_SYNTHPU_DLY, v);
1607}
1608
1609static void brcms_c_ucode_txant_set(struct brcms_hardware *wlc_hw)
1610{
1611 u16 phyctl;
1612 u16 phytxant = wlc_hw->bmac_phytxant;
1613 u16 mask = PHY_TXC_ANT_MASK;
1614
1615
1616 phyctl = brcms_b_read_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS);
1617 phyctl = (phyctl & ~mask) | phytxant;
1618 brcms_b_write_shm(wlc_hw, M_CTXPRS_BLK + C_CTX_PCTLWD_POS, phyctl);
1619
1620
1621 phyctl = brcms_b_read_shm(wlc_hw, M_RSP_PCTLWD);
1622 phyctl = (phyctl & ~mask) | phytxant;
1623 brcms_b_write_shm(wlc_hw, M_RSP_PCTLWD, phyctl);
1624}
1625
1626static u16 brcms_b_ofdm_ratetable_offset(struct brcms_hardware *wlc_hw,
1627 u8 rate)
1628{
1629 uint i;
1630 u8 plcp_rate = 0;
1631 struct plcp_signal_rate_lookup {
1632 u8 rate;
1633 u8 signal_rate;
1634 };
1635
1636 const struct plcp_signal_rate_lookup rate_lookup[] = {
1637 {BRCM_RATE_6M, 0xB},
1638 {BRCM_RATE_9M, 0xF},
1639 {BRCM_RATE_12M, 0xA},
1640 {BRCM_RATE_18M, 0xE},
1641 {BRCM_RATE_24M, 0x9},
1642 {BRCM_RATE_36M, 0xD},
1643 {BRCM_RATE_48M, 0x8},
1644 {BRCM_RATE_54M, 0xC}
1645 };
1646
1647 for (i = 0; i < ARRAY_SIZE(rate_lookup); i++) {
1648 if (rate == rate_lookup[i].rate) {
1649 plcp_rate = rate_lookup[i].signal_rate;
1650 break;
1651 }
1652 }
1653
1654
1655
1656
1657 return 2 * brcms_b_read_shm(wlc_hw, M_RT_DIRMAP_A + (plcp_rate * 2));
1658}
1659
1660static void brcms_upd_ofdm_pctl1_table(struct brcms_hardware *wlc_hw)
1661{
1662 u8 rate;
1663 u8 rates[8] = {
1664 BRCM_RATE_6M, BRCM_RATE_9M, BRCM_RATE_12M, BRCM_RATE_18M,
1665 BRCM_RATE_24M, BRCM_RATE_36M, BRCM_RATE_48M, BRCM_RATE_54M
1666 };
1667 u16 entry_ptr;
1668 u16 pctl1;
1669 uint i;
1670
1671 if (!BRCMS_PHY_11N_CAP(wlc_hw->band))
1672 return;
1673
1674
1675 for (i = 0; i < ARRAY_SIZE(rates); i++) {
1676 rate = rates[i];
1677
1678 entry_ptr = brcms_b_ofdm_ratetable_offset(wlc_hw, rate);
1679
1680
1681 pctl1 =
1682 brcms_b_read_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS);
1683
1684
1685 pctl1 &= ~PHY_TXC1_MODE_MASK;
1686 pctl1 |= (wlc_hw->hw_stf_ss_opmode << PHY_TXC1_MODE_SHIFT);
1687
1688
1689 brcms_b_write_shm(wlc_hw, entry_ptr + M_RT_OFDM_PCTL1_POS,
1690 pctl1);
1691 }
1692}
1693
1694
1695static void brcms_b_bsinit(struct brcms_c_info *wlc, u16 chanspec)
1696{
1697 struct brcms_hardware *wlc_hw = wlc->hw;
1698
1699 brcms_dbg_mac80211(wlc_hw->d11core, "wl%d: bandunit %d\n", wlc_hw->unit,
1700 wlc_hw->band->bandunit);
1701
1702 brcms_c_ucode_bsinit(wlc_hw);
1703
1704 wlc_phy_init(wlc_hw->band->pi, chanspec);
1705
1706 brcms_c_ucode_txant_set(wlc_hw);
1707
1708
1709
1710
1711
1712 brcms_b_set_cwmin(wlc_hw, wlc_hw->band->CWmin);
1713 brcms_b_set_cwmax(wlc_hw, wlc_hw->band->CWmax);
1714
1715 brcms_b_update_slot_timing(wlc_hw,
1716 wlc_hw->band->bandtype == BRCM_BAND_5G ?
1717 true : wlc_hw->shortslot);
1718
1719
1720 brcms_b_write_shm(wlc_hw, M_PHYTYPE, (u16) wlc_hw->band->phytype);
1721 brcms_b_write_shm(wlc_hw, M_PHYVER, (u16) wlc_hw->band->phyrev);
1722
1723
1724
1725
1726
1727 brcms_upd_ofdm_pctl1_table(wlc_hw);
1728
1729 brcms_b_upd_synthpu(wlc_hw);
1730}
1731
1732
1733void brcms_b_core_phypll_reset(struct brcms_hardware *wlc_hw)
1734{
1735 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_addr),
1736 ~0, 0);
1737 udelay(1);
1738 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1739 0x4, 0);
1740 udelay(1);
1741 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1742 0x4, 4);
1743 udelay(1);
1744 ai_cc_reg(wlc_hw->sih, offsetof(struct chipcregs, chipcontrol_data),
1745 0x4, 0);
1746 udelay(1);
1747}
1748
1749
1750
1751
1752void brcms_b_phyclk_fgc(struct brcms_hardware *wlc_hw, bool clk)
1753{
1754
1755 if (!BRCMS_ISNPHY(wlc_hw->band))
1756 return;
1757
1758 if (ON == clk)
1759 brcms_b_core_ioctl(wlc_hw, SICF_FGC, SICF_FGC);
1760 else
1761 brcms_b_core_ioctl(wlc_hw, SICF_FGC, 0);
1762
1763}
1764
1765void brcms_b_macphyclk_set(struct brcms_hardware *wlc_hw, bool clk)
1766{
1767 if (ON == clk)
1768 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, SICF_MPCLKE);
1769 else
1770 brcms_b_core_ioctl(wlc_hw, SICF_MPCLKE, 0);
1771}
1772
1773void brcms_b_phy_reset(struct brcms_hardware *wlc_hw)
1774{
1775 struct brcms_phy_pub *pih = wlc_hw->band->pi;
1776 u32 phy_bw_clkbits;
1777
1778 brcms_dbg_info(wlc_hw->d11core, "wl%d: reset phy\n", wlc_hw->unit);
1779
1780 if (pih == NULL)
1781 return;
1782
1783 phy_bw_clkbits = wlc_phy_clk_bwbits(wlc_hw->band->pi);
1784
1785
1786 if (BRCMS_ISNPHY(wlc_hw->band) && NREV_GE(wlc_hw->band->phyrev, 3) &&
1787 NREV_LE(wlc_hw->band->phyrev, 4)) {
1788
1789 brcms_b_core_ioctl(wlc_hw, SICF_BWMASK, phy_bw_clkbits);
1790
1791 udelay(1);
1792
1793
1794 brcms_b_core_phypll_reset(wlc_hw);
1795
1796
1797 brcms_b_core_ioctl(wlc_hw, (SICF_PRST | SICF_PCLKE),
1798 (SICF_PRST | SICF_PCLKE));
1799 } else {
1800 brcms_b_core_ioctl(wlc_hw,
1801 (SICF_PRST | SICF_PCLKE | SICF_BWMASK),
1802 (SICF_PRST | SICF_PCLKE | phy_bw_clkbits));
1803 }
1804
1805 udelay(2);
1806 brcms_b_core_phy_clk(wlc_hw, ON);
1807
1808 wlc_phy_anacore(pih, ON);
1809}
1810
1811
1812static void brcms_b_setband(struct brcms_hardware *wlc_hw, uint bandunit,
1813 u16 chanspec) {
1814 struct brcms_c_info *wlc = wlc_hw->wlc;
1815 u32 macintmask;
1816
1817
1818 if (!bcma_core_is_enabled(wlc_hw->d11core)) {
1819 bcma_core_enable(wlc_hw->d11core, 0);
1820 brcms_c_mctrl_reset(wlc_hw);
1821 }
1822
1823 macintmask = brcms_c_setband_inact(wlc, bandunit);
1824
1825 if (!wlc_hw->up)
1826 return;
1827
1828 brcms_b_core_phy_clk(wlc_hw, ON);
1829
1830
1831 brcms_b_bsinit(wlc, chanspec);
1832
1833
1834
1835
1836
1837
1838 if (wlc->macintstatus)
1839 wlc->macintstatus = MI_DMAINT;
1840
1841
1842 brcms_intrsrestore(wlc->wl, macintmask);
1843
1844
1845 WARN_ON((bcma_read32(wlc_hw->d11core, D11REGOFFS(maccontrol)) &
1846 MCTL_EN_MAC) != 0);
1847}
1848
1849static bool brcms_c_isgoodchip(struct brcms_hardware *wlc_hw)
1850{
1851
1852
1853 if (!CONF_HAS(D11CONF, wlc_hw->corerev)) {
1854 wiphy_err(wlc_hw->wlc->wiphy, "unsupported core rev %d\n",
1855 wlc_hw->corerev);
1856 return false;
1857 }
1858
1859 return true;
1860}
1861
1862
1863static bool brcms_c_validboardtype(struct brcms_hardware *wlc_hw)
1864{
1865 uint boardrev = wlc_hw->boardrev;
1866
1867
1868 uint brt = (boardrev & 0xf000) >> 12;
1869 uint b0 = (boardrev & 0xf00) >> 8;
1870 uint b1 = (boardrev & 0xf0) >> 4;
1871 uint b2 = boardrev & 0xf;
1872
1873
1874 if (ai_get_boardvendor(wlc_hw->sih) != PCI_VENDOR_ID_BROADCOM)
1875 return true;
1876
1877
1878 if (boardrev == 0)
1879 return false;
1880
1881 if (boardrev <= 0xff)
1882 return true;
1883
1884 if ((brt > 2) || (brt == 0) || (b0 > 9) || (b0 == 0) || (b1 > 9)
1885 || (b2 > 9))
1886 return false;
1887
1888 return true;
1889}
1890
1891static void brcms_c_get_macaddr(struct brcms_hardware *wlc_hw, u8 etheraddr[ETH_ALEN])
1892{
1893 struct ssb_sprom *sprom = &wlc_hw->d11core->bus->sprom;
1894
1895
1896 if (!is_zero_ether_addr(sprom->il0mac)) {
1897 memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
1898 return;
1899 }
1900
1901 if (wlc_hw->_nbands > 1)
1902 memcpy(etheraddr, sprom->et1mac, ETH_ALEN);
1903 else
1904 memcpy(etheraddr, sprom->il0mac, ETH_ALEN);
1905}
1906
1907
1908static void brcms_b_xtal(struct brcms_hardware *wlc_hw, bool want)
1909{
1910 brcms_dbg_info(wlc_hw->d11core, "wl%d: want %d\n", wlc_hw->unit, want);
1911
1912
1913
1914
1915
1916 if (!want && wlc_hw->pllreq)
1917 return;
1918
1919 wlc_hw->sbclk = want;
1920 if (!wlc_hw->sbclk) {
1921 wlc_hw->clk = false;
1922 if (wlc_hw->band && wlc_hw->band->pi)
1923 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
1924 }
1925}
1926
1927
1928
1929
1930
1931
1932
1933static bool brcms_b_radio_read_hwdisabled(struct brcms_hardware *wlc_hw)
1934{
1935 bool v, clk, xtal;
1936 u32 flags = 0;
1937
1938 xtal = wlc_hw->sbclk;
1939 if (!xtal)
1940 brcms_b_xtal(wlc_hw, ON);
1941
1942
1943 clk = wlc_hw->clk;
1944 if (!clk) {
1945
1946
1947
1948
1949
1950 if (D11REV_GE(wlc_hw->corerev, 18))
1951 flags |= SICF_PCLKE;
1952
1953
1954
1955
1956
1957
1958
1959
1960 bcma_core_enable(wlc_hw->d11core, flags);
1961 brcms_c_mctrl_reset(wlc_hw);
1962 }
1963
1964 v = ((bcma_read32(wlc_hw->d11core,
1965 D11REGOFFS(phydebug)) & PDBG_RFD) != 0);
1966
1967
1968 if (!clk)
1969 bcma_core_disable(wlc_hw->d11core, 0);
1970
1971 if (!xtal)
1972 brcms_b_xtal(wlc_hw, OFF);
1973
1974 return v;
1975}
1976
1977static bool wlc_dma_rxreset(struct brcms_hardware *wlc_hw, uint fifo)
1978{
1979 struct dma_pub *di = wlc_hw->di[fifo];
1980 return dma_rxreset(di);
1981}
1982
1983
1984
1985
1986
1987
1988
1989
1990
1991void brcms_b_corereset(struct brcms_hardware *wlc_hw, u32 flags)
1992{
1993 uint i;
1994 bool fastclk;
1995
1996 if (flags == BRCMS_USE_COREFLAGS)
1997 flags = (wlc_hw->band->pi ? wlc_hw->band->core_flags : 0);
1998
1999 brcms_dbg_info(wlc_hw->d11core, "wl%d: core reset\n", wlc_hw->unit);
2000
2001
2002 fastclk = wlc_hw->forcefastclk;
2003 if (!fastclk)
2004 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2005
2006
2007 if (bcma_core_is_enabled(wlc_hw->d11core)) {
2008 for (i = 0; i < NFIFO; i++)
2009 if ((wlc_hw->di[i]) && (!dma_txreset(wlc_hw->di[i])))
2010 brcms_err(wlc_hw->d11core, "wl%d: %s: "
2011 "dma_txreset[%d]: cannot stop dma\n",
2012 wlc_hw->unit, __func__, i);
2013
2014 if ((wlc_hw->di[RX_FIFO])
2015 && (!wlc_dma_rxreset(wlc_hw, RX_FIFO)))
2016 brcms_err(wlc_hw->d11core, "wl%d: %s: dma_rxreset"
2017 "[%d]: cannot stop dma\n",
2018 wlc_hw->unit, __func__, RX_FIFO);
2019 }
2020
2021 if (wlc_hw->noreset) {
2022 wlc_hw->wlc->macintstatus = 0;
2023 brcms_b_mctrl(wlc_hw, MCTL_PSM_RUN | MCTL_EN_MAC, 0);
2024 return;
2025 }
2026
2027
2028
2029
2030
2031
2032 if (D11REV_GE(wlc_hw->corerev, 18))
2033 flags |= SICF_PCLKE;
2034
2035
2036
2037
2038
2039
2040
2041
2042
2043
2044
2045 wlc_hw->clk = false;
2046 bcma_core_enable(wlc_hw->d11core, flags);
2047 wlc_hw->clk = true;
2048 if (wlc_hw->band && wlc_hw->band->pi)
2049 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, true);
2050
2051 brcms_c_mctrl_reset(wlc_hw);
2052
2053 if (ai_get_cccaps(wlc_hw->sih) & CC_CAP_PMU)
2054 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
2055
2056 brcms_b_phy_reset(wlc_hw);
2057
2058
2059 brcms_b_core_phypll_ctl(wlc_hw, true);
2060
2061
2062 wlc_hw->wlc->macintstatus = 0;
2063
2064
2065 if (!fastclk)
2066 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
2067}
2068
2069
2070
2071
2072static void brcms_b_corerev_fifofixup(struct brcms_hardware *wlc_hw)
2073{
2074 struct bcma_device *core = wlc_hw->d11core;
2075 u16 fifo_nu;
2076 u16 txfifo_startblk = TXFIFO_START_BLK, txfifo_endblk;
2077 u16 txfifo_def, txfifo_def1;
2078 u16 txfifo_cmd;
2079
2080
2081 txfifo_startblk = TXFIFO_START_BLK;
2082
2083
2084 for (fifo_nu = 0; fifo_nu < NFIFO; fifo_nu++) {
2085
2086 txfifo_endblk = txfifo_startblk + wlc_hw->xmtfifo_sz[fifo_nu];
2087 txfifo_def = (txfifo_startblk & 0xff) |
2088 (((txfifo_endblk - 1) & 0xff) << TXFIFO_FIFOTOP_SHIFT);
2089 txfifo_def1 = ((txfifo_startblk >> 8) & 0x1) |
2090 ((((txfifo_endblk -
2091 1) >> 8) & 0x1) << TXFIFO_FIFOTOP_SHIFT);
2092 txfifo_cmd =
2093 TXFIFOCMD_RESET_MASK | (fifo_nu << TXFIFOCMD_FIFOSEL_SHIFT);
2094
2095 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2096 bcma_write16(core, D11REGOFFS(xmtfifodef), txfifo_def);
2097 bcma_write16(core, D11REGOFFS(xmtfifodef1), txfifo_def1);
2098
2099 bcma_write16(core, D11REGOFFS(xmtfifocmd), txfifo_cmd);
2100
2101 txfifo_startblk += wlc_hw->xmtfifo_sz[fifo_nu];
2102 }
2103
2104
2105
2106
2107 brcms_b_write_shm(wlc_hw, M_FIFOSIZE0,
2108 wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]);
2109 brcms_b_write_shm(wlc_hw, M_FIFOSIZE1,
2110 wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]);
2111 brcms_b_write_shm(wlc_hw, M_FIFOSIZE2,
2112 ((wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO] << 8) | wlc_hw->
2113 xmtfifo_sz[TX_AC_BK_FIFO]));
2114 brcms_b_write_shm(wlc_hw, M_FIFOSIZE3,
2115 ((wlc_hw->xmtfifo_sz[TX_ATIM_FIFO] << 8) | wlc_hw->
2116 xmtfifo_sz[TX_BCMC_FIFO]));
2117}
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132void brcms_b_switch_macfreq(struct brcms_hardware *wlc_hw, u8 spurmode)
2133{
2134 struct bcma_device *core = wlc_hw->d11core;
2135
2136 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43224) ||
2137 (ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM43225)) {
2138 if (spurmode == WL_SPURAVOID_ON2) {
2139 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x2082);
2140 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2141 } else if (spurmode == WL_SPURAVOID_ON1) {
2142 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x5341);
2143 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2144 } else {
2145 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x8889);
2146 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0x8);
2147 }
2148 } else if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2149 if (spurmode == WL_SPURAVOID_ON1) {
2150 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0x7CE0);
2151 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2152 } else {
2153 bcma_write16(core, D11REGOFFS(tsf_clk_frac_l), 0xCCCD);
2154 bcma_write16(core, D11REGOFFS(tsf_clk_frac_h), 0xC);
2155 }
2156 }
2157}
2158
2159void brcms_c_start_station(struct brcms_c_info *wlc, u8 *addr)
2160{
2161 memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2162 wlc->bsscfg->type = BRCMS_TYPE_STATION;
2163}
2164
2165void brcms_c_start_ap(struct brcms_c_info *wlc, u8 *addr, const u8 *bssid,
2166 u8 *ssid, size_t ssid_len)
2167{
2168 brcms_c_set_ssid(wlc, ssid, ssid_len);
2169
2170 memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2171 memcpy(wlc->bsscfg->BSSID, bssid, sizeof(wlc->bsscfg->BSSID));
2172 wlc->bsscfg->type = BRCMS_TYPE_AP;
2173
2174 brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, MCTL_AP | MCTL_INFRA);
2175}
2176
2177void brcms_c_start_adhoc(struct brcms_c_info *wlc, u8 *addr)
2178{
2179 memcpy(wlc->pub->cur_etheraddr, addr, sizeof(wlc->pub->cur_etheraddr));
2180 wlc->bsscfg->type = BRCMS_TYPE_ADHOC;
2181
2182 brcms_b_mctrl(wlc->hw, MCTL_AP | MCTL_INFRA, 0);
2183}
2184
2185
2186static void brcms_c_gpio_init(struct brcms_c_info *wlc)
2187{
2188 struct brcms_hardware *wlc_hw = wlc->hw;
2189 u32 gc, gm;
2190
2191
2192 brcms_b_mctrl(wlc_hw, MCTL_GPOUT_SEL_MASK, 0);
2193
2194
2195
2196
2197
2198
2199
2200
2201
2202 gc = gm = 0;
2203
2204
2205 if (wlc_hw->antsel_type == ANTSEL_2x3) {
2206
2207 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2208 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2209 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE,
2210 MHF3_ANTSEL_MODE, BRCM_BAND_ALL);
2211
2212
2213 wlc_phy_antsel_init(wlc_hw->band->pi, false);
2214
2215 } else if (wlc_hw->antsel_type == ANTSEL_2x4) {
2216 gm |= gc |= (BOARD_GPIO_12 | BOARD_GPIO_13);
2217
2218
2219
2220
2221 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_oe),
2222 (BOARD_GPIO_12 | BOARD_GPIO_13));
2223 bcma_set16(wlc_hw->d11core, D11REGOFFS(psm_gpio_out),
2224 (BOARD_GPIO_12 | BOARD_GPIO_13));
2225
2226
2227 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_EN,
2228 MHF3_ANTSEL_EN, BRCM_BAND_ALL);
2229 brcms_b_mhf(wlc_hw, MHF3, MHF3_ANTSEL_MODE, 0,
2230 BRCM_BAND_ALL);
2231
2232
2233 brcms_b_write_shm(wlc_hw, M_ANTSEL_CLKDIV,
2234 ANTSEL_CLKDIV_4MHZ);
2235 }
2236
2237
2238
2239
2240
2241 if (wlc_hw->boardflags & BFL_PACTRL)
2242 gm |= gc |= BOARD_GPIO_PACTRL;
2243
2244
2245 bcma_chipco_gpio_control(&wlc_hw->d11core->bus->drv_cc, gm, gc);
2246}
2247
2248static void brcms_ucode_write(struct brcms_hardware *wlc_hw,
2249 const __le32 ucode[], const size_t nbytes)
2250{
2251 struct bcma_device *core = wlc_hw->d11core;
2252 uint i;
2253 uint count;
2254
2255 brcms_dbg_info(wlc_hw->d11core, "wl%d\n", wlc_hw->unit);
2256
2257 count = (nbytes / sizeof(u32));
2258
2259 bcma_write32(core, D11REGOFFS(objaddr),
2260 OBJADDR_AUTO_INC | OBJADDR_UCM_SEL);
2261 (void)bcma_read32(core, D11REGOFFS(objaddr));
2262 for (i = 0; i < count; i++)
2263 bcma_write32(core, D11REGOFFS(objdata), le32_to_cpu(ucode[i]));
2264
2265}
2266
2267static void brcms_ucode_download(struct brcms_hardware *wlc_hw)
2268{
2269 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
2270
2271 if (wlc_hw->ucode_loaded)
2272 return;
2273
2274 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
2275 if (BRCMS_ISNPHY(wlc_hw->band)) {
2276 brcms_ucode_write(wlc_hw, ucode->bcm43xx_16_mimo,
2277 ucode->bcm43xx_16_mimosz);
2278 wlc_hw->ucode_loaded = true;
2279 } else
2280 brcms_err(wlc_hw->d11core,
2281 "%s: wl%d: unsupported phy in corerev %d\n",
2282 __func__, wlc_hw->unit, wlc_hw->corerev);
2283 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
2284 if (BRCMS_ISLCNPHY(wlc_hw->band)) {
2285 brcms_ucode_write(wlc_hw, ucode->bcm43xx_24_lcn,
2286 ucode->bcm43xx_24_lcnsz);
2287 wlc_hw->ucode_loaded = true;
2288 } else {
2289 brcms_err(wlc_hw->d11core,
2290 "%s: wl%d: unsupported phy in corerev %d\n",
2291 __func__, wlc_hw->unit, wlc_hw->corerev);
2292 }
2293 }
2294}
2295
2296void brcms_b_txant_set(struct brcms_hardware *wlc_hw, u16 phytxant)
2297{
2298
2299 wlc_hw->bmac_phytxant = phytxant;
2300
2301
2302 if (!wlc_hw->up)
2303 return;
2304 brcms_c_ucode_txant_set(wlc_hw);
2305
2306}
2307
2308u16 brcms_b_get_txant(struct brcms_hardware *wlc_hw)
2309{
2310 return (u16) wlc_hw->wlc->stf->txant;
2311}
2312
2313void brcms_b_antsel_type_set(struct brcms_hardware *wlc_hw, u8 antsel_type)
2314{
2315 wlc_hw->antsel_type = antsel_type;
2316
2317
2318 wlc_phy_antsel_type_set(wlc_hw->band->pi, antsel_type);
2319}
2320
2321static void brcms_b_fifoerrors(struct brcms_hardware *wlc_hw)
2322{
2323 bool fatal = false;
2324 uint unit;
2325 uint intstatus, idx;
2326 struct bcma_device *core = wlc_hw->d11core;
2327
2328 unit = wlc_hw->unit;
2329
2330 for (idx = 0; idx < NFIFO; idx++) {
2331
2332 intstatus =
2333 bcma_read32(core,
2334 D11REGOFFS(intctrlregs[idx].intstatus)) &
2335 I_ERRORS;
2336 if (!intstatus)
2337 continue;
2338
2339 brcms_dbg_int(core, "wl%d: intstatus%d 0x%x\n",
2340 unit, idx, intstatus);
2341
2342 if (intstatus & I_RO) {
2343 brcms_err(core, "wl%d: fifo %d: receive fifo "
2344 "overflow\n", unit, idx);
2345 fatal = true;
2346 }
2347
2348 if (intstatus & I_PC) {
2349 brcms_err(core, "wl%d: fifo %d: descriptor error\n",
2350 unit, idx);
2351 fatal = true;
2352 }
2353
2354 if (intstatus & I_PD) {
2355 brcms_err(core, "wl%d: fifo %d: data error\n", unit,
2356 idx);
2357 fatal = true;
2358 }
2359
2360 if (intstatus & I_DE) {
2361 brcms_err(core, "wl%d: fifo %d: descriptor protocol "
2362 "error\n", unit, idx);
2363 fatal = true;
2364 }
2365
2366 if (intstatus & I_RU)
2367 brcms_err(core, "wl%d: fifo %d: receive descriptor "
2368 "underflow\n", idx, unit);
2369
2370 if (intstatus & I_XU) {
2371 brcms_err(core, "wl%d: fifo %d: transmit fifo "
2372 "underflow\n", idx, unit);
2373 fatal = true;
2374 }
2375
2376 if (fatal) {
2377 brcms_fatal_error(wlc_hw->wlc->wl);
2378 break;
2379 } else
2380 bcma_write32(core,
2381 D11REGOFFS(intctrlregs[idx].intstatus),
2382 intstatus);
2383 }
2384}
2385
2386void brcms_c_intrson(struct brcms_c_info *wlc)
2387{
2388 struct brcms_hardware *wlc_hw = wlc->hw;
2389 wlc->macintmask = wlc->defmacintmask;
2390 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2391}
2392
2393u32 brcms_c_intrsoff(struct brcms_c_info *wlc)
2394{
2395 struct brcms_hardware *wlc_hw = wlc->hw;
2396 u32 macintmask;
2397
2398 if (!wlc_hw->clk)
2399 return 0;
2400
2401 macintmask = wlc->macintmask;
2402
2403 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), 0);
2404 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(macintmask));
2405 udelay(1);
2406 wlc->macintmask = 0;
2407
2408
2409 return wlc->macintstatus ? 0 : macintmask;
2410}
2411
2412void brcms_c_intrsrestore(struct brcms_c_info *wlc, u32 macintmask)
2413{
2414 struct brcms_hardware *wlc_hw = wlc->hw;
2415 if (!wlc_hw->clk)
2416 return;
2417
2418 wlc->macintmask = macintmask;
2419 bcma_write32(wlc_hw->d11core, D11REGOFFS(macintmask), wlc->macintmask);
2420}
2421
2422
2423static void brcms_b_tx_fifo_suspend(struct brcms_hardware *wlc_hw,
2424 uint tx_fifo)
2425{
2426 u8 fifo = 1 << tx_fifo;
2427
2428
2429
2430
2431 if ((wlc_hw->suspended_fifos & fifo) == fifo)
2432 return;
2433
2434
2435 if (wlc_hw->suspended_fifos == 0)
2436 brcms_c_ucode_wake_override_set(wlc_hw,
2437 BRCMS_WAKE_OVERRIDE_TXFIFO);
2438
2439 wlc_hw->suspended_fifos |= fifo;
2440
2441 if (wlc_hw->di[tx_fifo]) {
2442
2443
2444
2445
2446
2447 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2448 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
2449
2450 dma_txsuspend(wlc_hw->di[tx_fifo]);
2451
2452 if (BRCMS_PHY_11N_CAP(wlc_hw->band))
2453 brcms_c_enable_mac(wlc_hw->wlc);
2454 }
2455}
2456
2457static void brcms_b_tx_fifo_resume(struct brcms_hardware *wlc_hw,
2458 uint tx_fifo)
2459{
2460
2461
2462
2463
2464
2465 if (wlc_hw->di[tx_fifo])
2466 dma_txresume(wlc_hw->di[tx_fifo]);
2467
2468
2469 if (wlc_hw->suspended_fifos == 0)
2470 return;
2471 else {
2472 wlc_hw->suspended_fifos &= ~(1 << tx_fifo);
2473 if (wlc_hw->suspended_fifos == 0)
2474 brcms_c_ucode_wake_override_clear(wlc_hw,
2475 BRCMS_WAKE_OVERRIDE_TXFIFO);
2476 }
2477}
2478
2479
2480static void brcms_b_mute(struct brcms_hardware *wlc_hw, bool mute_tx)
2481{
2482 static const u8 null_ether_addr[ETH_ALEN] = {0, 0, 0, 0, 0, 0};
2483 u8 *ethaddr = wlc_hw->wlc->pub->cur_etheraddr;
2484
2485 if (mute_tx) {
2486
2487 brcms_b_tx_fifo_suspend(wlc_hw, TX_DATA_FIFO);
2488 brcms_b_tx_fifo_suspend(wlc_hw, TX_CTL_FIFO);
2489 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_BK_FIFO);
2490 brcms_b_tx_fifo_suspend(wlc_hw, TX_AC_VI_FIFO);
2491
2492
2493 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, null_ether_addr);
2494 } else {
2495
2496 brcms_b_tx_fifo_resume(wlc_hw, TX_DATA_FIFO);
2497 brcms_b_tx_fifo_resume(wlc_hw, TX_CTL_FIFO);
2498 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_BK_FIFO);
2499 brcms_b_tx_fifo_resume(wlc_hw, TX_AC_VI_FIFO);
2500
2501
2502 brcms_b_set_addrmatch(wlc_hw, RCM_MAC_OFFSET, ethaddr);
2503 }
2504
2505 wlc_phy_mute_upd(wlc_hw->band->pi, mute_tx, 0);
2506
2507 if (mute_tx)
2508 brcms_c_ucode_mute_override_set(wlc_hw);
2509 else
2510 brcms_c_ucode_mute_override_clear(wlc_hw);
2511}
2512
2513void
2514brcms_c_mute(struct brcms_c_info *wlc, bool mute_tx)
2515{
2516 brcms_b_mute(wlc->hw, mute_tx);
2517}
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527static inline u32 wlc_intstatus(struct brcms_c_info *wlc, bool in_isr)
2528{
2529 struct brcms_hardware *wlc_hw = wlc->hw;
2530 struct bcma_device *core = wlc_hw->d11core;
2531 u32 macintstatus, mask;
2532
2533
2534 macintstatus = bcma_read32(core, D11REGOFFS(macintstatus));
2535 mask = in_isr ? wlc->macintmask : wlc->defmacintmask;
2536
2537 trace_brcms_macintstatus(&core->dev, in_isr, macintstatus, mask);
2538
2539
2540 if (brcms_deviceremoved(wlc))
2541 return -1;
2542
2543
2544
2545
2546 if (macintstatus == 0xffffffff)
2547 return 0;
2548
2549
2550 macintstatus &= mask;
2551
2552
2553 if (macintstatus == 0)
2554 return 0;
2555
2556
2557 bcma_write32(core, D11REGOFFS(macintmask), 0);
2558 (void)bcma_read32(core, D11REGOFFS(macintmask));
2559 wlc->macintmask = 0;
2560
2561
2562 bcma_write32(core, D11REGOFFS(macintstatus), macintstatus);
2563
2564
2565 if (macintstatus & MI_DMAINT)
2566
2567
2568
2569
2570
2571 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intstatus),
2572 DEF_RXINTMASK);
2573
2574 return macintstatus;
2575}
2576
2577
2578
2579bool brcms_c_intrsupd(struct brcms_c_info *wlc)
2580{
2581 u32 macintstatus;
2582
2583
2584 macintstatus = wlc_intstatus(wlc, false);
2585
2586
2587 if (macintstatus == 0xffffffff)
2588 return false;
2589
2590
2591 wlc->macintstatus |= macintstatus;
2592
2593 return true;
2594}
2595
2596
2597
2598
2599
2600
2601
2602bool brcms_c_isr(struct brcms_c_info *wlc)
2603{
2604 struct brcms_hardware *wlc_hw = wlc->hw;
2605 u32 macintstatus;
2606
2607 if (!wlc_hw->up || !wlc->macintmask)
2608 return false;
2609
2610
2611 macintstatus = wlc_intstatus(wlc, true);
2612
2613 if (macintstatus == 0xffffffff) {
2614 brcms_err(wlc_hw->d11core,
2615 "DEVICEREMOVED detected in the ISR code path\n");
2616 return false;
2617 }
2618
2619
2620 if (macintstatus == 0)
2621 return false;
2622
2623
2624 wlc->macintstatus = macintstatus;
2625
2626 return true;
2627
2628}
2629
2630void brcms_c_suspend_mac_and_wait(struct brcms_c_info *wlc)
2631{
2632 struct brcms_hardware *wlc_hw = wlc->hw;
2633 struct bcma_device *core = wlc_hw->d11core;
2634 u32 mc, mi;
2635
2636 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2637 wlc_hw->band->bandunit);
2638
2639
2640
2641
2642 wlc_hw->mac_suspend_depth++;
2643 if (wlc_hw->mac_suspend_depth > 1)
2644 return;
2645
2646
2647 brcms_c_ucode_wake_override_set(wlc_hw, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2648
2649 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2650
2651 if (mc == 0xffffffff) {
2652 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2653 __func__);
2654 brcms_down(wlc->wl);
2655 return;
2656 }
2657 WARN_ON(mc & MCTL_PSM_JMP_0);
2658 WARN_ON(!(mc & MCTL_PSM_RUN));
2659 WARN_ON(!(mc & MCTL_EN_MAC));
2660
2661 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2662 if (mi == 0xffffffff) {
2663 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2664 __func__);
2665 brcms_down(wlc->wl);
2666 return;
2667 }
2668 WARN_ON(mi & MI_MACSSPNDD);
2669
2670 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, 0);
2671
2672 SPINWAIT(!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD),
2673 BRCMS_MAX_MAC_SUSPEND);
2674
2675 if (!(bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD)) {
2676 brcms_err(core, "wl%d: wlc_suspend_mac_and_wait: waited %d uS"
2677 " and MI_MACSSPNDD is still not on.\n",
2678 wlc_hw->unit, BRCMS_MAX_MAC_SUSPEND);
2679 brcms_err(core, "wl%d: psmdebug 0x%08x, phydebug 0x%08x, "
2680 "psm_brc 0x%04x\n", wlc_hw->unit,
2681 bcma_read32(core, D11REGOFFS(psmdebug)),
2682 bcma_read32(core, D11REGOFFS(phydebug)),
2683 bcma_read16(core, D11REGOFFS(psm_brc)));
2684 }
2685
2686 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2687 if (mc == 0xffffffff) {
2688 brcms_err(core, "wl%d: %s: dead chip\n", wlc_hw->unit,
2689 __func__);
2690 brcms_down(wlc->wl);
2691 return;
2692 }
2693 WARN_ON(mc & MCTL_PSM_JMP_0);
2694 WARN_ON(!(mc & MCTL_PSM_RUN));
2695 WARN_ON(mc & MCTL_EN_MAC);
2696}
2697
2698void brcms_c_enable_mac(struct brcms_c_info *wlc)
2699{
2700 struct brcms_hardware *wlc_hw = wlc->hw;
2701 struct bcma_device *core = wlc_hw->d11core;
2702 u32 mc, mi;
2703
2704 brcms_dbg_mac80211(core, "wl%d: bandunit %d\n", wlc_hw->unit,
2705 wlc->band->bandunit);
2706
2707
2708
2709
2710 wlc_hw->mac_suspend_depth--;
2711 if (wlc_hw->mac_suspend_depth > 0)
2712 return;
2713
2714 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2715 WARN_ON(mc & MCTL_PSM_JMP_0);
2716 WARN_ON(mc & MCTL_EN_MAC);
2717 WARN_ON(!(mc & MCTL_PSM_RUN));
2718
2719 brcms_b_mctrl(wlc_hw, MCTL_EN_MAC, MCTL_EN_MAC);
2720 bcma_write32(core, D11REGOFFS(macintstatus), MI_MACSSPNDD);
2721
2722 mc = bcma_read32(core, D11REGOFFS(maccontrol));
2723 WARN_ON(mc & MCTL_PSM_JMP_0);
2724 WARN_ON(!(mc & MCTL_EN_MAC));
2725 WARN_ON(!(mc & MCTL_PSM_RUN));
2726
2727 mi = bcma_read32(core, D11REGOFFS(macintstatus));
2728 WARN_ON(mi & MI_MACSSPNDD);
2729
2730 brcms_c_ucode_wake_override_clear(wlc_hw,
2731 BRCMS_WAKE_OVERRIDE_MACSUSPEND);
2732}
2733
2734void brcms_b_band_stf_ss_set(struct brcms_hardware *wlc_hw, u8 stf_mode)
2735{
2736 wlc_hw->hw_stf_ss_opmode = stf_mode;
2737
2738 if (wlc_hw->clk)
2739 brcms_upd_ofdm_pctl1_table(wlc_hw);
2740}
2741
2742static bool brcms_b_validate_chip_access(struct brcms_hardware *wlc_hw)
2743{
2744 struct bcma_device *core = wlc_hw->d11core;
2745 u32 w, val;
2746 struct wiphy *wiphy = wlc_hw->wlc->wiphy;
2747
2748
2749
2750 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2751 (void)bcma_read32(core, D11REGOFFS(objaddr));
2752 w = bcma_read32(core, D11REGOFFS(objdata));
2753
2754
2755 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2756 (void)bcma_read32(core, D11REGOFFS(objaddr));
2757 bcma_write32(core, D11REGOFFS(objdata), (u32) 0xaa5555aa);
2758
2759 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2760 (void)bcma_read32(core, D11REGOFFS(objaddr));
2761 val = bcma_read32(core, D11REGOFFS(objdata));
2762 if (val != (u32) 0xaa5555aa) {
2763 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2764 "expected 0xaa5555aa\n", wlc_hw->unit, val);
2765 return false;
2766 }
2767
2768 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2769 (void)bcma_read32(core, D11REGOFFS(objaddr));
2770 bcma_write32(core, D11REGOFFS(objdata), (u32) 0x55aaaa55);
2771
2772 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2773 (void)bcma_read32(core, D11REGOFFS(objaddr));
2774 val = bcma_read32(core, D11REGOFFS(objdata));
2775 if (val != (u32) 0x55aaaa55) {
2776 wiphy_err(wiphy, "wl%d: validate_chip_access: SHM = 0x%x, "
2777 "expected 0x55aaaa55\n", wlc_hw->unit, val);
2778 return false;
2779 }
2780
2781 bcma_write32(core, D11REGOFFS(objaddr), OBJADDR_SHM_SEL | 0);
2782 (void)bcma_read32(core, D11REGOFFS(objaddr));
2783 bcma_write32(core, D11REGOFFS(objdata), w);
2784
2785
2786 bcma_write32(core, D11REGOFFS(tsf_cfpstart), 0);
2787
2788 w = bcma_read32(core, D11REGOFFS(maccontrol));
2789 if ((w != (MCTL_IHR_EN | MCTL_WAKE)) &&
2790 (w != (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE))) {
2791 wiphy_err(wiphy, "wl%d: validate_chip_access: maccontrol = "
2792 "0x%x, expected 0x%x or 0x%x\n", wlc_hw->unit, w,
2793 (MCTL_IHR_EN | MCTL_WAKE),
2794 (MCTL_IHR_EN | MCTL_GMODE | MCTL_WAKE));
2795 return false;
2796 }
2797
2798 return true;
2799}
2800
2801#define PHYPLL_WAIT_US 100000
2802
2803void brcms_b_core_phypll_ctl(struct brcms_hardware *wlc_hw, bool on)
2804{
2805 struct bcma_device *core = wlc_hw->d11core;
2806 u32 tmp;
2807
2808 brcms_dbg_info(core, "wl%d\n", wlc_hw->unit);
2809
2810 tmp = 0;
2811
2812 if (on) {
2813 if ((ai_get_chip_id(wlc_hw->sih) == BCMA_CHIP_ID_BCM4313)) {
2814 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2815 CCS_ERSRC_REQ_HT |
2816 CCS_ERSRC_REQ_D11PLL |
2817 CCS_ERSRC_REQ_PHYPLL);
2818 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2819 CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT,
2820 PHYPLL_WAIT_US);
2821
2822 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2823 if ((tmp & CCS_ERSRC_AVAIL_HT) != CCS_ERSRC_AVAIL_HT)
2824 brcms_err(core, "%s: turn on PHY PLL failed\n",
2825 __func__);
2826 } else {
2827 bcma_set32(core, D11REGOFFS(clk_ctl_st),
2828 tmp | CCS_ERSRC_REQ_D11PLL |
2829 CCS_ERSRC_REQ_PHYPLL);
2830 SPINWAIT((bcma_read32(core, D11REGOFFS(clk_ctl_st)) &
2831 (CCS_ERSRC_AVAIL_D11PLL |
2832 CCS_ERSRC_AVAIL_PHYPLL)) !=
2833 (CCS_ERSRC_AVAIL_D11PLL |
2834 CCS_ERSRC_AVAIL_PHYPLL), PHYPLL_WAIT_US);
2835
2836 tmp = bcma_read32(core, D11REGOFFS(clk_ctl_st));
2837 if ((tmp &
2838 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2839 !=
2840 (CCS_ERSRC_AVAIL_D11PLL | CCS_ERSRC_AVAIL_PHYPLL))
2841 brcms_err(core, "%s: turn on PHY PLL failed\n",
2842 __func__);
2843 }
2844 } else {
2845
2846
2847
2848
2849
2850 bcma_mask32(core, D11REGOFFS(clk_ctl_st),
2851 ~CCS_ERSRC_REQ_PHYPLL);
2852 (void)bcma_read32(core, D11REGOFFS(clk_ctl_st));
2853 }
2854}
2855
2856static void brcms_c_coredisable(struct brcms_hardware *wlc_hw)
2857{
2858 bool dev_gone;
2859
2860 brcms_dbg_info(wlc_hw->d11core, "wl%d: disable core\n", wlc_hw->unit);
2861
2862 dev_gone = brcms_deviceremoved(wlc_hw->wlc);
2863
2864 if (dev_gone)
2865 return;
2866
2867 if (wlc_hw->noreset)
2868 return;
2869
2870
2871 wlc_phy_switch_radio(wlc_hw->band->pi, OFF);
2872
2873
2874 wlc_phy_anacore(wlc_hw->band->pi, OFF);
2875
2876
2877 brcms_b_core_phypll_ctl(wlc_hw, false);
2878
2879 wlc_hw->clk = false;
2880 bcma_core_disable(wlc_hw->d11core, 0);
2881 wlc_phy_hw_clk_state_upd(wlc_hw->band->pi, false);
2882}
2883
2884static void brcms_c_flushqueues(struct brcms_c_info *wlc)
2885{
2886 struct brcms_hardware *wlc_hw = wlc->hw;
2887 uint i;
2888
2889
2890 for (i = 0; i < NFIFO; i++) {
2891 if (wlc_hw->di[i]) {
2892 dma_txreclaim(wlc_hw->di[i], DMA_RANGE_ALL);
2893 if (i < TX_BCMC_FIFO)
2894 ieee80211_wake_queue(wlc->pub->ieee_hw,
2895 brcms_fifo_to_ac(i));
2896 }
2897 }
2898
2899
2900 dma_rxreclaim(wlc_hw->di[RX_FIFO]);
2901}
2902
2903static u16
2904brcms_b_read_objmem(struct brcms_hardware *wlc_hw, uint offset, u32 sel)
2905{
2906 struct bcma_device *core = wlc_hw->d11core;
2907 u16 objoff = D11REGOFFS(objdata);
2908
2909 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2910 (void)bcma_read32(core, D11REGOFFS(objaddr));
2911 if (offset & 2)
2912 objoff += 2;
2913
2914 return bcma_read16(core, objoff);
2915}
2916
2917static void
2918brcms_b_write_objmem(struct brcms_hardware *wlc_hw, uint offset, u16 v,
2919 u32 sel)
2920{
2921 struct bcma_device *core = wlc_hw->d11core;
2922 u16 objoff = D11REGOFFS(objdata);
2923
2924 bcma_write32(core, D11REGOFFS(objaddr), sel | (offset >> 2));
2925 (void)bcma_read32(core, D11REGOFFS(objaddr));
2926 if (offset & 2)
2927 objoff += 2;
2928
2929 bcma_wflush16(core, objoff, v);
2930}
2931
2932
2933
2934
2935
2936u16 brcms_b_read_shm(struct brcms_hardware *wlc_hw, uint offset)
2937{
2938 return brcms_b_read_objmem(wlc_hw, offset, OBJADDR_SHM_SEL);
2939}
2940
2941
2942
2943
2944
2945void brcms_b_write_shm(struct brcms_hardware *wlc_hw, uint offset, u16 v)
2946{
2947 brcms_b_write_objmem(wlc_hw, offset, v, OBJADDR_SHM_SEL);
2948}
2949
2950
2951
2952
2953
2954
2955
2956void
2957brcms_b_copyto_objmem(struct brcms_hardware *wlc_hw, uint offset,
2958 const void *buf, int len, u32 sel)
2959{
2960 u16 v;
2961 const u8 *p = (const u8 *)buf;
2962 int i;
2963
2964 if (len <= 0 || (offset & 1) || (len & 1))
2965 return;
2966
2967 for (i = 0; i < len; i += 2) {
2968 v = p[i] | (p[i + 1] << 8);
2969 brcms_b_write_objmem(wlc_hw, offset + i, v, sel);
2970 }
2971}
2972
2973
2974
2975
2976
2977
2978
2979void
2980brcms_b_copyfrom_objmem(struct brcms_hardware *wlc_hw, uint offset, void *buf,
2981 int len, u32 sel)
2982{
2983 u16 v;
2984 u8 *p = (u8 *) buf;
2985 int i;
2986
2987 if (len <= 0 || (offset & 1) || (len & 1))
2988 return;
2989
2990 for (i = 0; i < len; i += 2) {
2991 v = brcms_b_read_objmem(wlc_hw, offset + i, sel);
2992 p[i] = v & 0xFF;
2993 p[i + 1] = (v >> 8) & 0xFF;
2994 }
2995}
2996
2997
2998
2999
3000
3001static void brcms_c_copyto_shm(struct brcms_c_info *wlc, uint offset,
3002 const void *buf, int len)
3003{
3004 brcms_b_copyto_objmem(wlc->hw, offset, buf, len, OBJADDR_SHM_SEL);
3005}
3006
3007static void brcms_b_retrylimit_upd(struct brcms_hardware *wlc_hw,
3008 u16 SRL, u16 LRL)
3009{
3010 wlc_hw->SRL = SRL;
3011 wlc_hw->LRL = LRL;
3012
3013
3014 if (wlc_hw->up) {
3015 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3016 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3017 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3018 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->SRL);
3019 bcma_write32(wlc_hw->d11core, D11REGOFFS(objaddr),
3020 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3021 (void)bcma_read32(wlc_hw->d11core, D11REGOFFS(objaddr));
3022 bcma_write32(wlc_hw->d11core, D11REGOFFS(objdata), wlc_hw->LRL);
3023 }
3024}
3025
3026static void brcms_b_pllreq(struct brcms_hardware *wlc_hw, bool set, u32 req_bit)
3027{
3028 if (set) {
3029 if (mboolisset(wlc_hw->pllreq, req_bit))
3030 return;
3031
3032 mboolset(wlc_hw->pllreq, req_bit);
3033
3034 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3035 if (!wlc_hw->sbclk)
3036 brcms_b_xtal(wlc_hw, ON);
3037 }
3038 } else {
3039 if (!mboolisset(wlc_hw->pllreq, req_bit))
3040 return;
3041
3042 mboolclr(wlc_hw->pllreq, req_bit);
3043
3044 if (mboolisset(wlc_hw->pllreq, BRCMS_PLLREQ_FLIP)) {
3045 if (wlc_hw->sbclk)
3046 brcms_b_xtal(wlc_hw, OFF);
3047 }
3048 }
3049}
3050
3051static void brcms_b_antsel_set(struct brcms_hardware *wlc_hw, u32 antsel_avail)
3052{
3053 wlc_hw->antsel_avail = antsel_avail;
3054}
3055
3056
3057
3058
3059
3060static bool brcms_c_ps_allowed(struct brcms_c_info *wlc)
3061{
3062
3063 return false;
3064}
3065
3066static void brcms_c_statsupd(struct brcms_c_info *wlc)
3067{
3068 int i;
3069 struct macstat *macstats;
3070#ifdef DEBUG
3071 u16 delta;
3072 u16 rxf0ovfl;
3073 u16 txfunfl[NFIFO];
3074#endif
3075
3076
3077 if (!wlc->pub->up)
3078 return;
3079
3080 macstats = wlc->core->macstat_snapshot;
3081
3082#ifdef DEBUG
3083
3084 rxf0ovfl = macstats->rxf0ovfl;
3085
3086
3087 for (i = 0; i < NFIFO; i++)
3088 txfunfl[i] = macstats->txfunfl[i];
3089#endif
3090
3091
3092 brcms_b_copyfrom_objmem(wlc->hw, M_UCODE_MACSTAT, macstats,
3093 sizeof(*macstats), OBJADDR_SHM_SEL);
3094
3095#ifdef DEBUG
3096
3097 delta = (u16)(macstats->rxf0ovfl - rxf0ovfl);
3098 if (delta)
3099 brcms_err(wlc->hw->d11core, "wl%d: %u rx fifo 0 overflows!\n",
3100 wlc->pub->unit, delta);
3101
3102
3103 for (i = 0; i < NFIFO; i++) {
3104 delta = macstats->txfunfl[i] - txfunfl[i];
3105 if (delta)
3106 brcms_err(wlc->hw->d11core,
3107 "wl%d: %u tx fifo %d underflows!\n",
3108 wlc->pub->unit, delta, i);
3109 }
3110#endif
3111
3112
3113 for (i = 0; i < NFIFO; i++) {
3114 if (wlc->hw->di[i])
3115 dma_counterreset(wlc->hw->di[i]);
3116 }
3117}
3118
3119static void brcms_b_reset(struct brcms_hardware *wlc_hw)
3120{
3121
3122 if (!brcms_deviceremoved(wlc_hw->wlc))
3123 brcms_b_corereset(wlc_hw, BRCMS_USE_COREFLAGS);
3124
3125
3126 brcms_c_flushqueues(wlc_hw->wlc);
3127}
3128
3129void brcms_c_reset(struct brcms_c_info *wlc)
3130{
3131 brcms_dbg_info(wlc->hw->d11core, "wl%d\n", wlc->pub->unit);
3132
3133
3134 brcms_c_statsupd(wlc);
3135
3136
3137 memset(wlc->core->macstat_snapshot, 0, sizeof(struct macstat));
3138
3139 brcms_b_reset(wlc->hw);
3140}
3141
3142void brcms_c_init_scb(struct scb *scb)
3143{
3144 int i;
3145
3146 memset(scb, 0, sizeof(struct scb));
3147 scb->flags = SCB_WMECAP | SCB_HTCAP;
3148 for (i = 0; i < NUMPRIO; i++) {
3149 scb->seqnum[i] = 0;
3150 scb->seqctl[i] = 0xFFFF;
3151 }
3152
3153 scb->seqctl_nonqos = 0xFFFF;
3154 scb->magic = SCB_MAGIC;
3155}
3156
3157
3158
3159
3160
3161
3162
3163
3164
3165static void brcms_b_coreinit(struct brcms_c_info *wlc)
3166{
3167 struct brcms_hardware *wlc_hw = wlc->hw;
3168 struct bcma_device *core = wlc_hw->d11core;
3169 u32 bcnint_us;
3170 uint i = 0;
3171 bool fifosz_fixup = false;
3172 int err = 0;
3173 u16 buf[NFIFO];
3174 struct brcms_ucode *ucode = &wlc_hw->wlc->wl->ucode;
3175
3176 brcms_dbg_info(core, "wl%d: core init\n", wlc_hw->unit);
3177
3178
3179 brcms_b_mctrl(wlc_hw, ~0, (MCTL_IHR_EN | MCTL_PSM_JMP_0 | MCTL_WAKE));
3180
3181 brcms_ucode_download(wlc_hw);
3182
3183
3184
3185 fifosz_fixup = true;
3186
3187
3188 bcma_write32(core, D11REGOFFS(macintstatus), -1);
3189 brcms_b_mctrl(wlc_hw, ~0,
3190 (MCTL_IHR_EN | MCTL_INFRA | MCTL_PSM_RUN | MCTL_WAKE));
3191
3192
3193 SPINWAIT(((bcma_read32(core, D11REGOFFS(macintstatus)) &
3194 MI_MACSSPNDD) == 0), 1000 * 1000);
3195 if ((bcma_read32(core, D11REGOFFS(macintstatus)) & MI_MACSSPNDD) == 0)
3196 brcms_err(core, "wl%d: wlc_coreinit: ucode did not self-"
3197 "suspend!\n", wlc_hw->unit);
3198
3199 brcms_c_gpio_init(wlc);
3200
3201 bcma_aread32(core, BCMA_IOST);
3202
3203 if (D11REV_IS(wlc_hw->corerev, 17) || D11REV_IS(wlc_hw->corerev, 23)) {
3204 if (BRCMS_ISNPHY(wlc_hw->band))
3205 brcms_c_write_inits(wlc_hw, ucode->d11n0initvals16);
3206 else
3207 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3208 " %d\n", __func__, wlc_hw->unit,
3209 wlc_hw->corerev);
3210 } else if (D11REV_IS(wlc_hw->corerev, 24)) {
3211 if (BRCMS_ISLCNPHY(wlc_hw->band))
3212 brcms_c_write_inits(wlc_hw, ucode->d11lcn0initvals24);
3213 else
3214 brcms_err(core, "%s: wl%d: unsupported phy in corerev"
3215 " %d\n", __func__, wlc_hw->unit,
3216 wlc_hw->corerev);
3217 } else {
3218 brcms_err(core, "%s: wl%d: unsupported corerev %d\n",
3219 __func__, wlc_hw->unit, wlc_hw->corerev);
3220 }
3221
3222
3223 if (fifosz_fixup)
3224 brcms_b_corerev_fifofixup(wlc_hw);
3225
3226
3227 buf[TX_AC_BE_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE0);
3228 if (buf[TX_AC_BE_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BE_FIFO]) {
3229 i = TX_AC_BE_FIFO;
3230 err = -1;
3231 }
3232 buf[TX_AC_VI_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE1);
3233 if (buf[TX_AC_VI_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VI_FIFO]) {
3234 i = TX_AC_VI_FIFO;
3235 err = -1;
3236 }
3237 buf[TX_AC_BK_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE2);
3238 buf[TX_AC_VO_FIFO] = (buf[TX_AC_BK_FIFO] >> 8) & 0xff;
3239 buf[TX_AC_BK_FIFO] &= 0xff;
3240 if (buf[TX_AC_BK_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_BK_FIFO]) {
3241 i = TX_AC_BK_FIFO;
3242 err = -1;
3243 }
3244 if (buf[TX_AC_VO_FIFO] != wlc_hw->xmtfifo_sz[TX_AC_VO_FIFO]) {
3245 i = TX_AC_VO_FIFO;
3246 err = -1;
3247 }
3248 buf[TX_BCMC_FIFO] = brcms_b_read_shm(wlc_hw, M_FIFOSIZE3);
3249 buf[TX_ATIM_FIFO] = (buf[TX_BCMC_FIFO] >> 8) & 0xff;
3250 buf[TX_BCMC_FIFO] &= 0xff;
3251 if (buf[TX_BCMC_FIFO] != wlc_hw->xmtfifo_sz[TX_BCMC_FIFO]) {
3252 i = TX_BCMC_FIFO;
3253 err = -1;
3254 }
3255 if (buf[TX_ATIM_FIFO] != wlc_hw->xmtfifo_sz[TX_ATIM_FIFO]) {
3256 i = TX_ATIM_FIFO;
3257 err = -1;
3258 }
3259 if (err != 0)
3260 brcms_err(core, "wlc_coreinit: txfifo mismatch: ucode size %d"
3261 " driver size %d index %d\n", buf[i],
3262 wlc_hw->xmtfifo_sz[i], i);
3263
3264
3265 WARN_ON(bcma_read32(core, D11REGOFFS(maccontrol)) == 0xffffffff);
3266
3267
3268
3269
3270 brcms_b_write_shm(wlc_hw, M_MBURST_SIZE, MAXTXFRAMEBURST);
3271 brcms_b_write_shm(wlc_hw, M_MAX_ANTCNT, ANTCNT);
3272
3273
3274 bcma_write32(core, D11REGOFFS(intrcvlazy[0]), (1 << IRL_FC_SHIFT));
3275
3276
3277 brcms_b_mctrl(wlc_hw,
3278 (MCTL_INFRA | MCTL_DISCARD_PMQ | MCTL_AP),
3279 (MCTL_INFRA | MCTL_DISCARD_PMQ));
3280
3281
3282 bcnint_us = 0x8000 << 10;
3283 bcma_write32(core, D11REGOFFS(tsf_cfprep),
3284 (bcnint_us << CFPREP_CBI_SHIFT));
3285 bcma_write32(core, D11REGOFFS(tsf_cfpstart), bcnint_us);
3286 bcma_write32(core, D11REGOFFS(macintstatus), MI_GP1);
3287
3288
3289 bcma_write32(core, D11REGOFFS(intctrlregs[RX_FIFO].intmask),
3290 DEF_RXINTMASK);
3291
3292
3293 brcms_b_macphyclk_set(wlc_hw, ON);
3294
3295
3296 wlc->fastpwrup_dly = ai_clkctl_fast_pwrup_delay(wlc_hw->sih);
3297 bcma_write16(core, D11REGOFFS(scc_fastpwrup_dly), wlc->fastpwrup_dly);
3298
3299
3300 brcms_b_write_shm(wlc_hw, M_MACHW_VER, (u16) wlc_hw->corerev);
3301
3302
3303 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_L,
3304 (u16) (wlc_hw->machwcap & 0xffff));
3305 brcms_b_write_shm(wlc_hw, M_MACHW_CAP_H,
3306 (u16) ((wlc_hw->
3307 machwcap >> 16) & 0xffff));
3308
3309
3310 bcma_write32(core, D11REGOFFS(objaddr),
3311 OBJADDR_SCR_SEL | S_DOT11_SRC_LMT);
3312 (void)bcma_read32(core, D11REGOFFS(objaddr));
3313 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->SRL);
3314 bcma_write32(core, D11REGOFFS(objaddr),
3315 OBJADDR_SCR_SEL | S_DOT11_LRC_LMT);
3316 (void)bcma_read32(core, D11REGOFFS(objaddr));
3317 bcma_write32(core, D11REGOFFS(objdata), wlc_hw->LRL);
3318
3319
3320 brcms_b_write_shm(wlc_hw, M_SFRMTXCNTFBRTHSD, wlc_hw->SFBL);
3321 brcms_b_write_shm(wlc_hw, M_LFRMTXCNTFBRTHSD, wlc_hw->LFBL);
3322
3323 bcma_mask16(core, D11REGOFFS(ifs_ctl), 0x0FFF);
3324 bcma_write16(core, D11REGOFFS(ifs_aifsn), EDCF_AIFSN_MIN);
3325
3326
3327 for (i = 0; i < NFIFO; i++) {
3328 if (wlc_hw->di[i])
3329 dma_txinit(wlc_hw->di[i]);
3330 }
3331
3332
3333 dma_rxinit(wlc_hw->di[RX_FIFO]);
3334 dma_rxfill(wlc_hw->di[RX_FIFO]);
3335}
3336
3337static void brcms_b_init(struct brcms_hardware *wlc_hw, u16 chanspec)
3338{
3339 u32 macintmask;
3340 bool fastclk;
3341 struct brcms_c_info *wlc = wlc_hw->wlc;
3342
3343
3344 fastclk = wlc_hw->forcefastclk;
3345 if (!fastclk)
3346 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_FAST);
3347
3348
3349 macintmask = brcms_intrsoff(wlc->wl);
3350
3351
3352 brcms_c_setxband(wlc_hw, chspec_bandunit(chanspec));
3353 wlc_phy_chanspec_radio_set(wlc_hw->band->pi, chanspec);
3354
3355
3356 wlc_phy_cal_init(wlc_hw->band->pi);
3357
3358
3359 brcms_b_coreinit(wlc);
3360
3361
3362 brcms_b_bsinit(wlc, chanspec);
3363
3364
3365 brcms_intrsrestore(wlc->wl, macintmask);
3366
3367
3368
3369
3370 mboolset(wlc_hw->wake_override, BRCMS_WAKE_OVERRIDE_MACSUSPEND);
3371
3372
3373
3374
3375
3376 wlc_hw->mac_suspend_depth = 1;
3377
3378
3379 if (!fastclk)
3380 brcms_b_clkctl_clk(wlc_hw, BCMA_CLKMODE_DYNAMIC);
3381}
3382
3383static void brcms_c_set_phy_chanspec(struct brcms_c_info *wlc,
3384 u16 chanspec)
3385{
3386
3387 wlc->chanspec = chanspec;
3388
3389
3390 brcms_c_channel_set_chanspec(wlc->cmi, chanspec, BRCMS_TXPWR_MAX);
3391
3392 if (wlc->stf->ss_algosel_auto)
3393 brcms_c_stf_ss_algo_channel_get(wlc, &wlc->stf->ss_algo_channel,
3394 chanspec);
3395
3396 brcms_c_stf_ss_update(wlc, wlc->band);
3397}
3398
3399static void
3400brcms_default_rateset(struct brcms_c_info *wlc, struct brcms_c_rateset *rs)
3401{
3402 brcms_c_rateset_default(rs, NULL, wlc->band->phytype,
3403 wlc->band->bandtype, false, BRCMS_RATE_MASK_FULL,
3404 (bool) (wlc->pub->_n_enab & SUPPORT_11N),
3405 brcms_chspec_bw(wlc->default_bss->chanspec),
3406 wlc->stf->txstreams);
3407}
3408
3409
3410static void brcms_c_rate_lookup_init(struct brcms_c_info *wlc,
3411 struct brcms_c_rateset *rateset)
3412{
3413 u8 rate;
3414 u8 mandatory;
3415 u8 cck_basic = 0;
3416 u8 ofdm_basic = 0;
3417 u8 *br = wlc->band->basic_rate;
3418 uint i;
3419
3420
3421 memset(br, 0, BRCM_MAXRATE + 1);
3422
3423
3424
3425
3426 for (i = 0; i < rateset->count; i++) {
3427
3428 if (!(rateset->rates[i] & BRCMS_RATE_FLAG))
3429 continue;
3430
3431
3432 rate = (rateset->rates[i] & BRCMS_RATE_MASK);
3433
3434 if (rate > BRCM_MAXRATE) {
3435 brcms_err(wlc->hw->d11core, "brcms_c_rate_lookup_init: "
3436 "invalid rate 0x%X in rate set\n",
3437 rateset->rates[i]);
3438 continue;
3439 }
3440
3441 br[rate] = rate;
3442 }
3443
3444
3445
3446
3447
3448
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458 for (i = 0; i < wlc->band->hw_rateset.count; i++) {
3459 rate = wlc->band->hw_rateset.rates[i];
3460
3461 if (br[rate] != 0) {
3462
3463
3464
3465
3466 if (is_ofdm_rate(rate))
3467 ofdm_basic = rate;
3468 else
3469 cck_basic = rate;
3470
3471 continue;
3472 }
3473
3474
3475
3476
3477
3478
3479 br[rate] = is_ofdm_rate(rate) ? ofdm_basic : cck_basic;
3480
3481 if (br[rate] != 0)
3482 continue;
3483
3484 if (is_ofdm_rate(rate)) {
3485
3486
3487
3488
3489 if (rate >= BRCM_RATE_24M)
3490 mandatory = BRCM_RATE_24M;
3491 else if (rate >= BRCM_RATE_12M)
3492 mandatory = BRCM_RATE_12M;
3493 else
3494 mandatory = BRCM_RATE_6M;
3495 } else {
3496
3497 mandatory = rate;
3498 }
3499
3500 br[rate] = mandatory;
3501 }
3502}
3503
3504static void brcms_c_bandinit_ordered(struct brcms_c_info *wlc,
3505 u16 chanspec)
3506{
3507 struct brcms_c_rateset default_rateset;
3508 uint parkband;
3509 uint i, band_order[2];
3510
3511
3512
3513
3514
3515 if (wlc->bandlocked || wlc->pub->_nbands == 1) {
3516
3517 parkband = wlc->band->bandunit;
3518 band_order[0] = band_order[1] = parkband;
3519 } else {
3520
3521 parkband = chspec_bandunit(chanspec);
3522
3523
3524 band_order[0] = parkband ^ 1;
3525 band_order[1] = parkband;
3526 }
3527
3528
3529 for (i = 0; i < wlc->pub->_nbands; i++) {
3530 uint j = band_order[i];
3531
3532 wlc->band = wlc->bandstate[j];
3533
3534 brcms_default_rateset(wlc, &default_rateset);
3535
3536
3537 brcms_c_rateset_filter(&default_rateset, &wlc->band->hw_rateset,
3538 false, BRCMS_RATES_CCK_OFDM, BRCMS_RATE_MASK,
3539 (bool) (wlc->pub->_n_enab & SUPPORT_11N));
3540
3541
3542 brcms_c_rate_lookup_init(wlc, &default_rateset);
3543 }
3544
3545
3546 brcms_c_set_phy_chanspec(wlc, chanspec);
3547}
3548
3549
3550
3551
3552
3553void brcms_c_mac_promisc(struct brcms_c_info *wlc, uint filter_flags)
3554{
3555 u32 promisc_bits = 0;
3556
3557 wlc->filter_flags = filter_flags;
3558
3559 if (filter_flags & FIF_OTHER_BSS)
3560 promisc_bits |= MCTL_PROMISC;
3561
3562 if (filter_flags & FIF_BCN_PRBRESP_PROMISC)
3563 promisc_bits |= MCTL_BCNS_PROMISC;
3564
3565 if (filter_flags & FIF_FCSFAIL)
3566 promisc_bits |= MCTL_KEEPBADFCS;
3567
3568 if (filter_flags & (FIF_CONTROL | FIF_PSPOLL))
3569 promisc_bits |= MCTL_KEEPCONTROL;
3570
3571 brcms_b_mctrl(wlc->hw,
3572 MCTL_PROMISC | MCTL_BCNS_PROMISC |
3573 MCTL_KEEPCONTROL | MCTL_KEEPBADFCS,
3574 promisc_bits);
3575}
3576
3577
3578
3579
3580
3581static void brcms_c_ucode_mac_upd(struct brcms_c_info *wlc)
3582{
3583
3584
3585
3586 if (wlc->home_chanspec == wlc_phy_chanspec_get(wlc->band->pi)) {
3587 if (wlc->pub->associated) {
3588
3589
3590
3591
3592
3593
3594
3595
3596
3597 if (BRCMS_PHY_11N_CAP(wlc->band))
3598 brcms_b_write_shm(wlc->hw,
3599 M_BCN_TXTSF_OFFSET, 0);
3600 }
3601 } else {
3602
3603 }
3604}
3605
3606static void brcms_c_write_rate_shm(struct brcms_c_info *wlc, u8 rate,
3607 u8 basic_rate)
3608{
3609 u8 phy_rate, index;
3610 u8 basic_phy_rate, basic_index;
3611 u16 dir_table, basic_table;
3612 u16 basic_ptr;
3613
3614
3615 dir_table = is_ofdm_rate(basic_rate) ? M_RT_DIRMAP_A : M_RT_DIRMAP_B;
3616
3617
3618 basic_table = is_ofdm_rate(rate) ? M_RT_BBRSMAP_A : M_RT_BBRSMAP_B;
3619
3620
3621
3622
3623
3624 phy_rate = rate_info[rate] & BRCMS_RATE_MASK;
3625 basic_phy_rate = rate_info[basic_rate] & BRCMS_RATE_MASK;
3626 index = phy_rate & 0xf;
3627 basic_index = basic_phy_rate & 0xf;
3628
3629
3630
3631
3632 basic_ptr = brcms_b_read_shm(wlc->hw, (dir_table + basic_index * 2));
3633
3634
3635
3636
3637 brcms_b_write_shm(wlc->hw, (basic_table + index * 2), basic_ptr);
3638}
3639
3640static const struct brcms_c_rateset *
3641brcms_c_rateset_get_hwrs(struct brcms_c_info *wlc)
3642{
3643 const struct brcms_c_rateset *rs_dflt;
3644
3645 if (BRCMS_PHY_11N_CAP(wlc->band)) {
3646 if (wlc->band->bandtype == BRCM_BAND_5G)
3647 rs_dflt = &ofdm_mimo_rates;
3648 else
3649 rs_dflt = &cck_ofdm_mimo_rates;
3650 } else if (wlc->band->gmode)
3651 rs_dflt = &cck_ofdm_rates;
3652 else
3653 rs_dflt = &cck_rates;
3654
3655 return rs_dflt;
3656}
3657
3658static void brcms_c_set_ratetable(struct brcms_c_info *wlc)
3659{
3660 const struct brcms_c_rateset *rs_dflt;
3661 struct brcms_c_rateset rs;
3662 u8 rate, basic_rate;
3663 uint i;
3664
3665 rs_dflt = brcms_c_rateset_get_hwrs(wlc);
3666
3667 brcms_c_rateset_copy(rs_dflt, &rs);
3668 brcms_c_rateset_mcs_upd(&rs, wlc->stf->txstreams);
3669
3670
3671 for (i = 0; i < rs.count; i++) {
3672 rate = rs.rates[i] & BRCMS_RATE_MASK;
3673
3674
3675
3676
3677 basic_rate = brcms_basic_rate(wlc, rate);
3678 if (basic_rate == 0)
3679
3680
3681
3682 basic_rate = rs.rates[0] & BRCMS_RATE_MASK;
3683
3684 brcms_c_write_rate_shm(wlc, rate, basic_rate);
3685 }
3686}
3687
3688
3689static void brcms_c_bsinit(struct brcms_c_info *wlc)
3690{
3691 brcms_dbg_info(wlc->hw->d11core, "wl%d: bandunit %d\n",
3692 wlc->pub->unit, wlc->band->bandunit);
3693
3694
3695 brcms_c_set_ratetable(wlc);
3696
3697
3698 brcms_c_ucode_mac_upd(wlc);
3699
3700
3701 brcms_c_antsel_init(wlc->asi);
3702
3703}
3704
3705
3706static int
3707brcms_c_duty_cycle_set(struct brcms_c_info *wlc, int duty_cycle, bool isOFDM,
3708 bool writeToShm)
3709{
3710 int idle_busy_ratio_x_16 = 0;
3711 uint offset =
3712 isOFDM ? M_TX_IDLE_BUSY_RATIO_X_16_OFDM :
3713 M_TX_IDLE_BUSY_RATIO_X_16_CCK;
3714 if (duty_cycle > 100 || duty_cycle < 0) {
3715 brcms_err(wlc->hw->d11core,
3716 "wl%d: duty cycle value off limit\n",
3717 wlc->pub->unit);
3718 return -EINVAL;
3719 }
3720 if (duty_cycle)
3721 idle_busy_ratio_x_16 = (100 - duty_cycle) * 16 / duty_cycle;
3722
3723 if (writeToShm)
3724 brcms_b_write_shm(wlc->hw, offset, (u16) idle_busy_ratio_x_16);
3725
3726 if (isOFDM)
3727 wlc->tx_duty_cycle_ofdm = (u16) duty_cycle;
3728 else
3729 wlc->tx_duty_cycle_cck = (u16) duty_cycle;
3730
3731 return 0;
3732}
3733
3734
3735static void brcms_c_set_ps_ctrl(struct brcms_c_info *wlc)
3736{
3737 u32 v1, v2;
3738 bool hps;
3739 bool awake_before;
3740
3741 hps = brcms_c_ps_allowed(wlc);
3742
3743 brcms_dbg_mac80211(wlc->hw->d11core, "wl%d: hps %d\n", wlc->pub->unit,
3744 hps);
3745
3746 v1 = bcma_read32(wlc->hw->d11core, D11REGOFFS(maccontrol));
3747 v2 = MCTL_WAKE;
3748 if (hps)
3749 v2 |= MCTL_HPS;
3750
3751 brcms_b_mctrl(wlc->hw, MCTL_WAKE | MCTL_HPS, v2);
3752
3753 awake_before = ((v1 & MCTL_WAKE) || ((v1 & MCTL_HPS) == 0));
3754
3755 if (!awake_before)
3756 brcms_b_wait_for_wake(wlc->hw);
3757}
3758
3759
3760
3761
3762
3763static void brcms_c_set_mac(struct brcms_bss_cfg *bsscfg)
3764{
3765 struct brcms_c_info *wlc = bsscfg->wlc;
3766
3767
3768 brcms_c_set_addrmatch(wlc, RCM_MAC_OFFSET, wlc->pub->cur_etheraddr);
3769
3770 brcms_c_ampdu_macaddr_upd(wlc);
3771}
3772
3773
3774
3775
3776static void brcms_c_set_bssid(struct brcms_bss_cfg *bsscfg)
3777{
3778
3779 brcms_c_set_addrmatch(bsscfg->wlc, RCM_BSSID_OFFSET, bsscfg->BSSID);
3780}
3781
3782void brcms_c_set_ssid(struct brcms_c_info *wlc, u8 *ssid, size_t ssid_len)
3783{
3784 u8 len = min_t(u8, sizeof(wlc->bsscfg->SSID), ssid_len);
3785 memset(wlc->bsscfg->SSID, 0, sizeof(wlc->bsscfg->SSID));
3786
3787 memcpy(wlc->bsscfg->SSID, ssid, len);
3788 wlc->bsscfg->SSID_len = len;
3789}
3790
3791static void brcms_b_set_shortslot(struct brcms_hardware *wlc_hw, bool shortslot)
3792{
3793 wlc_hw->shortslot = shortslot;
3794
3795 if (wlc_hw->band->bandtype == BRCM_BAND_2G && wlc_hw->up) {
3796 brcms_c_suspend_mac_and_wait(wlc_hw->wlc);
3797 brcms_b_update_slot_timing(wlc_hw, shortslot);
3798 brcms_c_enable_mac(wlc_hw->wlc);
3799 }
3800}
3801
3802
3803
3804
3805
3806static void brcms_c_switch_shortslot(struct brcms_c_info *wlc, bool shortslot)
3807{
3808
3809 if (wlc->shortslot_override != BRCMS_SHORTSLOT_AUTO)
3810 shortslot = (wlc->shortslot_override == BRCMS_SHORTSLOT_ON);
3811
3812 if (wlc->shortslot == shortslot)
3813 return;
3814
3815 wlc->shortslot = shortslot;
3816
3817 brcms_b_set_shortslot(wlc->hw, shortslot);
3818}
3819
3820static void brcms_c_set_home_chanspec(struct brcms_c_info *wlc, u16 chanspec)
3821{
3822 if (wlc->home_chanspec != chanspec) {
3823 wlc->home_chanspec = chanspec;
3824
3825 if (wlc->pub->associated)
3826 wlc->bsscfg->current_bss->chanspec = chanspec;
3827 }
3828}
3829
3830void
3831brcms_b_set_chanspec(struct brcms_hardware *wlc_hw, u16 chanspec,
3832 bool mute_tx, struct txpwr_limits *txpwr)
3833{
3834 uint bandunit;