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17#ifndef _HAL_H_
18#define _HAL_H_
19
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32
33
34#define WCN36XX_HAL_VER_MAJOR 1
35#define WCN36XX_HAL_VER_MINOR 4
36#define WCN36XX_HAL_VER_VERSION 1
37#define WCN36XX_HAL_VER_REVISION 2
38
39
40#define WCN36XX_HAL_MAX_ENUM_SIZE 0x7FFFFFFF
41#define WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE 0x7FFF
42
43
44#define STACFG_MAX_TC 8
45
46
47#define WCN36XX_HAL_MAX_AC 4
48
49#define WCN36XX_HAL_IPV4_ADDR_LEN 4
50
51#define WCN36XX_HAL_STA_INVALID_IDX 0xFF
52#define WCN36XX_HAL_BSS_INVALID_IDX 0xFF
53
54
55#define BEACON_TEMPLATE_SIZE 0x180
56
57
58#define TIM_MIN_PVM_SIZE 6
59
60
61#define PARAM_BCN_INTERVAL_CHANGED (1 << 0)
62#define PARAM_SHORT_PREAMBLE_CHANGED (1 << 1)
63#define PARAM_SHORT_SLOT_TIME_CHANGED (1 << 2)
64#define PARAM_llACOEXIST_CHANGED (1 << 3)
65#define PARAM_llBCOEXIST_CHANGED (1 << 4)
66#define PARAM_llGCOEXIST_CHANGED (1 << 5)
67#define PARAM_HT20MHZCOEXIST_CHANGED (1<<6)
68#define PARAM_NON_GF_DEVICES_PRESENT_CHANGED (1<<7)
69#define PARAM_RIFS_MODE_CHANGED (1<<8)
70#define PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED (1<<9)
71#define PARAM_OBSS_MODE_CHANGED (1<<10)
72#define PARAM_BEACON_UPDATE_MASK \
73 (PARAM_BCN_INTERVAL_CHANGED | \
74 PARAM_SHORT_PREAMBLE_CHANGED | \
75 PARAM_SHORT_SLOT_TIME_CHANGED | \
76 PARAM_llACOEXIST_CHANGED | \
77 PARAM_llBCOEXIST_CHANGED | \
78 PARAM_llGCOEXIST_CHANGED | \
79 PARAM_HT20MHZCOEXIST_CHANGED | \
80 PARAM_NON_GF_DEVICES_PRESENT_CHANGED | \
81 PARAM_RIFS_MODE_CHANGED | \
82 PARAM_LSIG_TXOP_FULL_SUPPORT_CHANGED | \
83 PARAM_OBSS_MODE_CHANGED)
84
85
86#define DUMPCMD_RSP_BUFFER 100
87
88
89#define WCN36XX_HAL_VERSION_LENGTH 64
90
91
92#define WCN36XX_AMPDU_START_THRESH 20
93
94#define WCN36XX_MAX_SCAN_SSIDS 9
95#define WCN36XX_MAX_SCAN_IE_LEN 500
96
97
98enum wcn36xx_hal_host_msg_type {
99
100 WCN36XX_HAL_START_REQ = 0,
101 WCN36XX_HAL_START_RSP = 1,
102 WCN36XX_HAL_STOP_REQ = 2,
103 WCN36XX_HAL_STOP_RSP = 3,
104
105
106 WCN36XX_HAL_INIT_SCAN_REQ = 4,
107 WCN36XX_HAL_INIT_SCAN_RSP = 5,
108 WCN36XX_HAL_START_SCAN_REQ = 6,
109 WCN36XX_HAL_START_SCAN_RSP = 7,
110 WCN36XX_HAL_END_SCAN_REQ = 8,
111 WCN36XX_HAL_END_SCAN_RSP = 9,
112 WCN36XX_HAL_FINISH_SCAN_REQ = 10,
113 WCN36XX_HAL_FINISH_SCAN_RSP = 11,
114
115
116 WCN36XX_HAL_CONFIG_STA_REQ = 12,
117 WCN36XX_HAL_CONFIG_STA_RSP = 13,
118 WCN36XX_HAL_DELETE_STA_REQ = 14,
119 WCN36XX_HAL_DELETE_STA_RSP = 15,
120 WCN36XX_HAL_CONFIG_BSS_REQ = 16,
121 WCN36XX_HAL_CONFIG_BSS_RSP = 17,
122 WCN36XX_HAL_DELETE_BSS_REQ = 18,
123 WCN36XX_HAL_DELETE_BSS_RSP = 19,
124
125
126 WCN36XX_HAL_JOIN_REQ = 20,
127 WCN36XX_HAL_JOIN_RSP = 21,
128 WCN36XX_HAL_POST_ASSOC_REQ = 22,
129 WCN36XX_HAL_POST_ASSOC_RSP = 23,
130
131
132 WCN36XX_HAL_SET_BSSKEY_REQ = 24,
133 WCN36XX_HAL_SET_BSSKEY_RSP = 25,
134 WCN36XX_HAL_SET_STAKEY_REQ = 26,
135 WCN36XX_HAL_SET_STAKEY_RSP = 27,
136 WCN36XX_HAL_RMV_BSSKEY_REQ = 28,
137 WCN36XX_HAL_RMV_BSSKEY_RSP = 29,
138 WCN36XX_HAL_RMV_STAKEY_REQ = 30,
139 WCN36XX_HAL_RMV_STAKEY_RSP = 31,
140
141
142 WCN36XX_HAL_ADD_TS_REQ = 32,
143 WCN36XX_HAL_ADD_TS_RSP = 33,
144 WCN36XX_HAL_DEL_TS_REQ = 34,
145 WCN36XX_HAL_DEL_TS_RSP = 35,
146 WCN36XX_HAL_UPD_EDCA_PARAMS_REQ = 36,
147 WCN36XX_HAL_UPD_EDCA_PARAMS_RSP = 37,
148 WCN36XX_HAL_ADD_BA_REQ = 38,
149 WCN36XX_HAL_ADD_BA_RSP = 39,
150 WCN36XX_HAL_DEL_BA_REQ = 40,
151 WCN36XX_HAL_DEL_BA_RSP = 41,
152
153 WCN36XX_HAL_CH_SWITCH_REQ = 42,
154 WCN36XX_HAL_CH_SWITCH_RSP = 43,
155 WCN36XX_HAL_SET_LINK_ST_REQ = 44,
156 WCN36XX_HAL_SET_LINK_ST_RSP = 45,
157 WCN36XX_HAL_GET_STATS_REQ = 46,
158 WCN36XX_HAL_GET_STATS_RSP = 47,
159 WCN36XX_HAL_UPDATE_CFG_REQ = 48,
160 WCN36XX_HAL_UPDATE_CFG_RSP = 49,
161
162 WCN36XX_HAL_MISSED_BEACON_IND = 50,
163 WCN36XX_HAL_UNKNOWN_ADDR2_FRAME_RX_IND = 51,
164 WCN36XX_HAL_MIC_FAILURE_IND = 52,
165 WCN36XX_HAL_FATAL_ERROR_IND = 53,
166 WCN36XX_HAL_SET_KEYDONE_MSG = 54,
167
168
169 WCN36XX_HAL_DOWNLOAD_NV_REQ = 55,
170 WCN36XX_HAL_DOWNLOAD_NV_RSP = 56,
171
172 WCN36XX_HAL_ADD_BA_SESSION_REQ = 57,
173 WCN36XX_HAL_ADD_BA_SESSION_RSP = 58,
174 WCN36XX_HAL_TRIGGER_BA_REQ = 59,
175 WCN36XX_HAL_TRIGGER_BA_RSP = 60,
176 WCN36XX_HAL_UPDATE_BEACON_REQ = 61,
177 WCN36XX_HAL_UPDATE_BEACON_RSP = 62,
178 WCN36XX_HAL_SEND_BEACON_REQ = 63,
179 WCN36XX_HAL_SEND_BEACON_RSP = 64,
180
181 WCN36XX_HAL_SET_BCASTKEY_REQ = 65,
182 WCN36XX_HAL_SET_BCASTKEY_RSP = 66,
183 WCN36XX_HAL_DELETE_STA_CONTEXT_IND = 67,
184 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_REQ = 68,
185 WCN36XX_HAL_UPDATE_PROBE_RSP_TEMPLATE_RSP = 69,
186
187
188 WCN36XX_HAL_PROCESS_PTT_REQ = 70,
189 WCN36XX_HAL_PROCESS_PTT_RSP = 71,
190
191
192 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_REQ = 72,
193 WCN36XX_HAL_SIGNAL_BTAMP_EVENT_RSP = 73,
194 WCN36XX_HAL_TL_HAL_FLUSH_AC_REQ = 74,
195 WCN36XX_HAL_TL_HAL_FLUSH_AC_RSP = 75,
196
197 WCN36XX_HAL_ENTER_IMPS_REQ = 76,
198 WCN36XX_HAL_EXIT_IMPS_REQ = 77,
199 WCN36XX_HAL_ENTER_BMPS_REQ = 78,
200 WCN36XX_HAL_EXIT_BMPS_REQ = 79,
201 WCN36XX_HAL_ENTER_UAPSD_REQ = 80,
202 WCN36XX_HAL_EXIT_UAPSD_REQ = 81,
203 WCN36XX_HAL_UPDATE_UAPSD_PARAM_REQ = 82,
204 WCN36XX_HAL_CONFIGURE_RXP_FILTER_REQ = 83,
205 WCN36XX_HAL_ADD_BCN_FILTER_REQ = 84,
206 WCN36XX_HAL_REM_BCN_FILTER_REQ = 85,
207 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN = 86,
208 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN = 87,
209 WCN36XX_HAL_ENTER_WOWL_REQ = 88,
210 WCN36XX_HAL_EXIT_WOWL_REQ = 89,
211 WCN36XX_HAL_HOST_OFFLOAD_REQ = 90,
212 WCN36XX_HAL_SET_RSSI_THRESH_REQ = 91,
213 WCN36XX_HAL_GET_RSSI_REQ = 92,
214 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_REQ = 93,
215 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_REQ = 94,
216
217 WCN36XX_HAL_ENTER_IMPS_RSP = 95,
218 WCN36XX_HAL_EXIT_IMPS_RSP = 96,
219 WCN36XX_HAL_ENTER_BMPS_RSP = 97,
220 WCN36XX_HAL_EXIT_BMPS_RSP = 98,
221 WCN36XX_HAL_ENTER_UAPSD_RSP = 99,
222 WCN36XX_HAL_EXIT_UAPSD_RSP = 100,
223 WCN36XX_HAL_SET_UAPSD_AC_PARAMS_RSP = 101,
224 WCN36XX_HAL_UPDATE_UAPSD_PARAM_RSP = 102,
225 WCN36XX_HAL_CONFIGURE_RXP_FILTER_RSP = 103,
226 WCN36XX_HAL_ADD_BCN_FILTER_RSP = 104,
227 WCN36XX_HAL_REM_BCN_FILTER_RSP = 105,
228 WCN36XX_HAL_SET_RSSI_THRESH_RSP = 106,
229 WCN36XX_HAL_HOST_OFFLOAD_RSP = 107,
230 WCN36XX_HAL_ADD_WOWL_BCAST_PTRN_RSP = 108,
231 WCN36XX_HAL_DEL_WOWL_BCAST_PTRN_RSP = 109,
232 WCN36XX_HAL_ENTER_WOWL_RSP = 110,
233 WCN36XX_HAL_EXIT_WOWL_RSP = 111,
234 WCN36XX_HAL_RSSI_NOTIFICATION_IND = 112,
235 WCN36XX_HAL_GET_RSSI_RSP = 113,
236 WCN36XX_HAL_CONFIGURE_APPS_CPU_WAKEUP_STATE_RSP = 114,
237
238
239 WCN36XX_HAL_SET_MAX_TX_POWER_REQ = 115,
240 WCN36XX_HAL_SET_MAX_TX_POWER_RSP = 116,
241
242
243 WCN36XX_HAL_AGGR_ADD_TS_REQ = 117,
244 WCN36XX_HAL_AGGR_ADD_TS_RSP = 118,
245
246
247 WCN36XX_HAL_SET_P2P_GONOA_REQ = 119,
248 WCN36XX_HAL_SET_P2P_GONOA_RSP = 120,
249
250
251 WCN36XX_HAL_DUMP_COMMAND_REQ = 121,
252 WCN36XX_HAL_DUMP_COMMAND_RSP = 122,
253
254
255 WCN36XX_HAL_START_OEM_DATA_REQ = 123,
256 WCN36XX_HAL_START_OEM_DATA_RSP = 124,
257
258
259 WCN36XX_HAL_ADD_STA_SELF_REQ = 125,
260 WCN36XX_HAL_ADD_STA_SELF_RSP = 126,
261
262
263 WCN36XX_HAL_DEL_STA_SELF_REQ = 127,
264 WCN36XX_HAL_DEL_STA_SELF_RSP = 128,
265
266
267 WCN36XX_HAL_COEX_IND = 129,
268
269
270 WCN36XX_HAL_OTA_TX_COMPL_IND = 130,
271
272
273 WCN36XX_HAL_HOST_SUSPEND_IND = 131,
274 WCN36XX_HAL_HOST_RESUME_REQ = 132,
275 WCN36XX_HAL_HOST_RESUME_RSP = 133,
276
277 WCN36XX_HAL_SET_TX_POWER_REQ = 134,
278 WCN36XX_HAL_SET_TX_POWER_RSP = 135,
279 WCN36XX_HAL_GET_TX_POWER_REQ = 136,
280 WCN36XX_HAL_GET_TX_POWER_RSP = 137,
281
282 WCN36XX_HAL_P2P_NOA_ATTR_IND = 138,
283
284 WCN36XX_HAL_ENABLE_RADAR_DETECT_REQ = 139,
285 WCN36XX_HAL_ENABLE_RADAR_DETECT_RSP = 140,
286 WCN36XX_HAL_GET_TPC_REPORT_REQ = 141,
287 WCN36XX_HAL_GET_TPC_REPORT_RSP = 142,
288 WCN36XX_HAL_RADAR_DETECT_IND = 143,
289 WCN36XX_HAL_RADAR_DETECT_INTR_IND = 144,
290 WCN36XX_HAL_KEEP_ALIVE_REQ = 145,
291 WCN36XX_HAL_KEEP_ALIVE_RSP = 146,
292
293
294 WCN36XX_HAL_SET_PREF_NETWORK_REQ = 147,
295 WCN36XX_HAL_SET_PREF_NETWORK_RSP = 148,
296 WCN36XX_HAL_SET_RSSI_FILTER_REQ = 149,
297 WCN36XX_HAL_SET_RSSI_FILTER_RSP = 150,
298 WCN36XX_HAL_UPDATE_SCAN_PARAM_REQ = 151,
299 WCN36XX_HAL_UPDATE_SCAN_PARAM_RSP = 152,
300 WCN36XX_HAL_PREF_NETW_FOUND_IND = 153,
301
302 WCN36XX_HAL_SET_TX_PER_TRACKING_REQ = 154,
303 WCN36XX_HAL_SET_TX_PER_TRACKING_RSP = 155,
304 WCN36XX_HAL_TX_PER_HIT_IND = 156,
305
306 WCN36XX_HAL_8023_MULTICAST_LIST_REQ = 157,
307 WCN36XX_HAL_8023_MULTICAST_LIST_RSP = 158,
308
309 WCN36XX_HAL_SET_PACKET_FILTER_REQ = 159,
310 WCN36XX_HAL_SET_PACKET_FILTER_RSP = 160,
311 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_REQ = 161,
312 WCN36XX_HAL_PACKET_FILTER_MATCH_COUNT_RSP = 162,
313 WCN36XX_HAL_CLEAR_PACKET_FILTER_REQ = 163,
314 WCN36XX_HAL_CLEAR_PACKET_FILTER_RSP = 164,
315
316
317
318
319
320 WCN36XX_HAL_INIT_SCAN_CON_REQ = 165,
321
322 WCN36XX_HAL_SET_POWER_PARAMS_REQ = 166,
323 WCN36XX_HAL_SET_POWER_PARAMS_RSP = 167,
324
325 WCN36XX_HAL_TSM_STATS_REQ = 168,
326 WCN36XX_HAL_TSM_STATS_RSP = 169,
327
328
329 WCN36XX_HAL_WAKE_REASON_IND = 170,
330
331
332 WCN36XX_HAL_GTK_OFFLOAD_REQ = 171,
333 WCN36XX_HAL_GTK_OFFLOAD_RSP = 172,
334 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_REQ = 173,
335 WCN36XX_HAL_GTK_OFFLOAD_GETINFO_RSP = 174,
336
337 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_REQ = 175,
338 WCN36XX_HAL_FEATURE_CAPS_EXCHANGE_RSP = 176,
339 WCN36XX_HAL_EXCLUDE_UNENCRYPTED_IND = 177,
340
341 WCN36XX_HAL_SET_THERMAL_MITIGATION_REQ = 178,
342 WCN36XX_HAL_SET_THERMAL_MITIGATION_RSP = 179,
343
344 WCN36XX_HAL_UPDATE_VHT_OP_MODE_REQ = 182,
345 WCN36XX_HAL_UPDATE_VHT_OP_MODE_RSP = 183,
346
347 WCN36XX_HAL_P2P_NOA_START_IND = 184,
348
349 WCN36XX_HAL_GET_ROAM_RSSI_REQ = 185,
350 WCN36XX_HAL_GET_ROAM_RSSI_RSP = 186,
351
352 WCN36XX_HAL_CLASS_B_STATS_IND = 187,
353 WCN36XX_HAL_DEL_BA_IND = 188,
354 WCN36XX_HAL_DHCP_START_IND = 189,
355 WCN36XX_HAL_DHCP_STOP_IND = 190,
356
357
358 WCN36XX_HAL_START_SCAN_OFFLOAD_REQ = 204,
359 WCN36XX_HAL_START_SCAN_OFFLOAD_RSP = 205,
360 WCN36XX_HAL_STOP_SCAN_OFFLOAD_REQ = 206,
361 WCN36XX_HAL_STOP_SCAN_OFFLOAD_RSP = 207,
362 WCN36XX_HAL_SCAN_OFFLOAD_IND = 210,
363
364 WCN36XX_HAL_AVOID_FREQ_RANGE_IND = 233,
365
366 WCN36XX_HAL_PRINT_REG_INFO_IND = 259,
367
368 WCN36XX_HAL_MSG_MAX = WCN36XX_HAL_MSG_TYPE_MAX_ENUM_SIZE
369};
370
371
372enum wcn36xx_hal_host_msg_version {
373 WCN36XX_HAL_MSG_VERSION0 = 0,
374 WCN36XX_HAL_MSG_VERSION1 = 1,
375
376 WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION = 0x7FFF,
377 WCN36XX_HAL_MSG_VERSION_MAX_FIELD = WCN36XX_HAL_MSG_WCNSS_CTRL_VERSION
378};
379
380enum driver_type {
381 DRIVER_TYPE_PRODUCTION = 0,
382 DRIVER_TYPE_MFG = 1,
383 DRIVER_TYPE_DVT = 2,
384 DRIVER_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
385};
386
387enum wcn36xx_hal_stop_type {
388 HAL_STOP_TYPE_SYS_RESET,
389 HAL_STOP_TYPE_SYS_DEEP_SLEEP,
390 HAL_STOP_TYPE_RF_KILL,
391 HAL_STOP_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
392};
393
394enum wcn36xx_hal_sys_mode {
395 HAL_SYS_MODE_NORMAL,
396 HAL_SYS_MODE_LEARN,
397 HAL_SYS_MODE_SCAN,
398 HAL_SYS_MODE_PROMISC,
399 HAL_SYS_MODE_SUSPEND_LINK,
400 HAL_SYS_MODE_ROAM_SCAN,
401 HAL_SYS_MODE_ROAM_SUSPEND_LINK,
402 HAL_SYS_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
403};
404
405enum phy_chan_bond_state {
406
407 PHY_SINGLE_CHANNEL_CENTERED = 0,
408
409
410 PHY_DOUBLE_CHANNEL_LOW_PRIMARY = 1,
411
412
413 PHY_DOUBLE_CHANNEL_CENTERED = 2,
414
415
416 PHY_DOUBLE_CHANNEL_HIGH_PRIMARY = 3,
417
418
419 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_CENTERED = 4,
420
421
422 PHY_QUADRUPLE_CHANNEL_20MHZ_CENTERED_40MHZ_CENTERED = 5,
423
424
425 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_CENTERED = 6,
426
427
428 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_LOW = 7,
429
430
431 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_LOW = 8,
432
433
434 PHY_QUADRUPLE_CHANNEL_20MHZ_LOW_40MHZ_HIGH = 9,
435
436
437 PHY_QUADRUPLE_CHANNEL_20MHZ_HIGH_40MHZ_HIGH = 10,
438
439 PHY_CHANNEL_BONDING_STATE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
440};
441
442
443enum wcn36xx_hal_ht_mimo_state {
444
445 WCN36XX_HAL_HT_MIMO_PS_STATIC = 0,
446
447
448 WCN36XX_HAL_HT_MIMO_PS_DYNAMIC = 1,
449
450
451 WCN36XX_HAL_HT_MIMO_PS_NA = 2,
452
453
454 WCN36XX_HAL_HT_MIMO_PS_NO_LIMIT = 3,
455
456 WCN36XX_HAL_HT_MIMO_PS_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
457};
458
459
460enum sta_rate_mode {
461 STA_TAURUS = 0,
462 STA_TITAN,
463 STA_POLARIS,
464 STA_11b,
465 STA_11bg,
466 STA_11a,
467 STA_11n,
468 STA_11ac,
469 STA_INVALID_RATE_MODE = WCN36XX_HAL_MAX_ENUM_SIZE
470};
471
472
473#define WCN36XX_HAL_NUM_DSSS_RATES 4
474
475
476#define WCN36XX_HAL_NUM_OFDM_RATES 8
477
478
479#define WCN36XX_HAL_NUM_POLARIS_RATES 3
480
481#define WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET 16
482
483enum wcn36xx_hal_bss_type {
484 WCN36XX_HAL_INFRASTRUCTURE_MODE,
485
486
487 WCN36XX_HAL_INFRA_AP_MODE,
488
489 WCN36XX_HAL_IBSS_MODE,
490
491
492 WCN36XX_HAL_BTAMP_STA_MODE,
493
494
495 WCN36XX_HAL_BTAMP_AP_MODE,
496
497 WCN36XX_HAL_AUTO_MODE,
498
499 WCN36XX_HAL_DONOT_USE_BSS_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
500};
501
502enum wcn36xx_hal_nw_type {
503 WCN36XX_HAL_11A_NW_TYPE,
504 WCN36XX_HAL_11B_NW_TYPE,
505 WCN36XX_HAL_11G_NW_TYPE,
506 WCN36XX_HAL_11N_NW_TYPE,
507 WCN36XX_HAL_DONOT_USE_NW_TYPE = WCN36XX_HAL_MAX_ENUM_SIZE
508};
509
510#define WCN36XX_HAL_MAC_RATESET_EID_MAX 12
511
512enum wcn36xx_hal_ht_operating_mode {
513
514 WCN36XX_HAL_HT_OP_MODE_PURE,
515
516
517 WCN36XX_HAL_HT_OP_MODE_OVERLAP_LEGACY,
518
519
520 WCN36XX_HAL_HT_OP_MODE_NO_LEGACY_20MHZ_HT,
521
522
523 WCN36XX_HAL_HT_OP_MODE_MIXED,
524
525 WCN36XX_HAL_HT_OP_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
526};
527
528
529enum ani_ed_type {
530 WCN36XX_HAL_ED_NONE,
531 WCN36XX_HAL_ED_WEP40,
532 WCN36XX_HAL_ED_WEP104,
533 WCN36XX_HAL_ED_TKIP,
534 WCN36XX_HAL_ED_CCMP,
535 WCN36XX_HAL_ED_WPI,
536 WCN36XX_HAL_ED_AES_128_CMAC,
537 WCN36XX_HAL_ED_NOT_IMPLEMENTED = WCN36XX_HAL_MAX_ENUM_SIZE
538};
539
540#define WLAN_MAX_KEY_RSC_LEN 16
541#define WLAN_WAPI_KEY_RSC_LEN 16
542
543
544#define WCN36XX_HAL_MAC_MAX_KEY_LENGTH 32
545#define WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS 4
546
547
548
549
550enum ani_key_direction {
551 WCN36XX_HAL_TX_ONLY,
552 WCN36XX_HAL_RX_ONLY,
553 WCN36XX_HAL_TX_RX,
554 WCN36XX_HAL_TX_DEFAULT,
555 WCN36XX_HAL_DONOT_USE_KEY_DIRECTION = WCN36XX_HAL_MAX_ENUM_SIZE
556};
557
558enum ani_wep_type {
559 WCN36XX_HAL_WEP_STATIC,
560 WCN36XX_HAL_WEP_DYNAMIC,
561 WCN36XX_HAL_WEP_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
562};
563
564enum wcn36xx_hal_link_state {
565
566 WCN36XX_HAL_LINK_IDLE_STATE = 0,
567 WCN36XX_HAL_LINK_PREASSOC_STATE = 1,
568 WCN36XX_HAL_LINK_POSTASSOC_STATE = 2,
569 WCN36XX_HAL_LINK_AP_STATE = 3,
570 WCN36XX_HAL_LINK_IBSS_STATE = 4,
571
572
573 WCN36XX_HAL_LINK_BTAMP_PREASSOC_STATE = 5,
574 WCN36XX_HAL_LINK_BTAMP_POSTASSOC_STATE = 6,
575 WCN36XX_HAL_LINK_BTAMP_AP_STATE = 7,
576 WCN36XX_HAL_LINK_BTAMP_STA_STATE = 8,
577
578
579 WCN36XX_HAL_LINK_LEARN_STATE = 9,
580 WCN36XX_HAL_LINK_SCAN_STATE = 10,
581 WCN36XX_HAL_LINK_FINISH_SCAN_STATE = 11,
582 WCN36XX_HAL_LINK_INIT_CAL_STATE = 12,
583 WCN36XX_HAL_LINK_FINISH_CAL_STATE = 13,
584 WCN36XX_HAL_LINK_LISTEN_STATE = 14,
585
586 WCN36XX_HAL_LINK_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
587};
588
589enum wcn36xx_hal_stats_mask {
590 HAL_SUMMARY_STATS_INFO = 0x00000001,
591 HAL_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
592 HAL_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
593 HAL_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
594 HAL_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
595 HAL_PER_STA_STATS_INFO = 0x00000020
596};
597
598
599enum bt_amp_event_type {
600 BTAMP_EVENT_CONNECTION_START,
601 BTAMP_EVENT_CONNECTION_STOP,
602 BTAMP_EVENT_CONNECTION_TERMINATED,
603
604
605 BTAMP_EVENT_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE,
606};
607
608
609enum pe_stats_mask {
610 PE_SUMMARY_STATS_INFO = 0x00000001,
611 PE_GLOBAL_CLASS_A_STATS_INFO = 0x00000002,
612 PE_GLOBAL_CLASS_B_STATS_INFO = 0x00000004,
613 PE_GLOBAL_CLASS_C_STATS_INFO = 0x00000008,
614 PE_GLOBAL_CLASS_D_STATS_INFO = 0x00000010,
615 PE_PER_STA_STATS_INFO = 0x00000020,
616
617
618 PE_STATS_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
619};
620
621
622
623
624#define WCN36XX_HAL_CFG_STA_ID 0
625#define WCN36XX_HAL_CFG_CURRENT_TX_ANTENNA 1
626#define WCN36XX_HAL_CFG_CURRENT_RX_ANTENNA 2
627#define WCN36XX_HAL_CFG_LOW_GAIN_OVERRIDE 3
628#define WCN36XX_HAL_CFG_POWER_STATE_PER_CHAIN 4
629#define WCN36XX_HAL_CFG_CAL_PERIOD 5
630#define WCN36XX_HAL_CFG_CAL_CONTROL 6
631#define WCN36XX_HAL_CFG_PROXIMITY 7
632#define WCN36XX_HAL_CFG_NETWORK_DENSITY 8
633#define WCN36XX_HAL_CFG_MAX_MEDIUM_TIME 9
634#define WCN36XX_HAL_CFG_MAX_MPDUS_IN_AMPDU 10
635#define WCN36XX_HAL_CFG_RTS_THRESHOLD 11
636#define WCN36XX_HAL_CFG_SHORT_RETRY_LIMIT 12
637#define WCN36XX_HAL_CFG_LONG_RETRY_LIMIT 13
638#define WCN36XX_HAL_CFG_FRAGMENTATION_THRESHOLD 14
639#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ZERO 15
640#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_ONE 16
641#define WCN36XX_HAL_CFG_DYNAMIC_THRESHOLD_TWO 17
642#define WCN36XX_HAL_CFG_FIXED_RATE 18
643#define WCN36XX_HAL_CFG_RETRYRATE_POLICY 19
644#define WCN36XX_HAL_CFG_RETRYRATE_SECONDARY 20
645#define WCN36XX_HAL_CFG_RETRYRATE_TERTIARY 21
646#define WCN36XX_HAL_CFG_FORCE_POLICY_PROTECTION 22
647#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_24GHZ 23
648#define WCN36XX_HAL_CFG_FIXED_RATE_MULTICAST_5GHZ 24
649#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_24GHZ 25
650#define WCN36XX_HAL_CFG_DEFAULT_RATE_INDEX_5GHZ 26
651#define WCN36XX_HAL_CFG_MAX_BA_SESSIONS 27
652#define WCN36XX_HAL_CFG_PS_DATA_INACTIVITY_TIMEOUT 28
653#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_FILTER 29
654#define WCN36XX_HAL_CFG_PS_ENABLE_RSSI_MONITOR 30
655#define WCN36XX_HAL_CFG_NUM_BEACON_PER_RSSI_AVERAGE 31
656#define WCN36XX_HAL_CFG_STATS_PERIOD 32
657#define WCN36XX_HAL_CFG_CFP_MAX_DURATION 33
658#define WCN36XX_HAL_CFG_FRAME_TRANS_ENABLED 34
659#define WCN36XX_HAL_CFG_DTIM_PERIOD 35
660#define WCN36XX_HAL_CFG_EDCA_WMM_ACBK 36
661#define WCN36XX_HAL_CFG_EDCA_WMM_ACBE 37
662#define WCN36XX_HAL_CFG_EDCA_WMM_ACVO 38
663#define WCN36XX_HAL_CFG_EDCA_WMM_ACVI 39
664#define WCN36XX_HAL_CFG_BA_THRESHOLD_HIGH 40
665#define WCN36XX_HAL_CFG_MAX_BA_BUFFERS 41
666#define WCN36XX_HAL_CFG_RPE_POLLING_THRESHOLD 42
667#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC0_REG 43
668#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC1_REG 44
669#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC2_REG 45
670#define WCN36XX_HAL_CFG_RPE_AGING_THRESHOLD_FOR_AC3_REG 46
671#define WCN36XX_HAL_CFG_NO_OF_ONCHIP_REORDER_SESSIONS 47
672#define WCN36XX_HAL_CFG_PS_LISTEN_INTERVAL 48
673#define WCN36XX_HAL_CFG_PS_HEART_BEAT_THRESHOLD 49
674#define WCN36XX_HAL_CFG_PS_NTH_BEACON_FILTER 50
675#define WCN36XX_HAL_CFG_PS_MAX_PS_POLL 51
676#define WCN36XX_HAL_CFG_PS_MIN_RSSI_THRESHOLD 52
677#define WCN36XX_HAL_CFG_PS_RSSI_FILTER_PERIOD 53
678#define WCN36XX_HAL_CFG_PS_BROADCAST_FRAME_FILTER_ENABLE 54
679#define WCN36XX_HAL_CFG_PS_IGNORE_DTIM 55
680#define WCN36XX_HAL_CFG_PS_ENABLE_BCN_EARLY_TERM 56
681#define WCN36XX_HAL_CFG_DYNAMIC_PS_POLL_VALUE 57
682#define WCN36XX_HAL_CFG_PS_NULLDATA_AP_RESP_TIMEOUT 58
683#define WCN36XX_HAL_CFG_TELE_BCN_WAKEUP_EN 59
684#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI 60
685#define WCN36XX_HAL_CFG_TELE_BCN_TRANS_LI_IDLE_BCNS 61
686#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI 62
687#define WCN36XX_HAL_CFG_TELE_BCN_MAX_LI_IDLE_BCNS 63
688#define WCN36XX_HAL_CFG_TX_PWR_CTRL_ENABLE 64
689#define WCN36XX_HAL_CFG_VALID_RADAR_CHANNEL_LIST 65
690#define WCN36XX_HAL_CFG_TX_POWER_24_20 66
691#define WCN36XX_HAL_CFG_TX_POWER_24_40 67
692#define WCN36XX_HAL_CFG_TX_POWER_50_20 68
693#define WCN36XX_HAL_CFG_TX_POWER_50_40 69
694#define WCN36XX_HAL_CFG_MCAST_BCAST_FILTER_SETTING 70
695#define WCN36XX_HAL_CFG_BCN_EARLY_TERM_WAKEUP_INTERVAL 71
696#define WCN36XX_HAL_CFG_MAX_TX_POWER_2_4 72
697#define WCN36XX_HAL_CFG_MAX_TX_POWER_5 73
698#define WCN36XX_HAL_CFG_INFRA_STA_KEEP_ALIVE_PERIOD 74
699#define WCN36XX_HAL_CFG_ENABLE_CLOSE_LOOP 75
700#define WCN36XX_HAL_CFG_BTC_EXECUTION_MODE 76
701#define WCN36XX_HAL_CFG_BTC_DHCP_BT_SLOTS_TO_BLOCK 77
702#define WCN36XX_HAL_CFG_BTC_A2DP_DHCP_BT_SUB_INTERVALS 78
703#define WCN36XX_HAL_CFG_PS_TX_INACTIVITY_TIMEOUT 79
704#define WCN36XX_HAL_CFG_WCNSS_API_VERSION 80
705#define WCN36XX_HAL_CFG_AP_KEEPALIVE_TIMEOUT 81
706#define WCN36XX_HAL_CFG_GO_KEEPALIVE_TIMEOUT 82
707#define WCN36XX_HAL_CFG_ENABLE_MC_ADDR_LIST 83
708#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_BT 84
709#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_BT 85
710#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_BT 86
711#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_BT 87
712#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_INQ_WLAN 88
713#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_PAGE_WLAN 89
714#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_CONN_WLAN 90
715#define WCN36XX_HAL_CFG_BTC_STATIC_LEN_LE_WLAN 91
716#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_BT 92
717#define WCN36XX_HAL_CFG_BTC_DYN_MAX_LEN_WLAN 93
718#define WCN36XX_HAL_CFG_BTC_MAX_SCO_BLOCK_PERC 94
719#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_A2DP 95
720#define WCN36XX_HAL_CFG_BTC_DHCP_PROT_ON_SCO 96
721#define WCN36XX_HAL_CFG_ENABLE_UNICAST_FILTER 97
722#define WCN36XX_HAL_CFG_MAX_ASSOC_LIMIT 98
723#define WCN36XX_HAL_CFG_ENABLE_LPWR_IMG_TRANSITION 99
724#define WCN36XX_HAL_CFG_ENABLE_MCC_ADAPTIVE_SCHEDULER 100
725#define WCN36XX_HAL_CFG_ENABLE_DETECT_PS_SUPPORT 101
726#define WCN36XX_HAL_CFG_AP_LINK_MONITOR_TIMEOUT 102
727#define WCN36XX_HAL_CFG_BTC_DWELL_TIME_MULTIPLIER 103
728#define WCN36XX_HAL_CFG_ENABLE_TDLS_OXYGEN_MODE 104
729#define WCN36XX_HAL_CFG_ENABLE_NAT_KEEP_ALIVE_FILTER 105
730#define WCN36XX_HAL_CFG_ENABLE_SAP_OBSS_PROT 106
731#define WCN36XX_HAL_CFG_PSPOLL_DATA_RECEP_TIMEOUT 107
732#define WCN36XX_HAL_CFG_TDLS_PUAPSD_BUFFER_STA_CAPABLE 108
733#define WCN36XX_HAL_CFG_TDLS_PUAPSD_MASK 109
734#define WCN36XX_HAL_CFG_TDLS_PUAPSD_INACTIVITY_TIME 110
735#define WCN36XX_HAL_CFG_TDLS_PUAPSD_RX_FRAME_THRESHOLD 111
736#define WCN36XX_HAL_CFG_ANTENNA_DIVERSITY 112
737#define WCN36XX_HAL_CFG_ATH_DISABLE 113
738#define WCN36XX_HAL_CFG_FLEXCONNECT_POWER_FACTOR 114
739#define WCN36XX_HAL_CFG_ENABLE_ADAPTIVE_RX_DRAIN 115
740#define WCN36XX_HAL_CFG_TDLS_OFF_CHANNEL_CAPABLE 116
741#define WCN36XX_HAL_CFG_MWS_COEX_V1_WAN_FREQ 117
742#define WCN36XX_HAL_CFG_MWS_COEX_V1_WLAN_FREQ 118
743#define WCN36XX_HAL_CFG_MWS_COEX_V1_CONFIG 119
744#define WCN36XX_HAL_CFG_MWS_COEX_V1_CONFIG2 120
745#define WCN36XX_HAL_CFG_MWS_COEX_V2_WAN_FREQ 121
746#define WCN36XX_HAL_CFG_MWS_COEX_V2_WLAN_FREQ 122
747#define WCN36XX_HAL_CFG_MWS_COEX_V2_CONFIG 123
748#define WCN36XX_HAL_CFG_MWS_COEX_V2_CONFIG2 124
749#define WCN36XX_HAL_CFG_MWS_COEX_V3_WAN_FREQ 125
750#define WCN36XX_HAL_CFG_MWS_COEX_V3_WLAN_FREQ 126
751#define WCN36XX_HAL_CFG_MWS_COEX_V3_CONFIG 127
752#define WCN36XX_HAL_CFG_MWS_COEX_V3_CONFIG2 128
753#define WCN36XX_HAL_CFG_MWS_COEX_V4_WAN_FREQ 129
754#define WCN36XX_HAL_CFG_MWS_COEX_V4_WLAN_FREQ 130
755#define WCN36XX_HAL_CFG_MWS_COEX_V4_CONFIG 131
756#define WCN36XX_HAL_CFG_MWS_COEX_V4_CONFIG2 132
757#define WCN36XX_HAL_CFG_MWS_COEX_V5_WAN_FREQ 133
758#define WCN36XX_HAL_CFG_MWS_COEX_V5_WLAN_FREQ 134
759#define WCN36XX_HAL_CFG_MWS_COEX_V5_CONFIG 135
760#define WCN36XX_HAL_CFG_MWS_COEX_V5_CONFIG2 136
761#define WCN36XX_HAL_CFG_MWS_COEX_V6_WAN_FREQ 137
762#define WCN36XX_HAL_CFG_MWS_COEX_V6_WLAN_FREQ 138
763#define WCN36XX_HAL_CFG_MWS_COEX_V6_CONFIG 139
764#define WCN36XX_HAL_CFG_MWS_COEX_V6_CONFIG2 140
765#define WCN36XX_HAL_CFG_MWS_COEX_V7_WAN_FREQ 141
766#define WCN36XX_HAL_CFG_MWS_COEX_V7_WLAN_FREQ 142
767#define WCN36XX_HAL_CFG_MWS_COEX_V7_CONFIG 143
768#define WCN36XX_HAL_CFG_MWS_COEX_V7_CONFIG2 144
769#define WCN36XX_HAL_CFG_MWS_COEX_V8_WAN_FREQ 145
770#define WCN36XX_HAL_CFG_MWS_COEX_V8_WLAN_FREQ 146
771#define WCN36XX_HAL_CFG_MWS_COEX_V8_CONFIG 147
772#define WCN36XX_HAL_CFG_MWS_COEX_V8_CONFIG2 148
773#define WCN36XX_HAL_CFG_MWS_COEX_V9_WAN_FREQ 149
774#define WCN36XX_HAL_CFG_MWS_COEX_V9_WLAN_FREQ 150
775#define WCN36XX_HAL_CFG_MWS_COEX_V9_CONFIG 151
776#define WCN36XX_HAL_CFG_MWS_COEX_V9_CONFIG2 152
777#define WCN36XX_HAL_CFG_MWS_COEX_V10_WAN_FREQ 153
778#define WCN36XX_HAL_CFG_MWS_COEX_V10_WLAN_FREQ 154
779#define WCN36XX_HAL_CFG_MWS_COEX_V10_CONFIG 155
780#define WCN36XX_HAL_CFG_MWS_COEX_V10_CONFIG2 156
781#define WCN36XX_HAL_CFG_MWS_COEX_MODEM_BACKOFF 157
782#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG1 158
783#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG2 159
784#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG3 160
785#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG4 161
786#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG5 162
787#define WCN36XX_HAL_CFG_MWS_COEX_CONFIG6 163
788#define WCN36XX_HAL_CFG_SAR_POWER_BACKOFF 164
789#define WCN36XX_HAL_CFG_GO_LINK_MONITOR_TIMEOUT 165
790#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_ACTIVE_WLAN_LEN 166
791#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_ACTIVE_BT_LEN 167
792#define WCN36XX_HAL_CFG_BTC_SAP_STATIC_OPP_ACTIVE_WLAN_LEN 168
793#define WCN36XX_HAL_CFG_BTC_SAP_STATIC_OPP_ACTIVE_BT_LEN 169
794#define WCN36XX_HAL_CFG_RMC_FIXED_RATE 170
795#define WCN36XX_HAL_CFG_ASD_PROBE_INTERVAL 171
796#define WCN36XX_HAL_CFG_ASD_TRIGGER_THRESHOLD 172
797#define WCN36XX_HAL_CFG_ASD_RTT_RSSI_HYST_THRESHOLD 173
798#define WCN36XX_HAL_CFG_BTC_CTS2S_ON_STA_DURING_SCO 174
799#define WCN36XX_HAL_CFG_SHORT_PREAMBLE 175
800#define WCN36XX_HAL_CFG_SHORT_SLOT_TIME 176
801#define WCN36XX_HAL_CFG_DELAYED_BA 177
802#define WCN36XX_HAL_CFG_IMMEDIATE_BA 178
803#define WCN36XX_HAL_CFG_DOT11_MODE 179
804#define WCN36XX_HAL_CFG_HT_CAPS 180
805#define WCN36XX_HAL_CFG_AMPDU_PARAMS 181
806#define WCN36XX_HAL_CFG_TX_BF_INFO 182
807#define WCN36XX_HAL_CFG_ASC_CAP_INFO 183
808#define WCN36XX_HAL_CFG_EXT_HT_CAPS 184
809#define WCN36XX_HAL_CFG_QOS_ENABLED 185
810#define WCN36XX_HAL_CFG_WME_ENABLED 186
811#define WCN36XX_HAL_CFG_WSM_ENABLED 187
812#define WCN36XX_HAL_CFG_WMM_ENABLED 188
813#define WCN36XX_HAL_CFG_UAPSD_PER_AC_BITMASK 189
814#define WCN36XX_HAL_CFG_MCS_RATES 190
815#define WCN36XX_HAL_CFG_VHT_CAPS 191
816#define WCN36XX_HAL_CFG_VHT_RX_SUPP_MCS 192
817#define WCN36XX_HAL_CFG_VHT_TX_SUPP_MCS 193
818#define WCN36XX_HAL_CFG_RA_FILTER_ENABLE 194
819#define WCN36XX_HAL_CFG_RA_RATE_LIMIT_INTERVAL 195
820#define WCN36XX_HAL_CFG_BTC_FATAL_HID_NSNIFF_BLK 196
821#define WCN36XX_HAL_CFG_BTC_CRITICAL_HID_NSNIFF_BLK 197
822#define WCN36XX_HAL_CFG_BTC_DYN_A2DP_TX_QUEUE_THOLD 198
823#define WCN36XX_HAL_CFG_BTC_DYN_OPP_TX_QUEUE_THOLD 199
824#define WCN36XX_HAL_CFG_LINK_FAIL_TIMEOUT 200
825#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_SP 201
826#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_RX_CNT 202
827#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_TX_CNT 203
828#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_RX_CNT_MEAS_WINDOW 204
829#define WCN36XX_HAL_CFG_MAX_UAPSD_CONSEC_TX_CNT_MEAS_WINDOW 205
830#define WCN36XX_HAL_CFG_MAX_PSPOLL_IN_WMM_UAPSD_PS_MODE 206
831#define WCN36XX_HAL_CFG_MAX_UAPSD_INACTIVITY_INTERVALS 207
832#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_WMMPS 208
833#define WCN36XX_HAL_CFG_BURST_MODE_BE_TXOP_VALUE 209
834#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_RA_START_RATE 210
835#define WCN36XX_HAL_CFG_BTC_FAST_WLAN_CONN_PREF 211
836#define WCN36XX_HAL_CFG_ENABLE_RTSCTS_HTVHT 212
837#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_IDLE_WLAN_LEN 213
838#define WCN36XX_HAL_CFG_BTC_STATIC_OPP_WLAN_IDLE_BT_LEN 214
839#define WCN36XX_HAL_CFG_LINK_FAIL_TX_CNT 215
840#define WCN36XX_HAL_CFG_TOGGLE_ARP_BDRATES 216
841#define WCN36XX_HAL_CFG_OPTIMIZE_CA_EVENT 217
842#define WCN36XX_HAL_CFG_EXT_SCAN_CONC_MODE 218
843#define WCN36XX_HAL_CFG_BAR_WAKEUP_HOST_DISABLE 219
844#define WCN36XX_HAL_CFG_SAR_BOFFSET_CORRECTION_ENABLE 220
845#define WCN36XX_HAL_CFG_UNITS_OF_BCN_WAIT_TIME 221
846#define WCN36XX_HAL_CFG_CONS_BCNMISS_COUNT 222
847#define WCN36XX_HAL_CFG_BTC_DISABLE_WLAN_LINK_CRITICAL 223
848#define WCN36XX_HAL_CFG_DISABLE_SCAN_DURING_SCO 224
849#define WCN36XX_HAL_CFG_TRIGGER_NULLFRAME_BEFORE_HB 225
850#define WCN36XX_HAL_CFG_ENABLE_POWERSAVE_OFFLOAD 226
851#define WCN36XX_HAL_CFG_MAX_PARAMS 227
852
853
854
855
856
857
858
859#define WCN36XX_HAL_CFG_ENABLE_DYNAMIC_RA_START_RATE 210
860
861
862
863
864struct wcnss_wlan_version {
865 u8 revision;
866 u8 version;
867 u8 minor;
868 u8 major;
869} __packed;
870
871
872struct wcn36xx_hal_keys {
873 u8 id;
874
875
876 u8 unicast;
877
878 enum ani_key_direction direction;
879
880
881 u8 rsc[WLAN_MAX_KEY_RSC_LEN];
882
883
884 u8 pae_role;
885
886 u16 length;
887 u8 key[WCN36XX_HAL_MAC_MAX_KEY_LENGTH];
888} __packed;
889
890
891
892
893
894struct wcn36xx_hal_set_sta_key_params {
895
896 u16 sta_index;
897
898
899 enum ani_ed_type enc_type;
900
901
902 enum ani_wep_type wep_type;
903
904
905 u8 def_wep_idx;
906
907
908 struct wcn36xx_hal_keys key[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
909
910
911
912
913
914 u8 single_tid_rc;
915
916} __packed;
917
918
919struct wcn36xx_hal_msg_header {
920 enum wcn36xx_hal_host_msg_type msg_type:16;
921 enum wcn36xx_hal_host_msg_version msg_version:16;
922 u32 len;
923} __packed;
924
925
926struct wcn36xx_hal_cfg {
927
928
929 u16 id;
930
931
932
933 u16 len;
934
935
936 u16 pad_bytes;
937
938
939 u16 reserve;
940
941
942
943} __packed;
944
945struct wcn36xx_hal_mac_start_parameters {
946
947 enum driver_type type;
948
949
950 u32 len;
951
952
953
954
955
956
957
958} __packed;
959
960struct wcn36xx_hal_mac_start_req_msg {
961
962 struct wcn36xx_hal_msg_header header;
963 struct wcn36xx_hal_mac_start_parameters params;
964} __packed;
965
966struct wcn36xx_hal_mac_start_rsp_params {
967
968 u16 status;
969
970
971 u8 stations;
972
973
974 u8 bssids;
975
976
977 struct wcnss_wlan_version version;
978
979
980 u8 crm_version[WCN36XX_HAL_VERSION_LENGTH];
981
982
983 u8 wlan_version[WCN36XX_HAL_VERSION_LENGTH];
984
985} __packed;
986
987struct wcn36xx_hal_mac_start_rsp_msg {
988 struct wcn36xx_hal_msg_header header;
989 struct wcn36xx_hal_mac_start_rsp_params start_rsp_params;
990} __packed;
991
992struct wcn36xx_hal_mac_stop_req_params {
993
994 enum wcn36xx_hal_stop_type reason;
995
996} __packed;
997
998struct wcn36xx_hal_mac_stop_req_msg {
999 struct wcn36xx_hal_msg_header header;
1000 struct wcn36xx_hal_mac_stop_req_params stop_req_params;
1001} __packed;
1002
1003struct wcn36xx_hal_mac_stop_rsp_msg {
1004 struct wcn36xx_hal_msg_header header;
1005
1006
1007 u32 status;
1008} __packed;
1009
1010struct wcn36xx_hal_update_cfg_req_msg {
1011
1012
1013
1014
1015 struct wcn36xx_hal_msg_header header;
1016
1017
1018 u32 len;
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028} __packed;
1029
1030struct wcn36xx_hal_update_cfg_rsp_msg {
1031 struct wcn36xx_hal_msg_header header;
1032
1033
1034 u32 status;
1035
1036} __packed;
1037
1038
1039struct wcn36xx_hal_mac_frame_ctl {
1040
1041#ifndef ANI_LITTLE_BIT_ENDIAN
1042
1043 u8 subType:4;
1044 u8 type:2;
1045 u8 protVer:2;
1046
1047 u8 order:1;
1048 u8 wep:1;
1049 u8 moreData:1;
1050 u8 powerMgmt:1;
1051 u8 retry:1;
1052 u8 moreFrag:1;
1053 u8 fromDS:1;
1054 u8 toDS:1;
1055
1056#else
1057
1058 u8 protVer:2;
1059 u8 type:2;
1060 u8 subType:4;
1061
1062 u8 toDS:1;
1063 u8 fromDS:1;
1064 u8 moreFrag:1;
1065 u8 retry:1;
1066 u8 powerMgmt:1;
1067 u8 moreData:1;
1068 u8 wep:1;
1069 u8 order:1;
1070
1071#endif
1072
1073};
1074
1075
1076struct wcn36xx_hal_mac_seq_ctl {
1077 u8 fragNum:4;
1078 u8 seqNumLo:4;
1079 u8 seqNumHi:8;
1080};
1081
1082
1083struct wcn36xx_hal_mac_mgmt_hdr {
1084 struct wcn36xx_hal_mac_frame_ctl fc;
1085 u8 durationLo;
1086 u8 durationHi;
1087 u8 da[6];
1088 u8 sa[6];
1089 u8 bssId[6];
1090 struct wcn36xx_hal_mac_seq_ctl seqControl;
1091};
1092
1093
1094#define WCN36XX_HAL_NUM_BSSID 2
1095
1096
1097struct wcn36xx_hal_scan_entry {
1098 u8 bss_index[WCN36XX_HAL_NUM_BSSID];
1099 u8 active_bss_count;
1100};
1101
1102struct wcn36xx_hal_init_scan_req_msg {
1103 struct wcn36xx_hal_msg_header header;
1104
1105
1106
1107 enum wcn36xx_hal_sys_mode mode;
1108
1109
1110 u8 bssid[ETH_ALEN];
1111
1112
1113 u8 notify;
1114
1115
1116
1117 u8 frame_type;
1118
1119
1120
1121
1122
1123 u8 frame_len;
1124
1125
1126
1127 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1128
1129
1130 struct wcn36xx_hal_scan_entry scan_entry;
1131};
1132
1133struct wcn36xx_hal_init_scan_con_req_msg {
1134 struct wcn36xx_hal_msg_header header;
1135
1136
1137
1138 enum wcn36xx_hal_sys_mode mode;
1139
1140
1141 u8 bssid[ETH_ALEN];
1142
1143
1144 u8 notify;
1145
1146
1147
1148 u8 frame_type;
1149
1150
1151
1152
1153
1154 u8 frame_length;
1155
1156
1157
1158 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1159
1160
1161 struct wcn36xx_hal_scan_entry scan_entry;
1162
1163
1164 u8 use_noa;
1165
1166
1167 u16 scan_duration;
1168
1169};
1170
1171struct wcn36xx_hal_init_scan_rsp_msg {
1172 struct wcn36xx_hal_msg_header header;
1173
1174
1175 u32 status;
1176
1177} __packed;
1178
1179struct wcn36xx_hal_start_scan_req_msg {
1180 struct wcn36xx_hal_msg_header header;
1181
1182
1183 u8 scan_channel;
1184} __packed;
1185
1186struct wcn36xx_hal_start_rsp_msg {
1187 struct wcn36xx_hal_msg_header header;
1188
1189
1190 u32 status;
1191
1192 u32 start_tsf[2];
1193 u8 tx_mgmt_power;
1194
1195} __packed;
1196
1197struct wcn36xx_hal_end_scan_req_msg {
1198 struct wcn36xx_hal_msg_header header;
1199
1200
1201
1202
1203 u8 scan_channel;
1204} __packed;
1205
1206struct wcn36xx_hal_end_scan_rsp_msg {
1207 struct wcn36xx_hal_msg_header header;
1208
1209
1210 u32 status;
1211} __packed;
1212
1213struct wcn36xx_hal_finish_scan_req_msg {
1214 struct wcn36xx_hal_msg_header header;
1215
1216
1217
1218 enum wcn36xx_hal_sys_mode mode;
1219
1220
1221 u8 oper_channel;
1222
1223
1224
1225
1226 enum phy_chan_bond_state cb_state;
1227
1228
1229 u8 bssid[ETH_ALEN];
1230
1231
1232 u8 notify;
1233
1234
1235
1236 u8 frame_type;
1237
1238
1239
1240
1241
1242 u8 frame_length;
1243
1244
1245
1246 struct wcn36xx_hal_mac_mgmt_hdr mac_mgmt_hdr;
1247
1248
1249 struct wcn36xx_hal_scan_entry scan_entry;
1250
1251} __packed;
1252
1253struct wcn36xx_hal_finish_scan_rsp_msg {
1254 struct wcn36xx_hal_msg_header header;
1255
1256
1257 u32 status;
1258
1259} __packed;
1260
1261enum wcn36xx_hal_scan_type {
1262 WCN36XX_HAL_SCAN_TYPE_PASSIVE = 0x00,
1263 WCN36XX_HAL_SCAN_TYPE_ACTIVE = WCN36XX_HAL_MAX_ENUM_SIZE
1264};
1265
1266struct wcn36xx_hal_mac_ssid {
1267 u8 length;
1268 u8 ssid[32];
1269} __packed;
1270
1271struct wcn36xx_hal_start_scan_offload_req_msg {
1272 struct wcn36xx_hal_msg_header header;
1273
1274
1275 u8 num_bssid;
1276 u8 bssids[4][ETH_ALEN];
1277
1278
1279 u8 num_ssid;
1280 struct wcn36xx_hal_mac_ssid ssids[10];
1281
1282
1283 u8 scan_hidden;
1284
1285
1286 u8 mac[ETH_ALEN];
1287
1288
1289 enum wcn36xx_hal_bss_type bss_type;
1290
1291
1292 enum wcn36xx_hal_scan_type scan_type;
1293
1294
1295 u32 min_ch_time;
1296
1297
1298 u32 max_ch_time;
1299
1300
1301 u8 p2p_search;
1302
1303
1304 u8 num_channel;
1305 u8 channels[80];
1306
1307
1308 u16 ie_len;
1309 u8 ie[WCN36XX_MAX_SCAN_IE_LEN];
1310} __packed;
1311
1312struct wcn36xx_hal_start_scan_offload_rsp_msg {
1313 struct wcn36xx_hal_msg_header header;
1314
1315
1316 u32 status;
1317} __packed;
1318
1319enum wcn36xx_hal_scan_offload_ind_type {
1320
1321 WCN36XX_HAL_SCAN_IND_STARTED = 0x01,
1322
1323 WCN36XX_HAL_SCAN_IND_COMPLETED = 0x02,
1324
1325 WCN36XX_HAL_SCAN_IND_FOREIGN_CHANNEL = 0x08,
1326
1327 WCN36XX_HAL_SCAN_IND_DEQUEUED = 0x10,
1328
1329 WCN36XX_HAL_SCAN_IND_PREEMPTED = 0x20,
1330
1331 WCN36XX_HAL_SCAN_IND_FAILED = 0x40,
1332
1333 WCN36XX_HAL_SCAN_IND_RESTARTED = 0x80,
1334 WCN36XX_HAL_SCAN_IND_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
1335};
1336
1337struct wcn36xx_hal_scan_offload_ind {
1338 struct wcn36xx_hal_msg_header header;
1339
1340 u32 type;
1341 u32 channel_mhz;
1342 u32 scan_id;
1343} __packed;
1344
1345struct wcn36xx_hal_stop_scan_offload_req_msg {
1346 struct wcn36xx_hal_msg_header header;
1347} __packed;
1348
1349struct wcn36xx_hal_stop_scan_offload_rsp_msg {
1350 struct wcn36xx_hal_msg_header header;
1351
1352
1353 u32 status;
1354} __packed;
1355
1356enum wcn36xx_hal_rate_index {
1357 HW_RATE_INDEX_1MBPS = 0x82,
1358 HW_RATE_INDEX_2MBPS = 0x84,
1359 HW_RATE_INDEX_5_5MBPS = 0x8B,
1360 HW_RATE_INDEX_6MBPS = 0x0C,
1361 HW_RATE_INDEX_9MBPS = 0x12,
1362 HW_RATE_INDEX_11MBPS = 0x96,
1363 HW_RATE_INDEX_12MBPS = 0x18,
1364 HW_RATE_INDEX_18MBPS = 0x24,
1365 HW_RATE_INDEX_24MBPS = 0x30,
1366 HW_RATE_INDEX_36MBPS = 0x48,
1367 HW_RATE_INDEX_48MBPS = 0x60,
1368 HW_RATE_INDEX_54MBPS = 0x6C
1369};
1370
1371struct wcn36xx_hal_supported_rates {
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391 enum sta_rate_mode op_rate_mode;
1392
1393
1394
1395 u16 dsss_rates[WCN36XX_HAL_NUM_DSSS_RATES];
1396 u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES];
1397 u16 legacy_rates[WCN36XX_HAL_NUM_POLARIS_RATES];
1398 u16 reserved;
1399
1400
1401
1402
1403
1404
1405 u32 enhanced_rate_bitmap;
1406
1407
1408
1409
1410
1411 u8 supported_mcs_set[WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET];
1412
1413
1414
1415
1416
1417
1418
1419 u16 rx_highest_data_rate;
1420
1421} __packed;
1422
1423struct wcn36xx_hal_config_sta_params {
1424
1425 u8 bssid[ETH_ALEN];
1426
1427
1428 u16 aid;
1429
1430
1431 u8 type;
1432
1433
1434 u8 short_preamble_supported;
1435
1436
1437 u8 mac[ETH_ALEN];
1438
1439
1440 u16 listen_interval;
1441
1442
1443 u8 wmm_enabled;
1444
1445
1446 u8 ht_capable;
1447
1448
1449 u8 tx_channel_width_set;
1450
1451
1452 u8 rifs_mode;
1453
1454
1455
1456
1457 u8 lsig_txop_protection;
1458
1459
1460
1461 u8 max_ampdu_size;
1462
1463
1464 u8 max_ampdu_density;
1465
1466
1467 u8 max_amsdu_size;
1468
1469
1470 u8 sgi_40mhz;
1471
1472
1473 u8 sgi_20Mhz;
1474
1475
1476
1477 struct wcn36xx_hal_supported_rates supported_rates;
1478
1479
1480 u8 rmf;
1481
1482
1483 u32 encrypt_type;
1484
1485
1486
1487
1488 u8 action;
1489
1490
1491
1492
1493 u8 uapsd;
1494
1495
1496 u8 max_sp_len;
1497
1498
1499
1500 u8 green_field_capable;
1501
1502
1503 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1504
1505
1506 u8 delayed_ba_support;
1507
1508
1509 u8 max_ampdu_duration;
1510
1511
1512
1513
1514
1515 u8 dsss_cck_mode_40mhz;
1516
1517
1518
1519 u8 sta_index;
1520
1521
1522
1523
1524 u8 bssid_index;
1525
1526 u8 p2p;
1527
1528
1529
1530
1531} __packed;
1532
1533struct wcn36xx_hal_config_sta_req_msg {
1534 struct wcn36xx_hal_msg_header header;
1535 struct wcn36xx_hal_config_sta_params sta_params;
1536} __packed;
1537
1538struct wcn36xx_hal_supported_rates_v1 {
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551
1552
1553
1554
1555
1556
1557 enum sta_rate_mode op_rate_mode;
1558
1559
1560
1561
1562 u16 dsss_rates[WCN36XX_HAL_NUM_DSSS_RATES];
1563 u16 ofdm_rates[WCN36XX_HAL_NUM_OFDM_RATES];
1564 u16 legacy_rates[WCN36XX_HAL_NUM_POLARIS_RATES];
1565 u16 reserved;
1566
1567
1568
1569
1570
1571
1572
1573 u32 enhanced_rate_bitmap;
1574
1575
1576
1577
1578 u8 supported_mcs_set[WCN36XX_HAL_MAC_MAX_SUPPORTED_MCS_SET];
1579
1580
1581
1582
1583
1584
1585 u16 rx_highest_data_rate;
1586
1587
1588
1589
1590 u16 vht_rx_mcs_map;
1591
1592
1593
1594
1595 u16 vht_rx_highest_data_rate;
1596
1597
1598
1599
1600 u16 vht_tx_mcs_map;
1601
1602
1603
1604
1605 u16 vht_tx_highest_data_rate;
1606} __packed;
1607
1608struct wcn36xx_hal_config_sta_params_v1 {
1609
1610 u8 bssid[ETH_ALEN];
1611
1612
1613 u16 aid;
1614
1615
1616 u8 type;
1617
1618
1619 u8 short_preamble_supported;
1620
1621
1622 u8 mac[ETH_ALEN];
1623
1624
1625 u16 listen_interval;
1626
1627
1628 u8 wmm_enabled;
1629
1630
1631 u8 ht_capable;
1632
1633
1634 u8 tx_channel_width_set;
1635
1636
1637 u8 rifs_mode;
1638
1639
1640
1641
1642 u8 lsig_txop_protection;
1643
1644
1645
1646 u8 max_ampdu_size;
1647
1648
1649 u8 max_ampdu_density;
1650
1651
1652 u8 max_amsdu_size;
1653
1654
1655 u8 sgi_40mhz;
1656
1657
1658 u8 sgi_20Mhz;
1659
1660
1661 u8 rmf;
1662
1663
1664 u32 encrypt_type;
1665
1666
1667
1668
1669 u8 action;
1670
1671
1672
1673
1674 u8 uapsd;
1675
1676
1677 u8 max_sp_len;
1678
1679
1680
1681 u8 green_field_capable;
1682
1683
1684 enum wcn36xx_hal_ht_mimo_state mimo_ps;
1685
1686
1687 u8 delayed_ba_support;
1688
1689
1690 u8 max_ampdu_duration;
1691
1692
1693
1694
1695
1696 u8 dsss_cck_mode_40mhz;
1697
1698
1699
1700 u8 sta_index;
1701
1702
1703
1704
1705 u8 bssid_index;
1706
1707 u8 p2p;
1708
1709
1710 u8 ht_ldpc_enabled:1;
1711 u8 vht_ldpc_enabled:1;
1712 u8 vht_tx_bf_enabled:1;
1713 u8 vht_tx_mu_beamformee_capable:1;
1714 u8 reserved:4;
1715
1716
1717 struct wcn36xx_hal_supported_rates_v1 supported_rates;
1718
1719 u8 vht_capable;
1720 u8 vht_tx_channel_width_set;
1721
1722} __packed;
1723
1724#define WCN36XX_DIFF_STA_PARAMS_V1_NOVHT 10
1725
1726struct wcn36xx_hal_config_sta_req_msg_v1 {
1727 struct wcn36xx_hal_msg_header header;
1728 struct wcn36xx_hal_config_sta_params_v1 sta_params;
1729} __packed;
1730
1731struct config_sta_rsp_params {
1732
1733 u32 status;
1734
1735
1736 u8 sta_index;
1737
1738
1739 u8 bssid_index;
1740
1741
1742 u8 dpu_index;
1743
1744
1745 u8 bcast_dpu_index;
1746
1747
1748 u8 bcast_mgmt_dpu_idx;
1749
1750
1751 u8 uc_ucast_sig;
1752
1753
1754 u8 uc_bcast_sig;
1755
1756
1757 u8 uc_mgmt_sig;
1758
1759 u8 p2p;
1760
1761} __packed;
1762
1763struct wcn36xx_hal_config_sta_rsp_msg {
1764 struct wcn36xx_hal_msg_header header;
1765
1766 struct config_sta_rsp_params params;
1767} __packed;
1768
1769
1770struct wcn36xx_hal_delete_sta_req_msg {
1771 struct wcn36xx_hal_msg_header header;
1772
1773
1774 u8 sta_index;
1775
1776} __packed;
1777
1778
1779struct wcn36xx_hal_delete_sta_rsp_msg {
1780 struct wcn36xx_hal_msg_header header;
1781
1782
1783 u32 status;
1784
1785
1786 u8 sta_id;
1787} __packed;
1788
1789
1790
1791struct wcn36xx_hal_rate_set {
1792 u8 num_rates;
1793 u8 rate[WCN36XX_HAL_MAC_RATESET_EID_MAX];
1794} __packed;
1795
1796
1797struct wcn36xx_hal_aci_aifsn {
1798#ifndef ANI_LITTLE_BIT_ENDIAN
1799 u8 rsvd:1;
1800 u8 aci:2;
1801 u8 acm:1;
1802 u8 aifsn:4;
1803#else
1804 u8 aifsn:4;
1805 u8 acm:1;
1806 u8 aci:2;
1807 u8 rsvd:1;
1808#endif
1809} __packed;
1810
1811
1812struct wcn36xx_hal_mac_cw {
1813#ifndef ANI_LITTLE_BIT_ENDIAN
1814 u8 max:4;
1815 u8 min:4;
1816#else
1817 u8 min:4;
1818 u8 max:4;
1819#endif
1820} __packed;
1821
1822struct wcn36xx_hal_edca_param_record {
1823 struct wcn36xx_hal_aci_aifsn aci;
1824 struct wcn36xx_hal_mac_cw cw;
1825 u16 txop_limit;
1826} __packed;
1827
1828
1829
1830enum wcn36xx_hal_con_mode {
1831 WCN36XX_HAL_STA_MODE = 0,
1832
1833
1834
1835 WCN36XX_HAL_STA_SAP_MODE = 1,
1836
1837 WCN36XX_HAL_P2P_CLIENT_MODE,
1838 WCN36XX_HAL_P2P_GO_MODE,
1839 WCN36XX_HAL_MONITOR_MODE,
1840};
1841
1842
1843
1844
1845
1846
1847enum wcn36xx_hal_concurrency_mode {
1848 HAL_STA = 1,
1849 HAL_SAP = 2,
1850
1851
1852 HAL_STA_SAP = 3,
1853
1854 HAL_P2P_CLIENT = 4,
1855 HAL_P2P_GO = 8,
1856 HAL_MAX_CONCURRENCY_PERSONA = 4
1857};
1858
1859struct wcn36xx_hal_config_bss_params {
1860
1861 u8 bssid[ETH_ALEN];
1862
1863
1864 u8 self_mac_addr[ETH_ALEN];
1865
1866
1867 enum wcn36xx_hal_bss_type bss_type;
1868
1869
1870 u8 oper_mode;
1871
1872
1873 enum wcn36xx_hal_nw_type nw_type;
1874
1875
1876 u8 short_slot_time_supported;
1877
1878
1879 u8 lla_coexist;
1880
1881
1882 u8 llb_coexist;
1883
1884
1885 u8 llg_coexist;
1886
1887
1888 u8 ht20_coexist;
1889
1890
1891 u8 lln_non_gf_coexist;
1892
1893
1894 u8 lsig_tx_op_protection_full_support;
1895
1896
1897 u8 rifs_mode;
1898
1899
1900 u16 beacon_interval;
1901
1902
1903 u8 dtim_period;
1904
1905
1906 u8 tx_channel_width_set;
1907
1908
1909 u8 oper_channel;
1910
1911
1912 u8 ext_channel;
1913
1914
1915 u8 reserved;
1916
1917
1918
1919
1920
1921
1922
1923
1924
1925
1926 struct wcn36xx_hal_config_sta_params sta;
1927
1928 struct wcn36xx_hal_mac_ssid ssid;
1929
1930
1931
1932
1933
1934 u8 action;
1935
1936
1937 struct wcn36xx_hal_rate_set rateset;
1938
1939
1940 u8 ht;
1941
1942
1943 u8 obss_prot_enabled;
1944
1945
1946 u8 rmf;
1947
1948
1949 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
1950
1951
1952 u8 dual_cts_protection;
1953
1954
1955 u8 max_probe_resp_retry_limit;
1956
1957
1958 u8 hidden_ssid;
1959
1960
1961 u8 proxy_probe_resp;
1962
1963
1964
1965
1966
1967 u8 edca_params_valid;
1968
1969
1970 struct wcn36xx_hal_edca_param_record acbe;
1971
1972
1973 struct wcn36xx_hal_edca_param_record acbk;
1974
1975
1976 struct wcn36xx_hal_edca_param_record acvi;
1977
1978
1979 struct wcn36xx_hal_edca_param_record acvo;
1980
1981
1982 u8 ext_set_sta_key_param_valid;
1983
1984
1985 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
1986
1987
1988
1989 u8 wcn36xx_hal_persona;
1990
1991 u8 spectrum_mgt_enable;
1992
1993
1994 s8 tx_mgmt_power;
1995
1996
1997
1998 s8 max_tx_power;
1999} __packed;
2000
2001struct wcn36xx_hal_config_bss_req_msg {
2002 struct wcn36xx_hal_msg_header header;
2003 struct wcn36xx_hal_config_bss_params bss_params;
2004} __packed;
2005
2006struct wcn36xx_hal_config_bss_params_v1 {
2007
2008 u8 bssid[ETH_ALEN];
2009
2010
2011 u8 self_mac_addr[ETH_ALEN];
2012
2013
2014 enum wcn36xx_hal_bss_type bss_type;
2015
2016
2017 u8 oper_mode;
2018
2019
2020 enum wcn36xx_hal_nw_type nw_type;
2021
2022
2023 u8 short_slot_time_supported;
2024
2025
2026 u8 lla_coexist;
2027
2028
2029 u8 llb_coexist;
2030
2031
2032 u8 llg_coexist;
2033
2034
2035 u8 ht20_coexist;
2036
2037
2038 u8 lln_non_gf_coexist;
2039
2040
2041 u8 lsig_tx_op_protection_full_support;
2042
2043
2044 u8 rifs_mode;
2045
2046
2047 u16 beacon_interval;
2048
2049
2050 u8 dtim_period;
2051
2052
2053 u8 tx_channel_width_set;
2054
2055
2056 u8 oper_channel;
2057
2058
2059 u8 ext_channel;
2060
2061
2062 u8 reserved;
2063
2064
2065 struct wcn36xx_hal_mac_ssid ssid;
2066
2067
2068
2069
2070
2071 u8 action;
2072
2073
2074 struct wcn36xx_hal_rate_set rateset;
2075
2076
2077 u8 ht;
2078
2079
2080 u8 obss_prot_enabled;
2081
2082
2083 u8 rmf;
2084
2085
2086 enum wcn36xx_hal_ht_operating_mode ht_oper_mode;
2087
2088
2089 u8 dual_cts_protection;
2090
2091
2092 u8 max_probe_resp_retry_limit;
2093
2094
2095 u8 hidden_ssid;
2096
2097
2098 u8 proxy_probe_resp;
2099
2100
2101
2102
2103
2104 u8 edca_params_valid;
2105
2106
2107 struct wcn36xx_hal_edca_param_record acbe;
2108
2109
2110 struct wcn36xx_hal_edca_param_record acbk;
2111
2112
2113 struct wcn36xx_hal_edca_param_record acvi;
2114
2115
2116 struct wcn36xx_hal_edca_param_record acvo;
2117
2118
2119 u8 ext_set_sta_key_param_valid;
2120
2121
2122 struct wcn36xx_hal_set_sta_key_params ext_set_sta_key_param;
2123
2124
2125
2126 u8 wcn36xx_hal_persona;
2127
2128 u8 spectrum_mgt_enable;
2129
2130
2131 s8 tx_mgmt_power;
2132
2133
2134
2135 s8 max_tx_power;
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145 struct wcn36xx_hal_config_sta_params_v1 sta;
2146
2147 u8 vht_capable;
2148 u8 vht_tx_channel_width_set;
2149
2150} __packed;
2151
2152#define WCN36XX_DIFF_BSS_PARAMS_V1_NOVHT (WCN36XX_DIFF_STA_PARAMS_V1_NOVHT + 2)
2153
2154struct wcn36xx_hal_config_bss_req_msg_v1 {
2155 struct wcn36xx_hal_msg_header header;
2156 struct wcn36xx_hal_config_bss_params_v1 bss_params;
2157} __packed;
2158
2159struct wcn36xx_hal_config_bss_rsp_params {
2160
2161 u32 status;
2162
2163
2164 u8 bss_index;
2165
2166
2167 u8 dpu_desc_index;
2168
2169
2170 u8 ucast_dpu_signature;
2171
2172
2173 u8 bcast_dpu_desc_indx;
2174
2175
2176 u8 bcast_dpu_signature;
2177
2178
2179 u8 mgmt_dpu_desc_index;
2180
2181
2182 u8 mgmt_dpu_signature;
2183
2184
2185 u8 bss_sta_index;
2186
2187
2188 u8 bss_self_sta_index;
2189
2190
2191 u8 bss_bcast_sta_idx;
2192
2193
2194 u8 mac[ETH_ALEN];
2195
2196
2197 s8 tx_mgmt_power;
2198
2199} __packed;
2200
2201struct wcn36xx_hal_config_bss_rsp_msg {
2202 struct wcn36xx_hal_msg_header header;
2203 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
2204} __packed;
2205
2206struct wcn36xx_hal_delete_bss_req_msg {
2207 struct wcn36xx_hal_msg_header header;
2208
2209
2210 u8 bss_index;
2211
2212} __packed;
2213
2214struct wcn36xx_hal_delete_bss_rsp_msg {
2215 struct wcn36xx_hal_msg_header header;
2216
2217
2218 u32 status;
2219
2220
2221 u8 bss_index;
2222
2223} __packed;
2224
2225struct wcn36xx_hal_join_req_msg {
2226 struct wcn36xx_hal_msg_header header;
2227
2228
2229 u8 bssid[ETH_ALEN];
2230
2231
2232 u8 channel;
2233
2234
2235 u8 self_sta_mac_addr[ETH_ALEN];
2236
2237
2238 u8 local_power_constraint;
2239
2240
2241 enum phy_chan_bond_state secondary_channel_offset;
2242
2243
2244 enum wcn36xx_hal_link_state link_state;
2245
2246
2247 s8 max_tx_power;
2248} __packed;
2249
2250struct wcn36xx_hal_join_rsp_msg {
2251 struct wcn36xx_hal_msg_header header;
2252
2253
2254 u32 status;
2255
2256
2257 u8 tx_mgmt_power;
2258} __packed;
2259
2260struct post_assoc_req_msg {
2261 struct wcn36xx_hal_msg_header header;
2262
2263 struct wcn36xx_hal_config_sta_params sta_params;
2264 struct wcn36xx_hal_config_bss_params bss_params;
2265};
2266
2267struct post_assoc_rsp_msg {
2268 struct wcn36xx_hal_msg_header header;
2269 struct config_sta_rsp_params sta_rsp_params;
2270 struct wcn36xx_hal_config_bss_rsp_params bss_rsp_params;
2271};
2272
2273
2274struct wcn36xx_hal_set_bss_key_req_msg {
2275 struct wcn36xx_hal_msg_header header;
2276
2277
2278 u8 bss_idx;
2279
2280
2281 enum ani_ed_type enc_type;
2282
2283
2284 u8 num_keys;
2285
2286
2287 struct wcn36xx_hal_keys keys[WCN36XX_HAL_MAC_MAX_NUM_OF_DEFAULT_KEYS];
2288
2289
2290
2291 u8 single_tid_rc;
2292} __packed;
2293
2294
2295struct wcn36xx_hal_set_bss_key_req_msg_tagged {
2296 struct wcn36xx_hal_set_bss_key_req_msg Msg;
2297 u32 tag;
2298} __packed;
2299
2300struct wcn36xx_hal_set_bss_key_rsp_msg {
2301 struct wcn36xx_hal_msg_header header;
2302
2303
2304 u32 status;
2305} __packed;
2306
2307
2308
2309
2310
2311
2312
2313struct wcn36xx_hal_set_sta_key_req_msg {
2314 struct wcn36xx_hal_msg_header header;
2315 struct wcn36xx_hal_set_sta_key_params set_sta_key_params;
2316} __packed;
2317
2318struct wcn36xx_hal_set_sta_key_rsp_msg {
2319 struct wcn36xx_hal_msg_header header;
2320
2321
2322 u32 status;
2323} __packed;
2324
2325struct wcn36xx_hal_remove_bss_key_req_msg {
2326 struct wcn36xx_hal_msg_header header;
2327
2328
2329 u8 bss_idx;
2330
2331
2332 enum ani_ed_type enc_type;
2333
2334
2335 u8 key_id;
2336
2337
2338
2339 enum ani_wep_type wep_type;
2340} __packed;
2341
2342struct wcn36xx_hal_remove_bss_key_rsp_msg {
2343 struct wcn36xx_hal_msg_header header;
2344
2345
2346 u32 status;
2347} __packed;
2348
2349
2350
2351
2352struct wcn36xx_hal_remove_sta_key_req_msg {
2353 struct wcn36xx_hal_msg_header header;
2354
2355
2356 u16 sta_idx;
2357
2358
2359 enum ani_ed_type enc_type;
2360
2361
2362 u8 key_id;
2363
2364
2365
2366 u8 unicast;
2367
2368} __packed;
2369
2370struct wcn36xx_hal_remove_sta_key_rsp_msg {
2371 struct wcn36xx_hal_msg_header header;
2372
2373
2374 u32 status;
2375
2376} __packed;
2377
2378#ifdef FEATURE_OEM_DATA_SUPPORT
2379
2380#ifndef OEM_DATA_REQ_SIZE
2381#define OEM_DATA_REQ_SIZE 134
2382#endif
2383
2384#ifndef OEM_DATA_RSP_SIZE
2385#define OEM_DATA_RSP_SIZE 1968
2386#endif
2387
2388struct start_oem_data_req_msg {
2389 struct wcn36xx_hal_msg_header header;
2390
2391 u32 status;
2392 tSirMacAddr self_mac_addr;
2393 u8 oem_data_req[OEM_DATA_REQ_SIZE];
2394
2395};
2396
2397struct start_oem_data_rsp_msg {
2398 struct wcn36xx_hal_msg_header header;
2399
2400 u8 oem_data_rsp[OEM_DATA_RSP_SIZE];
2401};
2402
2403#endif
2404
2405struct wcn36xx_hal_switch_channel_req_msg {
2406 struct wcn36xx_hal_msg_header header;
2407
2408
2409 u8 channel_number;
2410
2411
2412 u8 local_power_constraint;
2413
2414
2415 enum phy_chan_bond_state secondary_channel_offset;
2416
2417
2418 u8 tx_mgmt_power;
2419
2420
2421 u8 max_tx_power;
2422
2423
2424 u8 self_sta_mac_addr[ETH_ALEN];
2425
2426
2427
2428
2429
2430
2431
2432
2433
2434
2435 u8 bssid[ETH_ALEN];
2436} __packed;
2437
2438struct wcn36xx_hal_switch_channel_rsp_msg {
2439 struct wcn36xx_hal_msg_header header;
2440
2441
2442 u32 status;
2443
2444
2445 u8 channel_number;
2446
2447
2448 u8 tx_mgmt_power;
2449
2450
2451 u8 bssid[ETH_ALEN];
2452
2453} __packed;
2454
2455struct wcn36xx_hal_process_ptt_msg_req_msg {
2456 struct wcn36xx_hal_msg_header header;
2457
2458
2459 u8 ptt_msg[];
2460} __packed;
2461
2462struct wcn36xx_hal_process_ptt_msg_rsp_msg {
2463 struct wcn36xx_hal_msg_header header;
2464
2465
2466 u32 ptt_msg_resp_status;
2467
2468 u8 ptt_msg[];
2469} __packed;
2470
2471struct update_edca_params_req_msg {
2472 struct wcn36xx_hal_msg_header header;
2473
2474
2475 u16 bss_index;
2476
2477
2478 struct wcn36xx_hal_edca_param_record acbe;
2479
2480
2481 struct wcn36xx_hal_edca_param_record acbk;
2482
2483
2484 struct wcn36xx_hal_edca_param_record acvi;
2485
2486
2487 struct wcn36xx_hal_edca_param_record acvo;
2488};
2489
2490struct update_edca_params_rsp_msg {
2491 struct wcn36xx_hal_msg_header header;
2492
2493
2494 u32 status;
2495};
2496
2497struct dpu_stats_params {
2498
2499 u16 sta_index;
2500
2501
2502 u8 enc_mode;
2503
2504
2505 u32 status;
2506
2507
2508 u32 send_blocks;
2509 u32 recv_blocks;
2510 u32 replays;
2511 u8 mic_error_cnt;
2512 u32 prot_excl_cnt;
2513 u16 format_err_cnt;
2514 u16 un_decryptable_cnt;
2515 u32 decrypt_err_cnt;
2516 u32 decrypt_ok_cnt;
2517};
2518
2519struct wcn36xx_hal_stats_req_msg {
2520 struct wcn36xx_hal_msg_header header;
2521
2522
2523 u32 sta_id;
2524
2525
2526 u32 stats_mask;
2527};
2528
2529struct ani_summary_stats_info {
2530
2531
2532 u32 retry_cnt[4];
2533
2534
2535
2536
2537 u32 multiple_retry_cnt[4];
2538
2539
2540
2541
2542 u32 tx_frm_cnt[4];
2543
2544
2545
2546 u32 rx_frm_cnt;
2547
2548
2549 u32 frm_dup_cnt;
2550
2551
2552 u32 fail_cnt[4];
2553
2554
2555
2556 u32 rts_fail_cnt;
2557
2558
2559
2560 u32 ack_fail_cnt;
2561
2562
2563
2564 u32 rts_succ_cnt;
2565
2566
2567
2568
2569 u32 rx_discard_cnt;
2570
2571
2572
2573
2574 u32 rx_error_cnt;
2575
2576
2577
2578
2579 u32 tx_byte_cnt;
2580};
2581
2582
2583enum tx_rate_info {
2584
2585 HAL_TX_RATE_LEGACY = 0x1,
2586
2587
2588 HAL_TX_RATE_HT20 = 0x2,
2589
2590
2591 HAL_TX_RATE_HT40 = 0x4,
2592
2593
2594 HAL_TX_RATE_SGI = 0x8,
2595
2596
2597 HAL_TX_RATE_LGI = 0x10
2598};
2599
2600struct ani_global_class_a_stats_info {
2601
2602
2603 u32 rx_frag_cnt;
2604
2605
2606
2607
2608 u32 promiscuous_rx_frag_cnt;
2609
2610
2611
2612
2613
2614 u32 rx_input_sensitivity;
2615
2616
2617
2618 u32 max_pwr;
2619
2620
2621
2622
2623 u32 sync_fail_cnt;
2624
2625
2626
2627 u32 tx_rate;
2628
2629
2630 u32 mcs_index;
2631
2632
2633
2634 u32 tx_rate_flags;
2635};
2636
2637struct ani_global_security_stats {
2638
2639
2640
2641 u32 rx_wep_unencrypted_frm_cnt;
2642
2643
2644
2645 u32 rx_mic_fail_cnt;
2646
2647
2648
2649 u32 tkip_icv_err;
2650
2651
2652
2653 u32 aes_ccmp_format_err;
2654
2655
2656
2657 u32 aes_ccmp_replay_cnt;
2658
2659
2660
2661
2662 u32 aes_ccmp_decrpt_err;
2663
2664
2665
2666 u32 wep_undecryptable_cnt;
2667
2668
2669
2670 u32 wep_icv_err;
2671
2672
2673
2674 u32 rx_decrypt_succ_cnt;
2675
2676
2677
2678 u32 rx_decrypt_fail_cnt;
2679};
2680
2681struct ani_global_class_b_stats_info {
2682 struct ani_global_security_stats uc_stats;
2683 struct ani_global_security_stats mc_bc_stats;
2684};
2685
2686struct ani_global_class_c_stats_info {
2687
2688
2689
2690 u32 rx_amsdu_cnt;
2691
2692
2693
2694 u32 rx_ampdu_cnt;
2695
2696
2697
2698 u32 tx_20_frm_cnt;
2699
2700
2701
2702 u32 rx_20_frm_cnt;
2703
2704
2705
2706 u32 rx_mpdu_in_ampdu_cnt;
2707
2708
2709
2710
2711 u32 ampdu_delimiter_crc_err;
2712};
2713
2714struct ani_per_sta_stats_info {
2715
2716
2717 u32 tx_frag_cnt[4];
2718
2719
2720 u32 tx_ampdu_cnt;
2721
2722
2723
2724 u32 tx_mpdu_in_ampdu_cnt;
2725};
2726
2727struct wcn36xx_hal_stats_rsp_msg {
2728 struct wcn36xx_hal_msg_header header;
2729
2730
2731 u32 status;
2732
2733
2734 u32 sta_index;
2735
2736
2737 u32 stats_mask;
2738
2739
2740 u16 msg_type;
2741
2742
2743 u16 msg_len;
2744};
2745
2746struct wcn36xx_hal_set_link_state_req_msg {
2747 struct wcn36xx_hal_msg_header header;
2748
2749 u8 bssid[ETH_ALEN];
2750 enum wcn36xx_hal_link_state state;
2751 u8 self_mac_addr[ETH_ALEN];
2752
2753} __packed;
2754
2755struct set_link_state_rsp_msg {
2756 struct wcn36xx_hal_msg_header header;
2757
2758
2759 u32 status;
2760};
2761
2762
2763struct wcn36xx_hal_ts_info_tfc {
2764#ifndef ANI_LITTLE_BIT_ENDIAN
2765 u16 ackPolicy:2;
2766 u16 userPrio:3;
2767 u16 psb:1;
2768 u16 aggregation:1;
2769 u16 accessPolicy:2;
2770 u16 direction:2;
2771 u16 tsid:4;
2772 u16 trafficType:1;
2773#else
2774 u16 trafficType:1;
2775 u16 tsid:4;
2776 u16 direction:2;
2777 u16 accessPolicy:2;
2778 u16 aggregation:1;
2779 u16 psb:1;
2780 u16 userPrio:3;
2781 u16 ackPolicy:2;
2782#endif
2783};
2784
2785
2786struct wcn36xx_hal_ts_info_sch {
2787#ifndef ANI_LITTLE_BIT_ENDIAN
2788 u8 rsvd:7;
2789 u8 schedule:1;
2790#else
2791 u8 schedule:1;
2792 u8 rsvd:7;
2793#endif
2794};
2795
2796
2797struct wcn36xx_hal_ts_info {
2798 struct wcn36xx_hal_ts_info_tfc traffic;
2799 struct wcn36xx_hal_ts_info_sch schedule;
2800};
2801
2802
2803struct wcn36xx_hal_tspec_ie {
2804 u8 type;
2805 u8 length;
2806 struct wcn36xx_hal_ts_info ts_info;
2807 u16 nom_msdu_size;
2808 u16 max_msdu_size;
2809 u32 min_svc_interval;
2810 u32 max_svc_interval;
2811 u32 inact_interval;
2812 u32 suspend_interval;
2813 u32 svc_start_time;
2814 u32 min_data_rate;
2815 u32 mean_data_rate;
2816 u32 peak_data_rate;
2817 u32 max_burst_sz;
2818 u32 delay_bound;
2819 u32 min_phy_rate;
2820 u16 surplus_bw;
2821 u16 medium_time;
2822};
2823
2824struct add_ts_req_msg {
2825 struct wcn36xx_hal_msg_header header;
2826
2827
2828 u16 sta_index;
2829
2830
2831 u16 tspec_index;
2832
2833
2834 struct wcn36xx_hal_tspec_ie tspec;
2835
2836
2837
2838
2839 u8 uapsd;
2840
2841
2842
2843
2844 u32 service_interval[WCN36XX_HAL_MAX_AC];
2845
2846
2847 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
2848
2849
2850 u32 delay_interval[WCN36XX_HAL_MAX_AC];
2851};
2852
2853struct add_rs_rsp_msg {
2854 struct wcn36xx_hal_msg_header header;
2855
2856
2857 u32 status;
2858};
2859
2860struct del_ts_req_msg {
2861 struct wcn36xx_hal_msg_header header;
2862
2863
2864 u16 sta_index;
2865
2866
2867 u16 tspec_index;
2868
2869
2870 u8 bssid[ETH_ALEN];
2871};
2872
2873struct del_ts_rsp_msg {
2874 struct wcn36xx_hal_msg_header header;
2875
2876
2877 u32 status;
2878};
2879
2880
2881
2882
2883
2884struct wcn36xx_hal_add_ba_session_req_msg {
2885 struct wcn36xx_hal_msg_header header;
2886
2887
2888 u16 sta_index;
2889
2890
2891 u8 mac_addr[ETH_ALEN];
2892
2893
2894
2895 u8 dialog_token;
2896
2897
2898
2899 u8 tid;
2900
2901
2902
2903 u8 policy;
2904
2905
2906
2907
2908
2909
2910
2911 u16 buffer_size;
2912
2913
2914 u16 timeout;
2915
2916
2917
2918
2919 u16 ssn;
2920
2921
2922
2923
2924 u8 direction;
2925} __packed;
2926
2927struct wcn36xx_hal_add_ba_session_rsp_msg {
2928 struct wcn36xx_hal_msg_header header;
2929
2930
2931 u32 status;
2932
2933
2934 u8 dialog_token;
2935
2936
2937 u8 ba_tid;
2938
2939
2940 u8 ba_buffer_size;
2941
2942 u8 ba_session_id;
2943
2944
2945 u8 win_size;
2946
2947
2948 u8 sta_index;
2949
2950
2951 u16 ssn;
2952} __packed;
2953
2954struct wcn36xx_hal_add_ba_req_msg {
2955 struct wcn36xx_hal_msg_header header;
2956
2957
2958 u8 session_id;
2959
2960
2961 u8 win_size;
2962
2963#ifdef FEATURE_ON_CHIP_REORDERING
2964 u8 reordering_done_on_chip;
2965#endif
2966} __packed;
2967
2968struct wcn36xx_hal_add_ba_rsp_msg {
2969 struct wcn36xx_hal_msg_header header;
2970
2971
2972 u32 status;
2973
2974
2975 u8 dialog_token;
2976} __packed;
2977
2978struct add_ba_info {
2979 u16 ba_enable:1;
2980 u16 starting_seq_num:12;
2981 u16 reserved:3;
2982};
2983
2984struct wcn36xx_hal_trigger_ba_rsp_candidate {
2985 u8 sta_addr[ETH_ALEN];
2986 struct add_ba_info ba_info[STACFG_MAX_TC];
2987} __packed;
2988
2989struct wcn36xx_hal_trigger_ba_req_candidate {
2990 u8 sta_index;
2991 u8 tid_bitmap;
2992} __packed;
2993
2994struct wcn36xx_hal_trigger_ba_req_msg {
2995 struct wcn36xx_hal_msg_header header;
2996
2997
2998 u8 session_id;
2999
3000
3001
3002
3003 u16 candidate_cnt;
3004
3005} __packed;
3006
3007struct wcn36xx_hal_trigger_ba_rsp_msg {
3008 struct wcn36xx_hal_msg_header header;
3009
3010
3011 u8 bssid[ETH_ALEN];
3012
3013
3014 u32 status;
3015
3016
3017
3018
3019 u16 candidate_cnt;
3020} __packed;
3021
3022struct wcn36xx_hal_del_ba_req_msg {
3023 struct wcn36xx_hal_msg_header header;
3024
3025
3026 u16 sta_index;
3027
3028
3029 u8 tid;
3030
3031
3032
3033
3034 u8 direction;
3035} __packed;
3036
3037struct wcn36xx_hal_del_ba_rsp_msg {
3038 struct wcn36xx_hal_msg_header header;
3039
3040
3041 u32 status;
3042} __packed;
3043
3044struct tsm_stats_req_msg {
3045 struct wcn36xx_hal_msg_header header;
3046
3047
3048 u8 tid;
3049
3050 u8 bssid[ETH_ALEN];
3051};
3052
3053struct tsm_stats_rsp_msg {
3054 struct wcn36xx_hal_msg_header header;
3055
3056
3057 u32 status;
3058
3059
3060 u16 uplink_pkt_queue_delay;
3061
3062
3063 u16 uplink_pkt_queue_delay_hist[4];
3064
3065
3066 u32 uplink_pkt_tx_delay;
3067
3068
3069 u16 uplink_pkt_loss;
3070
3071
3072 u16 uplink_pkt_count;
3073
3074
3075 u8 roaming_count;
3076
3077
3078 u16 roaming_delay;
3079};
3080
3081struct set_key_done_msg {
3082 struct wcn36xx_hal_msg_header header;
3083
3084
3085 u8 bssidx;
3086 u8 enc_type;
3087};
3088
3089struct wcn36xx_hal_nv_img_download_req_msg {
3090
3091
3092
3093
3094 struct wcn36xx_hal_msg_header header;
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104 u16 frag_number;
3105
3106
3107
3108
3109
3110
3111 u16 last_fragment;
3112
3113
3114 u32 nv_img_buffer_size;
3115
3116
3117
3118
3119} __packed;
3120
3121struct wcn36xx_hal_nv_img_download_rsp_msg {
3122 struct wcn36xx_hal_msg_header header;
3123
3124
3125
3126 u32 status;
3127} __packed;
3128
3129struct wcn36xx_hal_nv_store_ind {
3130
3131
3132 struct wcn36xx_hal_msg_header header;
3133
3134
3135 u32 table_id;
3136
3137
3138 u32 nv_blob_size;
3139
3140
3141
3142};
3143
3144
3145
3146#define WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE 6
3147
3148
3149
3150
3151struct mic_failure_ind_msg {
3152 struct wcn36xx_hal_msg_header header;
3153
3154 u8 bssid[ETH_ALEN];
3155
3156
3157 u8 src_addr[ETH_ALEN];
3158
3159
3160 u8 ta_addr[ETH_ALEN];
3161
3162 u8 dst_addr[ETH_ALEN];
3163
3164 u8 multicast;
3165
3166
3167 u8 iv1;
3168
3169
3170 u8 key_id;
3171
3172
3173 u8 tsc[WCN36XX_HAL_CIPHER_SEQ_CTR_SIZE];
3174
3175
3176 u8 rx_addr[ETH_ALEN];
3177};
3178
3179struct update_vht_op_mode_req_msg {
3180 struct wcn36xx_hal_msg_header header;
3181
3182 u16 op_mode;
3183 u16 sta_id;
3184};
3185
3186struct update_vht_op_mode_params_rsp_msg {
3187 struct wcn36xx_hal_msg_header header;
3188
3189 u32 status;
3190};
3191
3192struct update_beacon_req_msg {
3193 struct wcn36xx_hal_msg_header header;
3194
3195 u8 bss_index;
3196
3197
3198
3199 u8 short_preamble;
3200
3201
3202 u8 short_slot_time;
3203
3204
3205 u16 beacon_interval;
3206
3207
3208 u8 lla_coexist;
3209 u8 llb_coexist;
3210 u8 llg_coexist;
3211 u8 ht20_coexist;
3212 u8 lln_non_gf_coexist;
3213 u8 lsig_tx_op_protection_full_support;
3214 u8 rifs_mode;
3215
3216 u16 param_change_bitmap;
3217};
3218
3219struct update_beacon_rsp_msg {
3220 struct wcn36xx_hal_msg_header header;
3221 u32 status;
3222};
3223
3224struct wcn36xx_hal_send_beacon_req_msg {
3225 struct wcn36xx_hal_msg_header header;
3226
3227
3228 u32 beacon_length6;
3229
3230
3231 u32 beacon_length;
3232
3233
3234 u8 beacon[BEACON_TEMPLATE_SIZE - sizeof(u32)];
3235
3236 u8 bssid[ETH_ALEN];
3237
3238
3239 u32 tim_ie_offset;
3240
3241
3242 u16 p2p_ie_offset;
3243} __packed;
3244
3245struct send_beacon_rsp_msg {
3246 struct wcn36xx_hal_msg_header header;
3247 u32 status;
3248} __packed;
3249
3250struct enable_radar_req_msg {
3251 struct wcn36xx_hal_msg_header header;
3252
3253 u8 bssid[ETH_ALEN];
3254 u8 channel;
3255};
3256
3257struct enable_radar_rsp_msg {
3258 struct wcn36xx_hal_msg_header header;
3259
3260
3261 u8 bssid[ETH_ALEN];
3262
3263
3264 u32 status;
3265};
3266
3267struct radar_detect_intr_ind_msg {
3268 struct wcn36xx_hal_msg_header header;
3269
3270 u8 radar_det_channel;
3271};
3272
3273struct radar_detect_ind_msg {
3274 struct wcn36xx_hal_msg_header header;
3275
3276
3277 u8 channel_number;
3278
3279
3280 u16 radar_pulse_width;
3281
3282
3283 u16 num_radar_pulse;
3284};
3285
3286struct wcn36xx_hal_get_tpc_report_req_msg {
3287 struct wcn36xx_hal_msg_header header;
3288
3289 u8 sta[ETH_ALEN];
3290 u8 dialog_token;
3291 u8 txpower;
3292};
3293
3294struct wcn36xx_hal_get_tpc_report_rsp_msg {
3295 struct wcn36xx_hal_msg_header header;
3296
3297
3298 u32 status;
3299};
3300
3301struct wcn36xx_hal_send_probe_resp_req_msg {
3302 struct wcn36xx_hal_msg_header header;
3303
3304 u8 probe_resp_template[BEACON_TEMPLATE_SIZE];
3305 u32 probe_resp_template_len;
3306 u32 proxy_probe_req_valid_ie_bmap[8];
3307 u8 bssid[ETH_ALEN];
3308};
3309
3310struct send_probe_resp_rsp_msg {
3311 struct wcn36xx_hal_msg_header header;
3312
3313
3314 u32 status;
3315};
3316
3317struct send_unknown_frame_rx_ind_msg {
3318 struct wcn36xx_hal_msg_header header;
3319
3320
3321 u32 status;
3322};
3323
3324struct wcn36xx_hal_delete_sta_context_ind_msg {
3325 struct wcn36xx_hal_msg_header header;
3326
3327 u16 aid;
3328 u16 sta_id;
3329
3330
3331 u8 bssid[ETH_ALEN];
3332
3333
3334 u8 addr2[ETH_ALEN];
3335
3336
3337 u16 reason_code;
3338} __packed;
3339
3340struct indicate_del_sta {
3341 struct wcn36xx_hal_msg_header header;
3342 u8 aid;
3343 u8 sta_index;
3344 u8 bss_index;
3345 u8 reason_code;
3346 u32 status;
3347};
3348
3349struct bt_amp_event_msg {
3350 struct wcn36xx_hal_msg_header header;
3351
3352 enum bt_amp_event_type btAmpEventType;
3353};
3354
3355struct bt_amp_event_rsp {
3356 struct wcn36xx_hal_msg_header header;
3357
3358
3359 u32 status;
3360};
3361
3362struct tl_hal_flush_ac_req_msg {
3363 struct wcn36xx_hal_msg_header header;
3364
3365
3366 u8 sta_id;
3367
3368
3369 u8 tid;
3370};
3371
3372struct tl_hal_flush_ac_rsp_msg {
3373 struct wcn36xx_hal_msg_header header;
3374
3375
3376 u8 sta_id;
3377
3378
3379 u8 tid;
3380
3381
3382 u32 status;
3383};
3384
3385struct wcn36xx_hal_enter_imps_req_msg {
3386 struct wcn36xx_hal_msg_header header;
3387};
3388
3389struct wcn36xx_hal_exit_imps_req {
3390 struct wcn36xx_hal_msg_header header;
3391};
3392
3393struct wcn36xx_hal_enter_bmps_req_msg {
3394 struct wcn36xx_hal_msg_header header;
3395
3396 u8 bss_index;
3397
3398
3399#ifndef BUILD_QWPTTSTATIC
3400 u64 tbtt;
3401#endif
3402 u8 dtim_count;
3403
3404
3405
3406 u8 dtim_period;
3407
3408
3409 u32 rssi_filter_period;
3410
3411 u32 num_beacon_per_rssi_average;
3412 u8 rssi_filter_enable;
3413} __packed;
3414
3415struct wcn36xx_hal_exit_bmps_req_msg {
3416 struct wcn36xx_hal_msg_header header;
3417
3418 u8 send_data_null;
3419 u8 bss_index;
3420} __packed;
3421
3422struct wcn36xx_hal_missed_beacon_ind_msg {
3423 struct wcn36xx_hal_msg_header header;
3424
3425 u8 bss_index;
3426} __packed;
3427
3428
3429
3430
3431
3432
3433struct beacon_filter_ie {
3434 u8 element_id;
3435 u8 check_ie_presence;
3436 u8 offset;
3437 u8 value;
3438 u8 bitmask;
3439 u8 ref;
3440};
3441
3442struct wcn36xx_hal_add_bcn_filter_req_msg {
3443 struct wcn36xx_hal_msg_header header;
3444
3445 u16 capability_info;
3446 u16 capability_mask;
3447 u16 beacon_interval;
3448 u16 ie_num;
3449 u8 bss_index;
3450 u8 reserved;
3451};
3452
3453struct wcn36xx_hal_rem_bcn_filter_req {
3454 struct wcn36xx_hal_msg_header header;
3455
3456 u8 ie_Count;
3457 u8 rem_ie_id[1];
3458};
3459
3460#define WCN36XX_HAL_IPV4_ARP_REPLY_OFFLOAD 0
3461#define WCN36XX_HAL_IPV6_NEIGHBOR_DISCOVERY_OFFLOAD 1
3462#define WCN36XX_HAL_IPV6_NS_OFFLOAD 2
3463#define WCN36XX_HAL_IPV6_ADDR_LEN 16
3464#define WCN36XX_HAL_OFFLOAD_DISABLE 0
3465#define WCN36XX_HAL_OFFLOAD_ENABLE 1
3466#define WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE 0x2
3467#define WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE 0x4
3468#define WCN36XX_HAL_OFFLOAD_NS_AND_MCAST_FILTER_ENABLE \
3469 (WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_MCAST_FILTER_ENABLE)
3470#define WCN36XX_HAL_OFFLOAD_ARP_AND_BCAST_FILTER_ENABLE \
3471 (WCN36XX_HAL_OFFLOAD_ENABLE | WCN36XX_HAL_OFFLOAD_BCAST_FILTER_ENABLE)
3472#define WCN36XX_HAL_IPV6_OFFLOAD_ADDR_MAX 0x02
3473
3474struct wcn36xx_hal_ns_offload_params {
3475 u8 src_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3476 u8 self_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3477
3478
3479 u8 target_ipv6_addr1[WCN36XX_HAL_IPV6_ADDR_LEN];
3480 u8 target_ipv6_addr2[WCN36XX_HAL_IPV6_ADDR_LEN];
3481
3482 u8 self_addr[ETH_ALEN];
3483 u8 src_ipv6_addr_valid:1;
3484 u8 target_ipv6_addr1_valid:1;
3485 u8 target_ipv6_addr2_valid:1;
3486 u8 reserved1:5;
3487
3488
3489 u8 reserved2;
3490
3491
3492 u32 slot_index;
3493 u8 bss_index;
3494} __packed;
3495
3496struct wcn36xx_hal_host_offload_req {
3497 u8 offload_type;
3498
3499
3500 u8 enable;
3501
3502 union {
3503 u8 host_ipv4_addr[4];
3504 u8 host_ipv6_addr[WCN36XX_HAL_IPV6_ADDR_LEN];
3505 } u;
3506} __packed;
3507
3508struct wcn36xx_hal_host_offload_req_msg {
3509 struct wcn36xx_hal_msg_header header;
3510 struct wcn36xx_hal_host_offload_req host_offload_params;
3511 struct wcn36xx_hal_ns_offload_params ns_offload_params;
3512} __packed;
3513
3514
3515#define WCN36XX_HAL_KEEP_ALIVE_NULL_PKT 1
3516#define WCN36XX_HAL_KEEP_ALIVE_UNSOLICIT_ARP_RSP 2
3517
3518
3519#define WCN36XX_HAL_KEEP_ALIVE_DISABLE 0
3520#define WCN36XX_HAL_KEEP_ALIVE_ENABLE 1
3521#define WCN36XX_KEEP_ALIVE_TIME_PERIOD 30
3522
3523
3524struct wcn36xx_hal_keep_alive_req_msg {
3525 struct wcn36xx_hal_msg_header header;
3526
3527 u8 packet_type;
3528 u32 time_period;
3529 u8 host_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3530 u8 dest_ipv4_addr[WCN36XX_HAL_IPV4_ADDR_LEN];
3531 u8 dest_addr[ETH_ALEN];
3532 u8 bss_index;
3533} __packed;
3534
3535struct wcn36xx_hal_rssi_threshold_req_msg {
3536 struct wcn36xx_hal_msg_header header;
3537
3538 s8 threshold1:8;
3539 s8 threshold2:8;
3540 s8 threshold3:8;
3541 u8 thres1_pos_notify:1;
3542 u8 thres1_neg_notify:1;
3543 u8 thres2_pos_notify:1;
3544 u8 thres2_neg_notify:1;
3545 u8 thres3_pos_notify:1;
3546 u8 thres3_neg_notify:1;
3547 u8 reserved10:2;
3548};
3549
3550struct wcn36xx_hal_enter_uapsd_req_msg {
3551 struct wcn36xx_hal_msg_header header;
3552
3553 u8 bk_delivery:1;
3554 u8 be_delivery:1;
3555 u8 vi_delivery:1;
3556 u8 vo_delivery:1;
3557 u8 bk_trigger:1;
3558 u8 be_trigger:1;
3559 u8 vi_trigger:1;
3560 u8 vo_trigger:1;
3561 u8 bss_index;
3562};
3563
3564struct wcn36xx_hal_exit_uapsd_req_msg {
3565 struct wcn36xx_hal_msg_header header;
3566 u8 bss_index;
3567};
3568
3569#define WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE 128
3570#define WCN36XX_HAL_WOWL_BCAST_MAX_NUM_PATTERNS 16
3571
3572struct wcn36xx_hal_wowl_add_bcast_ptrn_req_msg {
3573 struct wcn36xx_hal_msg_header header;
3574
3575
3576 u8 id;
3577
3578
3579
3580 u8 byte_Offset;
3581
3582
3583 u8 size;
3584
3585
3586 u8 pattern[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3587
3588
3589 u8 mask_size;
3590
3591
3592 u8 mask[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3593
3594
3595 u8 extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3596
3597
3598 u8 mask_extra[WCN36XX_HAL_WOWL_BCAST_PATTERN_MAX_SIZE];
3599
3600 u8 bss_index;
3601};
3602
3603struct wcn36xx_hal_wow_del_bcast_ptrn_req_msg {
3604 struct wcn36xx_hal_msg_header header;
3605
3606
3607 u8 id;
3608 u8 bss_index;
3609};
3610
3611struct wcn36xx_hal_wowl_enter_req_msg {
3612 struct wcn36xx_hal_msg_header header;
3613
3614
3615 u8 magic_packet_enable;
3616
3617
3618 u8 magic_pattern[ETH_ALEN];
3619
3620
3621
3622
3623
3624
3625 u8 pattern_filtering_enable;
3626
3627
3628
3629
3630
3631
3632
3633 u8 ucast_pattern_filtering_enable;
3634
3635
3636
3637
3638
3639 u8 wow_channel_switch_receive;
3640
3641
3642
3643
3644
3645 u8 wow_deauth_receive;
3646
3647
3648
3649
3650
3651 u8 wow_disassoc_receive;
3652
3653
3654
3655
3656
3657
3658 u8 wow_max_missed_beacons;
3659
3660
3661
3662
3663
3664
3665 u8 wow_max_sleep;
3666
3667
3668
3669
3670
3671 u8 wow_eap_id_request_enable;
3672
3673
3674
3675
3676 u8 wow_eapol_4way_enable;
3677
3678
3679
3680
3681 u8 wow_net_scan_offload_match;
3682
3683
3684
3685
3686 u8 wow_gtk_rekey_error;
3687
3688
3689
3690 u8 wow_bss_connection_loss;
3691
3692 u8 bss_index;
3693};
3694
3695struct wcn36xx_hal_wowl_exit_req_msg {
3696 struct wcn36xx_hal_msg_header header;
3697
3698 u8 bss_index;
3699};
3700
3701struct wcn36xx_hal_get_rssi_req_msg {
3702 struct wcn36xx_hal_msg_header header;
3703};
3704
3705struct wcn36xx_hal_get_roam_rssi_req_msg {
3706 struct wcn36xx_hal_msg_header header;
3707
3708
3709 u32 sta_id;
3710};
3711
3712struct wcn36xx_hal_set_uapsd_ac_params_req_msg {
3713 struct wcn36xx_hal_msg_header header;
3714
3715
3716 u8 sta_idx;
3717
3718
3719 u8 ac;
3720
3721
3722 u8 up;
3723
3724
3725 u32 service_interval;
3726
3727
3728 u32 suspend_interval;
3729
3730
3731 u32 delay_interval;
3732};
3733
3734struct wcn36xx_hal_configure_rxp_filter_req_msg {
3735 struct wcn36xx_hal_msg_header header;
3736
3737 u8 set_mcst_bcst_filter_setting;
3738 u8 set_mcst_bcst_filter;
3739};
3740
3741struct wcn36xx_hal_enter_imps_rsp_msg {
3742 struct wcn36xx_hal_msg_header header;
3743
3744
3745 u32 status;
3746};
3747
3748struct wcn36xx_hal_exit_imps_rsp_msg {
3749 struct wcn36xx_hal_msg_header header;
3750
3751
3752 u32 status;
3753};
3754
3755struct wcn36xx_hal_enter_bmps_rsp_msg {
3756 struct wcn36xx_hal_msg_header header;
3757
3758
3759 u32 status;
3760
3761 u8 bss_index;
3762} __packed;
3763
3764struct wcn36xx_hal_exit_bmps_rsp_msg {
3765 struct wcn36xx_hal_msg_header header;
3766
3767
3768 u32 status;
3769
3770 u8 bss_index;
3771} __packed;
3772
3773struct wcn36xx_hal_enter_uapsd_rsp_msg {
3774 struct wcn36xx_hal_msg_header header;
3775
3776
3777 u32 status;
3778
3779 u8 bss_index;
3780};
3781
3782struct wcn36xx_hal_exit_uapsd_rsp_msg {
3783 struct wcn36xx_hal_msg_header header;
3784
3785
3786 u32 status;
3787
3788 u8 bss_index;
3789};
3790
3791struct wcn36xx_hal_rssi_notification_ind_msg {
3792 struct wcn36xx_hal_msg_header header;
3793
3794 u32 rssi_thres1_pos_cross:1;
3795 u32 rssi_thres1_neg_cross:1;
3796 u32 rssi_thres2_pos_cross:1;
3797 u32 rssi_thres2_neg_cross:1;
3798 u32 rssi_thres3_pos_cross:1;
3799 u32 rssi_thres3_neg_cross:1;
3800 u32 avg_rssi:8;
3801 u32 reserved:18;
3802
3803};
3804
3805struct wcn36xx_hal_get_rssio_rsp_msg {
3806 struct wcn36xx_hal_msg_header header;
3807
3808
3809 u32 status;
3810 s8 rssi;
3811
3812};
3813
3814struct wcn36xx_hal_get_roam_rssi_rsp_msg {
3815 struct wcn36xx_hal_msg_header header;
3816
3817
3818 u32 status;
3819
3820 u8 sta_id;
3821 s8 rssi;
3822};
3823
3824struct wcn36xx_hal_wowl_enter_rsp_msg {
3825 struct wcn36xx_hal_msg_header header;
3826
3827
3828 u32 status;
3829 u8 bss_index;
3830};
3831
3832struct wcn36xx_hal_wowl_exit_rsp_msg {
3833 struct wcn36xx_hal_msg_header header;
3834
3835
3836 u32 status;
3837 u8 bss_index;
3838};
3839
3840struct wcn36xx_hal_add_bcn_filter_rsp_msg {
3841 struct wcn36xx_hal_msg_header header;
3842
3843
3844 u32 status;
3845};
3846
3847struct wcn36xx_hal_rem_bcn_filter_rsp_msg {
3848 struct wcn36xx_hal_msg_header header;
3849
3850
3851 u32 status;
3852};
3853
3854struct wcn36xx_hal_add_wowl_bcast_ptrn_rsp_msg {
3855 struct wcn36xx_hal_msg_header header;
3856
3857
3858 u32 status;
3859 u8 bss_index;
3860};
3861
3862struct wcn36xx_hal_del_wowl_bcast_ptrn_rsp_msg {
3863 struct wcn36xx_hal_msg_header header;
3864
3865
3866 u32 status;
3867 u8 bss_index;
3868};
3869
3870struct wcn36xx_hal_host_offload_rsp_msg {
3871 struct wcn36xx_hal_msg_header header;
3872
3873
3874 u32 status;
3875};
3876
3877struct wcn36xx_hal_keep_alive_rsp_msg {
3878 struct wcn36xx_hal_msg_header header;
3879
3880
3881 u32 status;
3882};
3883
3884struct wcn36xx_hal_set_rssi_thresh_rsp_msg {
3885 struct wcn36xx_hal_msg_header header;
3886
3887
3888 u32 status;
3889};
3890
3891struct wcn36xx_hal_set_uapsd_ac_params_rsp_msg {
3892 struct wcn36xx_hal_msg_header header;
3893
3894
3895 u32 status;
3896};
3897
3898struct wcn36xx_hal_configure_rxp_filter_rsp_msg {
3899 struct wcn36xx_hal_msg_header header;
3900
3901
3902 u32 status;
3903};
3904
3905struct set_max_tx_pwr_req {
3906 struct wcn36xx_hal_msg_header header;
3907
3908
3909
3910
3911 u8 bssid[ETH_ALEN];
3912
3913 u8 self_addr[ETH_ALEN];
3914
3915
3916 u8 power;
3917};
3918
3919struct set_max_tx_pwr_rsp_msg {
3920 struct wcn36xx_hal_msg_header header;
3921
3922
3923 u8 power;
3924
3925
3926 u32 status;
3927};
3928
3929struct set_tx_pwr_req_msg {
3930 struct wcn36xx_hal_msg_header header;
3931
3932
3933 u32 tx_power;
3934
3935 u8 bss_index;
3936};
3937
3938struct set_tx_pwr_rsp_msg {
3939 struct wcn36xx_hal_msg_header header;
3940
3941
3942 u32 status;
3943};
3944
3945struct get_tx_pwr_req_msg {
3946 struct wcn36xx_hal_msg_header header;
3947
3948 u8 sta_id;
3949};
3950
3951struct get_tx_pwr_rsp_msg {
3952 struct wcn36xx_hal_msg_header header;
3953
3954
3955 u32 status;
3956
3957
3958 u32 tx_power;
3959};
3960
3961struct set_p2p_gonoa_req_msg {
3962 struct wcn36xx_hal_msg_header header;
3963
3964 u8 opp_ps;
3965 u32 ct_window;
3966 u8 count;
3967 u32 duration;
3968 u32 interval;
3969 u32 single_noa_duration;
3970 u8 ps_selection;
3971};
3972
3973struct set_p2p_gonoa_rsp_msg {
3974 struct wcn36xx_hal_msg_header header;
3975
3976
3977 u32 status;
3978};
3979
3980struct wcn36xx_hal_add_sta_self_req {
3981 struct wcn36xx_hal_msg_header header;
3982
3983 u8 self_addr[ETH_ALEN];
3984 u32 status;
3985} __packed;
3986
3987struct wcn36xx_hal_add_sta_self_rsp_msg {
3988 struct wcn36xx_hal_msg_header header;
3989
3990
3991 u32 status;
3992
3993
3994 u8 self_sta_index;
3995
3996
3997 u8 dpu_index;
3998
3999
4000 u8 dpu_signature;
4001} __packed;
4002
4003struct wcn36xx_hal_del_sta_self_req_msg {
4004 struct wcn36xx_hal_msg_header header;
4005
4006 u8 self_addr[ETH_ALEN];
4007} __packed;
4008
4009struct wcn36xx_hal_del_sta_self_rsp_msg {
4010 struct wcn36xx_hal_msg_header header;
4011
4012
4013 u32 status;
4014
4015 u8 self_addr[ETH_ALEN];
4016} __packed;
4017
4018struct aggr_add_ts_req {
4019 struct wcn36xx_hal_msg_header header;
4020
4021
4022 u16 sta_idx;
4023
4024
4025
4026
4027 u16 tspec_index;
4028
4029
4030 struct wcn36xx_hal_tspec_ie tspec[WCN36XX_HAL_MAX_AC];
4031
4032
4033
4034
4035 u8 uapsd;
4036
4037
4038
4039
4040 u32 service_interval[WCN36XX_HAL_MAX_AC];
4041
4042
4043 u32 suspend_interval[WCN36XX_HAL_MAX_AC];
4044
4045
4046 u32 delay_interval[WCN36XX_HAL_MAX_AC];
4047};
4048
4049struct aggr_add_ts_rsp_msg {
4050 struct wcn36xx_hal_msg_header header;
4051
4052
4053 u32 status0;
4054
4055
4056 u32 status1;
4057};
4058
4059struct wcn36xx_hal_configure_apps_cpu_wakeup_state_req_msg {
4060 struct wcn36xx_hal_msg_header header;
4061
4062 u8 is_apps_cpu_awake;
4063};
4064
4065struct wcn36xx_hal_configure_apps_cpu_wakeup_state_rsp_msg {
4066 struct wcn36xx_hal_msg_header header;
4067
4068
4069 u32 status;
4070};
4071
4072struct wcn36xx_hal_dump_cmd_req_msg {
4073 struct wcn36xx_hal_msg_header header;
4074
4075 u32 arg1;
4076 u32 arg2;
4077 u32 arg3;
4078 u32 arg4;
4079 u32 arg5;
4080} __packed;
4081
4082struct wcn36xx_hal_dump_cmd_rsp_msg {
4083 struct wcn36xx_hal_msg_header header;
4084
4085
4086 u32 status;
4087
4088
4089 u32 rsp_length;
4090
4091
4092
4093 u8 rsp_buffer[DUMPCMD_RSP_BUFFER];
4094} __packed;
4095
4096#define WLAN_COEX_IND_DATA_SIZE (4)
4097#define WLAN_COEX_IND_TYPE_DISABLE_HB_MONITOR (0)
4098#define WLAN_COEX_IND_TYPE_ENABLE_HB_MONITOR (1)
4099
4100struct coex_ind_msg {
4101 struct wcn36xx_hal_msg_header header;
4102
4103
4104 u32 type;
4105
4106
4107 u32 data[WLAN_COEX_IND_DATA_SIZE];
4108};
4109
4110struct wcn36xx_hal_tx_compl_ind_msg {
4111 struct wcn36xx_hal_msg_header header;
4112
4113
4114 u32 status;
4115};
4116
4117struct wcn36xx_hal_wlan_host_suspend_ind_msg {
4118 struct wcn36xx_hal_msg_header header;
4119
4120 u32 configured_mcst_bcst_filter_setting;
4121 u32 active_session_count;
4122};
4123
4124struct wcn36xx_hal_wlan_exclude_unencrpted_ind_msg {
4125 struct wcn36xx_hal_msg_header header;
4126
4127 u8 dot11_exclude_unencrypted;
4128 u8 bssid[ETH_ALEN];
4129};
4130
4131struct noa_attr_ind_msg {
4132 struct wcn36xx_hal_msg_header header;
4133
4134 u8 index;
4135 u8 opp_ps_flag;
4136 u16 ctwin;
4137
4138 u16 noa1_interval_count;
4139 u16 bss_index;
4140 u32 noa1_duration;
4141 u32 noa1_interval;
4142 u32 noa1_starttime;
4143
4144 u16 noa2_interval_count;
4145 u16 reserved2;
4146 u32 noa2_duration;
4147 u32 noa2_interval;
4148 u32 noa2_start_time;
4149
4150 u32 status;
4151};
4152
4153struct noa_start_ind_msg {
4154 struct wcn36xx_hal_msg_header header;
4155
4156 u32 status;
4157 u32 bss_index;
4158};
4159
4160struct wcn36xx_hal_wlan_host_resume_req_msg {
4161 struct wcn36xx_hal_msg_header header;
4162
4163 u8 configured_mcst_bcst_filter_setting;
4164};
4165
4166struct wcn36xx_hal_host_resume_rsp_msg {
4167 struct wcn36xx_hal_msg_header header;
4168
4169
4170 u32 status;
4171};
4172
4173struct wcn36xx_hal_del_ba_ind_msg {
4174 struct wcn36xx_hal_msg_header header;
4175
4176 u16 sta_idx;
4177
4178
4179 u8 peer_addr[ETH_ALEN];
4180
4181
4182 u8 ba_tid;
4183
4184
4185
4186
4187
4188 u8 direction;
4189
4190 u32 reason_code;
4191
4192
4193 u8 bssid[ETH_ALEN];
4194};
4195
4196
4197
4198
4199#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS 26
4200
4201
4202#define WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX 60
4203
4204
4205#define WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS 16
4206
4207
4208#define WCN36XX_HAL_PNO_MAX_SCAN_TIMERS 10
4209
4210
4211#define WCN36XX_HAL_PNO_MAX_PROBE_SIZE 450
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222enum pno_mode {
4223 PNO_MODE_IMMEDIATE,
4224 PNO_MODE_ON_SUSPEND,
4225 PNO_MODE_ON_RESUME,
4226 PNO_MODE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4227};
4228
4229
4230enum auth_type {
4231 AUTH_TYPE_ANY = 0,
4232 AUTH_TYPE_OPEN_SYSTEM = 1,
4233
4234
4235 AUTH_TYPE_WPA = 2,
4236 AUTH_TYPE_WPA_PSK = 3,
4237
4238 AUTH_TYPE_RSN = 4,
4239 AUTH_TYPE_RSN_PSK = 5,
4240 AUTH_TYPE_FT_RSN = 6,
4241 AUTH_TYPE_FT_RSN_PSK = 7,
4242 AUTH_TYPE_WAPI_WAI_CERTIFICATE = 8,
4243 AUTH_TYPE_WAPI_WAI_PSK = 9,
4244
4245 AUTH_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4246};
4247
4248
4249enum ed_type {
4250 ED_ANY = 0,
4251 ED_NONE = 1,
4252 ED_WEP = 2,
4253 ED_TKIP = 3,
4254 ED_CCMP = 4,
4255 ED_WPI = 5,
4256
4257 ED_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4258};
4259
4260
4261enum ssid_bcast_type {
4262 BCAST_UNKNOWN = 0,
4263 BCAST_NORMAL = 1,
4264 BCAST_HIDDEN = 2,
4265
4266 BCAST_TYPE_MAX = WCN36XX_HAL_MAX_ENUM_SIZE
4267};
4268
4269
4270struct network_type {
4271
4272 struct wcn36xx_hal_mac_ssid ssid;
4273
4274
4275 enum auth_type authentication;
4276
4277
4278 enum ed_type encryption;
4279
4280
4281
4282 u8 channel_count;
4283 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4284
4285
4286 u8 rssi_threshold;
4287};
4288
4289struct scan_timer {
4290
4291 u32 value;
4292
4293
4294
4295 u32 repeat;
4296
4297
4298
4299
4300};
4301
4302
4303struct scan_timers_type {
4304
4305 u8 count;
4306
4307
4308
4309
4310
4311
4312
4313
4314 struct scan_timer values[WCN36XX_HAL_PNO_MAX_SCAN_TIMERS];
4315};
4316
4317
4318struct set_pref_netw_list_req {
4319 struct wcn36xx_hal_msg_header header;
4320
4321
4322 u32 enable;
4323
4324
4325 enum pno_mode mode;
4326
4327
4328 u32 networks_count;
4329
4330
4331 struct network_type networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
4332
4333
4334 struct scan_timers_type scan_timers;
4335
4336
4337 u16 band_24g_probe_size;
4338 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4339
4340
4341 u16 band_5g_probe_size;
4342 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4343};
4344
4345
4346struct network_type_new {
4347
4348 struct wcn36xx_hal_mac_ssid ssid;
4349
4350
4351 enum auth_type authentication;
4352
4353
4354 enum ed_type encryption;
4355
4356
4357 enum ssid_bcast_type bcast_network_type;
4358
4359
4360
4361 u8 channel_count;
4362 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4363
4364
4365 u8 rssi_threshold;
4366};
4367
4368
4369struct set_pref_netw_list_req_new {
4370 struct wcn36xx_hal_msg_header header;
4371
4372
4373 u32 enable;
4374
4375
4376 enum pno_mode mode;
4377
4378
4379 u32 networks_count;
4380
4381
4382 struct network_type_new networks[WCN36XX_HAL_PNO_MAX_SUPP_NETWORKS];
4383
4384
4385 struct scan_timers_type scan_timers;
4386
4387
4388 u16 band_24g_probe_size;
4389 u8 band_24g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4390
4391
4392 u16 band_5g_probe_size;
4393 u8 band_5g_probe_template[WCN36XX_HAL_PNO_MAX_PROBE_SIZE];
4394};
4395
4396
4397struct set_pref_netw_list_resp {
4398 struct wcn36xx_hal_msg_header header;
4399
4400
4401
4402 u32 status;
4403};
4404
4405
4406struct pref_netw_found_ind {
4407
4408 struct wcn36xx_hal_msg_header header;
4409
4410
4411 struct wcn36xx_hal_mac_ssid ssid;
4412
4413
4414 u8 rssi;
4415};
4416
4417
4418struct set_rssi_filter_req {
4419 struct wcn36xx_hal_msg_header header;
4420
4421
4422 u8 rssi_threshold;
4423};
4424
4425
4426struct set_rssi_filter_resp {
4427 struct wcn36xx_hal_msg_header header;
4428
4429
4430 u32 status;
4431};
4432
4433
4434
4435struct wcn36xx_hal_update_scan_params_req {
4436
4437 struct wcn36xx_hal_msg_header header;
4438
4439
4440 u8 dot11d_enabled;
4441
4442
4443 u8 dot11d_resolved;
4444
4445
4446 u8 channel_count;
4447 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS];
4448
4449
4450 u16 active_min_ch_time;
4451
4452
4453 u16 active_max_ch_time;
4454
4455
4456 u16 passive_min_ch_time;
4457
4458
4459 u16 passive_max_ch_time;
4460
4461
4462 enum phy_chan_bond_state state;
4463} __packed;
4464
4465
4466
4467struct wcn36xx_hal_update_scan_params_req_ex {
4468
4469 struct wcn36xx_hal_msg_header header;
4470
4471
4472 u8 dot11d_enabled;
4473
4474
4475 u8 dot11d_resolved;
4476
4477
4478 u8 channel_count;
4479 u8 channels[WCN36XX_HAL_PNO_MAX_NETW_CHANNELS_EX];
4480
4481
4482 u16 active_min_ch_time;
4483
4484
4485 u16 active_max_ch_time;
4486
4487
4488 u16 passive_min_ch_time;
4489
4490
4491 u16 passive_max_ch_time;
4492
4493
4494 enum phy_chan_bond_state state;
4495} __packed;
4496
4497
4498
4499struct wcn36xx_hal_update_scan_params_resp {
4500
4501 struct wcn36xx_hal_msg_header header;
4502
4503
4504 u32 status;
4505} __packed;
4506
4507struct wcn36xx_hal_set_tx_per_tracking_req_msg {
4508 struct wcn36xx_hal_msg_header header;
4509
4510
4511 u8 tx_per_tracking_enable;
4512
4513
4514 u8 tx_per_tracking_period;
4515
4516
4517 u8 tx_per_tracking_ratio;
4518
4519
4520
4521 u32 tx_per_tracking_watermark;
4522};
4523
4524struct wcn36xx_hal_set_tx_per_tracking_rsp_msg {
4525 struct wcn36xx_hal_msg_header header;
4526
4527
4528 u32 status;
4529
4530};
4531
4532struct tx_per_hit_ind_msg {
4533 struct wcn36xx_hal_msg_header header;
4534};
4535
4536
4537#define WCN36XX_HAL_PROTOCOL_DATA_LEN 8
4538#define WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS 240
4539#define WCN36XX_HAL_MAX_NUM_FILTERS 20
4540#define WCN36XX_HAL_MAX_CMP_PER_FILTER 10
4541
4542enum wcn36xx_hal_receive_packet_filter_type {
4543 HAL_RCV_FILTER_TYPE_INVALID,
4544 HAL_RCV_FILTER_TYPE_FILTER_PKT,
4545 HAL_RCV_FILTER_TYPE_BUFFER_PKT,
4546 HAL_RCV_FILTER_TYPE_MAX_ENUM_SIZE
4547};
4548
4549enum wcn36xx_hal_rcv_pkt_flt_protocol_type {
4550 HAL_FILTER_PROTO_TYPE_INVALID,
4551 HAL_FILTER_PROTO_TYPE_MAC,
4552 HAL_FILTER_PROTO_TYPE_ARP,
4553 HAL_FILTER_PROTO_TYPE_IPV4,
4554 HAL_FILTER_PROTO_TYPE_IPV6,
4555 HAL_FILTER_PROTO_TYPE_UDP,
4556 HAL_FILTER_PROTO_TYPE_MAX
4557};
4558
4559enum wcn36xx_hal_rcv_pkt_flt_cmp_flag_type {
4560 HAL_FILTER_CMP_TYPE_INVALID,
4561 HAL_FILTER_CMP_TYPE_EQUAL,
4562 HAL_FILTER_CMP_TYPE_MASK_EQUAL,
4563 HAL_FILTER_CMP_TYPE_NOT_EQUAL,
4564 HAL_FILTER_CMP_TYPE_MAX
4565};
4566
4567struct wcn36xx_hal_rcv_pkt_filter_params {
4568 u8 protocol_layer;
4569 u8 cmp_flag;
4570
4571
4572 u16 data_length;
4573
4574
4575 u8 data_offset;
4576
4577
4578 u8 reserved;
4579
4580
4581 u8 compare_data[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4582
4583
4584 u8 data_mask[WCN36XX_HAL_PROTOCOL_DATA_LEN];
4585};
4586
4587struct wcn36xx_hal_sessionized_rcv_pkt_filter_cfg_type {
4588 u8 id;
4589 u8 type;
4590 u8 params_count;
4591 u32 coleasce_time;
4592 u8 bss_index;
4593 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4594};
4595
4596struct wcn36xx_hal_set_rcv_pkt_filter_req_msg {
4597 struct wcn36xx_hal_msg_header header;
4598
4599 u8 id;
4600 u8 type;
4601 u8 params_count;
4602 u32 coalesce_time;
4603 struct wcn36xx_hal_rcv_pkt_filter_params params[1];
4604};
4605
4606struct wcn36xx_hal_rcv_flt_mc_addr_list_type {
4607
4608 u8 data_offset;
4609
4610 u32 mc_addr_count;
4611 u8 mc_addr[WCN36XX_HAL_MAX_NUM_MULTICAST_ADDRESS][ETH_ALEN];
4612 u8 bss_index;
4613} __packed;
4614
4615struct wcn36xx_hal_set_pkt_filter_rsp_msg {
4616 struct wcn36xx_hal_msg_header header;
4617
4618
4619 u32 status;
4620
4621 u8 bss_index;
4622};
4623
4624struct wcn36xx_hal_rcv_flt_pkt_match_cnt_req_msg {
4625 struct wcn36xx_hal_msg_header header;
4626
4627 u8 bss_index;
4628};
4629
4630struct wcn36xx_hal_rcv_flt_pkt_match_cnt {
4631 u8 id;
4632 u32 match_cnt;
4633};
4634
4635struct wcn36xx_hal_rcv_flt_pkt_match_cnt_rsp_msg {
4636 struct wcn36xx_hal_msg_header header;
4637
4638
4639 u32 status;
4640
4641 u32 match_count;
4642 struct wcn36xx_hal_rcv_flt_pkt_match_cnt
4643 matches[WCN36XX_HAL_MAX_NUM_FILTERS];
4644 u8 bss_index;
4645};
4646
4647struct wcn36xx_hal_rcv_flt_pkt_clear_param {
4648
4649 u32 status;
4650 u8 id;
4651 u8 bss_index;
4652};
4653
4654struct wcn36xx_hal_rcv_flt_pkt_clear_req_msg {
4655 struct wcn36xx_hal_msg_header header;
4656 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4657};
4658
4659struct wcn36xx_hal_rcv_flt_pkt_clear_rsp_msg {
4660 struct wcn36xx_hal_msg_header header;
4661 struct wcn36xx_hal_rcv_flt_pkt_clear_param param;
4662};
4663
4664struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_req_msg {
4665 struct wcn36xx_hal_msg_header header;
4666 struct wcn36xx_hal_rcv_flt_mc_addr_list_type mc_addr_list;
4667} __packed;
4668
4669struct wcn36xx_hal_rcv_flt_pkt_set_mc_list_rsp_msg {
4670 struct wcn36xx_hal_msg_header header;
4671 u32 status;
4672 u8 bss_index;
4673};
4674
4675
4676
4677struct wcn36xx_hal_set_power_params_req_msg {
4678 struct wcn36xx_hal_msg_header header;
4679
4680
4681 u32 ignore_dtim;
4682
4683
4684 u32 dtim_period;
4685
4686
4687 u32 listen_interval;
4688
4689
4690 u32 bcast_mcast_filter;
4691
4692
4693 u32 enable_bet;
4694
4695
4696 u32 bet_interval;
4697} __packed;
4698
4699struct wcn36xx_hal_set_power_params_resp {
4700
4701 struct wcn36xx_hal_msg_header header;
4702
4703
4704 u32 status;
4705} __packed;
4706
4707
4708
4709enum place_holder_in_cap_bitmap {
4710 MCC = 0,
4711 P2P = 1,