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25#ifndef WMI_H
26#define WMI_H
27
28#include <linux/ieee80211.h>
29
30#include "htc.h"
31
32#define HTC_PROTOCOL_VERSION 0x0002
33#define WMI_PROTOCOL_VERSION 0x0002
34#define WMI_CONTROL_MSG_MAX_LEN 256
35#define is_ethertype(type_or_len) ((type_or_len) >= 0x0600)
36
37#define IP_ETHERTYPE 0x0800
38
39#define WMI_IMPLICIT_PSTREAM 0xFF
40#define WMI_MAX_THINSTREAM 15
41
42#define SSID_IE_LEN_INDEX 13
43
44
45#define SIG_QUALITY_THRESH_LVLS 6
46#define SIG_QUALITY_UPPER_THRESH_LVLS SIG_QUALITY_THRESH_LVLS
47#define SIG_QUALITY_LOWER_THRESH_LVLS SIG_QUALITY_THRESH_LVLS
48
49#define A_BAND_24GHZ 0
50#define A_BAND_5GHZ 1
51#define ATH6KL_NUM_BANDS 2
52
53
54#define WMI_IMPLICIT_PSTREAM_INACTIVITY_INT 5000
55
56
57
58
59
60
61
62
63typedef __s16 __bitwise a_sle16;
64typedef __s32 __bitwise a_sle32;
65
66static inline a_sle32 a_cpu_to_sle32(s32 val)
67{
68 return (__force a_sle32) cpu_to_le32(val);
69}
70
71static inline s32 a_sle32_to_cpu(a_sle32 val)
72{
73 return le32_to_cpu((__force __le32) val);
74}
75
76static inline a_sle16 a_cpu_to_sle16(s16 val)
77{
78 return (__force a_sle16) cpu_to_le16(val);
79}
80
81static inline s16 a_sle16_to_cpu(a_sle16 val)
82{
83 return le16_to_cpu((__force __le16) val);
84}
85
86struct sq_threshold_params {
87 s16 upper_threshold[SIG_QUALITY_UPPER_THRESH_LVLS];
88 s16 lower_threshold[SIG_QUALITY_LOWER_THRESH_LVLS];
89 u32 upper_threshold_valid_count;
90 u32 lower_threshold_valid_count;
91 u32 polling_interval;
92 u8 weight;
93 u8 last_rssi;
94 u8 last_rssi_poll_event;
95};
96
97struct wmi_data_sync_bufs {
98 u8 traffic_class;
99 struct sk_buff *skb;
100};
101
102
103#define WMM_NUM_AC 4
104#define WMM_AC_BE 0
105#define WMM_AC_BK 1
106#define WMM_AC_VI 2
107#define WMM_AC_VO 3
108
109#define WMI_VOICE_USER_PRIORITY 0x7
110
111struct wmi {
112 u16 stream_exist_for_ac[WMM_NUM_AC];
113 u8 fat_pipe_exist;
114 struct ath6kl *parent_dev;
115 u8 pwr_mode;
116
117
118 spinlock_t lock;
119 enum htc_endpoint_id ep_id;
120 struct sq_threshold_params
121 sq_threshld[SIGNAL_QUALITY_METRICS_NUM_MAX];
122 bool is_wmm_enabled;
123 u8 traffic_class;
124 bool is_probe_ssid;
125
126 u8 *last_mgmt_tx_frame;
127 size_t last_mgmt_tx_frame_len;
128 u8 saved_pwr_mode;
129};
130
131struct host_app_area {
132 __le32 wmi_protocol_ver;
133} __packed;
134
135enum wmi_msg_type {
136 DATA_MSGTYPE = 0x0,
137 CNTL_MSGTYPE,
138 SYNC_MSGTYPE,
139 OPT_MSGTYPE,
140};
141
142
143
144
145
146#define WMI_DATA_HDR_MSG_TYPE_MASK 0x03
147#define WMI_DATA_HDR_MSG_TYPE_SHIFT 0
148#define WMI_DATA_HDR_UP_MASK 0x07
149#define WMI_DATA_HDR_UP_SHIFT 2
150
151
152
153
154#define WMI_DATA_HDR_PS_MASK 0x1
155#define WMI_DATA_HDR_PS_SHIFT 5
156
157#define WMI_DATA_HDR_MORE 0x20
158
159enum wmi_data_hdr_data_type {
160 WMI_DATA_HDR_DATA_TYPE_802_3 = 0,
161 WMI_DATA_HDR_DATA_TYPE_802_11,
162
163
164 WMI_DATA_HDR_DATA_TYPE_ACL,
165};
166
167
168enum wmi_data_hdr_flags {
169 WMI_DATA_HDR_FLAGS_MORE = 0x1,
170 WMI_DATA_HDR_FLAGS_EOSP = 0x2,
171 WMI_DATA_HDR_FLAGS_UAPSD = 0x4,
172};
173
174#define WMI_DATA_HDR_DATA_TYPE_MASK 0x3
175#define WMI_DATA_HDR_DATA_TYPE_SHIFT 6
176
177
178#define WMI_DATA_HDR_SEQNO_MASK 0xFFF
179#define WMI_DATA_HDR_SEQNO_SHIFT 0
180
181#define WMI_DATA_HDR_AMSDU_MASK 0x1
182#define WMI_DATA_HDR_AMSDU_SHIFT 12
183
184#define WMI_DATA_HDR_META_MASK 0x7
185#define WMI_DATA_HDR_META_SHIFT 13
186
187#define WMI_DATA_HDR_PAD_BEFORE_DATA_MASK 0xFF
188#define WMI_DATA_HDR_PAD_BEFORE_DATA_SHIFT 0x8
189
190
191#define WMI_DATA_HDR_IF_IDX_MASK 0xF
192
193#define WMI_DATA_HDR_TRIG 0x10
194#define WMI_DATA_HDR_EOSP 0x10
195
196struct wmi_data_hdr {
197 s8 rssi;
198
199
200
201
202
203
204
205
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207
208
209
210 u8 info;
211
212
213
214
215
216
217
218
219 __le16 info2;
220
221
222
223
224
225
226
227 __le16 info3;
228} __packed;
229
230static inline u8 wmi_data_hdr_get_up(struct wmi_data_hdr *dhdr)
231{
232 return (dhdr->info >> WMI_DATA_HDR_UP_SHIFT) & WMI_DATA_HDR_UP_MASK;
233}
234
235static inline void wmi_data_hdr_set_up(struct wmi_data_hdr *dhdr,
236 u8 usr_pri)
237{
238 dhdr->info &= ~(WMI_DATA_HDR_UP_MASK << WMI_DATA_HDR_UP_SHIFT);
239 dhdr->info |= usr_pri << WMI_DATA_HDR_UP_SHIFT;
240}
241
242static inline u8 wmi_data_hdr_get_dot11(struct wmi_data_hdr *dhdr)
243{
244 u8 data_type;
245
246 data_type = (dhdr->info >> WMI_DATA_HDR_DATA_TYPE_SHIFT) &
247 WMI_DATA_HDR_DATA_TYPE_MASK;
248 return (data_type == WMI_DATA_HDR_DATA_TYPE_802_11);
249}
250
251static inline u16 wmi_data_hdr_get_seqno(struct wmi_data_hdr *dhdr)
252{
253 return (le16_to_cpu(dhdr->info2) >> WMI_DATA_HDR_SEQNO_SHIFT) &
254 WMI_DATA_HDR_SEQNO_MASK;
255}
256
257static inline u8 wmi_data_hdr_is_amsdu(struct wmi_data_hdr *dhdr)
258{
259 return (le16_to_cpu(dhdr->info2) >> WMI_DATA_HDR_AMSDU_SHIFT) &
260 WMI_DATA_HDR_AMSDU_MASK;
261}
262
263static inline u8 wmi_data_hdr_get_meta(struct wmi_data_hdr *dhdr)
264{
265 return (le16_to_cpu(dhdr->info2) >> WMI_DATA_HDR_META_SHIFT) &
266 WMI_DATA_HDR_META_MASK;
267}
268
269static inline u8 wmi_data_hdr_get_if_idx(struct wmi_data_hdr *dhdr)
270{
271 return le16_to_cpu(dhdr->info3) & WMI_DATA_HDR_IF_IDX_MASK;
272}
273
274
275#define WMI_MAX_TX_META_SZ 12
276#define WMI_META_VERSION_1 0x01
277#define WMI_META_VERSION_2 0x02
278
279
280#define WMI_META_V2_FLAG_CSUM_OFFLOAD 0x01
281
282struct wmi_tx_meta_v1 {
283
284 u8 pkt_id;
285
286
287 u8 rate_plcy_id;
288} __packed;
289
290struct wmi_tx_meta_v2 {
291
292
293
294
295 u8 csum_start;
296
297
298 u8 csum_dest;
299
300
301 u8 csum_flags;
302} __packed;
303
304struct wmi_rx_meta_v1 {
305 u8 status;
306
307
308 u8 rix;
309
310
311 u8 rssi;
312
313
314 u8 channel;
315
316 __le16 flags;
317} __packed;
318
319struct wmi_rx_meta_v2 {
320 __le16 csum;
321
322
323 u8 csum_flags;
324} __packed;
325
326#define WMI_CMD_HDR_IF_ID_MASK 0xF
327
328
329struct wmi_cmd_hdr {
330 __le16 cmd_id;
331
332
333
334
335 __le16 info1;
336
337