1
2
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4
5
6#include <linux/module.h>
7#include <linux/msi.h>
8#include <linux/pci.h>
9
10#include "pci.h"
11#include "core.h"
12#include "hif.h"
13#include "mhi.h"
14#include "debug.h"
15
16#define ATH11K_PCI_BAR_NUM 0
17#define ATH11K_PCI_DMA_MASK 32
18
19#define ATH11K_PCI_IRQ_CE0_OFFSET 3
20
21#define WINDOW_ENABLE_BIT 0x40000000
22#define WINDOW_REG_ADDRESS 0x310c
23#define WINDOW_VALUE_MASK GENMASK(24, 19)
24#define WINDOW_START 0x80000
25#define WINDOW_RANGE_MASK GENMASK(18, 0)
26
27#define TCSR_SOC_HW_VERSION 0x0224
28#define TCSR_SOC_HW_VERSION_MAJOR_MASK GENMASK(16, 8)
29#define TCSR_SOC_HW_VERSION_MINOR_MASK GENMASK(7, 0)
30
31
32
33
34
35#define ACCESS_ALWAYS_OFF 0xFE0
36
37#define QCA6390_DEVICE_ID 0x1101
38#define QCN9074_DEVICE_ID 0x1104
39#define WCN6855_DEVICE_ID 0x1103
40
41static const struct pci_device_id ath11k_pci_id_table[] = {
42 { PCI_VDEVICE(QCOM, QCA6390_DEVICE_ID) },
43 { PCI_VDEVICE(QCOM, WCN6855_DEVICE_ID) },
44 { PCI_VDEVICE(QCOM, QCN9074_DEVICE_ID) },
45 {0}
46};
47
48MODULE_DEVICE_TABLE(pci, ath11k_pci_id_table);
49
50static const struct ath11k_bus_params ath11k_pci_bus_params = {
51 .mhi_support = true,
52 .m3_fw_support = true,
53 .fixed_bdf_addr = false,
54 .fixed_mem_region = false,
55};
56
57static const struct ath11k_msi_config ath11k_msi_config[] = {
58 {
59 .total_vectors = 32,
60 .total_users = 4,
61 .users = (struct ath11k_msi_user[]) {
62 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
63 { .name = "CE", .num_vectors = 10, .base_vector = 3 },
64 { .name = "WAKE", .num_vectors = 1, .base_vector = 13 },
65 { .name = "DP", .num_vectors = 18, .base_vector = 14 },
66 },
67 },
68 {
69 .total_vectors = 16,
70 .total_users = 3,
71 .users = (struct ath11k_msi_user[]) {
72 { .name = "MHI", .num_vectors = 3, .base_vector = 0 },
73 { .name = "CE", .num_vectors = 5, .base_vector = 3 },
74 { .name = "DP", .num_vectors = 8, .base_vector = 8 },
75 },
76 },
77};
78
79static const char *irq_name[ATH11K_IRQ_NUM_MAX] = {
80 "bhi",
81 "mhi-er0",
82 "mhi-er1",
83 "ce0",
84 "ce1",
85 "ce2",
86 "ce3",
87 "ce4",
88 "ce5",
89 "ce6",
90 "ce7",
91 "ce8",
92 "ce9",
93 "ce10",
94 "ce11",
95 "host2wbm-desc-feed",
96 "host2reo-re-injection",
97 "host2reo-command",
98 "host2rxdma-monitor-ring3",
99 "host2rxdma-monitor-ring2",
100 "host2rxdma-monitor-ring1",
101 "reo2ost-exception",
102 "wbm2host-rx-release",
103 "reo2host-status",
104 "reo2host-destination-ring4",
105 "reo2host-destination-ring3",
106 "reo2host-destination-ring2",
107 "reo2host-destination-ring1",
108 "rxdma2host-monitor-destination-mac3",
109 "rxdma2host-monitor-destination-mac2",
110 "rxdma2host-monitor-destination-mac1",
111 "ppdu-end-interrupts-mac3",
112 "ppdu-end-interrupts-mac2",
113 "ppdu-end-interrupts-mac1",
114 "rxdma2host-monitor-status-ring-mac3",
115 "rxdma2host-monitor-status-ring-mac2",
116 "rxdma2host-monitor-status-ring-mac1",
117 "host2rxdma-host-buf-ring-mac3",
118 "host2rxdma-host-buf-ring-mac2",
119 "host2rxdma-host-buf-ring-mac1",
120 "rxdma2host-destination-ring-mac3",
121 "rxdma2host-destination-ring-mac2",
122 "rxdma2host-destination-ring-mac1",
123 "host2tcl-input-ring4",
124 "host2tcl-input-ring3",
125 "host2tcl-input-ring2",
126 "host2tcl-input-ring1",
127 "wbm2host-tx-completions-ring3",
128 "wbm2host-tx-completions-ring2",
129 "wbm2host-tx-completions-ring1",
130 "tcl2host-status-ring",
131};
132
133static inline void ath11k_pci_select_window(struct ath11k_pci *ab_pci, u32 offset)
134{
135 struct ath11k_base *ab = ab_pci->ab;
136
137 u32 window = FIELD_GET(WINDOW_VALUE_MASK, offset);
138
139 lockdep_assert_held(&ab_pci->window_lock);
140
141 if (window != ab_pci->register_window) {
142 iowrite32(WINDOW_ENABLE_BIT | window,
143 ab->mem + WINDOW_REG_ADDRESS);
144 ioread32(ab->mem + WINDOW_REG_ADDRESS);
145 ab_pci->register_window = window;
146 }
147}
148
149static inline void ath11k_pci_select_static_window(struct ath11k_pci *ab_pci)
150{
151 u32 umac_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_SEQ_WCSS_UMAC_OFFSET);
152 u32 ce_window = FIELD_GET(WINDOW_VALUE_MASK, HAL_CE_WFSS_CE_REG_BASE);
153 u32 window;
154
155 window = (umac_window << 12) | (ce_window << 6);
156
157 iowrite32(WINDOW_ENABLE_BIT | window, ab_pci->ab->mem + WINDOW_REG_ADDRESS);
158}
159
160static inline u32 ath11k_pci_get_window_start(struct ath11k_base *ab,
161 u32 offset)
162{
163 u32 window_start;
164
165
166 if ((offset ^ HAL_SEQ_WCSS_UMAC_OFFSET) < WINDOW_RANGE_MASK)
167 window_start = 3 * WINDOW_START;
168
169 else if ((offset ^ HAL_CE_WFSS_CE_REG_BASE) < WINDOW_RANGE_MASK)
170 window_start = 2 * WINDOW_START;
171 else
172 window_start = WINDOW_START;
173
174 return window_start;
175}
176
177void ath11k_pci_write32(struct ath11k_base *ab, u32 offset, u32 value)
178{
179 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
180 u32 window_start;
181
182
183
184
185 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
186 offset >= ACCESS_ALWAYS_OFF)
187 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
188
189 if (offset < WINDOW_START) {
190 iowrite32(value, ab->mem + offset);
191 } else {
192 if (ab->bus_params.static_window_map)
193 window_start = ath11k_pci_get_window_start(ab, offset);
194 else
195 window_start = WINDOW_START;
196
197 if (window_start == WINDOW_START) {
198 spin_lock_bh(&ab_pci->window_lock);
199 ath11k_pci_select_window(ab_pci, offset);
200 iowrite32(value, ab->mem + window_start +
201 (offset & WINDOW_RANGE_MASK));
202 spin_unlock_bh(&ab_pci->window_lock);
203 } else {
204 iowrite32(value, ab->mem + window_start +
205 (offset & WINDOW_RANGE_MASK));
206 }
207 }
208
209 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
210 offset >= ACCESS_ALWAYS_OFF)
211 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
212}
213
214u32 ath11k_pci_read32(struct ath11k_base *ab, u32 offset)
215{
216 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
217 u32 val, window_start;
218
219
220
221
222 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
223 offset >= ACCESS_ALWAYS_OFF)
224 mhi_device_get_sync(ab_pci->mhi_ctrl->mhi_dev);
225
226 if (offset < WINDOW_START) {
227 val = ioread32(ab->mem + offset);
228 } else {
229 if (ab->bus_params.static_window_map)
230 window_start = ath11k_pci_get_window_start(ab, offset);
231 else
232 window_start = WINDOW_START;
233
234 if (window_start == WINDOW_START) {
235 spin_lock_bh(&ab_pci->window_lock);
236 ath11k_pci_select_window(ab_pci, offset);
237 val = ioread32(ab->mem + window_start +
238 (offset & WINDOW_RANGE_MASK));
239 spin_unlock_bh(&ab_pci->window_lock);
240 } else {
241 val = ioread32(ab->mem + window_start +
242 (offset & WINDOW_RANGE_MASK));
243 }
244 }
245
246 if (test_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags) &&
247 offset >= ACCESS_ALWAYS_OFF)
248 mhi_device_put(ab_pci->mhi_ctrl->mhi_dev);
249
250 return val;
251}
252
253static void ath11k_pci_soc_global_reset(struct ath11k_base *ab)
254{
255 u32 val, delay;
256
257 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
258
259 val |= PCIE_SOC_GLOBAL_RESET_V;
260
261 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
262
263
264 delay = 10;
265 mdelay(delay);
266
267
268 val &= ~PCIE_SOC_GLOBAL_RESET_V;
269
270 ath11k_pci_write32(ab, PCIE_SOC_GLOBAL_RESET, val);
271
272 mdelay(delay);
273
274 val = ath11k_pci_read32(ab, PCIE_SOC_GLOBAL_RESET);
275 if (val == 0xffffffff)
276 ath11k_warn(ab, "link down error during global reset\n");
277}
278
279static void ath11k_pci_clear_dbg_registers(struct ath11k_base *ab)
280{
281 u32 val;
282
283
284 val = ath11k_pci_read32(ab, PCIE_Q6_COOKIE_ADDR);
285 ath11k_dbg(ab, ATH11K_DBG_PCI, "cookie:0x%x\n", val);
286
287 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
288 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
289
290
291 mdelay(10);
292
293
294
295
296 ath11k_pci_write32(ab, WLAON_WARM_SW_ENTRY, 0);
297 mdelay(10);
298
299 val = ath11k_pci_read32(ab, WLAON_WARM_SW_ENTRY);
300 ath11k_dbg(ab, ATH11K_DBG_PCI, "WLAON_WARM_SW_ENTRY 0x%x\n", val);
301
302
303
304
305 val = ath11k_pci_read32(ab, WLAON_SOC_RESET_CAUSE_REG);
306 ath11k_dbg(ab, ATH11K_DBG_PCI, "soc reset cause:%d\n", val);
307}
308
309static int ath11k_pci_set_link_reg(struct ath11k_base *ab,
310 u32 offset, u32 value, u32 mask)
311{
312 u32 v;
313 int i;
314
315 v = ath11k_pci_read32(ab, offset);
316 if ((v & mask) == value)
317 return 0;
318
319 for (i = 0; i < 10; i++) {
320 ath11k_pci_write32(ab, offset, (v & ~mask) | value);
321
322 v = ath11k_pci_read32(ab, offset);
323 if ((v & mask) == value)
324 return 0;
325
326 mdelay(2);
327 }
328
329 ath11k_warn(ab, "failed to set pcie link register 0x%08x: 0x%08x != 0x%08x\n",
330 offset, v & mask, value);
331
332 return -ETIMEDOUT;
333}
334
335static int ath11k_pci_fix_l1ss(struct ath11k_base *ab)
336{
337 int ret;
338
339 ret = ath11k_pci_set_link_reg(ab,
340 PCIE_QSERDES_COM_SYSCLK_EN_SEL_REG(ab),
341 PCIE_QSERDES_COM_SYSCLK_EN_SEL_VAL,
342 PCIE_QSERDES_COM_SYSCLK_EN_SEL_MSK);
343 if (ret) {
344 ath11k_warn(ab, "failed to set sysclk: %d\n", ret);
345 return ret;
346 }
347
348 ret = ath11k_pci_set_link_reg(ab,
349 PCIE_PCS_OSC_DTCT_CONFIG1_REG(ab),
350 PCIE_PCS_OSC_DTCT_CONFIG1_VAL,
351 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
352 if (ret) {
353 ath11k_warn(ab, "failed to set dtct config1 error: %d\n", ret);
354 return ret;
355 }
356
357 ret = ath11k_pci_set_link_reg(ab,
358 PCIE_PCS_OSC_DTCT_CONFIG2_REG(ab),
359 PCIE_PCS_OSC_DTCT_CONFIG2_VAL,
360 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
361 if (ret) {
362 ath11k_warn(ab, "failed to set dtct config2: %d\n", ret);
363 return ret;
364 }
365
366 ret = ath11k_pci_set_link_reg(ab,
367 PCIE_PCS_OSC_DTCT_CONFIG4_REG(ab),
368 PCIE_PCS_OSC_DTCT_CONFIG4_VAL,
369 PCIE_PCS_OSC_DTCT_CONFIG_MSK);
370 if (ret) {
371 ath11k_warn(ab, "failed to set dtct config4: %d\n", ret);
372 return ret;
373 }
374
375 return 0;
376}
377
378static void ath11k_pci_enable_ltssm(struct ath11k_base *ab)
379{
380 u32 val;
381 int i;
382
383 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
384
385
386 for (i = 0; val != PARM_LTSSM_VALUE && i < 5; i++) {
387 if (val == 0xffffffff)
388 mdelay(5);
389
390 ath11k_pci_write32(ab, PCIE_PCIE_PARF_LTSSM, PARM_LTSSM_VALUE);
391 val = ath11k_pci_read32(ab, PCIE_PCIE_PARF_LTSSM);
392 }
393
394 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci ltssm 0x%x\n", val);
395
396 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
397 val |= GCC_GCC_PCIE_HOT_RST_VAL;
398 ath11k_pci_write32(ab, GCC_GCC_PCIE_HOT_RST, val);
399 val = ath11k_pci_read32(ab, GCC_GCC_PCIE_HOT_RST);
400
401 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci pcie_hot_rst 0x%x\n", val);
402
403 mdelay(5);
404}
405
406static void ath11k_pci_clear_all_intrs(struct ath11k_base *ab)
407{
408
409
410
411
412
413 ath11k_pci_write32(ab, PCIE_PCIE_INT_ALL_CLEAR, PCIE_INT_CLEAR_ALL);
414}
415
416static void ath11k_pci_set_wlaon_pwr_ctrl(struct ath11k_base *ab)
417{
418 u32 val;
419
420 val = ath11k_pci_read32(ab, WLAON_QFPROM_PWR_CTRL_REG);
421 val &= ~QFPROM_PWR_CTRL_VDD4BLOW_MASK;
422 ath11k_pci_write32(ab, WLAON_QFPROM_PWR_CTRL_REG, val);
423}
424
425static void ath11k_pci_force_wake(struct ath11k_base *ab)
426{
427 ath11k_pci_write32(ab, PCIE_SOC_WAKE_PCIE_LOCAL_REG, 1);
428 mdelay(5);
429}
430
431static void ath11k_pci_sw_reset(struct ath11k_base *ab, bool power_on)
432{
433 if (power_on) {
434 ath11k_pci_enable_ltssm(ab);
435 ath11k_pci_clear_all_intrs(ab);
436 ath11k_pci_set_wlaon_pwr_ctrl(ab);
437 if (ab->hw_params.fix_l1ss)
438 ath11k_pci_fix_l1ss(ab);
439 }
440
441 ath11k_mhi_clear_vector(ab);
442 ath11k_pci_soc_global_reset(ab);
443 ath11k_mhi_set_mhictrl_reset(ab);
444 ath11k_pci_clear_dbg_registers(ab);
445}
446
447int ath11k_pci_get_msi_irq(struct device *dev, unsigned int vector)
448{
449 struct pci_dev *pci_dev = to_pci_dev(dev);
450
451 return pci_irq_vector(pci_dev, vector);
452}
453
454static void ath11k_pci_get_msi_address(struct ath11k_base *ab, u32 *msi_addr_lo,
455 u32 *msi_addr_hi)
456{
457 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
458 struct pci_dev *pci_dev = to_pci_dev(ab->dev);
459
460 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_LO,
461 msi_addr_lo);
462
463 if (test_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags)) {
464 pci_read_config_dword(pci_dev, pci_dev->msi_cap + PCI_MSI_ADDRESS_HI,
465 msi_addr_hi);
466 } else {
467 *msi_addr_hi = 0;
468 }
469}
470
471int ath11k_pci_get_user_msi_assignment(struct ath11k_pci *ab_pci, char *user_name,
472 int *num_vectors, u32 *user_base_data,
473 u32 *base_vector)
474{
475 struct ath11k_base *ab = ab_pci->ab;
476 const struct ath11k_msi_config *msi_config = ab_pci->msi_config;
477 int idx;
478
479 for (idx = 0; idx < msi_config->total_users; idx++) {
480 if (strcmp(user_name, msi_config->users[idx].name) == 0) {
481 *num_vectors = msi_config->users[idx].num_vectors;
482 *user_base_data = msi_config->users[idx].base_vector
483 + ab_pci->msi_ep_base_data;
484 *base_vector = msi_config->users[idx].base_vector;
485
486 ath11k_dbg(ab, ATH11K_DBG_PCI, "Assign MSI to user: %s, num_vectors: %d, user_base_data: %u, base_vector: %u\n",
487 user_name, *num_vectors, *user_base_data,
488 *base_vector);
489
490 return 0;
491 }
492 }
493
494 ath11k_err(ab, "Failed to find MSI assignment for %s!\n", user_name);
495
496 return -EINVAL;
497}
498
499static void ath11k_pci_get_ce_msi_idx(struct ath11k_base *ab, u32 ce_id,
500 u32 *msi_idx)
501{
502 u32 i, msi_data_idx;
503
504 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
505 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
506 continue;
507
508 if (ce_id == i)
509 break;
510
511 msi_data_idx++;
512 }
513 *msi_idx = msi_data_idx;
514}
515
516static int ath11k_get_user_msi_assignment(struct ath11k_base *ab, char *user_name,
517 int *num_vectors, u32 *user_base_data,
518 u32 *base_vector)
519{
520 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
521
522 return ath11k_pci_get_user_msi_assignment(ab_pci, user_name,
523 num_vectors, user_base_data,
524 base_vector);
525}
526
527static void ath11k_pci_free_ext_irq(struct ath11k_base *ab)
528{
529 int i, j;
530
531 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
532 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
533
534 for (j = 0; j < irq_grp->num_irq; j++)
535 free_irq(ab->irq_num[irq_grp->irqs[j]], irq_grp);
536
537 netif_napi_del(&irq_grp->napi);
538 }
539}
540
541static void ath11k_pci_free_irq(struct ath11k_base *ab)
542{
543 int i, irq_idx;
544
545 for (i = 0; i < ab->hw_params.ce_count; i++) {
546 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
547 continue;
548 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
549 free_irq(ab->irq_num[irq_idx], &ab->ce.ce_pipe[i]);
550 }
551
552 ath11k_pci_free_ext_irq(ab);
553}
554
555static void ath11k_pci_ce_irq_enable(struct ath11k_base *ab, u16 ce_id)
556{
557 u32 irq_idx;
558
559 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
560 enable_irq(ab->irq_num[irq_idx]);
561}
562
563static void ath11k_pci_ce_irq_disable(struct ath11k_base *ab, u16 ce_id)
564{
565 u32 irq_idx;
566
567 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + ce_id;
568 disable_irq_nosync(ab->irq_num[irq_idx]);
569}
570
571static void ath11k_pci_ce_irqs_disable(struct ath11k_base *ab)
572{
573 int i;
574
575 for (i = 0; i < ab->hw_params.ce_count; i++) {
576 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
577 continue;
578 ath11k_pci_ce_irq_disable(ab, i);
579 }
580}
581
582static void ath11k_pci_sync_ce_irqs(struct ath11k_base *ab)
583{
584 int i;
585 int irq_idx;
586
587 for (i = 0; i < ab->hw_params.ce_count; i++) {
588 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
589 continue;
590
591 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
592 synchronize_irq(ab->irq_num[irq_idx]);
593 }
594}
595
596static void ath11k_pci_ce_tasklet(struct tasklet_struct *t)
597{
598 struct ath11k_ce_pipe *ce_pipe = from_tasklet(ce_pipe, t, intr_tq);
599
600 ath11k_ce_per_engine_service(ce_pipe->ab, ce_pipe->pipe_num);
601
602 ath11k_pci_ce_irq_enable(ce_pipe->ab, ce_pipe->pipe_num);
603}
604
605static irqreturn_t ath11k_pci_ce_interrupt_handler(int irq, void *arg)
606{
607 struct ath11k_ce_pipe *ce_pipe = arg;
608
609
610 ce_pipe->timestamp = jiffies;
611
612 ath11k_pci_ce_irq_disable(ce_pipe->ab, ce_pipe->pipe_num);
613 tasklet_schedule(&ce_pipe->intr_tq);
614
615 return IRQ_HANDLED;
616}
617
618static void ath11k_pci_ext_grp_disable(struct ath11k_ext_irq_grp *irq_grp)
619{
620 int i;
621
622 for (i = 0; i < irq_grp->num_irq; i++)
623 disable_irq_nosync(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
624}
625
626static void __ath11k_pci_ext_irq_disable(struct ath11k_base *sc)
627{
628 int i;
629
630 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
631 struct ath11k_ext_irq_grp *irq_grp = &sc->ext_irq_grp[i];
632
633 ath11k_pci_ext_grp_disable(irq_grp);
634
635 napi_synchronize(&irq_grp->napi);
636 napi_disable(&irq_grp->napi);
637 }
638}
639
640static void ath11k_pci_ext_grp_enable(struct ath11k_ext_irq_grp *irq_grp)
641{
642 int i;
643
644 for (i = 0; i < irq_grp->num_irq; i++)
645 enable_irq(irq_grp->ab->irq_num[irq_grp->irqs[i]]);
646}
647
648static void ath11k_pci_ext_irq_enable(struct ath11k_base *ab)
649{
650 int i;
651
652 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
653 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
654
655 napi_enable(&irq_grp->napi);
656 ath11k_pci_ext_grp_enable(irq_grp);
657 }
658}
659
660static void ath11k_pci_sync_ext_irqs(struct ath11k_base *ab)
661{
662 int i, j, irq_idx;
663
664 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
665 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
666
667 for (j = 0; j < irq_grp->num_irq; j++) {
668 irq_idx = irq_grp->irqs[j];
669 synchronize_irq(ab->irq_num[irq_idx]);
670 }
671 }
672}
673
674static void ath11k_pci_ext_irq_disable(struct ath11k_base *ab)
675{
676 __ath11k_pci_ext_irq_disable(ab);
677 ath11k_pci_sync_ext_irqs(ab);
678}
679
680static int ath11k_pci_ext_grp_napi_poll(struct napi_struct *napi, int budget)
681{
682 struct ath11k_ext_irq_grp *irq_grp = container_of(napi,
683 struct ath11k_ext_irq_grp,
684 napi);
685 struct ath11k_base *ab = irq_grp->ab;
686 int work_done;
687
688 work_done = ath11k_dp_service_srng(ab, irq_grp, budget);
689 if (work_done < budget) {
690 napi_complete_done(napi, work_done);
691 ath11k_pci_ext_grp_enable(irq_grp);
692 }
693
694 if (work_done > budget)
695 work_done = budget;
696
697 return work_done;
698}
699
700static irqreturn_t ath11k_pci_ext_interrupt_handler(int irq, void *arg)
701{
702 struct ath11k_ext_irq_grp *irq_grp = arg;
703
704 ath11k_dbg(irq_grp->ab, ATH11K_DBG_PCI, "ext irq:%d\n", irq);
705
706
707 irq_grp->timestamp = jiffies;
708
709 ath11k_pci_ext_grp_disable(irq_grp);
710
711 napi_schedule(&irq_grp->napi);
712
713 return IRQ_HANDLED;
714}
715
716static int ath11k_pci_ext_irq_config(struct ath11k_base *ab)
717{
718 int i, j, ret, num_vectors = 0;
719 u32 user_base_data = 0, base_vector = 0, base_idx;
720
721 base_idx = ATH11K_PCI_IRQ_CE0_OFFSET + CE_COUNT_MAX;
722 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab), "DP",
723 &num_vectors,
724 &user_base_data,
725 &base_vector);
726 if (ret < 0)
727 return ret;
728
729 for (i = 0; i < ATH11K_EXT_IRQ_GRP_NUM_MAX; i++) {
730 struct ath11k_ext_irq_grp *irq_grp = &ab->ext_irq_grp[i];
731 u32 num_irq = 0;
732
733 irq_grp->ab = ab;
734 irq_grp->grp_id = i;
735 init_dummy_netdev(&irq_grp->napi_ndev);
736 netif_napi_add(&irq_grp->napi_ndev, &irq_grp->napi,
737 ath11k_pci_ext_grp_napi_poll, NAPI_POLL_WEIGHT);
738
739 if (ab->hw_params.ring_mask->tx[i] ||
740 ab->hw_params.ring_mask->rx[i] ||
741 ab->hw_params.ring_mask->rx_err[i] ||
742 ab->hw_params.ring_mask->rx_wbm_rel[i] ||
743 ab->hw_params.ring_mask->reo_status[i] ||
744 ab->hw_params.ring_mask->rxdma2host[i] ||
745 ab->hw_params.ring_mask->host2rxdma[i] ||
746 ab->hw_params.ring_mask->rx_mon_status[i]) {
747 num_irq = 1;
748 }
749
750 irq_grp->num_irq = num_irq;
751 irq_grp->irqs[0] = base_idx + i;
752
753 for (j = 0; j < irq_grp->num_irq; j++) {
754 int irq_idx = irq_grp->irqs[j];
755 int vector = (i % num_vectors) + base_vector;
756 int irq = ath11k_pci_get_msi_irq(ab->dev, vector);
757
758 ab->irq_num[irq_idx] = irq;
759
760 ath11k_dbg(ab, ATH11K_DBG_PCI,
761 "irq:%d group:%d\n", irq, i);
762
763 irq_set_status_flags(irq, IRQ_DISABLE_UNLAZY);
764 ret = request_irq(irq, ath11k_pci_ext_interrupt_handler,
765 IRQF_SHARED,
766 "DP_EXT_IRQ", irq_grp);
767 if (ret) {
768 ath11k_err(ab, "failed request irq %d: %d\n",
769 vector, ret);
770 return ret;
771 }
772
773 disable_irq_nosync(ab->irq_num[irq_idx]);
774 }
775 }
776
777 return 0;
778}
779
780static int ath11k_pci_config_irq(struct ath11k_base *ab)
781{
782 struct ath11k_ce_pipe *ce_pipe;
783 u32 msi_data_start;
784 u32 msi_data_count, msi_data_idx;
785 u32 msi_irq_start;
786 unsigned int msi_data;
787 int irq, i, ret, irq_idx;
788
789 ret = ath11k_pci_get_user_msi_assignment(ath11k_pci_priv(ab),
790 "CE", &msi_data_count,
791 &msi_data_start, &msi_irq_start);
792 if (ret)
793 return ret;
794
795
796 for (i = 0, msi_data_idx = 0; i < ab->hw_params.ce_count; i++) {
797 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
798 continue;
799
800 msi_data = (msi_data_idx % msi_data_count) + msi_irq_start;
801 irq = ath11k_pci_get_msi_irq(ab->dev, msi_data);
802 ce_pipe = &ab->ce.ce_pipe[i];
803
804 irq_idx = ATH11K_PCI_IRQ_CE0_OFFSET + i;
805
806 tasklet_setup(&ce_pipe->intr_tq, ath11k_pci_ce_tasklet);
807
808 ret = request_irq(irq, ath11k_pci_ce_interrupt_handler,
809 IRQF_SHARED, irq_name[irq_idx],
810 ce_pipe);
811 if (ret) {
812 ath11k_err(ab, "failed to request irq %d: %d\n",
813 irq_idx, ret);
814 return ret;
815 }
816
817 ab->irq_num[irq_idx] = irq;
818 msi_data_idx++;
819
820 ath11k_pci_ce_irq_disable(ab, i);
821 }
822
823 ret = ath11k_pci_ext_irq_config(ab);
824 if (ret)
825 return ret;
826
827 return 0;
828}
829
830static void ath11k_pci_init_qmi_ce_config(struct ath11k_base *ab)
831{
832 struct ath11k_qmi_ce_cfg *cfg = &ab->qmi.ce_cfg;
833
834 cfg->tgt_ce = ab->hw_params.target_ce_config;
835 cfg->tgt_ce_len = ab->hw_params.target_ce_count;
836
837 cfg->svc_to_ce_map = ab->hw_params.svc_to_ce_map;
838 cfg->svc_to_ce_map_len = ab->hw_params.svc_to_ce_map_len;
839 ab->qmi.service_ins_id = ab->hw_params.qmi_service_ins_id;
840
841 ath11k_ce_get_shadow_config(ab, &cfg->shadow_reg_v2,
842 &cfg->shadow_reg_v2_len);
843}
844
845static void ath11k_pci_ce_irqs_enable(struct ath11k_base *ab)
846{
847 int i;
848
849 for (i = 0; i < ab->hw_params.ce_count; i++) {
850 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
851 continue;
852 ath11k_pci_ce_irq_enable(ab, i);
853 }
854}
855
856static int ath11k_pci_enable_msi(struct ath11k_pci *ab_pci)
857{
858 struct ath11k_base *ab = ab_pci->ab;
859 const struct ath11k_msi_config *msi_config = ab_pci->msi_config;
860 struct msi_desc *msi_desc;
861 int num_vectors;
862 int ret;
863
864 num_vectors = pci_alloc_irq_vectors(ab_pci->pdev,
865 msi_config->total_vectors,
866 msi_config->total_vectors,
867 PCI_IRQ_MSI);
868 if (num_vectors != msi_config->total_vectors) {
869 ath11k_err(ab, "failed to get %d MSI vectors, only %d available",
870 msi_config->total_vectors, num_vectors);
871
872 if (num_vectors >= 0)
873 return -EINVAL;
874 else
875 return num_vectors;
876 }
877
878 msi_desc = irq_get_msi_desc(ab_pci->pdev->irq);
879 if (!msi_desc) {
880 ath11k_err(ab, "msi_desc is NULL!\n");
881 ret = -EINVAL;
882 goto free_msi_vector;
883 }
884
885 ab_pci->msi_ep_base_data = msi_desc->msg.data;
886 if (msi_desc->msi_attrib.is_64)
887 set_bit(ATH11K_PCI_FLAG_IS_MSI_64, &ab_pci->flags);
888
889 ath11k_dbg(ab, ATH11K_DBG_PCI, "msi base data is %d\n", ab_pci->msi_ep_base_data);
890
891 return 0;
892
893free_msi_vector:
894 pci_free_irq_vectors(ab_pci->pdev);
895
896 return ret;
897}
898
899static void ath11k_pci_disable_msi(struct ath11k_pci *ab_pci)
900{
901 pci_free_irq_vectors(ab_pci->pdev);
902}
903
904static int ath11k_pci_claim(struct ath11k_pci *ab_pci, struct pci_dev *pdev)
905{
906 struct ath11k_base *ab = ab_pci->ab;
907 u16 device_id;
908 int ret = 0;
909
910 pci_read_config_word(pdev, PCI_DEVICE_ID, &device_id);
911 if (device_id != ab_pci->dev_id) {
912 ath11k_err(ab, "pci device id mismatch: 0x%x 0x%x\n",
913 device_id, ab_pci->dev_id);
914 ret = -EIO;
915 goto out;
916 }
917
918 ret = pci_assign_resource(pdev, ATH11K_PCI_BAR_NUM);
919 if (ret) {
920 ath11k_err(ab, "failed to assign pci resource: %d\n", ret);
921 goto out;
922 }
923
924 ret = pci_enable_device(pdev);
925 if (ret) {
926 ath11k_err(ab, "failed to enable pci device: %d\n", ret);
927 goto out;
928 }
929
930 ret = pci_request_region(pdev, ATH11K_PCI_BAR_NUM, "ath11k_pci");
931 if (ret) {
932 ath11k_err(ab, "failed to request pci region: %d\n", ret);
933 goto disable_device;
934 }
935
936 ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
937 if (ret) {
938 ath11k_err(ab, "failed to set pci dma mask to %d: %d\n",
939 ATH11K_PCI_DMA_MASK, ret);
940 goto release_region;
941 }
942
943 ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ATH11K_PCI_DMA_MASK));
944 if (ret) {
945 ath11k_err(ab, "failed to set pci consistent dma mask to %d: %d\n",
946 ATH11K_PCI_DMA_MASK, ret);
947 goto release_region;
948 }
949
950 pci_set_master(pdev);
951
952 ab->mem_len = pci_resource_len(pdev, ATH11K_PCI_BAR_NUM);
953 ab->mem = pci_iomap(pdev, ATH11K_PCI_BAR_NUM, 0);
954 if (!ab->mem) {
955 ath11k_err(ab, "failed to map pci bar %d\n", ATH11K_PCI_BAR_NUM);
956 ret = -EIO;
957 goto clear_master;
958 }
959
960 ath11k_dbg(ab, ATH11K_DBG_BOOT, "boot pci_mem 0x%pK\n", ab->mem);
961 return 0;
962
963clear_master:
964 pci_clear_master(pdev);
965release_region:
966 pci_release_region(pdev, ATH11K_PCI_BAR_NUM);
967disable_device:
968 pci_disable_device(pdev);
969out:
970 return ret;
971}
972
973static void ath11k_pci_free_region(struct ath11k_pci *ab_pci)
974{
975 struct ath11k_base *ab = ab_pci->ab;
976 struct pci_dev *pci_dev = ab_pci->pdev;
977
978 pci_iounmap(pci_dev, ab->mem);
979 ab->mem = NULL;
980 pci_clear_master(pci_dev);
981 pci_release_region(pci_dev, ATH11K_PCI_BAR_NUM);
982 if (pci_is_enabled(pci_dev))
983 pci_disable_device(pci_dev);
984}
985
986static void ath11k_pci_aspm_disable(struct ath11k_pci *ab_pci)
987{
988 struct ath11k_base *ab = ab_pci->ab;
989
990 pcie_capability_read_word(ab_pci->pdev, PCI_EXP_LNKCTL,
991 &ab_pci->link_ctl);
992
993 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n",
994 ab_pci->link_ctl,
995 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L0S),
996 u16_get_bits(ab_pci->link_ctl, PCI_EXP_LNKCTL_ASPM_L1));
997
998
999 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
1000 ab_pci->link_ctl & ~PCI_EXP_LNKCTL_ASPMC);
1001
1002 set_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags);
1003}
1004
1005static void ath11k_pci_aspm_restore(struct ath11k_pci *ab_pci)
1006{
1007 if (test_and_clear_bit(ATH11K_PCI_ASPM_RESTORE, &ab_pci->flags))
1008 pcie_capability_write_word(ab_pci->pdev, PCI_EXP_LNKCTL,
1009 ab_pci->link_ctl);
1010}
1011
1012static int ath11k_pci_power_up(struct ath11k_base *ab)
1013{
1014 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
1015 int ret;
1016
1017 ab_pci->register_window = 0;
1018 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1019 ath11k_pci_sw_reset(ab_pci->ab, true);
1020
1021
1022
1023
1024 ath11k_pci_aspm_disable(ab_pci);
1025
1026 ret = ath11k_mhi_start(ab_pci);
1027 if (ret) {
1028 ath11k_err(ab, "failed to start mhi: %d\n", ret);
1029 return ret;
1030 }
1031
1032 if (ab->bus_params.static_window_map)
1033 ath11k_pci_select_static_window(ab_pci);
1034
1035 return 0;
1036}
1037
1038static void ath11k_pci_power_down(struct ath11k_base *ab)
1039{
1040 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
1041
1042
1043 ath11k_pci_aspm_restore(ab_pci);
1044
1045 ath11k_pci_force_wake(ab_pci->ab);
1046 ath11k_mhi_stop(ab_pci);
1047 clear_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1048 ath11k_pci_sw_reset(ab_pci->ab, false);
1049}
1050
1051static int ath11k_pci_hif_suspend(struct ath11k_base *ab)
1052{
1053 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
1054
1055 ath11k_mhi_suspend(ar_pci);
1056
1057 return 0;
1058}
1059
1060static int ath11k_pci_hif_resume(struct ath11k_base *ab)
1061{
1062 struct ath11k_pci *ar_pci = ath11k_pci_priv(ab);
1063
1064 ath11k_mhi_resume(ar_pci);
1065
1066 return 0;
1067}
1068
1069static void ath11k_pci_kill_tasklets(struct ath11k_base *ab)
1070{
1071 int i;
1072
1073 for (i = 0; i < ab->hw_params.ce_count; i++) {
1074 struct ath11k_ce_pipe *ce_pipe = &ab->ce.ce_pipe[i];
1075
1076 if (ath11k_ce_get_attr_flags(ab, i) & CE_ATTR_DIS_INTR)
1077 continue;
1078
1079 tasklet_kill(&ce_pipe->intr_tq);
1080 }
1081}
1082
1083static void ath11k_pci_ce_irq_disable_sync(struct ath11k_base *ab)
1084{
1085 ath11k_pci_ce_irqs_disable(ab);
1086 ath11k_pci_sync_ce_irqs(ab);
1087 ath11k_pci_kill_tasklets(ab);
1088}
1089
1090static void ath11k_pci_stop(struct ath11k_base *ab)
1091{
1092 ath11k_pci_ce_irq_disable_sync(ab);
1093 ath11k_ce_cleanup_pipes(ab);
1094}
1095
1096static int ath11k_pci_start(struct ath11k_base *ab)
1097{
1098 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
1099
1100 set_bit(ATH11K_PCI_FLAG_INIT_DONE, &ab_pci->flags);
1101
1102 ath11k_pci_aspm_restore(ab_pci);
1103
1104 ath11k_pci_ce_irqs_enable(ab);
1105 ath11k_ce_rx_post_buf(ab);
1106
1107 return 0;
1108}
1109
1110static void ath11k_pci_hif_ce_irq_enable(struct ath11k_base *ab)
1111{
1112 ath11k_pci_ce_irqs_enable(ab);
1113}
1114
1115static void ath11k_pci_hif_ce_irq_disable(struct ath11k_base *ab)
1116{
1117 ath11k_pci_ce_irq_disable_sync(ab);
1118}
1119
1120static int ath11k_pci_map_service_to_pipe(struct ath11k_base *ab, u16 service_id,
1121 u8 *ul_pipe, u8 *dl_pipe)
1122{
1123 const struct service_to_pipe *entry;
1124 bool ul_set = false, dl_set = false;
1125 int i;
1126
1127 for (i = 0; i < ab->hw_params.svc_to_ce_map_len; i++) {
1128 entry = &ab->hw_params.svc_to_ce_map[i];
1129
1130 if (__le32_to_cpu(entry->service_id) != service_id)
1131 continue;
1132
1133 switch (__le32_to_cpu(entry->pipedir)) {
1134 case PIPEDIR_NONE:
1135 break;
1136 case PIPEDIR_IN:
1137 WARN_ON(dl_set);
1138 *dl_pipe = __le32_to_cpu(entry->pipenum);
1139 dl_set = true;
1140 break;
1141 case PIPEDIR_OUT:
1142 WARN_ON(ul_set);
1143 *ul_pipe = __le32_to_cpu(entry->pipenum);
1144 ul_set = true;
1145 break;
1146 case PIPEDIR_INOUT:
1147 WARN_ON(dl_set);
1148 WARN_ON(ul_set);
1149 *dl_pipe = __le32_to_cpu(entry->pipenum);
1150 *ul_pipe = __le32_to_cpu(entry->pipenum);
1151 dl_set = true;
1152 ul_set = true;
1153 break;
1154 }
1155 }
1156
1157 if (WARN_ON(!ul_set || !dl_set))
1158 return -ENOENT;
1159
1160 return 0;
1161}
1162
1163static const struct ath11k_hif_ops ath11k_pci_hif_ops = {
1164 .start = ath11k_pci_start,
1165 .stop = ath11k_pci_stop,
1166 .read32 = ath11k_pci_read32,
1167 .write32 = ath11k_pci_write32,
1168 .power_down = ath11k_pci_power_down,
1169 .power_up = ath11k_pci_power_up,
1170 .suspend = ath11k_pci_hif_suspend,
1171 .resume = ath11k_pci_hif_resume,
1172 .irq_enable = ath11k_pci_ext_irq_enable,
1173 .irq_disable = ath11k_pci_ext_irq_disable,
1174 .get_msi_address = ath11k_pci_get_msi_address,
1175 .get_user_msi_vector = ath11k_get_user_msi_assignment,
1176 .map_service_to_pipe = ath11k_pci_map_service_to_pipe,
1177 .ce_irq_enable = ath11k_pci_hif_ce_irq_enable,
1178 .ce_irq_disable = ath11k_pci_hif_ce_irq_disable,
1179 .get_ce_msi_idx = ath11k_pci_get_ce_msi_idx,
1180};
1181
1182static void ath11k_pci_read_hw_version(struct ath11k_base *ab, u32 *major, u32 *minor)
1183{
1184 u32 soc_hw_version;
1185
1186 soc_hw_version = ath11k_pci_read32(ab, TCSR_SOC_HW_VERSION);
1187 *major = FIELD_GET(TCSR_SOC_HW_VERSION_MAJOR_MASK,
1188 soc_hw_version);
1189 *minor = FIELD_GET(TCSR_SOC_HW_VERSION_MINOR_MASK,
1190 soc_hw_version);
1191
1192 ath11k_dbg(ab, ATH11K_DBG_PCI, "pci tcsr_soc_hw_version major %d minor %d\n",
1193 *major, *minor);
1194}
1195
1196static int ath11k_pci_probe(struct pci_dev *pdev,
1197 const struct pci_device_id *pci_dev)
1198{
1199 struct ath11k_base *ab;
1200 struct ath11k_pci *ab_pci;
1201 u32 soc_hw_version_major, soc_hw_version_minor;
1202 int ret;
1203
1204 ab = ath11k_core_alloc(&pdev->dev, sizeof(*ab_pci), ATH11K_BUS_PCI,
1205 &ath11k_pci_bus_params);
1206 if (!ab) {
1207 dev_err(&pdev->dev, "failed to allocate ath11k base\n");
1208 return -ENOMEM;
1209 }
1210
1211 ab->dev = &pdev->dev;
1212 pci_set_drvdata(pdev, ab);
1213 ab_pci = ath11k_pci_priv(ab);
1214 ab_pci->dev_id = pci_dev->device;
1215 ab_pci->ab = ab;
1216 ab_pci->pdev = pdev;
1217 ab->hif.ops = &ath11k_pci_hif_ops;
1218 pci_set_drvdata(pdev, ab);
1219 spin_lock_init(&ab_pci->window_lock);
1220
1221 ret = ath11k_pci_claim(ab_pci, pdev);
1222 if (ret) {
1223 ath11k_err(ab, "failed to claim device: %d\n", ret);
1224 goto err_free_core;
1225 }
1226
1227 switch (pci_dev->device) {
1228 case QCA6390_DEVICE_ID:
1229 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
1230 &soc_hw_version_minor);
1231 switch (soc_hw_version_major) {
1232 case 2:
1233 ab->hw_rev = ATH11K_HW_QCA6390_HW20;
1234 break;
1235 default:
1236 dev_err(&pdev->dev, "Unsupported QCA6390 SOC hardware version: %d %d\n",
1237 soc_hw_version_major, soc_hw_version_minor);
1238 ret = -EOPNOTSUPP;
1239 goto err_pci_free_region;
1240 }
1241 ab_pci->msi_config = &ath11k_msi_config[0];
1242 break;
1243 case QCN9074_DEVICE_ID:
1244 ab_pci->msi_config = &ath11k_msi_config[1];
1245 ab->bus_params.static_window_map = true;
1246 ab->hw_rev = ATH11K_HW_QCN9074_HW10;
1247 break;
1248 case WCN6855_DEVICE_ID:
1249 ath11k_pci_read_hw_version(ab, &soc_hw_version_major,
1250 &soc_hw_version_minor);
1251 switch (soc_hw_version_major) {
1252 case 2:
1253 ab->hw_rev = ATH11K_HW_WCN6855_HW20;
1254 break;
1255 default:
1256 dev_err(&pdev->dev, "Unsupported WCN6855 SOC hardware version: %d %d\n",
1257 soc_hw_version_major, soc_hw_version_minor);
1258 ret = -EOPNOTSUPP;
1259 goto err_pci_free_region;
1260 }
1261 ab_pci->msi_config = &ath11k_msi_config[0];
1262 break;
1263 default:
1264 dev_err(&pdev->dev, "Unknown PCI device found: 0x%x\n",
1265 pci_dev->device);
1266 ret = -EOPNOTSUPP;
1267 goto err_pci_free_region;
1268 }
1269
1270 ret = ath11k_pci_enable_msi(ab_pci);
1271 if (ret) {
1272 ath11k_err(ab, "failed to enable msi: %d\n", ret);
1273 goto err_pci_free_region;
1274 }
1275
1276 ret = ath11k_core_pre_init(ab);
1277 if (ret)
1278 goto err_pci_disable_msi;
1279
1280 ret = ath11k_mhi_register(ab_pci);
1281 if (ret) {
1282 ath11k_err(ab, "failed to register mhi: %d\n", ret);
1283 goto err_pci_disable_msi;
1284 }
1285
1286 ret = ath11k_hal_srng_init(ab);
1287 if (ret)
1288 goto err_mhi_unregister;
1289
1290 ret = ath11k_ce_alloc_pipes(ab);
1291 if (ret) {
1292 ath11k_err(ab, "failed to allocate ce pipes: %d\n", ret);
1293 goto err_hal_srng_deinit;
1294 }
1295
1296 ath11k_pci_init_qmi_ce_config(ab);
1297
1298 ret = ath11k_pci_config_irq(ab);
1299 if (ret) {
1300 ath11k_err(ab, "failed to config irq: %d\n", ret);
1301 goto err_ce_free;
1302 }
1303
1304 ret = ath11k_core_init(ab);
1305 if (ret) {
1306 ath11k_err(ab, "failed to init core: %d\n", ret);
1307 goto err_free_irq;
1308 }
1309 return 0;
1310
1311err_free_irq:
1312 ath11k_pci_free_irq(ab);
1313
1314err_ce_free:
1315 ath11k_ce_free_pipes(ab);
1316
1317err_hal_srng_deinit:
1318 ath11k_hal_srng_deinit(ab);
1319
1320err_mhi_unregister:
1321 ath11k_mhi_unregister(ab_pci);
1322
1323err_pci_disable_msi:
1324 ath11k_pci_disable_msi(ab_pci);
1325
1326err_pci_free_region:
1327 ath11k_pci_free_region(ab_pci);
1328
1329err_free_core:
1330 ath11k_core_free(ab);
1331
1332 return ret;
1333}
1334
1335static void ath11k_pci_remove(struct pci_dev *pdev)
1336{
1337 struct ath11k_base *ab = pci_get_drvdata(pdev);
1338 struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
1339
1340 if (test_bit(ATH11K_FLAG_QMI_FAIL, &ab->dev_flags)) {
1341 ath11k_pci_power_down(ab);
1342 ath11k_debugfs_soc_destroy(ab);
1343 ath11k_qmi_deinit_service(ab);
1344 goto qmi_fail;
1345 }
1346
1347 set_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags);
1348
1349 ath11k_core_deinit(ab);
1350
1351qmi_fail:
1352 ath11k_mhi_unregister(ab_pci);
1353
1354 ath11k_pci_free_irq(ab);
1355 ath11k_pci_disable_msi(ab_pci);
1356 ath11k_pci_free_region(ab_pci);
1357
1358 ath11k_hal_srng_deinit(ab);
1359 ath11k_ce_free_pipes(ab);
1360 ath11k_core_free(ab);
1361}
1362
1363static void ath11k_pci_shutdown(struct pci_dev *pdev)
1364{
1365 struct ath11k_base *ab = pci_get_drvdata(pdev);
1366
1367 ath11k_pci_power_down(ab);
1368}
1369
1370static __maybe_unused int ath11k_pci_pm_suspend(struct device *dev)
1371{
1372 struct ath11k_base *ab = dev_get_drvdata(dev);
1373 int ret;
1374
1375 ret = ath11k_core_suspend(ab);
1376 if (ret)
1377 ath11k_warn(ab, "failed to suspend core: %d\n", ret);
1378
1379 return ret;
1380}
1381
1382static __maybe_unused int ath11k_pci_pm_resume(struct device *dev)
1383{
1384 struct ath11k_base *ab = dev_get_drvdata(dev);
1385 int ret;
1386
1387 ret = ath11k_core_resume(ab);
1388 if (ret)
1389 ath11k_warn(ab, "failed to resume core: %d\n", ret);
1390
1391 return ret;
1392}
1393
1394static SIMPLE_DEV_PM_OPS(ath11k_pci_pm_ops,
1395 ath11k_pci_pm_suspend,
1396 ath11k_pci_pm_resume);
1397
1398static struct pci_driver ath11k_pci_driver = {
1399 .name = "ath11k_pci",
1400 .id_table = ath11k_pci_id_table,
1401 .probe = ath11k_pci_probe,
1402 .remove = ath11k_pci_remove,
1403 .shutdown = ath11k_pci_shutdown,
1404#ifdef CONFIG_PM
1405 .driver.pm = &ath11k_pci_pm_ops,
1406#endif
1407};
1408
1409static int ath11k_pci_init(void)
1410{
1411 int ret;
1412
1413 ret = pci_register_driver(&ath11k_pci_driver);
1414 if (ret)
1415 pr_err("failed to register ath11k pci driver: %d\n",
1416 ret);
1417
1418 return ret;
1419}
1420module_init(ath11k_pci_init);
1421
1422static void ath11k_pci_exit(void)
1423{
1424 pci_unregister_driver(&ath11k_pci_driver);
1425}
1426
1427module_exit(ath11k_pci_exit);
1428
1429MODULE_DESCRIPTION("Driver support for Qualcomm Technologies 802.11ax WLAN PCIe devices");
1430MODULE_LICENSE("Dual BSD/GPL");
1431
1432
1433MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_BOARD_API2_FILE);
1434MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_AMSS_FILE);
1435MODULE_FIRMWARE(ATH11K_FW_DIR "/QCA6390/hw2.0/" ATH11K_M3_FILE);
1436
