linux/drivers/net/mdio/mdio-bcm-unimac.c
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   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * Broadcom UniMAC MDIO bus controller driver
   4 *
   5 * Copyright (C) 2014-2017 Broadcom
   6 */
   7
   8#include <linux/clk.h>
   9#include <linux/delay.h>
  10#include <linux/io.h>
  11#include <linux/kernel.h>
  12#include <linux/module.h>
  13#include <linux/of.h>
  14#include <linux/of_mdio.h>
  15#include <linux/of_platform.h>
  16#include <linux/phy.h>
  17#include <linux/platform_data/mdio-bcm-unimac.h>
  18#include <linux/platform_device.h>
  19#include <linux/sched.h>
  20
  21#define MDIO_CMD                0x00
  22#define  MDIO_START_BUSY        (1 << 29)
  23#define  MDIO_READ_FAIL         (1 << 28)
  24#define  MDIO_RD                (2 << 26)
  25#define  MDIO_WR                (1 << 26)
  26#define  MDIO_PMD_SHIFT         21
  27#define  MDIO_PMD_MASK          0x1F
  28#define  MDIO_REG_SHIFT         16
  29#define  MDIO_REG_MASK          0x1F
  30
  31#define MDIO_CFG                0x04
  32#define  MDIO_C22               (1 << 0)
  33#define  MDIO_C45               0
  34#define  MDIO_CLK_DIV_SHIFT     4
  35#define  MDIO_CLK_DIV_MASK      0x3F
  36#define  MDIO_SUPP_PREAMBLE     (1 << 12)
  37
  38struct unimac_mdio_priv {
  39        struct mii_bus          *mii_bus;
  40        void __iomem            *base;
  41        int (*wait_func)        (void *wait_func_data);
  42        void                    *wait_func_data;
  43        struct clk              *clk;
  44        u32                     clk_freq;
  45};
  46
  47static inline u32 unimac_mdio_readl(struct unimac_mdio_priv *priv, u32 offset)
  48{
  49        /* MIPS chips strapped for BE will automagically configure the
  50         * peripheral registers for CPU-native byte order.
  51         */
  52        if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  53                return __raw_readl(priv->base + offset);
  54        else
  55                return readl_relaxed(priv->base + offset);
  56}
  57
  58static inline void unimac_mdio_writel(struct unimac_mdio_priv *priv, u32 val,
  59                                      u32 offset)
  60{
  61        if (IS_ENABLED(CONFIG_MIPS) && IS_ENABLED(CONFIG_CPU_BIG_ENDIAN))
  62                __raw_writel(val, priv->base + offset);
  63        else
  64                writel_relaxed(val, priv->base + offset);
  65}
  66
  67static inline void unimac_mdio_start(struct unimac_mdio_priv *priv)
  68{
  69        u32 reg;
  70
  71        reg = unimac_mdio_readl(priv, MDIO_CMD);
  72        reg |= MDIO_START_BUSY;
  73        unimac_mdio_writel(priv, reg, MDIO_CMD);
  74}
  75
  76static inline unsigned int unimac_mdio_busy(struct unimac_mdio_priv *priv)
  77{
  78        return unimac_mdio_readl(priv, MDIO_CMD) & MDIO_START_BUSY;
  79}
  80
  81static int unimac_mdio_poll(void *wait_func_data)
  82{
  83        struct unimac_mdio_priv *priv = wait_func_data;
  84        unsigned int timeout = 1000;
  85
  86        do {
  87                if (!unimac_mdio_busy(priv))
  88                        return 0;
  89
  90                usleep_range(1000, 2000);
  91        } while (--timeout);
  92
  93        return -ETIMEDOUT;
  94}
  95
  96static int unimac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
  97{
  98        struct unimac_mdio_priv *priv = bus->priv;
  99        int ret;
 100        u32 cmd;
 101
 102        /* Prepare the read operation */
 103        cmd = MDIO_RD | (phy_id << MDIO_PMD_SHIFT) | (reg << MDIO_REG_SHIFT);
 104        unimac_mdio_writel(priv, cmd, MDIO_CMD);
 105
 106        /* Start MDIO transaction */
 107        unimac_mdio_start(priv);
 108
 109        ret = priv->wait_func(priv->wait_func_data);
 110        if (ret)
 111                return ret;
 112
 113        cmd = unimac_mdio_readl(priv, MDIO_CMD);
 114
 115        /* Some broken devices are known not to release the line during
 116         * turn-around, e.g: Broadcom BCM53125 external switches, so check for
 117         * that condition here and ignore the MDIO controller read failure
 118         * indication.
 119         */
 120        if (!(bus->phy_ignore_ta_mask & 1 << phy_id) && (cmd & MDIO_READ_FAIL))
 121                return -EIO;
 122
 123        return cmd & 0xffff;
 124}
 125
 126static int unimac_mdio_write(struct mii_bus *bus, int phy_id,
 127                             int reg, u16 val)
 128{
 129        struct unimac_mdio_priv *priv = bus->priv;
 130        u32 cmd;
 131
 132        /* Prepare the write operation */
 133        cmd = MDIO_WR | (phy_id << MDIO_PMD_SHIFT) |
 134                (reg << MDIO_REG_SHIFT) | (0xffff & val);
 135        unimac_mdio_writel(priv, cmd, MDIO_CMD);
 136
 137        unimac_mdio_start(priv);
 138
 139        return priv->wait_func(priv->wait_func_data);
 140}
 141
 142/* Workaround for integrated BCM7xxx Gigabit PHYs which have a problem with
 143 * their internal MDIO management controller making them fail to successfully
 144 * be read from or written to for the first transaction.  We insert a dummy
 145 * BMSR read here to make sure that phy_get_device() and get_phy_id() can
 146 * correctly read the PHY MII_PHYSID1/2 registers and successfully register a
 147 * PHY device for this peripheral.
 148 *
 149 * Once the PHY driver is registered, we can workaround subsequent reads from
 150 * there (e.g: during system-wide power management).
 151 *
 152 * bus->reset is invoked before mdiobus_scan during mdiobus_register and is
 153 * therefore the right location to stick that workaround. Since we do not want
 154 * to read from non-existing PHYs, we either use bus->phy_mask or do a manual
 155 * Device Tree scan to limit the search area.
 156 */
 157static int unimac_mdio_reset(struct mii_bus *bus)
 158{
 159        struct device_node *np = bus->dev.of_node;
 160        struct device_node *child;
 161        u32 read_mask = 0;
 162        int addr;
 163
 164        if (!np) {
 165                read_mask = ~bus->phy_mask;
 166        } else {
 167                for_each_available_child_of_node(np, child) {
 168                        addr = of_mdio_parse_addr(&bus->dev, child);
 169                        if (addr < 0)
 170                                continue;
 171
 172                        read_mask |= 1 << addr;
 173                }
 174        }
 175
 176        for (addr = 0; addr < PHY_MAX_ADDR; addr++) {
 177                if (read_mask & 1 << addr) {
 178                        dev_dbg(&bus->dev, "Workaround for PHY @ %d\n", addr);
 179                        mdiobus_read(bus, addr, MII_BMSR);
 180                }
 181        }
 182
 183        return 0;
 184}
 185
 186static void unimac_mdio_clk_set(struct unimac_mdio_priv *priv)
 187{
 188        unsigned long rate;
 189        u32 reg, div;
 190
 191        /* Keep the hardware default values */
 192        if (!priv->clk_freq)
 193                return;
 194
 195        if (!priv->clk)
 196                rate = 250000000;
 197        else
 198                rate = clk_get_rate(priv->clk);
 199
 200        div = (rate / (2 * priv->clk_freq)) - 1;
 201        if (div & ~MDIO_CLK_DIV_MASK) {
 202                pr_warn("Incorrect MDIO clock frequency, ignoring\n");
 203                return;
 204        }
 205
 206        /* The MDIO clock is the reference clock (typically 250Mhz) divided by
 207         * 2 x (MDIO_CLK_DIV + 1)
 208         */
 209        reg = unimac_mdio_readl(priv, MDIO_CFG);
 210        reg &= ~(MDIO_CLK_DIV_MASK << MDIO_CLK_DIV_SHIFT);
 211        reg |= div << MDIO_CLK_DIV_SHIFT;
 212        unimac_mdio_writel(priv, reg, MDIO_CFG);
 213}
 214
 215static int unimac_mdio_probe(struct platform_device *pdev)
 216{
 217        struct unimac_mdio_pdata *pdata = pdev->dev.platform_data;
 218        struct unimac_mdio_priv *priv;
 219        struct device_node *np;
 220        struct mii_bus *bus;
 221        struct resource *r;
 222        int ret;
 223
 224        np = pdev->dev.of_node;
 225
 226        priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 227        if (!priv)
 228                return -ENOMEM;
 229
 230        r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 231        if (!r)
 232                return -EINVAL;
 233
 234        /* Just ioremap, as this MDIO block is usually integrated into an
 235         * Ethernet MAC controller register range
 236         */
 237        priv->base = devm_ioremap(&pdev->dev, r->start, resource_size(r));
 238        if (!priv->base) {
 239                dev_err(&pdev->dev, "failed to remap register\n");
 240                return -ENOMEM;
 241        }
 242
 243        priv->clk = devm_clk_get_optional(&pdev->dev, NULL);
 244        if (IS_ERR(priv->clk))
 245                return PTR_ERR(priv->clk);
 246
 247        ret = clk_prepare_enable(priv->clk);
 248        if (ret)
 249                return ret;
 250
 251        if (of_property_read_u32(np, "clock-frequency", &priv->clk_freq))
 252                priv->clk_freq = 0;
 253
 254        unimac_mdio_clk_set(priv);
 255
 256        priv->mii_bus = mdiobus_alloc();
 257        if (!priv->mii_bus) {
 258                ret = -ENOMEM;
 259                goto out_clk_disable;
 260        }
 261
 262        bus = priv->mii_bus;
 263        bus->priv = priv;
 264        if (pdata) {
 265                bus->name = pdata->bus_name;
 266                priv->wait_func = pdata->wait_func;
 267                priv->wait_func_data = pdata->wait_func_data;
 268                bus->phy_mask = ~pdata->phy_mask;
 269        } else {
 270                bus->name = "unimac MII bus";
 271                priv->wait_func_data = priv;
 272                priv->wait_func = unimac_mdio_poll;
 273        }
 274        bus->parent = &pdev->dev;
 275        bus->read = unimac_mdio_read;
 276        bus->write = unimac_mdio_write;
 277        bus->reset = unimac_mdio_reset;
 278        snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", pdev->name, pdev->id);
 279
 280        ret = of_mdiobus_register(bus, np);
 281        if (ret) {
 282                dev_err(&pdev->dev, "MDIO bus registration failed\n");
 283                goto out_mdio_free;
 284        }
 285
 286        platform_set_drvdata(pdev, priv);
 287
 288        dev_info(&pdev->dev, "Broadcom UniMAC MDIO bus\n");
 289
 290        return 0;
 291
 292out_mdio_free:
 293        mdiobus_free(bus);
 294out_clk_disable:
 295        clk_disable_unprepare(priv->clk);
 296        return ret;
 297}
 298
 299static int unimac_mdio_remove(struct platform_device *pdev)
 300{
 301        struct unimac_mdio_priv *priv = platform_get_drvdata(pdev);
 302
 303        mdiobus_unregister(priv->mii_bus);
 304        mdiobus_free(priv->mii_bus);
 305        clk_disable_unprepare(priv->clk);
 306
 307        return 0;
 308}
 309
 310static int __maybe_unused unimac_mdio_suspend(struct device *d)
 311{
 312        struct unimac_mdio_priv *priv = dev_get_drvdata(d);
 313
 314        clk_disable_unprepare(priv->clk);
 315
 316        return 0;
 317}
 318
 319static int __maybe_unused unimac_mdio_resume(struct device *d)
 320{
 321        struct unimac_mdio_priv *priv = dev_get_drvdata(d);
 322        int ret;
 323
 324        ret = clk_prepare_enable(priv->clk);
 325        if (ret)
 326                return ret;
 327
 328        unimac_mdio_clk_set(priv);
 329
 330        return 0;
 331}
 332
 333static SIMPLE_DEV_PM_OPS(unimac_mdio_pm_ops,
 334                         unimac_mdio_suspend, unimac_mdio_resume);
 335
 336static const struct of_device_id unimac_mdio_ids[] = {
 337        { .compatible = "brcm,genet-mdio-v5", },
 338        { .compatible = "brcm,genet-mdio-v4", },
 339        { .compatible = "brcm,genet-mdio-v3", },
 340        { .compatible = "brcm,genet-mdio-v2", },
 341        { .compatible = "brcm,genet-mdio-v1", },
 342        { .compatible = "brcm,unimac-mdio", },
 343        { /* sentinel */ },
 344};
 345MODULE_DEVICE_TABLE(of, unimac_mdio_ids);
 346
 347static struct platform_driver unimac_mdio_driver = {
 348        .driver = {
 349                .name = UNIMAC_MDIO_DRV_NAME,
 350                .of_match_table = unimac_mdio_ids,
 351                .pm = &unimac_mdio_pm_ops,
 352        },
 353        .probe  = unimac_mdio_probe,
 354        .remove = unimac_mdio_remove,
 355};
 356module_platform_driver(unimac_mdio_driver);
 357
 358MODULE_AUTHOR("Broadcom Corporation");
 359MODULE_DESCRIPTION("Broadcom UniMAC MDIO bus controller");
 360MODULE_LICENSE("GPL");
 361MODULE_ALIAS("platform:" UNIMAC_MDIO_DRV_NAME);
 362