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9#ifndef __STMMAC_H__
10#define __STMMAC_H__
11
12#define STMMAC_RESOURCE_NAME "stmmaceth"
13#define DRV_MODULE_VERSION "Jan_2016"
14
15#include <linux/clk.h>
16#include <linux/hrtimer.h>
17#include <linux/if_vlan.h>
18#include <linux/stmmac.h>
19#include <linux/phylink.h>
20#include <linux/pci.h>
21#include "common.h"
22#include <linux/ptp_clock_kernel.h>
23#include <linux/net_tstamp.h>
24#include <linux/reset.h>
25#include <net/page_pool.h>
26
27struct stmmac_resources {
28 void __iomem *addr;
29 u8 mac[ETH_ALEN];
30 int wol_irq;
31 int lpi_irq;
32 int irq;
33 int sfty_ce_irq;
34 int sfty_ue_irq;
35 int rx_irq[MTL_MAX_RX_QUEUES];
36 int tx_irq[MTL_MAX_TX_QUEUES];
37};
38
39enum stmmac_txbuf_type {
40 STMMAC_TXBUF_T_SKB,
41 STMMAC_TXBUF_T_XDP_TX,
42 STMMAC_TXBUF_T_XDP_NDO,
43 STMMAC_TXBUF_T_XSK_TX,
44};
45
46struct stmmac_tx_info {
47 dma_addr_t buf;
48 bool map_as_page;
49 unsigned len;
50 bool last_segment;
51 bool is_jumbo;
52 enum stmmac_txbuf_type buf_type;
53};
54
55#define STMMAC_TBS_AVAIL BIT(0)
56#define STMMAC_TBS_EN BIT(1)
57
58
59struct stmmac_tx_queue {
60 u32 tx_count_frames;
61 int tbs;
62 struct hrtimer txtimer;
63 u32 queue_index;
64 struct stmmac_priv *priv_data;
65 struct dma_extended_desc *dma_etx ____cacheline_aligned_in_smp;
66 struct dma_edesc *dma_entx;
67 struct dma_desc *dma_tx;
68 union {
69 struct sk_buff **tx_skbuff;
70 struct xdp_frame **xdpf;
71 };
72 struct stmmac_tx_info *tx_skbuff_dma;
73 struct xsk_buff_pool *xsk_pool;
74 u32 xsk_frames_done;
75 unsigned int cur_tx;
76 unsigned int dirty_tx;
77 dma_addr_t dma_tx_phy;
78 dma_addr_t tx_tail_addr;
79 u32 mss;
80};
81
82struct stmmac_rx_buffer {
83 union {
84 struct {
85 struct page *page;
86 dma_addr_t addr;
87 __u32 page_offset;
88 };
89 struct xdp_buff *xdp;
90 };
91 struct page *sec_page;
92 dma_addr_t sec_addr;
93};
94
95struct stmmac_rx_queue {
96 u32 rx_count_frames;
97 u32 queue_index;
98 struct xdp_rxq_info xdp_rxq;
99 struct xsk_buff_pool *xsk_pool;
100 struct page_pool *page_pool;
101 struct stmmac_rx_buffer *buf_pool;
102 struct stmmac_priv *priv_data;
103 struct dma_extended_desc *dma_erx;
104 struct dma_desc *dma_rx ____cacheline_aligned_in_smp;
105 unsigned int cur_rx;
106 unsigned int dirty_rx;
107 unsigned int buf_alloc_num;
108 u32 rx_zeroc_thresh;
109 dma_addr_t dma_rx_phy;
110 u32 rx_tail_addr;
111 unsigned int state_saved;
112 struct {
113 struct sk_buff *skb;
114 unsigned int len;
115 unsigned int error;
116 } state;
117};
118
119struct stmmac_channel {
120 struct napi_struct rx_napi ____cacheline_aligned_in_smp;
121 struct napi_struct tx_napi ____cacheline_aligned_in_smp;
122 struct napi_struct rxtx_napi ____cacheline_aligned_in_smp;
123 struct stmmac_priv *priv_data;
124 spinlock_t lock;
125 u32 index;
126};
127
128struct stmmac_tc_entry {
129 bool in_use;
130 bool in_hw;
131 bool is_last;
132 bool is_frag;
133 void *frag_ptr;
134 unsigned int table_pos;
135 u32 handle;
136 u32 prio;
137 struct {
138 u32 match_data;
139 u32 match_en;
140 u8 af:1;
141 u8 rf:1;
142 u8 im:1;
143 u8 nc:1;
144 u8 res1:4;
145 u8 frame_offset;
146 u8 ok_index;
147 u8 dma_ch_no;
148 u32 res2;
149 } __packed val;
150};
151
152#define STMMAC_PPS_MAX 4
153struct stmmac_pps_cfg {
154 bool available;
155 struct timespec64 start;
156 struct timespec64 period;
157};
158
159struct stmmac_rss {
160 int enable;
161 u8 key[STMMAC_RSS_HASH_KEY_SIZE];
162 u32 table[STMMAC_RSS_MAX_TABLE_SIZE];
163};
164
165#define STMMAC_FLOW_ACTION_DROP BIT(0)
166struct stmmac_flow_entry {
167 unsigned long cookie;
168 unsigned long action;
169 u8 ip_proto;
170 int in_use;
171 int idx;
172 int is_l4;
173};
174
175struct stmmac_priv {
176
177 u32 tx_coal_frames[MTL_MAX_TX_QUEUES];
178 u32 tx_coal_timer[MTL_MAX_TX_QUEUES];
179 u32 rx_coal_frames[MTL_MAX_TX_QUEUES];
180
181 int tx_coalesce;
182 int hwts_tx_en;
183 bool tx_path_in_lpi_mode;
184 bool tso;
185 int sph;
186 int sph_cap;
187 u32 sarc_type;
188
189 unsigned int dma_buf_sz;
190 unsigned int rx_copybreak;
191 u32 rx_riwt[MTL_MAX_TX_QUEUES];
192 int hwts_rx_en;
193
194 void __iomem *ioaddr;
195 struct net_device *dev;
196 struct device *device;
197 struct mac_device_info *hw;
198 int (*hwif_quirks)(struct stmmac_priv *priv);
199 struct mutex lock;
200
201
202 struct stmmac_rx_queue rx_queue[MTL_MAX_RX_QUEUES];
203 unsigned int dma_rx_size;
204
205
206 struct stmmac_tx_queue tx_queue[MTL_MAX_TX_QUEUES];
207 unsigned int dma_tx_size;
208
209
210 struct stmmac_channel channel[STMMAC_CH_MAX];
211
212 int speed;
213 unsigned int flow_ctrl;
214 unsigned int pause;
215 struct mii_bus *mii;
216 int mii_irq[PHY_MAX_ADDR];
217
218 struct phylink_config phylink_config;
219 struct phylink *phylink;
220
221 struct stmmac_extra_stats xstats ____cacheline_aligned_in_smp;
222 struct stmmac_safety_stats sstats;
223 struct plat_stmmacenet_data *plat;
224 struct dma_features dma_cap;
225 struct stmmac_counters mmc;
226 int hw_cap_support;
227 int synopsys_id;
228 u32 msg_enable;
229 int wolopts;
230 int wol_irq;
231 int clk_csr;
232 struct timer_list eee_ctrl_timer;
233 int lpi_irq;
234 int eee_enabled;
235 int eee_active;
236 int tx_lpi_timer;
237 int tx_lpi_enabled;
238 int eee_tw_timer;
239 bool eee_sw_timer_en;
240 unsigned int mode;
241 unsigned int chain_mode;
242 int extend_desc;
243 struct hwtstamp_config tstamp_config;
244 struct ptp_clock *ptp_clock;
245 struct ptp_clock_info ptp_clock_ops;
246 unsigned int default_addend;
247 u32 sub_second_inc;
248 u32 systime_flags;
249 u32 adv_ts;
250 int use_riwt;
251 int irq_wake;
252 spinlock_t ptp_lock;
253
254 struct mutex aux_ts_lock;
255
256 void __iomem *mmcaddr;
257 void __iomem *ptpaddr;
258 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)];
259 int sfty_ce_irq;
260 int sfty_ue_irq;
261 int rx_irq[MTL_MAX_RX_QUEUES];
262 int tx_irq[MTL_MAX_TX_QUEUES];
263
264 char int_name_mac[IFNAMSIZ + 9];
265 char int_name_wol[IFNAMSIZ + 9];
266 char int_name_lpi[IFNAMSIZ + 9];
267 char int_name_sfty_ce[IFNAMSIZ + 10];
268 char int_name_sfty_ue[IFNAMSIZ + 10];
269 char int_name_rx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 14];
270 char int_name_tx_irq[MTL_MAX_TX_QUEUES][IFNAMSIZ + 18];
271
272#ifdef CONFIG_DEBUG_FS
273 struct dentry *dbgfs_dir;
274#endif
275
276 unsigned long state;
277 struct workqueue_struct *wq;
278 struct work_struct service_task;
279
280
281 unsigned long fpe_task_state;
282 struct workqueue_struct *fpe_wq;
283 struct work_struct fpe_task;
284 char wq_name[IFNAMSIZ + 4];
285
286
287 unsigned int tc_entries_max;
288 unsigned int tc_off_max;
289 struct stmmac_tc_entry *tc_entries;
290 unsigned int flow_entries_max;
291 struct stmmac_flow_entry *flow_entries;
292
293
294 struct stmmac_pps_cfg pps[STMMAC_PPS_MAX];
295
296
297 struct stmmac_rss rss;
298
299
300 unsigned long *af_xdp_zc_qps;
301 struct bpf_prog *xdp_prog;
302};
303
304enum stmmac_state {
305 STMMAC_DOWN,
306 STMMAC_RESET_REQUESTED,
307 STMMAC_RESETING,
308 STMMAC_SERVICE_SCHED,
309};
310
311int stmmac_mdio_unregister(struct net_device *ndev);
312int stmmac_mdio_register(struct net_device *ndev);
313int stmmac_mdio_reset(struct mii_bus *mii);
314int stmmac_xpcs_setup(struct mii_bus *mii);
315void stmmac_set_ethtool_ops(struct net_device *netdev);
316
317void stmmac_ptp_register(struct stmmac_priv *priv);
318void stmmac_ptp_unregister(struct stmmac_priv *priv);
319int stmmac_open(struct net_device *dev);
320int stmmac_release(struct net_device *dev);
321int stmmac_resume(struct device *dev);
322int stmmac_suspend(struct device *dev);
323int stmmac_dvr_remove(struct device *dev);
324int stmmac_dvr_probe(struct device *device,
325 struct plat_stmmacenet_data *plat_dat,
326 struct stmmac_resources *res);
327void stmmac_disable_eee_mode(struct stmmac_priv *priv);
328bool stmmac_eee_init(struct stmmac_priv *priv);
329int stmmac_reinit_queues(struct net_device *dev, u32 rx_cnt, u32 tx_cnt);
330int stmmac_reinit_ringparam(struct net_device *dev, u32 rx_size, u32 tx_size);
331int stmmac_bus_clks_config(struct stmmac_priv *priv, bool enabled);
332void stmmac_fpe_handshake(struct stmmac_priv *priv, bool enable);
333
334static inline bool stmmac_xdp_is_enabled(struct stmmac_priv *priv)
335{
336 return !!priv->xdp_prog;
337}
338
339static inline unsigned int stmmac_rx_offset(struct stmmac_priv *priv)
340{
341 if (stmmac_xdp_is_enabled(priv))
342 return XDP_PACKET_HEADROOM;
343
344 return 0;
345}
346
347void stmmac_disable_rx_queue(struct stmmac_priv *priv, u32 queue);
348void stmmac_enable_rx_queue(struct stmmac_priv *priv, u32 queue);
349void stmmac_disable_tx_queue(struct stmmac_priv *priv, u32 queue);
350void stmmac_enable_tx_queue(struct stmmac_priv *priv, u32 queue);
351int stmmac_xsk_wakeup(struct net_device *dev, u32 queue, u32 flags);
352struct timespec64 stmmac_calc_tas_basetime(ktime_t old_base_time,
353 ktime_t current_time,
354 u64 cycle_time);
355
356#if IS_ENABLED(CONFIG_STMMAC_SELFTESTS)
357void stmmac_selftest_run(struct net_device *dev,
358 struct ethtool_test *etest, u64 *buf);
359void stmmac_selftest_get_strings(struct stmmac_priv *priv, u8 *data);
360int stmmac_selftest_get_count(struct stmmac_priv *priv);
361#else
362static inline void stmmac_selftest_run(struct net_device *dev,
363 struct ethtool_test *etest, u64 *buf)
364{
365
366}
367static inline void stmmac_selftest_get_strings(struct stmmac_priv *priv,
368 u8 *data)
369{
370
371}
372static inline int stmmac_selftest_get_count(struct stmmac_priv *priv)
373{
374 return -EOPNOTSUPP;
375}
376#endif
377
378#endif
379
