linux/drivers/net/ethernet/qlogic/qed/qed_hsi.h
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   1/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) */
   2/* QLogic qed NIC Driver
   3 * Copyright (c) 2015-2017  QLogic Corporation
   4 * Copyright (c) 2019-2020 Marvell International Ltd.
   5 */
   6
   7#ifndef _QED_HSI_H
   8#define _QED_HSI_H
   9
  10#include <linux/types.h>
  11#include <linux/io.h>
  12#include <linux/bitops.h>
  13#include <linux/delay.h>
  14#include <linux/kernel.h>
  15#include <linux/list.h>
  16#include <linux/slab.h>
  17#include <linux/qed/common_hsi.h>
  18#include <linux/qed/storage_common.h>
  19#include <linux/qed/tcp_common.h>
  20#include <linux/qed/fcoe_common.h>
  21#include <linux/qed/eth_common.h>
  22#include <linux/qed/iscsi_common.h>
  23#include <linux/qed/nvmetcp_common.h>
  24#include <linux/qed/iwarp_common.h>
  25#include <linux/qed/rdma_common.h>
  26#include <linux/qed/roce_common.h>
  27#include <linux/qed/qed_fcoe_if.h>
  28
  29struct qed_hwfn;
  30struct qed_ptt;
  31
  32/* Opcodes for the event ring */
  33enum common_event_opcode {
  34        COMMON_EVENT_PF_START,
  35        COMMON_EVENT_PF_STOP,
  36        COMMON_EVENT_VF_START,
  37        COMMON_EVENT_VF_STOP,
  38        COMMON_EVENT_VF_PF_CHANNEL,
  39        COMMON_EVENT_VF_FLR,
  40        COMMON_EVENT_PF_UPDATE,
  41        COMMON_EVENT_MALICIOUS_VF,
  42        COMMON_EVENT_RL_UPDATE,
  43        COMMON_EVENT_EMPTY,
  44        MAX_COMMON_EVENT_OPCODE
  45};
  46
  47/* Common Ramrod Command IDs */
  48enum common_ramrod_cmd_id {
  49        COMMON_RAMROD_UNUSED,
  50        COMMON_RAMROD_PF_START,
  51        COMMON_RAMROD_PF_STOP,
  52        COMMON_RAMROD_VF_START,
  53        COMMON_RAMROD_VF_STOP,
  54        COMMON_RAMROD_PF_UPDATE,
  55        COMMON_RAMROD_RL_UPDATE,
  56        COMMON_RAMROD_EMPTY,
  57        MAX_COMMON_RAMROD_CMD_ID
  58};
  59
  60/* How ll2 should deal with packet upon errors */
  61enum core_error_handle {
  62        LL2_DROP_PACKET,
  63        LL2_DO_NOTHING,
  64        LL2_ASSERT,
  65        MAX_CORE_ERROR_HANDLE
  66};
  67
  68/* Opcodes for the event ring */
  69enum core_event_opcode {
  70        CORE_EVENT_TX_QUEUE_START,
  71        CORE_EVENT_TX_QUEUE_STOP,
  72        CORE_EVENT_RX_QUEUE_START,
  73        CORE_EVENT_RX_QUEUE_STOP,
  74        CORE_EVENT_RX_QUEUE_FLUSH,
  75        CORE_EVENT_TX_QUEUE_UPDATE,
  76        CORE_EVENT_QUEUE_STATS_QUERY,
  77        MAX_CORE_EVENT_OPCODE
  78};
  79
  80/* The L4 pseudo checksum mode for Core */
  81enum core_l4_pseudo_checksum_mode {
  82        CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH,
  83        CORE_L4_PSEUDO_CSUM_ZERO_LENGTH,
  84        MAX_CORE_L4_PSEUDO_CHECKSUM_MODE
  85};
  86
  87/* Light-L2 RX Producers in Tstorm RAM */
  88struct core_ll2_port_stats {
  89        struct regpair gsi_invalid_hdr;
  90        struct regpair gsi_invalid_pkt_length;
  91        struct regpair gsi_unsupported_pkt_typ;
  92        struct regpair gsi_crcchksm_error;
  93};
  94
  95/* LL2 TX Per Queue Stats */
  96struct core_ll2_pstorm_per_queue_stat {
  97        struct regpair sent_ucast_bytes;
  98        struct regpair sent_mcast_bytes;
  99        struct regpair sent_bcast_bytes;
 100        struct regpair sent_ucast_pkts;
 101        struct regpair sent_mcast_pkts;
 102        struct regpair sent_bcast_pkts;
 103        struct regpair error_drop_pkts;
 104};
 105
 106/* Light-L2 RX Producers in Tstorm RAM */
 107struct core_ll2_rx_prod {
 108        __le16 bd_prod;
 109        __le16 cqe_prod;
 110};
 111
 112struct core_ll2_tstorm_per_queue_stat {
 113        struct regpair packet_too_big_discard;
 114        struct regpair no_buff_discard;
 115};
 116
 117struct core_ll2_ustorm_per_queue_stat {
 118        struct regpair rcv_ucast_bytes;
 119        struct regpair rcv_mcast_bytes;
 120        struct regpair rcv_bcast_bytes;
 121        struct regpair rcv_ucast_pkts;
 122        struct regpair rcv_mcast_pkts;
 123        struct regpair rcv_bcast_pkts;
 124};
 125
 126/* Structure for doorbell data, in PWM mode, for RX producers update. */
 127struct core_pwm_prod_update_data {
 128        __le16 icid; /* internal CID */
 129        u8 reserved0;
 130        u8 params;
 131#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_MASK    0x3
 132#define CORE_PWM_PROD_UPDATE_DATA_AGG_CMD_SHIFT   0
 133#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_MASK  0x3F  /* Set 0 */
 134#define CORE_PWM_PROD_UPDATE_DATA_RESERVED1_SHIFT 2
 135        struct core_ll2_rx_prod prod; /* Producers */
 136};
 137
 138/* Core Ramrod Command IDs (light L2) */
 139enum core_ramrod_cmd_id {
 140        CORE_RAMROD_UNUSED,
 141        CORE_RAMROD_RX_QUEUE_START,
 142        CORE_RAMROD_TX_QUEUE_START,
 143        CORE_RAMROD_RX_QUEUE_STOP,
 144        CORE_RAMROD_TX_QUEUE_STOP,
 145        CORE_RAMROD_RX_QUEUE_FLUSH,
 146        CORE_RAMROD_TX_QUEUE_UPDATE,
 147        CORE_RAMROD_QUEUE_STATS_QUERY,
 148        MAX_CORE_RAMROD_CMD_ID
 149};
 150
 151/* Core RX CQE Type for Light L2 */
 152enum core_roce_flavor_type {
 153        CORE_ROCE,
 154        CORE_RROCE,
 155        MAX_CORE_ROCE_FLAVOR_TYPE
 156};
 157
 158/* Specifies how ll2 should deal with packets errors: packet_too_big and
 159 * no_buff.
 160 */
 161struct core_rx_action_on_error {
 162        u8 error_type;
 163#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK     0x3
 164#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT    0
 165#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK            0x3
 166#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT           2
 167#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK           0xF
 168#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT          4
 169};
 170
 171/* Core RX BD for Light L2 */
 172struct core_rx_bd {
 173        struct regpair addr;
 174        __le16 reserved[4];
 175};
 176
 177/* Core RX CM offload BD for Light L2 */
 178struct core_rx_bd_with_buff_len {
 179        struct regpair addr;
 180        __le16 buff_length;
 181        __le16 reserved[3];
 182};
 183
 184/* Core RX CM offload BD for Light L2 */
 185union core_rx_bd_union {
 186        struct core_rx_bd rx_bd;
 187        struct core_rx_bd_with_buff_len rx_bd_with_len;
 188};
 189
 190/* Opaque Data for Light L2 RX CQE */
 191struct core_rx_cqe_opaque_data {
 192        __le32 data[2];
 193};
 194
 195/* Core RX CQE Type for Light L2 */
 196enum core_rx_cqe_type {
 197        CORE_RX_CQE_ILLEGAL_TYPE,
 198        CORE_RX_CQE_TYPE_REGULAR,
 199        CORE_RX_CQE_TYPE_GSI_OFFLOAD,
 200        CORE_RX_CQE_TYPE_SLOW_PATH,
 201        MAX_CORE_RX_CQE_TYPE
 202};
 203
 204/* Core RX CQE for Light L2 */
 205struct core_rx_fast_path_cqe {
 206        u8 type;
 207        u8 placement_offset;
 208        struct parsing_and_err_flags parse_flags;
 209        __le16 packet_length;
 210        __le16 vlan;
 211        struct core_rx_cqe_opaque_data opaque_data;
 212        struct parsing_err_flags err_flags;
 213        __le16 reserved0;
 214        __le32 reserved1[3];
 215};
 216
 217/* Core Rx CM offload CQE */
 218struct core_rx_gsi_offload_cqe {
 219        u8 type;
 220        u8 data_length_error;
 221        struct parsing_and_err_flags parse_flags;
 222        __le16 data_length;
 223        __le16 vlan;
 224        __le32 src_mac_addrhi;
 225        __le16 src_mac_addrlo;
 226        __le16 qp_id;
 227        __le32 src_qp;
 228        struct core_rx_cqe_opaque_data opaque_data;
 229        __le32 reserved;
 230};
 231
 232/* Core RX CQE for Light L2 */
 233struct core_rx_slow_path_cqe {
 234        u8 type;
 235        u8 ramrod_cmd_id;
 236        __le16 echo;
 237        struct core_rx_cqe_opaque_data opaque_data;
 238        __le32 reserved1[5];
 239};
 240
 241/* Core RX CM offload BD for Light L2 */
 242union core_rx_cqe_union {
 243        struct core_rx_fast_path_cqe rx_cqe_fp;
 244        struct core_rx_gsi_offload_cqe rx_cqe_gsi;
 245        struct core_rx_slow_path_cqe rx_cqe_sp;
 246};
 247
 248/* Ramrod data for rx queue start ramrod */
 249struct core_rx_start_ramrod_data {
 250        struct regpair bd_base;
 251        struct regpair cqe_pbl_addr;
 252        __le16 mtu;
 253        __le16 sb_id;
 254        u8 sb_index;
 255        u8 complete_cqe_flg;
 256        u8 complete_event_flg;
 257        u8 drop_ttl0_flg;
 258        __le16 num_of_pbl_pages;
 259        u8 inner_vlan_stripping_en;
 260        u8 report_outer_vlan;
 261        u8 queue_id;
 262        u8 main_func_queue;
 263        u8 mf_si_bcast_accept_all;
 264        u8 mf_si_mcast_accept_all;
 265        struct core_rx_action_on_error action_on_error;
 266        u8 gsi_offload_flag;
 267        u8 vport_id_valid;
 268        u8 vport_id;
 269        u8 zero_prod_flg;
 270        u8 wipe_inner_vlan_pri_en;
 271        u8 reserved[2];
 272};
 273
 274/* Ramrod data for rx queue stop ramrod */
 275struct core_rx_stop_ramrod_data {
 276        u8 complete_cqe_flg;
 277        u8 complete_event_flg;
 278        u8 queue_id;
 279        u8 reserved1;
 280        __le16 reserved2[2];
 281};
 282
 283/* Flags for Core TX BD */
 284struct core_tx_bd_data {
 285        __le16 as_bitfield;
 286#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK            0x1
 287#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT           0
 288#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK             0x1
 289#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT            1
 290#define CORE_TX_BD_DATA_START_BD_MASK                   0x1
 291#define CORE_TX_BD_DATA_START_BD_SHIFT                  2
 292#define CORE_TX_BD_DATA_IP_CSUM_MASK                    0x1
 293#define CORE_TX_BD_DATA_IP_CSUM_SHIFT                   3
 294#define CORE_TX_BD_DATA_L4_CSUM_MASK                    0x1
 295#define CORE_TX_BD_DATA_L4_CSUM_SHIFT                   4
 296#define CORE_TX_BD_DATA_IPV6_EXT_MASK                   0x1
 297#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT                  5
 298#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK                0x1
 299#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT               6
 300#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK        0x1
 301#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT       7
 302#define CORE_TX_BD_DATA_NBDS_MASK                       0xF
 303#define CORE_TX_BD_DATA_NBDS_SHIFT                      8
 304#define CORE_TX_BD_DATA_ROCE_FLAV_MASK                  0x1
 305#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT                 12
 306#define CORE_TX_BD_DATA_IP_LEN_MASK                     0x1
 307#define CORE_TX_BD_DATA_IP_LEN_SHIFT                    13
 308#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK     0x1
 309#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT    14
 310#define CORE_TX_BD_DATA_RESERVED0_MASK                  0x1
 311#define CORE_TX_BD_DATA_RESERVED0_SHIFT                 15
 312};
 313
 314/* Core TX BD for Light L2 */
 315struct core_tx_bd {
 316        struct regpair addr;
 317        __le16 nbytes;
 318        __le16 nw_vlan_or_lb_echo;
 319        struct core_tx_bd_data bd_data;
 320        __le16 bitfield1;
 321#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK         0x3FFF
 322#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT        0
 323#define CORE_TX_BD_TX_DST_MASK                  0x3
 324#define CORE_TX_BD_TX_DST_SHIFT                 14
 325};
 326
 327/* Light L2 TX Destination */
 328enum core_tx_dest {
 329        CORE_TX_DEST_NW,
 330        CORE_TX_DEST_LB,
 331        CORE_TX_DEST_RESERVED,
 332        CORE_TX_DEST_DROP,
 333        MAX_CORE_TX_DEST
 334};
 335
 336/* Ramrod data for tx queue start ramrod */
 337struct core_tx_start_ramrod_data {
 338        struct regpair pbl_base_addr;
 339        __le16 mtu;
 340        __le16 sb_id;
 341        u8 sb_index;
 342        u8 stats_en;
 343        u8 stats_id;
 344        u8 conn_type;
 345        __le16 pbl_size;
 346        __le16 qm_pq_id;
 347        u8 gsi_offload_flag;
 348        u8 ctx_stats_en;
 349        u8 vport_id_valid;
 350        u8 vport_id;
 351        u8 enforce_security_flag;
 352        u8 reserved[7];
 353};
 354
 355/* Ramrod data for tx queue stop ramrod */
 356struct core_tx_stop_ramrod_data {
 357        __le32 reserved0[2];
 358};
 359
 360/* Ramrod data for tx queue update ramrod */
 361struct core_tx_update_ramrod_data {
 362        u8 update_qm_pq_id_flg;
 363        u8 reserved0;
 364        __le16 qm_pq_id;
 365        __le32 reserved1;
 366};
 367
 368/* Enum flag for what type of dcb data to update */
 369enum dcb_dscp_update_mode {
 370        DONT_UPDATE_DCB_DSCP,
 371        UPDATE_DCB,
 372        UPDATE_DSCP,
 373        UPDATE_DCB_DSCP,
 374        MAX_DCB_DSCP_UPDATE_MODE
 375};
 376
 377/* The core storm context for the Ystorm */
 378struct ystorm_core_conn_st_ctx {
 379        __le32 reserved[4];
 380};
 381
 382/* The core storm context for the Pstorm */
 383struct pstorm_core_conn_st_ctx {
 384        __le32 reserved[20];
 385};
 386
 387/* Core Slowpath Connection storm context of Xstorm */
 388struct xstorm_core_conn_st_ctx {
 389        __le32 spq_base_lo;
 390        __le32 spq_base_hi;
 391        struct regpair consolid_base_addr;
 392        __le16 spq_cons;
 393        __le16 consolid_cons;
 394        __le32 reserved0[55];
 395};
 396
 397struct e4_xstorm_core_conn_ag_ctx {
 398        u8 reserved0;
 399        u8 state;
 400        u8 flags0;
 401#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK    0x1
 402#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT   0
 403#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK       0x1
 404#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT      1
 405#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK       0x1
 406#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT      2
 407#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK    0x1
 408#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT   3
 409#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK       0x1
 410#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT      4
 411#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK       0x1
 412#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT      5
 413#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK       0x1
 414#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT      6
 415#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK       0x1
 416#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT      7
 417        u8 flags1;
 418#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK       0x1
 419#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT      0
 420#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK       0x1
 421#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT      1
 422#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK       0x1
 423#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT      2
 424#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK           0x1
 425#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT          3
 426#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK           0x1
 427#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT          4
 428#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK           0x1
 429#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT          5
 430#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK  0x1
 431#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6
 432#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK    0x1
 433#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT   7
 434        u8 flags2;
 435#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 436#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    0
 437#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 438#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    2
 439#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 440#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    4
 441#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 442#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT    6
 443        u8 flags3;
 444#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 445#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT    0
 446#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 447#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT    2
 448#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 449#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT    4
 450#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK     0x3
 451#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT    6
 452        u8 flags4;
 453#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK     0x3
 454#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT    0
 455#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK     0x3
 456#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT    2
 457#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK    0x3
 458#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT   4
 459#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK    0x3
 460#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT   6
 461        u8 flags5;
 462#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK    0x3
 463#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT   0
 464#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK    0x3
 465#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT   2
 466#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK    0x3
 467#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT   4
 468#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK    0x3
 469#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT   6
 470        u8 flags6;
 471#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK        0x3
 472#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT       0
 473#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK                    0x3
 474#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT                   2
 475#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK                   0x3
 476#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT                  4
 477#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK            0x3
 478#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT           6
 479        u8 flags7;
 480#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK        0x3
 481#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT       0
 482#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK      0x3
 483#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT     2
 484#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK       0x3
 485#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT      4
 486#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
 487#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          6
 488#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
 489#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          7
 490        u8 flags8;
 491#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK   0x1
 492#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT  0
 493#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK   0x1
 494#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT  1
 495#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK   0x1
 496#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT  2
 497#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK   0x1
 498#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT  3
 499#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK   0x1
 500#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT  4
 501#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK   0x1
 502#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT  5
 503#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK   0x1
 504#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT  6
 505#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK   0x1
 506#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT  7
 507        u8 flags9;
 508#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK                  0x1
 509#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT                 0
 510#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK                  0x1
 511#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT                 1
 512#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK                  0x1
 513#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT                 2
 514#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK                  0x1
 515#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT                 3
 516#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK                  0x1
 517#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT                 4
 518#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK                  0x1
 519#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT                 5
 520#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK     0x1
 521#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT    6
 522#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK                  0x1
 523#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT                 7
 524        u8 flags10;
 525#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK                0x1
 526#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT               0
 527#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK         0x1
 528#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT        1
 529#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK             0x1
 530#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT            2
 531#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK              0x1
 532#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT             3
 533#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK            0x1
 534#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT           4
 535#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK                  0x1
 536#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT                 5
 537#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK              0x1
 538#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT             6
 539#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK              0x1
 540#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT             7
 541        u8 flags11;
 542#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK      0x1
 543#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT     0
 544#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK      0x1
 545#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT     1
 546#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK  0x1
 547#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2
 548#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 549#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        3
 550#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 551#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        4
 552#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 553#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        5
 554#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK    0x1
 555#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT   6
 556#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK         0x1
 557#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT        7
 558        u8 flags12;
 559#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK        0x1
 560#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT       0
 561#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK        0x1
 562#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT       1
 563#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK    0x1
 564#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT   2
 565#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK    0x1
 566#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT   3
 567#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK        0x1
 568#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT       4
 569#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK        0x1
 570#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT       5
 571#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK        0x1
 572#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT       6
 573#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK        0x1
 574#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT       7
 575        u8 flags13;
 576#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK        0x1
 577#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT       0
 578#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK        0x1
 579#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT       1
 580#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK    0x1
 581#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT   2
 582#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK    0x1
 583#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT   3
 584#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK    0x1
 585#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT   4
 586#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK    0x1
 587#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT   5
 588#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK    0x1
 589#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT   6
 590#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK    0x1
 591#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT   7
 592        u8 flags14;
 593#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK   0x1
 594#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT  0
 595#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK   0x1
 596#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT  1
 597#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK   0x1
 598#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT  2
 599#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK   0x1
 600#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT  3
 601#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK   0x1
 602#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT  4
 603#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK   0x1
 604#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT  5
 605#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK    0x3
 606#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT   6
 607        u8 byte2;
 608        __le16 physical_q0;
 609        __le16 consolid_prod;
 610        __le16 reserved16;
 611        __le16 tx_bd_cons;
 612        __le16 tx_bd_or_spq_prod;
 613        __le16 updated_qm_pq_id;
 614        __le16 conn_dpi;
 615        u8 byte3;
 616        u8 byte4;
 617        u8 byte5;
 618        u8 byte6;
 619        __le32 reg0;
 620        __le32 reg1;
 621        __le32 reg2;
 622        __le32 reg3;
 623        __le32 reg4;
 624        __le32 reg5;
 625        __le32 reg6;
 626        __le16 word7;
 627        __le16 word8;
 628        __le16 word9;
 629        __le16 word10;
 630        __le32 reg7;
 631        __le32 reg8;
 632        __le32 reg9;
 633        u8 byte7;
 634        u8 byte8;
 635        u8 byte9;
 636        u8 byte10;
 637        u8 byte11;
 638        u8 byte12;
 639        u8 byte13;
 640        u8 byte14;
 641        u8 byte15;
 642        u8 e5_reserved;
 643        __le16 word11;
 644        __le32 reg10;
 645        __le32 reg11;
 646        __le32 reg12;
 647        __le32 reg13;
 648        __le32 reg14;
 649        __le32 reg15;
 650        __le32 reg16;
 651        __le32 reg17;
 652        __le32 reg18;
 653        __le32 reg19;
 654        __le16 word12;
 655        __le16 word13;
 656        __le16 word14;
 657        __le16 word15;
 658};
 659
 660struct e4_tstorm_core_conn_ag_ctx {
 661        u8 byte0;
 662        u8 byte1;
 663        u8 flags0;
 664#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
 665#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
 666#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
 667#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
 668#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK    0x1
 669#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT   2
 670#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK    0x1
 671#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT   3
 672#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK    0x1
 673#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT   4
 674#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK    0x1
 675#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT   5
 676#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 677#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    6
 678        u8 flags1;
 679#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 680#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    0
 681#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 682#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    2
 683#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 684#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT    4
 685#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 686#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT    6
 687        u8 flags2;
 688#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 689#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT    0
 690#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 691#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT    2
 692#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK     0x3
 693#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT    4
 694#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK     0x3
 695#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT    6
 696        u8 flags3;
 697#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK     0x3
 698#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT    0
 699#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK    0x3
 700#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT   2
 701#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK   0x1
 702#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT  4
 703#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK   0x1
 704#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT  5
 705#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK   0x1
 706#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT  6
 707#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK   0x1
 708#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT  7
 709        u8 flags4;
 710#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK           0x1
 711#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT          0
 712#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK           0x1
 713#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT          1
 714#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK           0x1
 715#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT          2
 716#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK           0x1
 717#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT          3
 718#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK           0x1
 719#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT          4
 720#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK           0x1
 721#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT          5
 722#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK          0x1
 723#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT         6
 724#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
 725#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        7
 726        u8 flags5;
 727#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
 728#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        0
 729#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
 730#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        1
 731#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
 732#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        2
 733#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
 734#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        3
 735#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 736#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        4
 737#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 738#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        5
 739#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 740#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        6
 741#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK         0x1
 742#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT        7
 743        __le32 reg0;
 744        __le32 reg1;
 745        __le32 reg2;
 746        __le32 reg3;
 747        __le32 reg4;
 748        __le32 reg5;
 749        __le32 reg6;
 750        __le32 reg7;
 751        __le32 reg8;
 752        u8 byte2;
 753        u8 byte3;
 754        __le16 word0;
 755        u8 byte4;
 756        u8 byte5;
 757        __le16 word1;
 758        __le16 word2;
 759        __le16 word3;
 760        __le32 ll2_rx_prod;
 761        __le32 reg10;
 762};
 763
 764struct e4_ustorm_core_conn_ag_ctx {
 765        u8 reserved;
 766        u8 byte1;
 767        u8 flags0;
 768#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
 769#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
 770#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
 771#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
 772#define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
 773#define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
 774#define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
 775#define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
 776#define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
 777#define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
 778        u8 flags1;
 779#define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK     0x3
 780#define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT    0
 781#define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK     0x3
 782#define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT    2
 783#define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK     0x3
 784#define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT    4
 785#define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK     0x3
 786#define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT    6
 787        u8 flags2;
 788#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
 789#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
 790#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
 791#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
 792#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
 793#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
 794#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK           0x1
 795#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT          3
 796#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK           0x1
 797#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT          4
 798#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK           0x1
 799#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT          5
 800#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK           0x1
 801#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT          6
 802#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
 803#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        7
 804        u8 flags3;
 805#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
 806#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        0
 807#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
 808#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        1
 809#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
 810#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        2
 811#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
 812#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        3
 813#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK         0x1
 814#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT        4
 815#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK         0x1
 816#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT        5
 817#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK         0x1
 818#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT        6
 819#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK         0x1
 820#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT        7
 821        u8 byte2;
 822        u8 byte3;
 823        __le16 word0;
 824        __le16 word1;
 825        __le32 rx_producers;
 826        __le32 reg1;
 827        __le32 reg2;
 828        __le32 reg3;
 829        __le16 word2;
 830        __le16 word3;
 831};
 832
 833/* The core storm context for the Mstorm */
 834struct mstorm_core_conn_st_ctx {
 835        __le32 reserved[40];
 836};
 837
 838/* The core storm context for the Ustorm */
 839struct ustorm_core_conn_st_ctx {
 840        __le32 reserved[20];
 841};
 842
 843/* The core storm context for the Tstorm */
 844struct tstorm_core_conn_st_ctx {
 845        __le32 reserved[4];
 846};
 847
 848/* core connection context */
 849struct e4_core_conn_context {
 850        struct ystorm_core_conn_st_ctx ystorm_st_context;
 851        struct regpair ystorm_st_padding[2];
 852        struct pstorm_core_conn_st_ctx pstorm_st_context;
 853        struct regpair pstorm_st_padding[2];
 854        struct xstorm_core_conn_st_ctx xstorm_st_context;
 855        struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context;
 856        struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context;
 857        struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context;
 858        struct mstorm_core_conn_st_ctx mstorm_st_context;
 859        struct ustorm_core_conn_st_ctx ustorm_st_context;
 860        struct regpair ustorm_st_padding[2];
 861        struct tstorm_core_conn_st_ctx tstorm_st_context;
 862        struct regpair tstorm_st_padding[2];
 863};
 864
 865struct eth_mstorm_per_pf_stat {
 866        struct regpair gre_discard_pkts;
 867        struct regpair vxlan_discard_pkts;
 868        struct regpair geneve_discard_pkts;
 869        struct regpair lb_discard_pkts;
 870};
 871
 872struct eth_mstorm_per_queue_stat {
 873        struct regpair ttl0_discard;
 874        struct regpair packet_too_big_discard;
 875        struct regpair no_buff_discard;
 876        struct regpair not_active_discard;
 877        struct regpair tpa_coalesced_pkts;
 878        struct regpair tpa_coalesced_events;
 879        struct regpair tpa_aborts_num;
 880        struct regpair tpa_coalesced_bytes;
 881};
 882
 883/* Ethernet TX Per PF */
 884struct eth_pstorm_per_pf_stat {
 885        struct regpair sent_lb_ucast_bytes;
 886        struct regpair sent_lb_mcast_bytes;
 887        struct regpair sent_lb_bcast_bytes;
 888        struct regpair sent_lb_ucast_pkts;
 889        struct regpair sent_lb_mcast_pkts;
 890        struct regpair sent_lb_bcast_pkts;
 891        struct regpair sent_gre_bytes;
 892        struct regpair sent_vxlan_bytes;
 893        struct regpair sent_geneve_bytes;
 894        struct regpair sent_mpls_bytes;
 895        struct regpair sent_gre_mpls_bytes;
 896        struct regpair sent_udp_mpls_bytes;
 897        struct regpair sent_gre_pkts;
 898        struct regpair sent_vxlan_pkts;
 899        struct regpair sent_geneve_pkts;
 900        struct regpair sent_mpls_pkts;
 901        struct regpair sent_gre_mpls_pkts;
 902        struct regpair sent_udp_mpls_pkts;
 903        struct regpair gre_drop_pkts;
 904        struct regpair vxlan_drop_pkts;
 905        struct regpair geneve_drop_pkts;
 906        struct regpair mpls_drop_pkts;
 907        struct regpair gre_mpls_drop_pkts;
 908        struct regpair udp_mpls_drop_pkts;
 909};
 910
 911/* Ethernet TX Per Queue Stats */
 912struct eth_pstorm_per_queue_stat {
 913        struct regpair sent_ucast_bytes;
 914        struct regpair sent_mcast_bytes;
 915        struct regpair sent_bcast_bytes;
 916        struct regpair sent_ucast_pkts;
 917        struct regpair sent_mcast_pkts;
 918        struct regpair sent_bcast_pkts;
 919        struct regpair error_drop_pkts;
 920};
 921
 922/* ETH Rx producers data */
 923struct eth_rx_rate_limit {
 924        __le16 mult;
 925        __le16 cnst;
 926        u8 add_sub_cnst;
 927        u8 reserved0;
 928        __le16 reserved1;
 929};
 930
 931/* Update RSS indirection table entry command */
 932struct eth_tstorm_rss_update_data {
 933        u8 valid;
 934        u8 vport_id;
 935        u8 ind_table_index;
 936        u8 reserved;
 937        __le16 ind_table_value;
 938        __le16 reserved1;
 939};
 940
 941struct eth_ustorm_per_pf_stat {
 942        struct regpair rcv_lb_ucast_bytes;
 943        struct regpair rcv_lb_mcast_bytes;
 944        struct regpair rcv_lb_bcast_bytes;
 945        struct regpair rcv_lb_ucast_pkts;
 946        struct regpair rcv_lb_mcast_pkts;
 947        struct regpair rcv_lb_bcast_pkts;
 948        struct regpair rcv_gre_bytes;
 949        struct regpair rcv_vxlan_bytes;
 950        struct regpair rcv_geneve_bytes;
 951        struct regpair rcv_gre_pkts;
 952        struct regpair rcv_vxlan_pkts;
 953        struct regpair rcv_geneve_pkts;
 954};
 955
 956struct eth_ustorm_per_queue_stat {
 957        struct regpair rcv_ucast_bytes;
 958        struct regpair rcv_mcast_bytes;
 959        struct regpair rcv_bcast_bytes;
 960        struct regpair rcv_ucast_pkts;
 961        struct regpair rcv_mcast_pkts;
 962        struct regpair rcv_bcast_pkts;
 963};
 964
 965/* Event Ring VF-PF Channel data */
 966struct vf_pf_channel_eqe_data {
 967        struct regpair msg_addr;
 968};
 969
 970/* Event Ring malicious VF data */
 971struct malicious_vf_eqe_data {
 972        u8 vf_id;
 973        u8 err_id;
 974        __le16 reserved[3];
 975};
 976
 977/* Event Ring initial cleanup data */
 978struct initial_cleanup_eqe_data {
 979        u8 vf_id;
 980        u8 reserved[7];
 981};
 982
 983/* Event Data Union */
 984union event_ring_data {
 985        u8 bytes[8];
 986        struct vf_pf_channel_eqe_data vf_pf_channel;
 987        struct iscsi_eqe_data iscsi_info;
 988        struct iscsi_connect_done_results iscsi_conn_done_info;
 989        union rdma_eqe_data rdma_data;
 990        struct malicious_vf_eqe_data malicious_vf;
 991        struct initial_cleanup_eqe_data vf_init_cleanup;
 992};
 993
 994/* Event Ring Entry */
 995struct event_ring_entry {
 996        u8 protocol_id;
 997        u8 opcode;
 998        u8 reserved0;
 999        u8 vf_id;
1000        __le16 echo;
1001        u8 fw_return_code;
1002        u8 flags;
1003#define EVENT_RING_ENTRY_ASYNC_MASK             0x1
1004#define EVENT_RING_ENTRY_ASYNC_SHIFT            0
1005#define EVENT_RING_ENTRY_RESERVED1_MASK         0x7F
1006#define EVENT_RING_ENTRY_RESERVED1_SHIFT        1
1007        union event_ring_data data;
1008};
1009
1010/* Event Ring Next Page Address */
1011struct event_ring_next_addr {
1012        struct regpair addr;
1013        __le32 reserved[2];
1014};
1015
1016/* Event Ring Element */
1017union event_ring_element {
1018        struct event_ring_entry entry;
1019        struct event_ring_next_addr next_addr;
1020};
1021
1022/* Ports mode */
1023enum fw_flow_ctrl_mode {
1024        flow_ctrl_pause,
1025        flow_ctrl_pfc,
1026        MAX_FW_FLOW_CTRL_MODE
1027};
1028
1029/* GFT profile type */
1030enum gft_profile_type {
1031        GFT_PROFILE_TYPE_4_TUPLE,
1032        GFT_PROFILE_TYPE_L4_DST_PORT,
1033        GFT_PROFILE_TYPE_IP_DST_ADDR,
1034        GFT_PROFILE_TYPE_IP_SRC_ADDR,
1035        GFT_PROFILE_TYPE_TUNNEL_TYPE,
1036        MAX_GFT_PROFILE_TYPE
1037};
1038
1039/* Major and Minor hsi Versions */
1040struct hsi_fp_ver_struct {
1041        u8 minor_ver_arr[2];
1042        u8 major_ver_arr[2];
1043};
1044
1045enum iwarp_ll2_tx_queues {
1046        IWARP_LL2_IN_ORDER_TX_QUEUE = 1,
1047        IWARP_LL2_ALIGNED_TX_QUEUE,
1048        IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE,
1049        IWARP_LL2_ERROR,
1050        MAX_IWARP_LL2_TX_QUEUES
1051};
1052
1053/* Malicious VF error ID */
1054enum malicious_vf_error_id {
1055        MALICIOUS_VF_NO_ERROR,
1056        VF_PF_CHANNEL_NOT_READY,
1057        VF_ZONE_MSG_NOT_VALID,
1058        VF_ZONE_FUNC_NOT_ENABLED,
1059        ETH_PACKET_TOO_SMALL,
1060        ETH_ILLEGAL_VLAN_MODE,
1061        ETH_MTU_VIOLATION,
1062        ETH_ILLEGAL_INBAND_TAGS,
1063        ETH_VLAN_INSERT_AND_INBAND_VLAN,
1064        ETH_ILLEGAL_NBDS,
1065        ETH_FIRST_BD_WO_SOP,
1066        ETH_INSUFFICIENT_BDS,
1067        ETH_ILLEGAL_LSO_HDR_NBDS,
1068        ETH_ILLEGAL_LSO_MSS,
1069        ETH_ZERO_SIZE_BD,
1070        ETH_ILLEGAL_LSO_HDR_LEN,
1071        ETH_INSUFFICIENT_PAYLOAD,
1072        ETH_EDPM_OUT_OF_SYNC,
1073        ETH_TUNN_IPV6_EXT_NBD_ERR,
1074        ETH_CONTROL_PACKET_VIOLATION,
1075        ETH_ANTI_SPOOFING_ERR,
1076        ETH_PACKET_SIZE_TOO_LARGE,
1077        CORE_ILLEGAL_VLAN_MODE,
1078        CORE_ILLEGAL_NBDS,
1079        CORE_FIRST_BD_WO_SOP,
1080        CORE_INSUFFICIENT_BDS,
1081        CORE_PACKET_TOO_SMALL,
1082        CORE_ILLEGAL_INBAND_TAGS,
1083        CORE_VLAN_INSERT_AND_INBAND_VLAN,
1084        CORE_MTU_VIOLATION,
1085        CORE_CONTROL_PACKET_VIOLATION,
1086        CORE_ANTI_SPOOFING_ERR,
1087        CORE_PACKET_SIZE_TOO_LARGE,
1088        CORE_ILLEGAL_BD_FLAGS,
1089        CORE_GSI_PACKET_VIOLATION,
1090        MAX_MALICIOUS_VF_ERROR_ID,
1091};
1092
1093/* Mstorm non-triggering VF zone */
1094struct mstorm_non_trigger_vf_zone {
1095        struct eth_mstorm_per_queue_stat eth_queue_stat;
1096        struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD];
1097};
1098
1099/* Mstorm VF zone */
1100struct mstorm_vf_zone {
1101        struct mstorm_non_trigger_vf_zone non_trigger;
1102};
1103
1104/* vlan header including TPID and TCI fields */
1105struct vlan_header {
1106        __le16 tpid;
1107        __le16 tci;
1108};
1109
1110/* outer tag configurations */
1111struct outer_tag_config_struct {
1112        u8 enable_stag_pri_change;
1113        u8 pri_map_valid;
1114        u8 reserved[2];
1115        struct vlan_header outer_tag;
1116        u8 inner_to_outer_pri_map[8];
1117};
1118
1119/* personality per PF */
1120enum personality_type {
1121        BAD_PERSONALITY_TYP,
1122        PERSONALITY_TCP_ULP,
1123        PERSONALITY_FCOE,
1124        PERSONALITY_RDMA_AND_ETH,
1125        PERSONALITY_RDMA,
1126        PERSONALITY_CORE,
1127        PERSONALITY_ETH,
1128        PERSONALITY_RESERVED,
1129        MAX_PERSONALITY_TYPE
1130};
1131
1132/* tunnel configuration */
1133struct pf_start_tunnel_config {
1134        u8 set_vxlan_udp_port_flg;
1135        u8 set_geneve_udp_port_flg;
1136        u8 set_no_inner_l2_vxlan_udp_port_flg;
1137        u8 tunnel_clss_vxlan;
1138        u8 tunnel_clss_l2geneve;
1139        u8 tunnel_clss_ipgeneve;
1140        u8 tunnel_clss_l2gre;
1141        u8 tunnel_clss_ipgre;
1142        __le16 vxlan_udp_port;
1143        __le16 geneve_udp_port;
1144        __le16 no_inner_l2_vxlan_udp_port;
1145        __le16 reserved[3];
1146};
1147
1148/* Ramrod data for PF start ramrod */
1149struct pf_start_ramrod_data {
1150        struct regpair event_ring_pbl_addr;
1151        struct regpair consolid_q_pbl_addr;
1152        struct pf_start_tunnel_config tunnel_config;
1153        __le16 event_ring_sb_id;
1154        u8 base_vf_id;
1155        u8 num_vfs;
1156        u8 event_ring_num_pages;
1157        u8 event_ring_sb_index;
1158        u8 path_id;
1159        u8 warning_as_error;
1160        u8 dont_log_ramrods;
1161        u8 personality;
1162        __le16 log_type_mask;
1163        u8 mf_mode;
1164        u8 integ_phase;
1165        u8 allow_npar_tx_switching;
1166        u8 reserved0;
1167        struct hsi_fp_ver_struct hsi_fp_ver;
1168        struct outer_tag_config_struct outer_tag_config;
1169};
1170
1171/* Data for port update ramrod */
1172struct protocol_dcb_data {
1173        u8 dcb_enable_flag;
1174        u8 dscp_enable_flag;
1175        u8 dcb_priority;
1176        u8 dcb_tc;
1177        u8 dscp_val;
1178        u8 dcb_dont_add_vlan0;
1179};
1180
1181/* Update tunnel configuration */
1182struct pf_update_tunnel_config {
1183        u8 update_rx_pf_clss;
1184        u8 update_rx_def_ucast_clss;
1185        u8 update_rx_def_non_ucast_clss;
1186        u8 set_vxlan_udp_port_flg;
1187        u8 set_geneve_udp_port_flg;
1188        u8 set_no_inner_l2_vxlan_udp_port_flg;
1189        u8 tunnel_clss_vxlan;
1190        u8 tunnel_clss_l2geneve;
1191        u8 tunnel_clss_ipgeneve;
1192        u8 tunnel_clss_l2gre;
1193        u8 tunnel_clss_ipgre;
1194        u8 reserved;
1195        __le16 vxlan_udp_port;
1196        __le16 geneve_udp_port;
1197        __le16 no_inner_l2_vxlan_udp_port;
1198        __le16 reserved1[3];
1199};
1200
1201/* Data for port update ramrod */
1202struct pf_update_ramrod_data {
1203        u8 update_eth_dcb_data_mode;
1204        u8 update_fcoe_dcb_data_mode;
1205        u8 update_iscsi_dcb_data_mode;
1206        u8 update_roce_dcb_data_mode;
1207        u8 update_rroce_dcb_data_mode;
1208        u8 update_iwarp_dcb_data_mode;
1209        u8 update_mf_vlan_flag;
1210        u8 update_enable_stag_pri_change;
1211        struct protocol_dcb_data eth_dcb_data;
1212        struct protocol_dcb_data fcoe_dcb_data;
1213        struct protocol_dcb_data iscsi_dcb_data;
1214        struct protocol_dcb_data roce_dcb_data;
1215        struct protocol_dcb_data rroce_dcb_data;
1216        struct protocol_dcb_data iwarp_dcb_data;
1217        __le16 mf_vlan;
1218        u8 enable_stag_pri_change;
1219        u8 reserved;
1220        struct pf_update_tunnel_config tunnel_config;
1221};
1222
1223/* Ports mode */
1224enum ports_mode {
1225        ENGX2_PORTX1,
1226        ENGX2_PORTX2,
1227        ENGX1_PORTX1,
1228        ENGX1_PORTX2,
1229        ENGX1_PORTX4,
1230        MAX_PORTS_MODE
1231};
1232
1233/* use to index in hsi_fp_[major|minor]_ver_arr per protocol */
1234enum protocol_version_array_key {
1235        ETH_VER_KEY = 0,
1236        ROCE_VER_KEY,
1237        MAX_PROTOCOL_VERSION_ARRAY_KEY
1238};
1239
1240/* RDMA TX Stats */
1241struct rdma_sent_stats {
1242        struct regpair sent_bytes;
1243        struct regpair sent_pkts;
1244};
1245
1246/* Pstorm non-triggering VF zone */
1247struct pstorm_non_trigger_vf_zone {
1248        struct eth_pstorm_per_queue_stat eth_queue_stat;
1249        struct rdma_sent_stats rdma_stats;
1250};
1251
1252/* Pstorm VF zone */
1253struct pstorm_vf_zone {
1254        struct pstorm_non_trigger_vf_zone non_trigger;
1255        struct regpair reserved[7];
1256};
1257
1258/* Ramrod Header of SPQE */
1259struct ramrod_header {
1260        __le32 cid;
1261        u8 cmd_id;
1262        u8 protocol_id;
1263        __le16 echo;
1264};
1265
1266/* RDMA RX Stats */
1267struct rdma_rcv_stats {
1268        struct regpair rcv_bytes;
1269        struct regpair rcv_pkts;
1270};
1271
1272/* Data for update QCN/DCQCN RL ramrod */
1273struct rl_update_ramrod_data {
1274        u8 qcn_update_param_flg;
1275        u8 dcqcn_update_param_flg;
1276        u8 rl_init_flg;
1277        u8 rl_start_flg;
1278        u8 rl_stop_flg;
1279        u8 rl_id_first;
1280        u8 rl_id_last;
1281        u8 rl_dc_qcn_flg;
1282        u8 dcqcn_reset_alpha_on_idle;
1283        u8 rl_bc_stage_th;
1284        u8 rl_timer_stage_th;
1285        u8 reserved1;
1286        __le32 rl_bc_rate;
1287        __le16 rl_max_rate;
1288        __le16 rl_r_ai;
1289        __le16 rl_r_hai;
1290        __le16 dcqcn_g;
1291        __le32 dcqcn_k_us;
1292        __le32 dcqcn_timeuot_us;
1293        __le32 qcn_timeuot_us;
1294        __le32 reserved2;
1295};
1296
1297/* Slowpath Element (SPQE) */
1298struct slow_path_element {
1299        struct ramrod_header hdr;
1300        struct regpair data_ptr;
1301};
1302
1303/* Tstorm non-triggering VF zone */
1304struct tstorm_non_trigger_vf_zone {
1305        struct rdma_rcv_stats rdma_stats;
1306};
1307
1308struct tstorm_per_port_stat {
1309        struct regpair trunc_error_discard;
1310        struct regpair mac_error_discard;
1311        struct regpair mftag_filter_discard;
1312        struct regpair eth_mac_filter_discard;
1313        struct regpair ll2_mac_filter_discard;
1314        struct regpair ll2_conn_disabled_discard;
1315        struct regpair iscsi_irregular_pkt;
1316        struct regpair fcoe_irregular_pkt;
1317        struct regpair roce_irregular_pkt;
1318        struct regpair iwarp_irregular_pkt;
1319        struct regpair eth_irregular_pkt;
1320        struct regpair toe_irregular_pkt;
1321        struct regpair preroce_irregular_pkt;
1322        struct regpair eth_gre_tunn_filter_discard;
1323        struct regpair eth_vxlan_tunn_filter_discard;
1324        struct regpair eth_geneve_tunn_filter_discard;
1325        struct regpair eth_gft_drop_pkt;
1326};
1327
1328/* Tstorm VF zone */
1329struct tstorm_vf_zone {
1330        struct tstorm_non_trigger_vf_zone non_trigger;
1331};
1332
1333/* Tunnel classification scheme */
1334enum tunnel_clss {
1335        TUNNEL_CLSS_MAC_VLAN = 0,
1336        TUNNEL_CLSS_MAC_VNI,
1337        TUNNEL_CLSS_INNER_MAC_VLAN,
1338        TUNNEL_CLSS_INNER_MAC_VNI,
1339        TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE,
1340        MAX_TUNNEL_CLSS
1341};
1342
1343/* Ustorm non-triggering VF zone */
1344struct ustorm_non_trigger_vf_zone {
1345        struct eth_ustorm_per_queue_stat eth_queue_stat;
1346        struct regpair vf_pf_msg_addr;
1347};
1348
1349/* Ustorm triggering VF zone */
1350struct ustorm_trigger_vf_zone {
1351        u8 vf_pf_msg_valid;
1352        u8 reserved[7];
1353};
1354
1355/* Ustorm VF zone */
1356struct ustorm_vf_zone {
1357        struct ustorm_non_trigger_vf_zone non_trigger;
1358        struct ustorm_trigger_vf_zone trigger;
1359};
1360
1361/* VF-PF channel data */
1362struct vf_pf_channel_data {
1363        __le32 ready;
1364        u8 valid;
1365        u8 reserved0;
1366        __le16 reserved1;
1367};
1368
1369/* Ramrod data for VF start ramrod */
1370struct vf_start_ramrod_data {
1371        u8 vf_id;
1372        u8 enable_flr_ack;
1373        __le16 opaque_fid;
1374        u8 personality;
1375        u8 reserved[7];
1376        struct hsi_fp_ver_struct hsi_fp_ver;
1377
1378};
1379
1380/* Ramrod data for VF start ramrod */
1381struct vf_stop_ramrod_data {
1382        u8 vf_id;
1383        u8 reserved0;
1384        __le16 reserved1;
1385        __le32 reserved2;
1386};
1387
1388/* VF zone size mode */
1389enum vf_zone_size_mode {
1390        VF_ZONE_SIZE_MODE_DEFAULT,
1391        VF_ZONE_SIZE_MODE_DOUBLE,
1392        VF_ZONE_SIZE_MODE_QUAD,
1393        MAX_VF_ZONE_SIZE_MODE
1394};
1395
1396/* Xstorm non-triggering VF zone */
1397struct xstorm_non_trigger_vf_zone {
1398        struct regpair non_edpm_ack_pkts;
1399};
1400
1401/* Tstorm VF zone */
1402struct xstorm_vf_zone {
1403        struct xstorm_non_trigger_vf_zone non_trigger;
1404};
1405
1406/* Attentions status block */
1407struct atten_status_block {
1408        __le32 atten_bits;
1409        __le32 atten_ack;
1410        __le16 reserved0;
1411        __le16 sb_index;
1412        __le32 reserved1;
1413};
1414
1415/* DMAE command */
1416struct dmae_cmd {
1417        __le32 opcode;
1418#define DMAE_CMD_SRC_MASK               0x1
1419#define DMAE_CMD_SRC_SHIFT              0
1420#define DMAE_CMD_DST_MASK               0x3
1421#define DMAE_CMD_DST_SHIFT              1
1422#define DMAE_CMD_C_DST_MASK             0x1
1423#define DMAE_CMD_C_DST_SHIFT            3
1424#define DMAE_CMD_CRC_RESET_MASK         0x1
1425#define DMAE_CMD_CRC_RESET_SHIFT        4
1426#define DMAE_CMD_SRC_ADDR_RESET_MASK    0x1
1427#define DMAE_CMD_SRC_ADDR_RESET_SHIFT   5
1428#define DMAE_CMD_DST_ADDR_RESET_MASK    0x1
1429#define DMAE_CMD_DST_ADDR_RESET_SHIFT   6
1430#define DMAE_CMD_COMP_FUNC_MASK         0x1
1431#define DMAE_CMD_COMP_FUNC_SHIFT        7
1432#define DMAE_CMD_COMP_WORD_EN_MASK      0x1
1433#define DMAE_CMD_COMP_WORD_EN_SHIFT     8
1434#define DMAE_CMD_COMP_CRC_EN_MASK       0x1
1435#define DMAE_CMD_COMP_CRC_EN_SHIFT      9
1436#define DMAE_CMD_COMP_CRC_OFFSET_MASK   0x7
1437#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10
1438#define DMAE_CMD_RESERVED1_MASK         0x1
1439#define DMAE_CMD_RESERVED1_SHIFT        13
1440#define DMAE_CMD_ENDIANITY_MODE_MASK    0x3
1441#define DMAE_CMD_ENDIANITY_MODE_SHIFT   14
1442#define DMAE_CMD_ERR_HANDLING_MASK      0x3
1443#define DMAE_CMD_ERR_HANDLING_SHIFT     16
1444#define DMAE_CMD_PORT_ID_MASK           0x3
1445#define DMAE_CMD_PORT_ID_SHIFT          18
1446#define DMAE_CMD_SRC_PF_ID_MASK         0xF
1447#define DMAE_CMD_SRC_PF_ID_SHIFT        20
1448#define DMAE_CMD_DST_PF_ID_MASK         0xF
1449#define DMAE_CMD_DST_PF_ID_SHIFT        24
1450#define DMAE_CMD_SRC_VF_ID_VALID_MASK   0x1
1451#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28
1452#define DMAE_CMD_DST_VF_ID_VALID_MASK   0x1
1453#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29
1454#define DMAE_CMD_RESERVED2_MASK         0x3
1455#define DMAE_CMD_RESERVED2_SHIFT        30
1456        __le32 src_addr_lo;
1457        __le32 src_addr_hi;
1458        __le32 dst_addr_lo;
1459        __le32 dst_addr_hi;
1460        __le16 length_dw;
1461        __le16 opcode_b;
1462#define DMAE_CMD_SRC_VF_ID_MASK         0xFF
1463#define DMAE_CMD_SRC_VF_ID_SHIFT        0
1464#define DMAE_CMD_DST_VF_ID_MASK         0xFF
1465#define DMAE_CMD_DST_VF_ID_SHIFT        8
1466        __le32 comp_addr_lo;
1467        __le32 comp_addr_hi;
1468        __le32 comp_val;
1469        __le32 crc32;
1470        __le32 crc_32_c;
1471        __le16 crc16;
1472        __le16 crc16_c;
1473        __le16 crc10;
1474        __le16 error_bit_reserved;
1475#define DMAE_CMD_ERROR_BIT_MASK        0x1
1476#define DMAE_CMD_ERROR_BIT_SHIFT       0
1477#define DMAE_CMD_RESERVED_MASK         0x7FFF
1478#define DMAE_CMD_RESERVED_SHIFT        1
1479        __le16 xsum16;
1480        __le16 xsum8;
1481};
1482
1483enum dmae_cmd_comp_crc_en_enum {
1484        dmae_cmd_comp_crc_disabled,
1485        dmae_cmd_comp_crc_enabled,
1486        MAX_DMAE_CMD_COMP_CRC_EN_ENUM
1487};
1488
1489enum dmae_cmd_comp_func_enum {
1490        dmae_cmd_comp_func_to_src,
1491        dmae_cmd_comp_func_to_dst,
1492        MAX_DMAE_CMD_COMP_FUNC_ENUM
1493};
1494
1495enum dmae_cmd_comp_word_en_enum {
1496        dmae_cmd_comp_word_disabled,
1497        dmae_cmd_comp_word_enabled,
1498        MAX_DMAE_CMD_COMP_WORD_EN_ENUM
1499};
1500
1501enum dmae_cmd_c_dst_enum {
1502        dmae_cmd_c_dst_pcie,
1503        dmae_cmd_c_dst_grc,
1504        MAX_DMAE_CMD_C_DST_ENUM
1505};
1506
1507enum dmae_cmd_dst_enum {
1508        dmae_cmd_dst_none_0,
1509        dmae_cmd_dst_pcie,
1510        dmae_cmd_dst_grc,
1511        dmae_cmd_dst_none_3,
1512        MAX_DMAE_CMD_DST_ENUM
1513};
1514
1515enum dmae_cmd_error_handling_enum {
1516        dmae_cmd_error_handling_send_regular_comp,
1517        dmae_cmd_error_handling_send_comp_with_err,
1518        dmae_cmd_error_handling_dont_send_comp,
1519        MAX_DMAE_CMD_ERROR_HANDLING_ENUM
1520};
1521
1522enum dmae_cmd_src_enum {
1523        dmae_cmd_src_pcie,
1524        dmae_cmd_src_grc,
1525        MAX_DMAE_CMD_SRC_ENUM
1526};
1527
1528struct e4_mstorm_core_conn_ag_ctx {
1529        u8 byte0;
1530        u8 byte1;
1531        u8 flags0;
1532#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
1533#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
1534#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
1535#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
1536#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
1537#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
1538#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
1539#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
1540#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
1541#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
1542        u8 flags1;
1543#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
1544#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
1545#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
1546#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
1547#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
1548#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
1549#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
1550#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        3
1551#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
1552#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        4
1553#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
1554#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        5
1555#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
1556#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        6
1557#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
1558#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        7
1559        __le16 word0;
1560        __le16 word1;
1561        __le32 reg0;
1562        __le32 reg1;
1563};
1564
1565struct e4_ystorm_core_conn_ag_ctx {
1566        u8 byte0;
1567        u8 byte1;
1568        u8 flags0;
1569#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK    0x1
1570#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT   0
1571#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK    0x1
1572#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT   1
1573#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK     0x3
1574#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT    2
1575#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK     0x3
1576#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT    4
1577#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK     0x3
1578#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT    6
1579        u8 flags1;
1580#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK           0x1
1581#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT          0
1582#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK           0x1
1583#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT          1
1584#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK           0x1
1585#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT          2
1586#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK         0x1
1587#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT        3
1588#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK         0x1
1589#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT        4
1590#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK         0x1
1591#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT        5
1592#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK         0x1
1593#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT        6
1594#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK         0x1
1595#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT        7
1596        u8 byte2;
1597        u8 byte3;
1598        __le16 word0;
1599        __le32 reg0;
1600        __le32 reg1;
1601        __le16 word1;
1602        __le16 word2;
1603        __le16 word3;
1604        __le16 word4;
1605        __le32 reg2;
1606        __le32 reg3;
1607};
1608
1609/* DMAE parameters */
1610struct qed_dmae_params {
1611        u32 flags;
1612/* If QED_DMAE_PARAMS_RW_REPL_SRC flag is set and the
1613 * source is a block of length DMAE_MAX_RW_SIZE and the
1614 * destination is larger, the source block will be duplicated as
1615 * many times as required to fill the destination block. This is
1616 * used mostly to write a zeroed buffer to destination address
1617 * using DMA
1618 */
1619#define QED_DMAE_PARAMS_RW_REPL_SRC_MASK        0x1
1620#define QED_DMAE_PARAMS_RW_REPL_SRC_SHIFT       0
1621#define QED_DMAE_PARAMS_SRC_VF_VALID_MASK       0x1
1622#define QED_DMAE_PARAMS_SRC_VF_VALID_SHIFT      1
1623#define QED_DMAE_PARAMS_DST_VF_VALID_MASK       0x1
1624#define QED_DMAE_PARAMS_DST_VF_VALID_SHIFT      2
1625#define QED_DMAE_PARAMS_COMPLETION_DST_MASK     0x1
1626#define QED_DMAE_PARAMS_COMPLETION_DST_SHIFT    3
1627#define QED_DMAE_PARAMS_PORT_VALID_MASK         0x1
1628#define QED_DMAE_PARAMS_PORT_VALID_SHIFT        4
1629#define QED_DMAE_PARAMS_SRC_PF_VALID_MASK       0x1
1630#define QED_DMAE_PARAMS_SRC_PF_VALID_SHIFT      5
1631#define QED_DMAE_PARAMS_DST_PF_VALID_MASK       0x1
1632#define QED_DMAE_PARAMS_DST_PF_VALID_SHIFT      6
1633#define QED_DMAE_PARAMS_RESERVED_MASK           0x1FFFFFF
1634#define QED_DMAE_PARAMS_RESERVED_SHIFT          7
1635        u8 src_vfid;
1636        u8 dst_vfid;
1637        u8 port_id;
1638        u8 src_pfid;
1639        u8 dst_pfid;
1640        u8 reserved1;
1641        __le16 reserved2;
1642};
1643
1644/* IGU cleanup command */
1645struct igu_cleanup {
1646        __le32 sb_id_and_flags;
1647#define IGU_CLEANUP_RESERVED0_MASK      0x7FFFFFF
1648#define IGU_CLEANUP_RESERVED0_SHIFT     0
1649#define IGU_CLEANUP_CLEANUP_SET_MASK    0x1
1650#define IGU_CLEANUP_CLEANUP_SET_SHIFT   27
1651#define IGU_CLEANUP_CLEANUP_TYPE_MASK   0x7
1652#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT  28
1653#define IGU_CLEANUP_COMMAND_TYPE_MASK   0x1
1654#define IGU_CLEANUP_COMMAND_TYPE_SHIFT  31
1655        __le32 reserved1;
1656};
1657
1658/* IGU firmware driver command */
1659union igu_command {
1660        struct igu_prod_cons_update prod_cons_update;
1661        struct igu_cleanup cleanup;
1662};
1663
1664/* IGU firmware driver command */
1665struct igu_command_reg_ctrl {
1666        __le16 opaque_fid;
1667        __le16 igu_command_reg_ctrl_fields;
1668#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK  0xFFF
1669#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0
1670#define IGU_COMMAND_REG_CTRL_RESERVED_MASK      0x7
1671#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT     12
1672#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK  0x1
1673#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15
1674};
1675
1676/* IGU mapping line structure */
1677struct igu_mapping_line {
1678        __le32 igu_mapping_line_fields;
1679#define IGU_MAPPING_LINE_VALID_MASK             0x1
1680#define IGU_MAPPING_LINE_VALID_SHIFT            0
1681#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK     0xFF
1682#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT    1
1683#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK   0xFF
1684#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT  9
1685#define IGU_MAPPING_LINE_PF_VALID_MASK          0x1
1686#define IGU_MAPPING_LINE_PF_VALID_SHIFT         17
1687#define IGU_MAPPING_LINE_IPS_GROUP_MASK         0x3F
1688#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT        18
1689#define IGU_MAPPING_LINE_RESERVED_MASK          0xFF
1690#define IGU_MAPPING_LINE_RESERVED_SHIFT         24
1691};
1692
1693/* IGU MSIX line structure */
1694struct igu_msix_vector {
1695        struct regpair address;
1696        __le32 data;
1697        __le32 msix_vector_fields;
1698#define IGU_MSIX_VECTOR_MASK_BIT_MASK           0x1
1699#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT          0
1700#define IGU_MSIX_VECTOR_RESERVED0_MASK          0x7FFF
1701#define IGU_MSIX_VECTOR_RESERVED0_SHIFT         1
1702#define IGU_MSIX_VECTOR_STEERING_TAG_MASK       0xFF
1703#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT      16
1704#define IGU_MSIX_VECTOR_RESERVED1_MASK          0xFF
1705#define IGU_MSIX_VECTOR_RESERVED1_SHIFT         24
1706};
1707/* per encapsulation type enabling flags */
1708struct prs_reg_encapsulation_type_en {
1709        u8 flags;
1710#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK          0x1
1711#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT         0
1712#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK           0x1
1713#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT          1
1714#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK                 0x1
1715#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT                2
1716#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK                 0x1
1717#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT                3
1718#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK       0x1
1719#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT      4
1720#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK        0x1
1721#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT       5
1722#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK                     0x3
1723#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT                    6
1724};
1725
1726enum pxp_tph_st_hint {
1727        TPH_ST_HINT_BIDIR,
1728        TPH_ST_HINT_REQUESTER,
1729        TPH_ST_HINT_TARGET,
1730        TPH_ST_HINT_TARGET_PRIO,
1731        MAX_PXP_TPH_ST_HINT
1732};
1733
1734/* QM hardware structure of enable bypass credit mask */
1735struct qm_rf_bypass_mask {
1736        u8 flags;
1737#define QM_RF_BYPASS_MASK_LINEVOQ_MASK          0x1
1738#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT         0
1739#define QM_RF_BYPASS_MASK_RESERVED0_MASK        0x1
1740#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT       1
1741#define QM_RF_BYPASS_MASK_PFWFQ_MASK            0x1
1742#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT           2
1743#define QM_RF_BYPASS_MASK_VPWFQ_MASK            0x1
1744#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT           3
1745#define QM_RF_BYPASS_MASK_PFRL_MASK             0x1
1746#define QM_RF_BYPASS_MASK_PFRL_SHIFT            4
1747#define QM_RF_BYPASS_MASK_VPQCNRL_MASK          0x1
1748#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT         5
1749#define QM_RF_BYPASS_MASK_FWPAUSE_MASK          0x1
1750#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT         6
1751#define QM_RF_BYPASS_MASK_RESERVED1_MASK        0x1
1752#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT       7
1753};
1754
1755/* QM hardware structure of opportunistic credit mask */
1756struct qm_rf_opportunistic_mask {
1757        __le16 flags;
1758#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK           0x1
1759#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT          0
1760#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK           0x1
1761#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT          1
1762#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK             0x1
1763#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT            2
1764#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK             0x1
1765#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT            3
1766#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK              0x1
1767#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT             4
1768#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK           0x1
1769#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT          5
1770#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK           0x1
1771#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT          6
1772#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK         0x1
1773#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT        7
1774#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK        0x1
1775#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT       8
1776#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK         0x7F
1777#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT        9
1778};
1779
1780/* QM hardware structure of QM map memory */
1781struct qm_rf_pq_map_e4 {
1782        __le32 reg;
1783#define QM_RF_PQ_MAP_E4_PQ_VALID_MASK           0x1
1784#define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT          0
1785#define QM_RF_PQ_MAP_E4_RL_ID_MASK              0xFF
1786#define QM_RF_PQ_MAP_E4_RL_ID_SHIFT             1
1787#define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK           0x1FF
1788#define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT          9
1789#define QM_RF_PQ_MAP_E4_VOQ_MASK                0x1F
1790#define QM_RF_PQ_MAP_E4_VOQ_SHIFT               18
1791#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK   0x3
1792#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT  23
1793#define QM_RF_PQ_MAP_E4_RL_VALID_MASK           0x1
1794#define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT          25
1795#define QM_RF_PQ_MAP_E4_RESERVED_MASK           0x3F
1796#define QM_RF_PQ_MAP_E4_RESERVED_SHIFT          26
1797};
1798
1799/* Completion params for aggregated interrupt completion */
1800struct sdm_agg_int_comp_params {
1801        __le16 params;
1802#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK      0x3F
1803#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT     0
1804#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK  0x1
1805#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6
1806#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK     0x1FF
1807#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT    7
1808};
1809
1810/* SDM operation gen command (generate aggregative interrupt) */
1811struct sdm_op_gen {
1812        __le32 command;
1813#define SDM_OP_GEN_COMP_PARAM_MASK      0xFFFF
1814#define SDM_OP_GEN_COMP_PARAM_SHIFT     0
1815#define SDM_OP_GEN_COMP_TYPE_MASK       0xF
1816#define SDM_OP_GEN_COMP_TYPE_SHIFT      16
1817#define SDM_OP_GEN_RESERVED_MASK        0xFFF
1818#define SDM_OP_GEN_RESERVED_SHIFT       20
1819};
1820
1821/* Physical memory descriptor */
1822struct phys_mem_desc {
1823        dma_addr_t phys_addr;
1824        void *virt_addr;
1825        u32 size;               /* In bytes */
1826};
1827
1828/* Virtual memory descriptor */
1829struct virt_mem_desc {
1830        void *ptr;
1831        u32 size;               /* In bytes */
1832};
1833
1834/****************************************/
1835/* Debug Tools HSI constants and macros */
1836/****************************************/
1837
1838enum block_id {
1839        BLOCK_GRC,
1840        BLOCK_MISCS,
1841        BLOCK_MISC,
1842        BLOCK_DBU,
1843        BLOCK_PGLUE_B,
1844        BLOCK_CNIG,
1845        BLOCK_CPMU,
1846        BLOCK_NCSI,
1847        BLOCK_OPTE,
1848        BLOCK_BMB,
1849        BLOCK_PCIE,
1850        BLOCK_MCP,
1851        BLOCK_MCP2,
1852        BLOCK_PSWHST,
1853        BLOCK_PSWHST2,
1854        BLOCK_PSWRD,
1855        BLOCK_PSWRD2,
1856        BLOCK_PSWWR,
1857        BLOCK_PSWWR2,
1858        BLOCK_PSWRQ,
1859        BLOCK_PSWRQ2,
1860        BLOCK_PGLCS,
1861        BLOCK_DMAE,
1862        BLOCK_PTU,
1863        BLOCK_TCM,
1864        BLOCK_MCM,
1865        BLOCK_UCM,
1866        BLOCK_XCM,
1867        BLOCK_YCM,
1868        BLOCK_PCM,
1869        BLOCK_QM,
1870        BLOCK_TM,
1871        BLOCK_DORQ,
1872        BLOCK_BRB,
1873        BLOCK_SRC,
1874        BLOCK_PRS,
1875        BLOCK_TSDM,
1876        BLOCK_MSDM,
1877        BLOCK_USDM,
1878        BLOCK_XSDM,
1879        BLOCK_YSDM,
1880        BLOCK_PSDM,
1881        BLOCK_TSEM,
1882        BLOCK_MSEM,
1883        BLOCK_USEM,
1884        BLOCK_XSEM,
1885        BLOCK_YSEM,
1886        BLOCK_PSEM,
1887        BLOCK_RSS,
1888        BLOCK_TMLD,
1889        BLOCK_MULD,
1890        BLOCK_YULD,
1891        BLOCK_XYLD,
1892        BLOCK_PRM,
1893        BLOCK_PBF_PB1,
1894        BLOCK_PBF_PB2,
1895        BLOCK_RPB,
1896        BLOCK_BTB,
1897        BLOCK_PBF,
1898        BLOCK_RDIF,
1899        BLOCK_TDIF,
1900        BLOCK_CDU,
1901        BLOCK_CCFC,
1902        BLOCK_TCFC,
1903        BLOCK_IGU,
1904        BLOCK_CAU,
1905        BLOCK_UMAC,
1906        BLOCK_XMAC,
1907        BLOCK_MSTAT,
1908        BLOCK_DBG,
1909        BLOCK_NIG,
1910        BLOCK_WOL,
1911        BLOCK_BMBN,
1912        BLOCK_IPC,
1913        BLOCK_NWM,
1914        BLOCK_NWS,
1915        BLOCK_MS,
1916        BLOCK_PHY_PCIE,
1917        BLOCK_LED,
1918        BLOCK_AVS_WRAP,
1919        BLOCK_PXPREQBUS,
1920        BLOCK_BAR0_MAP,
1921        BLOCK_MCP_FIO,
1922        BLOCK_LAST_INIT,
1923        BLOCK_PRS_FC,
1924        BLOCK_PBF_FC,
1925        BLOCK_NIG_LB_FC,
1926        BLOCK_NIG_LB_FC_PLLH,
1927        BLOCK_NIG_TX_FC_PLLH,
1928        BLOCK_NIG_TX_FC,
1929        BLOCK_NIG_RX_FC_PLLH,
1930        BLOCK_NIG_RX_FC,
1931        MAX_BLOCK_ID
1932};
1933
1934/* binary debug buffer types */
1935enum bin_dbg_buffer_type {
1936        BIN_BUF_DBG_MODE_TREE,
1937        BIN_BUF_DBG_DUMP_REG,
1938        BIN_BUF_DBG_DUMP_MEM,
1939        BIN_BUF_DBG_IDLE_CHK_REGS,
1940        BIN_BUF_DBG_IDLE_CHK_IMMS,
1941        BIN_BUF_DBG_IDLE_CHK_RULES,
1942        BIN_BUF_DBG_IDLE_CHK_PARSING_DATA,
1943        BIN_BUF_DBG_ATTN_BLOCKS,
1944        BIN_BUF_DBG_ATTN_REGS,
1945        BIN_BUF_DBG_ATTN_INDEXES,
1946        BIN_BUF_DBG_ATTN_NAME_OFFSETS,
1947        BIN_BUF_DBG_BLOCKS,
1948        BIN_BUF_DBG_BLOCKS_CHIP_DATA,
1949        BIN_BUF_DBG_BUS_LINES,
1950        BIN_BUF_DBG_BLOCKS_USER_DATA,
1951        BIN_BUF_DBG_BLOCKS_CHIP_USER_DATA,
1952        BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS,
1953        BIN_BUF_DBG_RESET_REGS,
1954        BIN_BUF_DBG_PARSING_STRINGS,
1955        MAX_BIN_DBG_BUFFER_TYPE
1956};
1957
1958
1959/* Attention bit mapping */
1960struct dbg_attn_bit_mapping {
1961        u16 data;
1962#define DBG_ATTN_BIT_MAPPING_VAL_MASK                   0x7FFF
1963#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT                  0
1964#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK     0x1
1965#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT    15
1966};
1967
1968/* Attention block per-type data */
1969struct dbg_attn_block_type_data {
1970        u16 names_offset;
1971        u16 reserved1;
1972        u8 num_regs;
1973        u8 reserved2;
1974        u16 regs_offset;
1975
1976};
1977
1978/* Block attentions */
1979struct dbg_attn_block {
1980        struct dbg_attn_block_type_data per_type_data[2];
1981};
1982
1983/* Attention register result */
1984struct dbg_attn_reg_result {
1985        u32 data;
1986#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK    0xFFFFFF
1987#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT   0
1988#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK   0xFF
1989#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT  24
1990        u16 block_attn_offset;
1991        u16 reserved;
1992        u32 sts_val;
1993        u32 mask_val;
1994};
1995
1996/* Attention block result */
1997struct dbg_attn_block_result {
1998        u8 block_id;
1999        u8 data;
2000#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK    0x3
2001#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT   0
2002#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK     0x3F
2003#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT    2
2004        u16 names_offset;
2005        struct dbg_attn_reg_result reg_results[15];
2006};
2007
2008/* Mode header */
2009struct dbg_mode_hdr {
2010        u16 data;
2011#define DBG_MODE_HDR_EVAL_MODE_MASK             0x1
2012#define DBG_MODE_HDR_EVAL_MODE_SHIFT            0
2013#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK      0x7FFF
2014#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT     1
2015};
2016
2017/* Attention register */
2018struct dbg_attn_reg {
2019        struct dbg_mode_hdr mode;
2020        u16 block_attn_offset;
2021        u32 data;
2022#define DBG_ATTN_REG_STS_ADDRESS_MASK   0xFFFFFF
2023#define DBG_ATTN_REG_STS_ADDRESS_SHIFT  0
2024#define DBG_ATTN_REG_NUM_REG_ATTN_MASK  0xFF
2025#define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24
2026        u32 sts_clr_address;
2027        u32 mask_address;
2028};
2029
2030/* Attention types */
2031enum dbg_attn_type {
2032        ATTN_TYPE_INTERRUPT,
2033        ATTN_TYPE_PARITY,
2034        MAX_DBG_ATTN_TYPE
2035};
2036
2037/* Block debug data */
2038struct dbg_block {
2039        u8 name[15];
2040        u8 associated_storm_letter;
2041};
2042
2043/* Chip-specific block debug data */
2044struct dbg_block_chip {
2045        u8 flags;
2046#define DBG_BLOCK_CHIP_IS_REMOVED_MASK           0x1
2047#define DBG_BLOCK_CHIP_IS_REMOVED_SHIFT          0
2048#define DBG_BLOCK_CHIP_HAS_RESET_REG_MASK        0x1
2049#define DBG_BLOCK_CHIP_HAS_RESET_REG_SHIFT       1
2050#define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_MASK  0x1
2051#define DBG_BLOCK_CHIP_UNRESET_BEFORE_DUMP_SHIFT 2
2052#define DBG_BLOCK_CHIP_HAS_DBG_BUS_MASK          0x1
2053#define DBG_BLOCK_CHIP_HAS_DBG_BUS_SHIFT         3
2054#define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_MASK   0x1
2055#define DBG_BLOCK_CHIP_HAS_LATENCY_EVENTS_SHIFT  4
2056#define DBG_BLOCK_CHIP_RESERVED0_MASK            0x7
2057#define DBG_BLOCK_CHIP_RESERVED0_SHIFT           5
2058        u8 dbg_client_id;
2059        u8 reset_reg_id;
2060        u8 reset_reg_bit_offset;
2061        struct dbg_mode_hdr dbg_bus_mode;
2062        u16 reserved1;
2063        u8 reserved2;
2064        u8 num_of_dbg_bus_lines;
2065        u16 dbg_bus_lines_offset;
2066        u32 dbg_select_reg_addr;
2067        u32 dbg_dword_enable_reg_addr;
2068        u32 dbg_shift_reg_addr;
2069        u32 dbg_force_valid_reg_addr;
2070        u32 dbg_force_frame_reg_addr;
2071};
2072
2073/* Chip-specific block user debug data */
2074struct dbg_block_chip_user {
2075        u8 num_of_dbg_bus_lines;
2076        u8 has_latency_events;
2077        u16 names_offset;
2078};
2079
2080/* Block user debug data */
2081struct dbg_block_user {
2082        u8 name[16];
2083};
2084
2085/* Block Debug line data */
2086struct dbg_bus_line {
2087        u8 data;
2088#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK         0xF
2089#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT        0
2090#define DBG_BUS_LINE_IS_256B_MASK               0x1
2091#define DBG_BUS_LINE_IS_256B_SHIFT              4
2092#define DBG_BUS_LINE_RESERVED_MASK              0x7
2093#define DBG_BUS_LINE_RESERVED_SHIFT             5
2094        u8 group_sizes;
2095};
2096
2097/* Condition header for registers dump */
2098struct dbg_dump_cond_hdr {
2099        struct dbg_mode_hdr mode; /* Mode header */
2100        u8 block_id; /* block ID */
2101        u8 data_size; /* size in dwords of the data following this header */
2102};
2103
2104/* Memory data for registers dump */
2105struct dbg_dump_mem {
2106        u32 dword0;
2107#define DBG_DUMP_MEM_ADDRESS_MASK       0xFFFFFF
2108#define DBG_DUMP_MEM_ADDRESS_SHIFT      0
2109#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK  0xFF
2110#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24
2111        u32 dword1;
2112#define DBG_DUMP_MEM_LENGTH_MASK        0xFFFFFF
2113#define DBG_DUMP_MEM_LENGTH_SHIFT       0
2114#define DBG_DUMP_MEM_WIDE_BUS_MASK      0x1
2115#define DBG_DUMP_MEM_WIDE_BUS_SHIFT     24
2116#define DBG_DUMP_MEM_RESERVED_MASK      0x7F
2117#define DBG_DUMP_MEM_RESERVED_SHIFT     25
2118};
2119
2120/* Register data for registers dump */
2121struct dbg_dump_reg {
2122        u32 data;
2123#define DBG_DUMP_REG_ADDRESS_MASK       0x7FFFFF
2124#define DBG_DUMP_REG_ADDRESS_SHIFT      0
2125#define DBG_DUMP_REG_WIDE_BUS_MASK      0x1
2126#define DBG_DUMP_REG_WIDE_BUS_SHIFT     23
2127#define DBG_DUMP_REG_LENGTH_MASK        0xFF
2128#define DBG_DUMP_REG_LENGTH_SHIFT       24
2129};
2130
2131/* Split header for registers dump */
2132struct dbg_dump_split_hdr {
2133        u32 hdr;
2134#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK       0xFFFFFF
2135#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT      0
2136#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK   0xFF
2137#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT  24
2138};
2139
2140/* Condition header for idle check */
2141struct dbg_idle_chk_cond_hdr {
2142        struct dbg_mode_hdr mode; /* Mode header */
2143        u16 data_size; /* size in dwords of the data following this header */
2144};
2145
2146/* Idle Check condition register */
2147struct dbg_idle_chk_cond_reg {
2148        u32 data;
2149#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK      0x7FFFFF
2150#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT     0
2151#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK     0x1
2152#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT    23
2153#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK     0xFF
2154#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT    24
2155        u16 num_entries;
2156        u8 entry_size;
2157        u8 start_entry;
2158};
2159
2160/* Idle Check info register */
2161struct dbg_idle_chk_info_reg {
2162        u32 data;
2163#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK      0x7FFFFF
2164#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT     0
2165#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK     0x1
2166#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT    23
2167#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK     0xFF
2168#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT    24
2169        u16 size; /* register size in dwords */
2170        struct dbg_mode_hdr mode; /* Mode header */
2171};
2172
2173/* Idle Check register */
2174union dbg_idle_chk_reg {
2175        struct dbg_idle_chk_cond_reg cond_reg; /* condition register */
2176        struct dbg_idle_chk_info_reg info_reg; /* info register */
2177};
2178
2179/* Idle Check result header */
2180struct dbg_idle_chk_result_hdr {
2181        u16 rule_id; /* Failing rule index */
2182        u16 mem_entry_id; /* Failing memory entry index */
2183        u8 num_dumped_cond_regs; /* number of dumped condition registers */
2184        u8 num_dumped_info_regs; /* number of dumped condition registers */
2185        u8 severity; /* from dbg_idle_chk_severity_types enum */
2186        u8 reserved;
2187};
2188
2189/* Idle Check result register header */
2190struct dbg_idle_chk_result_reg_hdr {
2191        u8 data;
2192#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK  0x1
2193#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0
2194#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK  0x7F
2195#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1
2196        u8 start_entry; /* index of the first checked entry */
2197        u16 size; /* register size in dwords */
2198};
2199
2200/* Idle Check rule */
2201struct dbg_idle_chk_rule {
2202        u16 rule_id; /* Idle Check rule ID */
2203        u8 severity; /* value from dbg_idle_chk_severity_types enum */
2204        u8 cond_id; /* Condition ID */
2205        u8 num_cond_regs; /* number of condition registers */
2206        u8 num_info_regs; /* number of info registers */
2207        u8 num_imms; /* number of immediates in the condition */
2208        u8 reserved1;
2209        u16 reg_offset; /* offset of this rules registers in the idle check
2210                         * register array (in dbg_idle_chk_reg units).
2211                         */
2212        u16 imm_offset; /* offset of this rules immediate values in the
2213                         * immediate values array (in dwords).
2214                         */
2215};
2216
2217/* Idle Check rule parsing data */
2218struct dbg_idle_chk_rule_parsing_data {
2219        u32 data;
2220#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK  0x1
2221#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0
2222#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK  0x7FFFFFFF
2223#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1
2224};
2225
2226/* Idle check severity types */
2227enum dbg_idle_chk_severity_types {
2228        /* idle check failure should cause an error */
2229        IDLE_CHK_SEVERITY_ERROR,
2230        /* idle check failure should cause an error only if theres no traffic */
2231        IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC,
2232        /* idle check failure should cause a warning */
2233        IDLE_CHK_SEVERITY_WARNING,
2234        MAX_DBG_IDLE_CHK_SEVERITY_TYPES
2235};
2236
2237/* Reset register */
2238struct dbg_reset_reg {
2239        u32 data;
2240#define DBG_RESET_REG_ADDR_MASK        0xFFFFFF
2241#define DBG_RESET_REG_ADDR_SHIFT       0
2242#define DBG_RESET_REG_IS_REMOVED_MASK  0x1
2243#define DBG_RESET_REG_IS_REMOVED_SHIFT 24
2244#define DBG_RESET_REG_RESERVED_MASK    0x7F
2245#define DBG_RESET_REG_RESERVED_SHIFT   25
2246};
2247
2248/* Debug Bus block data */
2249struct dbg_bus_block_data {
2250        u8 enable_mask;
2251        u8 right_shift;
2252        u8 force_valid_mask;
2253        u8 force_frame_mask;
2254        u8 dword_mask;
2255        u8 line_num;
2256        u8 hw_id;
2257        u8 flags;
2258#define DBG_BUS_BLOCK_DATA_IS_256B_LINE_MASK  0x1
2259#define DBG_BUS_BLOCK_DATA_IS_256B_LINE_SHIFT 0
2260#define DBG_BUS_BLOCK_DATA_RESERVED_MASK      0x7F
2261#define DBG_BUS_BLOCK_DATA_RESERVED_SHIFT     1
2262};
2263
2264enum dbg_bus_clients {
2265        DBG_BUS_CLIENT_RBCN,
2266        DBG_BUS_CLIENT_RBCP,
2267        DBG_BUS_CLIENT_RBCR,
2268        DBG_BUS_CLIENT_RBCT,
2269        DBG_BUS_CLIENT_RBCU,
2270        DBG_BUS_CLIENT_RBCF,
2271        DBG_BUS_CLIENT_RBCX,
2272        DBG_BUS_CLIENT_RBCS,
2273        DBG_BUS_CLIENT_RBCH,
2274        DBG_BUS_CLIENT_RBCZ,
2275        DBG_BUS_CLIENT_OTHER_ENGINE,
2276        DBG_BUS_CLIENT_TIMESTAMP,
2277        DBG_BUS_CLIENT_CPU,
2278        DBG_BUS_CLIENT_RBCY,
2279        DBG_BUS_CLIENT_RBCQ,
2280        DBG_BUS_CLIENT_RBCM,
2281        DBG_BUS_CLIENT_RBCB,
2282        DBG_BUS_CLIENT_RBCW,
2283        DBG_BUS_CLIENT_RBCV,
2284        MAX_DBG_BUS_CLIENTS
2285};
2286
2287/* Debug Bus constraint operation types */
2288enum dbg_bus_constraint_ops {
2289        DBG_BUS_CONSTRAINT_OP_EQ,
2290        DBG_BUS_CONSTRAINT_OP_NE,
2291        DBG_BUS_CONSTRAINT_OP_LT,
2292        DBG_BUS_CONSTRAINT_OP_LTC,
2293        DBG_BUS_CONSTRAINT_OP_LE,
2294        DBG_BUS_CONSTRAINT_OP_LEC,
2295        DBG_BUS_CONSTRAINT_OP_GT,
2296        DBG_BUS_CONSTRAINT_OP_GTC,
2297        DBG_BUS_CONSTRAINT_OP_GE,
2298        DBG_BUS_CONSTRAINT_OP_GEC,
2299        MAX_DBG_BUS_CONSTRAINT_OPS
2300};
2301
2302/* Debug Bus trigger state data */
2303struct dbg_bus_trigger_state_data {
2304        u8 msg_len;
2305        u8 constraint_dword_mask;
2306        u8 storm_id;
2307        u8 reserved;
2308};
2309
2310/* Debug Bus memory address */
2311struct dbg_bus_mem_addr {
2312        u32 lo;
2313        u32 hi;
2314};
2315
2316/* Debug Bus PCI buffer data */
2317struct dbg_bus_pci_buf_data {
2318        struct dbg_bus_mem_addr phys_addr; /* PCI buffer physical address */
2319        struct dbg_bus_mem_addr virt_addr; /* PCI buffer virtual address */
2320        u32 size; /* PCI buffer size in bytes */
2321};
2322
2323/* Debug Bus Storm EID range filter params */
2324struct dbg_bus_storm_eid_range_params {
2325        u8 min; /* Minimal event ID to filter on */
2326        u8 max; /* Maximal event ID to filter on */
2327};
2328
2329/* Debug Bus Storm EID mask filter params */
2330struct dbg_bus_storm_eid_mask_params {
2331        u8 val; /* Event ID value */
2332        u8 mask; /* Event ID mask. 1s in the mask = dont care bits. */
2333};
2334
2335/* Debug Bus Storm EID filter params */
2336union dbg_bus_storm_eid_params {
2337        struct dbg_bus_storm_eid_range_params range;
2338        struct dbg_bus_storm_eid_mask_params mask;
2339};
2340
2341/* Debug Bus Storm data */
2342struct dbg_bus_storm_data {
2343        u8 enabled;
2344        u8 mode;
2345        u8 hw_id;
2346        u8 eid_filter_en;
2347        u8 eid_range_not_mask;
2348        u8 cid_filter_en;
2349        union dbg_bus_storm_eid_params eid_filter_params;
2350        u32 cid;
2351};
2352
2353/* Debug Bus data */
2354struct dbg_bus_data {
2355        u32 app_version;
2356        u8 state;
2357        u8 mode_256b_en;
2358        u8 num_enabled_blocks;
2359        u8 num_enabled_storms;
2360        u8 target;
2361        u8 one_shot_en;
2362        u8 grc_input_en;
2363        u8 timestamp_input_en;
2364        u8 filter_en;
2365        u8 adding_filter;
2366        u8 filter_pre_trigger;
2367        u8 filter_post_trigger;
2368        u8 trigger_en;
2369        u8 filter_constraint_dword_mask;
2370        u8 next_trigger_state;
2371        u8 next_constraint_id;
2372        struct dbg_bus_trigger_state_data trigger_states[3];
2373        u8 filter_msg_len;
2374        u8 rcv_from_other_engine;
2375        u8 blocks_dword_mask;
2376        u8 blocks_dword_overlap;
2377        u32 hw_id_mask;
2378        struct dbg_bus_pci_buf_data pci_buf;
2379        struct dbg_bus_block_data blocks[132];
2380        struct dbg_bus_storm_data storms[6];
2381};
2382
2383/* Debug bus states */
2384enum dbg_bus_states {
2385        DBG_BUS_STATE_IDLE,
2386        DBG_BUS_STATE_READY,
2387        DBG_BUS_STATE_RECORDING,
2388        DBG_BUS_STATE_STOPPED,
2389        MAX_DBG_BUS_STATES
2390};
2391
2392/* Debug Bus Storm modes */
2393enum dbg_bus_storm_modes {
2394        DBG_BUS_STORM_MODE_PRINTF,
2395        DBG_BUS_STORM_MODE_PRAM_ADDR,
2396        DBG_BUS_STORM_MODE_DRA_RW,
2397        DBG_BUS_STORM_MODE_DRA_W,
2398        DBG_BUS_STORM_MODE_LD_ST_ADDR,
2399        DBG_BUS_STORM_MODE_DRA_FSM,
2400        DBG_BUS_STORM_MODE_FAST_DBGMUX,
2401        DBG_BUS_STORM_MODE_RH,
2402        DBG_BUS_STORM_MODE_RH_WITH_STORE,
2403        DBG_BUS_STORM_MODE_FOC,
2404        DBG_BUS_STORM_MODE_EXT_STORE,
2405        MAX_DBG_BUS_STORM_MODES
2406};
2407
2408/* Debug bus target IDs */
2409enum dbg_bus_targets {
2410        DBG_BUS_TARGET_ID_INT_BUF,
2411        DBG_BUS_TARGET_ID_NIG,
2412        DBG_BUS_TARGET_ID_PCI,
2413        MAX_DBG_BUS_TARGETS
2414};
2415
2416/* GRC Dump data */
2417struct dbg_grc_data {
2418        u8 params_initialized;
2419        u8 reserved1;
2420        u16 reserved2;
2421        u32 param_val[48];
2422};
2423
2424/* Debug GRC params */
2425enum dbg_grc_params {
2426        DBG_GRC_PARAM_DUMP_TSTORM,
2427        DBG_GRC_PARAM_DUMP_MSTORM,
2428        DBG_GRC_PARAM_DUMP_USTORM,
2429        DBG_GRC_PARAM_DUMP_XSTORM,
2430        DBG_GRC_PARAM_DUMP_YSTORM,
2431        DBG_GRC_PARAM_DUMP_PSTORM,
2432        DBG_GRC_PARAM_DUMP_REGS,
2433        DBG_GRC_PARAM_DUMP_RAM,
2434        DBG_GRC_PARAM_DUMP_PBUF,
2435        DBG_GRC_PARAM_DUMP_IOR,
2436        DBG_GRC_PARAM_DUMP_VFC,
2437        DBG_GRC_PARAM_DUMP_CM_CTX,
2438        DBG_GRC_PARAM_DUMP_PXP,
2439        DBG_GRC_PARAM_DUMP_RSS,
2440        DBG_GRC_PARAM_DUMP_CAU,
2441        DBG_GRC_PARAM_DUMP_QM,
2442        DBG_GRC_PARAM_DUMP_MCP,
2443        DBG_GRC_PARAM_DUMP_DORQ,
2444        DBG_GRC_PARAM_DUMP_CFC,
2445        DBG_GRC_PARAM_DUMP_IGU,
2446        DBG_GRC_PARAM_DUMP_BRB,
2447        DBG_GRC_PARAM_DUMP_BTB,
2448        DBG_GRC_PARAM_DUMP_BMB,
2449        DBG_GRC_PARAM_RESERVD1,
2450        DBG_GRC_PARAM_DUMP_MULD,
2451        DBG_GRC_PARAM_DUMP_PRS,
2452        DBG_GRC_PARAM_DUMP_DMAE,
2453        DBG_GRC_PARAM_DUMP_TM,
2454        DBG_GRC_PARAM_DUMP_SDM,
2455        DBG_GRC_PARAM_DUMP_DIF,
2456        DBG_GRC_PARAM_DUMP_STATIC,
2457        DBG_GRC_PARAM_UNSTALL,
2458        DBG_GRC_PARAM_RESERVED2,
2459        DBG_GRC_PARAM_MCP_TRACE_META_SIZE,
2460        DBG_GRC_PARAM_EXCLUDE_ALL,
2461        DBG_GRC_PARAM_CRASH,
2462        DBG_GRC_PARAM_PARITY_SAFE,
2463        DBG_GRC_PARAM_DUMP_CM,
2464        DBG_GRC_PARAM_DUMP_PHY,
2465        DBG_GRC_PARAM_NO_MCP,
2466        DBG_GRC_PARAM_NO_FW_VER,
2467        DBG_GRC_PARAM_RESERVED3,
2468        DBG_GRC_PARAM_DUMP_MCP_HW_DUMP,
2469        DBG_GRC_PARAM_DUMP_ILT_CDUC,
2470        DBG_GRC_PARAM_DUMP_ILT_CDUT,
2471        DBG_GRC_PARAM_DUMP_CAU_EXT,
2472        MAX_DBG_GRC_PARAMS
2473};
2474
2475/* Debug status codes */
2476enum dbg_status {
2477        DBG_STATUS_OK,
2478        DBG_STATUS_APP_VERSION_NOT_SET,
2479        DBG_STATUS_UNSUPPORTED_APP_VERSION,
2480        DBG_STATUS_DBG_BLOCK_NOT_RESET,
2481        DBG_STATUS_INVALID_ARGS,
2482        DBG_STATUS_OUTPUT_ALREADY_SET,
2483        DBG_STATUS_INVALID_PCI_BUF_SIZE,
2484        DBG_STATUS_PCI_BUF_ALLOC_FAILED,
2485        DBG_STATUS_PCI_BUF_NOT_ALLOCATED,
2486        DBG_STATUS_INVALID_FILTER_TRIGGER_DWORDS,
2487        DBG_STATUS_NO_MATCHING_FRAMING_MODE,
2488        DBG_STATUS_VFC_READ_ERROR,
2489        DBG_STATUS_STORM_ALREADY_ENABLED,
2490        DBG_STATUS_STORM_NOT_ENABLED,
2491        DBG_STATUS_BLOCK_ALREADY_ENABLED,
2492        DBG_STATUS_BLOCK_NOT_ENABLED,
2493        DBG_STATUS_NO_INPUT_ENABLED,
2494        DBG_STATUS_NO_FILTER_TRIGGER_256B,
2495        DBG_STATUS_FILTER_ALREADY_ENABLED,
2496        DBG_STATUS_TRIGGER_ALREADY_ENABLED,
2497        DBG_STATUS_TRIGGER_NOT_ENABLED,
2498        DBG_STATUS_CANT_ADD_CONSTRAINT,
2499        DBG_STATUS_TOO_MANY_TRIGGER_STATES,
2500        DBG_STATUS_TOO_MANY_CONSTRAINTS,
2501        DBG_STATUS_RECORDING_NOT_STARTED,
2502        DBG_STATUS_DATA_DIDNT_TRIGGER,
2503        DBG_STATUS_NO_DATA_RECORDED,
2504        DBG_STATUS_DUMP_BUF_TOO_SMALL,
2505        DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED,
2506        DBG_STATUS_UNKNOWN_CHIP,
2507        DBG_STATUS_VIRT_MEM_ALLOC_FAILED,
2508        DBG_STATUS_BLOCK_IN_RESET,
2509        DBG_STATUS_INVALID_TRACE_SIGNATURE,
2510        DBG_STATUS_INVALID_NVRAM_BUNDLE,
2511        DBG_STATUS_NVRAM_GET_IMAGE_FAILED,
2512        DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE,
2513        DBG_STATUS_NVRAM_READ_FAILED,
2514        DBG_STATUS_IDLE_CHK_PARSE_FAILED,
2515        DBG_STATUS_MCP_TRACE_BAD_DATA,
2516        DBG_STATUS_MCP_TRACE_NO_META,
2517        DBG_STATUS_MCP_COULD_NOT_HALT,
2518        DBG_STATUS_MCP_COULD_NOT_RESUME,
2519        DBG_STATUS_RESERVED0,
2520        DBG_STATUS_SEMI_FIFO_NOT_EMPTY,
2521        DBG_STATUS_IGU_FIFO_BAD_DATA,
2522        DBG_STATUS_MCP_COULD_NOT_MASK_PRTY,
2523        DBG_STATUS_FW_ASSERTS_PARSE_FAILED,
2524        DBG_STATUS_REG_FIFO_BAD_DATA,
2525        DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA,
2526        DBG_STATUS_DBG_ARRAY_NOT_SET,
2527        DBG_STATUS_RESERVED1,
2528        DBG_STATUS_NON_MATCHING_LINES,
2529        DBG_STATUS_INSUFFICIENT_HW_IDS,
2530        DBG_STATUS_DBG_BUS_IN_USE,
2531        DBG_STATUS_INVALID_STORM_DBG_MODE,
2532        DBG_STATUS_OTHER_ENGINE_BB_ONLY,
2533        DBG_STATUS_FILTER_SINGLE_HW_ID,
2534        DBG_STATUS_TRIGGER_SINGLE_HW_ID,
2535        DBG_STATUS_MISSING_TRIGGER_STATE_STORM,
2536        MAX_DBG_STATUS
2537};
2538
2539/* Debug Storms IDs */
2540enum dbg_storms {
2541        DBG_TSTORM_ID,
2542        DBG_MSTORM_ID,
2543        DBG_USTORM_ID,
2544        DBG_XSTORM_ID,
2545        DBG_YSTORM_ID,
2546        DBG_PSTORM_ID,
2547        MAX_DBG_STORMS
2548};
2549
2550/* Idle Check data */
2551struct idle_chk_data {
2552        u32 buf_size;
2553        u8 buf_size_set;
2554        u8 reserved1;
2555        u16 reserved2;
2556};
2557
2558struct pretend_params {
2559        u8 split_type;
2560        u8 reserved;
2561        u16 split_id;
2562};
2563
2564/* Debug Tools data (per HW function)
2565 */
2566struct dbg_tools_data {
2567        struct dbg_grc_data grc;
2568        struct dbg_bus_data bus;
2569        struct idle_chk_data idle_chk;
2570        u8 mode_enable[40];
2571        u8 block_in_reset[132];
2572        u8 chip_id;
2573        u8 hw_type;
2574        u8 num_ports;
2575        u8 num_pfs_per_port;
2576        u8 num_vfs;
2577        u8 initialized;
2578        u8 use_dmae;
2579        u8 reserved;
2580        struct pretend_params pretend;
2581        u32 num_regs_read;
2582};
2583
2584/* ILT Clients */
2585enum ilt_clients {
2586        ILT_CLI_CDUC,
2587        ILT_CLI_CDUT,
2588        ILT_CLI_QM,
2589        ILT_CLI_TM,
2590        ILT_CLI_SRC,
2591        ILT_CLI_TSDM,
2592        ILT_CLI_RGFS,
2593        ILT_CLI_TGFS,
2594        MAX_ILT_CLIENTS
2595};
2596
2597/********************************/
2598/* HSI Init Functions constants */
2599/********************************/
2600
2601/* Number of VLAN priorities */
2602#define NUM_OF_VLAN_PRIORITIES  8
2603
2604/* BRB RAM init requirements */
2605struct init_brb_ram_req {
2606        u32 guranteed_per_tc;
2607        u32 headroom_per_tc;
2608        u32 min_pkt_size;
2609        u32 max_ports_per_engine;
2610        u8 num_active_tcs[MAX_NUM_PORTS];
2611};
2612
2613/* ETS per-TC init requirements */
2614struct init_ets_tc_req {
2615        u8 use_sp;
2616        u8 use_wfq;
2617        u16 weight;
2618};
2619
2620/* ETS init requirements */
2621struct init_ets_req {
2622        u32 mtu;
2623        struct init_ets_tc_req tc_req[NUM_OF_TCS];
2624};
2625
2626/* NIG LB RL init requirements */
2627struct init_nig_lb_rl_req {
2628        u16 lb_mac_rate;
2629        u16 lb_rate;
2630        u32 mtu;
2631        u16 tc_rate[NUM_OF_PHYS_TCS];
2632};
2633
2634/* NIG TC mapping for each priority */
2635struct init_nig_pri_tc_map_entry {
2636        u8 tc_id;
2637        u8 valid;
2638};
2639
2640/* NIG priority to TC map init requirements */
2641struct init_nig_pri_tc_map_req {
2642        struct init_nig_pri_tc_map_entry pri[NUM_OF_VLAN_PRIORITIES];
2643};
2644
2645/* QM per global RL init parameters */
2646struct init_qm_global_rl_params {
2647        u32 rate_limit;
2648};
2649
2650/* QM per-port init parameters */
2651struct init_qm_port_params {
2652        u16 active_phys_tcs;
2653        u16 num_pbf_cmd_lines;
2654        u16 num_btb_blocks;
2655        u8 active;
2656        u8 reserved;
2657};
2658
2659/* QM per-PQ init parameters */
2660struct init_qm_pq_params {
2661        u8 vport_id;
2662        u8 tc_id;
2663        u8 wrr_group;
2664        u8 rl_valid;
2665        u16 rl_id;
2666        u8 port_id;
2667        u8 reserved;
2668};
2669
2670/* QM per-vport init parameters */
2671struct init_qm_vport_params {
2672        u16 wfq;
2673        u16 first_tx_pq_id[NUM_OF_TCS];
2674};
2675
2676/**************************************/
2677/* Init Tool HSI constants and macros */
2678/**************************************/
2679
2680/* Width of GRC address in bits (addresses are specified in dwords) */
2681#define GRC_ADDR_BITS   23
2682#define MAX_GRC_ADDR    (BIT(GRC_ADDR_BITS) - 1)
2683
2684/* indicates an init that should be applied to any phase ID */
2685#define ANY_PHASE_ID    0xffff
2686
2687/* Max size in dwords of a zipped array */
2688#define MAX_ZIPPED_SIZE 8192
2689enum chip_ids {
2690        CHIP_BB,
2691        CHIP_K2,
2692        MAX_CHIP_IDS
2693};
2694
2695struct fw_asserts_ram_section {
2696        __le16 section_ram_line_offset;
2697        __le16 section_ram_line_size;
2698        u8 list_dword_offset;
2699        u8 list_element_dword_size;
2700        u8 list_num_elements;
2701        u8 list_next_index_dword_offset;
2702};
2703
2704struct fw_ver_num {
2705        u8 major;
2706        u8 minor;
2707        u8 rev;
2708        u8 eng;
2709};
2710
2711struct fw_ver_info {
2712        __le16 tools_ver;
2713        u8 image_id;
2714        u8 reserved1;
2715        struct fw_ver_num num;
2716        __le32 timestamp;
2717        __le32 reserved2;
2718};
2719
2720struct fw_info {
2721        struct fw_ver_info ver;
2722        struct fw_asserts_ram_section fw_asserts_section;
2723};
2724
2725struct fw_info_location {
2726        __le32 grc_addr;
2727        __le32 size;
2728};
2729
2730enum init_modes {
2731        MODE_RESERVED,
2732        MODE_BB,
2733        MODE_K2,
2734        MODE_ASIC,
2735        MODE_RESERVED2,
2736        MODE_RESERVED3,
2737        MODE_RESERVED4,
2738        MODE_RESERVED5,
2739        MODE_SF,
2740        MODE_MF_SD,
2741        MODE_MF_SI,
2742        MODE_PORTS_PER_ENG_1,
2743        MODE_PORTS_PER_ENG_2,
2744        MODE_PORTS_PER_ENG_4,
2745        MODE_100G,
2746        MODE_RESERVED6,
2747        MODE_RESERVED7,
2748        MAX_INIT_MODES
2749};
2750
2751enum init_phases {
2752        PHASE_ENGINE,
2753        PHASE_PORT,
2754        PHASE_PF,
2755        PHASE_VF,
2756        PHASE_QM_PF,
2757        MAX_INIT_PHASES
2758};
2759
2760enum init_split_types {
2761        SPLIT_TYPE_NONE,
2762        SPLIT_TYPE_PORT,
2763        SPLIT_TYPE_PF,
2764        SPLIT_TYPE_PORT_PF,
2765        SPLIT_TYPE_VF,
2766        MAX_INIT_SPLIT_TYPES
2767};
2768
2769/* Binary buffer header */
2770struct bin_buffer_hdr {
2771        u32 offset;
2772        u32 length;
2773};
2774
2775/* Binary init buffer types */
2776enum bin_init_buffer_type {
2777        BIN_BUF_INIT_FW_VER_INFO,
2778        BIN_BUF_INIT_CMD,
2779        BIN_BUF_INIT_VAL,
2780        BIN_BUF_INIT_MODE_TREE,
2781        BIN_BUF_INIT_IRO,
2782        BIN_BUF_INIT_OVERLAYS,
2783        MAX_BIN_INIT_BUFFER_TYPE
2784};
2785
2786/* FW overlay buffer header */
2787struct fw_overlay_buf_hdr {
2788        u32 data;
2789#define FW_OVERLAY_BUF_HDR_STORM_ID_MASK  0xFF
2790#define FW_OVERLAY_BUF_HDR_STORM_ID_SHIFT 0
2791#define FW_OVERLAY_BUF_HDR_BUF_SIZE_MASK  0xFFFFFF
2792#define FW_OVERLAY_BUF_HDR_BUF_SIZE_SHIFT 8
2793};
2794
2795/* init array header: raw */
2796struct init_array_raw_hdr {
2797        __le32                                          data;
2798#define INIT_ARRAY_RAW_HDR_TYPE_MASK                    0xF
2799#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT                   0
2800#define INIT_ARRAY_RAW_HDR_PARAMS_MASK                  0xFFFFFFF
2801#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT                 4
2802};
2803
2804/* init array header: standard */
2805struct init_array_standard_hdr {
2806        __le32                                          data;
2807#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK               0xF
2808#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT              0
2809#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK               0xFFFFFFF
2810#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT              4
2811};
2812
2813/* init array header: zipped */
2814struct init_array_zipped_hdr {
2815        __le32                                          data;
2816#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK                 0xF
2817#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT                0
2818#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK          0xFFFFFFF
2819#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT         4
2820};
2821
2822/* init array header: pattern */
2823struct init_array_pattern_hdr {
2824        __le32                                          data;
2825#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK                0xF
2826#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT               0
2827#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK        0xF
2828#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT       4
2829#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK         0xFFFFFF
2830#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT        8
2831};
2832
2833/* init array header union */
2834union init_array_hdr {
2835        struct init_array_raw_hdr                       raw;
2836        struct init_array_standard_hdr                  standard;
2837        struct init_array_zipped_hdr                    zipped;
2838        struct init_array_pattern_hdr                   pattern;
2839};
2840
2841/* init array types */
2842enum init_array_types {
2843        INIT_ARR_STANDARD,
2844        INIT_ARR_ZIPPED,
2845        INIT_ARR_PATTERN,
2846        MAX_INIT_ARRAY_TYPES
2847};
2848
2849/* init operation: callback */
2850struct init_callback_op {
2851        __le32                                          op_data;
2852#define INIT_CALLBACK_OP_OP_MASK                        0xF
2853#define INIT_CALLBACK_OP_OP_SHIFT                       0
2854#define INIT_CALLBACK_OP_RESERVED_MASK                  0xFFFFFFF
2855#define INIT_CALLBACK_OP_RESERVED_SHIFT                 4
2856        __le16                                          callback_id;
2857        __le16                                          block_id;
2858};
2859
2860/* init operation: delay */
2861struct init_delay_op {
2862        __le32                                          op_data;
2863#define INIT_DELAY_OP_OP_MASK                           0xF
2864#define INIT_DELAY_OP_OP_SHIFT                          0
2865#define INIT_DELAY_OP_RESERVED_MASK                     0xFFFFFFF
2866#define INIT_DELAY_OP_RESERVED_SHIFT                    4
2867        __le32                                          delay;
2868};
2869
2870/* init operation: if_mode */
2871struct init_if_mode_op {
2872        __le32                                          op_data;
2873#define INIT_IF_MODE_OP_OP_MASK                         0xF
2874#define INIT_IF_MODE_OP_OP_SHIFT                        0
2875#define INIT_IF_MODE_OP_RESERVED1_MASK                  0xFFF
2876#define INIT_IF_MODE_OP_RESERVED1_SHIFT                 4
2877#define INIT_IF_MODE_OP_CMD_OFFSET_MASK                 0xFFFF
2878#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT                16
2879        __le16                                          reserved2;
2880        __le16                                          modes_buf_offset;
2881};
2882
2883/* init operation: if_phase */
2884struct init_if_phase_op {
2885        __le32                                          op_data;
2886#define INIT_IF_PHASE_OP_OP_MASK                        0xF
2887#define INIT_IF_PHASE_OP_OP_SHIFT                       0
2888#define INIT_IF_PHASE_OP_RESERVED1_MASK                 0xFFF
2889#define INIT_IF_PHASE_OP_RESERVED1_SHIFT                4
2890#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK                0xFFFF
2891#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT               16
2892        __le32                                          phase_data;
2893#define INIT_IF_PHASE_OP_PHASE_MASK                     0xFF
2894#define INIT_IF_PHASE_OP_PHASE_SHIFT                    0
2895#define INIT_IF_PHASE_OP_RESERVED2_MASK                 0xFF
2896#define INIT_IF_PHASE_OP_RESERVED2_SHIFT                8
2897#define INIT_IF_PHASE_OP_PHASE_ID_MASK                  0xFFFF
2898#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT                 16
2899};
2900
2901/* init mode operators */
2902enum init_mode_ops {
2903        INIT_MODE_OP_NOT,
2904        INIT_MODE_OP_OR,
2905        INIT_MODE_OP_AND,
2906        MAX_INIT_MODE_OPS
2907};
2908
2909/* init operation: raw */
2910struct init_raw_op {
2911        __le32                                          op_data;
2912#define INIT_RAW_OP_OP_MASK                             0xF
2913#define INIT_RAW_OP_OP_SHIFT                            0
2914#define INIT_RAW_OP_PARAM1_MASK                         0xFFFFFFF
2915#define INIT_RAW_OP_PARAM1_SHIFT                        4
2916        __le32                                          param2;
2917};
2918
2919/* init array params */
2920struct init_op_array_params {
2921        __le16                                          size;
2922        __le16                                          offset;
2923};
2924
2925/* Write init operation arguments */
2926union init_write_args {
2927        __le32                                          inline_val;
2928        __le32                                          zeros_count;
2929        __le32                                          array_offset;
2930        struct init_op_array_params                     runtime;
2931};
2932
2933/* init operation: write */
2934struct init_write_op {
2935        __le32                                          data;
2936#define INIT_WRITE_OP_OP_MASK                           0xF
2937#define INIT_WRITE_OP_OP_SHIFT                          0
2938#define INIT_WRITE_OP_SOURCE_MASK                       0x7
2939#define INIT_WRITE_OP_SOURCE_SHIFT                      4
2940#define INIT_WRITE_OP_RESERVED_MASK                     0x1
2941#define INIT_WRITE_OP_RESERVED_SHIFT                    7
2942#define INIT_WRITE_OP_WIDE_BUS_MASK                     0x1
2943#define INIT_WRITE_OP_WIDE_BUS_SHIFT                    8
2944#define INIT_WRITE_OP_ADDRESS_MASK                      0x7FFFFF
2945#define INIT_WRITE_OP_ADDRESS_SHIFT                     9
2946        union init_write_args                           args;
2947};
2948
2949/* init operation: read */
2950struct init_read_op {
2951        __le32                                          op_data;
2952#define INIT_READ_OP_OP_MASK                            0xF
2953#define INIT_READ_OP_OP_SHIFT                           0
2954#define INIT_READ_OP_POLL_TYPE_MASK                     0xF
2955#define INIT_READ_OP_POLL_TYPE_SHIFT                    4
2956#define INIT_READ_OP_RESERVED_MASK                      0x1
2957#define INIT_READ_OP_RESERVED_SHIFT                     8
2958#define INIT_READ_OP_ADDRESS_MASK                       0x7FFFFF
2959#define INIT_READ_OP_ADDRESS_SHIFT                      9
2960        __le32                                          expected_val;
2961};
2962
2963/* Init operations union */
2964union init_op {
2965        struct init_raw_op                              raw;
2966        struct init_write_op                            write;
2967        struct init_read_op                             read;
2968        struct init_if_mode_op                          if_mode;
2969        struct init_if_phase_op                         if_phase;
2970        struct init_callback_op                         callback;
2971        struct init_delay_op                            delay;
2972};
2973
2974/* Init command operation types */
2975enum init_op_types {
2976        INIT_OP_READ,
2977        INIT_OP_WRITE,
2978        INIT_OP_IF_MODE,
2979        INIT_OP_IF_PHASE,
2980        INIT_OP_DELAY,
2981        INIT_OP_CALLBACK,
2982        MAX_INIT_OP_TYPES
2983};
2984
2985/* init polling types */
2986enum init_poll_types {
2987        INIT_POLL_NONE,
2988        INIT_POLL_EQ,
2989        INIT_POLL_OR,
2990        INIT_POLL_AND,
2991        MAX_INIT_POLL_TYPES
2992};
2993
2994/* init source types */
2995enum init_source_types {
2996        INIT_SRC_INLINE,
2997        INIT_SRC_ZEROS,
2998        INIT_SRC_ARRAY,
2999        INIT_SRC_RUNTIME,
3000        MAX_INIT_SOURCE_TYPES
3001};
3002
3003/* Internal RAM Offsets macro data */
3004struct iro {
3005        u32 base;
3006        u16 m1;
3007        u16 m2;
3008        u16 m3;
3009        u16 size;
3010};
3011
3012/***************************** Public Functions *******************************/
3013
3014/**
3015 * @brief qed_dbg_set_bin_ptr - Sets a pointer to the binary data with debug
3016 *      arrays.
3017 *
3018 * @param p_hwfn -          HW device data
3019 * @param bin_ptr - a pointer to the binary data with debug arrays.
3020 */
3021enum dbg_status qed_dbg_set_bin_ptr(struct qed_hwfn *p_hwfn,
3022                                    const u8 * const bin_ptr);
3023
3024/**
3025 * @brief qed_read_regs - Reads registers into a buffer (using GRC).
3026 *
3027 * @param p_hwfn - HW device data
3028 * @param p_ptt - Ptt window used for writing the registers.
3029 * @param buf - Destination buffer.
3030 * @param addr - Source GRC address in dwords.
3031 * @param len - Number of registers to read.
3032 */
3033void qed_read_regs(struct qed_hwfn *p_hwfn,
3034                   struct qed_ptt *p_ptt, u32 *buf, u32 addr, u32 len);
3035
3036/**
3037 * @brief qed_read_fw_info - Reads FW info from the chip.
3038 *
3039 * The FW info contains FW-related information, such as the FW version,
3040 * FW image (main/L2B/kuku), FW timestamp, etc.
3041 * The FW info is read from the internal RAM of the first Storm that is not in
3042 * reset.
3043 *
3044 * @param p_hwfn -          HW device data
3045 * @param p_ptt -           Ptt window used for writing the registers.
3046 * @param fw_info -     Out: a pointer to write the FW info into.
3047 *
3048 * @return true if the FW info was read successfully from one of the Storms,
3049 * or false if all Storms are in reset.
3050 */
3051bool qed_read_fw_info(struct qed_hwfn *p_hwfn,
3052                      struct qed_ptt *p_ptt, struct fw_info *fw_info);
3053/**
3054 * @brief qed_dbg_grc_config - Sets the value of a GRC parameter.
3055 *
3056 * @param p_hwfn -      HW device data
3057 * @param grc_param -   GRC parameter
3058 * @param val -         Value to set.
3059 *
3060 * @return error if one of the following holds:
3061 *      - the version wasn't set
3062 *      - grc_param is invalid
3063 *      - val is outside the allowed boundaries
3064 */
3065enum dbg_status qed_dbg_grc_config(struct qed_hwfn *p_hwfn,
3066                                   enum dbg_grc_params grc_param, u32 val);
3067
3068/**
3069 * @brief qed_dbg_grc_set_params_default - Reverts all GRC parameters to their
3070 *      default value.
3071 *
3072 * @param p_hwfn                - HW device data
3073 */
3074void qed_dbg_grc_set_params_default(struct qed_hwfn *p_hwfn);
3075/**
3076 * @brief qed_dbg_grc_get_dump_buf_size - Returns the required buffer size for
3077 *      GRC Dump.
3078 *
3079 * @param p_hwfn - HW device data
3080 * @param p_ptt - Ptt window used for writing the registers.
3081 * @param buf_size - OUT: required buffer size (in dwords) for the GRC Dump
3082 *      data.
3083 *
3084 * @return error if one of the following holds:
3085 *      - the version wasn't set
3086 * Otherwise, returns ok.
3087 */
3088enum dbg_status qed_dbg_grc_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3089                                              struct qed_ptt *p_ptt,
3090                                              u32 *buf_size);
3091
3092/**
3093 * @brief qed_dbg_grc_dump - Dumps GRC data into the specified buffer.
3094 *
3095 * @param p_hwfn - HW device data
3096 * @param p_ptt - Ptt window used for writing the registers.
3097 * @param dump_buf - Pointer to write the collected GRC data into.
3098 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3099 * @param num_dumped_dwords - OUT: number of dumped dwords.
3100 *
3101 * @return error if one of the following holds:
3102 *      - the version wasn't set
3103 *      - the specified dump buffer is too small
3104 * Otherwise, returns ok.
3105 */
3106enum dbg_status qed_dbg_grc_dump(struct qed_hwfn *p_hwfn,
3107                                 struct qed_ptt *p_ptt,
3108                                 u32 *dump_buf,
3109                                 u32 buf_size_in_dwords,
3110                                 u32 *num_dumped_dwords);
3111
3112/**
3113 * @brief qed_dbg_idle_chk_get_dump_buf_size - Returns the required buffer size
3114 *      for idle check results.
3115 *
3116 * @param p_hwfn - HW device data
3117 * @param p_ptt - Ptt window used for writing the registers.
3118 * @param buf_size - OUT: required buffer size (in dwords) for the idle check
3119 *      data.
3120 *
3121 * @return error if one of the following holds:
3122 *      - the version wasn't set
3123 * Otherwise, returns ok.
3124 */
3125enum dbg_status qed_dbg_idle_chk_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3126                                                   struct qed_ptt *p_ptt,
3127                                                   u32 *buf_size);
3128
3129/**
3130 * @brief qed_dbg_idle_chk_dump - Performs idle check and writes the results
3131 *      into the specified buffer.
3132 *
3133 * @param p_hwfn - HW device data
3134 * @param p_ptt - Ptt window used for writing the registers.
3135 * @param dump_buf - Pointer to write the idle check data into.
3136 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3137 * @param num_dumped_dwords - OUT: number of dumped dwords.
3138 *
3139 * @return error if one of the following holds:
3140 *      - the version wasn't set
3141 *      - the specified buffer is too small
3142 * Otherwise, returns ok.
3143 */
3144enum dbg_status qed_dbg_idle_chk_dump(struct qed_hwfn *p_hwfn,
3145                                      struct qed_ptt *p_ptt,
3146                                      u32 *dump_buf,
3147                                      u32 buf_size_in_dwords,
3148                                      u32 *num_dumped_dwords);
3149
3150/**
3151 * @brief qed_dbg_mcp_trace_get_dump_buf_size - Returns the required buffer size
3152 *      for mcp trace results.
3153 *
3154 * @param p_hwfn - HW device data
3155 * @param p_ptt - Ptt window used for writing the registers.
3156 * @param buf_size - OUT: required buffer size (in dwords) for mcp trace data.
3157 *
3158 * @return error if one of the following holds:
3159 *      - the version wasn't set
3160 *      - the trace data in MCP scratchpad contain an invalid signature
3161 *      - the bundle ID in NVRAM is invalid
3162 *      - the trace meta data cannot be found (in NVRAM or image file)
3163 * Otherwise, returns ok.
3164 */
3165enum dbg_status qed_dbg_mcp_trace_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3166                                                    struct qed_ptt *p_ptt,
3167                                                    u32 *buf_size);
3168
3169/**
3170 * @brief qed_dbg_mcp_trace_dump - Performs mcp trace and writes the results
3171 *      into the specified buffer.
3172 *
3173 * @param p_hwfn - HW device data
3174 * @param p_ptt - Ptt window used for writing the registers.
3175 * @param dump_buf - Pointer to write the mcp trace data into.
3176 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3177 * @param num_dumped_dwords - OUT: number of dumped dwords.
3178 *
3179 * @return error if one of the following holds:
3180 *      - the version wasn't set
3181 *      - the specified buffer is too small
3182 *      - the trace data in MCP scratchpad contain an invalid signature
3183 *      - the bundle ID in NVRAM is invalid
3184 *      - the trace meta data cannot be found (in NVRAM or image file)
3185 *      - the trace meta data cannot be read (from NVRAM or image file)
3186 * Otherwise, returns ok.
3187 */
3188enum dbg_status qed_dbg_mcp_trace_dump(struct qed_hwfn *p_hwfn,
3189                                       struct qed_ptt *p_ptt,
3190                                       u32 *dump_buf,
3191                                       u32 buf_size_in_dwords,
3192                                       u32 *num_dumped_dwords);
3193
3194/**
3195 * @brief qed_dbg_reg_fifo_get_dump_buf_size - Returns the required buffer size
3196 *      for grc trace fifo results.
3197 *
3198 * @param p_hwfn - HW device data
3199 * @param p_ptt - Ptt window used for writing the registers.
3200 * @param buf_size - OUT: required buffer size (in dwords) for reg fifo data.
3201 *
3202 * @return error if one of the following holds:
3203 *      - the version wasn't set
3204 * Otherwise, returns ok.
3205 */
3206enum dbg_status qed_dbg_reg_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3207                                                   struct qed_ptt *p_ptt,
3208                                                   u32 *buf_size);
3209
3210/**
3211 * @brief qed_dbg_reg_fifo_dump - Reads the reg fifo and writes the results into
3212 *      the specified buffer.
3213 *
3214 * @param p_hwfn - HW device data
3215 * @param p_ptt - Ptt window used for writing the registers.
3216 * @param dump_buf - Pointer to write the reg fifo data into.
3217 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3218 * @param num_dumped_dwords - OUT: number of dumped dwords.
3219 *
3220 * @return error if one of the following holds:
3221 *      - the version wasn't set
3222 *      - the specified buffer is too small
3223 *      - DMAE transaction failed
3224 * Otherwise, returns ok.
3225 */
3226enum dbg_status qed_dbg_reg_fifo_dump(struct qed_hwfn *p_hwfn,
3227                                      struct qed_ptt *p_ptt,
3228                                      u32 *dump_buf,
3229                                      u32 buf_size_in_dwords,
3230                                      u32 *num_dumped_dwords);
3231
3232/**
3233 * @brief qed_dbg_igu_fifo_get_dump_buf_size - Returns the required buffer size
3234 *      for the IGU fifo results.
3235 *
3236 * @param p_hwfn - HW device data
3237 * @param p_ptt - Ptt window used for writing the registers.
3238 * @param buf_size - OUT: required buffer size (in dwords) for the IGU fifo
3239 *      data.
3240 *
3241 * @return error if one of the following holds:
3242 *      - the version wasn't set
3243 * Otherwise, returns ok.
3244 */
3245enum dbg_status qed_dbg_igu_fifo_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3246                                                   struct qed_ptt *p_ptt,
3247                                                   u32 *buf_size);
3248
3249/**
3250 * @brief qed_dbg_igu_fifo_dump - Reads the IGU fifo and writes the results into
3251 *      the specified buffer.
3252 *
3253 * @param p_hwfn - HW device data
3254 * @param p_ptt - Ptt window used for writing the registers.
3255 * @param dump_buf - Pointer to write the IGU fifo data into.
3256 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3257 * @param num_dumped_dwords - OUT: number of dumped dwords.
3258 *
3259 * @return error if one of the following holds:
3260 *      - the version wasn't set
3261 *      - the specified buffer is too small
3262 *      - DMAE transaction failed
3263 * Otherwise, returns ok.
3264 */
3265enum dbg_status qed_dbg_igu_fifo_dump(struct qed_hwfn *p_hwfn,
3266                                      struct qed_ptt *p_ptt,
3267                                      u32 *dump_buf,
3268                                      u32 buf_size_in_dwords,
3269                                      u32 *num_dumped_dwords);
3270
3271/**
3272 * @brief qed_dbg_protection_override_get_dump_buf_size - Returns the required
3273 *      buffer size for protection override window results.
3274 *
3275 * @param p_hwfn - HW device data
3276 * @param p_ptt - Ptt window used for writing the registers.
3277 * @param buf_size - OUT: required buffer size (in dwords) for protection
3278 *      override data.
3279 *
3280 * @return error if one of the following holds:
3281 *      - the version wasn't set
3282 * Otherwise, returns ok.
3283 */
3284enum dbg_status
3285qed_dbg_protection_override_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3286                                              struct qed_ptt *p_ptt,
3287                                              u32 *buf_size);
3288/**
3289 * @brief qed_dbg_protection_override_dump - Reads protection override window
3290 *      entries and writes the results into the specified buffer.
3291 *
3292 * @param p_hwfn - HW device data
3293 * @param p_ptt - Ptt window used for writing the registers.
3294 * @param dump_buf - Pointer to write the protection override data into.
3295 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3296 * @param num_dumped_dwords - OUT: number of dumped dwords.
3297 *
3298 * @return error if one of the following holds:
3299 *      - the version wasn't set
3300 *      - the specified buffer is too small
3301 *      - DMAE transaction failed
3302 * Otherwise, returns ok.
3303 */
3304enum dbg_status qed_dbg_protection_override_dump(struct qed_hwfn *p_hwfn,
3305                                                 struct qed_ptt *p_ptt,
3306                                                 u32 *dump_buf,
3307                                                 u32 buf_size_in_dwords,
3308                                                 u32 *num_dumped_dwords);
3309/**
3310 * @brief qed_dbg_fw_asserts_get_dump_buf_size - Returns the required buffer
3311 *      size for FW Asserts results.
3312 *
3313 * @param p_hwfn - HW device data
3314 * @param p_ptt - Ptt window used for writing the registers.
3315 * @param buf_size - OUT: required buffer size (in dwords) for FW Asserts data.
3316 *
3317 * @return error if one of the following holds:
3318 *      - the version wasn't set
3319 * Otherwise, returns ok.
3320 */
3321enum dbg_status qed_dbg_fw_asserts_get_dump_buf_size(struct qed_hwfn *p_hwfn,
3322                                                     struct qed_ptt *p_ptt,
3323                                                     u32 *buf_size);
3324/**
3325 * @brief qed_dbg_fw_asserts_dump - Reads the FW Asserts and writes the results
3326 *      into the specified buffer.
3327 *
3328 * @param p_hwfn - HW device data
3329 * @param p_ptt - Ptt window used for writing the registers.
3330 * @param dump_buf - Pointer to write the FW Asserts data into.
3331 * @param buf_size_in_dwords - Size of the specified buffer in dwords.
3332 * @param num_dumped_dwords - OUT: number of dumped dwords.
3333 *
3334 * @return error if one of the following holds:
3335 *      - the version wasn't set
3336 *      - the specified buffer is too small
3337 * Otherwise, returns ok.
3338 */
3339enum dbg_status qed_dbg_fw_asserts_dump(struct qed_hwfn *p_hwfn,
3340                                        struct qed_ptt *p_ptt,
3341                                        u32 *dump_buf,
3342                                        u32 buf_size_in_dwords,
3343                                        u32 *num_dumped_dwords);
3344
3345/**
3346 * @brief qed_dbg_read_attn - Reads the attention registers of the specified
3347 * block and type, and writes the results into the specified buffer.
3348 *
3349 * @param p_hwfn -       HW device data
3350 * @param p_ptt -        Ptt window used for writing the registers.
3351 * @param block -        Block ID.
3352 * @param attn_type -    Attention type.
3353 * @param clear_status - Indicates if the attention status should be cleared.
3354 * @param results -      OUT: Pointer to write the read results into
3355 *
3356 * @return error if one of the following holds:
3357 *      - the version wasn't set
3358 * Otherwise, returns ok.
3359 */
3360enum dbg_status qed_dbg_read_attn(struct qed_hwfn *p_hwfn,
3361                                  struct qed_ptt *p_ptt,
3362                                  enum block_id block,
3363                                  enum dbg_attn_type attn_type,
3364                                  bool clear_status,
3365                                  struct dbg_attn_block_result *results);
3366
3367/**
3368 * @brief qed_dbg_print_attn - Prints attention registers values in the
3369 *      specified results struct.
3370 *
3371 * @param p_hwfn
3372 * @param results - Pointer to the attention read results
3373 *
3374 * @return error if one of the following holds:
3375 *      - the version wasn't set
3376 * Otherwise, returns ok.
3377 */
3378enum dbg_status qed_dbg_print_attn(struct qed_hwfn *p_hwfn,
3379                                   struct dbg_attn_block_result *results);
3380
3381/******************************* Data Types **********************************/
3382
3383struct mcp_trace_format {
3384        u32 data;
3385#define MCP_TRACE_FORMAT_MODULE_MASK    0x0000ffff
3386#define MCP_TRACE_FORMAT_MODULE_OFFSET  0
3387#define MCP_TRACE_FORMAT_LEVEL_MASK     0x00030000
3388#define MCP_TRACE_FORMAT_LEVEL_OFFSET   16
3389#define MCP_TRACE_FORMAT_P1_SIZE_MASK   0x000c0000
3390#define MCP_TRACE_FORMAT_P1_SIZE_OFFSET 18
3391#define MCP_TRACE_FORMAT_P2_SIZE_MASK   0x00300000
3392#define MCP_TRACE_FORMAT_P2_SIZE_OFFSET 20
3393#define MCP_TRACE_FORMAT_P3_SIZE_MASK   0x00c00000
3394#define MCP_TRACE_FORMAT_P3_SIZE_OFFSET 22
3395#define MCP_TRACE_FORMAT_LEN_MASK       0xff000000
3396#define MCP_TRACE_FORMAT_LEN_OFFSET     24
3397
3398        char *format_str;
3399};
3400
3401/* MCP Trace Meta data structure */
3402struct mcp_trace_meta {
3403        u32 modules_num;
3404        char **modules;
3405        u32 formats_num;
3406        struct mcp_trace_format *formats;
3407        bool is_allocated;
3408};
3409
3410/* Debug Tools user data */
3411struct dbg_tools_user_data {
3412        struct mcp_trace_meta mcp_trace_meta;
3413        const u32 *mcp_trace_user_meta_buf;
3414};
3415
3416/******************************** Constants **********************************/
3417
3418#define MAX_NAME_LEN    16
3419
3420/***************************** Public Functions *******************************/
3421
3422/**
3423 * @brief qed_dbg_user_set_bin_ptr - Sets a pointer to the binary data with
3424 *      debug arrays.
3425 *
3426 * @param p_hwfn - HW device data
3427 * @param bin_ptr - a pointer to the binary data with debug arrays.
3428 */
3429enum dbg_status qed_dbg_user_set_bin_ptr(struct qed_hwfn *p_hwfn,
3430                                         const u8 * const bin_ptr);
3431
3432/**
3433 * @brief qed_dbg_alloc_user_data - Allocates user debug data.
3434 *
3435 * @param p_hwfn -               HW device data
3436 * @param user_data_ptr - OUT: a pointer to the allocated memory.
3437 */
3438enum dbg_status qed_dbg_alloc_user_data(struct qed_hwfn *p_hwfn,
3439                                        void **user_data_ptr);
3440
3441/**
3442 * @brief qed_dbg_get_status_str - Returns a string for the specified status.
3443 *
3444 * @param status - a debug status code.
3445 *
3446 * @return a string for the specified status
3447 */
3448const char *qed_dbg_get_status_str(enum dbg_status status);
3449
3450/**
3451 * @brief qed_get_idle_chk_results_buf_size - Returns the required buffer size
3452 *      for idle check results (in bytes).
3453 *
3454 * @param p_hwfn - HW device data
3455 * @param dump_buf - idle check dump buffer.
3456 * @param num_dumped_dwords - number of dwords that were dumped.
3457 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3458 *      results.
3459 *
3460 * @return error if the parsing fails, ok otherwise.
3461 */
3462enum dbg_status qed_get_idle_chk_results_buf_size(struct qed_hwfn *p_hwfn,
3463                                                  u32 *dump_buf,
3464                                                  u32  num_dumped_dwords,
3465                                                  u32 *results_buf_size);
3466/**
3467 * @brief qed_print_idle_chk_results - Prints idle check results
3468 *
3469 * @param p_hwfn - HW device data
3470 * @param dump_buf - idle check dump buffer.
3471 * @param num_dumped_dwords - number of dwords that were dumped.
3472 * @param results_buf - buffer for printing the idle check results.
3473 * @param num_errors - OUT: number of errors found in idle check.
3474 * @param num_warnings - OUT: number of warnings found in idle check.
3475 *
3476 * @return error if the parsing fails, ok otherwise.
3477 */
3478enum dbg_status qed_print_idle_chk_results(struct qed_hwfn *p_hwfn,
3479                                           u32 *dump_buf,
3480                                           u32 num_dumped_dwords,
3481                                           char *results_buf,
3482                                           u32 *num_errors,
3483                                           u32 *num_warnings);
3484
3485/**
3486 * @brief qed_dbg_mcp_trace_set_meta_data - Sets the MCP Trace meta data.
3487 *
3488 * Needed in case the MCP Trace dump doesn't contain the meta data (e.g. due to
3489 * no NVRAM access).
3490 *
3491 * @param data - pointer to MCP Trace meta data
3492 * @param size - size of MCP Trace meta data in dwords
3493 */
3494void qed_dbg_mcp_trace_set_meta_data(struct qed_hwfn *p_hwfn,
3495                                     const u32 *meta_buf);
3496
3497/**
3498 * @brief qed_get_mcp_trace_results_buf_size - Returns the required buffer size
3499 *      for MCP Trace results (in bytes).
3500 *
3501 * @param p_hwfn - HW device data
3502 * @param dump_buf - MCP Trace dump buffer.
3503 * @param num_dumped_dwords - number of dwords that were dumped.
3504 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3505 *      results.
3506 *
3507 * @return error if the parsing fails, ok otherwise.
3508 */
3509enum dbg_status qed_get_mcp_trace_results_buf_size(struct qed_hwfn *p_hwfn,
3510                                                   u32 *dump_buf,
3511                                                   u32 num_dumped_dwords,
3512                                                   u32 *results_buf_size);
3513
3514/**
3515 * @brief qed_print_mcp_trace_results - Prints MCP Trace results
3516 *
3517 * @param p_hwfn - HW device data
3518 * @param dump_buf - mcp trace dump buffer, starting from the header.
3519 * @param num_dumped_dwords - number of dwords that were dumped.
3520 * @param results_buf - buffer for printing the mcp trace results.
3521 *
3522 * @return error if the parsing fails, ok otherwise.
3523 */
3524enum dbg_status qed_print_mcp_trace_results(struct qed_hwfn *p_hwfn,
3525                                            u32 *dump_buf,
3526                                            u32 num_dumped_dwords,
3527                                            char *results_buf);
3528
3529/**
3530 * @brief qed_print_mcp_trace_results_cont - Prints MCP Trace results, and
3531 * keeps the MCP trace meta data allocated, to support continuous MCP Trace
3532 * parsing. After the continuous parsing ends, mcp_trace_free_meta_data should
3533 * be called to free the meta data.
3534 *
3535 * @param p_hwfn -            HW device data
3536 * @param dump_buf -          mcp trace dump buffer, starting from the header.
3537 * @param results_buf -       buffer for printing the mcp trace results.
3538 *
3539 * @return error if the parsing fails, ok otherwise.
3540 */
3541enum dbg_status qed_print_mcp_trace_results_cont(struct qed_hwfn *p_hwfn,
3542                                                 u32 *dump_buf,
3543                                                 char *results_buf);
3544
3545/**
3546 * @brief print_mcp_trace_line - Prints MCP Trace results for a single line
3547 *
3548 * @param p_hwfn -            HW device data
3549 * @param dump_buf -          mcp trace dump buffer, starting from the header.
3550 * @param num_dumped_bytes -  number of bytes that were dumped.
3551 * @param results_buf -       buffer for printing the mcp trace results.
3552 *
3553 * @return error if the parsing fails, ok otherwise.
3554 */
3555enum dbg_status qed_print_mcp_trace_line(struct qed_hwfn *p_hwfn,
3556                                         u8 *dump_buf,
3557                                         u32 num_dumped_bytes,
3558                                         char *results_buf);
3559
3560/**
3561 * @brief mcp_trace_free_meta_data - Frees the MCP Trace meta data.
3562 * Should be called after continuous MCP Trace parsing.
3563 *
3564 * @param p_hwfn - HW device data
3565 */
3566void qed_mcp_trace_free_meta_data(struct qed_hwfn *p_hwfn);
3567
3568/**
3569 * @brief qed_get_reg_fifo_results_buf_size - Returns the required buffer size
3570 *      for reg_fifo results (in bytes).
3571 *
3572 * @param p_hwfn - HW device data
3573 * @param dump_buf - reg fifo dump buffer.
3574 * @param num_dumped_dwords - number of dwords that were dumped.
3575 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3576 *      results.
3577 *
3578 * @return error if the parsing fails, ok otherwise.
3579 */
3580enum dbg_status qed_get_reg_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3581                                                  u32 *dump_buf,
3582                                                  u32 num_dumped_dwords,
3583                                                  u32 *results_buf_size);
3584
3585/**
3586 * @brief qed_print_reg_fifo_results - Prints reg fifo results
3587 *
3588 * @param p_hwfn - HW device data
3589 * @param dump_buf - reg fifo dump buffer, starting from the header.
3590 * @param num_dumped_dwords - number of dwords that were dumped.
3591 * @param results_buf - buffer for printing the reg fifo results.
3592 *
3593 * @return error if the parsing fails, ok otherwise.
3594 */
3595enum dbg_status qed_print_reg_fifo_results(struct qed_hwfn *p_hwfn,
3596                                           u32 *dump_buf,
3597                                           u32 num_dumped_dwords,
3598                                           char *results_buf);
3599
3600/**
3601 * @brief qed_get_igu_fifo_results_buf_size - Returns the required buffer size
3602 *      for igu_fifo results (in bytes).
3603 *
3604 * @param p_hwfn - HW device data
3605 * @param dump_buf - IGU fifo dump buffer.
3606 * @param num_dumped_dwords - number of dwords that were dumped.
3607 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3608 *      results.
3609 *
3610 * @return error if the parsing fails, ok otherwise.
3611 */
3612enum dbg_status qed_get_igu_fifo_results_buf_size(struct qed_hwfn *p_hwfn,
3613                                                  u32 *dump_buf,
3614                                                  u32 num_dumped_dwords,
3615                                                  u32 *results_buf_size);
3616
3617/**
3618 * @brief qed_print_igu_fifo_results - Prints IGU fifo results
3619 *
3620 * @param p_hwfn - HW device data
3621 * @param dump_buf - IGU fifo dump buffer, starting from the header.
3622 * @param num_dumped_dwords - number of dwords that were dumped.
3623 * @param results_buf - buffer for printing the IGU fifo results.
3624 *
3625 * @return error if the parsing fails, ok otherwise.
3626 */
3627enum dbg_status qed_print_igu_fifo_results(struct qed_hwfn *p_hwfn,
3628                                           u32 *dump_buf,
3629                                           u32 num_dumped_dwords,
3630                                           char *results_buf);
3631
3632/**
3633 * @brief qed_get_protection_override_results_buf_size - Returns the required
3634 *      buffer size for protection override results (in bytes).
3635 *
3636 * @param p_hwfn - HW device data
3637 * @param dump_buf - protection override dump buffer.
3638 * @param num_dumped_dwords - number of dwords that were dumped.
3639 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3640 *      results.
3641 *
3642 * @return error if the parsing fails, ok otherwise.
3643 */
3644enum dbg_status
3645qed_get_protection_override_results_buf_size(struct qed_hwfn *p_hwfn,
3646                                             u32 *dump_buf,
3647                                             u32 num_dumped_dwords,
3648                                             u32 *results_buf_size);
3649
3650/**
3651 * @brief qed_print_protection_override_results - Prints protection override
3652 *      results.
3653 *
3654 * @param p_hwfn - HW device data
3655 * @param dump_buf - protection override dump buffer, starting from the header.
3656 * @param num_dumped_dwords - number of dwords that were dumped.
3657 * @param results_buf - buffer for printing the reg fifo results.
3658 *
3659 * @return error if the parsing fails, ok otherwise.
3660 */
3661enum dbg_status qed_print_protection_override_results(struct qed_hwfn *p_hwfn,
3662                                                      u32 *dump_buf,
3663                                                      u32 num_dumped_dwords,
3664                                                      char *results_buf);
3665
3666/**
3667 * @brief qed_get_fw_asserts_results_buf_size - Returns the required buffer size
3668 *      for FW Asserts results (in bytes).
3669 *
3670 * @param p_hwfn - HW device data
3671 * @param dump_buf - FW Asserts dump buffer.
3672 * @param num_dumped_dwords - number of dwords that were dumped.
3673 * @param results_buf_size - OUT: required buffer size (in bytes) for the parsed
3674 *      results.
3675 *
3676 * @return error if the parsing fails, ok otherwise.
3677 */
3678enum dbg_status qed_get_fw_asserts_results_buf_size(struct qed_hwfn *p_hwfn,
3679                                                    u32 *dump_buf,
3680                                                    u32 num_dumped_dwords,
3681                                                    u32 *results_buf_size);
3682
3683/**
3684 * @brief qed_print_fw_asserts_results - Prints FW Asserts results
3685 *
3686 * @param p_hwfn - HW device data
3687 * @param dump_buf - FW Asserts dump buffer, starting from the header.
3688 * @param num_dumped_dwords - number of dwords that were dumped.
3689 * @param results_buf - buffer for printing the FW Asserts results.
3690 *
3691 * @return error if the parsing fails, ok otherwise.
3692 */
3693enum dbg_status qed_print_fw_asserts_results(struct qed_hwfn *p_hwfn,
3694                                             u32 *dump_buf,
3695                                             u32 num_dumped_dwords,
3696                                             char *results_buf);
3697
3698/**
3699 * @brief qed_dbg_parse_attn - Parses and prints attention registers values in
3700 * the specified results struct.
3701 *
3702 * @param p_hwfn -  HW device data
3703 * @param results - Pointer to the attention read results
3704 *
3705 * @return error if one of the following holds:
3706 *      - the version wasn't set
3707 * Otherwise, returns ok.
3708 */
3709enum dbg_status qed_dbg_parse_attn(struct qed_hwfn *p_hwfn,
3710                                   struct dbg_attn_block_result *results);
3711
3712/* Win 2 */
3713#define GTT_BAR0_MAP_REG_IGU_CMD        0x00f000UL
3714
3715/* Win 3 */
3716#define GTT_BAR0_MAP_REG_TSDM_RAM       0x010000UL
3717
3718/* Win 4 */
3719#define GTT_BAR0_MAP_REG_MSDM_RAM       0x011000UL
3720
3721/* Win 5 */
3722#define GTT_BAR0_MAP_REG_MSDM_RAM_1024  0x012000UL
3723
3724/* Win 6 */
3725#define GTT_BAR0_MAP_REG_MSDM_RAM_2048  0x013000UL
3726
3727/* Win 7 */
3728#define GTT_BAR0_MAP_REG_USDM_RAM       0x014000UL
3729
3730/* Win 8 */
3731#define GTT_BAR0_MAP_REG_USDM_RAM_1024  0x015000UL
3732
3733/* Win 9 */
3734#define GTT_BAR0_MAP_REG_USDM_RAM_2048  0x016000UL
3735
3736/* Win 10 */
3737#define GTT_BAR0_MAP_REG_XSDM_RAM       0x017000UL
3738
3739/* Win 11 */
3740#define GTT_BAR0_MAP_REG_XSDM_RAM_1024  0x018000UL
3741
3742/* Win 12 */
3743#define GTT_BAR0_MAP_REG_YSDM_RAM       0x019000UL
3744
3745/* Win 13 */
3746#define GTT_BAR0_MAP_REG_PSDM_RAM       0x01a000UL
3747
3748/**
3749 * @brief qed_qm_pf_mem_size - prepare QM ILT sizes
3750 *
3751 * Returns the required host memory size in 4KB units.
3752 * Must be called before all QM init HSI functions.
3753 *
3754 * @param num_pf_cids - number of connections used by this PF
3755 * @param num_vf_cids - number of connections used by VFs of this PF
3756 * @param num_tids - number of tasks used by this PF
3757 * @param num_pf_pqs - number of PQs used by this PF
3758 * @param num_vf_pqs - number of PQs used by VFs of this PF
3759 *
3760 * @return The required host memory size in 4KB units.
3761 */
3762u32 qed_qm_pf_mem_size(u32 num_pf_cids,
3763                       u32 num_vf_cids,
3764                       u32 num_tids, u16 num_pf_pqs, u16 num_vf_pqs);
3765
3766struct qed_qm_common_rt_init_params {
3767        u8 max_ports_per_engine;
3768        u8 max_phys_tcs_per_port;
3769        bool pf_rl_en;
3770        bool pf_wfq_en;
3771        bool global_rl_en;
3772        bool vport_wfq_en;
3773        struct init_qm_port_params *port_params;
3774};
3775
3776int qed_qm_common_rt_init(struct qed_hwfn *p_hwfn,
3777                          struct qed_qm_common_rt_init_params *p_params);
3778
3779struct qed_qm_pf_rt_init_params {
3780        u8 port_id;
3781        u8 pf_id;
3782        u8 max_phys_tcs_per_port;
3783        bool is_pf_loading;
3784        u32 num_pf_cids;
3785        u32 num_vf_cids;
3786        u32 num_tids;
3787        u16 start_pq;
3788        u16 num_pf_pqs;
3789        u16 num_vf_pqs;
3790        u16 start_vport;
3791        u16 num_vports;
3792        u16 pf_wfq;
3793        u32 pf_rl;
3794        struct init_qm_pq_params *pq_params;
3795        struct init_qm_vport_params *vport_params;
3796};
3797
3798int qed_qm_pf_rt_init(struct qed_hwfn *p_hwfn,
3799        struct qed_ptt *p_ptt,
3800        struct qed_qm_pf_rt_init_params *p_params);
3801
3802/**
3803 * @brief qed_init_pf_wfq - Initializes the WFQ weight of the specified PF
3804 *
3805 * @param p_hwfn
3806 * @param p_ptt - ptt window used for writing the registers
3807 * @param pf_id - PF ID
3808 * @param pf_wfq - WFQ weight. Must be non-zero.
3809 *
3810 * @return 0 on success, -1 on error.
3811 */
3812int qed_init_pf_wfq(struct qed_hwfn *p_hwfn,
3813                    struct qed_ptt *p_ptt, u8 pf_id, u16 pf_wfq);
3814
3815/**
3816 * @brief qed_init_pf_rl - Initializes the rate limit of the specified PF
3817 *
3818 * @param p_hwfn
3819 * @param p_ptt - ptt window used for writing the registers
3820 * @param pf_id - PF ID
3821 * @param pf_rl - rate limit in Mb/sec units
3822 *
3823 * @return 0 on success, -1 on error.
3824 */
3825int qed_init_pf_rl(struct qed_hwfn *p_hwfn,
3826                   struct qed_ptt *p_ptt, u8 pf_id, u32 pf_rl);
3827
3828/**
3829 * @brief qed_init_vport_wfq Initializes the WFQ weight of the specified VPORT
3830 *
3831 * @param p_hwfn
3832 * @param p_ptt - ptt window used for writing the registers
3833 * @param first_tx_pq_id- An array containing the first Tx PQ ID associated
3834 *        with the VPORT for each TC. This array is filled by
3835 *        qed_qm_pf_rt_init
3836 * @param vport_wfq - WFQ weight. Must be non-zero.
3837 *
3838 * @return 0 on success, -1 on error.
3839 */
3840int qed_init_vport_wfq(struct qed_hwfn *p_hwfn,
3841                       struct qed_ptt *p_ptt,
3842                       u16 first_tx_pq_id[NUM_OF_TCS], u16 wfq);
3843
3844/**
3845 * @brief qed_init_global_rl - Initializes the rate limit of the specified
3846 * rate limiter
3847 *
3848 * @param p_hwfn
3849 * @param p_ptt - ptt window used for writing the registers
3850 * @param rl_id - RL ID
3851 * @param rate_limit - rate limit in Mb/sec units
3852 *
3853 * @return 0 on success, -1 on error.
3854 */
3855int qed_init_global_rl(struct qed_hwfn *p_hwfn,
3856                       struct qed_ptt *p_ptt,
3857                       u16 rl_id, u32 rate_limit);
3858
3859/**
3860 * @brief qed_send_qm_stop_cmd  Sends a stop command to the QM
3861 *
3862 * @param p_hwfn
3863 * @param p_ptt
3864 * @param is_release_cmd - true for release, false for stop.
3865 * @param is_tx_pq - true for Tx PQs, false for Other PQs.
3866 * @param start_pq - first PQ ID to stop
3867 * @param num_pqs - Number of PQs to stop, starting from start_pq.
3868 *
3869 * @return bool, true if successful, false if timeout occurred while waiting for
3870 *      QM command done.
3871 */
3872bool qed_send_qm_stop_cmd(struct qed_hwfn *p_hwfn,
3873                          struct qed_ptt *p_ptt,
3874                          bool is_release_cmd,
3875                          bool is_tx_pq, u16 start_pq, u16 num_pqs);
3876
3877/**
3878 * @brief qed_set_vxlan_dest_port - initializes vxlan tunnel destination udp port
3879 *
3880 * @param p_hwfn
3881 * @param p_ptt - ptt window used for writing the registers.
3882 * @param dest_port - vxlan destination udp port.
3883 */
3884void qed_set_vxlan_dest_port(struct qed_hwfn *p_hwfn,
3885                             struct qed_ptt *p_ptt, u16 dest_port);
3886
3887/**
3888 * @brief qed_set_vxlan_enable - enable or disable VXLAN tunnel in HW
3889 *
3890 * @param p_hwfn
3891 * @param p_ptt - ptt window used for writing the registers.
3892 * @param vxlan_enable - vxlan enable flag.
3893 */
3894void qed_set_vxlan_enable(struct qed_hwfn *p_hwfn,
3895                          struct qed_ptt *p_ptt, bool vxlan_enable);
3896
3897/**
3898 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3899 *
3900 * @param p_hwfn
3901 * @param p_ptt - ptt window used for writing the registers.
3902 * @param eth_gre_enable - eth GRE enable enable flag.
3903 * @param ip_gre_enable - IP GRE enable enable flag.
3904 */
3905void qed_set_gre_enable(struct qed_hwfn *p_hwfn,
3906                        struct qed_ptt *p_ptt,
3907                        bool eth_gre_enable, bool ip_gre_enable);
3908
3909/**
3910 * @brief qed_set_geneve_dest_port - initializes geneve tunnel destination udp port
3911 *
3912 * @param p_hwfn
3913 * @param p_ptt - ptt window used for writing the registers.
3914 * @param dest_port - geneve destination udp port.
3915 */
3916void qed_set_geneve_dest_port(struct qed_hwfn *p_hwfn,
3917                              struct qed_ptt *p_ptt, u16 dest_port);
3918
3919/**
3920 * @brief qed_set_gre_enable - enable or disable GRE tunnel in HW
3921 *
3922 * @param p_ptt - ptt window used for writing the registers.
3923 * @param eth_geneve_enable - eth GENEVE enable enable flag.
3924 * @param ip_geneve_enable - IP GENEVE enable enable flag.
3925 */
3926void qed_set_geneve_enable(struct qed_hwfn *p_hwfn,
3927                           struct qed_ptt *p_ptt,
3928                           bool eth_geneve_enable, bool ip_geneve_enable);
3929
3930void qed_set_vxlan_no_l2_enable(struct qed_hwfn *p_hwfn,
3931                                struct qed_ptt *p_ptt, bool enable);
3932
3933/**
3934 * @brief qed_gft_disable - Disable GFT
3935 *
3936 * @param p_hwfn
3937 * @param p_ptt - ptt window used for writing the registers.
3938 * @param pf_id - pf on which to disable GFT.
3939 */
3940void qed_gft_disable(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, u16 pf_id);
3941
3942/**
3943 * @brief qed_gft_config - Enable and configure HW for GFT
3944 *
3945 * @param p_hwfn - HW device data
3946 * @param p_ptt - ptt window used for writing the registers.
3947 * @param pf_id - pf on which to enable GFT.
3948 * @param tcp - set profile tcp packets.
3949 * @param udp - set profile udp  packet.
3950 * @param ipv4 - set profile ipv4 packet.
3951 * @param ipv6 - set profile ipv6 packet.
3952 * @param profile_type - define packet same fields. Use enum gft_profile_type.
3953 */
3954void qed_gft_config(struct qed_hwfn *p_hwfn,
3955                    struct qed_ptt *p_ptt,
3956                    u16 pf_id,
3957                    bool tcp,
3958                    bool udp,
3959                    bool ipv4, bool ipv6, enum gft_profile_type profile_type);
3960
3961/**
3962 * @brief qed_enable_context_validation - Enable and configure context
3963 *      validation.
3964 *
3965 * @param p_hwfn
3966 * @param p_ptt - ptt window used for writing the registers.
3967 */
3968void qed_enable_context_validation(struct qed_hwfn *p_hwfn,
3969                                   struct qed_ptt *p_ptt);
3970
3971/**
3972 * @brief qed_calc_session_ctx_validation - Calcualte validation byte for
3973 *      session context.
3974 *
3975 * @param p_ctx_mem - pointer to context memory.
3976 * @param ctx_size - context size.
3977 * @param ctx_type - context type.
3978 * @param cid - context cid.
3979 */
3980void qed_calc_session_ctx_validation(void *p_ctx_mem,
3981                                     u16 ctx_size, u8 ctx_type, u32 cid);
3982
3983/**
3984 * @brief qed_calc_task_ctx_validation - Calcualte validation byte for task
3985 *      context.
3986 *
3987 * @param p_ctx_mem - pointer to context memory.
3988 * @param ctx_size - context size.
3989 * @param ctx_type - context type.
3990 * @param tid - context tid.
3991 */
3992void qed_calc_task_ctx_validation(void *p_ctx_mem,
3993                                  u16 ctx_size, u8 ctx_type, u32 tid);
3994
3995/**
3996 * @brief qed_memset_session_ctx - Memset session context to 0 while
3997 *      preserving validation bytes.
3998 *
3999 * @param p_hwfn -
4000 * @param p_ctx_mem - pointer to context memory.
4001 * @param ctx_size - size to initialzie.
4002 * @param ctx_type - context type.
4003 */
4004void qed_memset_session_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4005
4006/**
4007 * @brief qed_memset_task_ctx - Memset task context to 0 while preserving
4008 *      validation bytes.
4009 *
4010 * @param p_ctx_mem - pointer to context memory.
4011 * @param ctx_size - size to initialzie.
4012 * @param ctx_type - context type.
4013 */
4014void qed_memset_task_ctx(void *p_ctx_mem, u32 ctx_size, u8 ctx_type);
4015
4016#define NUM_STORMS 6
4017
4018/**
4019 * @brief qed_set_rdma_error_level - Sets the RDMA assert level.
4020 *                                   If the severity of the error will be
4021 *                                   above the level, the FW will assert.
4022 * @param p_hwfn - HW device data
4023 * @param p_ptt - ptt window used for writing the registers
4024 * @param assert_level - An array of assert levels for each storm.
4025 *
4026 */
4027void qed_set_rdma_error_level(struct qed_hwfn *p_hwfn,
4028                              struct qed_ptt *p_ptt,
4029                              u8 assert_level[NUM_STORMS]);
4030/**
4031 * @brief qed_fw_overlay_mem_alloc - Allocates and fills the FW overlay memory.
4032 *
4033 * @param p_hwfn - HW device data
4034 * @param fw_overlay_in_buf - the input FW overlay buffer.
4035 * @param buf_size - the size of the input FW overlay buffer in bytes.
4036 *                   must be aligned to dwords.
4037 * @param fw_overlay_out_mem - OUT: a pointer to the allocated overlays memory.
4038 *
4039 * @return a pointer to the allocated overlays memory,
4040 * or NULL in case of failures.
4041 */
4042struct phys_mem_desc *
4043qed_fw_overlay_mem_alloc(struct qed_hwfn *p_hwfn,
4044                         const u32 * const fw_overlay_in_buf,
4045                         u32 buf_size_in_bytes);
4046
4047/**
4048 * @brief qed_fw_overlay_init_ram - Initializes the FW overlay RAM.
4049 *
4050 * @param p_hwfn - HW device data.
4051 * @param p_ptt - ptt window used for writing the registers.
4052 * @param fw_overlay_mem - the allocated FW overlay memory.
4053 */
4054void qed_fw_overlay_init_ram(struct qed_hwfn *p_hwfn,
4055                             struct qed_ptt *p_ptt,
4056                             struct phys_mem_desc *fw_overlay_mem);
4057
4058/**
4059 * @brief qed_fw_overlay_mem_free - Frees the FW overlay memory.
4060 *
4061 * @param p_hwfn - HW device data.
4062 * @param fw_overlay_mem - the allocated FW overlay memory to free.
4063 */
4064void qed_fw_overlay_mem_free(struct qed_hwfn *p_hwfn,
4065                             struct phys_mem_desc *fw_overlay_mem);
4066
4067/* Ystorm flow control mode. Use enum fw_flow_ctrl_mode */
4068#define YSTORM_FLOW_CONTROL_MODE_OFFSET                 (IRO[0].base)
4069#define YSTORM_FLOW_CONTROL_MODE_SIZE                   (IRO[0].size)
4070
4071/* Tstorm port statistics */
4072#define TSTORM_PORT_STAT_OFFSET(port_id) \
4073        (IRO[1].base + ((port_id) * IRO[1].m1))
4074#define TSTORM_PORT_STAT_SIZE                           (IRO[1].size)
4075
4076/* Tstorm ll2 port statistics */
4077#define TSTORM_LL2_PORT_STAT_OFFSET(port_id) \
4078        (IRO[2].base + ((port_id) * IRO[2].m1))
4079#define TSTORM_LL2_PORT_STAT_SIZE                       (IRO[2].size)
4080
4081/* Ustorm VF-PF Channel ready flag */
4082#define USTORM_VF_PF_CHANNEL_READY_OFFSET(vf_id) \
4083        (IRO[3].base + ((vf_id) * IRO[3].m1))
4084#define USTORM_VF_PF_CHANNEL_READY_SIZE                 (IRO[3].size)
4085
4086/* Ustorm Final flr cleanup ack */
4087#define USTORM_FLR_FINAL_ACK_OFFSET(pf_id) \
4088        (IRO[4].base + ((pf_id) * IRO[4].m1))
4089#define USTORM_FLR_FINAL_ACK_SIZE                       (IRO[4].size)
4090
4091/* Ustorm Event ring consumer */
4092#define USTORM_EQE_CONS_OFFSET(pf_id) \
4093        (IRO[5].base + ((pf_id) * IRO[5].m1))
4094#define USTORM_EQE_CONS_SIZE                            (IRO[5].size)
4095
4096/* Ustorm eth queue zone */
4097#define USTORM_ETH_QUEUE_ZONE_OFFSET(queue_zone_id) \
4098        (IRO[6].base + ((queue_zone_id) * IRO[6].m1))
4099#define USTORM_ETH_QUEUE_ZONE_SIZE                      (IRO[6].size)
4100
4101/* Ustorm Common Queue ring consumer */
4102#define USTORM_COMMON_QUEUE_CONS_OFFSET(queue_zone_id) \
4103        (IRO[7].base + ((queue_zone_id) * IRO[7].m1))
4104#define USTORM_COMMON_QUEUE_CONS_SIZE                   (IRO[7].size)
4105
4106/* Xstorm common PQ info */
4107#define XSTORM_PQ_INFO_OFFSET(pq_id) \
4108        (IRO[8].base + ((pq_id) * IRO[8].m1))
4109#define XSTORM_PQ_INFO_SIZE                             (IRO[8].size)
4110
4111/* Xstorm Integration Test Data */
4112#define XSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[9].base)
4113#define XSTORM_INTEG_TEST_DATA_SIZE                     (IRO[9].size)
4114
4115/* Ystorm Integration Test Data */
4116#define YSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[10].base)
4117#define YSTORM_INTEG_TEST_DATA_SIZE                     (IRO[10].size)
4118
4119/* Pstorm Integration Test Data */
4120#define PSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[11].base)
4121#define PSTORM_INTEG_TEST_DATA_SIZE                     (IRO[11].size)
4122
4123/* Tstorm Integration Test Data */
4124#define TSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[12].base)
4125#define TSTORM_INTEG_TEST_DATA_SIZE                     (IRO[12].size)
4126
4127/* Mstorm Integration Test Data */
4128#define MSTORM_INTEG_TEST_DATA_OFFSET                   (IRO[13].base)
4129#define MSTORM_INTEG_TEST_DATA_SIZE                     (IRO[13].size)
4130
4131/* Ustorm Integration Test Data */
4132#define USTORM_INTEG_TEST_DATA_OFFSET                   (IRO[14].base)
4133#define USTORM_INTEG_TEST_DATA_SIZE                     (IRO[14].size)
4134
4135/* Xstorm overlay buffer host address */
4136#define XSTORM_OVERLAY_BUF_ADDR_OFFSET                  (IRO[15].base)
4137#define XSTORM_OVERLAY_BUF_ADDR_SIZE                    (IRO[15].size)
4138
4139/* Ystorm overlay buffer host address */
4140#define YSTORM_OVERLAY_BUF_ADDR_OFFSET                  (IRO[16].base)
4141#define YSTORM_OVERLAY_BUF_ADDR_SIZE                    (IRO[16].size)
4142
4143/* Pstorm overlay buffer host address */
4144#define PSTORM_OVERLAY_BUF_ADDR_OFFSET                  (IRO[17].base)
4145#define PSTORM_OVERLAY_BUF_ADDR_SIZE                    (IRO[17].size)
4146
4147/* Tstorm overlay buffer host address */
4148#define TSTORM_OVERLAY_BUF_ADDR_OFFSET                  (IRO[18].base)
4149#define TSTORM_OVERLAY_BUF_ADDR_SIZE                    (IRO[18].size)
4150
4151/* Mstorm overlay buffer host address */
4152#define MSTORM_OVERLAY_BUF_ADDR_OFFSET                  (IRO[19].base)
4153#define MSTORM_OVERLAY_BUF_ADDR_SIZE                    (IRO[19].size)
4154
4155/* Ustorm overlay buffer host address */
4156#define USTORM_OVERLAY_BUF_ADDR_OFFSET                  (IRO[20].base)
4157#define USTORM_OVERLAY_BUF_ADDR_SIZE                    (IRO[20].size)
4158
4159/* Tstorm producers */
4160#define TSTORM_LL2_RX_PRODS_OFFSET(core_rx_queue_id) \
4161        (IRO[21].base + ((core_rx_queue_id) * IRO[21].m1))
4162#define TSTORM_LL2_RX_PRODS_SIZE                        (IRO[21].size)
4163
4164/* Tstorm LightL2 queue statistics */
4165#define CORE_LL2_TSTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4166        (IRO[22].base + ((core_rx_queue_id) * IRO[22].m1))
4167#define CORE_LL2_TSTORM_PER_QUEUE_STAT_SIZE             (IRO[22].size)
4168
4169/* Ustorm LiteL2 queue statistics */
4170#define CORE_LL2_USTORM_PER_QUEUE_STAT_OFFSET(core_rx_queue_id) \
4171        (IRO[23].base + ((core_rx_queue_id) * IRO[23].m1))
4172#define CORE_LL2_USTORM_PER_QUEUE_STAT_SIZE             (IRO[23].size)
4173
4174/* Pstorm LiteL2 queue statistics */
4175#define CORE_LL2_PSTORM_PER_QUEUE_STAT_OFFSET(core_tx_stats_id) \
4176        (IRO[24].base + ((core_tx_stats_id) * IRO[24].m1))
4177#define CORE_LL2_PSTORM_PER_QUEUE_STAT_SIZE             (IRO[24].size)
4178
4179/* Mstorm queue statistics */
4180#define MSTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4181        (IRO[25].base + ((stat_counter_id) * IRO[25].m1))
4182#define MSTORM_QUEUE_STAT_SIZE                          (IRO[25].size)
4183
4184/* TPA agregation timeout in us resolution (on ASIC) */
4185#define MSTORM_TPA_TIMEOUT_US_OFFSET                    (IRO[26].base)
4186#define MSTORM_TPA_TIMEOUT_US_SIZE                      (IRO[26].size)
4187
4188/* Mstorm ETH VF queues producers offset in RAM. Used in default VF zone size
4189 * mode
4190 */
4191#define MSTORM_ETH_VF_PRODS_OFFSET(vf_id, vf_queue_id) \
4192        (IRO[27].base + ((vf_id) * IRO[27].m1) + ((vf_queue_id) * IRO[27].m2))
4193#define MSTORM_ETH_VF_PRODS_SIZE                        (IRO[27].size)
4194
4195/* Mstorm ETH PF queues producers */
4196#define MSTORM_ETH_PF_PRODS_OFFSET(queue_id) \
4197        (IRO[28].base + ((queue_id) * IRO[28].m1))
4198#define MSTORM_ETH_PF_PRODS_SIZE                        (IRO[28].size)
4199
4200/* Mstorm pf statistics */
4201#define MSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4202        (IRO[29].base + ((pf_id) * IRO[29].m1))
4203#define MSTORM_ETH_PF_STAT_SIZE                         (IRO[29].size)
4204
4205/* Ustorm queue statistics */
4206#define USTORM_QUEUE_STAT_OFFSET(stat_counter_id) \
4207        (IRO[30].base + ((stat_counter_id) * IRO[30].m1))
4208#define USTORM_QUEUE_STAT_SIZE                          (IRO[30].size)
4209
4210/* Ustorm pf statistics */
4211#define USTORM_ETH_PF_STAT_OFFSET(pf_id) \
4212        (IRO[31].base + ((pf_id) * IRO[31].m1))
4213#define USTORM_ETH_PF_STAT_SIZE                         (IRO[31].size)
4214
4215/* Pstorm queue statistics */
4216#define PSTORM_QUEUE_STAT_OFFSET(stat_counter_id)       \
4217        (IRO[32].base + ((stat_counter_id) * IRO[32].m1))
4218#define PSTORM_QUEUE_STAT_SIZE                          (IRO[32].size)
4219
4220/* Pstorm pf statistics */
4221#define PSTORM_ETH_PF_STAT_OFFSET(pf_id) \
4222        (IRO[33].base + ((pf_id) * IRO[33].m1))
4223#define PSTORM_ETH_PF_STAT_SIZE                         (IRO[33].size)
4224
4225/* Control frame's EthType configuration for TX control frame security */
4226#define PSTORM_CTL_FRAME_ETHTYPE_OFFSET(eth_type_id)    \
4227        (IRO[34].base + ((eth_type_id) * IRO[34].m1))
4228#define PSTORM_CTL_FRAME_ETHTYPE_SIZE                   (IRO[34].size)
4229
4230/* Tstorm last parser message */
4231#define TSTORM_ETH_PRS_INPUT_OFFSET                     (IRO[35].base)
4232#define TSTORM_ETH_PRS_INPUT_SIZE                       (IRO[35].size)
4233
4234/* Tstorm Eth limit Rx rate */