// SPDX-License-Identifier: GPL-2.0
/* Copyright(c) 2017 - 2019 Pensando Systems, Inc */

#include <linux/ethtool.h>
#include <linux/printk.h>
#include <linux/dynamic_debug.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/if_vlan.h>
#include <linux/rtnetlink.h>
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/cpumask.h>

#include "ionic.h"
#include "ionic_bus.h"
#include "ionic_lif.h"
#include "ionic_txrx.h"
#include "ionic_ethtool.h"
#include "ionic_debugfs.h"

/* queuetype support level */
static const u8 ionic_qtype_versions[IONIC_QTYPE_MAX] = {
        [IONIC_QTYPE_ADMINQ]  = 0,   /* 0 = Base version with CQ support */
        [IONIC_QTYPE_NOTIFYQ] = 0,   /* 0 = Base version */
        [IONIC_QTYPE_RXQ]     = 0,   /* 0 = Base version with CQ+SG support */
        [IONIC_QTYPE_TXQ]     = 1,   /* 0 = Base version with CQ+SG support
                                      * 1 =   ... with Tx SG version 1
                                      */
};

static void ionic_lif_rx_mode(struct ionic_lif *lif);
static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr);
static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr);
static void ionic_link_status_check(struct ionic_lif *lif);
static void ionic_lif_handle_fw_down(struct ionic_lif *lif);
static void ionic_lif_handle_fw_up(struct ionic_lif *lif);
static void ionic_lif_set_netdev_info(struct ionic_lif *lif);

static void ionic_txrx_deinit(struct ionic_lif *lif);
static int ionic_txrx_init(struct ionic_lif *lif);
static int ionic_start_queues(struct ionic_lif *lif);
static void ionic_stop_queues(struct ionic_lif *lif);
static void ionic_lif_queue_identify(struct ionic_lif *lif);

static void ionic_dim_work(struct work_struct *work)
{
        struct dim *dim = container_of(work, struct dim, work);
        struct dim_cq_moder cur_moder;
        struct ionic_qcq *qcq;
        u32 new_coal;

        cur_moder = net_dim_get_rx_moderation(dim->mode, dim->profile_ix);
        qcq = container_of(dim, struct ionic_qcq, dim);
        new_coal = ionic_coal_usec_to_hw(qcq->q.lif->ionic, cur_moder.usec);
        new_coal = new_coal ? new_coal : 1;

        if (qcq->intr.dim_coal_hw != new_coal) {
                unsigned int qi = qcq->cq.bound_q->index;
                struct ionic_lif *lif = qcq->q.lif;

                qcq->intr.dim_coal_hw = new_coal;

                ionic_intr_coal_init(lif->ionic->idev.intr_ctrl,
                                     lif->rxqcqs[qi]->intr.index,
                                     qcq->intr.dim_coal_hw);
        }

        dim->state = DIM_START_MEASURE;
}

static void ionic_lif_deferred_work(struct work_struct *work)
{
        struct ionic_lif *lif = container_of(work, struct ionic_lif, deferred.work);
        struct ionic_deferred *def = &lif->deferred;
        struct ionic_deferred_work *w = NULL;

        do {
                spin_lock_bh(&def->lock);
                if (!list_empty(&def->list)) {
                        w = list_first_entry(&def->list,
                                             struct ionic_deferred_work, list);
                        list_del(&w->list);
                }
                spin_unlock_bh(&def->lock);

                if (!w)
                        break;

                switch (w->type) {
                case IONIC_DW_TYPE_RX_MODE:
                        ionic_lif_rx_mode(lif);
                        break;
                case IONIC_DW_TYPE_RX_ADDR_ADD:
                        ionic_lif_addr_add(lif, w->addr);
                        break;
                case IONIC_DW_TYPE_RX_ADDR_DEL:
                        ionic_lif_addr_del(lif, w->addr);
                        break;
                case IONIC_DW_TYPE_LINK_STATUS:
                        ionic_link_status_check(lif);
                        break;
                case IONIC_DW_TYPE_LIF_RESET:
                        if (w->fw_status)
                                ionic_lif_handle_fw_up(lif);
                        else
                                ionic_lif_handle_fw_down(lif);
                        break;
                default:
                        break;
                }
                kfree(w);
                w = NULL;
        } while (true);
}

void ionic_lif_deferred_enqueue(struct ionic_deferred *def,
                                struct ionic_deferred_work *work)
{
        spin_lock_bh(&def->lock);
        list_add_tail(&work->list, &def->list);
        spin_unlock_bh(&def->lock);
        schedule_work(&def->work);
}

static void ionic_link_status_check(struct ionic_lif *lif)
{
        struct net_device *netdev = lif->netdev;
        u16 link_status;
        bool link_up;

        if (!test_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
                return;

        /* Don't put carrier back up if we're in a broken state */
        if (test_bit(IONIC_LIF_F_BROKEN, lif->state)) {
                clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
                return;
        }

        link_status = le16_to_cpu(lif->info->status.link_status);
        link_up = link_status == IONIC_PORT_OPER_STATUS_UP;

        if (link_up) {
                int err = 0;

                if (netdev->flags & IFF_UP && netif_running(netdev)) {
                        mutex_lock(&lif->queue_lock);
                        err = ionic_start_queues(lif);
                        if (err && err != -EBUSY) {
                                netdev_err(lif->netdev,
                                           "Failed to start queues: %d\n", err);
                                set_bit(IONIC_LIF_F_BROKEN, lif->state);
                                netif_carrier_off(lif->netdev);
                        }
                        mutex_unlock(&lif->queue_lock);
                }

                if (!err && !netif_carrier_ok(netdev)) {
                        ionic_port_identify(lif->ionic);
                        netdev_info(netdev, "Link up - %d Gbps\n",
                                    le32_to_cpu(lif->info->status.link_speed) / 1000);
                        netif_carrier_on(netdev);
                }
        } else {
                if (netif_carrier_ok(netdev)) {
                        netdev_info(netdev, "Link down\n");
                        netif_carrier_off(netdev);
                }

                if (netdev->flags & IFF_UP && netif_running(netdev)) {
                        mutex_lock(&lif->queue_lock);
                        ionic_stop_queues(lif);
                        mutex_unlock(&lif->queue_lock);
                }
        }

        clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
}

void ionic_link_status_check_request(struct ionic_lif *lif, bool can_sleep)
{
        struct ionic_deferred_work *work;

        /* we only need one request outstanding at a time */
        if (test_and_set_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state))
                return;

        if (!can_sleep) {
                work = kzalloc(sizeof(*work), GFP_ATOMIC);
                if (!work) {
                        clear_bit(IONIC_LIF_F_LINK_CHECK_REQUESTED, lif->state);
                        return;
                }

                work->type = IONIC_DW_TYPE_LINK_STATUS;
                ionic_lif_deferred_enqueue(&lif->deferred, work);
        } else {
                ionic_link_status_check(lif);
        }
}

static irqreturn_t ionic_isr(int irq, void *data)
{
        struct napi_struct *napi = data;

        napi_schedule_irqoff(napi);

        return IRQ_HANDLED;
}

static int ionic_request_irq(struct ionic_lif *lif, struct ionic_qcq *qcq)
{
        struct ionic_intr_info *intr = &qcq->intr;
        struct device *dev = lif->ionic->dev;
        struct ionic_queue *q = &qcq->q;
        const char *name;

        if (lif->registered)
                name = lif->netdev->name;
        else
                name = dev_name(dev);

        snprintf(intr->name, sizeof(intr->name),
                 "%s-%s-%s", IONIC_DRV_NAME, name, q->name);

        return devm_request_irq(dev, intr->vector, ionic_isr,
                                0, intr->name, &qcq->napi);
}

static int ionic_intr_alloc(struct ionic_lif *lif, struct ionic_intr_info *intr)
{
        struct ionic *ionic = lif->ionic;
        int index;

        index = find_first_zero_bit(ionic->intrs, ionic->nintrs);
        if (index == ionic->nintrs) {
                netdev_warn(lif->netdev, "%s: no intr, index=%d nintrs=%d\n",
                            __func__, index, ionic->nintrs);
                return -ENOSPC;
        }

        set_bit(index, ionic->intrs);
        ionic_intr_init(&ionic->idev, intr, index);

        return 0;
}

static void ionic_intr_free(struct ionic *ionic, int index)
{
        if (index != IONIC_INTR_INDEX_NOT_ASSIGNED && index < ionic->nintrs)
                clear_bit(index, ionic->intrs);
}

static int ionic_qcq_enable(struct ionic_qcq *qcq)
{
        struct ionic_queue *q = &qcq->q;
        struct ionic_lif *lif = q->lif;
        struct ionic_dev *idev;
        struct device *dev;

        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.q_control = {
                        .opcode = IONIC_CMD_Q_CONTROL,
                        .lif_index = cpu_to_le16(lif->index),
                        .type = q->type,
                        .index = cpu_to_le32(q->index),
                        .oper = IONIC_Q_ENABLE,
                },
        };

        idev = &lif->ionic->idev;
        dev = lif->ionic->dev;

        dev_dbg(dev, "q_enable.index %d q_enable.qtype %d\n",
                ctx.cmd.q_control.index, ctx.cmd.q_control.type);

        if (qcq->flags & IONIC_QCQ_F_INTR) {
                irq_set_affinity_hint(qcq->intr.vector,
                                      &qcq->intr.affinity_mask);
                napi_enable(&qcq->napi);
                ionic_intr_clean(idev->intr_ctrl, qcq->intr.index);
                ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
                                IONIC_INTR_MASK_CLEAR);
        }

        return ionic_adminq_post_wait(lif, &ctx);
}

static int ionic_qcq_disable(struct ionic_qcq *qcq, bool send_to_hw)
{
        struct ionic_queue *q;
        struct ionic_lif *lif;
        int err = 0;

        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.q_control = {
                        .opcode = IONIC_CMD_Q_CONTROL,
                        .oper = IONIC_Q_DISABLE,
                },
        };

        if (!qcq)
                return -ENXIO;

        q = &qcq->q;
        lif = q->lif;

        if (qcq->flags & IONIC_QCQ_F_INTR) {
                struct ionic_dev *idev = &lif->ionic->idev;

                cancel_work_sync(&qcq->dim.work);
                ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
                                IONIC_INTR_MASK_SET);
                synchronize_irq(qcq->intr.vector);
                irq_set_affinity_hint(qcq->intr.vector, NULL);
                napi_disable(&qcq->napi);
        }

        if (send_to_hw) {
                ctx.cmd.q_control.lif_index = cpu_to_le16(lif->index);
                ctx.cmd.q_control.type = q->type;
                ctx.cmd.q_control.index = cpu_to_le32(q->index);
                dev_dbg(lif->ionic->dev, "q_disable.index %d q_disable.qtype %d\n",
                        ctx.cmd.q_control.index, ctx.cmd.q_control.type);

                err = ionic_adminq_post_wait(lif, &ctx);
        }

        return err;
}

static void ionic_lif_qcq_deinit(struct ionic_lif *lif, struct ionic_qcq *qcq)
{
        struct ionic_dev *idev = &lif->ionic->idev;

        if (!qcq)
                return;

        if (!(qcq->flags & IONIC_QCQ_F_INITED))
                return;

        if (qcq->flags & IONIC_QCQ_F_INTR) {
                ionic_intr_mask(idev->intr_ctrl, qcq->intr.index,
                                IONIC_INTR_MASK_SET);
                netif_napi_del(&qcq->napi);
        }

        qcq->flags &= ~IONIC_QCQ_F_INITED;
}

static void ionic_qcq_intr_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
{
        if (!(qcq->flags & IONIC_QCQ_F_INTR) || qcq->intr.vector == 0)
                return;

        irq_set_affinity_hint(qcq->intr.vector, NULL);
        devm_free_irq(lif->ionic->dev, qcq->intr.vector, &qcq->napi);
        qcq->intr.vector = 0;
        ionic_intr_free(lif->ionic, qcq->intr.index);
        qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
}

static void ionic_qcq_free(struct ionic_lif *lif, struct ionic_qcq *qcq)
{
        struct device *dev = lif->ionic->dev;

        if (!qcq)
                return;

        ionic_debugfs_del_qcq(qcq);

        if (qcq->q_base) {
                dma_free_coherent(dev, qcq->q_size, qcq->q_base, qcq->q_base_pa);
                qcq->q_base = NULL;
                qcq->q_base_pa = 0;
        }

        if (qcq->cq_base) {
                dma_free_coherent(dev, qcq->cq_size, qcq->cq_base, qcq->cq_base_pa);
                qcq->cq_base = NULL;
                qcq->cq_base_pa = 0;
        }

        if (qcq->sg_base) {
                dma_free_coherent(dev, qcq->sg_size, qcq->sg_base, qcq->sg_base_pa);
                qcq->sg_base = NULL;
                qcq->sg_base_pa = 0;
        }

        ionic_qcq_intr_free(lif, qcq);

        if (qcq->cq.info) {
                devm_kfree(dev, qcq->cq.info);
                qcq->cq.info = NULL;
        }
        if (qcq->q.info) {
                devm_kfree(dev, qcq->q.info);
                qcq->q.info = NULL;
        }
}

static void ionic_qcqs_free(struct ionic_lif *lif)
{
        struct device *dev = lif->ionic->dev;
        struct ionic_qcq *adminqcq;
        unsigned long irqflags;

        if (lif->notifyqcq) {
                ionic_qcq_free(lif, lif->notifyqcq);
                devm_kfree(dev, lif->notifyqcq);
                lif->notifyqcq = NULL;
        }

        if (lif->adminqcq) {
                spin_lock_irqsave(&lif->adminq_lock, irqflags);
                adminqcq = READ_ONCE(lif->adminqcq);
                lif->adminqcq = NULL;
                spin_unlock_irqrestore(&lif->adminq_lock, irqflags);
                if (adminqcq) {
                        ionic_qcq_free(lif, adminqcq);
                        devm_kfree(dev, adminqcq);
                }
        }

        if (lif->rxqcqs) {
                devm_kfree(dev, lif->rxqstats);
                lif->rxqstats = NULL;
                devm_kfree(dev, lif->rxqcqs);
                lif->rxqcqs = NULL;
        }

        if (lif->txqcqs) {
                devm_kfree(dev, lif->txqstats);
                lif->txqstats = NULL;
                devm_kfree(dev, lif->txqcqs);
                lif->txqcqs = NULL;
        }
}

static void ionic_link_qcq_interrupts(struct ionic_qcq *src_qcq,
                                      struct ionic_qcq *n_qcq)
{
        if (WARN_ON(n_qcq->flags & IONIC_QCQ_F_INTR)) {
                ionic_intr_free(n_qcq->cq.lif->ionic, n_qcq->intr.index);
                n_qcq->flags &= ~IONIC_QCQ_F_INTR;
        }

        n_qcq->intr.vector = src_qcq->intr.vector;
        n_qcq->intr.index = src_qcq->intr.index;
}

static int ionic_alloc_qcq_interrupt(struct ionic_lif *lif, struct ionic_qcq *qcq)
{
        int err;

        if (!(qcq->flags & IONIC_QCQ_F_INTR)) {
                qcq->intr.index = IONIC_INTR_INDEX_NOT_ASSIGNED;
                return 0;
        }

        err = ionic_intr_alloc(lif, &qcq->intr);
        if (err) {
                netdev_warn(lif->netdev, "no intr for %s: %d\n",
                            qcq->q.name, err);
                goto err_out;
        }

        err = ionic_bus_get_irq(lif->ionic, qcq->intr.index);
        if (err < 0) {
                netdev_warn(lif->netdev, "no vector for %s: %d\n",
                            qcq->q.name, err);
                goto err_out_free_intr;
        }
        qcq->intr.vector = err;
        ionic_intr_mask_assert(lif->ionic->idev.intr_ctrl, qcq->intr.index,
                               IONIC_INTR_MASK_SET);

        err = ionic_request_irq(lif, qcq);
        if (err) {
                netdev_warn(lif->netdev, "irq request failed %d\n", err);
                goto err_out_free_intr;
        }

        /* try to get the irq on the local numa node first */
        qcq->intr.cpu = cpumask_local_spread(qcq->intr.index,
                                             dev_to_node(lif->ionic->dev));
        if (qcq->intr.cpu != -1)
                cpumask_set_cpu(qcq->intr.cpu, &qcq->intr.affinity_mask);

        netdev_dbg(lif->netdev, "%s: Interrupt index %d\n", qcq->q.name, qcq->intr.index);
        return 0;

err_out_free_intr:
        ionic_intr_free(lif->ionic, qcq->intr.index);
err_out:
        return err;
}

static int ionic_qcq_alloc(struct ionic_lif *lif, unsigned int type,
                           unsigned int index,
                           const char *name, unsigned int flags,
                           unsigned int num_descs, unsigned int desc_size,
                           unsigned int cq_desc_size,
                           unsigned int sg_desc_size,
                           unsigned int pid, struct ionic_qcq **qcq)
{
        struct ionic_dev *idev = &lif->ionic->idev;
        struct device *dev = lif->ionic->dev;
        void *q_base, *cq_base, *sg_base;
        dma_addr_t cq_base_pa = 0;
        dma_addr_t sg_base_pa = 0;
        dma_addr_t q_base_pa = 0;
        struct ionic_qcq *new;
        int err;

        *qcq = NULL;

        new = devm_kzalloc(dev, sizeof(*new), GFP_KERNEL);
        if (!new) {
                netdev_err(lif->netdev, "Cannot allocate queue structure\n");
                err = -ENOMEM;
                goto err_out;
        }

        new->q.dev = dev;
        new->flags = flags;

        new->q.info = devm_kcalloc(dev, num_descs, sizeof(*new->q.info),
                                   GFP_KERNEL);
        if (!new->q.info) {
                netdev_err(lif->netdev, "Cannot allocate queue info\n");
                err = -ENOMEM;
                goto err_out_free_qcq;
        }

        new->q.type = type;
        new->q.max_sg_elems = lif->qtype_info[type].max_sg_elems;

        err = ionic_q_init(lif, idev, &new->q, index, name, num_descs,
                           desc_size, sg_desc_size, pid);
        if (err) {
                netdev_err(lif->netdev, "Cannot initialize queue\n");
                goto err_out_free_q_info;
        }

        err = ionic_alloc_qcq_interrupt(lif, new);
        if (err)
                goto err_out;

        new->cq.info = devm_kcalloc(dev, num_descs, sizeof(*new->cq.info),
                                    GFP_KERNEL);
        if (!new->cq.info) {
                netdev_err(lif->netdev, "Cannot allocate completion queue info\n");
                err = -ENOMEM;
                goto err_out_free_irq;
        }

        err = ionic_cq_init(lif, &new->cq, &new->intr, num_descs, cq_desc_size);
        if (err) {
                netdev_err(lif->netdev, "Cannot initialize completion queue\n");
                goto err_out_free_cq_info;
        }

        if (flags & IONIC_QCQ_F_NOTIFYQ) {
                int q_size, cq_size;

                /* q & cq need to be contiguous in case of notifyq */
                q_size = ALIGN(num_descs * desc_size, PAGE_SIZE);
                cq_size = ALIGN(num_descs * cq_desc_size, PAGE_SIZE);

                new->q_size = PAGE_SIZE + q_size + cq_size;
                new->q_base = dma_alloc_coherent(dev, new->q_size,
                                                 &new->q_base_pa, GFP_KERNEL);
                if (!new->q_base) {
                        netdev_err(lif->netdev, "Cannot allocate qcq DMA memory\n");
                        err = -ENOMEM;
                        goto err_out_free_cq_info;
                }
                q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
                q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
                ionic_q_map(&new->q, q_base, q_base_pa);

                cq_base = PTR_ALIGN(q_base + q_size, PAGE_SIZE);
                cq_base_pa = ALIGN(new->q_base_pa + q_size, PAGE_SIZE);
                ionic_cq_map(&new->cq, cq_base, cq_base_pa);
                ionic_cq_bind(&new->cq, &new->q);
        } else {
                new->q_size = PAGE_SIZE + (num_descs * desc_size);
                new->q_base = dma_alloc_coherent(dev, new->q_size, &new->q_base_pa,
                                                 GFP_KERNEL);
                if (!new->q_base) {
                        netdev_err(lif->netdev, "Cannot allocate queue DMA memory\n");
                        err = -ENOMEM;
                        goto err_out_free_cq_info;
                }
                q_base = PTR_ALIGN(new->q_base, PAGE_SIZE);
                q_base_pa = ALIGN(new->q_base_pa, PAGE_SIZE);
                ionic_q_map(&new->q, q_base, q_base_pa);

                new->cq_size = PAGE_SIZE + (num_descs * cq_desc_size);
                new->cq_base = dma_alloc_coherent(dev, new->cq_size, &new->cq_base_pa,
                                                  GFP_KERNEL);
                if (!new->cq_base) {
                        netdev_err(lif->netdev, "Cannot allocate cq DMA memory\n");
                        err = -ENOMEM;
                        goto err_out_free_q;
                }
                cq_base = PTR_ALIGN(new->cq_base, PAGE_SIZE);
                cq_base_pa = ALIGN(new->cq_base_pa, PAGE_SIZE);
                ionic_cq_map(&new->cq, cq_base, cq_base_pa);
                ionic_cq_bind(&new->cq, &new->q);
        }

        if (flags & IONIC_QCQ_F_SG) {
                new->sg_size = PAGE_SIZE + (num_descs * sg_desc_size);
                new->sg_base = dma_alloc_coherent(dev, new->sg_size, &new->sg_base_pa,
                                                  GFP_KERNEL);
                if (!new->sg_base) {
                        netdev_err(lif->netdev, "Cannot allocate sg DMA memory\n");
                        err = -ENOMEM;
                        goto err_out_free_cq;
                }
                sg_base = PTR_ALIGN(new->sg_base, PAGE_SIZE);
                sg_base_pa = ALIGN(new->sg_base_pa, PAGE_SIZE);
                ionic_q_sg_map(&new->q, sg_base, sg_base_pa);
        }

        INIT_WORK(&new->dim.work, ionic_dim_work);
        new->dim.mode = DIM_CQ_PERIOD_MODE_START_FROM_EQE;

        *qcq = new;

        return 0;

err_out_free_cq:
        dma_free_coherent(dev, new->cq_size, new->cq_base, new->cq_base_pa);
err_out_free_q:
        dma_free_coherent(dev, new->q_size, new->q_base, new->q_base_pa);
err_out_free_cq_info:
        devm_kfree(dev, new->cq.info);
err_out_free_irq:
        if (flags & IONIC_QCQ_F_INTR) {
                devm_free_irq(dev, new->intr.vector, &new->napi);
                ionic_intr_free(lif->ionic, new->intr.index);
        }
err_out_free_q_info:
        devm_kfree(dev, new->q.info);
err_out_free_qcq:
        devm_kfree(dev, new);
err_out:
        dev_err(dev, "qcq alloc of %s%d failed %d\n", name, index, err);
        return err;
}

static int ionic_qcqs_alloc(struct ionic_lif *lif)
{
        struct device *dev = lif->ionic->dev;
        unsigned int flags;
        int err;

        flags = IONIC_QCQ_F_INTR;
        err = ionic_qcq_alloc(lif, IONIC_QTYPE_ADMINQ, 0, "admin", flags,
                              IONIC_ADMINQ_LENGTH,
                              sizeof(struct ionic_admin_cmd),
                              sizeof(struct ionic_admin_comp),
                              0, lif->kern_pid, &lif->adminqcq);
        if (err)
                return err;
        ionic_debugfs_add_qcq(lif, lif->adminqcq);

        if (lif->ionic->nnqs_per_lif) {
                flags = IONIC_QCQ_F_NOTIFYQ;
                err = ionic_qcq_alloc(lif, IONIC_QTYPE_NOTIFYQ, 0, "notifyq",
                                      flags, IONIC_NOTIFYQ_LENGTH,
                                      sizeof(struct ionic_notifyq_cmd),
                                      sizeof(union ionic_notifyq_comp),
                                      0, lif->kern_pid, &lif->notifyqcq);
                if (err)
                        goto err_out;
                ionic_debugfs_add_qcq(lif, lif->notifyqcq);

                /* Let the notifyq ride on the adminq interrupt */
                ionic_link_qcq_interrupts(lif->adminqcq, lif->notifyqcq);
        }

        err = -ENOMEM;
        lif->txqcqs = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif,
                                   sizeof(*lif->txqcqs), GFP_KERNEL);
        if (!lif->txqcqs)
                goto err_out;
        lif->rxqcqs = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif,
                                   sizeof(*lif->rxqcqs), GFP_KERNEL);
        if (!lif->rxqcqs)
                goto err_out;

        lif->txqstats = devm_kcalloc(dev, lif->ionic->ntxqs_per_lif + 1,
                                     sizeof(*lif->txqstats), GFP_KERNEL);
        if (!lif->txqstats)
                goto err_out;
        lif->rxqstats = devm_kcalloc(dev, lif->ionic->nrxqs_per_lif + 1,
                                     sizeof(*lif->rxqstats), GFP_KERNEL);
        if (!lif->rxqstats)
                goto err_out;

        return 0;

err_out:
        ionic_qcqs_free(lif);
        return err;
}

static void ionic_qcq_sanitize(struct ionic_qcq *qcq)
{
        qcq->q.tail_idx = 0;
        qcq->q.head_idx = 0;
        qcq->cq.tail_idx = 0;
        qcq->cq.done_color = 1;
        memset(qcq->q_base, 0, qcq->q_size);
        memset(qcq->cq_base, 0, qcq->cq_size);
        memset(qcq->sg_base, 0, qcq->sg_size);
}

static int ionic_lif_txq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
{
        struct device *dev = lif->ionic->dev;
        struct ionic_queue *q = &qcq->q;
        struct ionic_cq *cq = &qcq->cq;
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.q_init = {
                        .opcode = IONIC_CMD_Q_INIT,
                        .lif_index = cpu_to_le16(lif->index),
                        .type = q->type,
                        .ver = lif->qtype_info[q->type].version,
                        .index = cpu_to_le32(q->index),
                        .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
                                             IONIC_QINIT_F_SG),
                        .pid = cpu_to_le16(q->pid),
                        .ring_size = ilog2(q->num_descs),
                        .ring_base = cpu_to_le64(q->base_pa),
                        .cq_ring_base = cpu_to_le64(cq->base_pa),
                        .sg_ring_base = cpu_to_le64(q->sg_base_pa),
                        .features = cpu_to_le64(q->features),
                },
        };
        unsigned int intr_index;
        int err;

        intr_index = qcq->intr.index;

        ctx.cmd.q_init.intr_index = cpu_to_le16(intr_index);

        dev_dbg(dev, "txq_init.pid %d\n", ctx.cmd.q_init.pid);
        dev_dbg(dev, "txq_init.index %d\n", ctx.cmd.q_init.index);
        dev_dbg(dev, "txq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
        dev_dbg(dev, "txq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
        dev_dbg(dev, "txq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
        dev_dbg(dev, "txq_init.ver %d\n", ctx.cmd.q_init.ver);
        dev_dbg(dev, "txq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);

        ionic_qcq_sanitize(qcq);

        err = ionic_adminq_post_wait(lif, &ctx);
        if (err)
                return err;

        q->hw_type = ctx.comp.q_init.hw_type;
        q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
        q->dbval = IONIC_DBELL_QID(q->hw_index);

        dev_dbg(dev, "txq->hw_type %d\n", q->hw_type);
        dev_dbg(dev, "txq->hw_index %d\n", q->hw_index);

        if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
                netif_napi_add(lif->netdev, &qcq->napi, ionic_tx_napi,
                               NAPI_POLL_WEIGHT);

        qcq->flags |= IONIC_QCQ_F_INITED;

        return 0;
}

static int ionic_lif_rxq_init(struct ionic_lif *lif, struct ionic_qcq *qcq)
{
        struct device *dev = lif->ionic->dev;
        struct ionic_queue *q = &qcq->q;
        struct ionic_cq *cq = &qcq->cq;
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.q_init = {
                        .opcode = IONIC_CMD_Q_INIT,
                        .lif_index = cpu_to_le16(lif->index),
                        .type = q->type,
                        .ver = lif->qtype_info[q->type].version,
                        .index = cpu_to_le32(q->index),
                        .flags = cpu_to_le16(IONIC_QINIT_F_IRQ |
                                             IONIC_QINIT_F_SG),
                        .intr_index = cpu_to_le16(cq->bound_intr->index),
                        .pid = cpu_to_le16(q->pid),
                        .ring_size = ilog2(q->num_descs),
                        .ring_base = cpu_to_le64(q->base_pa),
                        .cq_ring_base = cpu_to_le64(cq->base_pa),
                        .sg_ring_base = cpu_to_le64(q->sg_base_pa),
                        .features = cpu_to_le64(q->features),
                },
        };
        int err;

        dev_dbg(dev, "rxq_init.pid %d\n", ctx.cmd.q_init.pid);
        dev_dbg(dev, "rxq_init.index %d\n", ctx.cmd.q_init.index);
        dev_dbg(dev, "rxq_init.ring_base 0x%llx\n", ctx.cmd.q_init.ring_base);
        dev_dbg(dev, "rxq_init.ring_size %d\n", ctx.cmd.q_init.ring_size);
        dev_dbg(dev, "rxq_init.flags 0x%x\n", ctx.cmd.q_init.flags);
        dev_dbg(dev, "rxq_init.ver %d\n", ctx.cmd.q_init.ver);
        dev_dbg(dev, "rxq_init.intr_index %d\n", ctx.cmd.q_init.intr_index);

        ionic_qcq_sanitize(qcq);

        err = ionic_adminq_post_wait(lif, &ctx);
        if (err)
                return err;

        q->hw_type = ctx.comp.q_init.hw_type;
        q->hw_index = le32_to_cpu(ctx.comp.q_init.hw_index);
        q->dbval = IONIC_DBELL_QID(q->hw_index);

        dev_dbg(dev, "rxq->hw_type %d\n", q->hw_type);
        dev_dbg(dev, "rxq->hw_index %d\n", q->hw_index);

        if (test_bit(IONIC_LIF_F_SPLIT_INTR, lif->state))
                netif_napi_add(lif->netdev, &qcq->napi, ionic_rx_napi,
                               NAPI_POLL_WEIGHT);
        else
                netif_napi_add(lif->netdev, &qcq->napi, ionic_txrx_napi,
                               NAPI_POLL_WEIGHT);

        qcq->flags |= IONIC_QCQ_F_INITED;

        return 0;
}

int ionic_lif_create_hwstamp_txq(struct ionic_lif *lif)
{
        unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
        unsigned int txq_i, flags;
        struct ionic_qcq *txq;
        u64 features;
        int err;

        mutex_lock(&lif->queue_lock);

        if (lif->hwstamp_txq)
                goto out;

        features = IONIC_Q_F_2X_CQ_DESC | IONIC_TXQ_F_HWSTAMP;

        num_desc = IONIC_MIN_TXRX_DESC;
        desc_sz = sizeof(struct ionic_txq_desc);
        comp_sz = 2 * sizeof(struct ionic_txq_comp);

        if (lif->qtype_info[IONIC_QTYPE_TXQ].version >= 1 &&
            lif->qtype_info[IONIC_QTYPE_TXQ].sg_desc_sz == sizeof(struct ionic_txq_sg_desc_v1))
                sg_desc_sz = sizeof(struct ionic_txq_sg_desc_v1);
        else
                sg_desc_sz = sizeof(struct ionic_txq_sg_desc);

        txq_i = lif->ionic->ntxqs_per_lif;
        flags = IONIC_QCQ_F_TX_STATS | IONIC_QCQ_F_SG;

        err = ionic_qcq_alloc(lif, IONIC_QTYPE_TXQ, txq_i, "hwstamp_tx", flags,
                              num_desc, desc_sz, comp_sz, sg_desc_sz,
                              lif->kern_pid, &txq);
        if (err)
                goto err_qcq_alloc;

        txq->q.features = features;

        ionic_link_qcq_interrupts(lif->adminqcq, txq);
        ionic_debugfs_add_qcq(lif, txq);

        lif->hwstamp_txq = txq;

        if (netif_running(lif->netdev)) {
                err = ionic_lif_txq_init(lif, txq);
                if (err)
                        goto err_qcq_init;

                if (test_bit(IONIC_LIF_F_UP, lif->state)) {
                        err = ionic_qcq_enable(txq);
                        if (err)
                                goto err_qcq_enable;
                }
        }

out:
        mutex_unlock(&lif->queue_lock);

        return 0;

err_qcq_enable:
        ionic_lif_qcq_deinit(lif, txq);
err_qcq_init:
        lif->hwstamp_txq = NULL;
        ionic_debugfs_del_qcq(txq);
        ionic_qcq_free(lif, txq);
        devm_kfree(lif->ionic->dev, txq);
err_qcq_alloc:
        mutex_unlock(&lif->queue_lock);
        return err;
}

int ionic_lif_create_hwstamp_rxq(struct ionic_lif *lif)
{
        unsigned int num_desc, desc_sz, comp_sz, sg_desc_sz;
        unsigned int rxq_i, flags;
        struct ionic_qcq *rxq;
        u64 features;
        int err;

        mutex_lock(&lif->queue_lock);

        if (lif->hwstamp_rxq)
                goto out;

        features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;

        num_desc = IONIC_MIN_TXRX_DESC;
        desc_sz = sizeof(struct ionic_rxq_desc);
        comp_sz = 2 * sizeof(struct ionic_rxq_comp);
        sg_desc_sz = sizeof(struct ionic_rxq_sg_desc);

        rxq_i = lif->ionic->nrxqs_per_lif;
        flags = IONIC_QCQ_F_RX_STATS | IONIC_QCQ_F_SG;

        err = ionic_qcq_alloc(lif, IONIC_QTYPE_RXQ, rxq_i, "hwstamp_rx", flags,
                              num_desc, desc_sz, comp_sz, sg_desc_sz,
                              lif->kern_pid, &rxq);
        if (err)
                goto err_qcq_alloc;

        rxq->q.features = features;

        ionic_link_qcq_interrupts(lif->adminqcq, rxq);
        ionic_debugfs_add_qcq(lif, rxq);

        lif->hwstamp_rxq = rxq;

        if (netif_running(lif->netdev)) {
                err = ionic_lif_rxq_init(lif, rxq);
                if (err)
                        goto err_qcq_init;

                if (test_bit(IONIC_LIF_F_UP, lif->state)) {
                        ionic_rx_fill(&rxq->q);
                        err = ionic_qcq_enable(rxq);
                        if (err)
                                goto err_qcq_enable;
                }
        }

out:
        mutex_unlock(&lif->queue_lock);

        return 0;

err_qcq_enable:
        ionic_lif_qcq_deinit(lif, rxq);
err_qcq_init:
        lif->hwstamp_rxq = NULL;
        ionic_debugfs_del_qcq(rxq);
        ionic_qcq_free(lif, rxq);
        devm_kfree(lif->ionic->dev, rxq);
err_qcq_alloc:
        mutex_unlock(&lif->queue_lock);
        return err;
}

int ionic_lif_config_hwstamp_rxq_all(struct ionic_lif *lif, bool rx_all)
{
        struct ionic_queue_params qparam;

        ionic_init_queue_params(lif, &qparam);

        if (rx_all)
                qparam.rxq_features = IONIC_Q_F_2X_CQ_DESC | IONIC_RXQ_F_HWSTAMP;
        else
                qparam.rxq_features = 0;

        /* if we're not running, just set the values and return */
        if (!netif_running(lif->netdev)) {
                lif->rxq_features = qparam.rxq_features;
                return 0;
        }

        return ionic_reconfigure_queues(lif, &qparam);
}

int ionic_lif_set_hwstamp_txmode(struct ionic_lif *lif, u16 txstamp_mode)
{
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.lif_setattr = {
                        .opcode = IONIC_CMD_LIF_SETATTR,
                        .index = cpu_to_le16(lif->index),
                        .attr = IONIC_LIF_ATTR_TXSTAMP,
                        .txstamp_mode = cpu_to_le16(txstamp_mode),
                },
        };

        return ionic_adminq_post_wait(lif, &ctx);
}

static void ionic_lif_del_hwstamp_rxfilt(struct ionic_lif *lif)
{
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.rx_filter_del = {
                        .opcode = IONIC_CMD_RX_FILTER_DEL,
                        .lif_index = cpu_to_le16(lif->index),
                },
        };
        struct ionic_rx_filter *f;
        u32 filter_id;
        int err;

        spin_lock_bh(&lif->rx_filters.lock);

        f = ionic_rx_filter_rxsteer(lif);
        if (!f) {
                spin_unlock_bh(&lif->rx_filters.lock);
                return;
        }

        filter_id = f->filter_id;
        ionic_rx_filter_free(lif, f);

        spin_unlock_bh(&lif->rx_filters.lock);

        netdev_dbg(lif->netdev, "rx_filter del RXSTEER (id %d)\n", filter_id);

        ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(filter_id);

        err = ionic_adminq_post_wait(lif, &ctx);
        if (err && err != -EEXIST)
                netdev_dbg(lif->netdev, "failed to delete rx_filter RXSTEER (id %d)\n", filter_id);
}

static int ionic_lif_add_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
{
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.rx_filter_add = {
                        .opcode = IONIC_CMD_RX_FILTER_ADD,
                        .lif_index = cpu_to_le16(lif->index),
                        .match = cpu_to_le16(IONIC_RX_FILTER_STEER_PKTCLASS),
                        .pkt_class = cpu_to_le64(pkt_class),
                },
        };
        u8 qtype;
        u32 qid;
        int err;

        if (!lif->hwstamp_rxq)
                return -EINVAL;

        qtype = lif->hwstamp_rxq->q.type;
        ctx.cmd.rx_filter_add.qtype = qtype;

        qid = lif->hwstamp_rxq->q.index;
        ctx.cmd.rx_filter_add.qid = cpu_to_le32(qid);

        netdev_dbg(lif->netdev, "rx_filter add RXSTEER\n");
        err = ionic_adminq_post_wait(lif, &ctx);
        if (err && err != -EEXIST)
                return err;

        return ionic_rx_filter_save(lif, 0, qid, 0, &ctx);
}

int ionic_lif_set_hwstamp_rxfilt(struct ionic_lif *lif, u64 pkt_class)
{
        ionic_lif_del_hwstamp_rxfilt(lif);

        if (!pkt_class)
                return 0;

        return ionic_lif_add_hwstamp_rxfilt(lif, pkt_class);
}

static bool ionic_notifyq_service(struct ionic_cq *cq,
                                  struct ionic_cq_info *cq_info)
{
        union ionic_notifyq_comp *comp = cq_info->cq_desc;
        struct ionic_deferred_work *work;
        struct net_device *netdev;
        struct ionic_queue *q;
        struct ionic_lif *lif;
        u64 eid;

        q = cq->bound_q;
        lif = q->info[0].cb_arg;
        netdev = lif->netdev;
        eid = le64_to_cpu(comp->event.eid);

        /* Have we run out of new completions to process? */
        if ((s64)(eid - lif->last_eid) <= 0)
                return false;

        lif->last_eid = eid;

        dev_dbg(lif->ionic->dev, "notifyq event:\n");
        dynamic_hex_dump("event ", DUMP_PREFIX_OFFSET, 16, 1,
                         comp, sizeof(*comp), true);

        switch (le16_to_cpu(comp->event.ecode)) {
        case IONIC_EVENT_LINK_CHANGE:
                ionic_link_status_check_request(lif, CAN_NOT_SLEEP);
                break;
        case IONIC_EVENT_RESET:
                work = kzalloc(sizeof(*work), GFP_ATOMIC);
                if (!work) {
                        netdev_err(lif->netdev, "Reset event dropped\n");
                } else {
                        work->type = IONIC_DW_TYPE_LIF_RESET;
                        ionic_lif_deferred_enqueue(&lif->deferred, work);
                }
                break;
        default:
                netdev_warn(netdev, "Notifyq event ecode=%d eid=%lld\n",
                            comp->event.ecode, eid);
                break;
        }

        return true;
}

static bool ionic_adminq_service(struct ionic_cq *cq,
                                 struct ionic_cq_info *cq_info)
{
        struct ionic_admin_comp *comp = cq_info->cq_desc;

        if (!color_match(comp->color, cq->done_color))
                return false;

        ionic_q_service(cq->bound_q, cq_info, le16_to_cpu(comp->comp_index));

        return true;
}

static int ionic_adminq_napi(struct napi_struct *napi, int budget)
{
        struct ionic_intr_info *intr = napi_to_cq(napi)->bound_intr;
        struct ionic_lif *lif = napi_to_cq(napi)->lif;
        struct ionic_dev *idev = &lif->ionic->idev;
        unsigned long irqflags;
        unsigned int flags = 0;
        int rx_work = 0;
        int tx_work = 0;
        int n_work = 0;
        int a_work = 0;
        int work_done;
        int credits;

        if (lif->notifyqcq && lif->notifyqcq->flags & IONIC_QCQ_F_INITED)
                n_work = ionic_cq_service(&lif->notifyqcq->cq, budget,
                                          ionic_notifyq_service, NULL, NULL);

        spin_lock_irqsave(&lif->adminq_lock, irqflags);
        if (lif->adminqcq && lif->adminqcq->flags & IONIC_QCQ_F_INITED)
                a_work = ionic_cq_service(&lif->adminqcq->cq, budget,
                                          ionic_adminq_service, NULL, NULL);
        spin_unlock_irqrestore(&lif->adminq_lock, irqflags);

        if (lif->hwstamp_rxq)
                rx_work = ionic_cq_service(&lif->hwstamp_rxq->cq, budget,
                                           ionic_rx_service, NULL, NULL);

        if (lif->hwstamp_txq)
                tx_work = ionic_cq_service(&lif->hwstamp_txq->cq, budget,
                                           ionic_tx_service, NULL, NULL);

        work_done = max(max(n_work, a_work), max(rx_work, tx_work));
        if (work_done < budget && napi_complete_done(napi, work_done)) {
                flags |= IONIC_INTR_CRED_UNMASK;
                intr->rearm_count++;
        }

        if (work_done || flags) {
                flags |= IONIC_INTR_CRED_RESET_COALESCE;
                credits = n_work + a_work + rx_work + tx_work;
                ionic_intr_credits(idev->intr_ctrl, intr->index, credits, flags);
        }

        return work_done;
}

void ionic_get_stats64(struct net_device *netdev,
                       struct rtnl_link_stats64 *ns)
{
        struct ionic_lif *lif = netdev_priv(netdev);
        struct ionic_lif_stats *ls;

        memset(ns, 0, sizeof(*ns));
        ls = &lif->info->stats;

        ns->rx_packets = le64_to_cpu(ls->rx_ucast_packets) +
                         le64_to_cpu(ls->rx_mcast_packets) +
                         le64_to_cpu(ls->rx_bcast_packets);

        ns->tx_packets = le64_to_cpu(ls->tx_ucast_packets) +
                         le64_to_cpu(ls->tx_mcast_packets) +
                         le64_to_cpu(ls->tx_bcast_packets);

        ns->rx_bytes = le64_to_cpu(ls->rx_ucast_bytes) +
                       le64_to_cpu(ls->rx_mcast_bytes) +
                       le64_to_cpu(ls->rx_bcast_bytes);

        ns->tx_bytes = le64_to_cpu(ls->tx_ucast_bytes) +
                       le64_to_cpu(ls->tx_mcast_bytes) +
                       le64_to_cpu(ls->tx_bcast_bytes);

        ns->rx_dropped = le64_to_cpu(ls->rx_ucast_drop_packets) +
                         le64_to_cpu(ls->rx_mcast_drop_packets) +
                         le64_to_cpu(ls->rx_bcast_drop_packets);

        ns->tx_dropped = le64_to_cpu(ls->tx_ucast_drop_packets) +
                         le64_to_cpu(ls->tx_mcast_drop_packets) +
                         le64_to_cpu(ls->tx_bcast_drop_packets);

        ns->multicast = le64_to_cpu(ls->rx_mcast_packets);

        ns->rx_over_errors = le64_to_cpu(ls->rx_queue_empty);

        ns->rx_missed_errors = le64_to_cpu(ls->rx_dma_error) +
                               le64_to_cpu(ls->rx_queue_disabled) +
                               le64_to_cpu(ls->rx_desc_fetch_error) +
                               le64_to_cpu(ls->rx_desc_data_error);

        ns->tx_aborted_errors = le64_to_cpu(ls->tx_dma_error) +
                                le64_to_cpu(ls->tx_queue_disabled) +
                                le64_to_cpu(ls->tx_desc_fetch_error) +
                                le64_to_cpu(ls->tx_desc_data_error);

        ns->rx_errors = ns->rx_over_errors +
                        ns->rx_missed_errors;

        ns->tx_errors = ns->tx_aborted_errors;
}

static int ionic_lif_addr_add(struct ionic_lif *lif, const u8 *addr)
{
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.rx_filter_add = {
                        .opcode = IONIC_CMD_RX_FILTER_ADD,
                        .lif_index = cpu_to_le16(lif->index),
                        .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_MAC),
                },
        };
        struct ionic_rx_filter *f;
        int err;

        /* don't bother if we already have it */
        spin_lock_bh(&lif->rx_filters.lock);
        f = ionic_rx_filter_by_addr(lif, addr);
        spin_unlock_bh(&lif->rx_filters.lock);
        if (f)
                return 0;

        netdev_dbg(lif->netdev, "rx_filter add ADDR %pM\n", addr);

        memcpy(ctx.cmd.rx_filter_add.mac.addr, addr, ETH_ALEN);
        err = ionic_adminq_post_wait(lif, &ctx);
        if (err && err != -EEXIST)
                return err;

        return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
}

static int ionic_lif_addr_del(struct ionic_lif *lif, const u8 *addr)
{
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.rx_filter_del = {
                        .opcode = IONIC_CMD_RX_FILTER_DEL,
                        .lif_index = cpu_to_le16(lif->index),
                },
        };
        struct ionic_rx_filter *f;
        int err;

        spin_lock_bh(&lif->rx_filters.lock);
        f = ionic_rx_filter_by_addr(lif, addr);
        if (!f) {
                spin_unlock_bh(&lif->rx_filters.lock);
                return -ENOENT;
        }

        netdev_dbg(lif->netdev, "rx_filter del ADDR %pM (id %d)\n",
                   addr, f->filter_id);

        ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
        ionic_rx_filter_free(lif, f);
        spin_unlock_bh(&lif->rx_filters.lock);

        err = ionic_adminq_post_wait(lif, &ctx);
        if (err && err != -EEXIST)
                return err;

        return 0;
}

static int ionic_lif_addr(struct ionic_lif *lif, const u8 *addr, bool add)
{
        unsigned int nmfilters;
        unsigned int nufilters;

        if (add) {
                /* Do we have space for this filter?  We test the counters
                 * here before checking the need for deferral so that we
                 * can return an overflow error to the stack.
                 */
                nmfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);
                nufilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);

                if ((is_multicast_ether_addr(addr) && lif->nmcast < nmfilters))
                        lif->nmcast++;
                else if (!is_multicast_ether_addr(addr) &&
                         lif->nucast < nufilters)
                        lif->nucast++;
                else
                        return -ENOSPC;
        } else {
                if (is_multicast_ether_addr(addr) && lif->nmcast)
                        lif->nmcast--;
                else if (!is_multicast_ether_addr(addr) && lif->nucast)
                        lif->nucast--;
        }

        netdev_dbg(lif->netdev, "rx_filter %s %pM\n",
                   add ? "add" : "del", addr);
        if (add)
                return ionic_lif_addr_add(lif, addr);
        else
                return ionic_lif_addr_del(lif, addr);

        return 0;
}

static int ionic_addr_add(struct net_device *netdev, const u8 *addr)
{
        return ionic_lif_addr(netdev_priv(netdev), addr, ADD_ADDR);
}

static int ionic_addr_del(struct net_device *netdev, const u8 *addr)
{
        return ionic_lif_addr(netdev_priv(netdev), addr, DEL_ADDR);
}

static void ionic_lif_rx_mode(struct ionic_lif *lif)
{
        struct net_device *netdev = lif->netdev;
        unsigned int nfilters;
        unsigned int nd_flags;
        char buf[128];
        u16 rx_mode;
        int i;
#define REMAIN(__x) (sizeof(buf) - (__x))

        mutex_lock(&lif->config_lock);

        /* grab the flags once for local use */
        nd_flags = netdev->flags;

        rx_mode = IONIC_RX_MODE_F_UNICAST;
        rx_mode |= (nd_flags & IFF_MULTICAST) ? IONIC_RX_MODE_F_MULTICAST : 0;
        rx_mode |= (nd_flags & IFF_BROADCAST) ? IONIC_RX_MODE_F_BROADCAST : 0;
        rx_mode |= (nd_flags & IFF_PROMISC) ? IONIC_RX_MODE_F_PROMISC : 0;
        rx_mode |= (nd_flags & IFF_ALLMULTI) ? IONIC_RX_MODE_F_ALLMULTI : 0;

        /* sync unicast addresses
         * next check to see if we're in an overflow state
         *    if so, we track that we overflowed and enable NIC PROMISC
         *    else if the overflow is set and not needed
         *       we remove our overflow flag and check the netdev flags
         *       to see if we can disable NIC PROMISC
         */
        __dev_uc_sync(netdev, ionic_addr_add, ionic_addr_del);
        nfilters = le32_to_cpu(lif->identity->eth.max_ucast_filters);
        if (netdev_uc_count(netdev) + 1 > nfilters) {
                rx_mode |= IONIC_RX_MODE_F_PROMISC;
                lif->uc_overflow = true;
        } else if (lif->uc_overflow) {
                lif->uc_overflow = false;
                if (!(nd_flags & IFF_PROMISC))
                        rx_mode &= ~IONIC_RX_MODE_F_PROMISC;
        }

        /* same for multicast */
        __dev_mc_sync(netdev, ionic_addr_add, ionic_addr_del);
        nfilters = le32_to_cpu(lif->identity->eth.max_mcast_filters);
        if (netdev_mc_count(netdev) > nfilters) {
                rx_mode |= IONIC_RX_MODE_F_ALLMULTI;
                lif->mc_overflow = true;
        } else if (lif->mc_overflow) {
                lif->mc_overflow = false;
                if (!(nd_flags & IFF_ALLMULTI))
                        rx_mode &= ~IONIC_RX_MODE_F_ALLMULTI;
        }

        i = scnprintf(buf, sizeof(buf), "rx_mode 0x%04x -> 0x%04x:",
                      lif->rx_mode, rx_mode);
        if (rx_mode & IONIC_RX_MODE_F_UNICAST)
                i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_UNICAST");
        if (rx_mode & IONIC_RX_MODE_F_MULTICAST)
                i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_MULTICAST");
        if (rx_mode & IONIC_RX_MODE_F_BROADCAST)
                i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_BROADCAST");
        if (rx_mode & IONIC_RX_MODE_F_PROMISC)
                i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_PROMISC");
        if (rx_mode & IONIC_RX_MODE_F_ALLMULTI)
                i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_ALLMULTI");
        if (rx_mode & IONIC_RX_MODE_F_RDMA_SNIFFER)
                i += scnprintf(&buf[i], REMAIN(i), " RX_MODE_F_RDMA_SNIFFER");
        netdev_dbg(netdev, "lif%d %s\n", lif->index, buf);

        if (lif->rx_mode != rx_mode) {
                struct ionic_admin_ctx ctx = {
                        .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                        .cmd.rx_mode_set = {
                                .opcode = IONIC_CMD_RX_MODE_SET,
                                .lif_index = cpu_to_le16(lif->index),
                        },
                };
                int err;

                ctx.cmd.rx_mode_set.rx_mode = cpu_to_le16(rx_mode);
                err = ionic_adminq_post_wait(lif, &ctx);
                if (err)
                        netdev_warn(netdev, "set rx_mode 0x%04x failed: %d\n",
                                    rx_mode, err);
                else
                        lif->rx_mode = rx_mode;
        }

        mutex_unlock(&lif->config_lock);
}

static void ionic_set_rx_mode(struct net_device *netdev, bool can_sleep)
{
        struct ionic_lif *lif = netdev_priv(netdev);
        struct ionic_deferred_work *work;

        if (!can_sleep) {
                work = kzalloc(sizeof(*work), GFP_ATOMIC);
                if (!work) {
                        netdev_err(lif->netdev, "rxmode change dropped\n");
                        return;
                }
                work->type = IONIC_DW_TYPE_RX_MODE;
                netdev_dbg(lif->netdev, "deferred: rx_mode\n");
                ionic_lif_deferred_enqueue(&lif->deferred, work);
        } else {
                ionic_lif_rx_mode(lif);
        }
}

static void ionic_ndo_set_rx_mode(struct net_device *netdev)
{
        ionic_set_rx_mode(netdev, CAN_NOT_SLEEP);
}

static __le64 ionic_netdev_features_to_nic(netdev_features_t features)
{
        u64 wanted = 0;

        if (features & NETIF_F_HW_VLAN_CTAG_TX)
                wanted |= IONIC_ETH_HW_VLAN_TX_TAG;
        if (features & NETIF_F_HW_VLAN_CTAG_RX)
                wanted |= IONIC_ETH_HW_VLAN_RX_STRIP;
        if (features & NETIF_F_HW_VLAN_CTAG_FILTER)
                wanted |= IONIC_ETH_HW_VLAN_RX_FILTER;
        if (features & NETIF_F_RXHASH)
                wanted |= IONIC_ETH_HW_RX_HASH;
        if (features & NETIF_F_RXCSUM)
                wanted |= IONIC_ETH_HW_RX_CSUM;
        if (features & NETIF_F_SG)
                wanted |= IONIC_ETH_HW_TX_SG;
        if (features & NETIF_F_HW_CSUM)
                wanted |= IONIC_ETH_HW_TX_CSUM;
        if (features & NETIF_F_TSO)
                wanted |= IONIC_ETH_HW_TSO;
        if (features & NETIF_F_TSO6)
                wanted |= IONIC_ETH_HW_TSO_IPV6;
        if (features & NETIF_F_TSO_ECN)
                wanted |= IONIC_ETH_HW_TSO_ECN;
        if (features & NETIF_F_GSO_GRE)
                wanted |= IONIC_ETH_HW_TSO_GRE;
        if (features & NETIF_F_GSO_GRE_CSUM)
                wanted |= IONIC_ETH_HW_TSO_GRE_CSUM;
        if (features & NETIF_F_GSO_IPXIP4)
                wanted |= IONIC_ETH_HW_TSO_IPXIP4;
        if (features & NETIF_F_GSO_IPXIP6)
                wanted |= IONIC_ETH_HW_TSO_IPXIP6;
        if (features & NETIF_F_GSO_UDP_TUNNEL)
                wanted |= IONIC_ETH_HW_TSO_UDP;
        if (features & NETIF_F_GSO_UDP_TUNNEL_CSUM)
                wanted |= IONIC_ETH_HW_TSO_UDP_CSUM;

        return cpu_to_le64(wanted);
}

static int ionic_set_nic_features(struct ionic_lif *lif,
                                  netdev_features_t features)
{
        struct device *dev = lif->ionic->dev;
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.lif_setattr = {
                        .opcode = IONIC_CMD_LIF_SETATTR,
                        .index = cpu_to_le16(lif->index),
                        .attr = IONIC_LIF_ATTR_FEATURES,
                },
        };
        u64 vlan_flags = IONIC_ETH_HW_VLAN_TX_TAG |
                         IONIC_ETH_HW_VLAN_RX_STRIP |
                         IONIC_ETH_HW_VLAN_RX_FILTER;
        u64 old_hw_features;
        int err;

        ctx.cmd.lif_setattr.features = ionic_netdev_features_to_nic(features);

        if (lif->phc)
                ctx.cmd.lif_setattr.features |= cpu_to_le64(IONIC_ETH_HW_TIMESTAMP);

        err = ionic_adminq_post_wait(lif, &ctx);
        if (err)
                return err;

        old_hw_features = lif->hw_features;
        lif->hw_features = le64_to_cpu(ctx.cmd.lif_setattr.features &
                                       ctx.comp.lif_setattr.features);

        if ((old_hw_features ^ lif->hw_features) & IONIC_ETH_HW_RX_HASH)
                ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);

        if ((vlan_flags & features) &&
            !(vlan_flags & le64_to_cpu(ctx.comp.lif_setattr.features)))
                dev_info_once(lif->ionic->dev, "NIC is not supporting vlan offload, likely in SmartNIC mode\n");

        if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
                dev_dbg(dev, "feature ETH_HW_VLAN_TX_TAG\n");
        if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
                dev_dbg(dev, "feature ETH_HW_VLAN_RX_STRIP\n");
        if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
                dev_dbg(dev, "feature ETH_HW_VLAN_RX_FILTER\n");
        if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
                dev_dbg(dev, "feature ETH_HW_RX_HASH\n");
        if (lif->hw_features & IONIC_ETH_HW_TX_SG)
                dev_dbg(dev, "feature ETH_HW_TX_SG\n");
        if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
                dev_dbg(dev, "feature ETH_HW_TX_CSUM\n");
        if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
                dev_dbg(dev, "feature ETH_HW_RX_CSUM\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO)
                dev_dbg(dev, "feature ETH_HW_TSO\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
                dev_dbg(dev, "feature ETH_HW_TSO_IPV6\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
                dev_dbg(dev, "feature ETH_HW_TSO_ECN\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
                dev_dbg(dev, "feature ETH_HW_TSO_GRE\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
                dev_dbg(dev, "feature ETH_HW_TSO_GRE_CSUM\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
                dev_dbg(dev, "feature ETH_HW_TSO_IPXIP4\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
                dev_dbg(dev, "feature ETH_HW_TSO_IPXIP6\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
                dev_dbg(dev, "feature ETH_HW_TSO_UDP\n");
        if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
                dev_dbg(dev, "feature ETH_HW_TSO_UDP_CSUM\n");
        if (lif->hw_features & IONIC_ETH_HW_TIMESTAMP)
                dev_dbg(dev, "feature ETH_HW_TIMESTAMP\n");

        return 0;
}

static int ionic_init_nic_features(struct ionic_lif *lif)
{
        struct net_device *netdev = lif->netdev;
        netdev_features_t features;
        int err;

        /* set up what we expect to support by default */
        features = NETIF_F_HW_VLAN_CTAG_TX |
                   NETIF_F_HW_VLAN_CTAG_RX |
                   NETIF_F_HW_VLAN_CTAG_FILTER |
                   NETIF_F_RXHASH |
                   NETIF_F_SG |
                   NETIF_F_HW_CSUM |
                   NETIF_F_RXCSUM |
                   NETIF_F_TSO |
                   NETIF_F_TSO6 |
                   NETIF_F_TSO_ECN;

        err = ionic_set_nic_features(lif, features);
        if (err)
                return err;

        /* tell the netdev what we actually can support */
        netdev->features |= NETIF_F_HIGHDMA;

        if (lif->hw_features & IONIC_ETH_HW_VLAN_TX_TAG)
                netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
        if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_STRIP)
                netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
        if (lif->hw_features & IONIC_ETH_HW_VLAN_RX_FILTER)
                netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
        if (lif->hw_features & IONIC_ETH_HW_RX_HASH)
                netdev->hw_features |= NETIF_F_RXHASH;
        if (lif->hw_features & IONIC_ETH_HW_TX_SG)
                netdev->hw_features |= NETIF_F_SG;

        if (lif->hw_features & IONIC_ETH_HW_TX_CSUM)
                netdev->hw_enc_features |= NETIF_F_HW_CSUM;
        if (lif->hw_features & IONIC_ETH_HW_RX_CSUM)
                netdev->hw_enc_features |= NETIF_F_RXCSUM;
        if (lif->hw_features & IONIC_ETH_HW_TSO)
                netdev->hw_enc_features |= NETIF_F_TSO;
        if (lif->hw_features & IONIC_ETH_HW_TSO_IPV6)
                netdev->hw_enc_features |= NETIF_F_TSO6;
        if (lif->hw_features & IONIC_ETH_HW_TSO_ECN)
                netdev->hw_enc_features |= NETIF_F_TSO_ECN;
        if (lif->hw_features & IONIC_ETH_HW_TSO_GRE)
                netdev->hw_enc_features |= NETIF_F_GSO_GRE;
        if (lif->hw_features & IONIC_ETH_HW_TSO_GRE_CSUM)
                netdev->hw_enc_features |= NETIF_F_GSO_GRE_CSUM;
        if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP4)
                netdev->hw_enc_features |= NETIF_F_GSO_IPXIP4;
        if (lif->hw_features & IONIC_ETH_HW_TSO_IPXIP6)
                netdev->hw_enc_features |= NETIF_F_GSO_IPXIP6;
        if (lif->hw_features & IONIC_ETH_HW_TSO_UDP)
                netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL;
        if (lif->hw_features & IONIC_ETH_HW_TSO_UDP_CSUM)
                netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;

        netdev->hw_features |= netdev->hw_enc_features;
        netdev->features |= netdev->hw_features;
        netdev->vlan_features |= netdev->features & ~NETIF_F_VLAN_FEATURES;

        netdev->priv_flags |= IFF_UNICAST_FLT |
                              IFF_LIVE_ADDR_CHANGE;

        return 0;
}

static int ionic_set_features(struct net_device *netdev,
                              netdev_features_t features)
{
        struct ionic_lif *lif = netdev_priv(netdev);
        int err;

        netdev_dbg(netdev, "%s: lif->features=0x%08llx new_features=0x%08llx\n",
                   __func__, (u64)lif->netdev->features, (u64)features);

        err = ionic_set_nic_features(lif, features);

        return err;
}

static int ionic_set_mac_address(struct net_device *netdev, void *sa)
{
        struct sockaddr *addr = sa;
        u8 *mac;
        int err;

        mac = (u8 *)addr->sa_data;
        if (ether_addr_equal(netdev->dev_addr, mac))
                return 0;

        err = eth_prepare_mac_addr_change(netdev, addr);
        if (err)
                return err;

        if (!is_zero_ether_addr(netdev->dev_addr)) {
                netdev_info(netdev, "deleting mac addr %pM\n",
                            netdev->dev_addr);
                ionic_addr_del(netdev, netdev->dev_addr);
        }

        eth_commit_mac_addr_change(netdev, addr);
        netdev_info(netdev, "updating mac addr %pM\n", mac);

        return ionic_addr_add(netdev, mac);
}

static void ionic_stop_queues_reconfig(struct ionic_lif *lif)
{
        /* Stop and clean the queues before reconfiguration */
        mutex_lock(&lif->queue_lock);
        netif_device_detach(lif->netdev);
        ionic_stop_queues(lif);
        ionic_txrx_deinit(lif);
}

static int ionic_start_queues_reconfig(struct ionic_lif *lif)
{
        int err;

        /* Re-init the queues after reconfiguration */

        /* The only way txrx_init can fail here is if communication
         * with FW is suddenly broken.  There's not much we can do
         * at this point - error messages have already been printed,
         * so we can continue on and the user can eventually do a
         * DOWN and UP to try to reset and clear the issue.
         */
        err = ionic_txrx_init(lif);
        mutex_unlock(&lif->queue_lock);
        ionic_link_status_check_request(lif, CAN_SLEEP);
        netif_device_attach(lif->netdev);

        return err;
}

static int ionic_change_mtu(struct net_device *netdev, int new_mtu)
{
        struct ionic_lif *lif = netdev_priv(netdev);
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.lif_setattr = {
                        .opcode = IONIC_CMD_LIF_SETATTR,
                        .index = cpu_to_le16(lif->index),
                        .attr = IONIC_LIF_ATTR_MTU,
                        .mtu = cpu_to_le32(new_mtu),
                },
        };
        int err;

        err = ionic_adminq_post_wait(lif, &ctx);
        if (err)
                return err;

        /* if we're not running, nothing more to do */
        if (!netif_running(netdev)) {
                netdev->mtu = new_mtu;
                return 0;
        }

        ionic_stop_queues_reconfig(lif);
        netdev->mtu = new_mtu;
        return ionic_start_queues_reconfig(lif);
}

static void ionic_tx_timeout_work(struct work_struct *ws)
{
        struct ionic_lif *lif = container_of(ws, struct ionic_lif, tx_timeout_work);

        if (test_bit(IONIC_LIF_F_FW_RESET, lif->state))
                return;

        /* if we were stopped before this scheduled job was launched,
         * don't bother the queues as they are already stopped.
         */
        if (!netif_running(lif->netdev))
                return;

        ionic_stop_queues_reconfig(lif);
        ionic_start_queues_reconfig(lif);
}

static void ionic_tx_timeout(struct net_device *netdev, unsigned int txqueue)
{
        struct ionic_lif *lif = netdev_priv(netdev);

        netdev_info(lif->netdev, "Tx Timeout triggered - txq %d\n", txqueue);
        schedule_work(&lif->tx_timeout_work);
}

static int ionic_vlan_rx_add_vid(struct net_device *netdev, __be16 proto,
                                 u16 vid)
{
        struct ionic_lif *lif = netdev_priv(netdev);
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.rx_filter_add = {
                        .opcode = IONIC_CMD_RX_FILTER_ADD,
                        .lif_index = cpu_to_le16(lif->index),
                        .match = cpu_to_le16(IONIC_RX_FILTER_MATCH_VLAN),
                        .vlan.vlan = cpu_to_le16(vid),
                },
        };
        int err;

        netdev_dbg(netdev, "rx_filter add VLAN %d\n", vid);
        err = ionic_adminq_post_wait(lif, &ctx);
        if (err)
                return err;

        return ionic_rx_filter_save(lif, 0, IONIC_RXQ_INDEX_ANY, 0, &ctx);
}

static int ionic_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto,
                                  u16 vid)
{
        struct ionic_lif *lif = netdev_priv(netdev);
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.rx_filter_del = {
                        .opcode = IONIC_CMD_RX_FILTER_DEL,
                        .lif_index = cpu_to_le16(lif->index),
                },
        };
        struct ionic_rx_filter *f;

        spin_lock_bh(&lif->rx_filters.lock);

        f = ionic_rx_filter_by_vlan(lif, vid);
        if (!f) {
                spin_unlock_bh(&lif->rx_filters.lock);
                return -ENOENT;
        }

        netdev_dbg(netdev, "rx_filter del VLAN %d (id %d)\n",
                   vid, f->filter_id);

        ctx.cmd.rx_filter_del.filter_id = cpu_to_le32(f->filter_id);
        ionic_rx_filter_free(lif, f);
        spin_unlock_bh(&lif->rx_filters.lock);

        return ionic_adminq_post_wait(lif, &ctx);
}

int ionic_lif_rss_config(struct ionic_lif *lif, const u16 types,
                         const u8 *key, const u32 *indir)
{
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.lif_setattr = {
                        .opcode = IONIC_CMD_LIF_SETATTR,
                        .attr = IONIC_LIF_ATTR_RSS,
                        .rss.addr = cpu_to_le64(lif->rss_ind_tbl_pa),
                },
        };
        unsigned int i, tbl_sz;

        if (lif->hw_features & IONIC_ETH_HW_RX_HASH) {
                lif->rss_types = types;
                ctx.cmd.lif_setattr.rss.types = cpu_to_le16(types);
        }

        if (key)
                memcpy(lif->rss_hash_key, key, IONIC_RSS_HASH_KEY_SIZE);

        if (indir) {
                tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
                for (i = 0; i < tbl_sz; i++)
                        lif->rss_ind_tbl[i] = indir[i];
        }

        memcpy(ctx.cmd.lif_setattr.rss.key, lif->rss_hash_key,
               IONIC_RSS_HASH_KEY_SIZE);

        return ionic_adminq_post_wait(lif, &ctx);
}

static int ionic_lif_rss_init(struct ionic_lif *lif)
{
        unsigned int tbl_sz;
        unsigned int i;

        lif->rss_types = IONIC_RSS_TYPE_IPV4     |
                         IONIC_RSS_TYPE_IPV4_TCP |
                         IONIC_RSS_TYPE_IPV4_UDP |
                         IONIC_RSS_TYPE_IPV6     |
                         IONIC_RSS_TYPE_IPV6_TCP |
                         IONIC_RSS_TYPE_IPV6_UDP;

        /* Fill indirection table with 'default' values */
        tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
        for (i = 0; i < tbl_sz; i++)
                lif->rss_ind_tbl[i] = ethtool_rxfh_indir_default(i, lif->nxqs);

        return ionic_lif_rss_config(lif, lif->rss_types, NULL, NULL);
}

static void ionic_lif_rss_deinit(struct ionic_lif *lif)
{
        int tbl_sz;

        tbl_sz = le16_to_cpu(lif->ionic->ident.lif.eth.rss_ind_tbl_sz);
        memset(lif->rss_ind_tbl, 0, tbl_sz);
        memset(lif->rss_hash_key, 0, IONIC_RSS_HASH_KEY_SIZE);

        ionic_lif_rss_config(lif, 0x0, NULL, NULL);
}

static void ionic_lif_quiesce(struct ionic_lif *lif)
{
        struct ionic_admin_ctx ctx = {
                .work = COMPLETION_INITIALIZER_ONSTACK(ctx.work),
                .cmd.lif_setattr = {
                        .opcode = IONIC_CMD_LIF_SETATTR,
                        .index = cpu_to_le16(lif->index),
                        .attr = IONIC_LIF_ATTR_STATE,
                        .state = IONIC_LIF_QUIESCE,
                },
        };
        int err;

        err = ionic_adminq_post_wait(lif, &ctx);
        if (err)
                netdev_err(lif->netdev, "lif quiesce failed %d\n", err);
}

static void ionic_txrx_disable(struct ionic_lif *lif)
{
        unsigned int i;
        int err = 0;

        if (lif->txqcqs) {
                for (i = 0; i < lif->nxqs; i++)
                        err = ionic_qcq_disable(lif->txqcqs[i], (err != -ETIMEDOUT));
        }

        if (lif->hwstamp_txq)
                err = ionic_qcq_disable(lif->hwstamp_txq, (err != -ETIMEDOUT));

        if (lif->rxqcqs) {
                for (i = 0; i < lif->nxqs; i++)
                        err = ionic_qcq_disable(lif->rxqcqs[i], (err != -ETIMEDOUT));
        }

        if (lif->hwstamp_rxq)
                err = ionic_qcq_disable(lif->hwstamp_rxq, (err != -ETIMEDOUT));

        ionic_lif_quiesce(lif);
}

static void ionic_txrx_deinit(struct ionic_lif *lif)
{
        unsigned int i;

        if (lif->txqcqs) {
                for (i = 0; i < lif->nxqs && lif->txqcqs[i]; i++) {
                        ionic_lif_qcq_deinit(lif, lif->txqcqs[i]);
                        ionic_tx_flush(&lif->txqcqs[i]->cq);
                        ionic_tx_empty(&lif->txqcqs[i]->q);
                }
        }

        if (lif->rxqcqs) {
                for (i = 0; i < lif->nxqs && lif->rxqcqs[i]; i++) {
                        ionic_lif_qcq_deinit(lif, lif->rxqcqs[i]);
                        ionic_rx_empty(&lif->rxqcqs[i]->q);
                }
        }
        lif->rx_mode = 0;

        if (lif->hwstamp_txq) {
                ionic_lif_qcq_deinit(lif, lif->hwstamp_txq);
                ionic_tx_flush(&lif->hwstamp_txq->cq);
                ionic_tx_empty(&lif->hwstamp_txq->q);
        }

        if (lif->hwstamp_rxq) {
                ionic_lif_qcq_deinit(lif, lif->hwstamp_rxq);
                ionic_rx_empty(&lif->hwstamp_rxq->q);
        }
}

static void ionic_txrx_free(struct ionic_lif *lif)
{
        unsigned int i;

        if (lif->txqcqs) {
                for (i = 0; i < lif->ionic->ntxqs_per_lif && lif->txqcqs[i]; i++) {
                        ionic_qcq_free(lif, lif->txqcqs[i]);
                        devm_kfree(lif->ionic->dev, lif->txqcqs[i]);
                        lif->txqcqs[i] = NULL;
                }
        }

        if (lif->rxqcqs) {
                for (i = 0; i < lif->ionic->nrxqs_per_lif && lif->rxqcqs[i]; i++) {
                        ionic_qcq_free(lif, lif->rxqcqs[i]);
                        devm_kfree(lif->ionic->dev, lif->rxqcqs[i]);
                        lif->rxqcqs[i] = NULL;
                }
        }

        if (lif->hwstamp_txq) {
                ionic_qcq_free(lif, lif->hwstamp_txq);
                devm_kfree(lif->ionic->dev, lif->hwstamp_txq);
                lif->hwstamp_txq = NULL;
        }