LXR linux/drivers/net/ethernet/marvell/octeontx2/nic/otx2

   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Marvell OcteonTx2 RVU Ethernet driver
   3 *
   4 * Copyright (C) 2020 Marvell International Ltd.
   5 *
   6 * This program is free software; you can redistribute it and/or modify
   7 * it under the terms of the GNU General Public License version 2 as
   8 * published by the Free Software Foundation.
   9 */
  10
  11#ifndef OTX2_TXRX_H
  12#define OTX2_TXRX_H
  13
  14#include <linux/etherdevice.h>
  15#include <linux/iommu.h>
  16#include <linux/if_vlan.h>
  17
  18#define LBK_CHAN_BASE   0x000
  19#define SDP_CHAN_BASE   0x700
  20#define CGX_CHAN_BASE   0x800
  21
  22#define OTX2_DATA_ALIGN(X)      ALIGN(X, OTX2_ALIGN)
  23#define OTX2_HEAD_ROOM          OTX2_ALIGN
  24
  25#define OTX2_ETH_HLEN           (VLAN_ETH_HLEN + VLAN_HLEN)
  26#define OTX2_MIN_MTU            64
  27
  28#define OTX2_MAX_GSO_SEGS       255
  29#define OTX2_MAX_FRAGS_IN_SQE   9
  30
  31/* Rx buffer size should be in multiples of 128bytes */
  32#define RCV_FRAG_LEN1(x)                                \
  33                ((OTX2_HEAD_ROOM + OTX2_DATA_ALIGN(x)) + \
  34                OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
  35
  36/* Prefer 2048 byte buffers for better last level cache
  37 * utilization or data distribution across regions.
  38 */
  39#define RCV_FRAG_LEN(x) \
  40                ((RCV_FRAG_LEN1(x) < 2048) ? 2048 : RCV_FRAG_LEN1(x))
  41
  42#define DMA_BUFFER_LEN(x)               \
  43                ((x) - OTX2_HEAD_ROOM - \
  44                OTX2_DATA_ALIGN(sizeof(struct skb_shared_info)))
  45
  46/* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
  47 * is equal to this value.
  48 */
  49#define CQ_CQE_THRESH_DEFAULT   10
  50
  51/* IRQ triggered when NIX_LF_CINTX_CNT[ECOUNT]
  52 * is nonzero and this much time elapses after that.
  53 */
  54#define CQ_TIMER_THRESH_DEFAULT 1  /* 1 usec */
  55#define CQ_TIMER_THRESH_MAX     25 /* 25 usec */
  56
  57/* Min number of CQs (of the ones mapped to this CINT)
  58 * with valid CQEs.
  59 */
  60#define CQ_QCOUNT_DEFAULT       1
  61
  62struct queue_stats {
  63        u64     bytes;
  64        u64     pkts;
  65};
  66
  67struct otx2_rcv_queue {
  68        struct queue_stats      stats;
  69};
  70
  71struct sg_list {
  72        u16     num_segs;
  73        u64     skb;
  74        u64     size[OTX2_MAX_FRAGS_IN_SQE];
  75        u64     dma_addr[OTX2_MAX_FRAGS_IN_SQE];
  76};
  77
  78struct otx2_snd_queue {
  79        u8                      aura_id;
  80        u16                     head;
  81        u16                     sqe_size;
  82        u32                     sqe_cnt;
  83        u16                     num_sqbs;
  84        u16                     sqe_thresh;
  85        u8                      sqe_per_sqb;
  86        u32                     lmt_id;
  87        u64                      io_addr;
  88        u64                     *aura_fc_addr;
  89        u64                     *lmt_addr;
  90        void                    *sqe_base;
  91        struct qmem             *sqe;
  92        struct qmem             *tso_hdrs;
  93        struct sg_list          *sg;
  94        struct qmem             *timestamps;
  95        struct queue_stats      stats;
  96        u16                     sqb_count;
  97        u64                     *sqb_ptrs;
  98} ____cacheline_aligned_in_smp;
  99
 100enum cq_type {
 101        CQ_RX,
 102        CQ_TX,
 103        CQS_PER_CINT = 2, /* RQ + SQ */
 104};
 105
 106struct otx2_cq_poll {
 107        void                    *dev;
 108#define CINT_INVALID_CQ         255
 109        u8                      cint_idx;
 110        u8                      cq_ids[CQS_PER_CINT];
 111        struct napi_struct      napi;
 112};
 113
 114struct otx2_pool {
 115        struct qmem             *stack;
 116        struct qmem             *fc_addr;
 117        u64                     *lmt_addr;
 118        u16                     rbsize;
 119};
 120
 121struct otx2_cq_queue {
 122        u8                      cq_idx;
 123        u8                      cq_type;
 124        u8                      cint_idx; /* CQ interrupt id */
 125        u8                      refill_task_sched;
 126        u16                     cqe_size;
 127        u16                     pool_ptrs;
 128        u32                     cqe_cnt;
 129        u32                     cq_head;
 130        void                    *cqe_base;
 131        struct qmem             *cqe;
 132        struct otx2_pool        *rbpool;
 133} ____cacheline_aligned_in_smp;
 134
 135struct otx2_qset {
 136        u32                     rqe_cnt;
 137        u32                     sqe_cnt; /* Keep these two at top */
 138#define OTX2_MAX_CQ_CNT         64
 139        u16                     cq_cnt;
 140        u16                     xqe_size;
 141        struct otx2_pool        *pool;
 142        struct otx2_cq_poll     *napi;
 143        struct otx2_cq_queue    *cq;
 144        struct otx2_snd_queue   *sq;
 145        struct otx2_rcv_queue   *rq;
 146};
 147
 148/* Translate IOVA to physical address */
 149static inline u64 otx2_iova_to_phys(void *iommu_domain, dma_addr_t dma_addr)
 150{
 151        /* Translation is installed only when IOMMU is present */
 152        if (likely(iommu_domain))
 153                return iommu_iova_to_phys(iommu_domain, dma_addr);
 154        return dma_addr;
 155}
 156
 157int otx2_napi_handler(struct napi_struct *napi, int budget);
 158bool otx2_sq_append_skb(struct net_device *netdev, struct otx2_snd_queue *sq,
 159                        struct sk_buff *skb, u16 qidx);
 160void cn10k_sqe_flush(void *dev, struct otx2_snd_queue *sq,
 161                     int size, int qidx);
 162void otx2_sqe_flush(void *dev, struct otx2_snd_queue *sq,
 163                    int size, int qidx);
 164void otx2_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
 165void cn10k_refill_pool_ptrs(void *dev, struct otx2_cq_queue *cq);
 166#endif /* OTX2_TXRX_H */
 167