linux/drivers/net/ethernet/marvell/mvpp2/mvpp2.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/*
   3 * Definitions for Marvell PPv2 network controller for Armada 375 SoC.
   4 *
   5 * Copyright (C) 2014 Marvell
   6 *
   7 * Marcin Wojtas <mw@semihalf.com>
   8 */
   9#ifndef _MVPP2_H_
  10#define _MVPP2_H_
  11
  12#include <linux/interrupt.h>
  13#include <linux/kernel.h>
  14#include <linux/netdevice.h>
  15#include <linux/net_tstamp.h>
  16#include <linux/phy.h>
  17#include <linux/phylink.h>
  18#include <net/flow_offload.h>
  19#include <net/page_pool.h>
  20#include <linux/bpf.h>
  21#include <net/xdp.h>
  22
  23/* The PacketOffset field is measured in units of 32 bytes and is 3 bits wide,
  24 * so the maximum offset is 7 * 32 = 224
  25 */
  26#define MVPP2_SKB_HEADROOM      min(max(XDP_PACKET_HEADROOM, NET_SKB_PAD), 224)
  27
  28#define MVPP2_XDP_PASS          0
  29#define MVPP2_XDP_DROPPED       BIT(0)
  30#define MVPP2_XDP_TX            BIT(1)
  31#define MVPP2_XDP_REDIR         BIT(2)
  32
  33/* Fifo Registers */
  34#define MVPP2_RX_DATA_FIFO_SIZE_REG(port)       (0x00 + 4 * (port))
  35#define MVPP2_RX_ATTR_FIFO_SIZE_REG(port)       (0x20 + 4 * (port))
  36#define MVPP2_RX_MIN_PKT_SIZE_REG               0x60
  37#define MVPP2_RX_FIFO_INIT_REG                  0x64
  38#define MVPP22_TX_FIFO_THRESH_REG(port)         (0x8840 + 4 * (port))
  39#define MVPP22_TX_FIFO_SIZE_REG(port)           (0x8860 + 4 * (port))
  40
  41/* RX DMA Top Registers */
  42#define MVPP2_RX_CTRL_REG(port)                 (0x140 + 4 * (port))
  43#define     MVPP2_RX_LOW_LATENCY_PKT_SIZE(s)    (((s) & 0xfff) << 16)
  44#define     MVPP2_RX_USE_PSEUDO_FOR_CSUM_MASK   BIT(31)
  45#define MVPP2_POOL_BUF_SIZE_REG(pool)           (0x180 + 4 * (pool))
  46#define     MVPP2_POOL_BUF_SIZE_OFFSET          5
  47#define MVPP2_RXQ_CONFIG_REG(rxq)               (0x800 + 4 * (rxq))
  48#define     MVPP2_SNOOP_PKT_SIZE_MASK           0x1ff
  49#define     MVPP2_SNOOP_BUF_HDR_MASK            BIT(9)
  50#define     MVPP2_RXQ_POOL_SHORT_OFFS           20
  51#define     MVPP21_RXQ_POOL_SHORT_MASK          0x700000
  52#define     MVPP22_RXQ_POOL_SHORT_MASK          0xf00000
  53#define     MVPP2_RXQ_POOL_LONG_OFFS            24
  54#define     MVPP21_RXQ_POOL_LONG_MASK           0x7000000
  55#define     MVPP22_RXQ_POOL_LONG_MASK           0xf000000
  56#define     MVPP2_RXQ_PACKET_OFFSET_OFFS        28
  57#define     MVPP2_RXQ_PACKET_OFFSET_MASK        0x70000000
  58#define     MVPP2_RXQ_DISABLE_MASK              BIT(31)
  59
  60/* Top Registers */
  61#define MVPP2_MH_REG(port)                      (0x5040 + 4 * (port))
  62#define MVPP2_DSA_EXTENDED                      BIT(5)
  63#define MVPP2_VER_ID_REG                        0x50b0
  64#define MVPP2_VER_PP22                          0x10
  65#define MVPP2_VER_PP23                          0x11
  66
  67/* Parser Registers */
  68#define MVPP2_PRS_INIT_LOOKUP_REG               0x1000
  69#define     MVPP2_PRS_PORT_LU_MAX               0xf
  70#define     MVPP2_PRS_PORT_LU_MASK(port)        (0xff << ((port) * 4))
  71#define     MVPP2_PRS_PORT_LU_VAL(port, val)    ((val) << ((port) * 4))
  72#define MVPP2_PRS_INIT_OFFS_REG(port)           (0x1004 + ((port) & 4))
  73#define     MVPP2_PRS_INIT_OFF_MASK(port)       (0x3f << (((port) % 4) * 8))
  74#define     MVPP2_PRS_INIT_OFF_VAL(port, val)   ((val) << (((port) % 4) * 8))
  75#define MVPP2_PRS_MAX_LOOP_REG(port)            (0x100c + ((port) & 4))
  76#define     MVPP2_PRS_MAX_LOOP_MASK(port)       (0xff << (((port) % 4) * 8))
  77#define     MVPP2_PRS_MAX_LOOP_VAL(port, val)   ((val) << (((port) % 4) * 8))
  78#define MVPP2_PRS_TCAM_IDX_REG                  0x1100
  79#define MVPP2_PRS_TCAM_DATA_REG(idx)            (0x1104 + (idx) * 4)
  80#define     MVPP2_PRS_TCAM_INV_MASK             BIT(31)
  81#define MVPP2_PRS_SRAM_IDX_REG                  0x1200
  82#define MVPP2_PRS_SRAM_DATA_REG(idx)            (0x1204 + (idx) * 4)
  83#define MVPP2_PRS_TCAM_CTRL_REG                 0x1230
  84#define     MVPP2_PRS_TCAM_EN_MASK              BIT(0)
  85#define MVPP2_PRS_TCAM_HIT_IDX_REG              0x1240
  86#define MVPP2_PRS_TCAM_HIT_CNT_REG              0x1244
  87#define     MVPP2_PRS_TCAM_HIT_CNT_MASK         GENMASK(15, 0)
  88
  89/* RSS Registers */
  90#define MVPP22_RSS_INDEX                        0x1500
  91#define     MVPP22_RSS_INDEX_TABLE_ENTRY(idx)   (idx)
  92#define     MVPP22_RSS_INDEX_TABLE(idx)         ((idx) << 8)
  93#define     MVPP22_RSS_INDEX_QUEUE(idx)         ((idx) << 16)
  94#define MVPP22_RXQ2RSS_TABLE                    0x1504
  95#define     MVPP22_RSS_TABLE_POINTER(p)         (p)
  96#define MVPP22_RSS_TABLE_ENTRY                  0x1508
  97#define MVPP22_RSS_WIDTH                        0x150c
  98
  99/* Classifier Registers */
 100#define MVPP2_CLS_MODE_REG                      0x1800
 101#define     MVPP2_CLS_MODE_ACTIVE_MASK          BIT(0)
 102#define MVPP2_CLS_PORT_WAY_REG                  0x1810
 103#define     MVPP2_CLS_PORT_WAY_MASK(port)       (1 << (port))
 104#define MVPP2_CLS_LKP_INDEX_REG                 0x1814
 105#define     MVPP2_CLS_LKP_INDEX_WAY_OFFS        6
 106#define MVPP2_CLS_LKP_TBL_REG                   0x1818
 107#define     MVPP2_CLS_LKP_TBL_RXQ_MASK          0xff
 108#define     MVPP2_CLS_LKP_FLOW_PTR(flow)        ((flow) << 16)
 109#define     MVPP2_CLS_LKP_TBL_LOOKUP_EN_MASK    BIT(25)
 110#define MVPP2_CLS_FLOW_INDEX_REG                0x1820
 111#define MVPP2_CLS_FLOW_TBL0_REG                 0x1824
 112#define     MVPP2_CLS_FLOW_TBL0_LAST            BIT(0)
 113#define     MVPP2_CLS_FLOW_TBL0_ENG_MASK        0x7
 114#define     MVPP2_CLS_FLOW_TBL0_OFFS            1
 115#define     MVPP2_CLS_FLOW_TBL0_ENG(x)          ((x) << 1)
 116#define     MVPP2_CLS_FLOW_TBL0_PORT_ID_MASK    0xff
 117#define     MVPP2_CLS_FLOW_TBL0_PORT_ID(port)   ((port) << 4)
 118#define     MVPP2_CLS_FLOW_TBL0_PORT_ID_SEL     BIT(23)
 119#define MVPP2_CLS_FLOW_TBL1_REG                 0x1828
 120#define     MVPP2_CLS_FLOW_TBL1_N_FIELDS_MASK   0x7
 121#define     MVPP2_CLS_FLOW_TBL1_N_FIELDS(x)     (x)
 122#define     MVPP2_CLS_FLOW_TBL1_LU_TYPE(lu)     (((lu) & 0x3f) << 3)
 123#define     MVPP2_CLS_FLOW_TBL1_PRIO_MASK       0x3f
 124#define     MVPP2_CLS_FLOW_TBL1_PRIO(x)         ((x) << 9)
 125#define     MVPP2_CLS_FLOW_TBL1_SEQ_MASK        0x7
 126#define     MVPP2_CLS_FLOW_TBL1_SEQ(x)          ((x) << 15)
 127#define MVPP2_CLS_FLOW_TBL2_REG                 0x182c
 128#define     MVPP2_CLS_FLOW_TBL2_FLD_MASK        0x3f
 129#define     MVPP2_CLS_FLOW_TBL2_FLD_OFFS(n)     ((n) * 6)
 130#define     MVPP2_CLS_FLOW_TBL2_FLD(n, x)       ((x) << ((n) * 6))
 131#define MVPP2_CLS_OVERSIZE_RXQ_LOW_REG(port)    (0x1980 + ((port) * 4))
 132#define     MVPP2_CLS_OVERSIZE_RXQ_LOW_BITS     3
 133#define     MVPP2_CLS_OVERSIZE_RXQ_LOW_MASK     0x7
 134#define MVPP2_CLS_SWFWD_P2HQ_REG(port)          (0x19b0 + ((port) * 4))
 135#define MVPP2_CLS_SWFWD_PCTRL_REG               0x19d0
 136#define     MVPP2_CLS_SWFWD_PCTRL_MASK(port)    (1 << (port))
 137
 138/* Classifier C2 engine Registers */
 139#define MVPP22_CLS_C2_TCAM_IDX                  0x1b00
 140#define MVPP22_CLS_C2_TCAM_DATA0                0x1b10
 141#define MVPP22_CLS_C2_TCAM_DATA1                0x1b14
 142#define MVPP22_CLS_C2_TCAM_DATA2                0x1b18
 143#define MVPP22_CLS_C2_TCAM_DATA3                0x1b1c
 144#define MVPP22_CLS_C2_TCAM_DATA4                0x1b20
 145#define     MVPP22_CLS_C2_LU_TYPE(lu)           ((lu) & 0x3f)
 146#define     MVPP22_CLS_C2_PORT_ID(port)         ((port) << 8)
 147#define     MVPP22_CLS_C2_PORT_MASK             (0xff << 8)
 148#define MVPP22_CLS_C2_TCAM_INV                  0x1b24
 149#define     MVPP22_CLS_C2_TCAM_INV_BIT          BIT(31)
 150#define MVPP22_CLS_C2_HIT_CTR                   0x1b50
 151#define MVPP22_CLS_C2_ACT                       0x1b60
 152#define     MVPP22_CLS_C2_ACT_RSS_EN(act)       (((act) & 0x3) << 19)
 153#define     MVPP22_CLS_C2_ACT_FWD(act)          (((act) & 0x7) << 13)
 154#define     MVPP22_CLS_C2_ACT_QHIGH(act)        (((act) & 0x3) << 11)
 155#define     MVPP22_CLS_C2_ACT_QLOW(act)         (((act) & 0x3) << 9)
 156#define     MVPP22_CLS_C2_ACT_COLOR(act)        ((act) & 0x7)
 157#define MVPP22_CLS_C2_ATTR0                     0x1b64
 158#define     MVPP22_CLS_C2_ATTR0_QHIGH(qh)       (((qh) & 0x1f) << 24)
 159#define     MVPP22_CLS_C2_ATTR0_QHIGH_MASK      0x1f
 160#define     MVPP22_CLS_C2_ATTR0_QHIGH_OFFS      24
 161#define     MVPP22_CLS_C2_ATTR0_QLOW(ql)        (((ql) & 0x7) << 21)
 162#define     MVPP22_CLS_C2_ATTR0_QLOW_MASK       0x7
 163#define     MVPP22_CLS_C2_ATTR0_QLOW_OFFS       21
 164#define MVPP22_CLS_C2_ATTR1                     0x1b68
 165#define MVPP22_CLS_C2_ATTR2                     0x1b6c
 166#define     MVPP22_CLS_C2_ATTR2_RSS_EN          BIT(30)
 167#define MVPP22_CLS_C2_ATTR3                     0x1b70
 168#define MVPP22_CLS_C2_TCAM_CTRL                 0x1b90
 169#define     MVPP22_CLS_C2_TCAM_BYPASS_FIFO      BIT(0)
 170
 171/* Descriptor Manager Top Registers */
 172#define MVPP2_RXQ_NUM_REG                       0x2040
 173#define MVPP2_RXQ_DESC_ADDR_REG                 0x2044
 174#define     MVPP22_DESC_ADDR_OFFS               8
 175#define MVPP2_RXQ_DESC_SIZE_REG                 0x2048
 176#define     MVPP2_RXQ_DESC_SIZE_MASK            0x3ff0
 177#define MVPP2_RXQ_STATUS_UPDATE_REG(rxq)        (0x3000 + 4 * (rxq))
 178#define     MVPP2_RXQ_NUM_PROCESSED_OFFSET      0
 179#define     MVPP2_RXQ_NUM_NEW_OFFSET            16
 180#define MVPP2_RXQ_STATUS_REG(rxq)               (0x3400 + 4 * (rxq))
 181#define     MVPP2_RXQ_OCCUPIED_MASK             0x3fff
 182#define     MVPP2_RXQ_NON_OCCUPIED_OFFSET       16
 183#define     MVPP2_RXQ_NON_OCCUPIED_MASK         0x3fff0000
 184#define MVPP2_RXQ_THRESH_REG                    0x204c
 185#define     MVPP2_OCCUPIED_THRESH_OFFSET        0
 186#define     MVPP2_OCCUPIED_THRESH_MASK          0x3fff
 187#define MVPP2_RXQ_INDEX_REG                     0x2050
 188#define MVPP2_TXQ_NUM_REG                       0x2080
 189#define MVPP2_TXQ_DESC_ADDR_REG                 0x2084
 190#define MVPP2_TXQ_DESC_SIZE_REG                 0x2088
 191#define     MVPP2_TXQ_DESC_SIZE_MASK            0x3ff0
 192#define MVPP2_TXQ_THRESH_REG                    0x2094
 193#define     MVPP2_TXQ_THRESH_OFFSET             16
 194#define     MVPP2_TXQ_THRESH_MASK               0x3fff
 195#define MVPP2_AGGR_TXQ_UPDATE_REG               0x2090
 196#define MVPP2_TXQ_INDEX_REG                     0x2098
 197#define MVPP2_TXQ_PREF_BUF_REG                  0x209c
 198#define     MVPP2_PREF_BUF_PTR(desc)            ((desc) & 0xfff)
 199#define     MVPP2_PREF_BUF_SIZE_4               (BIT(12) | BIT(13))
 200#define     MVPP2_PREF_BUF_SIZE_16              (BIT(12) | BIT(14))
 201#define     MVPP2_PREF_BUF_THRESH(val)          ((val) << 17)
 202#define     MVPP2_TXQ_DRAIN_EN_MASK             BIT(31)
 203#define MVPP2_TXQ_PENDING_REG                   0x20a0
 204#define     MVPP2_TXQ_PENDING_MASK              0x3fff
 205#define MVPP2_TXQ_INT_STATUS_REG                0x20a4
 206#define MVPP2_TXQ_SENT_REG(txq)                 (0x3c00 + 4 * (txq))
 207#define     MVPP2_TRANSMITTED_COUNT_OFFSET      16
 208#define     MVPP2_TRANSMITTED_COUNT_MASK        0x3fff0000
 209#define MVPP2_TXQ_RSVD_REQ_REG                  0x20b0
 210#define     MVPP2_TXQ_RSVD_REQ_Q_OFFSET         16
 211#define MVPP2_TXQ_RSVD_RSLT_REG                 0x20b4
 212#define     MVPP2_TXQ_RSVD_RSLT_MASK            0x3fff
 213#define MVPP2_TXQ_RSVD_CLR_REG                  0x20b8
 214#define     MVPP2_TXQ_RSVD_CLR_OFFSET           16
 215#define MVPP2_AGGR_TXQ_DESC_ADDR_REG(cpu)       (0x2100 + 4 * (cpu))
 216#define     MVPP22_AGGR_TXQ_DESC_ADDR_OFFS      8
 217#define MVPP2_AGGR_TXQ_DESC_SIZE_REG(cpu)       (0x2140 + 4 * (cpu))
 218#define     MVPP2_AGGR_TXQ_DESC_SIZE_MASK       0x3ff0
 219#define MVPP2_AGGR_TXQ_STATUS_REG(cpu)          (0x2180 + 4 * (cpu))
 220#define     MVPP2_AGGR_TXQ_PENDING_MASK         0x3fff
 221#define MVPP2_AGGR_TXQ_INDEX_REG(cpu)           (0x21c0 + 4 * (cpu))
 222
 223/* MBUS bridge registers */
 224#define MVPP2_WIN_BASE(w)                       (0x4000 + ((w) << 2))
 225#define MVPP2_WIN_SIZE(w)                       (0x4020 + ((w) << 2))
 226#define MVPP2_WIN_REMAP(w)                      (0x4040 + ((w) << 2))
 227#define MVPP2_BASE_ADDR_ENABLE                  0x4060
 228
 229/* AXI Bridge Registers */
 230#define MVPP22_AXI_BM_WR_ATTR_REG               0x4100
 231#define MVPP22_AXI_BM_RD_ATTR_REG               0x4104
 232#define MVPP22_AXI_AGGRQ_DESCR_RD_ATTR_REG      0x4110
 233#define MVPP22_AXI_TXQ_DESCR_WR_ATTR_REG        0x4114
 234#define MVPP22_AXI_TXQ_DESCR_RD_ATTR_REG        0x4118
 235#define MVPP22_AXI_RXQ_DESCR_WR_ATTR_REG        0x411c
 236#define MVPP22_AXI_RX_DATA_WR_ATTR_REG          0x4120
 237#define MVPP22_AXI_TX_DATA_RD_ATTR_REG          0x4130
 238#define MVPP22_AXI_RD_NORMAL_CODE_REG           0x4150
 239#define MVPP22_AXI_RD_SNOOP_CODE_REG            0x4154
 240#define MVPP22_AXI_WR_NORMAL_CODE_REG           0x4160
 241#define MVPP22_AXI_WR_SNOOP_CODE_REG            0x4164
 242
 243/* Values for AXI Bridge registers */
 244#define MVPP22_AXI_ATTR_CACHE_OFFS              0
 245#define MVPP22_AXI_ATTR_DOMAIN_OFFS             12
 246
 247#define MVPP22_AXI_CODE_CACHE_OFFS              0
 248#define MVPP22_AXI_CODE_DOMAIN_OFFS             4
 249
 250#define MVPP22_AXI_CODE_CACHE_NON_CACHE         0x3
 251#define MVPP22_AXI_CODE_CACHE_WR_CACHE          0x7
 252#define MVPP22_AXI_CODE_CACHE_RD_CACHE          0xb
 253
 254#define MVPP22_AXI_CODE_DOMAIN_OUTER_DOM        2
 255#define MVPP22_AXI_CODE_DOMAIN_SYSTEM           3
 256
 257/* Interrupt Cause and Mask registers */
 258#define MVPP2_ISR_TX_THRESHOLD_REG(port)        (0x5140 + 4 * (port))
 259#define     MVPP2_MAX_ISR_TX_THRESHOLD          0xfffff0
 260
 261#define MVPP2_ISR_RX_THRESHOLD_REG(rxq)         (0x5200 + 4 * (rxq))
 262#define     MVPP2_MAX_ISR_RX_THRESHOLD          0xfffff0
 263#define MVPP21_ISR_RXQ_GROUP_REG(port)          (0x5400 + 4 * (port))
 264
 265#define MVPP22_ISR_RXQ_GROUP_INDEX_REG          0x5400
 266#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
 267#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
 268#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_OFFSET 7
 269
 270#define MVPP22_ISR_RXQ_GROUP_INDEX_SUBGROUP_MASK 0xf
 271#define MVPP22_ISR_RXQ_GROUP_INDEX_GROUP_MASK   0x380
 272
 273#define MVPP22_ISR_RXQ_SUB_GROUP_CONFIG_REG     0x5404
 274#define MVPP22_ISR_RXQ_SUB_GROUP_STARTQ_MASK    0x1f
 275#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_MASK      0xf00
 276#define MVPP22_ISR_RXQ_SUB_GROUP_SIZE_OFFSET    8
 277
 278#define MVPP2_ISR_ENABLE_REG(port)              (0x5420 + 4 * (port))
 279#define     MVPP2_ISR_ENABLE_INTERRUPT(mask)    ((mask) & 0xffff)
 280#define     MVPP2_ISR_DISABLE_INTERRUPT(mask)   (((mask) << 16) & 0xffff0000)
 281#define MVPP2_ISR_RX_TX_CAUSE_REG(port)         (0x5480 + 4 * (port))
 282#define     MVPP2_CAUSE_RXQ_OCCUP_DESC_ALL_MASK(version) \
 283                                        ((version) == MVPP21 ? 0xffff : 0xff)
 284#define     MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_MASK 0xff0000
 285#define     MVPP2_CAUSE_TXQ_OCCUP_DESC_ALL_OFFSET       16
 286#define     MVPP2_CAUSE_RX_FIFO_OVERRUN_MASK    BIT(24)
 287#define     MVPP2_CAUSE_FCS_ERR_MASK            BIT(25)
 288#define     MVPP2_CAUSE_TX_FIFO_UNDERRUN_MASK   BIT(26)
 289#define     MVPP2_CAUSE_TX_EXCEPTION_SUM_MASK   BIT(29)
 290#define     MVPP2_CAUSE_RX_EXCEPTION_SUM_MASK   BIT(30)
 291#define     MVPP2_CAUSE_MISC_SUM_MASK           BIT(31)
 292#define MVPP2_ISR_RX_TX_MASK_REG(port)          (0x54a0 + 4 * (port))
 293#define MVPP2_ISR_PON_RX_TX_MASK_REG            0x54bc
 294#define     MVPP2_PON_CAUSE_RXQ_OCCUP_DESC_ALL_MASK     0xffff
 295#define     MVPP2_PON_CAUSE_TXP_OCCUP_DESC_ALL_MASK     0x3fc00000
 296#define     MVPP2_PON_CAUSE_MISC_SUM_MASK               BIT(31)
 297#define MVPP2_ISR_MISC_CAUSE_REG                0x55b0
 298#define MVPP2_ISR_RX_ERR_CAUSE_REG(port)        (0x5520 + 4 * (port))
 299#define     MVPP2_ISR_RX_ERR_CAUSE_NONOCC_MASK  0x00ff
 300
 301/* Buffer Manager registers */
 302#define MVPP2_BM_POOL_BASE_REG(pool)            (0x6000 + ((pool) * 4))
 303#define     MVPP2_BM_POOL_BASE_ADDR_MASK        0xfffff80
 304#define MVPP2_BM_POOL_SIZE_REG(pool)            (0x6040 + ((pool) * 4))
 305#define     MVPP2_BM_POOL_SIZE_MASK             0xfff0
 306#define MVPP2_BM_POOL_READ_PTR_REG(pool)        (0x6080 + ((pool) * 4))
 307#define     MVPP2_BM_POOL_GET_READ_PTR_MASK     0xfff0
 308#define MVPP2_BM_POOL_PTRS_NUM_REG(pool)        (0x60c0 + ((pool) * 4))
 309#define     MVPP2_BM_POOL_PTRS_NUM_MASK         0xfff0
 310#define MVPP2_BM_BPPI_READ_PTR_REG(pool)        (0x6100 + ((pool) * 4))
 311#define MVPP2_BM_BPPI_PTRS_NUM_REG(pool)        (0x6140 + ((pool) * 4))
 312#define     MVPP2_BM_BPPI_PTR_NUM_MASK          0x7ff
 313#define MVPP22_BM_POOL_PTRS_NUM_MASK            0xfff8
 314#define     MVPP2_BM_BPPI_PREFETCH_FULL_MASK    BIT(16)
 315#define MVPP2_BM_POOL_CTRL_REG(pool)            (0x6200 + ((pool) * 4))
 316#define     MVPP2_BM_START_MASK                 BIT(0)
 317#define     MVPP2_BM_STOP_MASK                  BIT(1)
 318#define     MVPP2_BM_STATE_MASK                 BIT(4)
 319#define     MVPP2_BM_LOW_THRESH_OFFS            8
 320#define     MVPP2_BM_LOW_THRESH_MASK            0x7f00
 321#define     MVPP2_BM_LOW_THRESH_VALUE(val)      ((val) << \
 322                                                MVPP2_BM_LOW_THRESH_OFFS)
 323#define     MVPP2_BM_HIGH_THRESH_OFFS           16
 324#define     MVPP2_BM_HIGH_THRESH_MASK           0x7f0000
 325#define     MVPP2_BM_HIGH_THRESH_VALUE(val)     ((val) << \
 326                                                MVPP2_BM_HIGH_THRESH_OFFS)
 327#define     MVPP2_BM_BPPI_HIGH_THRESH           0x1E
 328#define     MVPP2_BM_BPPI_LOW_THRESH            0x1C
 329#define     MVPP23_BM_BPPI_HIGH_THRESH          0x34
 330#define     MVPP23_BM_BPPI_LOW_THRESH           0x28
 331#define MVPP2_BM_INTR_CAUSE_REG(pool)           (0x6240 + ((pool) * 4))
 332#define     MVPP2_BM_RELEASED_DELAY_MASK        BIT(0)
 333#define     MVPP2_BM_ALLOC_FAILED_MASK          BIT(1)
 334#define     MVPP2_BM_BPPE_EMPTY_MASK            BIT(2)
 335#define     MVPP2_BM_BPPE_FULL_MASK             BIT(3)
 336#define     MVPP2_BM_AVAILABLE_BP_LOW_MASK      BIT(4)
 337#define MVPP2_BM_INTR_MASK_REG(pool)            (0x6280 + ((pool) * 4))
 338#define MVPP2_BM_PHY_ALLOC_REG(pool)            (0x6400 + ((pool) * 4))
 339#define     MVPP2_BM_PHY_ALLOC_GRNTD_MASK       BIT(0)
 340#define MVPP2_BM_VIRT_ALLOC_REG                 0x6440
 341#define MVPP22_BM_ADDR_HIGH_ALLOC               0x6444
 342#define     MVPP22_BM_ADDR_HIGH_PHYS_MASK       0xff
 343#define     MVPP22_BM_ADDR_HIGH_VIRT_MASK       0xff00
 344#define     MVPP22_BM_ADDR_HIGH_VIRT_SHIFT      8
 345#define MVPP2_BM_PHY_RLS_REG(pool)              (0x6480 + ((pool) * 4))
 346#define     MVPP2_BM_PHY_RLS_MC_BUFF_MASK       BIT(0)
 347#define     MVPP2_BM_PHY_RLS_PRIO_EN_MASK       BIT(1)
 348#define     MVPP2_BM_PHY_RLS_GRNTD_MASK         BIT(2)
 349#define MVPP2_BM_VIRT_RLS_REG                   0x64c0
 350#define MVPP22_BM_ADDR_HIGH_RLS_REG             0x64c4
 351#define     MVPP22_BM_ADDR_HIGH_PHYS_RLS_MASK   0xff
 352#define     MVPP22_BM_ADDR_HIGH_VIRT_RLS_MASK   0xff00
 353#define     MVPP22_BM_ADDR_HIGH_VIRT_RLS_SHIFT  8
 354
 355/* Packet Processor per-port counters */
 356#define MVPP2_OVERRUN_ETH_DROP                  0x7000
 357#define MVPP2_CLS_ETH_DROP                      0x7020
 358
 359#define MVPP22_BM_POOL_BASE_ADDR_HIGH_REG       0x6310
 360#define     MVPP22_BM_POOL_BASE_ADDR_HIGH_MASK  0xff
 361#define     MVPP23_BM_8POOL_MODE                BIT(8)
 362
 363/* Hit counters registers */
 364#define MVPP2_CTRS_IDX                          0x7040
 365#define     MVPP22_CTRS_TX_CTR(port, txq)       ((txq) | ((port) << 3) | BIT(7))
 366#define MVPP2_TX_DESC_ENQ_CTR                   0x7100
 367#define MVPP2_TX_DESC_ENQ_TO_DDR_CTR            0x7104
 368#define MVPP2_TX_BUFF_ENQ_TO_DDR_CTR            0x7108
 369#define MVPP2_TX_DESC_ENQ_HW_FWD_CTR            0x710c
 370#define MVPP2_RX_DESC_ENQ_CTR                   0x7120
 371#define MVPP2_TX_PKTS_DEQ_CTR                   0x7130
 372#define MVPP2_TX_PKTS_FULL_QUEUE_DROP_CTR       0x7200
 373#define MVPP2_TX_PKTS_EARLY_DROP_CTR            0x7204
 374#define MVPP2_TX_PKTS_BM_DROP_CTR               0x7208
 375#define MVPP2_TX_PKTS_BM_MC_DROP_CTR            0x720c
 376#define MVPP2_RX_PKTS_FULL_QUEUE_DROP_CTR       0x7220
 377#define MVPP2_RX_PKTS_EARLY_DROP_CTR            0x7224
 378#define MVPP2_RX_PKTS_BM_DROP_CTR               0x7228
 379#define MVPP2_CLS_DEC_TBL_HIT_CTR               0x7700
 380#define MVPP2_CLS_FLOW_TBL_HIT_CTR              0x7704
 381
 382/* TX Scheduler registers */
 383#define MVPP2_TXP_SCHED_PORT_INDEX_REG          0x8000
 384#define MVPP2_TXP_SCHED_Q_CMD_REG               0x8004
 385#define     MVPP2_TXP_SCHED_ENQ_MASK            0xff
 386#define     MVPP2_TXP_SCHED_DISQ_OFFSET         8
 387#define MVPP2_TXP_SCHED_CMD_1_REG               0x8010
 388#define MVPP2_TXP_SCHED_FIXED_PRIO_REG          0x8014
 389#define MVPP2_TXP_SCHED_PERIOD_REG              0x8018
 390#define MVPP2_TXP_SCHED_MTU_REG                 0x801c
 391#define     MVPP2_TXP_MTU_MAX                   0x7FFFF
 392#define MVPP2_TXP_SCHED_REFILL_REG              0x8020
 393#define     MVPP2_TXP_REFILL_TOKENS_ALL_MASK    0x7ffff
 394#define     MVPP2_TXP_REFILL_PERIOD_ALL_MASK    0x3ff00000
 395#define     MVPP2_TXP_REFILL_PERIOD_MASK(v)     ((v) << 20)
 396#define MVPP2_TXP_SCHED_TOKEN_SIZE_REG          0x8024
 397#define     MVPP2_TXP_TOKEN_SIZE_MAX            0xffffffff
 398#define MVPP2_TXQ_SCHED_REFILL_REG(q)           (0x8040 + ((q) << 2))
 399#define     MVPP2_TXQ_REFILL_TOKENS_ALL_MASK    0x7ffff
 400#define     MVPP2_TXQ_REFILL_PERIOD_ALL_MASK    0x3ff00000
 401#define     MVPP2_TXQ_REFILL_PERIOD_MASK(v)     ((v) << 20)
 402#define MVPP2_TXQ_SCHED_TOKEN_SIZE_REG(q)       (0x8060 + ((q) << 2))
 403#define     MVPP2_TXQ_TOKEN_SIZE_MAX            0x7fffffff
 404#define MVPP2_TXQ_SCHED_TOKEN_CNTR_REG(q)       (0x8080 + ((q) << 2))
 405#define     MVPP2_TXQ_TOKEN_CNTR_MAX            0xffffffff
 406
 407/* TX general registers */
 408#define MVPP2_TX_SNOOP_REG                      0x8800
 409#define MVPP2_TX_PORT_FLUSH_REG                 0x8810
 410#define     MVPP2_TX_PORT_FLUSH_MASK(port)      (1 << (port))
 411
 412/* LMS registers */
 413#define MVPP2_SRC_ADDR_MIDDLE                   0x24
 414#define MVPP2_SRC_ADDR_HIGH                     0x28
 415#define MVPP2_PHY_AN_CFG0_REG                   0x34
 416#define     MVPP2_PHY_AN_STOP_SMI0_MASK         BIT(7)
 417#define MVPP2_MNG_EXTENDED_GLOBAL_CTRL_REG      0x305c
 418#define     MVPP2_EXT_GLOBAL_CTRL_DEFAULT       0x27
 419
 420/* Per-port registers */
 421#define MVPP2_GMAC_CTRL_0_REG                   0x0
 422#define     MVPP2_GMAC_PORT_EN_MASK             BIT(0)
 423#define     MVPP2_GMAC_PORT_TYPE_MASK           BIT(1)
 424#define     MVPP2_GMAC_MAX_RX_SIZE_OFFS         2
 425#define     MVPP2_GMAC_MAX_RX_SIZE_MASK         0x7ffc
 426#define     MVPP2_GMAC_MIB_CNTR_EN_MASK         BIT(15)
 427#define MVPP2_GMAC_CTRL_1_REG                   0x4
 428#define     MVPP2_GMAC_PERIODIC_XON_EN_MASK     BIT(1)
 429#define     MVPP2_GMAC_GMII_LB_EN_MASK          BIT(5)
 430#define     MVPP2_GMAC_PCS_LB_EN_BIT            6
 431#define     MVPP2_GMAC_PCS_LB_EN_MASK           BIT(6)
 432#define     MVPP2_GMAC_SA_LOW_OFFS              7
 433#define MVPP2_GMAC_CTRL_2_REG                   0x8
 434#define     MVPP2_GMAC_INBAND_AN_MASK           BIT(0)
 435#define     MVPP2_GMAC_FLOW_CTRL_MASK           GENMASK(2, 1)
 436#define     MVPP2_GMAC_PCS_ENABLE_MASK          BIT(3)
 437#define     MVPP2_GMAC_INTERNAL_CLK_MASK        BIT(4)
 438#define     MVPP2_GMAC_DISABLE_PADDING          BIT(5)
 439#define     MVPP2_GMAC_PORT_RESET_MASK          BIT(6)
 440#define MVPP2_GMAC_AUTONEG_CONFIG               0xc
 441#define     MVPP2_GMAC_FORCE_LINK_DOWN          BIT(0)
 442#define     MVPP2_GMAC_FORCE_LINK_PASS          BIT(1)
 443#define     MVPP2_GMAC_IN_BAND_AUTONEG          BIT(2)
 444#define     MVPP2_GMAC_IN_BAND_AUTONEG_BYPASS   BIT(3)
 445#define     MVPP2_GMAC_IN_BAND_RESTART_AN       BIT(4)
 446#define     MVPP2_GMAC_CONFIG_MII_SPEED         BIT(5)
 447#define     MVPP2_GMAC_CONFIG_GMII_SPEED        BIT(6)
 448#define     MVPP2_GMAC_AN_SPEED_EN              BIT(7)
 449#define     MVPP2_GMAC_FC_ADV_EN                BIT(9)
 450#define     MVPP2_GMAC_FC_ADV_ASM_EN            BIT(10)
 451#define     MVPP2_GMAC_FLOW_CTRL_AUTONEG        BIT(11)
 452#define     MVPP2_GMAC_CONFIG_FULL_DUPLEX       BIT(12)
 453#define     MVPP2_GMAC_AN_DUPLEX_EN             BIT(13)
 454#define MVPP2_GMAC_STATUS0                      0x10
 455#define     MVPP2_GMAC_STATUS0_LINK_UP          BIT(0)
 456#define     MVPP2_GMAC_STATUS0_GMII_SPEED       BIT(1)
 457#define     MVPP2_GMAC_STATUS0_MII_SPEED        BIT(2)
 458#define     MVPP2_GMAC_STATUS0_FULL_DUPLEX      BIT(3)
 459#define     MVPP2_GMAC_STATUS0_RX_PAUSE         BIT(4)
 460#define     MVPP2_GMAC_STATUS0_TX_PAUSE         BIT(5)
 461#define     MVPP2_GMAC_STATUS0_AN_COMPLETE      BIT(11)
 462#define MVPP2_GMAC_PORT_FIFO_CFG_1_REG          0x1c
 463#define     MVPP2_GMAC_TX_FIFO_MIN_TH_OFFS      6
 464#define     MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK  0x1fc0
 465#define     MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(v)   (((v) << 6) & \
 466                                        MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK)
 467#define MVPP22_GMAC_INT_STAT                    0x20
 468#define     MVPP22_GMAC_INT_STAT_LINK           BIT(1)
 469#define MVPP22_GMAC_INT_MASK                    0x24
 470#define     MVPP22_GMAC_INT_MASK_LINK_STAT      BIT(1)
 471#define MVPP22_GMAC_CTRL_4_REG                  0x90
 472#define     MVPP22_CTRL4_EXT_PIN_GMII_SEL       BIT(0)
 473#define     MVPP22_CTRL4_RX_FC_EN               BIT(3)
 474#define     MVPP22_CTRL4_TX_FC_EN               BIT(4)
 475#define     MVPP22_CTRL4_DP_CLK_SEL             BIT(5)
 476#define     MVPP22_CTRL4_SYNC_BYPASS_DIS        BIT(6)
 477#define     MVPP22_CTRL4_QSGMII_BYPASS_ACTIVE   BIT(7)
 478#define MVPP22_GMAC_INT_SUM_STAT                0xa0
 479#define     MVPP22_GMAC_INT_SUM_STAT_INTERNAL   BIT(1)
 480#define     MVPP22_GMAC_INT_SUM_STAT_PTP        BIT(2)
 481#define MVPP22_GMAC_INT_SUM_MASK                0xa4
 482#define     MVPP22_GMAC_INT_SUM_MASK_LINK_STAT  BIT(1)
 483#define     MVPP22_GMAC_INT_SUM_MASK_PTP        BIT(2)
 484
 485/* Per-port XGMAC registers. PPv2.2 and PPv2.3, only for GOP port 0,
 486 * relative to port->base.
 487 */
 488#define MVPP22_XLG_CTRL0_REG                    0x100
 489#define     MVPP22_XLG_CTRL0_PORT_EN            BIT(0)
 490#define     MVPP22_XLG_CTRL0_MAC_RESET_DIS      BIT(1)
 491#define     MVPP22_XLG_CTRL0_FORCE_LINK_DOWN    BIT(2)
 492#define     MVPP22_XLG_CTRL0_FORCE_LINK_PASS    BIT(3)
 493#define     MVPP22_XLG_CTRL0_RX_FLOW_CTRL_EN    BIT(7)
 494#define     MVPP22_XLG_CTRL0_TX_FLOW_CTRL_EN    BIT(8)
 495#define     MVPP22_XLG_CTRL0_MIB_CNT_DIS        BIT(14)
 496#define MVPP22_XLG_CTRL1_REG                    0x104
 497#define     MVPP22_XLG_CTRL1_FRAMESIZELIMIT_OFFS        0
 498#define     MVPP22_XLG_CTRL1_FRAMESIZELIMIT_MASK        0x1fff
 499#define MVPP22_XLG_STATUS                       0x10c
 500#define     MVPP22_XLG_STATUS_LINK_UP           BIT(0)
 501#define MVPP22_XLG_INT_STAT                     0x114
 502#define     MVPP22_XLG_INT_STAT_LINK            BIT(1)
 503#define MVPP22_XLG_INT_MASK                     0x118
 504#define     MVPP22_XLG_INT_MASK_LINK            BIT(1)
 505#define MVPP22_XLG_CTRL3_REG                    0x11c
 506#define     MVPP22_XLG_CTRL3_MACMODESELECT_MASK (7 << 13)
 507#define     MVPP22_XLG_CTRL3_MACMODESELECT_GMAC (0 << 13)
 508#define     MVPP22_XLG_CTRL3_MACMODESELECT_10G  (1 << 13)
 509#define MVPP22_XLG_EXT_INT_STAT                 0x158
 510#define     MVPP22_XLG_EXT_INT_STAT_XLG         BIT(1)
 511#define     MVPP22_XLG_EXT_INT_STAT_PTP         BIT(7)
 512#define MVPP22_XLG_EXT_INT_MASK                 0x15c
 513#define     MVPP22_XLG_EXT_INT_MASK_XLG         BIT(1)
 514#define     MVPP22_XLG_EXT_INT_MASK_GIG         BIT(2)
 515#define     MVPP22_XLG_EXT_INT_MASK_PTP         BIT(7)
 516#define MVPP22_XLG_CTRL4_REG                    0x184
 517#define     MVPP22_XLG_CTRL4_FWD_FC             BIT(5)
 518#define     MVPP22_XLG_CTRL4_FWD_PFC            BIT(6)
 519#define     MVPP22_XLG_CTRL4_MACMODSELECT_GMAC  BIT(12)
 520#define     MVPP22_XLG_CTRL4_EN_IDLE_CHECK      BIT(14)
 521
 522/* SMI registers. PPv2.2 and PPv2.3, relative to priv->iface_base. */
 523#define MVPP22_SMI_MISC_CFG_REG                 0x1204
 524#define     MVPP22_SMI_POLLING_EN               BIT(10)
 525
 526/* TAI registers, PPv2.2 only, relative to priv->iface_base */
 527#define MVPP22_TAI_INT_CAUSE                    0x1400
 528#define MVPP22_TAI_INT_MASK                     0x1404
 529#define MVPP22_TAI_CR0                          0x1408
 530#define MVPP22_TAI_CR1                          0x140c
 531#define MVPP22_TAI_TCFCR0                       0x1410
 532#define MVPP22_TAI_TCFCR1                       0x1414
 533#define MVPP22_TAI_TCFCR2                       0x1418
 534#define MVPP22_TAI_FATWR                        0x141c
 535#define MVPP22_TAI_TOD_STEP_NANO_CR             0x1420
 536#define MVPP22_TAI_TOD_STEP_FRAC_HIGH           0x1424
 537#define MVPP22_TAI_TOD_STEP_FRAC_LOW            0x1428
 538#define MVPP22_TAI_TAPDC_HIGH                   0x142c
 539#define MVPP22_TAI_TAPDC_LOW                    0x1430
 540#define MVPP22_TAI_TGTOD_SEC_HIGH               0x1434
 541#define MVPP22_TAI_TGTOD_SEC_MED                0x1438
 542#define MVPP22_TAI_TGTOD_SEC_LOW                0x143c
 543#define MVPP22_TAI_TGTOD_NANO_HIGH              0x1440
 544#define MVPP22_TAI_TGTOD_NANO_LOW               0x1444
 545#define MVPP22_TAI_TGTOD_FRAC_HIGH              0x1448
 546#define MVPP22_TAI_TGTOD_FRAC_LOW               0x144c
 547#define MVPP22_TAI_TLV_SEC_HIGH                 0x1450
 548#define MVPP22_TAI_TLV_SEC_MED                  0x1454
 549#define MVPP22_TAI_TLV_SEC_LOW                  0x1458
 550#define MVPP22_TAI_TLV_NANO_HIGH                0x145c
 551#define MVPP22_TAI_TLV_NANO_LOW                 0x1460
 552#define MVPP22_TAI_TLV_FRAC_HIGH                0x1464
 553#define MVPP22_TAI_TLV_FRAC_LOW                 0x1468
 554#define MVPP22_TAI_TCV0_SEC_HIGH                0x146c
 555#define MVPP22_TAI_TCV0_SEC_MED                 0x1470
 556#define MVPP22_TAI_TCV0_SEC_LOW                 0x1474
 557#define MVPP22_TAI_TCV0_NANO_HIGH               0x1478
 558#define MVPP22_TAI_TCV0_NANO_LOW                0x147c
 559#define MVPP22_TAI_TCV0_FRAC_HIGH               0x1480
 560#define MVPP22_TAI_TCV0_FRAC_LOW                0x1484
 561#define MVPP22_TAI_TCV1_SEC_HIGH                0x1488
 562#define MVPP22_TAI_TCV1_SEC_MED                 0x148c
 563#define MVPP22_TAI_TCV1_SEC_LOW                 0x1490
 564#define MVPP22_TAI_TCV1_NANO_HIGH               0x1494
 565#define MVPP22_TAI_TCV1_NANO_LOW                0x1498
 566#define MVPP22_TAI_TCV1_FRAC_HIGH               0x149c
 567#define MVPP22_TAI_TCV1_FRAC_LOW                0x14a0
 568#define MVPP22_TAI_TCSR                         0x14a4
 569#define MVPP22_TAI_TUC_LSB                      0x14a8
 570#define MVPP22_TAI_GFM_SEC_HIGH                 0x14ac
 571#define MVPP22_TAI_GFM_SEC_MED                  0x14b0
 572#define MVPP22_TAI_GFM_SEC_LOW                  0x14b4
 573#define MVPP22_TAI_GFM_NANO_HIGH                0x14b8
 574#define MVPP22_TAI_GFM_NANO_LOW                 0x14bc
 575#define MVPP22_TAI_GFM_FRAC_HIGH                0x14c0
 576#define MVPP22_TAI_GFM_FRAC_LOW                 0x14c4
 577#define MVPP22_TAI_PCLK_DA_HIGH                 0x14c8
 578#define MVPP22_TAI_PCLK_DA_LOW                  0x14cc
 579#define MVPP22_TAI_CTCR                         0x14d0
 580#define MVPP22_TAI_PCLK_CCC_HIGH                0x14d4
 581#define MVPP22_TAI_PCLK_CCC_LOW                 0x14d8
 582#define MVPP22_TAI_DTC_HIGH                     0x14dc
 583#define MVPP22_TAI_DTC_LOW                      0x14e0
 584#define MVPP22_TAI_CCC_HIGH                     0x14e4
 585#define MVPP22_TAI_CCC_LOW                      0x14e8
 586#define MVPP22_TAI_ICICE                        0x14f4
 587#define MVPP22_TAI_ICICC_LOW                    0x14f8
 588#define MVPP22_TAI_TUC_MSB                      0x14fc
 589
 590#define MVPP22_GMAC_BASE(port)          (0x7000 + (port) * 0x1000 + 0xe00)
 591
 592#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK      0xff
 593
 594/* Descriptor ring Macros */
 595#define MVPP2_QUEUE_NEXT_DESC(q, index) \
 596        (((index) < (q)->last_desc) ? ((index) + 1) : 0)
 597
 598/* XPCS registers.PPv2.2 and PPv2.3 */
 599#define MVPP22_MPCS_BASE(port)                  (0x7000 + (port) * 0x1000)
 600#define MVPP22_MPCS_CTRL                        0x14
 601#define     MVPP22_MPCS_CTRL_FWD_ERR_CONN       BIT(10)
 602#define MVPP22_MPCS_CLK_RESET                   0x14c
 603#define     MAC_CLK_RESET_SD_TX                 BIT(0)
 604#define     MAC_CLK_RESET_SD_RX                 BIT(1)
 605#define     MAC_CLK_RESET_MAC                   BIT(2)
 606#define     MVPP22_MPCS_CLK_RESET_DIV_RATIO(n)  ((n) << 4)
 607#define     MVPP22_MPCS_CLK_RESET_DIV_SET       BIT(11)
 608
 609/* FCA registers. PPv2.2 and PPv2.3 */
 610#define MVPP22_FCA_BASE(port)                   (0x7600 + (port) * 0x1000)
 611#define MVPP22_FCA_REG_SIZE                     16
 612#define MVPP22_FCA_REG_MASK                     0xFFFF
 613#define MVPP22_FCA_CONTROL_REG                  0x0
 614#define MVPP22_FCA_ENABLE_PERIODIC              BIT(11)
 615#define MVPP22_PERIODIC_COUNTER_LSB_REG         (0x110)
 616#define MVPP22_PERIODIC_COUNTER_MSB_REG         (0x114)
 617
 618/* XPCS registers. PPv2.2 and PPv2.3 */
 619#define MVPP22_XPCS_BASE(port)                  (0x7400 + (port) * 0x1000)
 620#define MVPP22_XPCS_CFG0                        0x0
 621#define     MVPP22_XPCS_CFG0_RESET_DIS          BIT(0)
 622#define     MVPP22_XPCS_CFG0_PCS_MODE(n)        ((n) << 3)
 623#define     MVPP22_XPCS_CFG0_ACTIVE_LANE(n)     ((n) << 5)
 624
 625/* PTP registers. PPv2.2 only */
 626#define MVPP22_PTP_BASE(port)                   (0x7800 + (port * 0x1000))
 627#define MVPP22_PTP_INT_CAUSE                    0x00
 628#define     MVPP22_PTP_INT_CAUSE_QUEUE1         BIT(6)
 629#define     MVPP22_PTP_INT_CAUSE_QUEUE0         BIT(5)
 630#define MVPP22_PTP_INT_MASK                     0x04
 631#define     MVPP22_PTP_INT_MASK_QUEUE1          BIT(6)
 632#define     MVPP22_PTP_INT_MASK_QUEUE0          BIT(5)
 633#define MVPP22_PTP_GCR                          0x08
 634#define     MVPP22_PTP_GCR_RX_RESET             BIT(13)
 635#define     MVPP22_PTP_GCR_TX_RESET             BIT(1)
 636#define     MVPP22_PTP_GCR_TSU_ENABLE           BIT(0)
 637#define MVPP22_PTP_TX_Q0_R0                     0x0c
 638#define MVPP22_PTP_TX_Q0_R1                     0x10
 639#define MVPP22_PTP_TX_Q0_R2                     0x14
 640#define MVPP22_PTP_TX_Q1_R0                     0x18
 641#define MVPP22_PTP_TX_Q1_R1                     0x1c
 642#define MVPP22_PTP_TX_Q1_R2                     0x20
 643#define MVPP22_PTP_TPCR                         0x24
 644#define MVPP22_PTP_V1PCR                        0x28
 645#define MVPP22_PTP_V2PCR                        0x2c
 646#define MVPP22_PTP_Y1731PCR                     0x30
 647#define MVPP22_PTP_NTPTSPCR                     0x34
 648#define MVPP22_PTP_NTPRXPCR                     0x38
 649#define MVPP22_PTP_NTPTXPCR                     0x3c
 650#define MVPP22_PTP_WAMPPCR                      0x40
 651#define MVPP22_PTP_NAPCR                        0x44
 652#define MVPP22_PTP_FAPCR                        0x48
 653#define MVPP22_PTP_CAPCR                        0x50
 654#define MVPP22_PTP_ATAPCR                       0x54
 655#define MVPP22_PTP_ACTAPCR                      0x58
 656#define MVPP22_PTP_CATAPCR                      0x5c
 657#define MVPP22_PTP_CACTAPCR                     0x60
 658#define MVPP22_PTP_AITAPCR                      0x64
 659#define MVPP22_PTP_CAITAPCR                     0x68
 660#define MVPP22_PTP_CITAPCR                      0x6c
 661#define MVPP22_PTP_NTP_OFF_HIGH                 0x70
 662#define MVPP22_PTP_NTP_OFF_LOW                  0x74
 663#define MVPP22_PTP_TX_PIPE_STATUS_DELAY         0x78
 664
 665/* System controller registers. Accessed through a regmap. */
 666#define GENCONF_SOFT_RESET1                             0x1108
 667#define     GENCONF_SOFT_RESET1_GOP                     BIT(6)
 668#define GENCONF_PORT_CTRL0                              0x1110
 669#define     GENCONF_PORT_CTRL0_BUS_WIDTH_SELECT         BIT(1)
 670#define     GENCONF_PORT_CTRL0_RX_DATA_SAMPLE           BIT(29)
 671#define     GENCONF_PORT_CTRL0_CLK_DIV_PHASE_CLR        BIT(31)
 672#define GENCONF_PORT_CTRL1                              0x1114
 673#define     GENCONF_PORT_CTRL1_EN(p)                    BIT(p)
 674#define     GENCONF_PORT_CTRL1_RESET(p)                 (BIT(p) << 28)
 675#define GENCONF_CTRL0                                   0x1120
 676#define     GENCONF_CTRL0_PORT2_RGMII                   BIT(0)
 677#define     GENCONF_CTRL0_PORT3_RGMII_MII               BIT(1)
 678#define     GENCONF_CTRL0_PORT3_RGMII                   BIT(2)
 679
 680/* Various constants */
 681
 682/* Coalescing */
 683#define MVPP2_TXDONE_COAL_PKTS_THRESH   64
 684#define MVPP2_TXDONE_HRTIMER_PERIOD_NS  1000000UL
 685#define MVPP2_TXDONE_COAL_USEC          1000
 686#define MVPP2_RX_COAL_PKTS              32
 687#define MVPP2_RX_COAL_USEC              64
 688
 689/* The two bytes Marvell header. Either contains a special value used
 690 * by Marvell switches when a specific hardware mode is enabled (not
 691 * supported by this driver) or is filled automatically by zeroes on
 692 * the RX side. Those two bytes being at the front of the Ethernet
 693 * header, they allow to have the IP header aligned on a 4 bytes
 694 * boundary automatically: the hardware skips those two bytes on its
 695 * own.
 696 */
 697#define MVPP2_MH_SIZE                   2
 698#define MVPP2_ETH_TYPE_LEN              2
 699#define MVPP2_PPPOE_HDR_SIZE            8
 700#define MVPP2_VLAN_TAG_LEN              4
 701#define MVPP2_VLAN_TAG_EDSA_LEN         8
 702
 703/* Lbtd 802.3 type */
 704#define MVPP2_IP_LBDT_TYPE              0xfffa
 705
 706#define MVPP2_TX_CSUM_MAX_SIZE          9800
 707
 708/* Timeout constants */
 709#define MVPP2_TX_DISABLE_TIMEOUT_MSEC   1000
 710#define MVPP2_TX_PENDING_TIMEOUT_MSEC   1000
 711
 712#define MVPP2_TX_MTU_MAX                0x7ffff
 713
 714/* Maximum number of T-CONTs of PON port */
 715#define MVPP2_MAX_TCONT                 16
 716
 717/* Maximum number of supported ports */
 718#define MVPP2_MAX_PORTS                 4
 719
 720/* Loopback port index */
 721#define MVPP2_LOOPBACK_PORT_INDEX       3
 722
 723/* Maximum number of TXQs used by single port */
 724#define MVPP2_MAX_TXQ                   8
 725
 726/* MVPP2_MAX_TSO_SEGS is the maximum number of fragments to allow in the GSO
 727 * skb. As we need a maxium of two descriptors per fragments (1 header, 1 data),
 728 * multiply this value by two to count the maximum number of skb descs needed.
 729 */
 730#define MVPP2_MAX_TSO_SEGS              300
 731#define MVPP2_MAX_SKB_DESCS             (MVPP2_MAX_TSO_SEGS * 2 + MAX_SKB_FRAGS)
 732
 733/* Max number of RXQs per port */
 734#define MVPP2_PORT_MAX_RXQ              32
 735
 736/* Max number of Rx descriptors */
 737#define MVPP2_MAX_RXD_MAX               2048
 738#define MVPP2_MAX_RXD_DFLT              1024
 739
 740/* Max number of Tx descriptors */
 741#define MVPP2_MAX_TXD_MAX               2048
 742#define MVPP2_MAX_TXD_DFLT              1024
 743
 744/* Amount of Tx descriptors that can be reserved at once by CPU */
 745#define MVPP2_CPU_DESC_CHUNK            64
 746
 747/* Max number of Tx descriptors in each aggregated queue */
 748#define MVPP2_AGGR_TXQ_SIZE             256
 749
 750/* Descriptor aligned size */
 751#define MVPP2_DESC_ALIGNED_SIZE         32
 752
 753/* Descriptor alignment mask */
 754#define MVPP2_TX_DESC_ALIGN             (MVPP2_DESC_ALIGNED_SIZE - 1)
 755
 756/* RX FIFO constants */
 757#define MVPP2_RX_FIFO_PORT_DATA_SIZE_44KB       0xb000
 758#define MVPP2_RX_FIFO_PORT_DATA_SIZE_32KB       0x8000
 759#define MVPP2_RX_FIFO_PORT_DATA_SIZE_8KB        0x2000
 760#define MVPP2_RX_FIFO_PORT_DATA_SIZE_4KB        0x1000
 761#define MVPP2_RX_FIFO_PORT_ATTR_SIZE(data_size) ((data_size) >> 6)
 762#define MVPP2_RX_FIFO_PORT_ATTR_SIZE_4KB        0x40
 763#define MVPP2_RX_FIFO_PORT_MIN_PKT              0x80
 764
 765/* TX FIFO constants */
 766#define MVPP22_TX_FIFO_DATA_SIZE_18KB           18
 767#define MVPP22_TX_FIFO_DATA_SIZE_10KB           10
 768#define MVPP22_TX_FIFO_DATA_SIZE_1KB            1
 769#define MVPP2_TX_FIFO_THRESHOLD_MIN             256 /* Bytes */
 770#define MVPP2_TX_FIFO_THRESHOLD(kb)     \
 771                ((kb) * 1024 - MVPP2_TX_FIFO_THRESHOLD_MIN)
 772
 773/* RX FIFO threshold in 1KB granularity */
 774#define MVPP23_PORT0_FIFO_TRSH  (9 * 1024)
 775#define MVPP23_PORT1_FIFO_TRSH  (4 * 1024)
 776#define MVPP23_PORT2_FIFO_TRSH  (2 * 1024)
 777
 778/* RX Flow Control Registers */
 779#define MVPP2_RX_FC_REG(port)           (0x150 + 4 * (port))
 780#define     MVPP2_RX_FC_EN              BIT(24)
 781#define     MVPP2_RX_FC_TRSH_OFFS       16
 782#define     MVPP2_RX_FC_TRSH_MASK       (0xFF << MVPP2_RX_FC_TRSH_OFFS)
 783#define     MVPP2_RX_FC_TRSH_UNIT       256
 784
 785/* MSS Flow control */
 786#define MSS_FC_COM_REG                  0
 787#define FLOW_CONTROL_ENABLE_BIT         BIT(0)
 788#define FLOW_CONTROL_UPDATE_COMMAND_BIT BIT(31)
 789#define FC_QUANTA                       0xFFFF
 790#define FC_CLK_DIVIDER                  100
 791
 792#define MSS_RXQ_TRESH_BASE              0x200
 793#define MSS_RXQ_TRESH_OFFS              4
 794#define MSS_RXQ_TRESH_REG(q, fq)        (MSS_RXQ_TRESH_BASE + (((q) + (fq)) \
 795                                        * MSS_RXQ_TRESH_OFFS))
 796
 797#define MSS_BUF_POOL_BASE               0x40
 798#define MSS_BUF_POOL_OFFS               4
 799#define MSS_BUF_POOL_REG(id)            (MSS_BUF_POOL_BASE              \
 800                                        + (id) * MSS_BUF_POOL_OFFS)
 801
 802#define MSS_BUF_POOL_STOP_MASK          0xFFF
 803#define MSS_BUF_POOL_START_MASK         (0xFFF << MSS_BUF_POOL_START_OFFS)
 804#define MSS_BUF_POOL_START_OFFS         12
 805#define MSS_BUF_POOL_PORTS_MASK         (0xF << MSS_BUF_POOL_PORTS_OFFS)
 806#define MSS_BUF_POOL_PORTS_OFFS         24
 807#define MSS_BUF_POOL_PORT_OFFS(id)      (0x1 <<                         \
 808                                        ((id) + MSS_BUF_POOL_PORTS_OFFS))
 809
 810#define MSS_RXQ_TRESH_START_MASK        0xFFFF
 811#define MSS_RXQ_TRESH_STOP_MASK         (0xFFFF << MSS_RXQ_TRESH_STOP_OFFS)
 812#define MSS_RXQ_TRESH_STOP_OFFS         16
 813
 814#define MSS_RXQ_ASS_BASE        0x80
 815#define MSS_RXQ_ASS_OFFS        4
 816#define MSS_RXQ_ASS_PER_REG     4
 817#define MSS_RXQ_ASS_PER_OFFS    8
 818#define MSS_RXQ_ASS_PORTID_OFFS 0
 819#define MSS_RXQ_ASS_PORTID_MASK 0x3
 820#define MSS_RXQ_ASS_HOSTID_OFFS 2
 821#define MSS_RXQ_ASS_HOSTID_MASK 0x3F
 822
 823#define MSS_RXQ_ASS_Q_BASE(q, fq) ((((q) + (fq)) % MSS_RXQ_ASS_PER_REG)  \
 824                                  * MSS_RXQ_ASS_PER_OFFS)
 825#define MSS_RXQ_ASS_PQ_BASE(q, fq) ((((q) + (fq)) / MSS_RXQ_ASS_PER_REG) \
 826                                   * MSS_RXQ_ASS_OFFS)
 827#define MSS_RXQ_ASS_REG(q, fq) (MSS_RXQ_ASS_BASE + MSS_RXQ_ASS_PQ_BASE(q, fq))
 828
 829#define MSS_THRESHOLD_STOP      768
 830#define MSS_THRESHOLD_START     1024
 831#define MSS_FC_MAX_TIMEOUT      5000
 832
 833/* RX buffer constants */
 834#define MVPP2_SKB_SHINFO_SIZE \
 835        SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
 836
 837#define MVPP2_RX_PKT_SIZE(mtu) \
 838        ALIGN((mtu) + MVPP2_MH_SIZE + MVPP2_VLAN_TAG_LEN + \
 839              ETH_HLEN + ETH_FCS_LEN, cache_line_size())
 840
 841#define MVPP2_RX_BUF_SIZE(pkt_size)     ((pkt_size) + MVPP2_SKB_HEADROOM)
 842#define MVPP2_RX_TOTAL_SIZE(buf_size)   ((buf_size) + MVPP2_SKB_SHINFO_SIZE)
 843#define MVPP2_RX_MAX_PKT_SIZE(total_size) \
 844        ((total_size) - MVPP2_SKB_HEADROOM - MVPP2_SKB_SHINFO_SIZE)
 845
 846#define MVPP2_MAX_RX_BUF_SIZE   (PAGE_SIZE - MVPP2_SKB_SHINFO_SIZE - MVPP2_SKB_HEADROOM)
 847
 848#define MVPP2_BIT_TO_BYTE(bit)          ((bit) / 8)
 849#define MVPP2_BIT_TO_WORD(bit)          ((bit) / 32)
 850#define MVPP2_BIT_IN_WORD(bit)          ((bit) % 32)
 851
 852#define MVPP2_N_PRS_FLOWS               52
 853#define MVPP2_N_RFS_ENTRIES_PER_FLOW    4
 854
 855/* There are 7 supported high-level flows */
 856#define MVPP2_N_RFS_RULES               (MVPP2_N_RFS_ENTRIES_PER_FLOW * 7)
 857
 858/* RSS constants */
 859#define MVPP22_N_RSS_TABLES             8
 860#define MVPP22_RSS_TABLE_ENTRIES        32
 861
 862/* IPv6 max L3 address size */
 863#define MVPP2_MAX_L3_ADDR_SIZE          16
 864
 865/* Port flags */
 866#define MVPP2_F_LOOPBACK                BIT(0)
 867#define MVPP2_F_DT_COMPAT               BIT(1)
 868
 869/* Marvell tag types */
 870enum mvpp2_tag_type {
 871        MVPP2_TAG_TYPE_NONE = 0,
 872        MVPP2_TAG_TYPE_MH   = 1,
 873        MVPP2_TAG_TYPE_DSA  = 2,
 874        MVPP2_TAG_TYPE_EDSA = 3,
 875        MVPP2_TAG_TYPE_VLAN = 4,
 876        MVPP2_TAG_TYPE_LAST = 5
 877};
 878
 879/* L2 cast enum */
 880enum mvpp2_prs_l2_cast {
 881        MVPP2_PRS_L2_UNI_CAST,
 882        MVPP2_PRS_L2_MULTI_CAST,
 883};
 884
 885/* L3 cast enum */
 886enum mvpp2_prs_l3_cast {
 887        MVPP2_PRS_L3_UNI_CAST,
 888        MVPP2_PRS_L3_MULTI_CAST,
 889        MVPP2_PRS_L3_BROAD_CAST
 890};
 891
 892/* PTP descriptor constants. The low bits of the descriptor are stored
 893 * separately from the high bits.
 894 */
 895#define MVPP22_PTP_DESC_MASK_LOW        0xfff
 896
 897/* PTPAction */
 898enum mvpp22_ptp_action {
 899        MVPP22_PTP_ACTION_NONE = 0,
 900        MVPP22_PTP_ACTION_FORWARD = 1,
 901        MVPP22_PTP_ACTION_CAPTURE = 3,
 902        /* The following have not been verified */
 903        MVPP22_PTP_ACTION_ADDTIME = 4,
 904        MVPP22_PTP_ACTION_ADDCORRECTEDTIME = 5,
 905        MVPP22_PTP_ACTION_CAPTUREADDTIME = 6,
 906        MVPP22_PTP_ACTION_CAPTUREADDCORRECTEDTIME = 7,
 907        MVPP22_PTP_ACTION_ADDINGRESSTIME = 8,
 908        MVPP22_PTP_ACTION_CAPTUREADDINGRESSTIME = 9,
 909        MVPP22_PTP_ACTION_CAPTUREINGRESSTIME = 10,
 910};
 911
 912/* PTPPacketFormat */
 913enum mvpp22_ptp_packet_format {
 914        MVPP22_PTP_PKT_FMT_PTPV2 = 0,
 915        MVPP22_PTP_PKT_FMT_PTPV1 = 1,
 916        MVPP22_PTP_PKT_FMT_Y1731 = 2,
 917        MVPP22_PTP_PKT_FMT_NTPTS = 3,
 918        MVPP22_PTP_PKT_FMT_NTPRX = 4,
 919        MVPP22_PTP_PKT_FMT_NTPTX = 5,
 920        MVPP22_PTP_PKT_FMT_TWAMP = 6,
 921};
 922
 923#define MVPP22_PTP_ACTION(x)            (((x) & 15) << 0)
 924#define MVPP22_PTP_PACKETFORMAT(x)      (((x) & 7) << 4)
 925#define MVPP22_PTP_MACTIMESTAMPINGEN    BIT(11)
 926#define MVPP22_PTP_TIMESTAMPENTRYID(x)  (((x) & 31) << 12)
 927#define MVPP22_PTP_TIMESTAMPQUEUESELECT BIT(18)
 928
 929/* BM constants */
 930#define MVPP2_BM_JUMBO_BUF_NUM          2048
 931#define MVPP2_BM_LONG_BUF_NUM           2048
 932#define MVPP2_BM_SHORT_BUF_NUM          2048
 933#define MVPP2_BM_POOL_SIZE_MAX          (16*1024 - MVPP2_BM_POOL_PTR_ALIGN/4)
 934#define MVPP2_BM_POOL_PTR_ALIGN         128
 935#define MVPP2_BM_MAX_POOLS              8
 936
 937/* BM cookie (32 bits) definition */
 938#define MVPP2_BM_COOKIE_POOL_OFFS       8
 939#define MVPP2_BM_COOKIE_CPU_OFFS        24
 940
 941#define MVPP2_BM_SHORT_FRAME_SIZE       736     /* frame size 128 */
 942#define MVPP2_BM_LONG_FRAME_SIZE        2240    /* frame size 1664 */
 943#define MVPP2_BM_JUMBO_FRAME_SIZE       10432   /* frame size 9856 */
 944/* BM short pool packet size
 945 * These value assure that for SWF the total number
 946 * of bytes allocated for each buffer will be 512
 947 */
 948#define MVPP2_BM_SHORT_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_SHORT_FRAME_SIZE)
 949#define MVPP2_BM_LONG_PKT_SIZE  MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_LONG_FRAME_SIZE)
 950#define MVPP2_BM_JUMBO_PKT_SIZE MVPP2_RX_MAX_PKT_SIZE(MVPP2_BM_JUMBO_FRAME_SIZE)
 951
 952#define MVPP21_ADDR_SPACE_SZ            0
 953#define MVPP22_ADDR_SPACE_SZ            SZ_64K
 954
 955#define MVPP2_MAX_THREADS               9
 956#define MVPP2_MAX_QVECS                 MVPP2_MAX_THREADS
 957
 958/* GMAC MIB Counters register definitions */
 959#define MVPP21_MIB_COUNTERS_OFFSET              0x1000
 960#define MVPP21_MIB_COUNTERS_PORT_SZ             0x400
 961#define MVPP22_MIB_COUNTERS_OFFSET              0x0
 962#define MVPP22_MIB_COUNTERS_PORT_SZ             0x100
 963
 964#define MVPP2_MIB_GOOD_OCTETS_RCVD              0x0
 965#define MVPP2_MIB_BAD_OCTETS_RCVD               0x8
 966#define MVPP2_MIB_CRC_ERRORS_SENT               0xc
 967#define MVPP2_MIB_UNICAST_FRAMES_RCVD           0x10
 968#define MVPP2_MIB_BROADCAST_FRAMES_RCVD         0x18
 969#define MVPP2_MIB_MULTICAST_FRAMES_RCVD         0x1c
 970#define MVPP2_MIB_FRAMES_64_OCTETS              0x20
 971#define MVPP2_MIB_FRAMES_65_TO_127_OCTETS       0x24
 972#define MVPP2_MIB_FRAMES_128_TO_255_OCTETS      0x28
 973#define MVPP2_MIB_FRAMES_256_TO_511_OCTETS      0x2c
 974#define MVPP2_MIB_FRAMES_512_TO_1023_OCTETS     0x30
 975#define MVPP2_MIB_FRAMES_1024_TO_MAX_OCTETS     0x34
 976#define MVPP2_MIB_GOOD_OCTETS_SENT              0x38
 977#define MVPP2_MIB_UNICAST_FRAMES_SENT           0x40
 978#define MVPP2_MIB_MULTICAST_FRAMES_SENT         0x48
 979#define MVPP2_MIB_BROADCAST_FRAMES_SENT         0x4c
 980#define MVPP2_MIB_FC_SENT                       0x54
 981#define MVPP2_MIB_FC_RCVD                       0x58
 982#define MVPP2_MIB_RX_FIFO_OVERRUN               0x5c
 983#define MVPP2_MIB_UNDERSIZE_RCVD                0x60
 984#define MVPP2_MIB_FRAGMENTS_RCVD                0x64
 985#define MVPP2_MIB_OVERSIZE_RCVD                 0x68
 986#define MVPP2_MIB_JABBER_RCVD                   0x6c
 987#define MVPP2_MIB_MAC_RCV_ERROR                 0x70
 988#define MVPP2_MIB_BAD_CRC_EVENT                 0x74
 989#define MVPP2_MIB_COLLISION                     0x78
 990#define MVPP2_MIB_LATE_COLLISION                0x7c
 991
 992#define MVPP2_MIB_COUNTERS_STATS_DELAY          (1 * HZ)
 993
 994#define MVPP2_DESC_DMA_MASK     DMA_BIT_MASK(40)
 995
 996/* Buffer header info bits */
 997#define MVPP2_B_HDR_INFO_MC_ID_MASK     0xfff
 998#define MVPP2_B_HDR_INFO_MC_ID(info)    ((info) & MVPP2_B_HDR_INFO_MC_ID_MASK)
 999#define MVPP2_B_HDR_INFO_LAST_OFFS      12
1000#define MVPP2_B_HDR_INFO_LAST_MASK      BIT(12)
1001#define MVPP2_B_HDR_INFO_IS_LAST(info) \
1002           (((info) & MVPP2_B_HDR_INFO_LAST_MASK) >> MVPP2_B_HDR_INFO_LAST_OFFS)
1003
1004struct mvpp2_tai;
1005
1006/* Definitions */
1007struct mvpp2_dbgfs_entries;
1008
1009struct mvpp2_rss_table {
1010        u32 indir[MVPP22_RSS_TABLE_ENTRIES];
1011};
1012
1013struct mvpp2_buff_hdr {
1014        __le32 next_phys_addr;
1015        __le32 next_dma_addr;
1016        __le16 byte_count;
1017        __le16 info;
1018        __le16 reserved1;       /* bm_qset (for future use, BM) */
1019        u8 next_phys_addr_high;
1020        u8 next_dma_addr_high;
1021        __le16 reserved2;
1022        __le16 reserved3;
1023        __le16 reserved4;
1024        __le16 reserved5;
1025};
1026
1027/* Shared Packet Processor resources */
1028struct mvpp2 {
1029        /* Shared registers' base addresses */
1030        void __iomem *lms_base;
1031        void __iomem *iface_base;
1032        void __iomem *cm3_base;
1033
1034        /* On PPv2.2 and PPv2.3, each "software thread" can access the base
1035         * register through a separate address space, each 64 KB apart
1036         * from each other. Typically, such address spaces will be
1037         * used per CPU.
1038         */
1039        void __iomem *swth_base[MVPP2_MAX_THREADS];
1040
1041        /* On PPv2.2 and PPv2.3, some port control registers are located into
1042         * the system controller space. These registers are accessible
1043         * through a regmap.
1044         */
1045        struct regmap *sysctrl_base;
1046
1047        /* Common clocks */
1048        struct clk *pp_clk;
1049        struct clk *gop_clk;
1050        struct clk *mg_clk;
1051        struct clk *mg_core_clk;
1052        struct clk *axi_clk;
1053
1054        /* List of pointers to port structures */
1055        int port_count;
1056        struct mvpp2_port *port_list[MVPP2_MAX_PORTS];
1057        /* Map of enabled ports */
1058        unsigned long port_map;
1059
1060        struct mvpp2_tai *tai;
1061
1062        /* Number of Tx threads used */
1063        unsigned int nthreads;
1064        /* Map of threads needing locking */
1065        unsigned long lock_map;
1066
1067        /* Aggregated TXQs */
1068        struct mvpp2_tx_queue *aggr_txqs;
1069
1070        /* Are we using page_pool with per-cpu pools? */
1071        int percpu_pools;
1072
1073        /* BM pools */
1074        struct mvpp2_bm_pool *bm_pools;
1075
1076        /* PRS shadow table */
1077        struct mvpp2_prs_shadow *prs_shadow;
1078        /* PRS auxiliary table for double vlan entries control */
1079        bool *prs_double_vlans;
1080
1081        /* Tclk value */
1082        u32 tclk;
1083
1084        /* HW version */
1085        enum { MVPP21, MVPP22, MVPP23 } hw_version;
1086
1087        /* Maximum number of RXQs per port */
1088        unsigned int max_port_rxqs;
1089
1090        /* Workqueue to gather hardware statistics */
1091        char queue_name[30];
1092        struct workqueue_struct *stats_queue;
1093
1094        /* Debugfs root entry */
1095        struct dentry *dbgfs_dir;
1096
1097        /* Debugfs entries private data */
1098        struct mvpp2_dbgfs_entries *dbgfs_entries;
1099
1100        /* RSS Indirection tables */
1101        struct mvpp2_rss_table *rss_tables[MVPP22_N_RSS_TABLES];
1102
1103        /* page_pool allocator */
1104        struct page_pool *page_pool[MVPP2_PORT_MAX_RXQ];
1105
1106        /* Global TX Flow Control config */
1107        bool global_tx_fc;
1108
1109        /* Spinlocks for CM3 shared memory configuration */
1110        spinlock_t mss_spinlock;
1111};
1112
1113struct mvpp2_pcpu_stats {
1114        struct  u64_stats_sync syncp;
1115        u64     rx_packets;
1116        u64     rx_bytes;
1117        u64     tx_packets;
1118        u64     tx_bytes;
1119        /* XDP */
1120        u64     xdp_redirect;
1121        u64     xdp_pass;
1122        u64     xdp_drop;
1123        u64     xdp_xmit;
1124        u64     xdp_xmit_err;
1125        u64     xdp_tx;
1126        u64     xdp_tx_err;
1127};
1128
1129/* Per-CPU port control */
1130struct mvpp2_port_pcpu {
1131        struct hrtimer tx_done_timer;
1132        struct net_device *dev;
1133        bool timer_scheduled;
1134};
1135
1136struct mvpp2_queue_vector {
1137        int irq;
1138        struct napi_struct napi;
1139        enum { MVPP2_QUEUE_VECTOR_SHARED, MVPP2_QUEUE_VECTOR_PRIVATE } type;
1140        int sw_thread_id;
1141        u16 sw_thread_mask;
1142        int first_rxq;
1143        int nrxqs;
1144        u32 pending_cause_rx;
1145        struct mvpp2_port *port;
1146        struct cpumask *mask;
1147};
1148
1149/* Internal represention of a Flow Steering rule */
1150struct mvpp2_rfs_rule {
1151        /* Rule location inside the flow*/
1152        int loc;
1153
1154        /* Flow type, such as TCP_V4_FLOW, IP6_FLOW, etc. */
1155        int flow_type;
1156
1157        /* Index of the C2 TCAM entry handling this rule */
1158        int c2_index;
1159
1160        /* Header fields that needs to be extracted to match this flow */
1161        u16 hek_fields;
1162
1163        /* CLS engine : only c2 is supported for now. */
1164        u8 engine;
1165
1166        /* TCAM key and mask for C2-based steering. These fields should be
1167         * encapsulated in a union should we add more engines.
1168         */
1169        u64 c2_tcam;
1170        u64 c2_tcam_mask;
1171
1172        struct flow_rule *flow;
1173};
1174
1175struct mvpp2_ethtool_fs {
1176        struct mvpp2_rfs_rule rule;
1177        struct ethtool_rxnfc rxnfc;
1178};
1179
1180struct mvpp2_hwtstamp_queue {
1181        struct sk_buff *skb[32];
1182        u8 next;
1183};
1184
1185struct mvpp2_port {
1186        u8 id;
1187
1188        /* Index of the port from the "group of ports" complex point
1189         * of view. This is specific to PPv2.2.
1190         */
1191        int gop_id;
1192
1193        int port_irq;
1194
1195        struct mvpp2 *priv;
1196
1197        /* Firmware node associated to the port */
1198        struct fwnode_handle *fwnode;
1199
1200        /* Per-port registers' base address */
1201        void __iomem *base;
1202        void __iomem *stats_base;
1203
1204        struct mvpp2_rx_queue **rxqs;
1205        unsigned int nrxqs;
1206        struct mvpp2_tx_queue **txqs;
1207        unsigned int ntxqs;
1208        struct net_device *dev;
1209
1210        struct bpf_prog *xdp_prog;
1211
1212        int pkt_size;
1213
1214        /* Per-CPU port control */
1215        struct mvpp2_port_pcpu __percpu *pcpu;
1216
1217        /* Protect the BM refills and the Tx paths when a thread is used on more
1218         * than a single CPU.
1219         */
1220        spinlock_t bm_lock[MVPP2_MAX_THREADS];
1221        spinlock_t tx_lock[MVPP2_MAX_THREADS];
1222
1223        /* Flags */
1224        unsigned long flags;
1225
1226        u16 tx_ring_size;
1227        u16 rx_ring_size;
1228        struct mvpp2_pcpu_stats __percpu *stats;
1229        u64 *ethtool_stats;
1230
1231        unsigned long state;
1232
1233        /* Per-port work and its lock to gather hardware statistics */
1234        struct mutex gather_stats_lock;
1235        struct delayed_work stats_work;
1236
1237        struct device_node *of_node;
1238
1239        phy_interface_t phy_interface;
1240        struct phylink *phylink;
1241        struct phylink_config phylink_config;
1242        struct phylink_pcs phylink_pcs;
1243        struct phy *comphy;
1244
1245        struct mvpp2_bm_pool *pool_long;
1246        struct mvpp2_bm_pool *pool_short;
1247
1248        /* Index of first port's physical RXQ */
1249        u8 first_rxq;
1250
1251        struct mvpp2_queue_vector qvecs[MVPP2_MAX_QVECS];
1252        unsigned int nqvecs;
1253        bool has_tx_irqs;
1254
1255        u32 tx_time_coal;
1256
1257        /* List of steering rules active on that port */
1258        struct mvpp2_ethtool_fs *rfs_rules[MVPP2_N_RFS_ENTRIES_PER_FLOW];
1259        int n_rfs_rules;
1260
1261        /* Each port has its own view of the rss contexts, so that it can number
1262         * them from 0
1263         */
1264        int rss_ctx[MVPP22_N_RSS_TABLES];
1265
1266        bool hwtstamp;
1267        bool rx_hwtstamp;
1268        enum hwtstamp_tx_types tx_hwtstamp_type;
1269        struct mvpp2_hwtstamp_queue tx_hwtstamp_queue[2];
1270
1271        /* Firmware TX flow control */
1272        bool tx_fc;
1273};
1274
1275/* The mvpp2_tx_desc and mvpp2_rx_desc structures describe the
1276 * layout of the transmit and reception DMA descriptors, and their
1277 * layout is therefore defined by the hardware design
1278 */
1279
1280#define MVPP2_TXD_L3_OFF_SHIFT          0
1281#define MVPP2_TXD_IP_HLEN_SHIFT         8
1282#define MVPP2_TXD_L4_CSUM_FRAG          BIT(13)
1283#define MVPP2_TXD_L4_CSUM_NOT           BIT(14)
1284#define MVPP2_TXD_IP_CSUM_DISABLE       BIT(15)
1285#define MVPP2_TXD_PADDING_DISABLE       BIT(23)
1286#define MVPP2_TXD_L4_UDP                BIT(24)
1287#define MVPP2_TXD_L3_IP6                BIT(26)
1288#define MVPP2_TXD_L_DESC                BIT(28)
1289#define MVPP2_TXD_F_DESC                BIT(29)
1290
1291#define MVPP2_RXD_ERR_SUMMARY           BIT(15)
1292#define MVPP2_RXD_ERR_CODE_MASK         (BIT(13) | BIT(14))
1293#define MVPP2_RXD_ERR_CRC               0x0
1294#define MVPP2_RXD_ERR_OVERRUN           BIT(13)
1295#define MVPP2_RXD_ERR_RESOURCE          (BIT(13) | BIT(14))
1296#define MVPP2_RXD_BM_POOL_ID_OFFS       16
1297#define MVPP2_RXD_BM_POOL_ID_MASK       (BIT(16) | BIT(17) | BIT(18))
1298#define MVPP2_RXD_HWF_SYNC              BIT(21)
1299#define MVPP2_RXD_L4_CSUM_OK            BIT(22)
1300#define MVPP2_RXD_IP4_HEADER_ERR        BIT(24)
1301#define MVPP2_RXD_L4_TCP                BIT(25)
1302#define MVPP2_RXD_L4_UDP                BIT(26)
1303#define MVPP2_RXD_L3_IP4                BIT(28)
1304#define MVPP2_RXD_L3_IP6                BIT(30)
1305#define MVPP2_RXD_BUF_HDR               BIT(31)
1306
1307/* HW TX descriptor for PPv2.1 */
1308struct mvpp21_tx_desc {
1309        __le32 command;         /* Options used by HW for packet transmitting.*/
1310        u8  packet_offset;      /* the offset from the buffer beginning */
1311        u8  phys_txq;           /* destination queue ID                 */
1312        __le16 data_size;       /* data size of transmitted packet in bytes */
1313        __le32 buf_dma_addr;    /* physical addr of transmitted buffer  */
1314        __le32 buf_cookie;      /* cookie for access to TX buffer in tx path */
1315        __le32 reserved1[3];    /* hw_cmd (for future use, BM, PON, PNC) */
1316        __le32 reserved2;       /* reserved (for future use)            */
1317};
1318
1319/* HW RX descriptor for PPv2.1 */
1320struct mvpp21_rx_desc {
1321        __le32 status;          /* info about received packet           */
1322        __le16 reserved1;       /* parser_info (for future use, PnC)    */
1323        __le16 data_size;       /* size of received packet in bytes     */
1324        __le32 buf_dma_addr;    /* physical address of the buffer       */
1325        __le32 buf_cookie;      /* cookie for access to RX buffer in rx path */
1326        __le16 reserved2;       /* gem_port_id (for future use, PON)    */
1327        __le16 reserved3;       /* csum_l4 (for future use, PnC)        */
1328        u8  reserved4;          /* bm_qset (for future use, BM)         */
1329        u8  reserved5;
1330        __le16 reserved6;       /* classify_info (for future use, PnC)  */
1331        __le32 reserved7;       /* flow_id (for future use, PnC) */
1332        __le32 reserved8;
1333};
1334
1335/* HW TX descriptor for PPv2.2 and PPv2.3 */
1336struct mvpp22_tx_desc {
1337        __le32 command;
1338        u8  packet_offset;
1339        u8  phys_txq;
1340        __le16 data_size;
1341        __le32 ptp_descriptor;
1342        __le32 reserved2;
1343        __le64 buf_dma_addr_ptp;
1344        __le64 buf_cookie_misc;
1345};
1346
1347/* HW RX descriptor for PPv2.2 and PPv2.3 */
1348struct mvpp22_rx_desc {
1349        __le32 status;
1350        __le16 reserved1;
1351        __le16 data_size;
1352        __le32 reserved2;
1353        __le32 timestamp;
1354        __le64 buf_dma_addr_key_hash;
1355        __le64 buf_cookie_misc;
1356};
1357
1358/* Opaque type used by the driver to manipulate the HW TX and RX
1359 * descriptors
1360 */
1361struct mvpp2_tx_desc {
1362        union {
1363                struct mvpp21_tx_desc pp21;
1364                struct mvpp22_tx_desc pp22;
1365        };
1366};
1367
1368struct mvpp2_rx_desc {
1369        union {
1370                struct mvpp21_rx_desc pp21;
1371                struct mvpp22_rx_desc pp22;
1372        };
1373};
1374
1375enum mvpp2_tx_buf_type {
1376        MVPP2_TYPE_SKB,
1377        MVPP2_TYPE_XDP_TX,
1378        MVPP2_TYPE_XDP_NDO,
1379};
1380
1381struct mvpp2_txq_pcpu_buf {
1382        enum mvpp2_tx_buf_type type;
1383
1384        /* Transmitted SKB */
1385        union {
1386                struct xdp_frame *xdpf;
1387                struct sk_buff *skb;
1388        };
1389
1390        /* Physical address of transmitted buffer */
1391        dma_addr_t dma;
1392
1393        /* Size transmitted */
1394        size_t size;
1395};
1396
1397/* Per-CPU Tx queue control */
1398struct mvpp2_txq_pcpu {
1399        unsigned int thread;
1400
1401        /* Number of Tx DMA descriptors in the descriptor ring */
1402        int size;
1403
1404        /* Number of currently used Tx DMA descriptor in the
1405         * descriptor ring
1406         */
1407        int count;
1408
1409        int wake_threshold;
1410        int stop_threshold;
1411
1412        /* Number of Tx DMA descriptors reserved for each CPU */
1413        int reserved_num;
1414
1415        /* Infos about transmitted buffers */
1416        struct mvpp2_txq_pcpu_buf *buffs;
1417
1418        /* Index of last TX DMA descriptor that was inserted */
1419        int txq_put_index;
1420
1421        /* Index of the TX DMA descriptor to be cleaned up */
1422        int txq_get_index;
1423
1424        /* DMA buffer for TSO headers */
1425        char *tso_headers;
1426        dma_addr_t tso_headers_dma;
1427};
1428
1429struct mvpp2_tx_queue {
1430        /* Physical number of this Tx queue */
1431        u8 id;
1432
1433        /* Logical number of this Tx queue */
1434        u8 log_id;
1435
1436        /* Number of Tx DMA descriptors in the descriptor ring */
1437        int size;
1438
1439        /* Number of currently used Tx DMA descriptor in the descriptor ring */
1440        int count;
1441
1442        /* Per-CPU control of physical Tx queues */
1443        struct mvpp2_txq_pcpu __percpu *pcpu;
1444
1445        u32 done_pkts_coal;
1446
1447        /* Virtual address of thex Tx DMA descriptors array */
1448        struct mvpp2_tx_desc *descs;
1449
1450        /* DMA address of the Tx DMA descriptors array */
1451        dma_addr_t descs_dma;
1452
1453        /* Index of the last Tx DMA descriptor */
1454        int last_desc;
1455
1456        /* Index of the next Tx DMA descriptor to process */
1457        int next_desc_to_proc;
1458};
1459
1460struct mvpp2_rx_queue {
1461        /* RX queue number, in the range 0-31 for physical RXQs */
1462        u8 id;
1463
1464        /* Num of rx descriptors in the rx descriptor ring */
1465        int size;
1466
1467        u32 pkts_coal;
1468        u32 time_coal;
1469
1470        /* Virtual address of the RX DMA descriptors array */
1471        struct mvpp2_rx_desc *descs;
1472
1473        /* DMA address of the RX DMA descriptors array */
1474        dma_addr_t descs_dma;
1475
1476        /* Index of the last RX DMA descriptor */
1477        int last_desc;
1478
1479        /* Index of the next RX DMA descriptor to process */
1480        int next_desc_to_proc;
1481
1482        /* ID of port to which physical RXQ is mapped */
1483        int port;
1484
1485        /* Port's logic RXQ number to which physical RXQ is mapped */
1486        int logic_rxq;
1487
1488        /* XDP memory accounting */
1489        struct xdp_rxq_info xdp_rxq_short;
1490        struct xdp_rxq_info xdp_rxq_long;
1491};
1492
1493struct mvpp2_bm_pool {
1494        /* Pool number in the range 0-7 */
1495        int id;
1496
1497        /* Buffer Pointers Pool External (BPPE) size */
1498        int size;
1499        /* BPPE size in bytes */
1500        int size_bytes;
1501        /* Number of buffers for this pool */
1502        int buf_num;
1503        /* Pool buffer size */
1504        int buf_size;
1505        /* Packet size */
1506        int pkt_size;
1507        int frag_size;
1508
1509        /* BPPE virtual base address */
1510        u32 *virt_addr;
1511        /* BPPE DMA base address */
1512        dma_addr_t dma_addr;
1513
1514        /* Ports using BM pool */
1515        u32 port_map;
1516};
1517
1518#define IS_TSO_HEADER(txq_pcpu, addr) \
1519        ((addr) >= (txq_pcpu)->tso_headers_dma && \
1520         (addr) < (txq_pcpu)->tso_headers_dma + \
1521         (txq_pcpu)->size * TSO_HEADER_SIZE)
1522
1523#define MVPP2_DRIVER_NAME "mvpp2"
1524#define MVPP2_DRIVER_VERSION "1.0"
1525
1526void mvpp2_write(struct mvpp2 *priv, u32 offset, u32 data);
1527u32 mvpp2_read(struct mvpp2 *priv, u32 offset);
1528
1529void mvpp2_dbgfs_init(struct mvpp2 *priv, const char *name);
1530
1531void mvpp2_dbgfs_cleanup(struct mvpp2 *priv);
1532
1533void mvpp23_rx_fifo_fc_en(struct mvpp2 *priv, int port, bool en);
1534
1535#ifdef CONFIG_MVPP2_PTP
1536int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv);
1537void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
1538                       struct skb_shared_hwtstamps *hwtstamp);
1539void mvpp22_tai_start(struct mvpp2_tai *tai);
1540void mvpp22_tai_stop(struct mvpp2_tai *tai);
1541int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai);
1542#else
1543static inline int mvpp22_tai_probe(struct device *dev, struct mvpp2 *priv)
1544{
1545        return 0;
1546}
1547static inline void mvpp22_tai_tstamp(struct mvpp2_tai *tai, u32 tstamp,
1548                                     struct skb_shared_hwtstamps *hwtstamp)
1549{
1550}
1551static inline void mvpp22_tai_start(struct mvpp2_tai *tai)
1552{
1553}
1554static inline void mvpp22_tai_stop(struct mvpp2_tai *tai)
1555{
1556}
1557static inline int mvpp22_tai_ptp_clock_index(struct mvpp2_tai *tai)
1558{
1559        return -1;
1560}
1561#endif
1562
1563static inline bool mvpp22_rx_hwtstamping(struct mvpp2_port *port)
1564{
1565        return IS_ENABLED(CONFIG_MVPP2_PTP) && port->rx_hwtstamp;
1566}
1567
1568#endif
1569