// SPDX-License-Identifier: GPL-2.0
/* Copyright (c)  2018 Intel Corporation */

#include <linux/module.h>
#include <linux/types.h>
#include <linux/if_vlan.h>
#include <linux/aer.h>
#include <linux/tcp.h>
#include <linux/udp.h>
#include <linux/ip.h>
#include <linux/pm_runtime.h>
#include <net/pkt_sched.h>
#include <linux/bpf_trace.h>
#include <net/xdp_sock_drv.h>
#include <net/ipv6.h>

#include "igc.h"
#include "igc_hw.h"
#include "igc_tsn.h"
#include "igc_xdp.h"

#define DRV_SUMMARY     "Intel(R) 2.5G Ethernet Linux Driver"

#define DEFAULT_MSG_ENABLE (NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK)

#define IGC_XDP_PASS            0
#define IGC_XDP_CONSUMED        BIT(0)
#define IGC_XDP_TX              BIT(1)
#define IGC_XDP_REDIRECT        BIT(2)

static int debug = -1;

MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
MODULE_DESCRIPTION(DRV_SUMMARY);
MODULE_LICENSE("GPL v2");
module_param(debug, int, 0);
MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");

char igc_driver_name[] = "igc";
static const char igc_driver_string[] = DRV_SUMMARY;
static const char igc_copyright[] =
        "Copyright(c) 2018 Intel Corporation.";

static const struct igc_info *igc_info_tbl[] = {
        [board_base] = &igc_base_info,
};

static const struct pci_device_id igc_pci_tbl[] = {
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LM), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_V), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_I), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I220_V), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_K2), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_K), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_LMVP), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_IT), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_LM), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_V), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_IT), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I221_V), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I226_BLANK_NVM), board_base },
        { PCI_VDEVICE(INTEL, IGC_DEV_ID_I225_BLANK_NVM), board_base },
        /* required last entry */
        {0, }
};

MODULE_DEVICE_TABLE(pci, igc_pci_tbl);

enum latency_range {
        lowest_latency = 0,
        low_latency = 1,
        bulk_latency = 2,
        latency_invalid = 255
};

void igc_reset(struct igc_adapter *adapter)
{
        struct net_device *dev = adapter->netdev;
        struct igc_hw *hw = &adapter->hw;
        struct igc_fc_info *fc = &hw->fc;
        u32 pba, hwm;

        /* Repartition PBA for greater than 9k MTU if required */
        pba = IGC_PBA_34K;

        /* flow control settings
         * The high water mark must be low enough to fit one full frame
         * after transmitting the pause frame.  As such we must have enough
         * space to allow for us to complete our current transmit and then
         * receive the frame that is in progress from the link partner.
         * Set it to:
         * - the full Rx FIFO size minus one full Tx plus one full Rx frame
         */
        hwm = (pba << 10) - (adapter->max_frame_size + MAX_JUMBO_FRAME_SIZE);

        fc->high_water = hwm & 0xFFFFFFF0;      /* 16-byte granularity */
        fc->low_water = fc->high_water - 16;
        fc->pause_time = 0xFFFF;
        fc->send_xon = 1;
        fc->current_mode = fc->requested_mode;

        hw->mac.ops.reset_hw(hw);

        if (hw->mac.ops.init_hw(hw))
                netdev_err(dev, "Error on hardware initialization\n");

        /* Re-establish EEE setting */
        igc_set_eee_i225(hw, true, true, true);

        if (!netif_running(adapter->netdev))
                igc_power_down_phy_copper_base(&adapter->hw);

        /* Enable HW to recognize an 802.1Q VLAN Ethernet packet */
        wr32(IGC_VET, ETH_P_8021Q);

        /* Re-enable PTP, where applicable. */
        igc_ptp_reset(adapter);

        /* Re-enable TSN offloading, where applicable. */
        igc_tsn_offload_apply(adapter);

        igc_get_phy_info(hw);
}

/**
 * igc_power_up_link - Power up the phy link
 * @adapter: address of board private structure
 */
static void igc_power_up_link(struct igc_adapter *adapter)
{
        igc_reset_phy(&adapter->hw);

        igc_power_up_phy_copper(&adapter->hw);

        igc_setup_link(&adapter->hw);
}

/**
 * igc_release_hw_control - release control of the h/w to f/w
 * @adapter: address of board private structure
 *
 * igc_release_hw_control resets CTRL_EXT:DRV_LOAD bit.
 * For ASF and Pass Through versions of f/w this means that the
 * driver is no longer loaded.
 */
static void igc_release_hw_control(struct igc_adapter *adapter)
{
        struct igc_hw *hw = &adapter->hw;
        u32 ctrl_ext;

        if (!pci_device_is_present(adapter->pdev))
                return;

        /* Let firmware take over control of h/w */
        ctrl_ext = rd32(IGC_CTRL_EXT);
        wr32(IGC_CTRL_EXT,
             ctrl_ext & ~IGC_CTRL_EXT_DRV_LOAD);
}

/**
 * igc_get_hw_control - get control of the h/w from f/w
 * @adapter: address of board private structure
 *
 * igc_get_hw_control sets CTRL_EXT:DRV_LOAD bit.
 * For ASF and Pass Through versions of f/w this means that
 * the driver is loaded.
 */
static void igc_get_hw_control(struct igc_adapter *adapter)
{
        struct igc_hw *hw = &adapter->hw;
        u32 ctrl_ext;

        /* Let firmware know the driver has taken over */
        ctrl_ext = rd32(IGC_CTRL_EXT);
        wr32(IGC_CTRL_EXT,
             ctrl_ext | IGC_CTRL_EXT_DRV_LOAD);
}

static void igc_unmap_tx_buffer(struct device *dev, struct igc_tx_buffer *buf)
{
        dma_unmap_single(dev, dma_unmap_addr(buf, dma),
                         dma_unmap_len(buf, len), DMA_TO_DEVICE);

        dma_unmap_len_set(buf, len, 0);
}

/**
 * igc_clean_tx_ring - Free Tx Buffers
 * @tx_ring: ring to be cleaned
 */
static void igc_clean_tx_ring(struct igc_ring *tx_ring)
{
        u16 i = tx_ring->next_to_clean;
        struct igc_tx_buffer *tx_buffer = &tx_ring->tx_buffer_info[i];
        u32 xsk_frames = 0;

        while (i != tx_ring->next_to_use) {
                union igc_adv_tx_desc *eop_desc, *tx_desc;

                switch (tx_buffer->type) {
                case IGC_TX_BUFFER_TYPE_XSK:
                        xsk_frames++;
                        break;
                case IGC_TX_BUFFER_TYPE_XDP:
                        xdp_return_frame(tx_buffer->xdpf);
                        igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
                        break;
                case IGC_TX_BUFFER_TYPE_SKB:
                        dev_kfree_skb_any(tx_buffer->skb);
                        igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
                        break;
                default:
                        netdev_warn_once(tx_ring->netdev, "Unknown Tx buffer type\n");
                        break;
                }

                /* check for eop_desc to determine the end of the packet */
                eop_desc = tx_buffer->next_to_watch;
                tx_desc = IGC_TX_DESC(tx_ring, i);

                /* unmap remaining buffers */
                while (tx_desc != eop_desc) {
                        tx_buffer++;
                        tx_desc++;
                        i++;
                        if (unlikely(i == tx_ring->count)) {
                                i = 0;
                                tx_buffer = tx_ring->tx_buffer_info;
                                tx_desc = IGC_TX_DESC(tx_ring, 0);
                        }

                        /* unmap any remaining paged data */
                        if (dma_unmap_len(tx_buffer, len))
                                igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);
                }

                tx_buffer->next_to_watch = NULL;

                /* move us one more past the eop_desc for start of next pkt */
                tx_buffer++;
                i++;
                if (unlikely(i == tx_ring->count)) {
                        i = 0;
                        tx_buffer = tx_ring->tx_buffer_info;
                }
        }

        if (tx_ring->xsk_pool && xsk_frames)
                xsk_tx_completed(tx_ring->xsk_pool, xsk_frames);

        /* reset BQL for queue */
        netdev_tx_reset_queue(txring_txq(tx_ring));

        /* reset next_to_use and next_to_clean */
        tx_ring->next_to_use = 0;
        tx_ring->next_to_clean = 0;
}

/**
 * igc_free_tx_resources - Free Tx Resources per Queue
 * @tx_ring: Tx descriptor ring for a specific queue
 *
 * Free all transmit software resources
 */
void igc_free_tx_resources(struct igc_ring *tx_ring)
{
        igc_clean_tx_ring(tx_ring);

        vfree(tx_ring->tx_buffer_info);
        tx_ring->tx_buffer_info = NULL;

        /* if not set, then don't free */
        if (!tx_ring->desc)
                return;

        dma_free_coherent(tx_ring->dev, tx_ring->size,
                          tx_ring->desc, tx_ring->dma);

        tx_ring->desc = NULL;
}

/**
 * igc_free_all_tx_resources - Free Tx Resources for All Queues
 * @adapter: board private structure
 *
 * Free all transmit software resources
 */
static void igc_free_all_tx_resources(struct igc_adapter *adapter)
{
        int i;

        for (i = 0; i < adapter->num_tx_queues; i++)
                igc_free_tx_resources(adapter->tx_ring[i]);
}

/**
 * igc_clean_all_tx_rings - Free Tx Buffers for all queues
 * @adapter: board private structure
 */
static void igc_clean_all_tx_rings(struct igc_adapter *adapter)
{
        int i;

        for (i = 0; i < adapter->num_tx_queues; i++)
                if (adapter->tx_ring[i])
                        igc_clean_tx_ring(adapter->tx_ring[i]);
}

/**
 * igc_setup_tx_resources - allocate Tx resources (Descriptors)
 * @tx_ring: tx descriptor ring (for a specific queue) to setup
 *
 * Return 0 on success, negative on failure
 */
int igc_setup_tx_resources(struct igc_ring *tx_ring)
{
        struct net_device *ndev = tx_ring->netdev;
        struct device *dev = tx_ring->dev;
        int size = 0;

        size = sizeof(struct igc_tx_buffer) * tx_ring->count;
        tx_ring->tx_buffer_info = vzalloc(size);
        if (!tx_ring->tx_buffer_info)
                goto err;

        /* round up to nearest 4K */
        tx_ring->size = tx_ring->count * sizeof(union igc_adv_tx_desc);
        tx_ring->size = ALIGN(tx_ring->size, 4096);

        tx_ring->desc = dma_alloc_coherent(dev, tx_ring->size,
                                           &tx_ring->dma, GFP_KERNEL);

        if (!tx_ring->desc)
                goto err;

        tx_ring->next_to_use = 0;
        tx_ring->next_to_clean = 0;

        return 0;

err:
        vfree(tx_ring->tx_buffer_info);
        netdev_err(ndev, "Unable to allocate memory for Tx descriptor ring\n");
        return -ENOMEM;
}

/**
 * igc_setup_all_tx_resources - wrapper to allocate Tx resources for all queues
 * @adapter: board private structure
 *
 * Return 0 on success, negative on failure
 */
static int igc_setup_all_tx_resources(struct igc_adapter *adapter)
{
        struct net_device *dev = adapter->netdev;
        int i, err = 0;

        for (i = 0; i < adapter->num_tx_queues; i++) {
                err = igc_setup_tx_resources(adapter->tx_ring[i]);
                if (err) {
                        netdev_err(dev, "Error on Tx queue %u setup\n", i);
                        for (i--; i >= 0; i--)
                                igc_free_tx_resources(adapter->tx_ring[i]);
                        break;
                }
        }

        return err;
}

static void igc_clean_rx_ring_page_shared(struct igc_ring *rx_ring)
{
        u16 i = rx_ring->next_to_clean;

        dev_kfree_skb(rx_ring->skb);
        rx_ring->skb = NULL;

        /* Free all the Rx ring sk_buffs */
        while (i != rx_ring->next_to_alloc) {
                struct igc_rx_buffer *buffer_info = &rx_ring->rx_buffer_info[i];

                /* Invalidate cache lines that may have been written to by
                 * device so that we avoid corrupting memory.
                 */
                dma_sync_single_range_for_cpu(rx_ring->dev,
                                              buffer_info->dma,
                                              buffer_info->page_offset,
                                              igc_rx_bufsz(rx_ring),
                                              DMA_FROM_DEVICE);

                /* free resources associated with mapping */
                dma_unmap_page_attrs(rx_ring->dev,
                                     buffer_info->dma,
                                     igc_rx_pg_size(rx_ring),
                                     DMA_FROM_DEVICE,
                                     IGC_RX_DMA_ATTR);
                __page_frag_cache_drain(buffer_info->page,
                                        buffer_info->pagecnt_bias);

                i++;
                if (i == rx_ring->count)
                        i = 0;
        }
}

static void igc_clean_rx_ring_xsk_pool(struct igc_ring *ring)
{
        struct igc_rx_buffer *bi;
        u16 i;

        for (i = 0; i < ring->count; i++) {
                bi = &ring->rx_buffer_info[i];
                if (!bi->xdp)
                        continue;

                xsk_buff_free(bi->xdp);
                bi->xdp = NULL;
        }
}

/**
 * igc_clean_rx_ring - Free Rx Buffers per Queue
 * @ring: ring to free buffers from
 */
static void igc_clean_rx_ring(struct igc_ring *ring)
{
        if (ring->xsk_pool)
                igc_clean_rx_ring_xsk_pool(ring);
        else
                igc_clean_rx_ring_page_shared(ring);

        clear_ring_uses_large_buffer(ring);

        ring->next_to_alloc = 0;
        ring->next_to_clean = 0;
        ring->next_to_use = 0;
}

/**
 * igc_clean_all_rx_rings - Free Rx Buffers for all queues
 * @adapter: board private structure
 */
static void igc_clean_all_rx_rings(struct igc_adapter *adapter)
{
        int i;

        for (i = 0; i < adapter->num_rx_queues; i++)
                if (adapter->rx_ring[i])
                        igc_clean_rx_ring(adapter->rx_ring[i]);
}

/**
 * igc_free_rx_resources - Free Rx Resources
 * @rx_ring: ring to clean the resources from
 *
 * Free all receive software resources
 */
void igc_free_rx_resources(struct igc_ring *rx_ring)
{
        igc_clean_rx_ring(rx_ring);

        xdp_rxq_info_unreg(&rx_ring->xdp_rxq);

        vfree(rx_ring->rx_buffer_info);
        rx_ring->rx_buffer_info = NULL;

        /* if not set, then don't free */
        if (!rx_ring->desc)
                return;

        dma_free_coherent(rx_ring->dev, rx_ring->size,
                          rx_ring->desc, rx_ring->dma);

        rx_ring->desc = NULL;
}

/**
 * igc_free_all_rx_resources - Free Rx Resources for All Queues
 * @adapter: board private structure
 *
 * Free all receive software resources
 */
static void igc_free_all_rx_resources(struct igc_adapter *adapter)
{
        int i;

        for (i = 0; i < adapter->num_rx_queues; i++)
                igc_free_rx_resources(adapter->rx_ring[i]);
}

/**
 * igc_setup_rx_resources - allocate Rx resources (Descriptors)
 * @rx_ring:    rx descriptor ring (for a specific queue) to setup
 *
 * Returns 0 on success, negative on failure
 */
int igc_setup_rx_resources(struct igc_ring *rx_ring)
{
        struct net_device *ndev = rx_ring->netdev;
        struct device *dev = rx_ring->dev;
        u8 index = rx_ring->queue_index;
        int size, desc_len, res;

        res = xdp_rxq_info_reg(&rx_ring->xdp_rxq, ndev, index,
                               rx_ring->q_vector->napi.napi_id);
        if (res < 0) {
                netdev_err(ndev, "Failed to register xdp_rxq index %u\n",
                           index);
                return res;
        }

        size = sizeof(struct igc_rx_buffer) * rx_ring->count;
        rx_ring->rx_buffer_info = vzalloc(size);
        if (!rx_ring->rx_buffer_info)
                goto err;

        desc_len = sizeof(union igc_adv_rx_desc);

        /* Round up to nearest 4K */
        rx_ring->size = rx_ring->count * desc_len;
        rx_ring->size = ALIGN(rx_ring->size, 4096);

        rx_ring->desc = dma_alloc_coherent(dev, rx_ring->size,
                                           &rx_ring->dma, GFP_KERNEL);

        if (!rx_ring->desc)
                goto err;

        rx_ring->next_to_alloc = 0;
        rx_ring->next_to_clean = 0;
        rx_ring->next_to_use = 0;

        return 0;

err:
        xdp_rxq_info_unreg(&rx_ring->xdp_rxq);
        vfree(rx_ring->rx_buffer_info);
        rx_ring->rx_buffer_info = NULL;
        netdev_err(ndev, "Unable to allocate memory for Rx descriptor ring\n");
        return -ENOMEM;
}

/**
 * igc_setup_all_rx_resources - wrapper to allocate Rx resources
 *                                (Descriptors) for all queues
 * @adapter: board private structure
 *
 * Return 0 on success, negative on failure
 */
static int igc_setup_all_rx_resources(struct igc_adapter *adapter)
{
        struct net_device *dev = adapter->netdev;
        int i, err = 0;

        for (i = 0; i < adapter->num_rx_queues; i++) {
                err = igc_setup_rx_resources(adapter->rx_ring[i]);
                if (err) {
                        netdev_err(dev, "Error on Rx queue %u setup\n", i);
                        for (i--; i >= 0; i--)
                                igc_free_rx_resources(adapter->rx_ring[i]);
                        break;
                }
        }

        return err;
}

static struct xsk_buff_pool *igc_get_xsk_pool(struct igc_adapter *adapter,
                                              struct igc_ring *ring)
{
        if (!igc_xdp_is_enabled(adapter) ||
            !test_bit(IGC_RING_FLAG_AF_XDP_ZC, &ring->flags))
                return NULL;

        return xsk_get_pool_from_qid(ring->netdev, ring->queue_index);
}

/**
 * igc_configure_rx_ring - Configure a receive ring after Reset
 * @adapter: board private structure
 * @ring: receive ring to be configured
 *
 * Configure the Rx unit of the MAC after a reset.
 */
static void igc_configure_rx_ring(struct igc_adapter *adapter,
                                  struct igc_ring *ring)
{
        struct igc_hw *hw = &adapter->hw;
        union igc_adv_rx_desc *rx_desc;
        int reg_idx = ring->reg_idx;
        u32 srrctl = 0, rxdctl = 0;
        u64 rdba = ring->dma;
        u32 buf_size;

        xdp_rxq_info_unreg_mem_model(&ring->xdp_rxq);
        ring->xsk_pool = igc_get_xsk_pool(adapter, ring);
        if (ring->xsk_pool) {
                WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
                                                   MEM_TYPE_XSK_BUFF_POOL,
                                                   NULL));
                xsk_pool_set_rxq_info(ring->xsk_pool, &ring->xdp_rxq);
        } else {
                WARN_ON(xdp_rxq_info_reg_mem_model(&ring->xdp_rxq,
                                                   MEM_TYPE_PAGE_SHARED,
                                                   NULL));
        }

        if (igc_xdp_is_enabled(adapter))
                set_ring_uses_large_buffer(ring);

        /* disable the queue */
        wr32(IGC_RXDCTL(reg_idx), 0);

        /* Set DMA base address registers */
        wr32(IGC_RDBAL(reg_idx),
             rdba & 0x00000000ffffffffULL);
        wr32(IGC_RDBAH(reg_idx), rdba >> 32);
        wr32(IGC_RDLEN(reg_idx),
             ring->count * sizeof(union igc_adv_rx_desc));

        /* initialize head and tail */
        ring->tail = adapter->io_addr + IGC_RDT(reg_idx);
        wr32(IGC_RDH(reg_idx), 0);
        writel(0, ring->tail);

        /* reset next-to- use/clean to place SW in sync with hardware */
        ring->next_to_clean = 0;
        ring->next_to_use = 0;

        if (ring->xsk_pool)
                buf_size = xsk_pool_get_rx_frame_size(ring->xsk_pool);
        else if (ring_uses_large_buffer(ring))
                buf_size = IGC_RXBUFFER_3072;
        else
                buf_size = IGC_RXBUFFER_2048;

        srrctl = IGC_RX_HDR_LEN << IGC_SRRCTL_BSIZEHDRSIZE_SHIFT;
        srrctl |= buf_size >> IGC_SRRCTL_BSIZEPKT_SHIFT;
        srrctl |= IGC_SRRCTL_DESCTYPE_ADV_ONEBUF;

        wr32(IGC_SRRCTL(reg_idx), srrctl);

        rxdctl |= IGC_RX_PTHRESH;
        rxdctl |= IGC_RX_HTHRESH << 8;
        rxdctl |= IGC_RX_WTHRESH << 16;

        /* initialize rx_buffer_info */
        memset(ring->rx_buffer_info, 0,
               sizeof(struct igc_rx_buffer) * ring->count);

        /* initialize Rx descriptor 0 */
        rx_desc = IGC_RX_DESC(ring, 0);
        rx_desc->wb.upper.length = 0;

        /* enable receive descriptor fetching */
        rxdctl |= IGC_RXDCTL_QUEUE_ENABLE;

        wr32(IGC_RXDCTL(reg_idx), rxdctl);
}

/**
 * igc_configure_rx - Configure receive Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Rx unit of the MAC after a reset.
 */
static void igc_configure_rx(struct igc_adapter *adapter)
{
        int i;

        /* Setup the HW Rx Head and Tail Descriptor Pointers and
         * the Base and Length of the Rx Descriptor Ring
         */
        for (i = 0; i < adapter->num_rx_queues; i++)
                igc_configure_rx_ring(adapter, adapter->rx_ring[i]);
}

/**
 * igc_configure_tx_ring - Configure transmit ring after Reset
 * @adapter: board private structure
 * @ring: tx ring to configure
 *
 * Configure a transmit ring after a reset.
 */
static void igc_configure_tx_ring(struct igc_adapter *adapter,
                                  struct igc_ring *ring)
{
        struct igc_hw *hw = &adapter->hw;
        int reg_idx = ring->reg_idx;
        u64 tdba = ring->dma;
        u32 txdctl = 0;

        ring->xsk_pool = igc_get_xsk_pool(adapter, ring);

        /* disable the queue */
        wr32(IGC_TXDCTL(reg_idx), 0);
        wrfl();
        mdelay(10);

        wr32(IGC_TDLEN(reg_idx),
             ring->count * sizeof(union igc_adv_tx_desc));
        wr32(IGC_TDBAL(reg_idx),
             tdba & 0x00000000ffffffffULL);
        wr32(IGC_TDBAH(reg_idx), tdba >> 32);

        ring->tail = adapter->io_addr + IGC_TDT(reg_idx);
        wr32(IGC_TDH(reg_idx), 0);
        writel(0, ring->tail);

        txdctl |= IGC_TX_PTHRESH;
        txdctl |= IGC_TX_HTHRESH << 8;
        txdctl |= IGC_TX_WTHRESH << 16;

        txdctl |= IGC_TXDCTL_QUEUE_ENABLE;
        wr32(IGC_TXDCTL(reg_idx), txdctl);
}

/**
 * igc_configure_tx - Configure transmit Unit after Reset
 * @adapter: board private structure
 *
 * Configure the Tx unit of the MAC after a reset.
 */
static void igc_configure_tx(struct igc_adapter *adapter)
{
        int i;

        for (i = 0; i < adapter->num_tx_queues; i++)
                igc_configure_tx_ring(adapter, adapter->tx_ring[i]);
}

/**
 * igc_setup_mrqc - configure the multiple receive queue control registers
 * @adapter: Board private structure
 */
static void igc_setup_mrqc(struct igc_adapter *adapter)
{
        struct igc_hw *hw = &adapter->hw;
        u32 j, num_rx_queues;
        u32 mrqc, rxcsum;
        u32 rss_key[10];

        netdev_rss_key_fill(rss_key, sizeof(rss_key));
        for (j = 0; j < 10; j++)
                wr32(IGC_RSSRK(j), rss_key[j]);

        num_rx_queues = adapter->rss_queues;

        if (adapter->rss_indir_tbl_init != num_rx_queues) {
                for (j = 0; j < IGC_RETA_SIZE; j++)
                        adapter->rss_indir_tbl[j] =
                        (j * num_rx_queues) / IGC_RETA_SIZE;
                adapter->rss_indir_tbl_init = num_rx_queues;
        }
        igc_write_rss_indir_tbl(adapter);

        /* Disable raw packet checksumming so that RSS hash is placed in
         * descriptor on writeback.  No need to enable TCP/UDP/IP checksum
         * offloads as they are enabled by default
         */
        rxcsum = rd32(IGC_RXCSUM);
        rxcsum |= IGC_RXCSUM_PCSD;

        /* Enable Receive Checksum Offload for SCTP */
        rxcsum |= IGC_RXCSUM_CRCOFL;

        /* Don't need to set TUOFL or IPOFL, they default to 1 */
        wr32(IGC_RXCSUM, rxcsum);

        /* Generate RSS hash based on packet types, TCP/UDP
         * port numbers and/or IPv4/v6 src and dst addresses
         */
        mrqc = IGC_MRQC_RSS_FIELD_IPV4 |
               IGC_MRQC_RSS_FIELD_IPV4_TCP |
               IGC_MRQC_RSS_FIELD_IPV6 |
               IGC_MRQC_RSS_FIELD_IPV6_TCP |
               IGC_MRQC_RSS_FIELD_IPV6_TCP_EX;

        if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV4_UDP)
                mrqc |= IGC_MRQC_RSS_FIELD_IPV4_UDP;
        if (adapter->flags & IGC_FLAG_RSS_FIELD_IPV6_UDP)
                mrqc |= IGC_MRQC_RSS_FIELD_IPV6_UDP;

        mrqc |= IGC_MRQC_ENABLE_RSS_MQ;

        wr32(IGC_MRQC, mrqc);
}

/**
 * igc_setup_rctl - configure the receive control registers
 * @adapter: Board private structure
 */
static void igc_setup_rctl(struct igc_adapter *adapter)
{
        struct igc_hw *hw = &adapter->hw;
        u32 rctl;

        rctl = rd32(IGC_RCTL);

        rctl &= ~(3 << IGC_RCTL_MO_SHIFT);
        rctl &= ~(IGC_RCTL_LBM_TCVR | IGC_RCTL_LBM_MAC);

        rctl |= IGC_RCTL_EN | IGC_RCTL_BAM | IGC_RCTL_RDMTS_HALF |
                (hw->mac.mc_filter_type << IGC_RCTL_MO_SHIFT);

        /* enable stripping of CRC. Newer features require
         * that the HW strips the CRC.
         */
        rctl |= IGC_RCTL_SECRC;

        /* disable store bad packets and clear size bits. */
        rctl &= ~(IGC_RCTL_SBP | IGC_RCTL_SZ_256);

        /* enable LPE to allow for reception of jumbo frames */
        rctl |= IGC_RCTL_LPE;

        /* disable queue 0 to prevent tail write w/o re-config */
        wr32(IGC_RXDCTL(0), 0);

        /* This is useful for sniffing bad packets. */
        if (adapter->netdev->features & NETIF_F_RXALL) {
                /* UPE and MPE will be handled by normal PROMISC logic
                 * in set_rx_mode
                 */
                rctl |= (IGC_RCTL_SBP | /* Receive bad packets */
                         IGC_RCTL_BAM | /* RX All Bcast Pkts */
                         IGC_RCTL_PMCF); /* RX All MAC Ctrl Pkts */

                rctl &= ~(IGC_RCTL_DPF | /* Allow filtered pause */
                          IGC_RCTL_CFIEN); /* Disable VLAN CFIEN Filter */
        }

        wr32(IGC_RCTL, rctl);
}

/**
 * igc_setup_tctl - configure the transmit control registers
 * @adapter: Board private structure
 */
static void igc_setup_tctl(struct igc_adapter *adapter)
{
        struct igc_hw *hw = &adapter->hw;
        u32 tctl;

        /* disable queue 0 which icould be enabled by default */
        wr32(IGC_TXDCTL(0), 0);

        /* Program the Transmit Control Register */
        tctl = rd32(IGC_TCTL);
        tctl &= ~IGC_TCTL_CT;
        tctl |= IGC_TCTL_PSP | IGC_TCTL_RTLC |
                (IGC_COLLISION_THRESHOLD << IGC_CT_SHIFT);

        /* Enable transmits */
        tctl |= IGC_TCTL_EN;

        wr32(IGC_TCTL, tctl);
}

/**
 * igc_set_mac_filter_hw() - Set MAC address filter in hardware
 * @adapter: Pointer to adapter where the filter should be set
 * @index: Filter index
 * @type: MAC address filter type (source or destination)
 * @addr: MAC address
 * @queue: If non-negative, queue assignment feature is enabled and frames
 *         matching the filter are enqueued onto 'queue'. Otherwise, queue
 *         assignment is disabled.
 */
static void igc_set_mac_filter_hw(struct igc_adapter *adapter, int index,
                                  enum igc_mac_filter_type type,
                                  const u8 *addr, int queue)
{
        struct net_device *dev = adapter->netdev;
        struct igc_hw *hw = &adapter->hw;
        u32 ral, rah;

        if (WARN_ON(index >= hw->mac.rar_entry_count))
                return;

        ral = le32_to_cpup((__le32 *)(addr));
        rah = le16_to_cpup((__le16 *)(addr + 4));

        if (type == IGC_MAC_FILTER_TYPE_SRC) {
                rah &= ~IGC_RAH_ASEL_MASK;
                rah |= IGC_RAH_ASEL_SRC_ADDR;
        }

        if (queue >= 0) {
                rah &= ~IGC_RAH_QSEL_MASK;
                rah |= (queue << IGC_RAH_QSEL_SHIFT);
                rah |= IGC_RAH_QSEL_ENABLE;
        }

        rah |= IGC_RAH_AV;

        wr32(IGC_RAL(index), ral);
        wr32(IGC_RAH(index), rah);

        netdev_dbg(dev, "MAC address filter set in HW: index %d", index);
}

/**
 * igc_clear_mac_filter_hw() - Clear MAC address filter in hardware
 * @adapter: Pointer to adapter where the filter should be cleared
 * @index: Filter index
 */
static void igc_clear_mac_filter_hw(struct igc_adapter *adapter, int index)
{
        struct net_device *dev = adapter->netdev;
        struct igc_hw *hw = &adapter->hw;

        if (WARN_ON(index >= hw->mac.rar_entry_count))
                return;

        wr32(IGC_RAL(index), 0);
        wr32(IGC_RAH(index), 0);

        netdev_dbg(dev, "MAC address filter cleared in HW: index %d", index);
}

/* Set default MAC address for the PF in the first RAR entry */
static void igc_set_default_mac_filter(struct igc_adapter *adapter)
{
        struct net_device *dev = adapter->netdev;
        u8 *addr = adapter->hw.mac.addr;

        netdev_dbg(dev, "Set default MAC address filter: address %pM", addr);

        igc_set_mac_filter_hw(adapter, 0, IGC_MAC_FILTER_TYPE_DST, addr, -1);
}

/**
 * igc_set_mac - Change the Ethernet Address of the NIC
 * @netdev: network interface device structure
 * @p: pointer to an address structure
 *
 * Returns 0 on success, negative on failure
 */
static int igc_set_mac(struct net_device *netdev, void *p)
{
        struct igc_adapter *adapter = netdev_priv(netdev);
        struct igc_hw *hw = &adapter->hw;
        struct sockaddr *addr = p;

        if (!is_valid_ether_addr(addr->sa_data))
                return -EADDRNOTAVAIL;

        memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
        memcpy(hw->mac.addr, addr->sa_data, netdev->addr_len);

        /* set the correct pool for the new PF MAC address in entry 0 */
        igc_set_default_mac_filter(adapter);

        return 0;
}

/**
 *  igc_write_mc_addr_list - write multicast addresses to MTA
 *  @netdev: network interface device structure
 *
 *  Writes multicast address list to the MTA hash table.
 *  Returns: -ENOMEM on failure
 *           0 on no addresses written
 *           X on writing X addresses to MTA
 **/
static int igc_write_mc_addr_list(struct net_device *netdev)
{
        struct igc_adapter *adapter = netdev_priv(netdev);
        struct igc_hw *hw = &adapter->hw;
        struct netdev_hw_addr *ha;
        u8  *mta_list;
        int i;

        if (netdev_mc_empty(netdev)) {
                /* nothing to program, so clear mc list */
                igc_update_mc_addr_list(hw, NULL, 0);
                return 0;
        }

        mta_list = kcalloc(netdev_mc_count(netdev), 6, GFP_ATOMIC);
        if (!mta_list)
                return -ENOMEM;

        /* The shared function expects a packed array of only addresses. */
        i = 0;
        netdev_for_each_mc_addr(ha, netdev)
                memcpy(mta_list + (i++ * ETH_ALEN), ha->addr, ETH_ALEN);

        igc_update_mc_addr_list(hw, mta_list, i);
        kfree(mta_list);

        return netdev_mc_count(netdev);
}

static __le32 igc_tx_launchtime(struct igc_adapter *adapter, ktime_t txtime)
{
        ktime_t cycle_time = adapter->cycle_time;
        ktime_t base_time = adapter->base_time;

        u32 launchtime;

        /* FIXME: when using ETF together with taprio, we may have a
         * case where 'delta' is larger than the cycle_time, this may
         * cause problems if we don't read the current value of
         * IGC_BASET, as the value writen into the launchtime
         * descriptor field may be misinterpreted.
         */
        div_s64_rem(ktime_sub_ns(txtime, base_time), cycle_time, &launchtime);

        return cpu_to_le32(launchtime);
}

static void igc_tx_ctxtdesc(struct igc_ring *tx_ring,
                            struct igc_tx_buffer *first,
                            u32 vlan_macip_lens, u32 type_tucmd,
                            u32 mss_l4len_idx)
{
        struct igc_adv_tx_context_desc *context_desc;
        u16 i = tx_ring->next_to_use;

        context_desc = IGC_TX_CTXTDESC(tx_ring, i);

        i++;
        tx_ring->next_to_use = (i < tx_ring->count) ? i : 0;

        /* set bits to identify this as an advanced context descriptor */
        type_tucmd |= IGC_TXD_CMD_DEXT | IGC_ADVTXD_DTYP_CTXT;

        /* For i225, context index must be unique per ring. */
        if (test_bit(IGC_RING_FLAG_TX_CTX_IDX, &tx_ring->flags))
                mss_l4len_idx |= tx_ring->reg_idx << 4;

        context_desc->vlan_macip_lens   = cpu_to_le32(vlan_macip_lens);
        context_desc->type_tucmd_mlhl   = cpu_to_le32(type_tucmd);
        context_desc->mss_l4len_idx     = cpu_to_le32(mss_l4len_idx);

        /* We assume there is always a valid Tx time available. Invalid times
         * should have been handled by the upper layers.
         */
        if (tx_ring->launchtime_enable) {
                struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);
                ktime_t txtime = first->skb->tstamp;

                skb_txtime_consumed(first->skb);
                context_desc->launch_time = igc_tx_launchtime(adapter,
                                                              txtime);
        } else {
                context_desc->launch_time = 0;
        }
}

static void igc_tx_csum(struct igc_ring *tx_ring, struct igc_tx_buffer *first)
{
        struct sk_buff *skb = first->skb;
        u32 vlan_macip_lens = 0;
        u32 type_tucmd = 0;

        if (skb->ip_summed != CHECKSUM_PARTIAL) {
csum_failed:
                if (!(first->tx_flags & IGC_TX_FLAGS_VLAN) &&
                    !tx_ring->launchtime_enable)
                        return;
                goto no_csum;
        }

        switch (skb->csum_offset) {
        case offsetof(struct tcphdr, check):
                type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;
                fallthrough;
        case offsetof(struct udphdr, check):
                break;
        case offsetof(struct sctphdr, checksum):
                /* validate that this is actually an SCTP request */
                if (skb_csum_is_sctp(skb)) {
                        type_tucmd = IGC_ADVTXD_TUCMD_L4T_SCTP;
                        break;
                }
                fallthrough;
        default:
                skb_checksum_help(skb);
                goto csum_failed;
        }

        /* update TX checksum flag */
        first->tx_flags |= IGC_TX_FLAGS_CSUM;
        vlan_macip_lens = skb_checksum_start_offset(skb) -
                          skb_network_offset(skb);
no_csum:
        vlan_macip_lens |= skb_network_offset(skb) << IGC_ADVTXD_MACLEN_SHIFT;
        vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;

        igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens, type_tucmd, 0);
}

static int __igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
{
        struct net_device *netdev = tx_ring->netdev;

        netif_stop_subqueue(netdev, tx_ring->queue_index);

        /* memory barriier comment */
        smp_mb();

        /* We need to check again in a case another CPU has just
         * made room available.
         */
        if (igc_desc_unused(tx_ring) < size)
                return -EBUSY;

        /* A reprieve! */
        netif_wake_subqueue(netdev, tx_ring->queue_index);

        u64_stats_update_begin(&tx_ring->tx_syncp2);
        tx_ring->tx_stats.restart_queue2++;
        u64_stats_update_end(&tx_ring->tx_syncp2);

        return 0;
}

static inline int igc_maybe_stop_tx(struct igc_ring *tx_ring, const u16 size)
{
        if (igc_desc_unused(tx_ring) >= size)
                return 0;
        return __igc_maybe_stop_tx(tx_ring, size);
}

#define IGC_SET_FLAG(_input, _flag, _result) \
        (((_flag) <= (_result)) ?                               \
         ((u32)((_input) & (_flag)) * ((_result) / (_flag))) :  \
         ((u32)((_input) & (_flag)) / ((_flag) / (_result))))

static u32 igc_tx_cmd_type(struct sk_buff *skb, u32 tx_flags)
{
        /* set type for advanced descriptor with frame checksum insertion */
        u32 cmd_type = IGC_ADVTXD_DTYP_DATA |
                       IGC_ADVTXD_DCMD_DEXT |
                       IGC_ADVTXD_DCMD_IFCS;

        /* set HW vlan bit if vlan is present */
        cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_VLAN,
                                 IGC_ADVTXD_DCMD_VLE);

        /* set segmentation bits for TSO */
        cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSO,
                                 (IGC_ADVTXD_DCMD_TSE));

        /* set timestamp bit if present */
        cmd_type |= IGC_SET_FLAG(tx_flags, IGC_TX_FLAGS_TSTAMP,
                                 (IGC_ADVTXD_MAC_TSTAMP));

        /* insert frame checksum */
        cmd_type ^= IGC_SET_FLAG(skb->no_fcs, 1, IGC_ADVTXD_DCMD_IFCS);

        return cmd_type;
}

static void igc_tx_olinfo_status(struct igc_ring *tx_ring,
                                 union igc_adv_tx_desc *tx_desc,
                                 u32 tx_flags, unsigned int paylen)
{
        u32 olinfo_status = paylen << IGC_ADVTXD_PAYLEN_SHIFT;

        /* insert L4 checksum */
        olinfo_status |= (tx_flags & IGC_TX_FLAGS_CSUM) *
                          ((IGC_TXD_POPTS_TXSM << 8) /
                          IGC_TX_FLAGS_CSUM);

        /* insert IPv4 checksum */
        olinfo_status |= (tx_flags & IGC_TX_FLAGS_IPV4) *
                          (((IGC_TXD_POPTS_IXSM << 8)) /
                          IGC_TX_FLAGS_IPV4);

        tx_desc->read.olinfo_status = cpu_to_le32(olinfo_status);
}

static int igc_tx_map(struct igc_ring *tx_ring,
                      struct igc_tx_buffer *first,
                      const u8 hdr_len)
{
        struct sk_buff *skb = first->skb;
        struct igc_tx_buffer *tx_buffer;
        union igc_adv_tx_desc *tx_desc;
        u32 tx_flags = first->tx_flags;
        skb_frag_t *frag;
        u16 i = tx_ring->next_to_use;
        unsigned int data_len, size;
        dma_addr_t dma;
        u32 cmd_type;

        cmd_type = igc_tx_cmd_type(skb, tx_flags);
        tx_desc = IGC_TX_DESC(tx_ring, i);

        igc_tx_olinfo_status(tx_ring, tx_desc, tx_flags, skb->len - hdr_len);

        size = skb_headlen(skb);
        data_len = skb->data_len;

        dma = dma_map_single(tx_ring->dev, skb->data, size, DMA_TO_DEVICE);

        tx_buffer = first;

        for (frag = &skb_shinfo(skb)->frags[0];; frag++) {
                if (dma_mapping_error(tx_ring->dev, dma))
                        goto dma_error;

                /* record length, and DMA address */
                dma_unmap_len_set(tx_buffer, len, size);
                dma_unmap_addr_set(tx_buffer, dma, dma);

                tx_desc->read.buffer_addr = cpu_to_le64(dma);

                while (unlikely(size > IGC_MAX_DATA_PER_TXD)) {
                        tx_desc->read.cmd_type_len =
                                cpu_to_le32(cmd_type ^ IGC_MAX_DATA_PER_TXD);

                        i++;
                        tx_desc++;
                        if (i == tx_ring->count) {
                                tx_desc = IGC_TX_DESC(tx_ring, 0);
                                i = 0;
                        }
                        tx_desc->read.olinfo_status = 0;

                        dma += IGC_MAX_DATA_PER_TXD;
                        size -= IGC_MAX_DATA_PER_TXD;

                        tx_desc->read.buffer_addr = cpu_to_le64(dma);
                }

                if (likely(!data_len))
                        break;

                tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type ^ size);

                i++;
                tx_desc++;
                if (i == tx_ring->count) {
                        tx_desc = IGC_TX_DESC(tx_ring, 0);
                        i = 0;
                }
                tx_desc->read.olinfo_status = 0;

                size = skb_frag_size(frag);
                data_len -= size;

                dma = skb_frag_dma_map(tx_ring->dev, frag, 0,
                                       size, DMA_TO_DEVICE);

                tx_buffer = &tx_ring->tx_buffer_info[i];
        }

        /* write last descriptor with RS and EOP bits */
        cmd_type |= size | IGC_TXD_DCMD;
        tx_desc->read.cmd_type_len = cpu_to_le32(cmd_type);

        netdev_tx_sent_queue(txring_txq(tx_ring), first->bytecount);

        /* set the timestamp */
        first->time_stamp = jiffies;

        skb_tx_timestamp(skb);

        /* Force memory writes to complete before letting h/w know there
         * are new descriptors to fetch.  (Only applicable for weak-ordered
         * memory model archs, such as IA-64).
         *
         * We also need this memory barrier to make certain all of the
         * status bits have been updated before next_to_watch is written.
         */
        wmb();

        /* set next_to_watch value indicating a packet is present */
        first->next_to_watch = tx_desc;

        i++;
        if (i == tx_ring->count)
                i = 0;

        tx_ring->next_to_use = i;

        /* Make sure there is space in the ring for the next send. */
        igc_maybe_stop_tx(tx_ring, DESC_NEEDED);

        if (netif_xmit_stopped(txring_txq(tx_ring)) || !netdev_xmit_more()) {
                writel(i, tx_ring->tail);
        }

        return 0;
dma_error:
        netdev_err(tx_ring->netdev, "TX DMA map failed\n");
        tx_buffer = &tx_ring->tx_buffer_info[i];

        /* clear dma mappings for failed tx_buffer_info map */
        while (tx_buffer != first) {
                if (dma_unmap_len(tx_buffer, len))
                        igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);

                if (i-- == 0)
                        i += tx_ring->count;
                tx_buffer = &tx_ring->tx_buffer_info[i];
        }

        if (dma_unmap_len(tx_buffer, len))
                igc_unmap_tx_buffer(tx_ring->dev, tx_buffer);

        dev_kfree_skb_any(tx_buffer->skb);
        tx_buffer->skb = NULL;

        tx_ring->next_to_use = i;

        return -1;
}

static int igc_tso(struct igc_ring *tx_ring,
                   struct igc_tx_buffer *first,
                   u8 *hdr_len)
{
        u32 vlan_macip_lens, type_tucmd, mss_l4len_idx;
        struct sk_buff *skb = first->skb;
        union {
                struct iphdr *v4;
                struct ipv6hdr *v6;
                unsigned char *hdr;
        } ip;
        union {
                struct tcphdr *tcp;
                struct udphdr *udp;
                unsigned char *hdr;
        } l4;
        u32 paylen, l4_offset;
        int err;

        if (skb->ip_summed != CHECKSUM_PARTIAL)
                return 0;

        if (!skb_is_gso(skb))
                return 0;

        err = skb_cow_head(skb, 0);
        if (err < 0)
                return err;

        ip.hdr = skb_network_header(skb);
        l4.hdr = skb_checksum_start(skb);

        /* ADV DTYP TUCMD MKRLOC/ISCSIHEDLEN */
        type_tucmd = IGC_ADVTXD_TUCMD_L4T_TCP;

        /* initialize outer IP header fields */
        if (ip.v4->version == 4) {
                unsigned char *csum_start = skb_checksum_start(skb);
                unsigned char *trans_start = ip.hdr + (ip.v4->ihl * 4);

                /* IP header will have to cancel out any data that
                 * is not a part of the outer IP header
                 */
                ip.v4->check = csum_fold(csum_partial(trans_start,
                                                      csum_start - trans_start,
                                                      0));
                type_tucmd |= IGC_ADVTXD_TUCMD_IPV4;

                ip.v4->tot_len = 0;
                first->tx_flags |= IGC_TX_FLAGS_TSO |
                                   IGC_TX_FLAGS_CSUM |
                                   IGC_TX_FLAGS_IPV4;
        } else {
                ip.v6->payload_len = 0;
                first->tx_flags |= IGC_TX_FLAGS_TSO |
                                   IGC_TX_FLAGS_CSUM;
        }

        /* determine offset of inner transport header */
        l4_offset = l4.hdr - skb->data;

        /* remove payload length from inner checksum */
        paylen = skb->len - l4_offset;
        if (type_tucmd & IGC_ADVTXD_TUCMD_L4T_TCP) {
                /* compute length of segmentation header */
                *hdr_len = (l4.tcp->doff * 4) + l4_offset;
                csum_replace_by_diff(&l4.tcp->check,
                                     (__force __wsum)htonl(paylen));
        } else {
                /* compute length of segmentation header */
                *hdr_len = sizeof(*l4.udp) + l4_offset;
                csum_replace_by_diff(&l4.udp->check,
                                     (__force __wsum)htonl(paylen));
        }

        /* update gso size and bytecount with header size */
        first->gso_segs = skb_shinfo(skb)->gso_segs;
        first->bytecount += (first->gso_segs - 1) * *hdr_len;

        /* MSS L4LEN IDX */
        mss_l4len_idx = (*hdr_len - l4_offset) << IGC_ADVTXD_L4LEN_SHIFT;
        mss_l4len_idx |= skb_shinfo(skb)->gso_size << IGC_ADVTXD_MSS_SHIFT;

        /* VLAN MACLEN IPLEN */
        vlan_macip_lens = l4.hdr - ip.hdr;
        vlan_macip_lens |= (ip.hdr - skb->data) << IGC_ADVTXD_MACLEN_SHIFT;
        vlan_macip_lens |= first->tx_flags & IGC_TX_FLAGS_VLAN_MASK;

        igc_tx_ctxtdesc(tx_ring, first, vlan_macip_lens,
                        type_tucmd, mss_l4len_idx);

        return 1;
}

static netdev_tx_t igc_xmit_frame_ring(struct sk_buff *skb,
                                       struct igc_ring *tx_ring)
{
        u16 count = TXD_USE_COUNT(skb_headlen(skb));
        __be16 protocol = vlan_get_protocol(skb);
        struct igc_tx_buffer *first;
        u32 tx_flags = 0;
        unsigned short f;
        u8 hdr_len = 0;
        int tso = 0;

        /* need: 1 descriptor per page * PAGE_SIZE/IGC_MAX_DATA_PER_TXD,
         *      + 1 desc for skb_headlen/IGC_MAX_DATA_PER_TXD,
         *      + 2 desc gap to keep tail from touching head,
         *      + 1 desc for context descriptor,
         * otherwise try next time
         */
        for (f = 0; f < skb_shinfo(skb)->nr_frags; f++)
                count += TXD_USE_COUNT(skb_frag_size(
                                                &skb_shinfo(skb)->frags[f]));

        if (igc_maybe_stop_tx(tx_ring, count + 3)) {
                /* this is a hard error */
                return NETDEV_TX_BUSY;
        }

        /* record the location of the first descriptor for this packet */
        first = &tx_ring->tx_buffer_info[tx_ring->next_to_use];
        first->type = IGC_TX_BUFFER_TYPE_SKB;
        first->skb = skb;
        first->bytecount = skb->len;
        first->gso_segs = 1;

        if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)) {
                struct igc_adapter *adapter = netdev_priv(tx_ring->netdev);

                /* FIXME: add support for retrieving timestamps from
                 * the other timer registers before skipping the
                 * timestamping request.
                 */
                if (adapter->tstamp_config.tx_type == HWTSTAMP_TX_ON &&
                    !test_and_set_bit_lock(__IGC_PTP_TX_IN_PROGRESS,
                                           &adapter->state)) {
                        skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
                        tx_flags |= IGC_TX_FLAGS_TSTAMP;

                        adapter->ptp_tx_skb = skb_get(skb);
                        adapter->ptp_tx_start = jiffies;
                } else {
                        adapter->tx_hwtstamp_skipped++;
                }
        }

        if (skb_vlan_tag_present(skb)) {
                tx_flags |= IGC_TX_FLAGS_VLAN;
                tx_flags |= (skb_vlan_tag_get(skb) << IGC_TX_FLAGS_VLAN_SHIFT);
        }

        /* record initial flags and protocol */
        first->tx_flags = tx_flags;
        first->protocol = protocol;

        tso = igc_tso(tx_ring, first, &hdr_len);
        if (tso < 0)
                goto out_drop;
        else if (!tso)
                igc_tx_csum(tx_ring, first);

        igc_tx_map(tx_ring, first, hdr_len);

        return NETDEV_TX_OK;

out_drop:
        dev_kfree_skb_any(first->skb);
        first->skb = NULL;

        return NETDEV_TX_OK;
}

static inline struct igc_ring *igc_tx_queue_mapping(struct igc_adapter *adapter,
                                                    struct sk_buff *skb)
{
        unsigned int r_idx = skb->queue_mapping;

        if (r_idx >= adapter->num_tx_queues)
                r_idx = r_idx % adapter->num_tx_queues;

        return adapter->tx_ring[r_idx];
}

static netdev_tx_t igc_xmit_frame(struct sk_buff *skb,
                                  struct net_device *netdev)
{
        struct igc_adapter *adapter = netdev_priv(netdev);

        /* The minimum packet size with TCTL.PSP set is 17 so pad the skb
         * in order to meet this minimum size requirement.
         */
        if (skb->len < 17) {
                if (skb_padto(skb, 17))
                        return NETDEV_TX_OK;
                skb->len = 17;
        }

        return igc_xmit_frame_ring(skb, igc_tx_queue_mapping(adapter, skb));
}

static void igc_rx_checksum(struct igc_ring *ring,
                            union igc_adv_rx_desc *rx_desc,
                            struct sk_buff *skb)
{
        skb_checksum_none_assert(skb);

        /* Ignore Checksum bit is set */
        if (igc_test_staterr(rx_desc, IGC_RXD_STAT_IXSM))
                return;

        /* Rx checksum disabled via ethtool */
        if (!(ring->netdev->features & NETIF_F_RXCSUM))
                return;

        /* TCP/UDP checksum error bit is set */
        if (igc_test_staterr(rx_desc,
                             IGC_RXDEXT_STATERR_L4E |
                             IGC_RXDEXT_STATERR_IPE)) {
                /* work around errata with sctp packets where the TCPE aka
                 * L4E bit is set incorrectly on 64 byte (60 byte w/o crc)
                 * packets (aka let the stack check the crc32c)
                 */
                if (!(skb->len == 60 &&
                      test_bit(IGC_RING_FLAG_RX_SCTP_CSUM, &ring->flags))) {
                        u64_stats_update_begin(&ring->rx_syncp);
                        ring->rx_stats.csum_err++;
                        u64_stats_update_end(&ring->rx_syncp);
                }
                /* let the stack verify checksum errors */
                return;
        }
        /* It must be a TCP or UDP packet with a valid checksum */
        if (igc_test_staterr(rx_desc, IGC_RXD_STAT_TCPCS |
                                      IGC_RXD_STAT_UDPCS))
                skb->ip_summed = CHECKSUM_UNNECESSARY;

        netdev_dbg(ring->netdev, "cksum success: bits %08X\n",
                   le32_to_cpu(rx_desc->wb.upper.status_error));
}

static inline void igc_rx_hash(struct igc_ring *ring,
                               union igc_adv_rx_desc *rx_desc,
                               struct sk_buff *skb)
{
        if (ring->netdev->features & NETIF_F_RXHASH)
                skb_set_hash(skb,
                             le32_to_cpu(rx_desc->wb.lower.hi_dword.rss),
                             PKT_HASH_TYPE_L3);
}

static void igc_rx_vlan(struct igc_ring *rx_ring,
                        union igc_adv_rx_desc *rx_desc,
                        struct sk_buff *skb)
{
        struct net_device *dev = rx_ring->netdev;
        u16 vid;

        if ((dev->features & NETIF_F_HW_VLAN_CTAG_RX) &&
            igc_test_staterr(rx_desc, IGC_RXD_STAT_VP)) {
                if (igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_LB) &&
                    test_bit(IGC_RING_FLAG_RX_LB_VLAN_BSWAP, &rx_ring->flags))
                        vid = be16_to_cpu((__force __be16)rx_desc->wb.upper.vlan);
                else
                        vid = le16_to_cpu(rx_desc->wb.upper.vlan);

                __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vid);
        }
}

/**
 * igc_process_skb_fields - Populate skb header fields from Rx descriptor
 * @rx_ring: rx descriptor ring packet is being transacted on
 * @rx_desc: pointer to the EOP Rx descriptor
 * @skb: pointer to current skb being populated
 *
 * This function checks the ring, descriptor, and packet information in order
 * to populate the hash, checksum, VLAN, protocol, and other fields within the
 * skb.
 */
static void igc_process_skb_fields(struct igc_ring *rx_ring,
                                   union igc_adv_rx_desc *rx_desc,
                                   struct sk_buff *skb)
{
        igc_rx_hash(rx_ring, rx_desc, skb);

        igc_rx_checksum(rx_ring, rx_desc, skb);

        igc_rx_vlan(rx_ring, rx_desc, skb);

        skb_record_rx_queue(skb, rx_ring->queue_index);

        skb->protocol = eth_type_trans(skb, rx_ring->netdev);
}

static void igc_vlan_mode(struct net_device *netdev, netdev_features_t features)
{
        bool enable = !!(features & NETIF_F_HW_VLAN_CTAG_RX);
        struct igc_adapter *adapter = netdev_priv(netdev);
        struct igc_hw *hw = &adapter->hw;
        u32 ctrl;

        ctrl = rd32(IGC_CTRL);

        if (enable) {
                /* enable VLAN tag insert/strip */
                ctrl |= IGC_CTRL_VME;
        } else {
                /* disable VLAN tag insert/strip */
                ctrl &= ~IGC_CTRL_VME;
        }
        wr32(IGC_CTRL, ctrl);
}

static void igc_restore_vlan(struct igc_adapter *adapter)
{
        igc_vlan_mode(adapter->netdev, adapter->netdev->features);
}

static struct igc_rx_buffer *igc_get_rx_buffer(struct igc_ring *rx_ring,
                                               const unsigned int size,
                                               int *rx_buffer_pgcnt)
{
        struct igc_rx_buffer *rx_buffer;

        rx_buffer = &rx_ring->rx_buffer_info[rx_ring->next_to_clean];
        *rx_buffer_pgcnt =
#if (PAGE_SIZE < 8192)
                page_count(rx_buffer->page);
#else
                0;
#endif
        prefetchw(rx_buffer->page);

        /* we are reusing so sync this buffer for CPU use */
        dma_sync_single_range_for_cpu(rx_ring->dev,
                                      rx_buffer->dma,
                                      rx_buffer->page_offset,
                                      size,
                                      DMA_FROM_DEVICE);

        rx_buffer->pagecnt_bias--;

        return rx_buffer;
}

static void igc_rx_buffer_flip(struct igc_rx_buffer *buffer,
                               unsigned int truesize)
{
#if (PAGE_SIZE < 8192)
        buffer->page_offset ^= truesize;
#else
        buffer->page_offset += truesize;
#endif
}

static unsigned int igc_get_rx_frame_truesize(struct igc_ring *ring,
                                              unsigned int size)
{
        unsigned int truesize;

#if (PAGE_SIZE < 8192)
        truesize = igc_rx_pg_size(ring) / 2;
#else
        truesize = ring_uses_build_skb(ring) ?
                   SKB_DATA_ALIGN(sizeof(struct skb_shared_info)) +
                   SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
                   SKB_DATA_ALIGN(size);
#endif
        return truesize;
}

/**
 * igc_add_rx_frag - Add contents of Rx buffer to sk_buff
 * @rx_ring: rx descriptor ring to transact packets on
 * @rx_buffer: buffer containing page to add
 * @skb: sk_buff to place the data into
 * @size: size of buffer to be added
 *
 * This function will add the data contained in rx_buffer->page to the skb.
 */
static void igc_add_rx_frag(struct igc_ring *rx_ring,
                            struct igc_rx_buffer *rx_buffer,
                            struct sk_buff *skb,
                            unsigned int size)
{
        unsigned int truesize;

#if (PAGE_SIZE < 8192)
        truesize = igc_rx_pg_size(rx_ring) / 2;
#else
        truesize = ring_uses_build_skb(rx_ring) ?
                   SKB_DATA_ALIGN(IGC_SKB_PAD + size) :
                   SKB_DATA_ALIGN(size);
#endif
        skb_add_rx_frag(skb, skb_shinfo(skb)->nr_frags, rx_buffer->page,
                        rx_buffer->page_offset, size, truesize);

        igc_rx_buffer_flip(rx_buffer, truesize);
}

static struct sk_buff *igc_build_skb(struct igc_ring *rx_ring,
                                     struct igc_rx_buffer *rx_buffer,
                                     union igc_adv_rx_desc *rx_desc,
                                     unsigned int size)
{
        void *va = page_address(rx_buffer->page) + rx_buffer->page_offset;
        unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
        struct sk_buff *skb;

        /* prefetch first cache line of first page */
        net_prefetch(va);

        /* build an skb around the page buffer */
        skb = build_skb(va - IGC_SKB_PAD, truesize);
        if (unlikely(!skb))
                return NULL;

        /* update pointers within the skb to store the data */
        skb_reserve(skb, IGC_SKB_PAD);
        __skb_put(skb, size);

        igc_rx_buffer_flip(rx_buffer, truesize);
        return skb;
}

static struct sk_buff *igc_construct_skb(struct igc_ring *rx_ring,
                                         struct igc_rx_buffer *rx_buffer,
                                         struct xdp_buff *xdp,
                                         ktime_t timestamp)
{
        unsigned int size = xdp->data_end - xdp->data;
        unsigned int truesize = igc_get_rx_frame_truesize(rx_ring, size);
        void *va = xdp->data;
        unsigned int headlen;
        struct sk_buff *skb;

        /* prefetch first cache line of first page */
        net_prefetch(va);

        /* allocate a skb to store the frags */
        skb = napi_alloc_skb(&rx_ring->q_vector->napi, IGC_RX_HDR_LEN);
        if (unlikely(!skb))
                return NULL;

        if (timestamp)
                skb_hwtstamps(skb)->hwtstamp = timestamp;

        /* Determine available headroom for copy */
        headlen = size;
        if (headlen > IGC_RX_HDR_LEN)
                headlen = eth_get_headlen(skb->dev, va, IGC_RX_HDR_LEN);

        /* align pull length to size of long to optimize memcpy performance */
        memcpy(__skb_put(skb, headlen), va, ALIGN(headlen, sizeof(long)));

        /* update all of the pointers */
        size -= headlen;
        if (size) {
                skb_add_rx_frag(skb, 0, rx_buffer->page,
                                (va + headlen) - page_address(rx_buffer->page),
                                size, truesize);
                igc_rx_buffer_flip(rx_buffer, truesize);
        } else {
                rx_buffer->pagecnt_bias++;
        }

        return skb;
}

/**
 * igc_reuse_rx_page - page flip buffer and store it back on the ring
 * @rx_ring: rx descriptor ring to store buffers on
 * @old_buff: donor buffer to have page reused
 *
 * Synchronizes page for reuse by the adapter
 */
static void igc_reuse_rx_page(struct igc_ring *rx_ring,
                              struct igc_rx_buffer *old_buff)
{
        u16 nta = rx_ring->next_to_alloc;
        struct igc_rx_buffer *new_buff;

        new_buff = &rx_ring->rx_buffer_info[nta];

        /* update, and store next to alloc */
        nta++;
        rx_ring->next_to_alloc = (nta < rx_ring->count) ? nta : 0;

        /* Transfer page from old buffer to new buffer.
         * Move each member individually to avoid possible store
         * forwarding stalls.
         */
        new_buff->dma           = old_buff->dma;
        new_buff->page          = old_buff->page;
        new_buff->page_offset   = old_buff->page_offset;
        new_buff->pagecnt_bias  = old_buff->pagecnt_bias;
}

static bool igc_can_reuse_rx_page(struct igc_rx_buffer *rx_buffer,
                                  int rx_buffer_pgcnt)
{
        unsigned int pagecnt_bias = rx_buffer->pagecnt_bias;
        struct page *page = rx_buffer->page;

        /* avoid re-using remote and pfmemalloc pages */
        if (!dev_page_is_reusable(page))
                return false;

#if (PAGE_SIZE < 8192)
        /* if we are only owner of page we can reuse it */
        if (unlikely((rx_buffer_pgcnt - pagecnt_bias) > 1))
                return false;
#else
#define IGC_LAST_OFFSET \
        (SKB_WITH_OVERHEAD(PAGE_SIZE) - IGC_RXBUFFER_2048)

        if (rx_buffer->page_offset > IGC_LAST_OFFSET)
                return false;
#endif

        /* If we have drained the page fragment pool we need to update
         * the pagecnt_bias and page count so that we fully restock the
         * number of references the driver holds.
         */
        if (unlikely(pagecnt_bias == 1)) {
                page_ref_add(page, USHRT_MAX - 1);
                rx_buffer->pagecnt_bias = USHRT_MAX;
        }

        return true;
}

/**
 * igc_is_non_eop - process handling of non-EOP buffers
 * @rx_ring: Rx ring being processed
 * @rx_desc: Rx descriptor for current buffer
 *
 * This function updates next to clean.  If the buffer is an EOP buffer
 * this function exits returning false, otherwise it will place the
 * sk_buff in the next buffer to be chained and return true indicating
 * that this is in fact a non-EOP buffer.
 */
static bool igc_is_non_eop(struct igc_ring *rx_ring,
                           union igc_adv_rx_desc *rx_desc)
{
        u32 ntc = rx_ring->next_to_clean + 1;

        /* fetch, update, and store next to clean */
        ntc = (ntc < rx_ring->count) ? ntc : 0;
        rx_ring->next_to_clean = ntc;

        prefetch(IGC_RX_DESC(rx_ring, ntc));

        if (likely(igc_test_staterr(rx_desc, IGC_RXD_STAT_EOP)))
                return false;

        return true;
}

/**
 * igc_cleanup_headers - Correct corrupted or empty headers
 * @rx_ring: rx descriptor ring packet is being transacted on
 * @rx_desc: pointer to the EOP Rx descriptor
 * @skb: pointer to current skb being fixed
 *
 * Address the case where we are pulling data in on pages only
 * and as such no data is present in the skb header.
 *
 * In addition if skb is not at least 60 bytes we need to pad it so that
 * it is large enough to qualify as a valid Ethernet frame.
 *
 * Returns true if an error was encountered and skb was freed.
 */
static bool igc_cleanup_headers(struct igc_ring *rx_ring,
                                union igc_adv_rx_desc *rx_desc,
                                struct sk_buff *skb)
{
        /* XDP packets use error pointer so abort at this point */
        if (IS_ERR(skb))
                return true;

        if (unlikely(igc_test_staterr(rx_desc, IGC_RXDEXT_STATERR_RXE))) {
                struct net_device *netdev = rx_ring->netdev;

                if (!(netdev->features & NETIF_F_RXALL)) {
                        dev_kfree_skb_any(skb);
                        return true;
                }
        }

        /* if eth_skb_pad returns an error the skb was freed */
        if (eth_skb_pad(skb))
                return true;

        return false;
}

static void igc_put_rx_buffer(struct igc_ring *rx_ring,
                              struct igc_rx_buffer *rx_buffer,
                              int rx_buffer_pgcnt)
{
        if (igc_can_reuse_rx_page(rx_buffer, rx_buffer_pgcnt)) {
                /* hand second half of page back to the ring */
                igc_reuse_rx_page(rx_ring, rx_buffer);
        } else {
                /* We are not reusing the buffer so unmap it and free
                 * any references we are holding to it
                 */
                dma_unmap_page_attrs(rx_ring->dev, rx_buffer->dma,
                                     igc_rx_pg_size(rx_ring), DMA_FROM_DEVICE,
                                     IGC_RX_DMA_ATTR);
                __page_frag_cache_drain(rx_buffer->page,
                                        rx_buffer->pagecnt_bias);
        }

        /* clear contents of rx_buffer */
        rx_buffer->page = NULL;
}

static inline unsigned int igc_rx_offset(struct igc_ring *rx_ring)
{
        struct igc_adapter *adapter = rx_ring->q_vector->adapter;

        if (ring_uses_build_skb(rx_ring))
                return IGC_SKB_PAD;
        if (igc_xdp_is_enabled(adapter))
                return XDP_PACKET_HEADROOM;

        return 0;
}

static bool igc_alloc_mapped_page(struct igc_ring *rx_ring,
                                  struct igc_rx_buffer *bi)
{
        struct page *page = bi->page;
        dma_addr_t dma;

        /* since we are recycling buffers we should seldom need to alloc */
        if (likely(page))
                return true;

        /* alloc new page for storage */
        page = dev_alloc_pages(igc_rx_pg_order(rx_ring));
        if (unlikely(!page)) {
                rx_ring->rx_stats.alloc_failed++;
                return false;
        }

        /* map page for use */
        dma = dma_map_page_attrs(rx_ring->dev, page, 0,
                                 igc_rx_pg_size(rx_ring),
                                 DMA_FROM_DEVICE,
                                 IGC_RX_DMA_ATTR);

        /* if mapping failed free memory back to system since
         * there isn't much point in holding memory we can't use
         */
        if (dma_mapping_error(rx_ring->dev, dma)) {
                __free_page(page);

                rx_ring->rx_stats.alloc_failed++;
                return false;
        }

        bi->dma = dma;
        bi->page = page;
        bi->page_offset = igc_rx_offset(rx_ring);
        page_ref_add(page, USHRT_MAX - 1);
        bi->pagecnt_bias = USHRT_MAX;

        return true;
}

/**
 * igc_alloc_rx_buffers - Replace used receive buffers; packet split
 * @rx_ring: rx descriptor ring
 * @cleaned_count: number of buffers to clean
 */
static void igc_alloc_rx_buffers(struct igc_ring *rx_ring, u16 cleaned_count)
{
        union igc_adv_rx_desc *rx_desc;
        u16 i = rx_ring->next_to_use;
        struct igc_rx_buffer *bi;
        u16 bufsz;