linux/drivers/net/ethernet/intel/igc/igc_defines.h
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   1/* SPDX-License-Identifier: GPL-2.0 */
   2/* Copyright (c)  2018 Intel Corporation */
   3
   4#ifndef _IGC_DEFINES_H_
   5#define _IGC_DEFINES_H_
   6
   7/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
   8#define REQ_TX_DESCRIPTOR_MULTIPLE      8
   9#define REQ_RX_DESCRIPTOR_MULTIPLE      8
  10
  11#define IGC_CTRL_EXT_SDP2_DIR   0x00000400 /* SDP2 Data direction */
  12#define IGC_CTRL_EXT_SDP3_DIR   0x00000800 /* SDP3 Data direction */
  13#define IGC_CTRL_EXT_DRV_LOAD   0x10000000 /* Drv loaded bit for FW */
  14
  15/* Definitions for power management and wakeup registers */
  16/* Wake Up Control */
  17#define IGC_WUC_PME_EN  0x00000002 /* PME Enable */
  18
  19/* Wake Up Filter Control */
  20#define IGC_WUFC_LNKC   0x00000001 /* Link Status Change Wakeup Enable */
  21#define IGC_WUFC_MAG    0x00000002 /* Magic Packet Wakeup Enable */
  22#define IGC_WUFC_EX     0x00000004 /* Directed Exact Wakeup Enable */
  23#define IGC_WUFC_MC     0x00000008 /* Directed Multicast Wakeup Enable */
  24#define IGC_WUFC_BC     0x00000010 /* Broadcast Wakeup Enable */
  25
  26#define IGC_CTRL_ADVD3WUC       0x00100000  /* D3 WUC */
  27
  28/* Wake Up Status */
  29#define IGC_WUS_EX      0x00000004 /* Directed Exact */
  30#define IGC_WUS_ARPD    0x00000020 /* Directed ARP Request */
  31#define IGC_WUS_IPV4    0x00000040 /* Directed IPv4 */
  32#define IGC_WUS_IPV6    0x00000080 /* Directed IPv6 */
  33#define IGC_WUS_NSD     0x00000400 /* Directed IPv6 Neighbor Solicitation */
  34
  35/* Packet types that are enabled for wake packet delivery */
  36#define WAKE_PKT_WUS ( \
  37        IGC_WUS_EX   | \
  38        IGC_WUS_ARPD | \
  39        IGC_WUS_IPV4 | \
  40        IGC_WUS_IPV6 | \
  41        IGC_WUS_NSD)
  42
  43/* Wake Up Packet Length */
  44#define IGC_WUPL_MASK   0x00000FFF
  45
  46/* Wake Up Packet Memory stores the first 128 bytes of the wake up packet */
  47#define IGC_WUPM_BYTES  128
  48
  49/* Loop limit on how long we wait for auto-negotiation to complete */
  50#define COPPER_LINK_UP_LIMIT            10
  51#define PHY_AUTO_NEG_LIMIT              45
  52
  53/* Number of 100 microseconds we wait for PCI Express master disable */
  54#define MASTER_DISABLE_TIMEOUT          800
  55/*Blocks new Master requests */
  56#define IGC_CTRL_GIO_MASTER_DISABLE     0x00000004
  57/* Status of Master requests. */
  58#define IGC_STATUS_GIO_MASTER_ENABLE    0x00080000
  59
  60/* Receive Address
  61 * Number of high/low register pairs in the RAR. The RAR (Receive Address
  62 * Registers) holds the directed and multicast addresses that we monitor.
  63 * Technically, we have 16 spots.  However, we reserve one of these spots
  64 * (RAR[15]) for our directed address used by controllers with
  65 * manageability enabled, allowing us room for 15 multicast addresses.
  66 */
  67#define IGC_RAH_RAH_MASK        0x0000FFFF
  68#define IGC_RAH_ASEL_MASK       0x00030000
  69#define IGC_RAH_ASEL_SRC_ADDR   BIT(16)
  70#define IGC_RAH_QSEL_MASK       0x000C0000
  71#define IGC_RAH_QSEL_SHIFT      18
  72#define IGC_RAH_QSEL_ENABLE     BIT(28)
  73#define IGC_RAH_AV              0x80000000 /* Receive descriptor valid */
  74
  75#define IGC_RAL_MAC_ADDR_LEN    4
  76#define IGC_RAH_MAC_ADDR_LEN    2
  77
  78/* Error Codes */
  79#define IGC_SUCCESS                     0
  80#define IGC_ERR_NVM                     1
  81#define IGC_ERR_PHY                     2
  82#define IGC_ERR_CONFIG                  3
  83#define IGC_ERR_PARAM                   4
  84#define IGC_ERR_MAC_INIT                5
  85#define IGC_ERR_RESET                   9
  86#define IGC_ERR_MASTER_REQUESTS_PENDING 10
  87#define IGC_ERR_BLK_PHY_RESET           12
  88#define IGC_ERR_SWFW_SYNC               13
  89
  90/* Device Control */
  91#define IGC_CTRL_DEV_RST        0x20000000  /* Device reset */
  92
  93#define IGC_CTRL_PHY_RST        0x80000000  /* PHY Reset */
  94#define IGC_CTRL_SLU            0x00000040  /* Set link up (Force Link) */
  95#define IGC_CTRL_FRCSPD         0x00000800  /* Force Speed */
  96#define IGC_CTRL_FRCDPX         0x00001000  /* Force Duplex */
  97#define IGC_CTRL_VME            0x40000000  /* IEEE VLAN mode enable */
  98
  99#define IGC_CTRL_RFCE           0x08000000  /* Receive Flow Control enable */
 100#define IGC_CTRL_TFCE           0x10000000  /* Transmit flow control enable */
 101
 102#define IGC_CTRL_SDP0_DIR       0x00400000  /* SDP0 Data direction */
 103#define IGC_CTRL_SDP1_DIR       0x00800000  /* SDP1 Data direction */
 104
 105/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
 106#define MAX_JUMBO_FRAME_SIZE    0x2600
 107
 108/* PBA constants */
 109#define IGC_PBA_34K             0x0022
 110
 111/* SW Semaphore Register */
 112#define IGC_SWSM_SMBI           0x00000001 /* Driver Semaphore bit */
 113#define IGC_SWSM_SWESMBI        0x00000002 /* FW Semaphore bit */
 114
 115/* SWFW_SYNC Definitions */
 116#define IGC_SWFW_EEP_SM         0x1
 117#define IGC_SWFW_PHY0_SM        0x2
 118
 119/* Autoneg Advertisement Register */
 120#define NWAY_AR_10T_HD_CAPS     0x0020   /* 10T   Half Duplex Capable */
 121#define NWAY_AR_10T_FD_CAPS     0x0040   /* 10T   Full Duplex Capable */
 122#define NWAY_AR_100TX_HD_CAPS   0x0080   /* 100TX Half Duplex Capable */
 123#define NWAY_AR_100TX_FD_CAPS   0x0100   /* 100TX Full Duplex Capable */
 124#define NWAY_AR_PAUSE           0x0400   /* Pause operation desired */
 125#define NWAY_AR_ASM_DIR         0x0800   /* Asymmetric Pause Direction bit */
 126
 127/* Link Partner Ability Register (Base Page) */
 128#define NWAY_LPAR_PAUSE         0x0400 /* LP Pause operation desired */
 129#define NWAY_LPAR_ASM_DIR       0x0800 /* LP Asymmetric Pause Direction bit */
 130
 131/* 1000BASE-T Control Register */
 132#define CR_1000T_HD_CAPS        0x0100 /* Advertise 1000T HD capability */
 133#define CR_1000T_FD_CAPS        0x0200 /* Advertise 1000T FD capability  */
 134
 135/* 1000BASE-T Status Register */
 136#define SR_1000T_REMOTE_RX_STATUS       0x1000 /* Remote receiver OK */
 137
 138/* PHY GPY 211 registers */
 139#define STANDARD_AN_REG_MASK    0x0007 /* MMD */
 140#define ANEG_MULTIGBT_AN_CTRL   0x0020 /* MULTI GBT AN Control Register */
 141#define MMD_DEVADDR_SHIFT       16     /* Shift MMD to higher bits */
 142#define CR_2500T_FD_CAPS        0x0080 /* Advertise 2500T FD capability */
 143
 144/* NVM Control */
 145/* Number of milliseconds for NVM auto read done after MAC reset. */
 146#define AUTO_READ_DONE_TIMEOUT          10
 147#define IGC_EECD_AUTO_RD                0x00000200  /* NVM Auto Read done */
 148#define IGC_EECD_REQ            0x00000040 /* NVM Access Request */
 149#define IGC_EECD_GNT            0x00000080 /* NVM Access Grant */
 150/* NVM Addressing bits based on type 0=small, 1=large */
 151#define IGC_EECD_ADDR_BITS              0x00000400
 152#define IGC_NVM_GRANT_ATTEMPTS          1000 /* NVM # attempts to gain grant */
 153#define IGC_EECD_SIZE_EX_MASK           0x00007800  /* NVM Size */
 154#define IGC_EECD_SIZE_EX_SHIFT          11
 155#define IGC_EECD_FLUPD_I225             0x00800000 /* Update FLASH */
 156#define IGC_EECD_FLUDONE_I225           0x04000000 /* Update FLASH done*/
 157#define IGC_EECD_FLASH_DETECTED_I225    0x00080000 /* FLASH detected */
 158#define IGC_FLUDONE_ATTEMPTS            20000
 159#define IGC_EERD_EEWR_MAX_COUNT         512 /* buffered EEPROM words rw */
 160
 161/* Offset to data in NVM read/write registers */
 162#define IGC_NVM_RW_REG_DATA     16
 163#define IGC_NVM_RW_REG_DONE     2    /* Offset to READ/WRITE done bit */
 164#define IGC_NVM_RW_REG_START    1    /* Start operation */
 165#define IGC_NVM_RW_ADDR_SHIFT   2    /* Shift to the address bits */
 166#define IGC_NVM_POLL_READ       0    /* Flag for polling for read complete */
 167#define IGC_NVM_DEV_STARTER     5    /* Dev_starter Version */
 168
 169/* NVM Word Offsets */
 170#define NVM_CHECKSUM_REG                0x003F
 171
 172/* For checksumming, the sum of all words in the NVM should equal 0xBABA. */
 173#define NVM_SUM                         0xBABA
 174#define NVM_WORD_SIZE_BASE_SHIFT        6
 175
 176/* Collision related configuration parameters */
 177#define IGC_COLLISION_THRESHOLD         15
 178#define IGC_CT_SHIFT                    4
 179#define IGC_COLLISION_DISTANCE          63
 180#define IGC_COLD_SHIFT                  12
 181
 182/* Device Status */
 183#define IGC_STATUS_FD           0x00000001      /* Full duplex.0=half,1=full */
 184#define IGC_STATUS_LU           0x00000002      /* Link up.0=no,1=link */
 185#define IGC_STATUS_FUNC_MASK    0x0000000C      /* PCI Function Mask */
 186#define IGC_STATUS_FUNC_SHIFT   2
 187#define IGC_STATUS_TXOFF        0x00000010      /* transmission paused */
 188#define IGC_STATUS_SPEED_100    0x00000040      /* Speed 100Mb/s */
 189#define IGC_STATUS_SPEED_1000   0x00000080      /* Speed 1000Mb/s */
 190#define IGC_STATUS_SPEED_2500   0x00400000      /* Speed 2.5Gb/s */
 191
 192#define SPEED_10                10
 193#define SPEED_100               100
 194#define SPEED_1000              1000
 195#define SPEED_2500              2500
 196#define HALF_DUPLEX             1
 197#define FULL_DUPLEX             2
 198
 199/* 1Gbps and 2.5Gbps half duplex is not supported, nor spec-compliant. */
 200#define ADVERTISE_10_HALF               0x0001
 201#define ADVERTISE_10_FULL               0x0002
 202#define ADVERTISE_100_HALF              0x0004
 203#define ADVERTISE_100_FULL              0x0008
 204#define ADVERTISE_1000_HALF             0x0010 /* Not used, just FYI */
 205#define ADVERTISE_1000_FULL             0x0020
 206#define ADVERTISE_2500_HALF             0x0040 /* Not used, just FYI */
 207#define ADVERTISE_2500_FULL             0x0080
 208
 209#define IGC_ALL_SPEED_DUPLEX_2500 ( \
 210        ADVERTISE_10_HALF | ADVERTISE_10_FULL | ADVERTISE_100_HALF | \
 211        ADVERTISE_100_FULL | ADVERTISE_1000_FULL | ADVERTISE_2500_FULL)
 212
 213#define AUTONEG_ADVERTISE_SPEED_DEFAULT_2500    IGC_ALL_SPEED_DUPLEX_2500
 214
 215/* Interrupt Cause Read */
 216#define IGC_ICR_TXDW            BIT(0)  /* Transmit desc written back */
 217#define IGC_ICR_TXQE            BIT(1)  /* Transmit Queue empty */
 218#define IGC_ICR_LSC             BIT(2)  /* Link Status Change */
 219#define IGC_ICR_RXSEQ           BIT(3)  /* Rx sequence error */
 220#define IGC_ICR_RXDMT0          BIT(4)  /* Rx desc min. threshold (0) */
 221#define IGC_ICR_RXO             BIT(6)  /* Rx overrun */
 222#define IGC_ICR_RXT0            BIT(7)  /* Rx timer intr (ring 0) */
 223#define IGC_ICR_TS              BIT(19) /* Time Sync Interrupt */
 224#define IGC_ICR_DRSTA           BIT(30) /* Device Reset Asserted */
 225
 226/* If this bit asserted, the driver should claim the interrupt */
 227#define IGC_ICR_INT_ASSERTED    BIT(31)
 228
 229#define IGC_ICS_RXT0            IGC_ICR_RXT0 /* Rx timer intr */
 230
 231#define IMS_ENABLE_MASK ( \
 232        IGC_IMS_RXT0   |    \
 233        IGC_IMS_TXDW   |    \
 234        IGC_IMS_RXDMT0 |    \
 235        IGC_IMS_RXSEQ  |    \
 236        IGC_IMS_LSC)
 237
 238/* Interrupt Mask Set */
 239#define IGC_IMS_TXDW            IGC_ICR_TXDW    /* Tx desc written back */
 240#define IGC_IMS_RXSEQ           IGC_ICR_RXSEQ   /* Rx sequence error */
 241#define IGC_IMS_LSC             IGC_ICR_LSC     /* Link Status Change */
 242#define IGC_IMS_DOUTSYNC        IGC_ICR_DOUTSYNC /* NIC DMA out of sync */
 243#define IGC_IMS_DRSTA           IGC_ICR_DRSTA   /* Device Reset Asserted */
 244#define IGC_IMS_RXT0            IGC_ICR_RXT0    /* Rx timer intr */
 245#define IGC_IMS_RXDMT0          IGC_ICR_RXDMT0  /* Rx desc min. threshold */
 246#define IGC_IMS_TS              IGC_ICR_TS      /* Time Sync Interrupt */
 247
 248#define IGC_QVECTOR_MASK        0x7FFC          /* Q-vector mask */
 249#define IGC_ITR_VAL_MASK        0x04            /* ITR value mask */
 250
 251/* Interrupt Cause Set */
 252#define IGC_ICS_LSC             IGC_ICR_LSC       /* Link Status Change */
 253#define IGC_ICS_RXDMT0          IGC_ICR_RXDMT0    /* rx desc min. threshold */
 254
 255#define IGC_ICR_DOUTSYNC        0x10000000 /* NIC DMA out of sync */
 256#define IGC_EITR_CNT_IGNR       0x80000000 /* Don't reset counters on write */
 257#define IGC_IVAR_VALID          0x80
 258#define IGC_GPIE_NSICR          0x00000001
 259#define IGC_GPIE_MSIX_MODE      0x00000010
 260#define IGC_GPIE_EIAME          0x40000000
 261#define IGC_GPIE_PBA            0x80000000
 262
 263/* Receive Descriptor bit definitions */
 264#define IGC_RXD_STAT_DD         0x01    /* Descriptor Done */
 265
 266/* Transmit Descriptor bit definitions */
 267#define IGC_TXD_DTYP_D          0x00100000 /* Data Descriptor */
 268#define IGC_TXD_DTYP_C          0x00000000 /* Context Descriptor */
 269#define IGC_TXD_POPTS_IXSM      0x01       /* Insert IP checksum */
 270#define IGC_TXD_POPTS_TXSM      0x02       /* Insert TCP/UDP checksum */
 271#define IGC_TXD_CMD_EOP         0x01000000 /* End of Packet */
 272#define IGC_TXD_CMD_IC          0x04000000 /* Insert Checksum */
 273#define IGC_TXD_CMD_DEXT        0x20000000 /* Desc extension (0 = legacy) */
 274#define IGC_TXD_CMD_VLE         0x40000000 /* Add VLAN tag */
 275#define IGC_TXD_STAT_DD         0x00000001 /* Descriptor Done */
 276#define IGC_TXD_CMD_TCP         0x01000000 /* TCP packet */
 277#define IGC_TXD_CMD_IP          0x02000000 /* IP packet */
 278#define IGC_TXD_CMD_TSE         0x04000000 /* TCP Seg enable */
 279#define IGC_TXD_EXTCMD_TSTAMP   0x00000010 /* IEEE1588 Timestamp packet */
 280
 281/* IPSec Encrypt Enable */
 282#define IGC_ADVTXD_L4LEN_SHIFT  8  /* Adv ctxt L4LEN shift */
 283#define IGC_ADVTXD_MSS_SHIFT    16 /* Adv ctxt MSS shift */
 284
 285/* Transmit Control */
 286#define IGC_TCTL_EN             0x00000002 /* enable Tx */
 287#define IGC_TCTL_PSP            0x00000008 /* pad short packets */
 288#define IGC_TCTL_CT             0x00000ff0 /* collision threshold */
 289#define IGC_TCTL_COLD           0x003ff000 /* collision distance */
 290#define IGC_TCTL_RTLC           0x01000000 /* Re-transmit on late collision */
 291
 292/* Flow Control Constants */
 293#define FLOW_CONTROL_ADDRESS_LOW        0x00C28001
 294#define FLOW_CONTROL_ADDRESS_HIGH       0x00000100
 295#define FLOW_CONTROL_TYPE               0x8808
 296/* Enable XON frame transmission */
 297#define IGC_FCRTL_XONE                  0x80000000
 298
 299/* Management Control */
 300#define IGC_MANC_RCV_TCO_EN     0x00020000 /* Receive TCO Packets Enabled */
 301#define IGC_MANC_BLK_PHY_RST_ON_IDE     0x00040000 /* Block phy resets */
 302
 303/* Receive Control */
 304#define IGC_RCTL_RST            0x00000001 /* Software reset */
 305#define IGC_RCTL_EN             0x00000002 /* enable */
 306#define IGC_RCTL_SBP            0x00000004 /* store bad packet */
 307#define IGC_RCTL_UPE            0x00000008 /* unicast promisc enable */
 308#define IGC_RCTL_MPE            0x00000010 /* multicast promisc enable */
 309#define IGC_RCTL_LPE            0x00000020 /* long packet enable */
 310#define IGC_RCTL_LBM_MAC        0x00000040 /* MAC loopback mode */
 311#define IGC_RCTL_LBM_TCVR       0x000000C0 /* tcvr loopback mode */
 312
 313#define IGC_RCTL_RDMTS_HALF     0x00000000 /* Rx desc min thresh size */
 314#define IGC_RCTL_BAM            0x00008000 /* broadcast enable */
 315
 316/* Split Replication Receive Control */
 317#define IGC_SRRCTL_TIMESTAMP            0x40000000
 318#define IGC_SRRCTL_TIMER1SEL(timer)     (((timer) & 0x3) << 14)
 319#define IGC_SRRCTL_TIMER0SEL(timer)     (((timer) & 0x3) << 17)
 320
 321/* Receive Descriptor bit definitions */
 322#define IGC_RXD_STAT_EOP        0x02    /* End of Packet */
 323#define IGC_RXD_STAT_IXSM       0x04    /* Ignore checksum */
 324#define IGC_RXD_STAT_UDPCS      0x10    /* UDP xsum calculated */
 325#define IGC_RXD_STAT_TCPCS      0x20    /* TCP xsum calculated */
 326#define IGC_RXD_STAT_VP         0x08    /* IEEE VLAN Packet */
 327
 328#define IGC_RXDEXT_STATERR_LB   0x00040000
 329
 330/* Advanced Receive Descriptor bit definitions */
 331#define IGC_RXDADV_STAT_TSIP    0x08000 /* timestamp in packet */
 332
 333#define IGC_RXDEXT_STATERR_L4E          0x20000000
 334#define IGC_RXDEXT_STATERR_IPE          0x40000000
 335#define IGC_RXDEXT_STATERR_RXE          0x80000000
 336
 337#define IGC_MRQC_RSS_FIELD_IPV4_TCP     0x00010000
 338#define IGC_MRQC_RSS_FIELD_IPV4         0x00020000
 339#define IGC_MRQC_RSS_FIELD_IPV6_TCP_EX  0x00040000
 340#define IGC_MRQC_RSS_FIELD_IPV6         0x00100000
 341#define IGC_MRQC_RSS_FIELD_IPV6_TCP     0x00200000
 342
 343/* Header split receive */
 344#define IGC_RFCTL_IPV6_EX_DIS   0x00010000
 345#define IGC_RFCTL_LEF           0x00040000
 346
 347#define IGC_RCTL_SZ_256         0x00030000 /* Rx buffer size 256 */
 348
 349#define IGC_RCTL_MO_SHIFT       12 /* multicast offset shift */
 350#define IGC_RCTL_CFIEN          0x00080000 /* canonical form enable */
 351#define IGC_RCTL_DPF            0x00400000 /* discard pause frames */
 352#define IGC_RCTL_PMCF           0x00800000 /* pass MAC control frames */
 353#define IGC_RCTL_SECRC          0x04000000 /* Strip Ethernet CRC */
 354
 355#define I225_RXPBSIZE_DEFAULT   0x000000A2 /* RXPBSIZE default */
 356#define I225_TXPBSIZE_DEFAULT   0x04000014 /* TXPBSIZE default */
 357#define IGC_RXPBS_CFG_TS_EN     0x80000000 /* Timestamp in Rx buffer */
 358
 359#define IGC_TXPBSIZE_TSN        0x04145145 /* 5k bytes buffer for each queue */
 360
 361#define IGC_DTXMXPKTSZ_TSN      0x19 /* 1600 bytes of max TX DMA packet size */
 362#define IGC_DTXMXPKTSZ_DEFAULT  0x98 /* 9728-byte Jumbo frames */
 363
 364/* Time Sync Interrupt Causes */
 365#define IGC_TSICR_SYS_WRAP      BIT(0) /* SYSTIM Wrap around. */
 366#define IGC_TSICR_TXTS          BIT(1) /* Transmit Timestamp. */
 367#define IGC_TSICR_TT0           BIT(3) /* Target Time 0 Trigger. */
 368#define IGC_TSICR_TT1           BIT(4) /* Target Time 1 Trigger. */
 369#define IGC_TSICR_AUTT0         BIT(5) /* Auxiliary Timestamp 0 Taken. */
 370#define IGC_TSICR_AUTT1         BIT(6) /* Auxiliary Timestamp 1 Taken. */
 371
 372#define IGC_TSICR_INTERRUPTS    IGC_TSICR_TXTS
 373
 374#define IGC_FTQF_VF_BP          0x00008000
 375#define IGC_FTQF_1588_TIME_STAMP        0x08000000
 376#define IGC_FTQF_MASK                   0xF0000000
 377#define IGC_FTQF_MASK_PROTO_BP  0x10000000
 378
 379/* Time Sync Receive Control bit definitions */
 380#define IGC_TSYNCRXCTL_TYPE_MASK        0x0000000E  /* Rx type mask */
 381#define IGC_TSYNCRXCTL_TYPE_L2_V2       0x00
 382#define IGC_TSYNCRXCTL_TYPE_L4_V1       0x02
 383#define IGC_TSYNCRXCTL_TYPE_L2_L4_V2    0x04
 384#define IGC_TSYNCRXCTL_TYPE_ALL         0x08
 385#define IGC_TSYNCRXCTL_TYPE_EVENT_V2    0x0A
 386#define IGC_TSYNCRXCTL_ENABLED          0x00000010  /* enable Rx timestamping */
 387#define IGC_TSYNCRXCTL_SYSCFI           0x00000020  /* Sys clock frequency */
 388#define IGC_TSYNCRXCTL_RXSYNSIG         0x00000400  /* Sample RX tstamp in PHY sop */
 389
 390/* Time Sync Receive Configuration */
 391#define IGC_TSYNCRXCFG_PTP_V1_CTRLT_MASK        0x000000FF
 392#define IGC_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE      0x00
 393#define IGC_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE 0x01
 394
 395/* Immediate Interrupt Receive */
 396#define IGC_IMIR_CLEAR_MASK     0xF001FFFF /* IMIR Reg Clear Mask */
 397#define IGC_IMIR_PORT_BYPASS    0x20000 /* IMIR Port Bypass Bit */
 398#define IGC_IMIR_PRIORITY_SHIFT 29 /* IMIR Priority Shift */
 399#define IGC_IMIREXT_CLEAR_MASK  0x7FFFF /* IMIREXT Reg Clear Mask */
 400
 401/* Immediate Interrupt Receive Extended */
 402#define IGC_IMIREXT_CTRL_BP     0x00080000  /* Bypass check of ctrl bits */
 403#define IGC_IMIREXT_SIZE_BP     0x00001000  /* Packet size bypass */
 404
 405/* Time Sync Transmit Control bit definitions */
 406#define IGC_TSYNCTXCTL_TXTT_0                   0x00000001  /* Tx timestamp reg 0 valid */
 407#define IGC_TSYNCTXCTL_ENABLED                  0x00000010  /* enable Tx timestamping */
 408#define IGC_TSYNCTXCTL_MAX_ALLOWED_DLY_MASK     0x0000F000  /* max delay */
 409#define IGC_TSYNCTXCTL_SYNC_COMP_ERR            0x20000000  /* sync err */
 410#define IGC_TSYNCTXCTL_SYNC_COMP                0x40000000  /* sync complete */
 411#define IGC_TSYNCTXCTL_START_SYNC               0x80000000  /* initiate sync */
 412#define IGC_TSYNCTXCTL_TXSYNSIG                 0x00000020  /* Sample TX tstamp in PHY sop */
 413
 414/* Timer selection bits */
 415#define IGC_AUX_IO_TIMER_SEL_SYSTIM0    (0u << 30) /* Select SYSTIM0 for auxiliary time stamp */
 416#define IGC_AUX_IO_TIMER_SEL_SYSTIM1    (1u << 30) /* Select SYSTIM1 for auxiliary time stamp */
 417#define IGC_AUX_IO_TIMER_SEL_SYSTIM2    (2u << 30) /* Select SYSTIM2 for auxiliary time stamp */
 418#define IGC_AUX_IO_TIMER_SEL_SYSTIM3    (3u << 30) /* Select SYSTIM3 for auxiliary time stamp */
 419#define IGC_TT_IO_TIMER_SEL_SYSTIM0     (0u << 30) /* Select SYSTIM0 for target time stamp */
 420#define IGC_TT_IO_TIMER_SEL_SYSTIM1     (1u << 30) /* Select SYSTIM1 for target time stamp */
 421#define IGC_TT_IO_TIMER_SEL_SYSTIM2     (2u << 30) /* Select SYSTIM2 for target time stamp */
 422#define IGC_TT_IO_TIMER_SEL_SYSTIM3     (3u << 30) /* Select SYSTIM3 for target time stamp */
 423
 424/* TSAUXC Configuration Bits */
 425#define IGC_TSAUXC_EN_TT0       BIT(0)  /* Enable target time 0. */
 426#define IGC_TSAUXC_EN_TT1       BIT(1)  /* Enable target time 1. */
 427#define IGC_TSAUXC_EN_CLK0      BIT(2)  /* Enable Configurable Frequency Clock 0. */
 428#define IGC_TSAUXC_EN_CLK1      BIT(5)  /* Enable Configurable Frequency Clock 1. */
 429#define IGC_TSAUXC_EN_TS0       BIT(8)  /* Enable hardware timestamp 0. */
 430#define IGC_TSAUXC_AUTT0        BIT(9)  /* Auxiliary Timestamp Taken. */
 431#define IGC_TSAUXC_EN_TS1       BIT(10) /* Enable hardware timestamp 0. */
 432#define IGC_TSAUXC_AUTT1        BIT(11) /* Auxiliary Timestamp Taken. */
 433#define IGC_TSAUXC_PLSG         BIT(17) /* Generate a pulse. */
 434#define IGC_TSAUXC_DISABLE1     BIT(27) /* Disable SYSTIM0 Count Operation. */
 435#define IGC_TSAUXC_DISABLE2     BIT(28) /* Disable SYSTIM1 Count Operation. */
 436#define IGC_TSAUXC_DISABLE3     BIT(29) /* Disable SYSTIM2 Count Operation. */
 437#define IGC_TSAUXC_DIS_TS_CLEAR BIT(30) /* Disable EN_TT0/1 auto clear. */
 438#define IGC_TSAUXC_DISABLE0     BIT(31) /* Disable SYSTIM0 Count Operation. */
 439
 440/* SDP Configuration Bits */
 441#define IGC_AUX0_SEL_SDP0       (0u << 0)  /* Assign SDP0 to auxiliary time stamp 0. */
 442#define IGC_AUX0_SEL_SDP1       (1u << 0)  /* Assign SDP1 to auxiliary time stamp 0. */
 443#define IGC_AUX0_SEL_SDP2       (2u << 0)  /* Assign SDP2 to auxiliary time stamp 0. */
 444#define IGC_AUX0_SEL_SDP3       (3u << 0)  /* Assign SDP3 to auxiliary time stamp 0. */
 445#define IGC_AUX0_TS_SDP_EN      (1u << 2)  /* Enable auxiliary time stamp trigger 0. */
 446#define IGC_AUX1_SEL_SDP0       (0u << 3)  /* Assign SDP0 to auxiliary time stamp 1. */
 447#define IGC_AUX1_SEL_SDP1       (1u << 3)  /* Assign SDP1 to auxiliary time stamp 1. */
 448#define IGC_AUX1_SEL_SDP2       (2u << 3)  /* Assign SDP2 to auxiliary time stamp 1. */
 449#define IGC_AUX1_SEL_SDP3       (3u << 3)  /* Assign SDP3 to auxiliary time stamp 1. */
 450#define IGC_AUX1_TS_SDP_EN      (1u << 5)  /* Enable auxiliary time stamp trigger 1. */
 451#define IGC_TS_SDP0_SEL_TT0     (0u << 6)  /* Target time 0 is output on SDP0. */
 452#define IGC_TS_SDP0_SEL_TT1     (1u << 6)  /* Target time 1 is output on SDP0. */
 453#define IGC_TS_SDP0_SEL_FC0     (2u << 6)  /* Freq clock  0 is output on SDP0. */
 454#define IGC_TS_SDP0_SEL_FC1     (3u << 6)  /* Freq clock  1 is output on SDP0. */
 455#define IGC_TS_SDP0_EN          (1u << 8)  /* SDP0 is assigned to Tsync. */
 456#define IGC_TS_SDP1_SEL_TT0     (0u << 9)  /* Target time 0 is output on SDP1. */
 457#define IGC_TS_SDP1_SEL_TT1     (1u << 9)  /* Target time 1 is output on SDP1. */
 458#define IGC_TS_SDP1_SEL_FC0     (2u << 9)  /* Freq clock  0 is output on SDP1. */
 459#define IGC_TS_SDP1_SEL_FC1     (3u << 9)  /* Freq clock  1 is output on SDP1. */
 460#define IGC_TS_SDP1_EN          (1u << 11) /* SDP1 is assigned to Tsync. */
 461#define IGC_TS_SDP2_SEL_TT0     (0u << 12) /* Target time 0 is output on SDP2. */
 462#define IGC_TS_SDP2_SEL_TT1     (1u << 12) /* Target time 1 is output on SDP2. */
 463#define IGC_TS_SDP2_SEL_FC0     (2u << 12) /* Freq clock  0 is output on SDP2. */
 464#define IGC_TS_SDP2_SEL_FC1     (3u << 12) /* Freq clock  1 is output on SDP2. */
 465#define IGC_TS_SDP2_EN          (1u << 14) /* SDP2 is assigned to Tsync. */
 466#define IGC_TS_SDP3_SEL_TT0     (0u << 15) /* Target time 0 is output on SDP3. */
 467#define IGC_TS_SDP3_SEL_TT1     (1u << 15) /* Target time 1 is output on SDP3. */
 468#define IGC_TS_SDP3_SEL_FC0     (2u << 15) /* Freq clock  0 is output on SDP3. */
 469#define IGC_TS_SDP3_SEL_FC1     (3u << 15) /* Freq clock  1 is output on SDP3. */
 470#define IGC_TS_SDP3_EN          (1u << 17) /* SDP3 is assigned to Tsync. */
 471
 472/* Transmit Scheduling */
 473#define IGC_TQAVCTRL_TRANSMIT_MODE_TSN  0x00000001
 474#define IGC_TQAVCTRL_ENHANCED_QAV       0x00000008
 475
 476#define IGC_TXQCTL_QUEUE_MODE_LAUNCHT   0x00000001
 477#define IGC_TXQCTL_STRICT_CYCLE         0x00000002
 478#define IGC_TXQCTL_STRICT_END           0x00000004
 479
 480/* Receive Checksum Control */
 481#define IGC_RXCSUM_CRCOFL       0x00000800   /* CRC32 offload enable */
 482#define IGC_RXCSUM_PCSD         0x00002000   /* packet checksum disabled */
 483
 484/* GPY211 - I225 defines */
 485#define GPY_MMD_MASK            0xFFFF0000
 486#define GPY_MMD_SHIFT           16
 487#define GPY_REG_MASK            0x0000FFFF
 488
 489#define IGC_MMDAC_FUNC_DATA     0x4000 /* Data, no post increment */
 490
 491/* MAC definitions */
 492#define IGC_FACTPS_MNGCG        0x20000000
 493#define IGC_FWSM_MODE_MASK      0xE
 494#define IGC_FWSM_MODE_SHIFT     1
 495
 496/* Management Control */
 497#define IGC_MANC_SMBUS_EN       0x00000001 /* SMBus Enabled - RO */
 498#define IGC_MANC_ASF_EN         0x00000002 /* ASF Enabled - RO */
 499
 500/* PHY */
 501#define PHY_REVISION_MASK       0xFFFFFFF0
 502#define MAX_PHY_REG_ADDRESS     0x1F  /* 5 bit address bus (0-0x1F) */
 503#define IGC_GEN_POLL_TIMEOUT    1920
 504
 505/* PHY Control Register */
 506#define MII_CR_FULL_DUPLEX      0x0100  /* FDX =1, half duplex =0 */
 507#define MII_CR_RESTART_AUTO_NEG 0x0200  /* Restart auto negotiation */
 508#define MII_CR_POWER_DOWN       0x0800  /* Power down */
 509#define MII_CR_AUTO_NEG_EN      0x1000  /* Auto Neg Enable */
 510
 511/* PHY Status Register */
 512#define MII_SR_LINK_STATUS      0x0004 /* Link Status 1 = link */
 513#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
 514#define IGC_PHY_RST_COMP        0x0100 /* Internal PHY reset completion */
 515
 516/* PHY 1000 MII Register/Bit Definitions */
 517/* PHY Registers defined by IEEE */
 518#define PHY_CONTROL             0x00 /* Control Register */
 519#define PHY_STATUS              0x01 /* Status Register */
 520#define PHY_ID1                 0x02 /* Phy Id Reg (word 1) */
 521#define PHY_ID2                 0x03 /* Phy Id Reg (word 2) */
 522#define PHY_AUTONEG_ADV         0x04 /* Autoneg Advertisement */
 523#define PHY_LP_ABILITY          0x05 /* Link Partner Ability (Base Page) */
 524#define PHY_1000T_CTRL          0x09 /* 1000Base-T Control Reg */
 525#define PHY_1000T_STATUS        0x0A /* 1000Base-T Status Reg */
 526
 527/* Bit definitions for valid PHY IDs. I = Integrated E = External */
 528#define I225_I_PHY_ID           0x67C9DC00
 529
 530/* MDI Control */
 531#define IGC_MDIC_DATA_MASK      0x0000FFFF
 532#define IGC_MDIC_REG_MASK       0x001F0000
 533#define IGC_MDIC_REG_SHIFT      16
 534#define IGC_MDIC_PHY_MASK       0x03E00000
 535#define IGC_MDIC_PHY_SHIFT      21
 536#define IGC_MDIC_OP_WRITE       0x04000000
 537#define IGC_MDIC_OP_READ        0x08000000
 538#define IGC_MDIC_READY          0x10000000
 539#define IGC_MDIC_INT_EN         0x20000000
 540#define IGC_MDIC_ERROR          0x40000000
 541
 542#define IGC_N0_QUEUE            -1
 543
 544#define IGC_MAX_MAC_HDR_LEN     127
 545#define IGC_MAX_NETWORK_HDR_LEN 511
 546
 547#define IGC_VLANPQF_QSEL(_n, q_idx) ((q_idx) << ((_n) * 4))
 548#define IGC_VLANPQF_VALID(_n)   (0x1 << (3 + (_n) * 4))
 549#define IGC_VLANPQF_QUEUE_MASK  0x03
 550
 551#define IGC_ADVTXD_MACLEN_SHIFT         9  /* Adv ctxt desc mac len shift */
 552#define IGC_ADVTXD_TUCMD_IPV4           0x00000400  /* IP Packet Type:1=IPv4 */
 553#define IGC_ADVTXD_TUCMD_L4T_TCP        0x00000800  /* L4 Packet Type of TCP */
 554#define IGC_ADVTXD_TUCMD_L4T_SCTP       0x00001000 /* L4 packet TYPE of SCTP */
 555
 556/* Maximum size of the MTA register table in all supported adapters */
 557#define MAX_MTA_REG                     128
 558
 559/* EEE defines */
 560#define IGC_IPCNFG_EEE_2_5G_AN          0x00000010 /* IPCNFG EEE Ena 2.5G AN */
 561#define IGC_IPCNFG_EEE_1G_AN            0x00000008 /* IPCNFG EEE Ena 1G AN */
 562#define IGC_IPCNFG_EEE_100M_AN          0x00000004 /* IPCNFG EEE Ena 100M AN */
 563#define IGC_EEER_EEE_NEG                0x20000000 /* EEE capability nego */
 564#define IGC_EEER_TX_LPI_EN              0x00010000 /* EEER Tx LPI Enable */
 565#define IGC_EEER_RX_LPI_EN              0x00020000 /* EEER Rx LPI Enable */
 566#define IGC_EEER_LPI_FC                 0x00040000 /* EEER Ena on Flow Cntrl */
 567#define IGC_EEE_SU_LPI_CLK_STP          0x00800000 /* EEE LPI Clock Stop */
 568
 569/* LTR defines */
 570#define IGC_LTRC_EEEMS_EN               0x00000020 /* Enable EEE LTR max send */
 571#define IGC_RXPBS_SIZE_I225_MASK        0x0000003F /* Rx packet buffer size */
 572#define IGC_TW_SYSTEM_1000_MASK         0x000000FF
 573/* Minimum time for 100BASE-T where no data will be transmit following move out
 574 * of EEE LPI Tx state
 575 */
 576#define IGC_TW_SYSTEM_100_MASK          0x0000FF00
 577#define IGC_TW_SYSTEM_100_SHIFT         8
 578#define IGC_DMACR_DMAC_EN               0x80000000 /* Enable DMA Coalescing */
 579#define IGC_DMACR_DMACTHR_MASK          0x00FF0000
 580#define IGC_DMACR_DMACTHR_SHIFT         16
 581/* Reg val to set scale to 1024 nsec */
 582#define IGC_LTRMINV_SCALE_1024          2
 583/* Reg val to set scale to 32768 nsec */
 584#define IGC_LTRMINV_SCALE_32768         3
 585/* Reg val to set scale to 1024 nsec */
 586#define IGC_LTRMAXV_SCALE_1024          2
 587/* Reg val to set scale to 32768 nsec */
 588#define IGC_LTRMAXV_SCALE_32768         3
 589#define IGC_LTRMINV_LTRV_MASK           0x000003FF /* LTR minimum value */
 590#define IGC_LTRMAXV_LTRV_MASK           0x000003FF /* LTR maximum value */
 591#define IGC_LTRMINV_LSNP_REQ            0x00008000 /* LTR Snoop Requirement */
 592#define IGC_LTRMINV_SCALE_SHIFT         10
 593#define IGC_LTRMAXV_LSNP_REQ            0x00008000 /* LTR Snoop Requirement */
 594#define IGC_LTRMAXV_SCALE_SHIFT         10
 595
 596#endif /* _IGC_DEFINES_H_ */
 597