linux/drivers/net/ethernet/intel/igb/e1000_mac.c
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   1// SPDX-License-Identifier: GPL-2.0
   2/* Copyright(c) 2007 - 2018 Intel Corporation. */
   3
   4#include <linux/if_ether.h>
   5#include <linux/delay.h>
   6#include <linux/pci.h>
   7#include <linux/netdevice.h>
   8#include <linux/etherdevice.h>
   9
  10#include "e1000_mac.h"
  11
  12#include "igb.h"
  13
  14static s32 igb_set_default_fc(struct e1000_hw *hw);
  15static void igb_set_fc_watermarks(struct e1000_hw *hw);
  16
  17/**
  18 *  igb_get_bus_info_pcie - Get PCIe bus information
  19 *  @hw: pointer to the HW structure
  20 *
  21 *  Determines and stores the system bus information for a particular
  22 *  network interface.  The following bus information is determined and stored:
  23 *  bus speed, bus width, type (PCIe), and PCIe function.
  24 **/
  25s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
  26{
  27        struct e1000_bus_info *bus = &hw->bus;
  28        s32 ret_val;
  29        u32 reg;
  30        u16 pcie_link_status;
  31
  32        bus->type = e1000_bus_type_pci_express;
  33
  34        ret_val = igb_read_pcie_cap_reg(hw,
  35                                        PCI_EXP_LNKSTA,
  36                                        &pcie_link_status);
  37        if (ret_val) {
  38                bus->width = e1000_bus_width_unknown;
  39                bus->speed = e1000_bus_speed_unknown;
  40        } else {
  41                switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
  42                case PCI_EXP_LNKSTA_CLS_2_5GB:
  43                        bus->speed = e1000_bus_speed_2500;
  44                        break;
  45                case PCI_EXP_LNKSTA_CLS_5_0GB:
  46                        bus->speed = e1000_bus_speed_5000;
  47                        break;
  48                default:
  49                        bus->speed = e1000_bus_speed_unknown;
  50                        break;
  51                }
  52
  53                bus->width = (enum e1000_bus_width)((pcie_link_status &
  54                                                     PCI_EXP_LNKSTA_NLW) >>
  55                                                     PCI_EXP_LNKSTA_NLW_SHIFT);
  56        }
  57
  58        reg = rd32(E1000_STATUS);
  59        bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;
  60
  61        return 0;
  62}
  63
  64/**
  65 *  igb_clear_vfta - Clear VLAN filter table
  66 *  @hw: pointer to the HW structure
  67 *
  68 *  Clears the register array which contains the VLAN filter table by
  69 *  setting all the values to 0.
  70 **/
  71void igb_clear_vfta(struct e1000_hw *hw)
  72{
  73        u32 offset;
  74
  75        for (offset = E1000_VLAN_FILTER_TBL_SIZE; offset--;)
  76                hw->mac.ops.write_vfta(hw, offset, 0);
  77}
  78
  79/**
  80 *  igb_write_vfta - Write value to VLAN filter table
  81 *  @hw: pointer to the HW structure
  82 *  @offset: register offset in VLAN filter table
  83 *  @value: register value written to VLAN filter table
  84 *
  85 *  Writes value at the given offset in the register array which stores
  86 *  the VLAN filter table.
  87 **/
  88void igb_write_vfta(struct e1000_hw *hw, u32 offset, u32 value)
  89{
  90        struct igb_adapter *adapter = hw->back;
  91
  92        array_wr32(E1000_VFTA, offset, value);
  93        wrfl();
  94
  95        adapter->shadow_vfta[offset] = value;
  96}
  97
  98/**
  99 *  igb_init_rx_addrs - Initialize receive address's
 100 *  @hw: pointer to the HW structure
 101 *  @rar_count: receive address registers
 102 *
 103 *  Setups the receive address registers by setting the base receive address
 104 *  register to the devices MAC address and clearing all the other receive
 105 *  address registers to 0.
 106 **/
 107void igb_init_rx_addrs(struct e1000_hw *hw, u16 rar_count)
 108{
 109        u32 i;
 110        u8 mac_addr[ETH_ALEN] = {0};
 111
 112        /* Setup the receive address */
 113        hw_dbg("Programming MAC Address into RAR[0]\n");
 114
 115        hw->mac.ops.rar_set(hw, hw->mac.addr, 0);
 116
 117        /* Zero out the other (rar_entry_count - 1) receive addresses */
 118        hw_dbg("Clearing RAR[1-%u]\n", rar_count-1);
 119        for (i = 1; i < rar_count; i++)
 120                hw->mac.ops.rar_set(hw, mac_addr, i);
 121}
 122
 123/**
 124 *  igb_find_vlvf_slot - find the VLAN id or the first empty slot
 125 *  @hw: pointer to hardware structure
 126 *  @vlan: VLAN id to write to VLAN filter
 127 *  @vlvf_bypass: skip VLVF if no match is found
 128 *
 129 *  return the VLVF index where this VLAN id should be placed
 130 *
 131 **/
 132static s32 igb_find_vlvf_slot(struct e1000_hw *hw, u32 vlan, bool vlvf_bypass)
 133{
 134        s32 regindex, first_empty_slot;
 135        u32 bits;
 136
 137        /* short cut the special case */
 138        if (vlan == 0)
 139                return 0;
 140
 141        /* if vlvf_bypass is set we don't want to use an empty slot, we
 142         * will simply bypass the VLVF if there are no entries present in the
 143         * VLVF that contain our VLAN
 144         */
 145        first_empty_slot = vlvf_bypass ? -E1000_ERR_NO_SPACE : 0;
 146
 147        /* Search for the VLAN id in the VLVF entries. Save off the first empty
 148         * slot found along the way.
 149         *
 150         * pre-decrement loop covering (IXGBE_VLVF_ENTRIES - 1) .. 1
 151         */
 152        for (regindex = E1000_VLVF_ARRAY_SIZE; --regindex > 0;) {
 153                bits = rd32(E1000_VLVF(regindex)) & E1000_VLVF_VLANID_MASK;
 154                if (bits == vlan)
 155                        return regindex;
 156                if (!first_empty_slot && !bits)
 157                        first_empty_slot = regindex;
 158        }
 159
 160        return first_empty_slot ? : -E1000_ERR_NO_SPACE;
 161}
 162
 163/**
 164 *  igb_vfta_set - enable or disable vlan in VLAN filter table
 165 *  @hw: pointer to the HW structure
 166 *  @vlan: VLAN id to add or remove
 167 *  @vind: VMDq output index that maps queue to VLAN id
 168 *  @vlan_on: if true add filter, if false remove
 169 *  @vlvf_bypass: skip VLVF if no match is found
 170 *
 171 *  Sets or clears a bit in the VLAN filter table array based on VLAN id
 172 *  and if we are adding or removing the filter
 173 **/
 174s32 igb_vfta_set(struct e1000_hw *hw, u32 vlan, u32 vind,
 175                 bool vlan_on, bool vlvf_bypass)
 176{
 177        struct igb_adapter *adapter = hw->back;
 178        u32 regidx, vfta_delta, vfta, bits;
 179        s32 vlvf_index;
 180
 181        if ((vlan > 4095) || (vind > 7))
 182                return -E1000_ERR_PARAM;
 183
 184        /* this is a 2 part operation - first the VFTA, then the
 185         * VLVF and VLVFB if VT Mode is set
 186         * We don't write the VFTA until we know the VLVF part succeeded.
 187         */
 188
 189        /* Part 1
 190         * The VFTA is a bitstring made up of 128 32-bit registers
 191         * that enable the particular VLAN id, much like the MTA:
 192         *    bits[11-5]: which register
 193         *    bits[4-0]:  which bit in the register
 194         */
 195        regidx = vlan / 32;
 196        vfta_delta = BIT(vlan % 32);
 197        vfta = adapter->shadow_vfta[regidx];
 198
 199        /* vfta_delta represents the difference between the current value
 200         * of vfta and the value we want in the register.  Since the diff
 201         * is an XOR mask we can just update vfta using an XOR.
 202         */
 203        vfta_delta &= vlan_on ? ~vfta : vfta;
 204        vfta ^= vfta_delta;
 205
 206        /* Part 2
 207         * If VT Mode is set
 208         *   Either vlan_on
 209         *     make sure the VLAN is in VLVF
 210         *     set the vind bit in the matching VLVFB
 211         *   Or !vlan_on
 212         *     clear the pool bit and possibly the vind
 213         */
 214        if (!adapter->vfs_allocated_count)
 215                goto vfta_update;
 216
 217        vlvf_index = igb_find_vlvf_slot(hw, vlan, vlvf_bypass);
 218        if (vlvf_index < 0) {
 219                if (vlvf_bypass)
 220                        goto vfta_update;
 221                return vlvf_index;
 222        }
 223
 224        bits = rd32(E1000_VLVF(vlvf_index));
 225
 226        /* set the pool bit */
 227        bits |= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);
 228        if (vlan_on)
 229                goto vlvf_update;
 230
 231        /* clear the pool bit */
 232        bits ^= BIT(E1000_VLVF_POOLSEL_SHIFT + vind);
 233
 234        if (!(bits & E1000_VLVF_POOLSEL_MASK)) {
 235                /* Clear VFTA first, then disable VLVF.  Otherwise
 236                 * we run the risk of stray packets leaking into
 237                 * the PF via the default pool
 238                 */
 239                if (vfta_delta)
 240                        hw->mac.ops.write_vfta(hw, regidx, vfta);
 241
 242                /* disable VLVF and clear remaining bit from pool */
 243                wr32(E1000_VLVF(vlvf_index), 0);
 244
 245                return 0;
 246        }
 247
 248        /* If there are still bits set in the VLVFB registers
 249         * for the VLAN ID indicated we need to see if the
 250         * caller is requesting that we clear the VFTA entry bit.
 251         * If the caller has requested that we clear the VFTA
 252         * entry bit but there are still pools/VFs using this VLAN
 253         * ID entry then ignore the request.  We're not worried
 254         * about the case where we're turning the VFTA VLAN ID
 255         * entry bit on, only when requested to turn it off as
 256         * there may be multiple pools and/or VFs using the
 257         * VLAN ID entry.  In that case we cannot clear the
 258         * VFTA bit until all pools/VFs using that VLAN ID have also
 259         * been cleared.  This will be indicated by "bits" being
 260         * zero.
 261         */
 262        vfta_delta = 0;
 263
 264vlvf_update:
 265        /* record pool change and enable VLAN ID if not already enabled */
 266        wr32(E1000_VLVF(vlvf_index), bits | vlan | E1000_VLVF_VLANID_ENABLE);
 267
 268vfta_update:
 269        /* bit was set/cleared before we started */
 270        if (vfta_delta)
 271                hw->mac.ops.write_vfta(hw, regidx, vfta);
 272
 273        return 0;
 274}
 275
 276/**
 277 *  igb_check_alt_mac_addr - Check for alternate MAC addr
 278 *  @hw: pointer to the HW structure
 279 *
 280 *  Checks the nvm for an alternate MAC address.  An alternate MAC address
 281 *  can be setup by pre-boot software and must be treated like a permanent
 282 *  address and must override the actual permanent MAC address.  If an
 283 *  alternate MAC address is found it is saved in the hw struct and
 284 *  programmed into RAR0 and the function returns success, otherwise the
 285 *  function returns an error.
 286 **/
 287s32 igb_check_alt_mac_addr(struct e1000_hw *hw)
 288{
 289        u32 i;
 290        s32 ret_val = 0;
 291        u16 offset, nvm_alt_mac_addr_offset, nvm_data;
 292        u8 alt_mac_addr[ETH_ALEN];
 293
 294        /* Alternate MAC address is handled by the option ROM for 82580
 295         * and newer. SW support not required.
 296         */
 297        if (hw->mac.type >= e1000_82580)
 298                goto out;
 299
 300        ret_val = hw->nvm.ops.read(hw, NVM_ALT_MAC_ADDR_PTR, 1,
 301                                 &nvm_alt_mac_addr_offset);
 302        if (ret_val) {
 303                hw_dbg("NVM Read Error\n");
 304                goto out;
 305        }
 306
 307        if ((nvm_alt_mac_addr_offset == 0xFFFF) ||
 308            (nvm_alt_mac_addr_offset == 0x0000))
 309                /* There is no Alternate MAC Address */
 310                goto out;
 311
 312        if (hw->bus.func == E1000_FUNC_1)
 313                nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN1;
 314        if (hw->bus.func == E1000_FUNC_2)
 315                nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN2;
 316
 317        if (hw->bus.func == E1000_FUNC_3)
 318                nvm_alt_mac_addr_offset += E1000_ALT_MAC_ADDRESS_OFFSET_LAN3;
 319        for (i = 0; i < ETH_ALEN; i += 2) {
 320                offset = nvm_alt_mac_addr_offset + (i >> 1);
 321                ret_val = hw->nvm.ops.read(hw, offset, 1, &nvm_data);
 322                if (ret_val) {
 323                        hw_dbg("NVM Read Error\n");
 324                        goto out;
 325                }
 326
 327                alt_mac_addr[i] = (u8)(nvm_data & 0xFF);
 328                alt_mac_addr[i + 1] = (u8)(nvm_data >> 8);
 329        }
 330
 331        /* if multicast bit is set, the alternate address will not be used */
 332        if (is_multicast_ether_addr(alt_mac_addr)) {
 333                hw_dbg("Ignoring Alternate Mac Address with MC bit set\n");
 334                goto out;
 335        }
 336
 337        /* We have a valid alternate MAC address, and we want to treat it the
 338         * same as the normal permanent MAC address stored by the HW into the
 339         * RAR. Do this by mapping this address into RAR0.
 340         */
 341        hw->mac.ops.rar_set(hw, alt_mac_addr, 0);
 342
 343out:
 344        return ret_val;
 345}
 346
 347/**
 348 *  igb_rar_set - Set receive address register
 349 *  @hw: pointer to the HW structure
 350 *  @addr: pointer to the receive address
 351 *  @index: receive address array register
 352 *
 353 *  Sets the receive address array register at index to the address passed
 354 *  in by addr.
 355 **/
 356void igb_rar_set(struct e1000_hw *hw, u8 *addr, u32 index)
 357{
 358        u32 rar_low, rar_high;
 359
 360        /* HW expects these in little endian so we reverse the byte order
 361         * from network order (big endian) to little endian
 362         */
 363        rar_low = ((u32) addr[0] |
 364                   ((u32) addr[1] << 8) |
 365                    ((u32) addr[2] << 16) | ((u32) addr[3] << 24));
 366
 367        rar_high = ((u32) addr[4] | ((u32) addr[5] << 8));
 368
 369        /* If MAC address zero, no need to set the AV bit */
 370        if (rar_low || rar_high)
 371                rar_high |= E1000_RAH_AV;
 372
 373        /* Some bridges will combine consecutive 32-bit writes into
 374         * a single burst write, which will malfunction on some parts.
 375         * The flushes avoid this.
 376         */
 377        wr32(E1000_RAL(index), rar_low);
 378        wrfl();
 379        wr32(E1000_RAH(index), rar_high);
 380        wrfl();
 381}
 382
 383/**
 384 *  igb_mta_set - Set multicast filter table address
 385 *  @hw: pointer to the HW structure
 386 *  @hash_value: determines the MTA register and bit to set
 387 *
 388 *  The multicast table address is a register array of 32-bit registers.
 389 *  The hash_value is used to determine what register the bit is in, the
 390 *  current value is read, the new bit is OR'd in and the new value is
 391 *  written back into the register.
 392 **/
 393void igb_mta_set(struct e1000_hw *hw, u32 hash_value)
 394{
 395        u32 hash_bit, hash_reg, mta;
 396
 397        /* The MTA is a register array of 32-bit registers. It is
 398         * treated like an array of (32*mta_reg_count) bits.  We want to
 399         * set bit BitArray[hash_value]. So we figure out what register
 400         * the bit is in, read it, OR in the new bit, then write
 401         * back the new value.  The (hw->mac.mta_reg_count - 1) serves as a
 402         * mask to bits 31:5 of the hash value which gives us the
 403         * register we're modifying.  The hash bit within that register
 404         * is determined by the lower 5 bits of the hash value.
 405         */
 406        hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
 407        hash_bit = hash_value & 0x1F;
 408
 409        mta = array_rd32(E1000_MTA, hash_reg);
 410
 411        mta |= BIT(hash_bit);
 412
 413        array_wr32(E1000_MTA, hash_reg, mta);
 414        wrfl();
 415}
 416
 417/**
 418 *  igb_hash_mc_addr - Generate a multicast hash value
 419 *  @hw: pointer to the HW structure
 420 *  @mc_addr: pointer to a multicast address
 421 *
 422 *  Generates a multicast address hash value which is used to determine
 423 *  the multicast filter table array address and new table value.  See
 424 *  igb_mta_set()
 425 **/
 426static u32 igb_hash_mc_addr(struct e1000_hw *hw, u8 *mc_addr)
 427{
 428        u32 hash_value, hash_mask;
 429        u8 bit_shift = 0;
 430
 431        /* Register count multiplied by bits per register */
 432        hash_mask = (hw->mac.mta_reg_count * 32) - 1;
 433
 434        /* For a mc_filter_type of 0, bit_shift is the number of left-shifts
 435         * where 0xFF would still fall within the hash mask.
 436         */
 437        while (hash_mask >> bit_shift != 0xFF)
 438                bit_shift++;
 439
 440        /* The portion of the address that is used for the hash table
 441         * is determined by the mc_filter_type setting.
 442         * The algorithm is such that there is a total of 8 bits of shifting.
 443         * The bit_shift for a mc_filter_type of 0 represents the number of
 444         * left-shifts where the MSB of mc_addr[5] would still fall within
 445         * the hash_mask.  Case 0 does this exactly.  Since there are a total
 446         * of 8 bits of shifting, then mc_addr[4] will shift right the
 447         * remaining number of bits. Thus 8 - bit_shift.  The rest of the
 448         * cases are a variation of this algorithm...essentially raising the
 449         * number of bits to shift mc_addr[5] left, while still keeping the
 450         * 8-bit shifting total.
 451         *
 452         * For example, given the following Destination MAC Address and an
 453         * mta register count of 128 (thus a 4096-bit vector and 0xFFF mask),
 454         * we can see that the bit_shift for case 0 is 4.  These are the hash
 455         * values resulting from each mc_filter_type...
 456         * [0] [1] [2] [3] [4] [5]
 457         * 01  AA  00  12  34  56
 458         * LSB                 MSB
 459         *
 460         * case 0: hash_value = ((0x34 >> 4) | (0x56 << 4)) & 0xFFF = 0x563
 461         * case 1: hash_value = ((0x34 >> 3) | (0x56 << 5)) & 0xFFF = 0xAC6
 462         * case 2: hash_value = ((0x34 >> 2) | (0x56 << 6)) & 0xFFF = 0x163
 463         * case 3: hash_value = ((0x34 >> 0) | (0x56 << 8)) & 0xFFF = 0x634
 464         */
 465        switch (hw->mac.mc_filter_type) {
 466        default:
 467        case 0:
 468                break;
 469        case 1:
 470                bit_shift += 1;
 471                break;
 472        case 2:
 473                bit_shift += 2;
 474                break;
 475        case 3:
 476                bit_shift += 4;
 477                break;
 478        }
 479
 480        hash_value = hash_mask & (((mc_addr[4] >> (8 - bit_shift)) |
 481                                  (((u16) mc_addr[5]) << bit_shift)));
 482
 483        return hash_value;
 484}
 485
 486/**
 487 * igb_i21x_hw_doublecheck - double checks potential HW issue in i21X
 488 * @hw: pointer to the HW structure
 489 *
 490 * Checks if multicast array is wrote correctly
 491 * If not then rewrites again to register
 492 **/
 493static void igb_i21x_hw_doublecheck(struct e1000_hw *hw)
 494{
 495        bool is_failed;
 496        int i;
 497
 498        do {
 499                is_failed = false;
 500                for (i = hw->mac.mta_reg_count - 1; i >= 0; i--) {
 501                        if (array_rd32(E1000_MTA, i) != hw->mac.mta_shadow[i]) {
 502                                is_failed = true;
 503                                array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
 504                                wrfl();
 505                                break;
 506                        }
 507                }
 508        } while (is_failed);
 509}
 510
 511/**
 512 *  igb_update_mc_addr_list - Update Multicast addresses
 513 *  @hw: pointer to the HW structure
 514 *  @mc_addr_list: array of multicast addresses to program
 515 *  @mc_addr_count: number of multicast addresses to program
 516 *
 517 *  Updates entire Multicast Table Array.
 518 *  The caller must have a packed mc_addr_list of multicast addresses.
 519 **/
 520void igb_update_mc_addr_list(struct e1000_hw *hw,
 521                             u8 *mc_addr_list, u32 mc_addr_count)
 522{
 523        u32 hash_value, hash_bit, hash_reg;
 524        int i;
 525
 526        /* clear mta_shadow */
 527        memset(&hw->mac.mta_shadow, 0, sizeof(hw->mac.mta_shadow));
 528
 529        /* update mta_shadow from mc_addr_list */
 530        for (i = 0; (u32) i < mc_addr_count; i++) {
 531                hash_value = igb_hash_mc_addr(hw, mc_addr_list);
 532
 533                hash_reg = (hash_value >> 5) & (hw->mac.mta_reg_count - 1);
 534                hash_bit = hash_value & 0x1F;
 535
 536                hw->mac.mta_shadow[hash_reg] |= BIT(hash_bit);
 537                mc_addr_list += (ETH_ALEN);
 538        }
 539
 540        /* replace the entire MTA table */
 541        for (i = hw->mac.mta_reg_count - 1; i >= 0; i--)
 542                array_wr32(E1000_MTA, i, hw->mac.mta_shadow[i]);
 543        wrfl();
 544        if (hw->mac.type == e1000_i210 || hw->mac.type == e1000_i211)
 545                igb_i21x_hw_doublecheck(hw);
 546}
 547
 548/**
 549 *  igb_clear_hw_cntrs_base - Clear base hardware counters
 550 *  @hw: pointer to the HW structure
 551 *
 552 *  Clears the base hardware counters by reading the counter registers.
 553 **/
 554void igb_clear_hw_cntrs_base(struct e1000_hw *hw)
 555{
 556        rd32(E1000_CRCERRS);
 557        rd32(E1000_SYMERRS);
 558        rd32(E1000_MPC);
 559        rd32(E1000_SCC);
 560        rd32(E1000_ECOL);
 561        rd32(E1000_MCC);
 562        rd32(E1000_LATECOL);
 563        rd32(E1000_COLC);
 564        rd32(E1000_DC);
 565        rd32(E1000_SEC);
 566        rd32(E1000_RLEC);
 567        rd32(E1000_XONRXC);
 568        rd32(E1000_XONTXC);
 569        rd32(E1000_XOFFRXC);
 570        rd32(E1000_XOFFTXC);
 571        rd32(E1000_FCRUC);
 572        rd32(E1000_GPRC);
 573        rd32(E1000_BPRC);
 574        rd32(E1000_MPRC);
 575        rd32(E1000_GPTC);
 576        rd32(E1000_GORCL);
 577        rd32(E1000_GORCH);
 578        rd32(E1000_GOTCL);
 579        rd32(E1000_GOTCH);
 580        rd32(E1000_RNBC);
 581        rd32(E1000_RUC);
 582        rd32(E1000_RFC);
 583        rd32(E1000_ROC);
 584        rd32(E1000_RJC);
 585        rd32(E1000_TORL);
 586        rd32(E1000_TORH);
 587        rd32(E1000_TOTL);
 588        rd32(E1000_TOTH);
 589        rd32(E1000_TPR);
 590        rd32(E1000_TPT);
 591        rd32(E1000_MPTC);
 592        rd32(E1000_BPTC);
 593}
 594
 595/**
 596 *  igb_check_for_copper_link - Check for link (Copper)
 597 *  @hw: pointer to the HW structure
 598 *
 599 *  Checks to see of the link status of the hardware has changed.  If a
 600 *  change in link status has been detected, then we read the PHY registers
 601 *  to get the current speed/duplex if link exists.
 602 **/
 603s32 igb_check_for_copper_link(struct e1000_hw *hw)
 604{
 605        struct e1000_mac_info *mac = &hw->mac;
 606        s32 ret_val;
 607        bool link;
 608
 609        /* We only want to go out to the PHY registers to see if Auto-Neg
 610         * has completed and/or if our link status has changed.  The
 611         * get_link_status flag is set upon receiving a Link Status
 612         * Change or Rx Sequence Error interrupt.
 613         */
 614        if (!mac->get_link_status) {
 615                ret_val = 0;
 616                goto out;
 617        }
 618
 619        /* First we want to see if the MII Status Register reports
 620         * link.  If so, then we want to get the current speed/duplex
 621         * of the PHY.
 622         */
 623        ret_val = igb_phy_has_link(hw, 1, 0, &link);
 624        if (ret_val)
 625                goto out;
 626
 627        if (!link)
 628                goto out; /* No link detected */
 629
 630        mac->get_link_status = false;
 631
 632        /* Check if there was DownShift, must be checked
 633         * immediately after link-up
 634         */
 635        igb_check_downshift(hw);
 636
 637        /* If we are forcing speed/duplex, then we simply return since
 638         * we have already determined whether we have link or not.
 639         */
 640        if (!mac->autoneg) {
 641                ret_val = -E1000_ERR_CONFIG;
 642                goto out;
 643        }
 644
 645        /* Auto-Neg is enabled.  Auto Speed Detection takes care
 646         * of MAC speed/duplex configuration.  So we only need to
 647         * configure Collision Distance in the MAC.
 648         */
 649        igb_config_collision_dist(hw);
 650
 651        /* Configure Flow Control now that Auto-Neg has completed.
 652         * First, we need to restore the desired flow control
 653         * settings because we may have had to re-autoneg with a
 654         * different link partner.
 655         */
 656        ret_val = igb_config_fc_after_link_up(hw);
 657        if (ret_val)
 658                hw_dbg("Error configuring flow control\n");
 659
 660out:
 661        return ret_val;
 662}
 663
 664/**
 665 *  igb_setup_link - Setup flow control and link settings
 666 *  @hw: pointer to the HW structure
 667 *
 668 *  Determines which flow control settings to use, then configures flow
 669 *  control.  Calls the appropriate media-specific link configuration
 670 *  function.  Assuming the adapter has a valid link partner, a valid link
 671 *  should be established.  Assumes the hardware has previously been reset
 672 *  and the transmitter and receiver are not enabled.
 673 **/
 674s32 igb_setup_link(struct e1000_hw *hw)
 675{
 676        s32 ret_val = 0;
 677
 678        /* In the case of the phy reset being blocked, we already have a link.
 679         * We do not need to set it up again.
 680         */
 681        if (igb_check_reset_block(hw))
 682                goto out;
 683
 684        /* If requested flow control is set to default, set flow control
 685         * based on the EEPROM flow control settings.
 686         */
 687        if (hw->fc.requested_mode == e1000_fc_default) {
 688                ret_val = igb_set_default_fc(hw);
 689                if (ret_val)
 690                        goto out;
 691        }
 692
 693        /* We want to save off the original Flow Control configuration just
 694         * in case we get disconnected and then reconnected into a different
 695         * hub or switch with different Flow Control capabilities.
 696         */
 697        hw->fc.current_mode = hw->fc.requested_mode;
 698
 699        hw_dbg("After fix-ups FlowControl is now = %x\n", hw->fc.current_mode);
 700
 701        /* Call the necessary media_type subroutine to configure the link. */
 702        ret_val = hw->mac.ops.setup_physical_interface(hw);
 703        if (ret_val)
 704                goto out;
 705
 706        /* Initialize the flow control address, type, and PAUSE timer
 707         * registers to their default values.  This is done even if flow
 708         * control is disabled, because it does not hurt anything to
 709         * initialize these registers.
 710         */
 711        hw_dbg("Initializing the Flow Control address, type and timer regs\n");
 712        wr32(E1000_FCT, FLOW_CONTROL_TYPE);
 713        wr32(E1000_FCAH, FLOW_CONTROL_ADDRESS_HIGH);
 714        wr32(E1000_FCAL, FLOW_CONTROL_ADDRESS_LOW);
 715
 716        wr32(E1000_FCTTV, hw->fc.pause_time);
 717
 718        igb_set_fc_watermarks(hw);
 719
 720out:
 721
 722        return ret_val;
 723}
 724
 725/**
 726 *  igb_config_collision_dist - Configure collision distance
 727 *  @hw: pointer to the HW structure
 728 *
 729 *  Configures the collision distance to the default value and is used
 730 *  during link setup. Currently no func pointer exists and all
 731 *  implementations are handled in the generic version of this function.
 732 **/
 733void igb_config_collision_dist(struct e1000_hw *hw)
 734{
 735        u32 tctl;
 736
 737        tctl = rd32(E1000_TCTL);
 738
 739        tctl &= ~E1000_TCTL_COLD;
 740        tctl |= E1000_COLLISION_DISTANCE << E1000_COLD_SHIFT;
 741
 742        wr32(E1000_TCTL, tctl);
 743        wrfl();
 744}
 745
 746/**
 747 *  igb_set_fc_watermarks - Set flow control high/low watermarks
 748 *  @hw: pointer to the HW structure
 749 *
 750 *  Sets the flow control high/low threshold (watermark) registers.  If
 751 *  flow control XON frame transmission is enabled, then set XON frame
 752 *  tansmission as well.
 753 **/
 754static void igb_set_fc_watermarks(struct e1000_hw *hw)
 755{
 756        u32 fcrtl = 0, fcrth = 0;
 757
 758        /* Set the flow control receive threshold registers.  Normally,
 759         * these registers will be set to a default threshold that may be
 760         * adjusted later by the driver's runtime code.  However, if the
 761         * ability to transmit pause frames is not enabled, then these
 762         * registers will be set to 0.
 763         */
 764        if (hw->fc.current_mode & e1000_fc_tx_pause) {
 765                /* We need to set up the Receive Threshold high and low water
 766                 * marks as well as (optionally) enabling the transmission of
 767                 * XON frames.
 768                 */
 769                fcrtl = hw->fc.low_water;
 770                if (hw->fc.send_xon)
 771                        fcrtl |= E1000_FCRTL_XONE;
 772
 773                fcrth = hw->fc.high_water;
 774        }
 775        wr32(E1000_FCRTL, fcrtl);
 776        wr32(E1000_FCRTH, fcrth);
 777}
 778
 779/**
 780 *  igb_set_default_fc - Set flow control default values
 781 *  @hw: pointer to the HW structure
 782 *
 783 *  Read the EEPROM for the default values for flow control and store the
 784 *  values.
 785 **/
 786static s32 igb_set_default_fc(struct e1000_hw *hw)
 787{
 788        s32 ret_val = 0;
 789        u16 lan_offset;
 790        u16 nvm_data;
 791
 792        /* Read and store word 0x0F of the EEPROM. This word contains bits
 793         * that determine the hardware's default PAUSE (flow control) mode,
 794         * a bit that determines whether the HW defaults to enabling or
 795         * disabling auto-negotiation, and the direction of the
 796         * SW defined pins. If there is no SW over-ride of the flow
 797         * control setting, then the variable hw->fc will
 798         * be initialized based on a value in the EEPROM.
 799         */
 800        if (hw->mac.type == e1000_i350)
 801                lan_offset = NVM_82580_LAN_FUNC_OFFSET(hw->bus.func);
 802        else
 803                lan_offset = 0;
 804
 805        ret_val = hw->nvm.ops.read(hw, NVM_INIT_CONTROL2_REG + lan_offset,
 806                                   1, &nvm_data);
 807        if (ret_val) {
 808                hw_dbg("NVM Read Error\n");
 809                goto out;
 810        }
 811
 812        if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == 0)
 813                hw->fc.requested_mode = e1000_fc_none;
 814        else if ((nvm_data & NVM_WORD0F_PAUSE_MASK) == NVM_WORD0F_ASM_DIR)
 815                hw->fc.requested_mode = e1000_fc_tx_pause;
 816        else
 817                hw->fc.requested_mode = e1000_fc_full;
 818
 819out:
 820        return ret_val;
 821}
 822
 823/**
 824 *  igb_force_mac_fc - Force the MAC's flow control settings
 825 *  @hw: pointer to the HW structure
 826 *
 827 *  Force the MAC's flow control settings.  Sets the TFCE and RFCE bits in the
 828 *  device control register to reflect the adapter settings.  TFCE and RFCE
 829 *  need to be explicitly set by software when a copper PHY is used because
 830 *  autonegotiation is managed by the PHY rather than the MAC.  Software must
 831 *  also configure these bits when link is forced on a fiber connection.
 832 **/
 833s32 igb_force_mac_fc(struct e1000_hw *hw)
 834{
 835        u32 ctrl;
 836        s32 ret_val = 0;
 837
 838        ctrl = rd32(E1000_CTRL);
 839
 840        /* Because we didn't get link via the internal auto-negotiation
 841         * mechanism (we either forced link or we got link via PHY
 842         * auto-neg), we have to manually enable/disable transmit an
 843         * receive flow control.
 844         *
 845         * The "Case" statement below enables/disable flow control
 846         * according to the "hw->fc.current_mode" parameter.
 847         *
 848         * The possible values of the "fc" parameter are:
 849         *      0:  Flow control is completely disabled
 850         *      1:  Rx flow control is enabled (we can receive pause
 851         *          frames but not send pause frames).
 852         *      2:  Tx flow control is enabled (we can send pause frames
 853         *          frames but we do not receive pause frames).
 854         *      3:  Both Rx and TX flow control (symmetric) is enabled.
 855         *  other:  No other values should be possible at this point.
 856         */
 857        hw_dbg("hw->fc.current_mode = %u\n", hw->fc.current_mode);
 858
 859        switch (hw->fc.current_mode) {
 860        case e1000_fc_none:
 861                ctrl &= (~(E1000_CTRL_TFCE | E1000_CTRL_RFCE));
 862                break;
 863        case e1000_fc_rx_pause:
 864                ctrl &= (~E1000_CTRL_TFCE);
 865                ctrl |= E1000_CTRL_RFCE;
 866                break;
 867        case e1000_fc_tx_pause:
 868                ctrl &= (~E1000_CTRL_RFCE);
 869                ctrl |= E1000_CTRL_TFCE;
 870                break;
 871        case e1000_fc_full:
 872                ctrl |= (E1000_CTRL_TFCE | E1000_CTRL_RFCE);
 873                break;
 874        default:
 875                hw_dbg("Flow control param set incorrectly\n");
 876                ret_val = -E1000_ERR_CONFIG;
 877                goto out;
 878        }
 879
 880        wr32(E1000_CTRL, ctrl);
 881
 882out:
 883        return ret_val;
 884}
 885
 886/**
 887 *  igb_config_fc_after_link_up - Configures flow control after link
 888 *  @hw: pointer to the HW structure
 889 *
 890 *  Checks the status of auto-negotiation after link up to ensure that the
 891 *  speed and duplex were not forced.  If the link needed to be forced, then
 892 *  flow control needs to be forced also.  If auto-negotiation is enabled
 893 *  and did not fail, then we configure flow control based on our link
 894 *  partner.
 895 **/
 896s32 igb_config_fc_after_link_up(struct e1000_hw *hw)
 897{
 898        struct e1000_mac_info *mac = &hw->mac;
 899        s32 ret_val = 0;
 900        u32 pcs_status_reg, pcs_adv_reg, pcs_lp_ability_reg, pcs_ctrl_reg;
 901        u16 mii_status_reg, mii_nway_adv_reg, mii_nway_lp_ability_reg;
 902        u16 speed, duplex;
 903
 904        /* Check for the case where we have fiber media and auto-neg failed
 905         * so we had to force link.  In this case, we need to force the
 906         * configuration of the MAC to match the "fc" parameter.
 907         */
 908        if (mac->autoneg_failed) {
 909                if (hw->phy.media_type == e1000_media_type_internal_serdes)
 910                        ret_val = igb_force_mac_fc(hw);
 911        } else {
 912                if (hw->phy.media_type == e1000_media_type_copper)
 913                        ret_val = igb_force_mac_fc(hw);
 914        }
 915
 916        if (ret_val) {
 917                hw_dbg("Error forcing flow control settings\n");
 918                goto out;
 919        }
 920
 921        /* Check for the case where we have copper media and auto-neg is
 922         * enabled.  In this case, we need to check and see if Auto-Neg
 923         * has completed, and if so, how the PHY and link partner has
 924         * flow control configured.
 925         */
 926        if ((hw->phy.media_type == e1000_media_type_copper) && mac->autoneg) {
 927                /* Read the MII Status Register and check to see if AutoNeg
 928                 * has completed.  We read this twice because this reg has
 929                 * some "sticky" (latched) bits.
 930                 */
 931                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
 932                                                   &mii_status_reg);
 933                if (ret_val)
 934                        goto out;
 935                ret_val = hw->phy.ops.read_reg(hw, PHY_STATUS,
 936                                                   &mii_status_reg);
 937                if (ret_val)
 938                        goto out;
 939
 940                if (!(mii_status_reg & MII_SR_AUTONEG_COMPLETE)) {
 941                        hw_dbg("Copper PHY and Auto Neg has not completed.\n");
 942                        goto out;
 943                }
 944
 945                /* The AutoNeg process has completed, so we now need to
 946                 * read both the Auto Negotiation Advertisement
 947                 * Register (Address 4) and the Auto_Negotiation Base
 948                 * Page Ability Register (Address 5) to determine how
 949                 * flow control was negotiated.
 950                 */
 951                ret_val = hw->phy.ops.read_reg(hw, PHY_AUTONEG_ADV,
 952                                            &mii_nway_adv_reg);
 953                if (ret_val)
 954                        goto out;
 955                ret_val = hw->phy.ops.read_reg(hw, PHY_LP_ABILITY,
 956                                            &mii_nway_lp_ability_reg);
 957                if (ret_val)
 958                        goto out;
 959
 960                /* Two bits in the Auto Negotiation Advertisement Register
 961                 * (Address 4) and two bits in the Auto Negotiation Base
 962                 * Page Ability Register (Address 5) determine flow control
 963                 * for both the PHY and the link partner.  The following
 964                 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
 965                 * 1999, describes these PAUSE resolution bits and how flow
 966                 * control is determined based upon these settings.
 967                 * NOTE:  DC = Don't Care
 968                 *
 969                 *   LOCAL DEVICE  |   LINK PARTNER
 970                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
 971                 *-------|---------|-------|---------|--------------------
 972                 *   0   |    0    |  DC   |   DC    | e1000_fc_none
 973                 *   0   |    1    |   0   |   DC    | e1000_fc_none
 974                 *   0   |    1    |   1   |    0    | e1000_fc_none
 975                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
 976                 *   1   |    0    |   0   |   DC    | e1000_fc_none
 977                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
 978                 *   1   |    1    |   0   |    0    | e1000_fc_none
 979                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
 980                 *
 981                 * Are both PAUSE bits set to 1?  If so, this implies
 982                 * Symmetric Flow Control is enabled at both ends.  The
 983                 * ASM_DIR bits are irrelevant per the spec.
 984                 *
 985                 * For Symmetric Flow Control:
 986                 *
 987                 *   LOCAL DEVICE  |   LINK PARTNER
 988                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
 989                 *-------|---------|-------|---------|--------------------
 990                 *   1   |   DC    |   1   |   DC    | E1000_fc_full
 991                 *
 992                 */
 993                if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
 994                    (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE)) {
 995                        /* Now we need to check if the user selected RX ONLY
 996                         * of pause frames.  In this case, we had to advertise
 997                         * FULL flow control because we could not advertise RX
 998                         * ONLY. Hence, we must now check to see if we need to
 999                         * turn OFF  the TRANSMISSION of PAUSE frames.
1000                         */
1001                        if (hw->fc.requested_mode == e1000_fc_full) {
1002                                hw->fc.current_mode = e1000_fc_full;
1003                                hw_dbg("Flow Control = FULL.\n");
1004                        } else {
1005                                hw->fc.current_mode = e1000_fc_rx_pause;
1006                                hw_dbg("Flow Control = RX PAUSE frames only.\n");
1007                        }
1008                }
1009                /* For receiving PAUSE frames ONLY.
1010                 *
1011                 *   LOCAL DEVICE  |   LINK PARTNER
1012                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1013                 *-------|---------|-------|---------|--------------------
1014                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1015                 */
1016                else if (!(mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1017                          (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1018                          (mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1019                          (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1020                        hw->fc.current_mode = e1000_fc_tx_pause;
1021                        hw_dbg("Flow Control = TX PAUSE frames only.\n");
1022                }
1023                /* For transmitting PAUSE frames ONLY.
1024                 *
1025                 *   LOCAL DEVICE  |   LINK PARTNER
1026                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1027                 *-------|---------|-------|---------|--------------------
1028                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1029                 */
1030                else if ((mii_nway_adv_reg & NWAY_AR_PAUSE) &&
1031                         (mii_nway_adv_reg & NWAY_AR_ASM_DIR) &&
1032                         !(mii_nway_lp_ability_reg & NWAY_LPAR_PAUSE) &&
1033                         (mii_nway_lp_ability_reg & NWAY_LPAR_ASM_DIR)) {
1034                        hw->fc.current_mode = e1000_fc_rx_pause;
1035                        hw_dbg("Flow Control = RX PAUSE frames only.\n");
1036                }
1037                /* Per the IEEE spec, at this point flow control should be
1038                 * disabled.  However, we want to consider that we could
1039                 * be connected to a legacy switch that doesn't advertise
1040                 * desired flow control, but can be forced on the link
1041                 * partner.  So if we advertised no flow control, that is
1042                 * what we will resolve to.  If we advertised some kind of
1043                 * receive capability (Rx Pause Only or Full Flow Control)
1044                 * and the link partner advertised none, we will configure
1045                 * ourselves to enable Rx Flow Control only.  We can do
1046                 * this safely for two reasons:  If the link partner really
1047                 * didn't want flow control enabled, and we enable Rx, no
1048                 * harm done since we won't be receiving any PAUSE frames
1049                 * anyway.  If the intent on the link partner was to have
1050                 * flow control enabled, then by us enabling RX only, we
1051                 * can at least receive pause frames and process them.
1052                 * This is a good idea because in most cases, since we are
1053                 * predominantly a server NIC, more times than not we will
1054                 * be asked to delay transmission of packets than asking
1055                 * our link partner to pause transmission of frames.
1056                 */
1057                else if ((hw->fc.requested_mode == e1000_fc_none) ||
1058                         (hw->fc.requested_mode == e1000_fc_tx_pause) ||
1059                         (hw->fc.strict_ieee)) {
1060                        hw->fc.current_mode = e1000_fc_none;
1061                        hw_dbg("Flow Control = NONE.\n");
1062                } else {
1063                        hw->fc.current_mode = e1000_fc_rx_pause;
1064                        hw_dbg("Flow Control = RX PAUSE frames only.\n");
1065                }
1066
1067                /* Now we need to do one last check...  If we auto-
1068                 * negotiated to HALF DUPLEX, flow control should not be
1069                 * enabled per IEEE 802.3 spec.
1070                 */
1071                ret_val = hw->mac.ops.get_speed_and_duplex(hw, &speed, &duplex);
1072                if (ret_val) {
1073                        hw_dbg("Error getting link speed and duplex\n");
1074                        goto out;
1075                }
1076
1077                if (duplex == HALF_DUPLEX)
1078                        hw->fc.current_mode = e1000_fc_none;
1079
1080                /* Now we call a subroutine to actually force the MAC
1081                 * controller to use the correct flow control settings.
1082                 */
1083                ret_val = igb_force_mac_fc(hw);
1084                if (ret_val) {
1085                        hw_dbg("Error forcing flow control settings\n");
1086                        goto out;
1087                }
1088        }
1089        /* Check for the case where we have SerDes media and auto-neg is
1090         * enabled.  In this case, we need to check and see if Auto-Neg
1091         * has completed, and if so, how the PHY and link partner has
1092         * flow control configured.
1093         */
1094        if ((hw->phy.media_type == e1000_media_type_internal_serdes)
1095                && mac->autoneg) {
1096                /* Read the PCS_LSTS and check to see if AutoNeg
1097                 * has completed.
1098                 */
1099                pcs_status_reg = rd32(E1000_PCS_LSTAT);
1100
1101                if (!(pcs_status_reg & E1000_PCS_LSTS_AN_COMPLETE)) {
1102                        hw_dbg("PCS Auto Neg has not completed.\n");
1103                        return ret_val;
1104                }
1105
1106                /* The AutoNeg process has completed, so we now need to
1107                 * read both the Auto Negotiation Advertisement
1108                 * Register (PCS_ANADV) and the Auto_Negotiation Base
1109                 * Page Ability Register (PCS_LPAB) to determine how
1110                 * flow control was negotiated.
1111                 */
1112                pcs_adv_reg = rd32(E1000_PCS_ANADV);
1113                pcs_lp_ability_reg = rd32(E1000_PCS_LPAB);
1114
1115                /* Two bits in the Auto Negotiation Advertisement Register
1116                 * (PCS_ANADV) and two bits in the Auto Negotiation Base
1117                 * Page Ability Register (PCS_LPAB) determine flow control
1118                 * for both the PHY and the link partner.  The following
1119                 * table, taken out of the IEEE 802.3ab/D6.0 dated March 25,
1120                 * 1999, describes these PAUSE resolution bits and how flow
1121                 * control is determined based upon these settings.
1122                 * NOTE:  DC = Don't Care
1123                 *
1124                 *   LOCAL DEVICE  |   LINK PARTNER
1125                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | NIC Resolution
1126                 *-------|---------|-------|---------|--------------------
1127                 *   0   |    0    |  DC   |   DC    | e1000_fc_none
1128                 *   0   |    1    |   0   |   DC    | e1000_fc_none
1129                 *   0   |    1    |   1   |    0    | e1000_fc_none
1130                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1131                 *   1   |    0    |   0   |   DC    | e1000_fc_none
1132                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1133                 *   1   |    1    |   0   |    0    | e1000_fc_none
1134                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1135                 *
1136                 * Are both PAUSE bits set to 1?  If so, this implies
1137                 * Symmetric Flow Control is enabled at both ends.  The
1138                 * ASM_DIR bits are irrelevant per the spec.
1139                 *
1140                 * For Symmetric Flow Control:
1141                 *
1142                 *   LOCAL DEVICE  |   LINK PARTNER
1143                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1144                 *-------|---------|-------|---------|--------------------
1145                 *   1   |   DC    |   1   |   DC    | e1000_fc_full
1146                 *
1147                 */
1148                if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1149                    (pcs_lp_ability_reg & E1000_TXCW_PAUSE)) {
1150                        /* Now we need to check if the user selected Rx ONLY
1151                         * of pause frames.  In this case, we had to advertise
1152                         * FULL flow control because we could not advertise Rx
1153                         * ONLY. Hence, we must now check to see if we need to
1154                         * turn OFF the TRANSMISSION of PAUSE frames.
1155                         */
1156                        if (hw->fc.requested_mode == e1000_fc_full) {
1157                                hw->fc.current_mode = e1000_fc_full;
1158                                hw_dbg("Flow Control = FULL.\n");
1159                        } else {
1160                                hw->fc.current_mode = e1000_fc_rx_pause;
1161                                hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1162                        }
1163                }
1164                /* For receiving PAUSE frames ONLY.
1165                 *
1166                 *   LOCAL DEVICE  |   LINK PARTNER
1167                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1168                 *-------|---------|-------|---------|--------------------
1169                 *   0   |    1    |   1   |    1    | e1000_fc_tx_pause
1170                 */
1171                else if (!(pcs_adv_reg & E1000_TXCW_PAUSE) &&
1172                          (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1173                          (pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1174                          (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1175                        hw->fc.current_mode = e1000_fc_tx_pause;
1176                        hw_dbg("Flow Control = Tx PAUSE frames only.\n");
1177                }
1178                /* For transmitting PAUSE frames ONLY.
1179                 *
1180                 *   LOCAL DEVICE  |   LINK PARTNER
1181                 * PAUSE | ASM_DIR | PAUSE | ASM_DIR | Result
1182                 *-------|---------|-------|---------|--------------------
1183                 *   1   |    1    |   0   |    1    | e1000_fc_rx_pause
1184                 */
1185                else if ((pcs_adv_reg & E1000_TXCW_PAUSE) &&
1186                         (pcs_adv_reg & E1000_TXCW_ASM_DIR) &&
1187                         !(pcs_lp_ability_reg & E1000_TXCW_PAUSE) &&
1188                         (pcs_lp_ability_reg & E1000_TXCW_ASM_DIR)) {
1189                        hw->fc.current_mode = e1000_fc_rx_pause;
1190                        hw_dbg("Flow Control = Rx PAUSE frames only.\n");
1191                } else {
1192                        /* Per the IEEE spec, at this point flow control
1193                         * should be disabled.
1194                         */
1195                        hw->fc.current_mode = e1000_fc_none;
1196                        hw_dbg("Flow Control = NONE.\n");
1197                }
1198
1199                /* Now we call a subroutine to actually force the MAC
1200                 * controller to use the correct flow control settings.
1201                 */
1202                pcs_ctrl_reg = rd32(E1000_PCS_LCTL);
1203                pcs_ctrl_reg |= E1000_PCS_LCTL_FORCE_FCTRL;
1204                wr32(E1000_PCS_LCTL, pcs_ctrl_reg);
1205
1206                ret_val = igb_force_mac_fc(hw);
1207                if (ret_val) {
1208                        hw_dbg("Error forcing flow control settings\n");
1209                        return ret_val;
1210                }
1211        }
1212
1213out:
1214        return ret_val;
1215}
1216
1217/**
1218 *  igb_get_speed_and_duplex_copper - Retrieve current speed/duplex
1219 *  @hw: pointer to the HW structure
1220 *  @speed: stores the current speed
1221 *  @duplex: stores the current duplex
1222 *
1223 *  Read the status register for the current speed/duplex and store the current
1224 *  speed and duplex for copper connections.
1225 **/
1226s32 igb_get_speed_and_duplex_copper(struct e1000_hw *hw, u16 *speed,
1227                                      u16 *duplex)
1228{
1229        u32 status;
1230
1231        status = rd32(E1000_STATUS);
1232        if (status & E1000_STATUS_SPEED_1000) {
1233                *speed = SPEED_1000;
1234                hw_dbg("1000 Mbs, ");
1235        } else if (status & E1000_STATUS_SPEED_100) {
1236                *speed = SPEED_100;
1237                hw_dbg("100 Mbs, ");
1238        } else {
1239                *speed = SPEED_10;
1240                hw_dbg("10 Mbs, ");
1241        }
1242
1243        if (status & E1000_STATUS_FD) {
1244                *duplex = FULL_DUPLEX;
1245                hw_dbg("Full Duplex\n");
1246        } else {
1247                *duplex = HALF_DUPLEX;
1248                hw_dbg("Half Duplex\n");
1249        }
1250
1251        return 0;
1252}
1253
1254/**
1255 *  igb_get_hw_semaphore - Acquire hardware semaphore
1256 *  @hw: pointer to the HW structure
1257 *
1258 *  Acquire the HW semaphore to access the PHY or NVM
1259 **/
1260s32 igb_get_hw_semaphore(struct e1000_hw *hw)
1261{
1262        u32 swsm;
1263        s32 ret_val = 0;
1264        s32 timeout = hw->nvm.word_size + 1;
1265        s32 i = 0;
1266
1267        /* Get the SW semaphore */
1268        while (i < timeout) {
1269                swsm = rd32(E1000_SWSM);
1270                if (!(swsm & E1000_SWSM_SMBI))
1271                        break;
1272
1273                udelay(50);
1274                i++;
1275        }
1276
1277        if (i == timeout) {
1278                hw_dbg("Driver can't access device - SMBI bit is set.\n");
1279                ret_val = -E1000_ERR_NVM;
1280                goto out;
1281        }
1282
1283        /* Get the FW semaphore. */
1284        for (i = 0; i < timeout; i++) {
1285                swsm = rd32(E1000_SWSM);
1286                wr32(E1000_SWSM, swsm | E1000_SWSM_SWESMBI);
1287
1288                /* Semaphore acquired if bit latched */
1289                if (rd32(E1000_SWSM) & E1000_SWSM_SWESMBI)
1290                        break;
1291
1292                udelay(50);
1293        }
1294
1295        if (i == timeout) {
1296                /* Release semaphores */
1297                igb_put_hw_semaphore(hw);
1298                hw_dbg("Driver can't access the NVM\n");
1299                ret_val = -E1000_ERR_NVM;
1300                goto out;
1301        }
1302
1303out:
1304        return ret_val;
1305}
1306
1307/**
1308 *  igb_put_hw_semaphore - Release hardware semaphore
1309 *  @hw: pointer to the HW structure
1310 *
1311 *  Release hardware semaphore used to access the PHY or NVM
1312 **/
1313void igb_put_hw_semaphore(struct e1000_hw *hw)
1314{
1315        u32 swsm;
1316
1317        swsm = rd32(E1000_SWSM);
1318
1319        swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
1320
1321        wr32(E1000_SWSM, swsm);
1322}
1323
1324/**
1325 *  igb_get_auto_rd_done - Check for auto read completion
1326 *  @hw: pointer to the HW structure
1327 *
1328 *  Check EEPROM for Auto Read done bit.
1329 **/
1330s32 igb_get_auto_rd_done(struct e1000_hw *hw)
1331{
1332        s32 i = 0;
1333        s32 ret_val = 0;
1334
1335
1336        while (i < AUTO_READ_DONE_TIMEOUT) {
1337                if (rd32(E1000_EECD) & E1000_EECD_AUTO_RD)
1338                        break;
1339                usleep_range(1000, 2000);
1340                i++;
1341        }
1342
1343        if (i == AUTO_READ_DONE_TIMEOUT) {
1344                hw_dbg("Auto read by HW from NVM has not completed.\n");
1345                ret_val = -E1000_ERR_RESET;
1346                goto out;
1347        }
1348
1349out:
1350        return ret_val;
1351}
1352
1353/**
1354 *  igb_valid_led_default - Verify a valid default LED config
1355 *  @hw: pointer to the HW structure
1356 *  @data: pointer to the NVM (EEPROM)
1357 *
1358 *  Read the EEPROM for the current default LED configuration.  If the
1359 *  LED configuration is not valid, set to a valid LED configuration.
1360 **/
1361static s32 igb_valid_led_default(struct e1000_hw *hw, u16 *data)
1362{
1363        s32 ret_val;
1364
1365        ret_val = hw->nvm.ops.read(hw, NVM_ID_LED_SETTINGS, 1, data);
1366        if (ret_val) {
1367                hw_dbg("NVM Read Error\n");
1368                goto out;
1369        }
1370
1371        if (*data == ID_LED_RESERVED_0000 || *data == ID_LED_RESERVED_FFFF) {
1372                switch (hw->phy.media_type) {
1373                case e1000_media_type_internal_serdes:
1374                        *data = ID_LED_DEFAULT_82575_SERDES;
1375                        break;
1376                case e1000_media_type_copper:
1377                default:
1378                        *data = ID_LED_DEFAULT;
1379                        break;
1380                }
1381        }
1382out:
1383        return ret_val;
1384}
1385
1386/**
1387 *  igb_id_led_init -
1388 *  @hw: pointer to the HW structure
1389 *
1390 **/
1391s32 igb_id_led_init(struct e1000_hw *hw)
1392{
1393        struct e1000_mac_info *mac = &hw->mac;
1394        s32 ret_val;
1395        const u32 ledctl_mask = 0x000000FF;
1396        const u32 ledctl_on = E1000_LEDCTL_MODE_LED_ON;
1397        const u32 ledctl_off = E1000_LEDCTL_MODE_LED_OFF;
1398        u16 data, i, temp;
1399        const u16 led_mask = 0x0F;
1400
1401        /* i210 and i211 devices have different LED mechanism */
1402        if ((hw->mac.type == e1000_i210) ||
1403            (hw->mac.type == e1000_i211))
1404                ret_val = igb_valid_led_default_i210(hw, &data);
1405        else
1406                ret_val = igb_valid_led_default(hw, &data);
1407
1408        if (ret_val)
1409                goto out;
1410
1411        mac->ledctl_default = rd32(E1000_LEDCTL);
1412        mac->ledctl_mode1 = mac->ledctl_default;
1413        mac->ledctl_mode2 = mac->ledctl_default;
1414
1415        for (i = 0; i < 4; i++) {
1416                temp = (data >> (i << 2)) & led_mask;
1417                switch (temp) {
1418                case ID_LED_ON1_DEF2:
1419                case ID_LED_ON1_ON2:
1420                case ID_LED_ON1_OFF2:
1421                        mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1422                        mac->ledctl_mode1 |= ledctl_on << (i << 3);
1423                        break;
1424                case ID_LED_OFF1_DEF2:
1425                case ID_LED_OFF1_ON2:
1426                case ID_LED_OFF1_OFF2:
1427                        mac->ledctl_mode1 &= ~(ledctl_mask << (i << 3));
1428                        mac->ledctl_mode1 |= ledctl_off << (i << 3);
1429                        break;
1430                default:
1431                        /* Do nothing */
1432                        break;
1433                }
1434                switch (temp) {
1435                case ID_LED_DEF1_ON2:
1436                case ID_LED_ON1_ON2:
1437                case ID_LED_OFF1_ON2:
1438                        mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1439                        mac->ledctl_mode2 |= ledctl_on << (i << 3);
1440                        break;
1441                case ID_LED_DEF1_OFF2:
1442                case ID_LED_ON1_OFF2:
1443                case ID_LED_OFF1_OFF2:
1444                        mac->ledctl_mode2 &= ~(ledctl_mask << (i << 3));
1445                        mac->ledctl_mode2 |= ledctl_off << (i << 3);
1446                        break;
1447                default:
1448                        /* Do nothing */
1449                        break;
1450                }
1451        }
1452
1453out:
1454        return ret_val;
1455}
1456
1457/**
1458 *  igb_cleanup_led - Set LED config to default operation
1459 *  @hw: pointer to the HW structure
1460 *
1461 *  Remove the current LED configuration and set the LED configuration
1462 *  to the default value, saved from the EEPROM.
1463 **/
1464s32 igb_cleanup_led(struct e1000_hw *hw)
1465{
1466        wr32(E1000_LEDCTL, hw->mac.ledctl_default);
1467        return 0;
1468}
1469
1470/**
1471 *  igb_blink_led - Blink LED
1472 *  @hw: pointer to the HW structure
1473 *
1474 *  Blink the led's which are set to be on.
1475 **/
1476s32 igb_blink_led(struct e1000_hw *hw)
1477{
1478        u32 ledctl_blink = 0;
1479        u32 i;
1480
1481        if (hw->phy.media_type == e1000_media_type_fiber) {
1482                /* always blink LED0 for PCI-E fiber */
1483                ledctl_blink = E1000_LEDCTL_LED0_BLINK |
1484                     (E1000_LEDCTL_MODE_LED_ON << E1000_LEDCTL_LED0_MODE_SHIFT);
1485        } else {
1486                /* Set the blink bit for each LED that's "on" (0x0E)
1487                 * (or "off" if inverted) in ledctl_mode2.  The blink
1488                 * logic in hardware only works when mode is set to "on"
1489                 * so it must be changed accordingly when the mode is
1490                 * "off" and inverted.
1491                 */
1492                ledctl_blink = hw->mac.ledctl_mode2;
1493                for (i = 0; i < 32; i += 8) {
1494                        u32 mode = (hw->mac.ledctl_mode2 >> i) &
1495                            E1000_LEDCTL_LED0_MODE_MASK;
1496                        u32 led_default = hw->mac.ledctl_default >> i;
1497
1498                        if ((!(led_default & E1000_LEDCTL_LED0_IVRT) &&
1499                             (mode == E1000_LEDCTL_MODE_LED_ON)) ||
1500                            ((led_default & E1000_LEDCTL_LED0_IVRT) &&
1501                             (mode == E1000_LEDCTL_MODE_LED_OFF))) {
1502                                ledctl_blink &=
1503                                    ~(E1000_LEDCTL_LED0_MODE_MASK << i);
1504                                ledctl_blink |= (E1000_LEDCTL_LED0_BLINK |
1505                                                 E1000_LEDCTL_MODE_LED_ON) << i;
1506                        }
1507                }
1508        }
1509
1510        wr32(E1000_LEDCTL, ledctl_blink);
1511
1512        return 0;
1513}
1514
1515/**
1516 *  igb_led_off - Turn LED off
1517 *  @hw: pointer to the HW structure
1518 *
1519 *  Turn LED off.
1520 **/
1521s32 igb_led_off(struct e1000_hw *hw)
1522{
1523        switch (hw->phy.media_type) {
1524        case e1000_media_type_copper:
1525                wr32(E1000_LEDCTL, hw->mac.ledctl_mode1);
1526                break;
1527        default:
1528                break;
1529        }
1530
1531        return 0;
1532}
1533
1534/**
1535 *  igb_disable_pcie_master - Disables PCI-express master access
1536 *  @hw: pointer to the HW structure
1537 *
1538 *  Returns 0 (0) if successful, else returns -10
1539 *  (-E1000_ERR_MASTER_REQUESTS_PENDING) if master disable bit has not caused
1540 *  the master requests to be disabled.
1541 *
1542 *  Disables PCI-Express master access and verifies there are no pending
1543 *  requests.
1544 **/
1545s32 igb_disable_pcie_master(struct e1000_hw *hw)
1546{
1547        u32 ctrl;
1548        s32 timeout = MASTER_DISABLE_TIMEOUT;
1549        s32 ret_val = 0;
1550
1551        if (hw->bus.type != e1000_bus_type_pci_express)
1552                goto out;
1553
1554        ctrl = rd32(E1000_CTRL);
1555        ctrl |= E1000_CTRL_GIO_MASTER_DISABLE;
1556        wr32(E1000_CTRL, ctrl);
1557
1558        while (timeout) {
1559                if (!(rd32(E1000_STATUS) &
1560                      E1000_STATUS_GIO_MASTER_ENABLE))
1561                        break;
1562                udelay(100);
1563                timeout--;
1564        }
1565
1566        if (!timeout) {
1567                hw_dbg("Master requests are pending.\n");
1568                ret_val = -E1000_ERR_MASTER_REQUESTS_PENDING;
1569                goto out;
1570        }
1571
1572out:
1573        return ret_val;
1574}
1575
1576/**
1577 *  igb_validate_mdi_setting - Verify MDI/MDIx settings
1578 *  @hw: pointer to the HW structure
1579 *
1580 *  Verify that when not using auto-negotitation that MDI/MDIx is correctly
1581 *  set, which is forced to MDI mode only.
1582 **/
1583s32 igb_validate_mdi_setting(struct e1000_hw *hw)
1584{
1585        s32 ret_val = 0;
1586
1587        /* All MDI settings are supported on 82580 and newer. */
1588        if (hw->mac.type >= e1000_82580)
1589                goto out;
1590
1591        if (!hw->mac.autoneg && (hw->phy.mdix == 0 || hw->phy.mdix == 3)) {
1592                hw_dbg("Invalid MDI setting detected\n");
1593                hw->phy.mdix = 1;
1594                ret_val = -E1000_ERR_CONFIG;
1595                goto out;
1596        }
1597
1598out:
1599        return ret_val;
1600}
1601
1602/**
1603 *  igb_write_8bit_ctrl_reg - Write a 8bit CTRL register
1604 *  @hw: pointer to the HW structure
1605 *  @reg: 32bit register offset such as E1000_SCTL
1606 *  @offset: register offset to write to
1607 *  @data: data to write at register offset
1608 *
1609 *  Writes an address/data control type register.  There are several of these
1610 *  and they all have the format address << 8 | data and bit 31 is polled for
1611 *  completion.
1612 **/
1613s32 igb_write_8bit_ctrl_reg(struct e1000_hw *hw, u32 reg,
1614                              u32 offset, u8 data)
1615{
1616        u32 i, regvalue = 0;
1617        s32 ret_val = 0;
1618
1619        /* Set up the address and data */
1620        regvalue = ((u32)data) | (offset << E1000_GEN_CTL_ADDRESS_SHIFT);
1621        wr32(reg, regvalue);
1622
1623        /* Poll the ready bit to see if the MDI read completed */
1624        for (i = 0; i < E1000_GEN_POLL_TIMEOUT; i++) {
1625                udelay(5);
1626                regvalue = rd32(reg);
1627                if (regvalue & E1000_GEN_CTL_READY)
1628                        break;
1629        }
1630        if (!(regvalue & E1000_GEN_CTL_READY)) {
1631                hw_dbg("Reg %08x did not indicate ready\n", reg);
1632                ret_val = -E1000_ERR_PHY;
1633                goto out;
1634        }
1635
1636out:
1637        return ret_val;
1638}
1639
1640/**
1641 *  igb_enable_mng_pass_thru - Enable processing of ARP's
1642 *  @hw: pointer to the HW structure
1643 *
1644 *  Verifies the hardware needs to leave interface enabled so that frames can
1645 *  be directed to and from the management interface.
1646 **/
1647bool igb_enable_mng_pass_thru(struct e1000_hw *hw)
1648{
1649        u32 manc;
1650        u32 fwsm, factps;
1651        bool ret_val = false;
1652
1653        if (!hw->mac.asf_firmware_present)
1654                goto out;
1655
1656        manc = rd32(E1000_MANC);
1657
1658        if (!(manc & E1000_MANC_RCV_TCO_EN))
1659                goto out;
1660
1661        if (hw->mac.arc_subsystem_valid) {
1662                fwsm = rd32(E1000_FWSM);
1663                factps = rd32(E1000_FACTPS);
1664
1665                if (!(factps & E1000_FACTPS_MNGCG) &&
1666                    ((fwsm & E1000_FWSM_MODE_MASK) ==
1667                     (e1000_mng_mode_pt << E1000_FWSM_MODE_SHIFT))) {
1668                        ret_val = true;
1669                        goto out;
1670                }
1671        } else {
1672                if ((manc & E1000_MANC_SMBUS_EN) &&
1673                    !(manc & E1000_MANC_ASF_EN)) {
1674                        ret_val = true;
1675                        goto out;
1676                }
1677        }
1678
1679out:
1680        return ret_val;
1681}
1682