1
2
3
4
5
6#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
7
8#include <generated/utsrelease.h>
9#include "ice.h"
10#include "ice_base.h"
11#include "ice_lib.h"
12#include "ice_fltr.h"
13#include "ice_dcb_lib.h"
14#include "ice_dcb_nl.h"
15#include "ice_devlink.h"
16
17
18
19
20#define CREATE_TRACE_POINTS
21#include "ice_trace.h"
22
23#define DRV_SUMMARY "Intel(R) Ethernet Connection E800 Series Linux Driver"
24static const char ice_driver_string[] = DRV_SUMMARY;
25static const char ice_copyright[] = "Copyright (c) 2018, Intel Corporation.";
26
27
28#define ICE_DDP_PKG_PATH "intel/ice/ddp/"
29#define ICE_DDP_PKG_FILE ICE_DDP_PKG_PATH "ice.pkg"
30
31MODULE_AUTHOR("Intel Corporation, <linux.nics@intel.com>");
32MODULE_DESCRIPTION(DRV_SUMMARY);
33MODULE_LICENSE("GPL v2");
34MODULE_FIRMWARE(ICE_DDP_PKG_FILE);
35
36static int debug = -1;
37module_param(debug, int, 0644);
38#ifndef CONFIG_DYNAMIC_DEBUG
39MODULE_PARM_DESC(debug, "netif level (0=none,...,16=all), hw debug_mask (0x8XXXXXXX)");
40#else
41MODULE_PARM_DESC(debug, "netif level (0=none,...,16=all)");
42#endif
43
44static DEFINE_IDA(ice_aux_ida);
45
46static struct workqueue_struct *ice_wq;
47static const struct net_device_ops ice_netdev_safe_mode_ops;
48static const struct net_device_ops ice_netdev_ops;
49static int ice_vsi_open(struct ice_vsi *vsi);
50
51static void ice_rebuild(struct ice_pf *pf, enum ice_reset_req reset_type);
52
53static void ice_vsi_release_all(struct ice_pf *pf);
54
55bool netif_is_ice(struct net_device *dev)
56{
57 return dev && (dev->netdev_ops == &ice_netdev_ops);
58}
59
60
61
62
63
64static u16 ice_get_tx_pending(struct ice_ring *ring)
65{
66 u16 head, tail;
67
68 head = ring->next_to_clean;
69 tail = ring->next_to_use;
70
71 if (head != tail)
72 return (head < tail) ?
73 tail - head : (tail + ring->count - head);
74 return 0;
75}
76
77
78
79
80
81static void ice_check_for_hang_subtask(struct ice_pf *pf)
82{
83 struct ice_vsi *vsi = NULL;
84 struct ice_hw *hw;
85 unsigned int i;
86 int packets;
87 u32 v;
88
89 ice_for_each_vsi(pf, v)
90 if (pf->vsi[v] && pf->vsi[v]->type == ICE_VSI_PF) {
91 vsi = pf->vsi[v];
92 break;
93 }
94
95 if (!vsi || test_bit(ICE_VSI_DOWN, vsi->state))
96 return;
97
98 if (!(vsi->netdev && netif_carrier_ok(vsi->netdev)))
99 return;
100
101 hw = &vsi->back->hw;
102
103 for (i = 0; i < vsi->num_txq; i++) {
104 struct ice_ring *tx_ring = vsi->tx_rings[i];
105
106 if (tx_ring && tx_ring->desc) {
107
108
109
110
111
112
113
114 packets = tx_ring->stats.pkts & INT_MAX;
115 if (tx_ring->tx_stats.prev_pkt == packets) {
116
117 ice_trigger_sw_intr(hw, tx_ring->q_vector);
118 continue;
119 }
120
121
122
123
124 smp_rmb();
125 tx_ring->tx_stats.prev_pkt =
126 ice_get_tx_pending(tx_ring) ? packets : -1;
127 }
128 }
129}
130
131
132
133
134
135
136
137
138
139static int ice_init_mac_fltr(struct ice_pf *pf)
140{
141 enum ice_status status;
142 struct ice_vsi *vsi;
143 u8 *perm_addr;
144
145 vsi = ice_get_main_vsi(pf);
146 if (!vsi)
147 return -EINVAL;
148
149 perm_addr = vsi->port_info->mac.perm_addr;
150 status = ice_fltr_add_mac_and_broadcast(vsi, perm_addr, ICE_FWD_TO_VSI);
151 if (status)
152 return -EIO;
153
154 return 0;
155}
156
157
158
159
160
161
162
163
164
165
166
167static int ice_add_mac_to_sync_list(struct net_device *netdev, const u8 *addr)
168{
169 struct ice_netdev_priv *np = netdev_priv(netdev);
170 struct ice_vsi *vsi = np->vsi;
171
172 if (ice_fltr_add_mac_to_list(vsi, &vsi->tmp_sync_list, addr,
173 ICE_FWD_TO_VSI))
174 return -EINVAL;
175
176 return 0;
177}
178
179
180
181
182
183
184
185
186
187
188
189static int ice_add_mac_to_unsync_list(struct net_device *netdev, const u8 *addr)
190{
191 struct ice_netdev_priv *np = netdev_priv(netdev);
192 struct ice_vsi *vsi = np->vsi;
193
194
195
196
197
198
199 if (ether_addr_equal(addr, netdev->dev_addr))
200 return 0;
201
202 if (ice_fltr_add_mac_to_list(vsi, &vsi->tmp_unsync_list, addr,
203 ICE_FWD_TO_VSI))
204 return -EINVAL;
205
206 return 0;
207}
208
209
210
211
212
213
214
215static bool ice_vsi_fltr_changed(struct ice_vsi *vsi)
216{
217 return test_bit(ICE_VSI_UMAC_FLTR_CHANGED, vsi->state) ||
218 test_bit(ICE_VSI_MMAC_FLTR_CHANGED, vsi->state) ||
219 test_bit(ICE_VSI_VLAN_FLTR_CHANGED, vsi->state);
220}
221
222
223
224
225
226
227
228
229static int ice_cfg_promisc(struct ice_vsi *vsi, u8 promisc_m, bool set_promisc)
230{
231 struct ice_hw *hw = &vsi->back->hw;
232 enum ice_status status = 0;
233
234 if (vsi->type != ICE_VSI_PF)
235 return 0;
236
237 if (vsi->num_vlan > 1) {
238 status = ice_set_vlan_vsi_promisc(hw, vsi->idx, promisc_m,
239 set_promisc);
240 } else {
241 if (set_promisc)
242 status = ice_set_vsi_promisc(hw, vsi->idx, promisc_m,
243 0);
244 else
245 status = ice_clear_vsi_promisc(hw, vsi->idx, promisc_m,
246 0);
247 }
248
249 if (status)
250 return -EIO;
251
252 return 0;
253}
254
255
256
257
258
259
260
261static int ice_vsi_sync_fltr(struct ice_vsi *vsi)
262{
263 struct device *dev = ice_pf_to_dev(vsi->back);
264 struct net_device *netdev = vsi->netdev;
265 bool promisc_forced_on = false;
266 struct ice_pf *pf = vsi->back;
267 struct ice_hw *hw = &pf->hw;
268 enum ice_status status = 0;
269 u32 changed_flags = 0;
270 u8 promisc_m;
271 int err = 0;
272
273 if (!vsi->netdev)
274 return -EINVAL;
275
276 while (test_and_set_bit(ICE_CFG_BUSY, vsi->state))
277 usleep_range(1000, 2000);
278
279 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
280 vsi->current_netdev_flags = vsi->netdev->flags;
281
282 INIT_LIST_HEAD(&vsi->tmp_sync_list);
283 INIT_LIST_HEAD(&vsi->tmp_unsync_list);
284
285 if (ice_vsi_fltr_changed(vsi)) {
286 clear_bit(ICE_VSI_UMAC_FLTR_CHANGED, vsi->state);
287 clear_bit(ICE_VSI_MMAC_FLTR_CHANGED, vsi->state);
288 clear_bit(ICE_VSI_VLAN_FLTR_CHANGED, vsi->state);
289
290
291 netif_addr_lock_bh(netdev);
292 __dev_uc_sync(netdev, ice_add_mac_to_sync_list,
293 ice_add_mac_to_unsync_list);
294 __dev_mc_sync(netdev, ice_add_mac_to_sync_list,
295 ice_add_mac_to_unsync_list);
296
297 netif_addr_unlock_bh(netdev);
298 }
299
300
301 status = ice_fltr_remove_mac_list(vsi, &vsi->tmp_unsync_list);
302 ice_fltr_free_list(dev, &vsi->tmp_unsync_list);
303 if (status) {
304 netdev_err(netdev, "Failed to delete MAC filters\n");
305
306 if (status == ICE_ERR_NO_MEMORY) {
307 err = -ENOMEM;
308 goto out;
309 }
310 }
311
312
313 status = ice_fltr_add_mac_list(vsi, &vsi->tmp_sync_list);
314 ice_fltr_free_list(dev, &vsi->tmp_sync_list);
315
316
317
318
319 if (status && status != ICE_ERR_ALREADY_EXISTS) {
320 netdev_err(netdev, "Failed to add MAC filters\n");
321
322
323
324
325 if (hw->adminq.sq_last_status == ICE_AQ_RC_ENOSPC &&
326 !test_and_set_bit(ICE_FLTR_OVERFLOW_PROMISC,
327 vsi->state)) {
328 promisc_forced_on = true;
329 netdev_warn(netdev, "Reached MAC filter limit, forcing promisc mode on VSI %d\n",
330 vsi->vsi_num);
331 } else {
332 err = -EIO;
333 goto out;
334 }
335 }
336
337 if (changed_flags & IFF_ALLMULTI) {
338 if (vsi->current_netdev_flags & IFF_ALLMULTI) {
339 if (vsi->num_vlan > 1)
340 promisc_m = ICE_MCAST_VLAN_PROMISC_BITS;
341 else
342 promisc_m = ICE_MCAST_PROMISC_BITS;
343
344 err = ice_cfg_promisc(vsi, promisc_m, true);
345 if (err) {
346 netdev_err(netdev, "Error setting Multicast promiscuous mode on VSI %i\n",
347 vsi->vsi_num);
348 vsi->current_netdev_flags &= ~IFF_ALLMULTI;
349 goto out_promisc;
350 }
351 } else {
352
353 if (vsi->num_vlan > 1)
354 promisc_m = ICE_MCAST_VLAN_PROMISC_BITS;
355 else
356 promisc_m = ICE_MCAST_PROMISC_BITS;
357
358 err = ice_cfg_promisc(vsi, promisc_m, false);
359 if (err) {
360 netdev_err(netdev, "Error clearing Multicast promiscuous mode on VSI %i\n",
361 vsi->vsi_num);
362 vsi->current_netdev_flags |= IFF_ALLMULTI;
363 goto out_promisc;
364 }
365 }
366 }
367
368 if (((changed_flags & IFF_PROMISC) || promisc_forced_on) ||
369 test_bit(ICE_VSI_PROMISC_CHANGED, vsi->state)) {
370 clear_bit(ICE_VSI_PROMISC_CHANGED, vsi->state);
371 if (vsi->current_netdev_flags & IFF_PROMISC) {
372
373 if (!ice_is_dflt_vsi_in_use(pf->first_sw)) {
374 err = ice_set_dflt_vsi(pf->first_sw, vsi);
375 if (err && err != -EEXIST) {
376 netdev_err(netdev, "Error %d setting default VSI %i Rx rule\n",
377 err, vsi->vsi_num);
378 vsi->current_netdev_flags &=
379 ~IFF_PROMISC;
380 goto out_promisc;
381 }
382 ice_cfg_vlan_pruning(vsi, false, false);
383 }
384 } else {
385
386 if (ice_is_vsi_dflt_vsi(pf->first_sw, vsi)) {
387 err = ice_clear_dflt_vsi(pf->first_sw);
388 if (err) {
389 netdev_err(netdev, "Error %d clearing default VSI %i Rx rule\n",
390 err, vsi->vsi_num);
391 vsi->current_netdev_flags |=
392 IFF_PROMISC;
393 goto out_promisc;
394 }
395 if (vsi->num_vlan > 1)
396 ice_cfg_vlan_pruning(vsi, true, false);
397 }
398 }
399 }
400 goto exit;
401
402out_promisc:
403 set_bit(ICE_VSI_PROMISC_CHANGED, vsi->state);
404 goto exit;
405out:
406
407 set_bit(ICE_VSI_UMAC_FLTR_CHANGED, vsi->state);
408 set_bit(ICE_VSI_MMAC_FLTR_CHANGED, vsi->state);
409exit:
410 clear_bit(ICE_CFG_BUSY, vsi->state);
411 return err;
412}
413
414
415
416
417
418static void ice_sync_fltr_subtask(struct ice_pf *pf)
419{
420 int v;
421
422 if (!pf || !(test_bit(ICE_FLAG_FLTR_SYNC, pf->flags)))
423 return;
424
425 clear_bit(ICE_FLAG_FLTR_SYNC, pf->flags);
426
427 ice_for_each_vsi(pf, v)
428 if (pf->vsi[v] && ice_vsi_fltr_changed(pf->vsi[v]) &&
429 ice_vsi_sync_fltr(pf->vsi[v])) {
430
431 set_bit(ICE_FLAG_FLTR_SYNC, pf->flags);
432 break;
433 }
434}
435
436
437
438
439
440
441static void ice_pf_dis_all_vsi(struct ice_pf *pf, bool locked)
442{
443 int node;
444 int v;
445
446 ice_for_each_vsi(pf, v)
447 if (pf->vsi[v])
448 ice_dis_vsi(pf->vsi[v], locked);
449
450 for (node = 0; node < ICE_MAX_PF_AGG_NODES; node++)
451 pf->pf_agg_node[node].num_vsis = 0;
452
453 for (node = 0; node < ICE_MAX_VF_AGG_NODES; node++)
454 pf->vf_agg_node[node].num_vsis = 0;
455}
456
457
458
459
460
461
462
463static void
464ice_prepare_for_reset(struct ice_pf *pf)
465{
466 struct ice_hw *hw = &pf->hw;
467 unsigned int i;
468
469
470 if (test_bit(ICE_PREPARED_FOR_RESET, pf->state))
471 return;
472
473 ice_unplug_aux_dev(pf);
474
475
476 if (ice_check_sq_alive(hw, &hw->mailboxq))
477 ice_vc_notify_reset(pf);
478
479
480 ice_for_each_vf(pf, i)
481 ice_set_vf_state_qs_dis(&pf->vf[i]);
482
483
484 ice_clear_hw_tbls(hw);
485
486 ice_pf_dis_all_vsi(pf, false);
487
488 if (test_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags))
489 ice_ptp_release(pf);
490
491 if (hw->port_info)
492 ice_sched_clear_port(hw->port_info);
493
494 ice_shutdown_all_ctrlq(hw);
495
496 set_bit(ICE_PREPARED_FOR_RESET, pf->state);
497}
498
499
500
501
502
503
504
505static void ice_do_reset(struct ice_pf *pf, enum ice_reset_req reset_type)
506{
507 struct device *dev = ice_pf_to_dev(pf);
508 struct ice_hw *hw = &pf->hw;
509
510 dev_dbg(dev, "reset_type 0x%x requested\n", reset_type);
511
512 ice_prepare_for_reset(pf);
513
514
515 if (ice_reset(hw, reset_type)) {
516 dev_err(dev, "reset %d failed\n", reset_type);
517 set_bit(ICE_RESET_FAILED, pf->state);
518 clear_bit(ICE_RESET_OICR_RECV, pf->state);
519 clear_bit(ICE_PREPARED_FOR_RESET, pf->state);
520 clear_bit(ICE_PFR_REQ, pf->state);
521 clear_bit(ICE_CORER_REQ, pf->state);
522 clear_bit(ICE_GLOBR_REQ, pf->state);
523 wake_up(&pf->reset_wait_queue);
524 return;
525 }
526
527
528
529
530
531 if (reset_type == ICE_RESET_PFR) {
532 pf->pfr_count++;
533 ice_rebuild(pf, reset_type);
534 clear_bit(ICE_PREPARED_FOR_RESET, pf->state);
535 clear_bit(ICE_PFR_REQ, pf->state);
536 wake_up(&pf->reset_wait_queue);
537 ice_reset_all_vfs(pf, true);
538 }
539}
540
541
542
543
544
545static void ice_reset_subtask(struct ice_pf *pf)
546{
547 enum ice_reset_req reset_type = ICE_RESET_INVAL;
548
549
550
551
552
553
554
555
556
557
558
559 if (test_bit(ICE_RESET_OICR_RECV, pf->state)) {
560
561 if (test_and_clear_bit(ICE_CORER_RECV, pf->state))
562 reset_type = ICE_RESET_CORER;
563 if (test_and_clear_bit(ICE_GLOBR_RECV, pf->state))
564 reset_type = ICE_RESET_GLOBR;
565 if (test_and_clear_bit(ICE_EMPR_RECV, pf->state))
566 reset_type = ICE_RESET_EMPR;
567
568 if (reset_type == ICE_RESET_INVAL)
569 return;
570 ice_prepare_for_reset(pf);
571
572
573 if (ice_check_reset(&pf->hw)) {
574 set_bit(ICE_RESET_FAILED, pf->state);
575 } else {
576
577 pf->hw.reset_ongoing = false;
578 ice_rebuild(pf, reset_type);
579
580
581
582 clear_bit(ICE_RESET_OICR_RECV, pf->state);
583 clear_bit(ICE_PREPARED_FOR_RESET, pf->state);
584 clear_bit(ICE_PFR_REQ, pf->state);
585 clear_bit(ICE_CORER_REQ, pf->state);
586 clear_bit(ICE_GLOBR_REQ, pf->state);
587 wake_up(&pf->reset_wait_queue);
588 ice_reset_all_vfs(pf, true);
589 }
590
591 return;
592 }
593
594
595 if (test_bit(ICE_PFR_REQ, pf->state))
596 reset_type = ICE_RESET_PFR;
597 if (test_bit(ICE_CORER_REQ, pf->state))
598 reset_type = ICE_RESET_CORER;
599 if (test_bit(ICE_GLOBR_REQ, pf->state))
600 reset_type = ICE_RESET_GLOBR;
601
602 if (reset_type == ICE_RESET_INVAL)
603 return;
604
605
606 if (!test_bit(ICE_DOWN, pf->state) &&
607 !test_bit(ICE_CFG_BUSY, pf->state)) {
608 ice_do_reset(pf, reset_type);
609 }
610}
611
612
613
614
615
616static void ice_print_topo_conflict(struct ice_vsi *vsi)
617{
618 switch (vsi->port_info->phy.link_info.topo_media_conflict) {
619 case ICE_AQ_LINK_TOPO_CONFLICT:
620 case ICE_AQ_LINK_MEDIA_CONFLICT:
621 case ICE_AQ_LINK_TOPO_UNREACH_PRT:
622 case ICE_AQ_LINK_TOPO_UNDRUTIL_PRT:
623 case ICE_AQ_LINK_TOPO_UNDRUTIL_MEDIA:
624 netdev_info(vsi->netdev, "Potential misconfiguration of the Ethernet port detected. If it was not intended, please use the Intel (R) Ethernet Port Configuration Tool to address the issue.\n");
625 break;
626 case ICE_AQ_LINK_TOPO_UNSUPP_MEDIA:
627 netdev_info(vsi->netdev, "Rx/Tx is disabled on this device because an unsupported module type was detected. Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n");
628 break;
629 default:
630 break;
631 }
632}
633
634
635
636
637
638
639void ice_print_link_msg(struct ice_vsi *vsi, bool isup)
640{
641 struct ice_aqc_get_phy_caps_data *caps;
642 const char *an_advertised;
643 enum ice_status status;
644 const char *fec_req;
645 const char *speed;
646 const char *fec;
647 const char *fc;
648 const char *an;
649
650 if (!vsi)
651 return;
652
653 if (vsi->current_isup == isup)
654 return;
655
656 vsi->current_isup = isup;
657
658 if (!isup) {
659 netdev_info(vsi->netdev, "NIC Link is Down\n");
660 return;
661 }
662
663 switch (vsi->port_info->phy.link_info.link_speed) {
664 case ICE_AQ_LINK_SPEED_100GB:
665 speed = "100 G";
666 break;
667 case ICE_AQ_LINK_SPEED_50GB:
668 speed = "50 G";
669 break;
670 case ICE_AQ_LINK_SPEED_40GB:
671 speed = "40 G";
672 break;
673 case ICE_AQ_LINK_SPEED_25GB:
674 speed = "25 G";
675 break;
676 case ICE_AQ_LINK_SPEED_20GB:
677 speed = "20 G";
678 break;
679 case ICE_AQ_LINK_SPEED_10GB:
680 speed = "10 G";
681 break;
682 case ICE_AQ_LINK_SPEED_5GB:
683 speed = "5 G";
684 break;
685 case ICE_AQ_LINK_SPEED_2500MB:
686 speed = "2.5 G";
687 break;
688 case ICE_AQ_LINK_SPEED_1000MB:
689 speed = "1 G";
690 break;
691 case ICE_AQ_LINK_SPEED_100MB:
692 speed = "100 M";
693 break;
694 default:
695 speed = "Unknown ";
696 break;
697 }
698
699 switch (vsi->port_info->fc.current_mode) {
700 case ICE_FC_FULL:
701 fc = "Rx/Tx";
702 break;
703 case ICE_FC_TX_PAUSE:
704 fc = "Tx";
705 break;
706 case ICE_FC_RX_PAUSE:
707 fc = "Rx";
708 break;
709 case ICE_FC_NONE:
710 fc = "None";
711 break;
712 default:
713 fc = "Unknown";
714 break;
715 }
716
717
718 switch (vsi->port_info->phy.link_info.fec_info) {
719 case ICE_AQ_LINK_25G_RS_528_FEC_EN:
720 case ICE_AQ_LINK_25G_RS_544_FEC_EN:
721 fec = "RS-FEC";
722 break;
723 case ICE_AQ_LINK_25G_KR_FEC_EN:
724 fec = "FC-FEC/BASE-R";
725 break;
726 default:
727 fec = "NONE";
728 break;
729 }
730
731
732 if (vsi->port_info->phy.link_info.an_info & ICE_AQ_AN_COMPLETED)
733 an = "True";
734 else
735 an = "False";
736
737
738 caps = kzalloc(sizeof(*caps), GFP_KERNEL);
739 if (!caps) {
740 fec_req = "Unknown";
741 an_advertised = "Unknown";
742 goto done;
743 }
744
745 status = ice_aq_get_phy_caps(vsi->port_info, false,
746 ICE_AQC_REPORT_ACTIVE_CFG, caps, NULL);
747 if (status)
748 netdev_info(vsi->netdev, "Get phy capability failed.\n");
749
750 an_advertised = ice_is_phy_caps_an_enabled(caps) ? "On" : "Off";
751
752 if (caps->link_fec_options & ICE_AQC_PHY_FEC_25G_RS_528_REQ ||
753 caps->link_fec_options & ICE_AQC_PHY_FEC_25G_RS_544_REQ)
754 fec_req = "RS-FEC";
755 else if (caps->link_fec_options & ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ ||
756 caps->link_fec_options & ICE_AQC_PHY_FEC_25G_KR_REQ)
757 fec_req = "FC-FEC/BASE-R";
758 else
759 fec_req = "NONE";
760
761 kfree(caps);
762
763done:
764 netdev_info(vsi->netdev, "NIC Link is up %sbps Full Duplex, Requested FEC: %s, Negotiated FEC: %s, Autoneg Advertised: %s, Autoneg Negotiated: %s, Flow Control: %s\n",
765 speed, fec_req, fec, an_advertised, an, fc);
766 ice_print_topo_conflict(vsi);
767}
768
769
770
771
772
773
774static void ice_vsi_link_event(struct ice_vsi *vsi, bool link_up)
775{
776 if (!vsi)
777 return;
778
779 if (test_bit(ICE_VSI_DOWN, vsi->state) || !vsi->netdev)
780 return;
781
782 if (vsi->type == ICE_VSI_PF) {
783 if (link_up == netif_carrier_ok(vsi->netdev))
784 return;
785
786 if (link_up) {
787 netif_carrier_on(vsi->netdev);
788 netif_tx_wake_all_queues(vsi->netdev);
789 } else {
790 netif_carrier_off(vsi->netdev);
791 netif_tx_stop_all_queues(vsi->netdev);
792 }
793 }
794}
795
796
797
798
799
800
801
802
803
804
805
806
807static void ice_set_dflt_mib(struct ice_pf *pf)
808{
809 struct device *dev = ice_pf_to_dev(pf);
810 u8 mib_type, *buf, *lldpmib = NULL;
811 u16 len, typelen, offset = 0;
812 struct ice_lldp_org_tlv *tlv;
813 struct ice_hw *hw = &pf->hw;
814 u32 ouisubtype;
815
816 mib_type = SET_LOCAL_MIB_TYPE_LOCAL_MIB;
817 lldpmib = kzalloc(ICE_LLDPDU_SIZE, GFP_KERNEL);
818 if (!lldpmib) {
819 dev_dbg(dev, "%s Failed to allocate MIB memory\n",
820 __func__);
821 return;
822 }
823
824
825 tlv = (struct ice_lldp_org_tlv *)lldpmib;
826 typelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) |
827 ICE_IEEE_ETS_TLV_LEN);
828 tlv->typelen = htons(typelen);
829 ouisubtype = ((ICE_IEEE_8021QAZ_OUI << ICE_LLDP_TLV_OUI_S) |
830 ICE_IEEE_SUBTYPE_ETS_CFG);
831 tlv->ouisubtype = htonl(ouisubtype);
832
833 buf = tlv->tlvinfo;
834 buf[0] = 0;
835
836
837
838
839
840 buf[5] = 0x64;
841 len = (typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S;
842 offset += len + 2;
843 tlv = (struct ice_lldp_org_tlv *)
844 ((char *)tlv + sizeof(tlv->typelen) + len);
845
846
847 buf = tlv->tlvinfo;
848 tlv->typelen = htons(typelen);
849
850 ouisubtype = ((ICE_IEEE_8021QAZ_OUI << ICE_LLDP_TLV_OUI_S) |
851 ICE_IEEE_SUBTYPE_ETS_REC);
852 tlv->ouisubtype = htonl(ouisubtype);
853
854
855
856
857
858
859 buf[5] = 0x64;
860 offset += len + 2;
861 tlv = (struct ice_lldp_org_tlv *)
862 ((char *)tlv + sizeof(tlv->typelen) + len);
863
864
865 typelen = ((ICE_TLV_TYPE_ORG << ICE_LLDP_TLV_TYPE_S) |
866 ICE_IEEE_PFC_TLV_LEN);
867 tlv->typelen = htons(typelen);
868
869 ouisubtype = ((ICE_IEEE_8021QAZ_OUI << ICE_LLDP_TLV_OUI_S) |
870 ICE_IEEE_SUBTYPE_PFC_CFG);
871 tlv->ouisubtype = htonl(ouisubtype);
872
873
874 buf[0] = 0x08;
875 len = (typelen & ICE_LLDP_TLV_LEN_M) >> ICE_LLDP_TLV_LEN_S;
876 offset += len + 2;
877
878 if (ice_aq_set_lldp_mib(hw, mib_type, (void *)lldpmib, offset, NULL))
879 dev_dbg(dev, "%s Failed to set default LLDP MIB\n", __func__);
880
881 kfree(lldpmib);
882}
883
884
885
886
887
888
889
890
891
892static void ice_check_module_power(struct ice_pf *pf, u8 link_cfg_err)
893{
894
895 if (!(link_cfg_err & (ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT |
896 ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED))) {
897 clear_bit(ICE_FLAG_MOD_POWER_UNSUPPORTED, pf->flags);
898 return;
899 }
900
901
902
903
904 if (test_bit(ICE_FLAG_MOD_POWER_UNSUPPORTED, pf->flags))
905 return;
906
907 if (link_cfg_err & ICE_AQ_LINK_INVAL_MAX_POWER_LIMIT) {
908 dev_err(ice_pf_to_dev(pf), "The installed module is incompatible with the device's NVM image. Cannot start link\n");
909 set_bit(ICE_FLAG_MOD_POWER_UNSUPPORTED, pf->flags);
910 } else if (link_cfg_err & ICE_AQ_LINK_MODULE_POWER_UNSUPPORTED) {
911 dev_err(ice_pf_to_dev(pf), "The module's power requirements exceed the device's power supply. Cannot start link\n");
912 set_bit(ICE_FLAG_MOD_POWER_UNSUPPORTED, pf->flags);
913 }
914}
915
916
917
918
919
920
921
922
923
924
925static int
926ice_link_event(struct ice_pf *pf, struct ice_port_info *pi, bool link_up,
927 u16 link_speed)
928{
929 struct device *dev = ice_pf_to_dev(pf);
930 struct ice_phy_info *phy_info;
931 enum ice_status status;
932 struct ice_vsi *vsi;
933 u16 old_link_speed;
934 bool old_link;
935
936 phy_info = &pi->phy;
937 phy_info->link_info_old = phy_info->link_info;
938
939 old_link = !!(phy_info->link_info_old.link_info & ICE_AQ_LINK_UP);
940 old_link_speed = phy_info->link_info_old.link_speed;
941
942
943
944
945 status = ice_update_link_info(pi);
946 if (status)
947 dev_dbg(dev, "Failed to update link status on port %d, err %s aq_err %s\n",
948 pi->lport, ice_stat_str(status),
949 ice_aq_str(pi->hw->adminq.sq_last_status));
950
951 ice_check_module_power(pf, pi->phy.link_info.link_cfg_err);
952
953
954
955
956 if (phy_info->link_info.link_info & ICE_AQ_LINK_UP)
957 link_up = true;
958
959 vsi = ice_get_main_vsi(pf);
960 if (!vsi || !vsi->port_info)
961 return -EINVAL;
962
963
964 if (!test_bit(ICE_FLAG_NO_MEDIA, pf->flags) &&
965 !(pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE)) {
966 set_bit(ICE_FLAG_NO_MEDIA, pf->flags);
967 ice_set_link(vsi, false);
968 }
969
970
971 if (link_up == old_link && link_speed == old_link_speed)
972 return 0;
973
974 if (ice_is_dcb_active(pf)) {
975 if (test_bit(ICE_FLAG_DCB_ENA, pf->flags))
976 ice_dcb_rebuild(pf);
977 } else {
978 if (link_up)
979 ice_set_dflt_mib(pf);
980 }
981 ice_vsi_link_event(vsi, link_up);
982 ice_print_link_msg(vsi, link_up);
983
984 ice_vc_notify_link_state(pf);
985
986 return 0;
987}
988
989
990
991
992
993static void ice_watchdog_subtask(struct ice_pf *pf)
994{
995 int i;
996
997
998 if (test_bit(ICE_DOWN, pf->state) ||
999 test_bit(ICE_CFG_BUSY, pf->state))
1000 return;
1001
1002
1003 if (time_before(jiffies,
1004 pf->serv_tmr_prev + pf->serv_tmr_period))
1005 return;
1006
1007 pf->serv_tmr_prev = jiffies;
1008
1009
1010
1011
1012 ice_update_pf_stats(pf);
1013 ice_for_each_vsi(pf, i)
1014 if (pf->vsi[i] && pf->vsi[i]->netdev)
1015 ice_update_vsi_stats(pf->vsi[i]);
1016}
1017
1018
1019
1020
1021
1022
1023
1024static int ice_init_link_events(struct ice_port_info *pi)
1025{
1026 u16 mask;
1027
1028 mask = ~((u16)(ICE_AQ_LINK_EVENT_UPDOWN | ICE_AQ_LINK_EVENT_MEDIA_NA |
1029 ICE_AQ_LINK_EVENT_MODULE_QUAL_FAIL));
1030
1031 if (ice_aq_set_event_mask(pi->hw, pi->lport, mask, NULL)) {
1032 dev_dbg(ice_hw_to_dev(pi->hw), "Failed to set link event mask for port %d\n",
1033 pi->lport);
1034 return -EIO;
1035 }
1036
1037 if (ice_aq_get_link_info(pi, true, NULL, NULL)) {
1038 dev_dbg(ice_hw_to_dev(pi->hw), "Failed to enable link events for port %d\n",
1039 pi->lport);
1040 return -EIO;
1041 }
1042
1043 return 0;
1044}
1045
1046
1047
1048
1049
1050
1051static int
1052ice_handle_link_event(struct ice_pf *pf, struct ice_rq_event_info *event)
1053{
1054 struct ice_aqc_get_link_status_data *link_data;
1055 struct ice_port_info *port_info;
1056 int status;
1057
1058 link_data = (struct ice_aqc_get_link_status_data *)event->msg_buf;
1059 port_info = pf->hw.port_info;
1060 if (!port_info)
1061 return -EINVAL;
1062
1063 status = ice_link_event(pf, port_info,
1064 !!(link_data->link_info & ICE_AQ_LINK_UP),
1065 le16_to_cpu(link_data->link_speed));
1066 if (status)
1067 dev_dbg(ice_pf_to_dev(pf), "Could not process link event, error %d\n",
1068 status);
1069
1070 return status;
1071}
1072
1073enum ice_aq_task_state {
1074 ICE_AQ_TASK_WAITING = 0,
1075 ICE_AQ_TASK_COMPLETE,
1076 ICE_AQ_TASK_CANCELED,
1077};
1078
1079struct ice_aq_task {
1080 struct hlist_node entry;
1081
1082 u16 opcode;
1083 struct ice_rq_event_info *event;
1084 enum ice_aq_task_state state;
1085};
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104int ice_aq_wait_for_event(struct ice_pf *pf, u16 opcode, unsigned long timeout,
1105 struct ice_rq_event_info *event)
1106{
1107 struct device *dev = ice_pf_to_dev(pf);
1108 struct ice_aq_task *task;
1109 unsigned long start;
1110 long ret;
1111 int err;
1112
1113 task = kzalloc(sizeof(*task), GFP_KERNEL);
1114 if (!task)
1115 return -ENOMEM;
1116
1117 INIT_HLIST_NODE(&task->entry);
1118 task->opcode = opcode;
1119 task->event = event;
1120 task->state = ICE_AQ_TASK_WAITING;
1121
1122 spin_lock_bh(&pf->aq_wait_lock);
1123 hlist_add_head(&task->entry, &pf->aq_wait_list);
1124 spin_unlock_bh(&pf->aq_wait_lock);
1125
1126 start = jiffies;
1127
1128 ret = wait_event_interruptible_timeout(pf->aq_wait_queue, task->state,
1129 timeout);
1130 switch (task->state) {
1131 case ICE_AQ_TASK_WAITING:
1132 err = ret < 0 ? ret : -ETIMEDOUT;
1133 break;
1134 case ICE_AQ_TASK_CANCELED:
1135 err = ret < 0 ? ret : -ECANCELED;
1136 break;
1137 case ICE_AQ_TASK_COMPLETE:
1138 err = ret < 0 ? ret : 0;
1139 break;
1140 default:
1141 WARN(1, "Unexpected AdminQ wait task state %u", task->state);
1142 err = -EINVAL;
1143 break;
1144 }
1145
1146 dev_dbg(dev, "Waited %u msecs (max %u msecs) for firmware response to op 0x%04x\n",
1147 jiffies_to_msecs(jiffies - start),
1148 jiffies_to_msecs(timeout),
1149 opcode);
1150
1151 spin_lock_bh(&pf->aq_wait_lock);
1152 hlist_del(&task->entry);
1153 spin_unlock_bh(&pf->aq_wait_lock);
1154 kfree(task);
1155
1156 return err;
1157}
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177static void ice_aq_check_events(struct ice_pf *pf, u16 opcode,
1178 struct ice_rq_event_info *event)
1179{
1180 struct ice_aq_task *task;
1181 bool found = false;
1182
1183 spin_lock_bh(&pf->aq_wait_lock);
1184 hlist_for_each_entry(task, &pf->aq_wait_list, entry) {
1185 if (task->state || task->opcode != opcode)
1186 continue;
1187
1188 memcpy(&task->event->desc, &event->desc, sizeof(event->desc));
1189 task->event->msg_len = event->msg_len;
1190
1191
1192 if (task->event->msg_buf &&
1193 task->event->buf_len > event->buf_len) {
1194 memcpy(task->event->msg_buf, event->msg_buf,
1195 event->buf_len);
1196 task->event->buf_len = event->buf_len;
1197 }
1198
1199 task->state = ICE_AQ_TASK_COMPLETE;
1200 found = true;
1201 }
1202 spin_unlock_bh(&pf->aq_wait_lock);
1203
1204 if (found)
1205 wake_up(&pf->aq_wait_queue);
1206}
1207
1208
1209
1210
1211
1212
1213
1214
1215static void ice_aq_cancel_waiting_tasks(struct ice_pf *pf)
1216{
1217 struct ice_aq_task *task;
1218
1219 spin_lock_bh(&pf->aq_wait_lock);
1220 hlist_for_each_entry(task, &pf->aq_wait_list, entry)
1221 task->state = ICE_AQ_TASK_CANCELED;
1222 spin_unlock_bh(&pf->aq_wait_lock);
1223
1224 wake_up(&pf->aq_wait_queue);
1225}
1226
1227
1228
1229
1230
1231
1232static int __ice_clean_ctrlq(struct ice_pf *pf, enum ice_ctl_q q_type)
1233{
1234 struct device *dev = ice_pf_to_dev(pf);
1235 struct ice_rq_event_info event;
1236 struct ice_hw *hw = &pf->hw;
1237 struct ice_ctl_q_info *cq;
1238 u16 pending, i = 0;
1239 const char *qtype;
1240 u32 oldval, val;
1241
1242
1243 if (test_bit(ICE_RESET_FAILED, pf->state))
1244 return 0;
1245
1246 switch (q_type) {
1247 case ICE_CTL_Q_ADMIN:
1248 cq = &hw->adminq;
1249 qtype = "Admin";
1250 break;
1251 case ICE_CTL_Q_SB:
1252 cq = &hw->sbq;
1253 qtype = "Sideband";
1254 break;
1255 case ICE_CTL_Q_MAILBOX:
1256 cq = &hw->mailboxq;
1257 qtype = "Mailbox";
1258
1259
1260
1261 hw->mbx_snapshot.mbx_buf.state = ICE_MAL_VF_DETECT_STATE_NEW_SNAPSHOT;
1262 break;
1263 default:
1264 dev_warn(dev, "Unknown control queue type 0x%x\n", q_type);
1265 return 0;
1266 }
1267
1268
1269
1270
1271 val = rd32(hw, cq->rq.len);
1272 if (val & (PF_FW_ARQLEN_ARQVFE_M | PF_FW_ARQLEN_ARQOVFL_M |
1273 PF_FW_ARQLEN_ARQCRIT_M)) {
1274 oldval = val;
1275 if (val & PF_FW_ARQLEN_ARQVFE_M)
1276 dev_dbg(dev, "%s Receive Queue VF Error detected\n",
1277 qtype);
1278 if (val & PF_FW_ARQLEN_ARQOVFL_M) {
1279 dev_dbg(dev, "%s Receive Queue Overflow Error detected\n",
1280 qtype);
1281 }
1282 if (val & PF_FW_ARQLEN_ARQCRIT_M)
1283 dev_dbg(dev, "%s Receive Queue Critical Error detected\n",
1284 qtype);
1285 val &= ~(PF_FW_ARQLEN_ARQVFE_M | PF_FW_ARQLEN_ARQOVFL_M |
1286 PF_FW_ARQLEN_ARQCRIT_M);
1287 if (oldval != val)
1288 wr32(hw, cq->rq.len, val);
1289 }
1290
1291 val = rd32(hw, cq->sq.len);
1292 if (val & (PF_FW_ATQLEN_ATQVFE_M | PF_FW_ATQLEN_ATQOVFL_M |
1293 PF_FW_ATQLEN_ATQCRIT_M)) {
1294 oldval = val;
1295 if (val & PF_FW_ATQLEN_ATQVFE_M)
1296 dev_dbg(dev, "%s Send Queue VF Error detected\n",
1297 qtype);
1298 if (val & PF_FW_ATQLEN_ATQOVFL_M) {
1299 dev_dbg(dev, "%s Send Queue Overflow Error detected\n",
1300 qtype);
1301 }
1302 if (val & PF_FW_ATQLEN_ATQCRIT_M)
1303 dev_dbg(dev, "%s Send Queue Critical Error detected\n",
1304 qtype);
1305 val &= ~(PF_FW_ATQLEN_ATQVFE_M | PF_FW_ATQLEN_ATQOVFL_M |
1306 PF_FW_ATQLEN_ATQCRIT_M);
1307 if (oldval != val)
1308 wr32(hw, cq->sq.len, val);
1309 }
1310
1311 event.buf_len = cq->rq_buf_size;
1312 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
1313 if (!event.msg_buf)
1314 return 0;
1315
1316 do {
1317 enum ice_status ret;
1318 u16 opcode;
1319
1320 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1321 if (ret == ICE_ERR_AQ_NO_WORK)
1322 break;
1323 if (ret) {
1324 dev_err(dev, "%s Receive Queue event error %s\n", qtype,
1325 ice_stat_str(ret));
1326 break;
1327 }
1328
1329 opcode = le16_to_cpu(event.desc.opcode);
1330
1331
1332 ice_aq_check_events(pf, opcode, &event);
1333
1334 switch (opcode) {
1335 case ice_aqc_opc_get_link_status:
1336 if (ice_handle_link_event(pf, &event))
1337 dev_err(dev, "Could not handle link event\n");
1338 break;
1339 case ice_aqc_opc_event_lan_overflow:
1340 ice_vf_lan_overflow_event(pf, &event);
1341 break;
1342 case ice_mbx_opc_send_msg_to_pf:
1343 if (!ice_is_malicious_vf(pf, &event, i, pending))
1344 ice_vc_process_vf_msg(pf, &event);
1345 break;
1346 case ice_aqc_opc_fw_logging:
1347 ice_output_fw_log(hw, &event.desc, event.msg_buf);
1348 break;
1349 case ice_aqc_opc_lldp_set_mib_change:
1350 ice_dcb_process_lldp_set_mib_change(pf, &event);
1351 break;
1352 default:
1353 dev_dbg(dev, "%s Receive Queue unknown event 0x%04x ignored\n",
1354 qtype, opcode);
1355 break;
1356 }
1357 } while (pending && (i++ < ICE_DFLT_IRQ_WORK));
1358
1359 kfree(event.msg_buf);
1360
1361 return pending && (i == ICE_DFLT_IRQ_WORK);
1362}
1363
1364
1365
1366
1367
1368
1369
1370
1371static bool ice_ctrlq_pending(struct ice_hw *hw, struct ice_ctl_q_info *cq)
1372{
1373 u16 ntu;
1374
1375 ntu = (u16)(rd32(hw, cq->rq.head) & cq->rq.head_mask);
1376 return cq->rq.next_to_clean != ntu;
1377}
1378
1379
1380
1381
1382
1383static void ice_clean_adminq_subtask(struct ice_pf *pf)
1384{
1385 struct ice_hw *hw = &pf->hw;
1386
1387 if (!test_bit(ICE_ADMINQ_EVENT_PENDING, pf->state))
1388 return;
1389
1390 if (__ice_clean_ctrlq(pf, ICE_CTL_Q_ADMIN))
1391 return;
1392
1393 clear_bit(ICE_ADMINQ_EVENT_PENDING, pf->state);
1394
1395
1396
1397
1398
1399
1400 if (ice_ctrlq_pending(hw, &hw->adminq))
1401 __ice_clean_ctrlq(pf, ICE_CTL_Q_ADMIN);
1402
1403 ice_flush(hw);
1404}
1405
1406
1407
1408
1409
1410static void ice_clean_mailboxq_subtask(struct ice_pf *pf)
1411{
1412 struct ice_hw *hw = &pf->hw;
1413
1414 if (!test_bit(ICE_MAILBOXQ_EVENT_PENDING, pf->state))
1415 return;
1416
1417 if (__ice_clean_ctrlq(pf, ICE_CTL_Q_MAILBOX))
1418 return;
1419
1420 clear_bit(ICE_MAILBOXQ_EVENT_PENDING, pf->state);
1421
1422 if (ice_ctrlq_pending(hw, &hw->mailboxq))
1423 __ice_clean_ctrlq(pf, ICE_CTL_Q_MAILBOX);
1424
1425 ice_flush(hw);
1426}
1427
1428
1429
1430
1431
1432static void ice_clean_sbq_subtask(struct ice_pf *pf)
1433{
1434 struct ice_hw *hw = &pf->hw;
1435
1436
1437 if (!ice_is_sbq_supported(hw)) {
1438 clear_bit(ICE_SIDEBANDQ_EVENT_PENDING, pf->state);
1439 return;
1440 }
1441
1442 if (!test_bit(ICE_SIDEBANDQ_EVENT_PENDING, pf->state))
1443 return;
1444
1445 if (__ice_clean_ctrlq(pf, ICE_CTL_Q_SB))
1446 return;
1447
1448 clear_bit(ICE_SIDEBANDQ_EVENT_PENDING, pf->state);
1449
1450 if (ice_ctrlq_pending(hw, &hw->sbq))
1451 __ice_clean_ctrlq(pf, ICE_CTL_Q_SB);
1452
1453 ice_flush(hw);
1454}
1455
1456
1457
1458
1459
1460
1461
1462void ice_service_task_schedule(struct ice_pf *pf)
1463{
1464 if (!test_bit(ICE_SERVICE_DIS, pf->state) &&
1465 !test_and_set_bit(ICE_SERVICE_SCHED, pf->state) &&
1466 !test_bit(ICE_NEEDS_RESTART, pf->state))
1467 queue_work(ice_wq, &pf->serv_task);
1468}
1469
1470
1471
1472
1473
1474static void ice_service_task_complete(struct ice_pf *pf)
1475{
1476 WARN_ON(!test_bit(ICE_SERVICE_SCHED, pf->state));
1477
1478
1479 smp_mb__before_atomic();
1480 clear_bit(ICE_SERVICE_SCHED, pf->state);
1481}
1482
1483
1484
1485
1486
1487
1488
1489
1490static int ice_service_task_stop(struct ice_pf *pf)
1491{
1492 int ret;
1493
1494 ret = test_and_set_bit(ICE_SERVICE_DIS, pf->state);
1495
1496 if (pf->serv_tmr.function)
1497 del_timer_sync(&pf->serv_tmr);
1498 if (pf->serv_task.func)
1499 cancel_work_sync(&pf->serv_task);
1500
1501 clear_bit(ICE_SERVICE_SCHED, pf->state);
1502 return ret;
1503}
1504
1505
1506
1507
1508
1509
1510
1511static void ice_service_task_restart(struct ice_pf *pf)
1512{
1513 clear_bit(ICE_SERVICE_DIS, pf->state);
1514 ice_service_task_schedule(pf);
1515}
1516
1517
1518
1519
1520
1521static void ice_service_timer(struct timer_list *t)
1522{
1523 struct ice_pf *pf = from_timer(pf, t, serv_tmr);
1524
1525 mod_timer(&pf->serv_tmr, round_jiffies(pf->serv_tmr_period + jiffies));
1526 ice_service_task_schedule(pf);
1527}
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538
1539static void ice_handle_mdd_event(struct ice_pf *pf)
1540{
1541 struct device *dev = ice_pf_to_dev(pf);
1542 struct ice_hw *hw = &pf->hw;
1543 unsigned int i;
1544 u32 reg;
1545
1546 if (!test_and_clear_bit(ICE_MDD_EVENT_PENDING, pf->state)) {
1547
1548
1549
1550 ice_print_vfs_mdd_events(pf);
1551 return;
1552 }
1553
1554
1555 reg = rd32(hw, GL_MDET_TX_PQM);
1556 if (reg & GL_MDET_TX_PQM_VALID_M) {
1557 u8 pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1558 GL_MDET_TX_PQM_PF_NUM_S;
1559 u16 vf_num = (reg & GL_MDET_TX_PQM_VF_NUM_M) >>
1560 GL_MDET_TX_PQM_VF_NUM_S;
1561 u8 event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1562 GL_MDET_TX_PQM_MAL_TYPE_S;
1563 u16 queue = ((reg & GL_MDET_TX_PQM_QNUM_M) >>
1564 GL_MDET_TX_PQM_QNUM_S);
1565
1566 if (netif_msg_tx_err(pf))
1567 dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n",
1568 event, queue, pf_num, vf_num);
1569 wr32(hw, GL_MDET_TX_PQM, 0xffffffff);
1570 }
1571
1572 reg = rd32(hw, GL_MDET_TX_TCLAN);
1573 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1574 u8 pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1575 GL_MDET_TX_TCLAN_PF_NUM_S;
1576 u16 vf_num = (reg & GL_MDET_TX_TCLAN_VF_NUM_M) >>
1577 GL_MDET_TX_TCLAN_VF_NUM_S;
1578 u8 event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1579 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1580 u16 queue = ((reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1581 GL_MDET_TX_TCLAN_QNUM_S);
1582
1583 if (netif_msg_tx_err(pf))
1584 dev_info(dev, "Malicious Driver Detection event %d on TX queue %d PF# %d VF# %d\n",
1585 event, queue, pf_num, vf_num);
1586 wr32(hw, GL_MDET_TX_TCLAN, 0xffffffff);
1587 }
1588
1589 reg = rd32(hw, GL_MDET_RX);
1590 if (reg & GL_MDET_RX_VALID_M) {
1591 u8 pf_num = (reg & GL_MDET_RX_PF_NUM_M) >>
1592 GL_MDET_RX_PF_NUM_S;
1593 u16 vf_num = (reg & GL_MDET_RX_VF_NUM_M) >>
1594 GL_MDET_RX_VF_NUM_S;
1595 u8 event = (reg & GL_MDET_RX_MAL_TYPE_M) >>
1596 GL_MDET_RX_MAL_TYPE_S;
1597 u16 queue = ((reg & GL_MDET_RX_QNUM_M) >>
1598 GL_MDET_RX_QNUM_S);
1599
1600 if (netif_msg_rx_err(pf))
1601 dev_info(dev, "Malicious Driver Detection event %d on RX queue %d PF# %d VF# %d\n",
1602 event, queue, pf_num, vf_num);
1603 wr32(hw, GL_MDET_RX, 0xffffffff);
1604 }
1605
1606
1607 reg = rd32(hw, PF_MDET_TX_PQM);
1608 if (reg & PF_MDET_TX_PQM_VALID_M) {
1609 wr32(hw, PF_MDET_TX_PQM, 0xFFFF);
1610 if (netif_msg_tx_err(pf))
1611 dev_info(dev, "Malicious Driver Detection event TX_PQM detected on PF\n");
1612 }
1613
1614 reg = rd32(hw, PF_MDET_TX_TCLAN);
1615 if (reg & PF_MDET_TX_TCLAN_VALID_M) {
1616 wr32(hw, PF_MDET_TX_TCLAN, 0xFFFF);
1617 if (netif_msg_tx_err(pf))
1618 dev_info(dev, "Malicious Driver Detection event TX_TCLAN detected on PF\n");
1619 }
1620
1621 reg = rd32(hw, PF_MDET_RX);
1622 if (reg & PF_MDET_RX_VALID_M) {
1623 wr32(hw, PF_MDET_RX, 0xFFFF);
1624 if (netif_msg_rx_err(pf))
1625 dev_info(dev, "Malicious Driver Detection event RX detected on PF\n");
1626 }
1627
1628
1629
1630
1631 ice_for_each_vf(pf, i) {
1632 struct ice_vf *vf = &pf->vf[i];
1633
1634 reg = rd32(hw, VP_MDET_TX_PQM(i));
1635 if (reg & VP_MDET_TX_PQM_VALID_M) {
1636 wr32(hw, VP_MDET_TX_PQM(i), 0xFFFF);
1637 vf->mdd_tx_events.count++;
1638 set_bit(ICE_MDD_VF_PRINT_PENDING, pf->state);
1639 if (netif_msg_tx_err(pf))
1640 dev_info(dev, "Malicious Driver Detection event TX_PQM detected on VF %d\n",
1641 i);
1642 }
1643
1644 reg = rd32(hw, VP_MDET_TX_TCLAN(i));
1645 if (reg & VP_MDET_TX_TCLAN_VALID_M) {
1646 wr32(hw, VP_MDET_TX_TCLAN(i), 0xFFFF);
1647 vf->mdd_tx_events.count++;
1648 set_bit(ICE_MDD_VF_PRINT_PENDING, pf->state);
1649 if (netif_msg_tx_err(pf))
1650 dev_info(dev, "Malicious Driver Detection event TX_TCLAN detected on VF %d\n",
1651 i);
1652 }
1653
1654 reg = rd32(hw, VP_MDET_TX_TDPU(i));
1655 if (reg & VP_MDET_TX_TDPU_VALID_M) {
1656 wr32(hw, VP_MDET_TX_TDPU(i), 0xFFFF);
1657 vf->mdd_tx_events.count++;
1658 set_bit(ICE_MDD_VF_PRINT_PENDING, pf->state);
1659 if (netif_msg_tx_err(pf))
1660 dev_info(dev, "Malicious Driver Detection event TX_TDPU detected on VF %d\n",
1661 i);
1662 }
1663
1664 reg = rd32(hw, VP_MDET_RX(i));
1665 if (reg & VP_MDET_RX_VALID_M) {
1666 wr32(hw, VP_MDET_RX(i), 0xFFFF);
1667 vf->mdd_rx_events.count++;
1668 set_bit(ICE_MDD_VF_PRINT_PENDING, pf->state);
1669 if (netif_msg_rx_err(pf))
1670 dev_info(dev, "Malicious Driver Detection event RX detected on VF %d\n",
1671 i);
1672
1673
1674
1675
1676
1677 if (test_bit(ICE_FLAG_MDD_AUTO_RESET_VF, pf->flags)) {
1678
1679
1680
1681 ice_print_vf_rx_mdd_event(vf);
1682 ice_reset_vf(&pf->vf[i], false);
1683 }
1684 }
1685 }
1686
1687 ice_print_vfs_mdd_events(pf);
1688}
1689
1690
1691
1692
1693
1694
1695
1696
1697
1698
1699
1700
1701
1702static int ice_force_phys_link_state(struct ice_vsi *vsi, bool link_up)
1703{
1704 struct ice_aqc_get_phy_caps_data *pcaps;
1705 struct ice_aqc_set_phy_cfg_data *cfg;
1706 struct ice_port_info *pi;
1707 struct device *dev;
1708 int retcode;
1709
1710 if (!vsi || !vsi->port_info || !vsi->back)
1711 return -EINVAL;
1712 if (vsi->type != ICE_VSI_PF)
1713 return 0;
1714
1715 dev = ice_pf_to_dev(vsi->back);
1716
1717 pi = vsi->port_info;
1718
1719 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
1720 if (!pcaps)
1721 return -ENOMEM;
1722
1723 retcode = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, pcaps,
1724 NULL);
1725 if (retcode) {
1726 dev_err(dev, "Failed to get phy capabilities, VSI %d error %d\n",
1727 vsi->vsi_num, retcode);
1728 retcode = -EIO;
1729 goto out;
1730 }
1731
1732
1733 if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
1734 link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
1735 goto out;
1736
1737
1738
1739
1740
1741 cfg = kmemdup(&pi->phy.curr_user_phy_cfg, sizeof(*cfg), GFP_KERNEL);
1742 if (!cfg) {
1743 retcode = -ENOMEM;
1744 goto out;
1745 }
1746
1747 cfg->caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
1748 if (link_up)
1749 cfg->caps |= ICE_AQ_PHY_ENA_LINK;
1750 else
1751 cfg->caps &= ~ICE_AQ_PHY_ENA_LINK;
1752
1753 retcode = ice_aq_set_phy_cfg(&vsi->back->hw, pi, cfg, NULL);
1754 if (retcode) {
1755 dev_err(dev, "Failed to set phy config, VSI %d error %d\n",
1756 vsi->vsi_num, retcode);
1757 retcode = -EIO;
1758 }
1759
1760 kfree(cfg);
1761out:
1762 kfree(pcaps);
1763 return retcode;
1764}
1765
1766
1767
1768
1769
1770
1771
1772static int ice_init_nvm_phy_type(struct ice_port_info *pi)
1773{
1774 struct ice_aqc_get_phy_caps_data *pcaps;
1775 struct ice_pf *pf = pi->hw->back;
1776 enum ice_status status;
1777 int err = 0;
1778
1779 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
1780 if (!pcaps)
1781 return -ENOMEM;
1782
1783 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_NO_MEDIA, pcaps,
1784 NULL);
1785
1786 if (status) {
1787 dev_err(ice_pf_to_dev(pf), "Get PHY capability failed.\n");
1788 err = -EIO;
1789 goto out;
1790 }
1791
1792 pf->nvm_phy_type_hi = pcaps->phy_type_high;
1793 pf->nvm_phy_type_lo = pcaps->phy_type_low;
1794
1795out:
1796 kfree(pcaps);
1797 return err;
1798}
1799
1800
1801
1802
1803
1804
1805
1806static void ice_init_link_dflt_override(struct ice_port_info *pi)
1807{
1808 struct ice_link_default_override_tlv *ldo;
1809 struct ice_pf *pf = pi->hw->back;
1810
1811 ldo = &pf->link_dflt_override;
1812 if (ice_get_link_default_override(ldo, pi))
1813 return;
1814
1815 if (!(ldo->options & ICE_LINK_OVERRIDE_PORT_DIS))
1816 return;
1817
1818
1819
1820
1821 set_bit(ICE_FLAG_TOTAL_PORT_SHUTDOWN_ENA, pf->flags);
1822 set_bit(ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA, pf->flags);
1823}
1824
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839
1840
1841
1842static void ice_init_phy_cfg_dflt_override(struct ice_port_info *pi)
1843{
1844 struct ice_link_default_override_tlv *ldo;
1845 struct ice_aqc_set_phy_cfg_data *cfg;
1846 struct ice_phy_info *phy = &pi->phy;
1847 struct ice_pf *pf = pi->hw->back;
1848
1849 ldo = &pf->link_dflt_override;
1850
1851
1852
1853
1854 cfg = &phy->curr_user_phy_cfg;
1855
1856 if (ldo->phy_type_low || ldo->phy_type_high) {
1857 cfg->phy_type_low = pf->nvm_phy_type_lo &
1858 cpu_to_le64(ldo->phy_type_low);
1859 cfg->phy_type_high = pf->nvm_phy_type_hi &
1860 cpu_to_le64(ldo->phy_type_high);
1861 }
1862 cfg->link_fec_opt = ldo->fec_options;
1863 phy->curr_user_fec_req = ICE_FEC_AUTO;
1864
1865 set_bit(ICE_LINK_DEFAULT_OVERRIDE_PENDING, pf->state);
1866}
1867
1868
1869
1870
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880
1881
1882static int ice_init_phy_user_cfg(struct ice_port_info *pi)
1883{
1884 struct ice_aqc_get_phy_caps_data *pcaps;
1885 struct ice_phy_info *phy = &pi->phy;
1886 struct ice_pf *pf = pi->hw->back;
1887 enum ice_status status;
1888 int err = 0;
1889
1890 if (!(phy->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE))
1891 return -EIO;
1892
1893 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
1894 if (!pcaps)
1895 return -ENOMEM;
1896
1897 if (ice_fw_supports_report_dflt_cfg(pi->hw))
1898 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_DFLT_CFG,
1899 pcaps, NULL);
1900 else
1901 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
1902 pcaps, NULL);
1903 if (status) {
1904 dev_err(ice_pf_to_dev(pf), "Get PHY capability failed.\n");
1905 err = -EIO;
1906 goto err_out;
1907 }
1908
1909 ice_copy_phy_caps_to_cfg(pi, pcaps, &pi->phy.curr_user_phy_cfg);
1910
1911
1912 if (ice_fw_supports_link_override(pi->hw) &&
1913 !(pcaps->module_compliance_enforcement &
1914 ICE_AQC_MOD_ENFORCE_STRICT_MODE)) {
1915 set_bit(ICE_FLAG_LINK_LENIENT_MODE_ENA, pf->flags);
1916
1917
1918
1919
1920
1921 if (!ice_fw_supports_report_dflt_cfg(pi->hw) &&
1922 (pf->link_dflt_override.options & ICE_LINK_OVERRIDE_EN)) {
1923 ice_init_phy_cfg_dflt_override(pi);
1924 goto out;
1925 }
1926 }
1927
1928
1929
1930
1931 phy->curr_user_fec_req = ice_caps_to_fec_mode(pcaps->caps,
1932 pcaps->link_fec_options);
1933 phy->curr_user_fc_req = ice_caps_to_fc_mode(pcaps->caps);
1934
1935out:
1936 phy->curr_user_speed_req = ICE_AQ_LINK_SPEED_M;
1937 set_bit(ICE_PHY_INIT_COMPLETE, pf->state);
1938err_out:
1939 kfree(pcaps);
1940 return err;
1941}
1942
1943
1944
1945
1946
1947
1948
1949
1950
1951static int ice_configure_phy(struct ice_vsi *vsi)
1952{
1953 struct device *dev = ice_pf_to_dev(vsi->back);
1954 struct ice_port_info *pi = vsi->port_info;
1955 struct ice_aqc_get_phy_caps_data *pcaps;
1956 struct ice_aqc_set_phy_cfg_data *cfg;
1957 struct ice_phy_info *phy = &pi->phy;
1958 struct ice_pf *pf = vsi->back;
1959 enum ice_status status;
1960 int err = 0;
1961
1962
1963 if (!(phy->link_info.link_info & ICE_AQ_MEDIA_AVAILABLE))
1964 return -EPERM;
1965
1966 ice_print_topo_conflict(vsi);
1967
1968 if (phy->link_info.topo_media_conflict == ICE_AQ_LINK_TOPO_UNSUPP_MEDIA)
1969 return -EPERM;
1970
1971 if (test_bit(ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA, pf->flags))
1972 return ice_force_phys_link_state(vsi, true);
1973
1974 pcaps = kzalloc(sizeof(*pcaps), GFP_KERNEL);
1975 if (!pcaps)
1976 return -ENOMEM;
1977
1978
1979 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG, pcaps,
1980 NULL);
1981 if (status) {
1982 dev_err(dev, "Failed to get PHY configuration, VSI %d error %s\n",
1983 vsi->vsi_num, ice_stat_str(status));
1984 err = -EIO;
1985 goto done;
1986 }
1987
1988
1989
1990
1991 if (pcaps->caps & ICE_AQC_PHY_EN_LINK &&
1992 ice_phy_caps_equals_cfg(pcaps, &phy->curr_user_phy_cfg))
1993 goto done;
1994
1995
1996 memset(pcaps, 0, sizeof(*pcaps));
1997 if (ice_fw_supports_report_dflt_cfg(pi->hw))
1998 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_DFLT_CFG,
1999 pcaps, NULL);
2000 else
2001 status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_TOPO_CAP_MEDIA,
2002 pcaps, NULL);
2003 if (status) {
2004 dev_err(dev, "Failed to get PHY caps, VSI %d error %s\n",
2005 vsi->vsi_num, ice_stat_str(status));
2006 err = -EIO;
2007 goto done;
2008 }
2009
2010 cfg = kzalloc(sizeof(*cfg), GFP_KERNEL);
2011 if (!cfg) {
2012 err = -ENOMEM;
2013 goto done;
2014 }
2015
2016 ice_copy_phy_caps_to_cfg(pi, pcaps, cfg);
2017
2018
2019
2020
2021 if (test_and_clear_bit(ICE_LINK_DEFAULT_OVERRIDE_PENDING,
2022 vsi->back->state)) {
2023 cfg->phy_type_low = phy->curr_user_phy_cfg.phy_type_low;
2024 cfg->phy_type_high = phy->curr_user_phy_cfg.phy_type_high;
2025 } else {
2026 u64 phy_low = 0, phy_high = 0;
2027
2028 ice_update_phy_type(&phy_low, &phy_high,
2029 pi->phy.curr_user_speed_req);
2030 cfg->phy_type_low = pcaps->phy_type_low & cpu_to_le64(phy_low);
2031 cfg->phy_type_high = pcaps->phy_type_high &
2032 cpu_to_le64(phy_high);
2033 }
2034
2035
2036 if (!cfg->phy_type_low && !cfg->phy_type_high) {
2037 cfg->phy_type_low = pcaps->phy_type_low;
2038 cfg->phy_type_high = pcaps->phy_type_high;
2039 }
2040
2041
2042 ice_cfg_phy_fec(pi, cfg, phy->curr_user_fec_req);
2043
2044
2045 if (cfg->link_fec_opt !=
2046 (cfg->link_fec_opt & pcaps->link_fec_options)) {
2047 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC;
2048 cfg->link_fec_opt = pcaps->link_fec_options;
2049 }
2050
2051
2052
2053
2054 ice_cfg_phy_fc(pi, cfg, phy->curr_user_fc_req);
2055
2056
2057 cfg->caps |= ICE_AQ_PHY_ENA_AUTO_LINK_UPDT | ICE_AQ_PHY_ENA_LINK;
2058
2059 status = ice_aq_set_phy_cfg(&pf->hw, pi, cfg, NULL);
2060 if (status) {
2061 dev_err(dev, "Failed to set phy config, VSI %d error %s\n",
2062 vsi->vsi_num, ice_stat_str(status));
2063 err = -EIO;
2064 }
2065
2066 kfree(cfg);
2067done:
2068 kfree(pcaps);
2069 return err;
2070}
2071
2072
2073
2074
2075
2076
2077
2078
2079static void ice_check_media_subtask(struct ice_pf *pf)
2080{
2081 struct ice_port_info *pi;
2082 struct ice_vsi *vsi;
2083 int err;
2084
2085
2086 if (!test_bit(ICE_FLAG_NO_MEDIA, pf->flags))
2087 return;
2088
2089 vsi = ice_get_main_vsi(pf);
2090 if (!vsi)
2091 return;
2092
2093
2094 pi = vsi->port_info;
2095 err = ice_update_link_info(pi);
2096 if (err)
2097 return;
2098
2099 ice_check_module_power(pf, pi->phy.link_info.link_cfg_err);
2100
2101 if (pi->phy.link_info.link_info & ICE_AQ_MEDIA_AVAILABLE) {
2102 if (!test_bit(ICE_PHY_INIT_COMPLETE, pf->state))
2103 ice_init_phy_user_cfg(pi);
2104
2105
2106
2107
2108 if (test_bit(ICE_VSI_DOWN, vsi->state) &&
2109 test_bit(ICE_FLAG_LINK_DOWN_ON_CLOSE_ENA, vsi->back->flags))
2110 return;
2111
2112 err = ice_configure_phy(vsi);
2113 if (!err)
2114 clear_bit(ICE_FLAG_NO_MEDIA, pf->flags);
2115
2116
2117
2118
2119 }
2120}
2121
2122
2123
2124
2125
2126static void ice_service_task(struct work_struct *work)
2127{
2128 struct ice_pf *pf = container_of(work, struct ice_pf, serv_task);
2129 unsigned long start_time = jiffies;
2130
2131
2132
2133
2134 ice_reset_subtask(pf);
2135
2136
2137 if (ice_is_reset_in_progress(pf->state) ||
2138 test_bit(ICE_SUSPENDED, pf->state) ||
2139 test_bit(ICE_NEEDS_RESTART, pf->state)) {
2140 ice_service_task_complete(pf);
2141 return;
2142 }
2143
2144 ice_clean_adminq_subtask(pf);
2145 ice_check_media_subtask(pf);
2146 ice_check_for_hang_subtask(pf);
2147 ice_sync_fltr_subtask(pf);
2148 ice_handle_mdd_event(pf);
2149 ice_watchdog_subtask(pf);
2150
2151 if (ice_is_safe_mode(pf)) {
2152 ice_service_task_complete(pf);
2153 return;
2154 }
2155
2156 ice_process_vflr_event(pf);
2157 ice_clean_mailboxq_subtask(pf);
2158 ice_clean_sbq_subtask(pf);
2159 ice_sync_arfs_fltrs(pf);
2160 ice_flush_fdir_ctx(pf);
2161
2162
2163 ice_service_task_complete(pf);
2164
2165
2166
2167
2168
2169 if (time_after(jiffies, (start_time + pf->serv_tmr_period)) ||
2170 test_bit(ICE_MDD_EVENT_PENDING, pf->state) ||
2171 test_bit(ICE_VFLR_EVENT_PENDING, pf->state) ||
2172 test_bit(ICE_MAILBOXQ_EVENT_PENDING, pf->state) ||
2173 test_bit(ICE_FD_VF_FLUSH_CTX, pf->state) ||
2174 test_bit(ICE_SIDEBANDQ_EVENT_PENDING, pf->state) ||
2175 test_bit(ICE_ADMINQ_EVENT_PENDING, pf->state))
2176 mod_timer(&pf->serv_tmr, jiffies);
2177}
2178
2179
2180
2181
2182
2183static void ice_set_ctrlq_len(struct ice_hw *hw)
2184{
2185 hw->adminq.num_rq_entries = ICE_AQ_LEN;
2186 hw->adminq.num_sq_entries = ICE_AQ_LEN;
2187 hw->adminq.rq_buf_size = ICE_AQ_MAX_BUF_LEN;
2188 hw->adminq.sq_buf_size = ICE_AQ_MAX_BUF_LEN;
2189 hw->mailboxq.num_rq_entries = PF_MBX_ARQLEN_ARQLEN_M;
2190 hw->mailboxq.num_sq_entries = ICE_MBXSQ_LEN;
2191 hw->mailboxq.rq_buf_size = ICE_MBXQ_MAX_BUF_LEN;
2192 hw->mailboxq.sq_buf_size = ICE_MBXQ_MAX_BUF_LEN;
2193 hw->sbq.num_rq_entries = ICE_SBQ_LEN;
2194 hw->sbq.num_sq_entries = ICE_SBQ_LEN;
2195 hw->sbq.rq_buf_size = ICE_SBQ_MAX_BUF_LEN;
2196 hw->sbq.sq_buf_size = ICE_SBQ_MAX_BUF_LEN;
2197}
2198
2199
2200
2201
2202
2203
2204int ice_schedule_reset(struct ice_pf *pf, enum ice_reset_req reset)
2205{
2206 struct device *dev = ice_pf_to_dev(pf);
2207
2208
2209 if (test_bit(ICE_RESET_FAILED, pf->state)) {
2210 dev_dbg(dev, "earlier reset has failed\n");
2211 return -EIO;
2212 }
2213
2214 if (ice_is_reset_in_progress(pf->state)) {
2215 dev_dbg(dev, "Reset already in progress\n");
2216 return -EBUSY;
2217 }
2218
2219 ice_unplug_aux_dev(pf);
2220
2221 switch (reset) {
2222 case ICE_RESET_PFR:
2223 set_bit(ICE_PFR_REQ, pf->state);
2224 break;
2225 case ICE_RESET_CORER:
2226 set_bit(ICE_CORER_REQ, pf->state);
2227 break;
2228 case ICE_RESET_GLOBR:
2229 set_bit(ICE_GLOBR_REQ, pf->state);
2230 break;
2231 default:
2232 return -EINVAL;
2233 }
2234
2235 ice_service_task_schedule(pf);
2236 return 0;
2237}
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247static void
2248ice_irq_affinity_notify(struct irq_affinity_notify *notify,
2249 const cpumask_t *mask)
2250{
2251 struct ice_q_vector *q_vector =
2252 container_of(notify, struct ice_q_vector, affinity_notify);
2253
2254 cpumask_copy(&q_vector->affinity_mask, mask);
2255}
2256
2257
2258
2259
2260
2261
2262
2263
2264
2265static void ice_irq_affinity_release(struct kref __always_unused *ref) {}
2266
2267
2268
2269
2270
2271static int ice_vsi_ena_irq(struct ice_vsi *vsi)
2272{
2273 struct ice_hw *hw = &vsi->back->hw;
2274 int i;
2275
2276 ice_for_each_q_vector(vsi, i)
2277 ice_irq_dynamic_ena(hw, vsi, vsi->q_vectors[i]);
2278
2279 ice_flush(hw);
2280 return 0;
2281}
2282
2283
2284
2285
2286
2287
2288static int ice_vsi_req_irq_msix(struct ice_vsi *vsi, char *basename)
2289{
2290 int q_vectors = vsi->num_q_vectors;
2291 struct ice_pf *pf = vsi->back;
2292 int base = vsi->base_vector;
2293 struct device *dev;
2294 int rx_int_idx = 0;
2295 int tx_int_idx = 0;
2296 int vector, err;
2297 int irq_num;
2298
2299 dev = ice_pf_to_dev(pf);
2300 for (vector = 0; vector < q_vectors; vector++) {
2301 struct ice_q_vector *q_vector = vsi->q_vectors[vector];
2302
2303 irq_num = pf->msix_entries[base + vector].vector;
2304
2305 if (q_vector->tx.ring && q_vector->rx.ring) {
2306 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2307 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
2308 tx_int_idx++;
2309 } else if (q_vector->rx.ring) {
2310 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2311 "%s-%s-%d", basename, "rx", rx_int_idx++);
2312 } else if (q_vector->tx.ring) {
2313 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
2314 "%s-%s-%d", basename, "tx", tx_int_idx++);
2315 } else {
2316
2317 continue;
2318 }
2319 if (vsi->type == ICE_VSI_CTRL && vsi->vf_id != ICE_INVAL_VFID)
2320 err = devm_request_irq(dev, irq_num, vsi->irq_handler,
2321 IRQF_SHARED, q_vector->name,
2322 q_vector);
2323 else
2324 err = devm_request_irq(dev, irq_num, vsi->irq_handler,
2325 0, q_vector->name, q_vector);
2326 if (err) {
2327 netdev_err(vsi->netdev, "MSIX request_irq failed, error: %d\n",
2328 err);
2329 goto free_q_irqs;
2330 }
2331
2332
2333 if (!IS_ENABLED(CONFIG_RFS_ACCEL)) {
2334 struct irq_affinity_notify *affinity_notify;
2335
2336 affinity_notify = &q_vector->affinity_notify;
2337 affinity_notify->notify = ice_irq_affinity_notify;
2338 affinity_notify->release = ice_irq_affinity_release;
2339 irq_set_affinity_notifier(irq_num, affinity_notify);
2340 }
2341
2342
2343 irq_set_affinity_hint(irq_num, &q_vector->affinity_mask);
2344 }
2345
2346 vsi->irqs_ready = true;
2347 return 0;
2348
2349free_q_irqs:
2350 while (vector) {
2351 vector--;
2352 irq_num = pf->msix_entries[base + vector].vector;
2353 if (!IS_ENABLED(CONFIG_RFS_ACCEL))
2354 irq_set_affinity_notifier(irq_num, NULL);
2355 irq_set_affinity_hint(irq_num, NULL);
2356 devm_free_irq(dev, irq_num, &vsi->q_vectors[vector]);
2357 }
2358 return err;
2359}
2360
2361
2362
2363
2364
2365
2366
2367static int ice_xdp_alloc_setup_rings(struct ice_vsi *vsi)
2368{
2369 struct device *dev = ice_pf_to_dev(vsi->back);
2370 int i;
2371
2372 for (i = 0; i < vsi->num_xdp_txq; i++) {
2373 u16 xdp_q_idx = vsi->alloc_txq + i;
2374 struct ice_ring *xdp_ring;
2375
2376 xdp_ring = kzalloc(sizeof(*xdp_ring), GFP_KERNEL);
2377
2378 if (!xdp_ring)
2379 goto free_xdp_rings;
2380
2381 xdp_ring->q_index = xdp_q_idx;
2382 xdp_ring->reg_idx = vsi->txq_map[xdp_q_idx];
2383 xdp_ring->ring_active = false;
2384 xdp_ring->vsi = vsi;
2385 xdp_ring->netdev = NULL;
2386 xdp_ring->dev = dev;
2387 xdp_ring->count = vsi->num_tx_desc;
2388 WRITE_ONCE(vsi->xdp_rings[i], xdp_ring);
2389 if (ice_setup_tx_ring(xdp_ring))
2390 goto free_xdp_rings;
2391 ice_set_ring_xdp(xdp_ring);
2392 xdp_ring->xsk_pool = ice_xsk_pool(xdp_ring);
2393 }
2394
2395 return 0;
2396
2397free_xdp_rings:
2398 for (; i >= 0; i--)
2399 if (vsi->xdp_rings[i] && vsi->xdp_rings[i]->desc)
2400 ice_free_tx_ring(vsi->xdp_rings[i]);
2401 return -ENOMEM;
2402}
2403
2404
2405
2406
2407
2408
2409static void ice_vsi_assign_bpf_prog(struct ice_vsi *vsi, struct bpf_prog *prog)
2410{
2411 struct bpf_prog *old_prog;
2412 int i;
2413
2414 old_prog = xchg(&vsi->xdp_prog, prog);
2415 if (old_prog)
2416 bpf_prog_put(old_prog);
2417
2418 ice_for_each_rxq(vsi, i)
2419 WRITE_ONCE(vsi->rx_rings[i]->xdp_prog, vsi->xdp_prog);
2420}
2421
2422
2423
2424
2425
2426
2427
2428
2429int ice_prepare_xdp_rings(struct ice_vsi *vsi, struct bpf_prog *prog)
2430{
2431 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
2432 int xdp_rings_rem = vsi->num_xdp_txq;
2433 struct ice_pf *pf = vsi->back;
2434 struct ice_qs_cfg xdp_qs_cfg = {
2435 .qs_mutex = &pf->avail_q_mutex,
2436 .pf_map = pf->avail_txqs,
2437 .pf_map_size = pf->max_pf_txqs,
2438 .q_count = vsi->num_xdp_txq,
2439 .scatter_count = ICE_MAX_SCATTER_TXQS,
2440 .vsi_map = vsi->txq_map,
2441 .vsi_map_offset = vsi->alloc_txq,
2442 .mapping_mode = ICE_VSI_MAP_CONTIG
2443 };
2444 enum ice_status status;
2445 struct device *dev;
2446 int i, v_idx;
2447
2448 dev = ice_pf_to_dev(pf);
2449 vsi->xdp_rings = devm_kcalloc(dev, vsi->num_xdp_txq,
2450 sizeof(*vsi->xdp_rings), GFP_KERNEL);
2451 if (!vsi->xdp_rings)
2452 return -ENOMEM;
2453
2454 vsi->xdp_mapping_mode = xdp_qs_cfg.mapping_mode;
2455 if (__ice_vsi_get_qs(&xdp_qs_cfg))
2456 goto err_map_xdp;
2457
2458 if (ice_xdp_alloc_setup_rings(vsi))
2459 goto clear_xdp_rings;
2460
2461
2462 ice_for_each_q_vector(vsi, v_idx) {
2463 struct ice_q_vector *q_vector = vsi->q_vectors[v_idx];
2464 int xdp_rings_per_v, q_id, q_base;
2465
2466 xdp_rings_per_v = DIV_ROUND_UP(xdp_rings_rem,
2467 vsi->num_q_vectors - v_idx);
2468 q_base = vsi->num_xdp_txq - xdp_rings_rem;
2469
2470 for (q_id = q_base; q_id < (q_base + xdp_rings_per_v); q_id++) {
2471 struct ice_ring *xdp_ring = vsi->xdp_rings[q_id];
2472
2473 xdp_ring->q_vector = q_vector;
2474 xdp_ring->next = q_vector->tx.ring;
2475 q_vector->tx.ring = xdp_ring;
2476 }
2477 xdp_rings_rem -= xdp_rings_per_v;
2478 }
2479
2480
2481
2482
2483
2484 if (ice_is_reset_in_progress(pf->state))
2485 return 0;
2486
2487
2488
2489
2490 for (i = 0; i < vsi->tc_cfg.numtc; i++)
2491 max_txqs[i] = vsi->num_txq + vsi->num_xdp_txq;
2492
2493 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
2494 max_txqs);
2495 if (status) {
2496 dev_err(dev, "Failed VSI LAN queue config for XDP, error: %s\n",
2497 ice_stat_str(status));
2498 goto clear_xdp_rings;
2499 }
2500 ice_vsi_assign_bpf_prog(vsi, prog);
2501
2502 return 0;
2503clear_xdp_rings:
2504 for (i = 0; i < vsi->num_xdp_txq; i++)
2505 if (vsi->xdp_rings[i]) {
2506 kfree_rcu(vsi->xdp_rings[i], rcu);
2507 vsi->xdp_rings[i] = NULL;
2508 }
2509
2510err_map_xdp:
2511 mutex_lock(&pf->avail_q_mutex);
2512 for (i = 0; i < vsi->num_xdp_txq; i++) {
2513 clear_bit(vsi->txq_map[i + vsi->alloc_txq], pf->avail_txqs);
2514 vsi->txq_map[i + vsi->alloc_txq] = ICE_INVAL_Q_INDEX;
2515 }
2516 mutex_unlock(&pf->avail_q_mutex);
2517
2518 devm_kfree(dev, vsi->xdp_rings);
2519 return -ENOMEM;
2520}
2521
2522
2523
2524
2525
2526
2527
2528
2529int ice_destroy_xdp_rings(struct ice_vsi *vsi)
2530{
2531 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
2532 struct ice_pf *pf = vsi->back;
2533 int i, v_idx;
2534
2535
2536
2537
2538
2539
2540 if (ice_is_reset_in_progress(pf->state) || !vsi->q_vectors[0])
2541 goto free_qmap;
2542
2543 ice_for_each_q_vector(vsi, v_idx) {
2544 struct ice_q_vector *q_vector = vsi->q_vectors[v_idx];
2545 struct ice_ring *ring;
2546
2547 ice_for_each_ring(ring, q_vector->tx)
2548 if (!ring->tx_buf || !ice_ring_is_xdp(ring))
2549 break;
2550
2551
2552 q_vector->tx.ring = ring;
2553 }
2554
2555free_qmap:
2556 mutex_lock(&pf->avail_q_mutex);
2557 for (i = 0; i < vsi->num_xdp_txq; i++) {
2558 clear_bit(vsi->txq_map[i + vsi->alloc_txq], pf->avail_txqs);
2559 vsi->txq_map[i + vsi->alloc_txq] = ICE_INVAL_Q_INDEX;
2560 }
2561 mutex_unlock(&pf->avail_q_mutex);
2562
2563 for (i = 0; i < vsi->num_xdp_txq; i++)
2564 if (vsi->xdp_rings[i]) {
2565 if (vsi->xdp_rings[i]->desc)
2566 ice_free_tx_ring(vsi->xdp_rings[i]);
2567 kfree_rcu(vsi->xdp_rings[i], rcu);
2568 vsi->xdp_rings[i] = NULL;
2569 }
2570
2571 devm_kfree(ice_pf_to_dev(pf), vsi->xdp_rings);
2572 vsi->xdp_rings = NULL;
2573
2574 if (ice_is_reset_in_progress(pf->state) || !vsi->q_vectors[0])
2575 return 0;
2576
2577 ice_vsi_assign_bpf_prog(vsi, NULL);
2578
2579
2580
2581
2582 for (i = 0; i < vsi->tc_cfg.numtc; i++)
2583 max_txqs[i] = vsi->num_txq;
2584
2585
2586 vsi->num_xdp_txq = 0;
2587
2588 return ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
2589 max_txqs);
2590}
2591
2592
2593
2594
2595
2596static void ice_vsi_rx_napi_schedule(struct ice_vsi *vsi)
2597{
2598 int i;
2599
2600 ice_for_each_rxq(vsi, i) {
2601 struct ice_ring *rx_ring = vsi->rx_rings[i];
2602
2603 if (rx_ring->xsk_pool)
2604 napi_schedule(&rx_ring->q_vector->napi);
2605 }
2606}
2607
2608
2609
2610
2611
2612
2613
2614static int
2615ice_xdp_setup_prog(struct ice_vsi *vsi, struct bpf_prog *prog,
2616 struct netlink_ext_ack *extack)
2617{
2618 int frame_size = vsi->netdev->mtu + ICE_ETH_PKT_HDR_PAD;
2619 bool if_running = netif_running(vsi->netdev);
2620 int ret = 0, xdp_ring_err = 0;
2621
2622 if (frame_size > vsi->rx_buf_len) {
2623 NL_SET_ERR_MSG_MOD(extack, "MTU too large for loading XDP");
2624 return -EOPNOTSUPP;
2625 }
2626
2627
2628 if (if_running && !test_and_set_bit(ICE_VSI_DOWN, vsi->state)) {
2629 ret = ice_down(vsi);
2630 if (ret) {
2631 NL_SET_ERR_MSG_MOD(extack, "Preparing device for XDP attach failed");
2632 return ret;
2633 }
2634 }
2635
2636 if (!ice_is_xdp_ena_vsi(vsi) && prog) {
2637 vsi->num_xdp_txq = vsi->alloc_rxq;
2638 xdp_ring_err = ice_prepare_xdp_rings(vsi, prog);
2639 if (xdp_ring_err)
2640 NL_SET_ERR_MSG_MOD(extack, "Setting up XDP Tx resources failed");
2641 } else if (ice_is_xdp_ena_vsi(vsi) && !prog) {
2642 xdp_ring_err = ice_destroy_xdp_rings(vsi);
2643 if (xdp_ring_err)
2644 NL_SET_ERR_MSG_MOD(extack, "Freeing XDP Tx resources failed");
2645 } else {
2646 ice_vsi_assign_bpf_prog(vsi, prog);
2647 }
2648
2649 if (if_running)
2650 ret = ice_up(vsi);
2651
2652 if (!ret && prog)
2653 ice_vsi_rx_napi_schedule(vsi);
2654
2655 return (ret || xdp_ring_err) ? -ENOMEM : 0;
2656}
2657
2658
2659
2660
2661
2662
2663static int ice_xdp_safe_mode(struct net_device __always_unused *dev,
2664 struct netdev_bpf *xdp)
2665{
2666 NL_SET_ERR_MSG_MOD(xdp->extack,
2667 "Please provide working DDP firmware package in order to use XDP\n"
2668 "Refer to Documentation/networking/device_drivers/ethernet/intel/ice.rst");
2669 return -EOPNOTSUPP;
2670}
2671
2672
2673
2674
2675
2676
2677static int ice_xdp(struct net_device *dev, struct netdev_bpf *xdp)
2678{
2679 struct ice_netdev_priv *np = netdev_priv(dev);
2680 struct ice_vsi *vsi = np->vsi;
2681
2682 if (vsi->type != ICE_VSI_PF) {
2683 NL_SET_ERR_MSG_MOD(xdp->extack, "XDP can be loaded only on PF VSI");
2684 return -EINVAL;
2685 }
2686
2687 switch (xdp->command) {
2688 case XDP_SETUP_PROG:
2689 return ice_xdp_setup_prog(vsi, xdp->prog, xdp->extack);
2690 case XDP_SETUP_XSK_POOL:
2691 return ice_xsk_pool_setup(vsi, xdp->xsk.pool,
2692 xdp->xsk.queue_id);
2693 default:
2694 return -EINVAL;
2695 }
2696}
2697
2698
2699
2700
2701
2702static void ice_ena_misc_vector(struct ice_pf *pf)
2703{
2704 struct ice_hw *hw = &pf->hw;
2705 u32 val;
2706
2707
2708
2709
2710
2711 val = rd32(hw, GL_MDCK_TX_TDPU);
2712 val |= GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M;
2713 wr32(hw, GL_MDCK_TX_TDPU, val);
2714
2715
2716 wr32(hw, PFINT_OICR_ENA, 0);
2717 rd32(hw, PFINT_OICR);
2718
2719 val = (PFINT_OICR_ECC_ERR_M |
2720 PFINT_OICR_MAL_DETECT_M |
2721 PFINT_OICR_GRST_M |
2722 PFINT_OICR_PCI_EXCEPTION_M |
2723 PFINT_OICR_VFLR_M |
2724 PFINT_OICR_HMC_ERR_M |
2725 PFINT_OICR_PE_PUSH_M |
2726 PFINT_OICR_PE_CRITERR_M);
2727
2728 wr32(hw, PFINT_OICR_ENA, val);
2729
2730
2731 wr32(hw, GLINT_DYN_CTL(pf->oicr_idx),
2732 GLINT_DYN_CTL_SW_ITR_INDX_M | GLINT_DYN_CTL_INTENA_MSK_M);
2733}
2734
2735
2736
2737
2738
2739
2740static irqreturn_t ice_misc_intr(int __always_unused irq, void *data)
2741{
2742 struct ice_pf *pf = (struct ice_pf *)data;
2743 struct ice_hw *hw = &pf->hw;
2744 irqreturn_t ret = IRQ_NONE;
2745 struct device *dev;
2746 u32 oicr, ena_mask;
2747
2748 dev = ice_pf_to_dev(pf);
2749 set_bit(ICE_ADMINQ_EVENT_PENDING, pf->state);
2750 set_bit(ICE_MAILBOXQ_EVENT_PENDING, pf->state);
2751 set_bit(ICE_SIDEBANDQ_EVENT_PENDING, pf->state);
2752
2753 oicr = rd32(hw, PFINT_OICR);
2754 ena_mask = rd32(hw, PFINT_OICR_ENA);
2755
2756 if (oicr & PFINT_OICR_SWINT_M) {
2757 ena_mask &= ~PFINT_OICR_SWINT_M;
2758 pf->sw_int_count++;
2759 }
2760
2761 if (oicr & PFINT_OICR_MAL_DETECT_M) {
2762 ena_mask &= ~PFINT_OICR_MAL_DETECT_M;
2763 set_bit(ICE_MDD_EVENT_PENDING, pf->state);
2764 }
2765 if (oicr & PFINT_OICR_VFLR_M) {
2766
2767 if (test_bit(ICE_VF_RESETS_DISABLED, pf->state)) {
2768 u32 reg = rd32(hw, PFINT_OICR_ENA);
2769
2770 reg &= ~PFINT_OICR_VFLR_M;
2771 wr32(hw, PFINT_OICR_ENA, reg);
2772 } else {
2773 ena_mask &= ~PFINT_OICR_VFLR_M;
2774 set_bit(ICE_VFLR_EVENT_PENDING, pf->state);
2775 }
2776 }
2777
2778 if (oicr & PFINT_OICR_GRST_M) {
2779 u32 reset;
2780
2781
2782 ena_mask &= ~PFINT_OICR_GRST_M;
2783 reset = (rd32(hw, GLGEN_RSTAT) & GLGEN_RSTAT_RESET_TYPE_M) >>
2784 GLGEN_RSTAT_RESET_TYPE_S;
2785
2786 if (reset == ICE_RESET_CORER)
2787 pf->corer_count++;
2788 else if (reset == ICE_RESET_GLOBR)
2789 pf->globr_count++;
2790 else if (reset == ICE_RESET_EMPR)
2791 pf->empr_count++;
2792 else
2793 dev_dbg(dev, "Invalid reset type %d\n", reset);
2794
2795
2796
2797
2798 if (!test_and_set_bit(ICE_RESET_OICR_RECV, pf->state)) {
2799 if (reset == ICE_RESET_CORER)
2800 set_bit(ICE_CORER_RECV, pf->state);
2801 else if (reset == ICE_RESET_GLOBR)
2802 set_bit(ICE_GLOBR_RECV, pf->state);
2803 else
2804 set_bit(ICE_EMPR_RECV, pf->state);
2805
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819 hw->reset_ongoing = true;
2820 }
2821 }
2822
2823 if (oicr & PFINT_OICR_TSYN_TX_M) {
2824 ena_mask &= ~PFINT_OICR_TSYN_TX_M;
2825 ice_ptp_process_ts(pf);
2826 }
2827
2828 if (oicr & PFINT_OICR_TSYN_EVNT_M) {
2829 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned;
2830 u32 gltsyn_stat = rd32(hw, GLTSYN_STAT(tmr_idx));
2831
2832
2833 pf->ptp.ext_ts_irq |= gltsyn_stat & (GLTSYN_STAT_EVENT0_M |
2834 GLTSYN_STAT_EVENT1_M |
2835 GLTSYN_STAT_EVENT2_M);
2836 ena_mask &= ~PFINT_OICR_TSYN_EVNT_M;
2837 kthread_queue_work(pf->ptp.kworker, &pf->ptp.extts_work);
2838 }
2839
2840#define ICE_AUX_CRIT_ERR (PFINT_OICR_PE_CRITERR_M | PFINT_OICR_HMC_ERR_M | PFINT_OICR_PE_PUSH_M)
2841 if (oicr & ICE_AUX_CRIT_ERR) {
2842 struct iidc_event *event;
2843
2844 ena_mask &= ~ICE_AUX_CRIT_ERR;
2845 event = kzalloc(sizeof(*event), GFP_KERNEL);
2846 if (event) {
2847 set_bit(IIDC_EVENT_CRIT_ERR, event->type);
2848
2849 event->reg = oicr;
2850 ice_send_event_to_aux(pf, event);
2851 kfree(event);
2852 }
2853 }
2854
2855
2856 oicr &= ena_mask;
2857 if (oicr) {
2858 dev_dbg(dev, "unhandled interrupt oicr=0x%08x\n", oicr);
2859
2860
2861
2862 if (oicr & (PFINT_OICR_PCI_EXCEPTION_M |
2863 PFINT_OICR_ECC_ERR_M)) {
2864 set_bit(ICE_PFR_REQ, pf->state);
2865 ice_service_task_schedule(pf);
2866 }
2867 }
2868 ret = IRQ_HANDLED;
2869
2870 ice_service_task_schedule(pf);
2871 ice_irq_dynamic_ena(hw, NULL, NULL);
2872
2873 return ret;
2874}
2875
2876
2877
2878
2879
2880static void ice_dis_ctrlq_interrupts(struct ice_hw *hw)
2881{
2882
2883 wr32(hw, PFINT_FW_CTL,
2884 rd32(hw, PFINT_FW_CTL) & ~PFINT_FW_CTL_CAUSE_ENA_M);
2885
2886
2887 wr32(hw, PFINT_MBX_CTL,
2888 rd32(hw, PFINT_MBX_CTL) & ~PFINT_MBX_CTL_CAUSE_ENA_M);
2889
2890 wr32(hw, PFINT_SB_CTL,
2891 rd32(hw, PFINT_SB_CTL) & ~PFINT_SB_CTL_CAUSE_ENA_M);
2892
2893
2894 wr32(hw, PFINT_OICR_CTL,
2895 rd32(hw, PFINT_OICR_CTL) & ~PFINT_OICR_CTL_CAUSE_ENA_M);
2896
2897 ice_flush(hw);
2898}
2899
2900
2901
2902
2903
2904static void ice_free_irq_msix_misc(struct ice_pf *pf)
2905{
2906 struct ice_hw *hw = &pf->hw;
2907
2908 ice_dis_ctrlq_interrupts(hw);
2909
2910
2911 wr32(hw, PFINT_OICR_ENA, 0);
2912 ice_flush(hw);
2913
2914 if (pf->msix_entries) {
2915 synchronize_irq(pf->msix_entries[pf->oicr_idx].vector);
2916 devm_free_irq(ice_pf_to_dev(pf),
2917 pf->msix_entries[pf->oicr_idx].vector, pf);
2918 }
2919
2920 pf->num_avail_sw_msix += 1;
2921 ice_free_res(pf->irq_tracker, pf->oicr_idx, ICE_RES_MISC_VEC_ID);
2922}
2923
2924
2925
2926
2927
2928
2929static void ice_ena_ctrlq_interrupts(struct ice_hw *hw, u16 reg_idx)
2930{
2931 u32 val;
2932
2933 val = ((reg_idx & PFINT_OICR_CTL_MSIX_INDX_M) |
2934 PFINT_OICR_CTL_CAUSE_ENA_M);
2935 wr32(hw, PFINT_OICR_CTL, val);
2936
2937
2938 val = ((reg_idx & PFINT_FW_CTL_MSIX_INDX_M) |
2939 PFINT_FW_CTL_CAUSE_ENA_M);
2940 wr32(hw, PFINT_FW_CTL, val);
2941
2942
2943 val = ((reg_idx & PFINT_MBX_CTL_MSIX_INDX_M) |
2944 PFINT_MBX_CTL_CAUSE_ENA_M);
2945 wr32(hw, PFINT_MBX_CTL, val);
2946
2947
2948 val = ((reg_idx & PFINT_SB_CTL_MSIX_INDX_M) |
2949 PFINT_SB_CTL_CAUSE_ENA_M);
2950 wr32(hw, PFINT_SB_CTL, val);
2951
2952 ice_flush(hw);
2953}
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963static int ice_req_irq_msix_misc(struct ice_pf *pf)
2964{
2965 struct device *dev = ice_pf_to_dev(pf);
2966 struct ice_hw *hw = &pf->hw;
2967 int oicr_idx, err = 0;
2968
2969 if (!pf->int_name[0])
2970 snprintf(pf->int_name, sizeof(pf->int_name) - 1, "%s-%s:misc",
2971 dev_driver_string(dev), dev_name(dev));
2972
2973
2974
2975
2976
2977 if (ice_is_reset_in_progress(pf->state))
2978 goto skip_req_irq;
2979
2980
2981 oicr_idx = ice_get_res(pf, pf->irq_tracker, 1, ICE_RES_MISC_VEC_ID);
2982 if (oicr_idx < 0)
2983 return oicr_idx;
2984
2985 pf->num_avail_sw_msix -= 1;
2986 pf->oicr_idx = (u16)oicr_idx;
2987
2988 err = devm_request_irq(dev, pf->msix_entries[pf->oicr_idx].vector,
2989 ice_misc_intr, 0, pf->int_name, pf);
2990 if (err) {
2991 dev_err(dev, "devm_request_irq for %s failed: %d\n",
2992 pf->int_name, err);
2993 ice_free_res(pf->irq_tracker, 1, ICE_RES_MISC_VEC_ID);
2994 pf->num_avail_sw_msix += 1;
2995 return err;
2996 }
2997
2998skip_req_irq:
2999 ice_ena_misc_vector(pf);
3000
3001 ice_ena_ctrlq_interrupts(hw, pf->oicr_idx);
3002 wr32(hw, GLINT_ITR(ICE_RX_ITR, pf->oicr_idx),
3003 ITR_REG_ALIGN(ICE_ITR_8K) >> ICE_ITR_GRAN_S);
3004
3005 ice_flush(hw);
3006 ice_irq_dynamic_ena(hw, NULL, NULL);
3007
3008 return 0;
3009}
3010
3011
3012
3013
3014
3015
3016
3017
3018
3019static void ice_napi_add(struct ice_vsi *vsi)
3020{
3021 int v_idx;
3022
3023 if (!vsi->netdev)
3024 return;
3025
3026 ice_for_each_q_vector(vsi, v_idx)
3027 netif_napi_add(vsi->netdev, &vsi->q_vectors[v_idx]->napi,
3028 ice_napi_poll, NAPI_POLL_WEIGHT);
3029}
3030
3031
3032
3033
3034
3035static void ice_set_ops(struct net_device *netdev)
3036{
3037 struct ice_pf *pf = ice_netdev_to_pf(netdev);
3038
3039 if (ice_is_safe_mode(pf)) {
3040 netdev->netdev_ops = &ice_netdev_safe_mode_ops;
3041 ice_set_ethtool_safe_mode_ops(netdev);
3042 return;
3043 }
3044
3045 netdev->netdev_ops = &ice_netdev_ops;
3046 netdev->udp_tunnel_nic_info = &pf->hw.udp_tunnel_nic;
3047 ice_set_ethtool_ops(netdev);
3048}
3049
3050
3051
3052
3053
3054static void ice_set_netdev_features(struct net_device *netdev)
3055{
3056 struct ice_pf *pf = ice_netdev_to_pf(netdev);
3057 netdev_features_t csumo_features;
3058 netdev_features_t vlano_features;
3059 netdev_features_t dflt_features;
3060 netdev_features_t tso_features;
3061
3062 if (ice_is_safe_mode(pf)) {
3063
3064 netdev->features = NETIF_F_SG | NETIF_F_HIGHDMA;
3065 netdev->hw_features = netdev->features;
3066 return;
3067 }
3068
3069 dflt_features = NETIF_F_SG |
3070 NETIF_F_HIGHDMA |
3071 NETIF_F_NTUPLE |
3072 NETIF_F_RXHASH;
3073
3074 csumo_features = NETIF_F_RXCSUM |
3075 NETIF_F_IP_CSUM |
3076 NETIF_F_SCTP_CRC |
3077 NETIF_F_IPV6_CSUM;
3078
3079 vlano_features = NETIF_F_HW_VLAN_CTAG_FILTER |
3080 NETIF_F_HW_VLAN_CTAG_TX |
3081 NETIF_F_HW_VLAN_CTAG_RX;
3082
3083 tso_features = NETIF_F_TSO |
3084 NETIF_F_TSO_ECN |
3085 NETIF_F_TSO6 |
3086 NETIF_F_GSO_GRE |
3087 NETIF_F_GSO_UDP_TUNNEL |
3088 NETIF_F_GSO_GRE_CSUM |
3089 NETIF_F_GSO_UDP_TUNNEL_CSUM |
3090 NETIF_F_GSO_PARTIAL |
3091 NETIF_F_GSO_IPXIP4 |
3092 NETIF_F_GSO_IPXIP6 |
3093 NETIF_F_GSO_UDP_L4;
3094
3095 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM |
3096 NETIF_F_GSO_GRE_CSUM;
3097
3098 netdev->hw_features = dflt_features | csumo_features |
3099 vlano_features | tso_features;
3100
3101
3102 netdev->mpls_features = NETIF_F_HW_CSUM;
3103
3104
3105 netdev->features |= netdev->hw_features;
3106
3107 netdev->hw_enc_features |= dflt_features | csumo_features |
3108 tso_features;
3109 netdev->vlan_features |= dflt_features | csumo_features |
3110 tso_features;
3111}
3112
3113
3114
3115
3116
3117
3118
3119static int ice_cfg_netdev(struct ice_vsi *vsi)
3120{
3121 struct ice_netdev_priv *np;
3122 struct net_device *netdev;
3123 u8 mac_addr[ETH_ALEN];
3124
3125 netdev = alloc_etherdev_mqs(sizeof(*np), vsi->alloc_txq,
3126 vsi->alloc_rxq);
3127 if (!netdev)
3128 return -ENOMEM;
3129
3130 set_bit(ICE_VSI_NETDEV_ALLOCD, vsi->state);
3131 vsi->netdev = netdev;
3132 np = netdev_priv(netdev);
3133 np->vsi = vsi;
3134
3135 ice_set_netdev_features(netdev);
3136
3137 ice_set_ops(netdev);
3138
3139 if (vsi->type == ICE_VSI_PF) {
3140 SET_NETDEV_DEV(netdev, ice_pf_to_dev(vsi->back));
3141 ether_addr_copy(mac_addr, vsi->port_info->mac.perm_addr);
3142 ether_addr_copy(netdev->dev_addr, mac_addr);
3143 ether_addr_copy(netdev->perm_addr, mac_addr);
3144 }
3145
3146 netdev->priv_flags |= IFF_UNICAST_FLT;
3147
3148
3149 ice_vsi_cfg_netdev_tc(vsi, vsi->tc_cfg.ena_tc);
3150
3151
3152 netdev->watchdog_timeo = 5 * HZ;
3153
3154 netdev->min_mtu = ETH_MIN_MTU;
3155 netdev->max_mtu = ICE_MAX_MTU;
3156
3157 return 0;
3158}
3159
3160
3161
3162
3163
3164
3165
3166void ice_fill_rss_lut(u8 *lut, u16 rss_table_size, u16 rss_size)
3167{
3168 u16 i;
3169
3170 for (i = 0; i < rss_table_size; i++)
3171 lut[i] = i % rss_size;
3172}
3173
3174
3175
3176
3177
3178
3179
3180
3181
3182static struct ice_vsi *
3183ice_pf_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi)
3184{
3185 return ice_vsi_setup(pf, pi, ICE_VSI_PF, ICE_INVAL_VFID);
3186}
3187
3188
3189
3190
3191
3192
3193
3194
3195
3196static struct ice_vsi *
3197ice_ctrl_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi)
3198{
3199 return ice_vsi_setup(pf, pi, ICE_VSI_CTRL, ICE_INVAL_VFID);
3200}
3201
3202
3203
3204
3205
3206
3207
3208
3209
3210struct ice_vsi *
3211ice_lb_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi)
3212{
3213 return ice_vsi_setup(pf, pi, ICE_VSI_LB, ICE_INVAL_VFID);
3214}
3215
3216
3217
3218
3219
3220
3221
3222
3223
3224static int
3225ice_vlan_rx_add_vid(struct net_device *netdev, __always_unused __be16 proto,
3226 u16 vid)
3227{
3228 struct ice_netdev_priv *np = netdev_priv(netdev);
3229 struct ice_vsi *vsi = np->vsi;
3230 int ret;
3231
3232
3233 if (!vid)
3234 return 0;
3235
3236
3237 if (!ice_vsi_is_vlan_pruning_ena(vsi)) {
3238 ret = ice_cfg_vlan_pruning(vsi, true, false);
3239 if (ret)
3240 return ret;
3241 }
3242
3243
3244
3245
3246 ret = ice_vsi_add_vlan(vsi, vid, ICE_FWD_TO_VSI);
3247 if (!ret)
3248 set_bit(ICE_VSI_VLAN_FLTR_CHANGED, vsi->state);
3249
3250 return ret;
3251}
3252
3253
3254
3255
3256
3257
3258
3259
3260
3261static int
3262ice_vlan_rx_kill_vid(struct net_device *netdev, __always_unused __be16 proto,
3263 u16 vid)
3264{
3265 struct ice_netdev_priv *np = netdev_priv(netdev);
3266 struct ice_vsi *vsi = np->vsi;
3267 int ret;
3268
3269
3270 if (!vid)
3271 return 0;
3272
3273
3274
3275
3276 ret = ice_vsi_kill_vlan(vsi, vid);
3277 if (ret)
3278 return ret;
3279
3280
3281 if (vsi->num_vlan == 1 && ice_vsi_is_vlan_pruning_ena(vsi))
3282 ret = ice_cfg_vlan_pruning(vsi, false, false);
3283
3284 set_bit(ICE_VSI_VLAN_FLTR_CHANGED, vsi->state);
3285 return ret;
3286}
3287
3288
3289
3290
3291
3292
3293
3294static int ice_setup_pf_sw(struct ice_pf *pf)
3295{
3296 struct ice_vsi *vsi;
3297 int status = 0;
3298
3299 if (ice_is_reset_in_progress(pf->state))
3300 return -EBUSY;
3301
3302 vsi = ice_pf_vsi_setup(pf, pf->hw.port_info);
3303 if (!vsi)
3304 return -ENOMEM;
3305
3306 status = ice_cfg_netdev(vsi);
3307 if (status) {
3308 status = -ENODEV;
3309 goto unroll_vsi_setup;
3310 }
3311
3312 ice_vsi_cfg_frame_size(vsi);
3313
3314
3315 ice_dcbnl_setup(vsi);
3316
3317
3318
3319
3320
3321 ice_napi_add(vsi);
3322
3323 status = ice_set_cpu_rx_rmap(vsi);
3324 if (status) {
3325 dev_err(ice_pf_to_dev(pf), "Failed to set CPU Rx map VSI %d error %d\n",
3326 vsi->vsi_num, status);
3327 status = -EINVAL;
3328 goto unroll_napi_add;
3329 }
3330 status = ice_init_mac_fltr(pf);
3331 if (status)
3332 goto free_cpu_rx_map;
3333
3334 return status;
3335
3336free_cpu_rx_map:
3337 ice_free_cpu_rx_rmap(vsi);
3338
3339unroll_napi_add:
3340 if (vsi) {
3341 ice_napi_del(vsi);
3342 if (vsi->netdev) {
3343 clear_bit(ICE_VSI_NETDEV_ALLOCD, vsi->state);
3344 free_netdev(vsi->netdev);
3345 vsi->netdev = NULL;
3346 }
3347 }
3348
3349unroll_vsi_setup:
3350 ice_vsi_release(vsi);
3351 return status;
3352}
3353
3354
3355
3356
3357
3358
3359
3360static u16
3361ice_get_avail_q_count(unsigned long *pf_qmap, struct mutex *lock, u16 size)
3362{
3363 unsigned long bit;
3364 u16 count = 0;
3365
3366 mutex_lock(lock);
3367 for_each_clear_bit(bit, pf_qmap, size)
3368 count++;
3369 mutex_unlock(lock);
3370
3371 return count;
3372}
3373
3374
3375
3376
3377
3378u16 ice_get_avail_txq_count(struct ice_pf *pf)
3379{
3380 return ice_get_avail_q_count(pf->avail_txqs, &pf->avail_q_mutex,
3381 pf->max_pf_txqs);
3382}
3383
3384
3385
3386
3387
3388u16 ice_get_avail_rxq_count(struct ice_pf *pf)
3389{
3390 return ice_get_avail_q_count(pf->avail_rxqs, &pf->avail_q_mutex,
3391 pf->max_pf_rxqs);
3392}
3393
3394
3395
3396
3397
3398static void ice_deinit_pf(struct ice_pf *pf)
3399{
3400 ice_service_task_stop(pf);
3401 mutex_destroy(&pf->sw_mutex);
3402 mutex_destroy(&pf->tc_mutex);
3403 mutex_destroy(&pf->avail_q_mutex);
3404
3405 if (pf->avail_txqs) {
3406 bitmap_free(pf->avail_txqs);
3407 pf->avail_txqs = NULL;
3408 }
3409
3410 if (pf->avail_rxqs) {
3411 bitmap_free(pf->avail_rxqs);
3412 pf->avail_rxqs = NULL;
3413 }
3414
3415 if (pf->ptp.clock)
3416 ptp_clock_unregister(pf->ptp.clock);
3417}
3418
3419
3420
3421
3422
3423static void ice_set_pf_caps(struct ice_pf *pf)
3424{
3425 struct ice_hw_func_caps *func_caps = &pf->hw.func_caps;
3426
3427 clear_bit(ICE_FLAG_RDMA_ENA, pf->flags);
3428 clear_bit(ICE_FLAG_AUX_ENA, pf->flags);
3429 if (func_caps->common_cap.rdma) {
3430 set_bit(ICE_FLAG_RDMA_ENA, pf->flags);
3431 set_bit(ICE_FLAG_AUX_ENA, pf->flags);
3432 }
3433 clear_bit(ICE_FLAG_DCB_CAPABLE, pf->flags);
3434 if (func_caps->common_cap.dcb)
3435 set_bit(ICE_FLAG_DCB_CAPABLE, pf->flags);
3436 clear_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
3437 if (func_caps->common_cap.sr_iov_1_1) {
3438 set_bit(ICE_FLAG_SRIOV_CAPABLE, pf->flags);
3439 pf->num_vfs_supported = min_t(int, func_caps->num_allocd_vfs,
3440 ICE_MAX_VF_COUNT);
3441 }
3442 clear_bit(ICE_FLAG_RSS_ENA, pf->flags);
3443 if (func_caps->common_cap.rss_table_size)
3444 set_bit(ICE_FLAG_RSS_ENA, pf->flags);
3445
3446 clear_bit(ICE_FLAG_FD_ENA, pf->flags);
3447 if (func_caps->fd_fltr_guar > 0 || func_caps->fd_fltr_best_effort > 0) {
3448 u16 unused;
3449
3450
3451
3452
3453 pf->ctrl_vsi_idx = ICE_NO_VSI;
3454 set_bit(ICE_FLAG_FD_ENA, pf->flags);
3455
3456 ice_alloc_fd_guar_item(&pf->hw, &unused,
3457 func_caps->fd_fltr_guar);
3458
3459 ice_alloc_fd_shrd_item(&pf->hw, &unused,
3460 func_caps->fd_fltr_best_effort);
3461 }
3462
3463 clear_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
3464 if (func_caps->common_cap.ieee_1588)
3465 set_bit(ICE_FLAG_PTP_SUPPORTED, pf->flags);
3466
3467 pf->max_pf_txqs = func_caps->common_cap.num_txq;
3468 pf->max_pf_rxqs = func_caps->common_cap.num_rxq;
3469}
3470
3471
3472
3473
3474
3475static int ice_init_pf(struct ice_pf *pf)
3476{
3477 ice_set_pf_caps(pf);
3478
3479 mutex_init(&pf->sw_mutex);
3480 mutex_init(&pf->tc_mutex);
3481
3482 INIT_HLIST_HEAD(&pf->aq_wait_list);
3483 spin_lock_init(&pf->aq_wait_lock);
3484 init_waitqueue_head(&pf->aq_wait_queue);
3485
3486 init_waitqueue_head(&pf->reset_wait_queue);
3487
3488
3489 timer_setup(&pf->serv_tmr, ice_service_timer, 0);
3490 pf->serv_tmr_period = HZ;
3491 INIT_WORK(&pf->serv_task, ice_service_task);
3492 clear_bit(ICE_SERVICE_SCHED, pf->state);
3493
3494 mutex_init(&pf->avail_q_mutex);
3495 pf->avail_txqs = bitmap_zalloc(pf->max_pf_txqs, GFP_KERNEL);
3496 if (!pf->avail_txqs)
3497 return -ENOMEM;
3498
3499 pf->avail_rxqs = bitmap_zalloc(pf->max_pf_rxqs, GFP_KERNEL);
3500 if (!pf->avail_rxqs) {
3501 devm_kfree(ice_pf_to_dev(pf), pf->avail_txqs);
3502 pf->avail_txqs = NULL;
3503 return -ENOMEM;
3504 }
3505
3506 return 0;
3507}
3508
3509
3510
3511
3512
3513
3514
3515
3516static int ice_ena_msix_range(struct ice_pf *pf)
3517{
3518 int num_cpus, v_left, v_actual, v_other, v_budget = 0;
3519 struct device *dev = ice_pf_to_dev(pf);
3520 int needed, err, i;
3521
3522 v_left = pf->hw.func_caps.common_cap.num_msix_vectors;
3523 num_cpus = num_online_cpus();
3524
3525
3526 needed = ICE_MIN_LAN_OICR_MSIX;
3527 if (v_left < needed)
3528 goto no_hw_vecs_left_err;
3529 v_budget += needed;
3530 v_left -= needed;
3531
3532
3533 if (test_bit(ICE_FLAG_FD_ENA, pf->flags)) {
3534 needed = ICE_FDIR_MSIX;
3535 if (v_left < needed)
3536 goto no_hw_vecs_left_err;
3537 v_budget += needed;
3538 v_left -= needed;
3539 }
3540
3541
3542 v_other = v_budget;
3543
3544
3545 needed = num_cpus;
3546 if (v_left < needed)
3547 goto no_hw_vecs_left_err;
3548 pf->num_lan_msix = needed;
3549 v_budget += needed;
3550 v_left -= needed;
3551
3552
3553 if (test_bit(ICE_FLAG_RDMA_ENA, pf->flags)) {
3554 needed = num_cpus + ICE_RDMA_NUM_AEQ_MSIX;
3555 if (v_left < needed)
3556 goto no_hw_vecs_left_err;
3557 pf->num_rdma_msix = needed;
3558 v_budget += needed;
3559 v_left -= needed;
3560 }
3561
3562 pf->msix_entries = devm_kcalloc(dev, v_budget,
3563 sizeof(*pf->msix_entries), GFP_KERNEL);
3564 if (!pf->msix_entries) {
3565 err = -ENOMEM;
3566 goto exit_err;
3567 }
3568
3569 for (i = 0; i < v_budget; i++)
3570 pf->msix_entries[i].entry = i;
3571
3572
3573 v_actual = pci_enable_msix_range(pf->pdev, pf->msix_entries,
3574 ICE_MIN_MSIX, v_budget);
3575 if (v_actual < 0) {
3576 dev_err(dev, "unable to reserve MSI-X vectors\n");
3577 err = v_actual;
3578 goto msix_err;
3579 }
3580
3581 if (v_actual < v_budget) {
3582 dev_warn(dev, "not enough OS MSI-X vectors. requested = %d, obtained = %d\n",
3583 v_budget, v_actual);
3584
3585 if (v_actual < ICE_MIN_MSIX) {
3586
3587 pci_disable_msix(pf->pdev);
3588 err = -ERANGE;
3589 goto msix_err;
3590 } else {
3591 int v_remain = v_actual - v_other;
3592 int v_rdma = 0, v_min_rdma = 0;
3593
3594 if (test_bit(ICE_FLAG_RDMA_ENA, pf->flags)) {
3595
3596
3597
3598 v_rdma = ICE_RDMA_NUM_AEQ_MSIX + 1;
3599 v_min_rdma = ICE_MIN_RDMA_MSIX;
3600 }
3601
3602 if (v_actual == ICE_MIN_MSIX ||
3603 v_remain < ICE_MIN_LAN_TXRX_MSIX + v_min_rdma) {
3604 dev_warn(dev, "Not enough MSI-X vectors to support RDMA.\n");
3605 clear_bit(ICE_FLAG_RDMA_ENA, pf->flags);
3606
3607 pf->num_rdma_msix = 0;
3608 pf->num_lan_msix = ICE_MIN_LAN_TXRX_MSIX;
3609 } else if ((v_remain < ICE_MIN_LAN_TXRX_MSIX + v_rdma) ||
3610 (v_remain - v_rdma < v_rdma)) {
3611
3612
3613
3614 pf->num_rdma_msix = v_min_rdma;
3615 pf->num_lan_msix = v_remain - v_min_rdma;
3616 } else {
3617
3618
3619
3620 pf->num_rdma_msix = (v_remain - ICE_RDMA_NUM_AEQ_MSIX) / 2 +
3621 ICE_RDMA_NUM_AEQ_MSIX;
3622 pf->num_lan_msix = v_remain - pf->num_rdma_msix;
3623 }
3624
3625 dev_notice(dev, "Enabled %d MSI-X vectors for LAN traffic.\n",
3626 pf->num_lan_msix);
3627
3628 if (test_bit(ICE_FLAG_RDMA_ENA, pf->flags))
3629 dev_notice(dev, "Enabled %d MSI-X vectors for RDMA.\n",
3630 pf->num_rdma_msix);
3631 }
3632 }
3633
3634 return v_actual;
3635
3636msix_err:
3637 devm_kfree(dev, pf->msix_entries);
3638 goto exit_err;
3639
3640no_hw_vecs_left_err:
3641 dev_err(dev, "not enough device MSI-X vectors. requested = %d, available = %d\n",
3642 needed, v_left);
3643 err = -ERANGE;
3644exit_err:
3645 pf->num_rdma_msix = 0;
3646 pf->num_lan_msix = 0;
3647 return err;
3648}
3649
3650
3651
3652
3653
3654static void ice_dis_msix(struct ice_pf *pf)
3655{
3656 pci_disable_msix(pf->pdev);
3657 devm_kfree(ice_pf_to_dev(pf), pf->msix_entries);
3658 pf->msix_entries = NULL;
3659}
3660
3661
3662
3663
3664
3665static void ice_clear_interrupt_scheme(struct ice_pf *pf)
3666{
3667 ice_dis_msix(pf);
3668
3669 if (pf->irq_tracker) {
3670 devm_kfree(ice_pf_to_dev(pf), pf->irq_tracker);
3671 pf->irq_tracker = NULL;
3672 }
3673}
3674
3675
3676
3677
3678
3679static int ice_init_interrupt_scheme(struct ice_pf *pf)
3680{
3681 int vectors;
3682
3683 vectors = ice_ena_msix_range(pf);
3684
3685 if (vectors < 0)
3686 return vectors;
3687
3688
3689 pf->irq_tracker = devm_kzalloc(ice_pf_to_dev(pf),
3690 struct_size(pf->irq_tracker, list, vectors),
3691 GFP_KERNEL);
3692 if (!pf->irq_tracker) {
3693 ice_dis_msix(pf);
3694 return -ENOMEM;
3695 }
3696
3697
3698 pf->num_avail_sw_msix = (u16)vectors;
3699 pf->irq_tracker->num_entries = (u16)vectors;
3700 pf->irq_tracker->end = pf->irq_tracker->num_entries;
3701
3702 return 0;
3703}
3704
3705
3706
3707
3708
3709
3710
3711
3712bool ice_is_wol_supported(struct ice_hw *hw)
3713{
3714 u16 wol_ctrl;
3715
3716
3717
3718
3719 if (ice_read_sr_word(hw, ICE_SR_NVM_WOL_CFG, &wol_ctrl))
3720 return false;
3721
3722 return !(BIT(hw->port_info->lport) & wol_ctrl);
3723}
3724
3725
3726
3727
3728
3729
3730
3731
3732
3733
3734
3735int ice_vsi_recfg_qs(struct ice_vsi *vsi, int new_rx, int new_tx)
3736{
3737 struct ice_pf *pf = vsi->back;
3738 int err = 0, timeout = 50;
3739
3740 if (!new_rx && !new_tx)
3741 return -EINVAL;
3742
3743 while (test_and_set_bit(ICE_CFG_BUSY, pf->state)) {
3744 timeout--;
3745 if (!timeout)
3746 return -EBUSY;
3747 usleep_range(1000, 2000);
3748 }
3749
3750 if (new_tx)
3751 vsi->req_txq = (u16)new_tx;
3752 if (new_rx)
3753 vsi->req_rxq = (u16)new_rx;
3754
3755
3756 if (!netif_running(vsi->netdev)) {
3757 ice_vsi_rebuild(vsi, false);
3758 dev_dbg(ice_pf_to_dev(pf), "Link is down, queue count change happens when link is brought up\n");
3759 goto done;
3760 }
3761
3762 ice_vsi_close(vsi);
3763 ice_vsi_rebuild(vsi, false);
3764 ice_pf_dcb_recfg(pf);
3765 ice_vsi_open(vsi);
3766done:
3767 clear_bit(ICE_CFG_BUSY, pf->state);
3768 return err;
3769}
3770
3771
3772
3773
3774
3775
3776
3777
3778static void ice_set_safe_mode_vlan_cfg(struct ice_pf *pf)
3779{
3780 struct ice_vsi *vsi = ice_get_main_vsi(pf);
3781 struct ice_vsi_ctx *ctxt;
3782 enum ice_status status;
3783 struct ice_hw *hw;
3784
3785 if (!vsi)
3786 return;
3787
3788 ctxt = kzalloc(sizeof(*ctxt), GFP_KERNEL);
3789 if (!ctxt)
3790 return;
3791
3792 hw = &pf->hw;
3793 ctxt->info = vsi->info;
3794
3795 ctxt->info.valid_sections =
3796 cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID |
3797 ICE_AQ_VSI_PROP_SECURITY_VALID |
3798 ICE_AQ_VSI_PROP_SW_VALID);
3799
3800
3801 ctxt->info.sec_flags &= ~(ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
3802 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S);
3803
3804
3805 ctxt->info.sw_flags2 &= ~ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3806
3807
3808 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL |
3809 ICE_AQ_VSI_VLAN_EMOD_NOTHING;
3810
3811 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
3812 if (status) {
3813 dev_err(ice_pf_to_dev(vsi->back), "Failed to update VSI for safe mode VLANs, err %s aq_err %s\n",
3814 ice_stat_str(status),
3815 ice_aq_str(hw->adminq.sq_last_status));
3816 } else {
3817 vsi->info.sec_flags = ctxt->info.sec_flags;
3818 vsi->info.sw_flags2 = ctxt->info.sw_flags2;
3819 vsi->info.vlan_flags = ctxt->info.vlan_flags;
3820 }
3821
3822 kfree(ctxt);
3823}
3824
3825
3826
3827
3828
3829
3830static void
3831ice_log_pkg_init(struct ice_hw *hw, enum ice_status *status)
3832{
3833 struct ice_pf *pf = (struct ice_pf *)hw->back;
3834 struct device *dev = ice_pf_to_dev(pf);
3835
3836 switch (*status) {
3837 case ICE_SUCCESS:
3838
3839
3840
3841
3842 if (hw->pkg_ver.major == hw->active_pkg_ver.major &&
3843 hw->pkg_ver.minor == hw->active_pkg_ver.minor &&
3844 hw->pkg_ver.update == hw->active_pkg_ver.update &&
3845 hw->pkg_ver.draft == hw->active_pkg_ver.draft &&
3846 !memcmp(hw->pkg_name, hw->active_pkg_name,
3847 sizeof(hw->pkg_name))) {
3848 if (hw->pkg_dwnld_status == ICE_AQ_RC_EEXIST)
3849 dev_info(dev, "DDP package already present on device: %s version %d.%d.%d.%d\n",
3850 hw->active_pkg_name,
3851 hw->active_pkg_ver.major,
3852 hw->active_pkg_ver.minor,
3853 hw->active_pkg_ver.update,
3854 hw->active_pkg_ver.draft);
3855 else
3856 dev_info(dev, "The DDP package was successfully loaded: %s version %d.%d.%d.%d\n",
3857 hw->active_pkg_name,
3858 hw->active_pkg_ver.major,
3859 hw->active_pkg_ver.minor,
3860 hw->active_pkg_ver.update,
3861 hw->active_pkg_ver.draft);
3862 } else if (hw->active_pkg_ver.major != ICE_PKG_SUPP_VER_MAJ ||
3863 hw->active_pkg_ver.minor != ICE_PKG_SUPP_VER_MNR) {
3864 dev_err(dev, "The device has a DDP package that is not supported by the driver. The device has package '%s' version %d.%d.x.x. The driver requires version %d.%d.x.x. Entering Safe Mode.\n",
3865 hw->active_pkg_name,
3866 hw->active_pkg_ver.major,
3867 hw->active_pkg_ver.minor,
3868 ICE_PKG_SUPP_VER_MAJ, ICE_PKG_SUPP_VER_MNR);
3869 *status = ICE_ERR_NOT_SUPPORTED;
3870 } else if (hw->active_pkg_ver.major == ICE_PKG_SUPP_VER_MAJ &&
3871 hw->active_pkg_ver.minor == ICE_PKG_SUPP_VER_MNR) {
3872 dev_info(dev, "The driver could not load the DDP package file because a compatible DDP package is already present on the device. The device has package '%s' version %d.%d.%d.%d. The package file found by the driver: '%s' version %d.%d.%d.%d.\n",
3873 hw->active_pkg_name,
3874 hw->active_pkg_ver.major,
3875 hw->active_pkg_ver.minor,
3876 hw->active_pkg_ver.update,
3877 hw->active_pkg_ver.draft,
3878 hw->pkg_name,
3879 hw->pkg_ver.major,
3880 hw->pkg_ver.minor,
3881 hw->pkg_ver.update,
3882 hw->pkg_ver.draft);
3883 } else {
3884 dev_err(dev, "An unknown error occurred when loading the DDP package, please reboot the system. If the problem persists, update the NVM. Entering Safe Mode.\n");
3885 *status = ICE_ERR_NOT_SUPPORTED;
3886 }
3887 break;
3888 case ICE_ERR_FW_DDP_MISMATCH:
3889 dev_err(dev, "The firmware loaded on the device is not compatible with the DDP package. Please update the device's NVM. Entering safe mode.\n");
3890 break;
3891 case ICE_ERR_BUF_TOO_SHORT:
3892 case ICE_ERR_CFG:
3893 dev_err(dev, "The DDP package file is invalid. Entering Safe Mode.\n");
3894 break;
3895 case ICE_ERR_NOT_SUPPORTED:
3896
3897 if (hw->pkg_ver.major > ICE_PKG_SUPP_VER_MAJ ||
3898 (hw->pkg_ver.major == ICE_PKG_SUPP_VER_MAJ &&
3899 hw->pkg_ver.minor > ICE_PKG_SUPP_VER_MNR))
3900 dev_err(dev, "The DDP package file version is higher than the driver supports. Please use an updated driver. Entering Safe Mode.\n");
3901 else if (hw->pkg_ver.major < ICE_PKG_SUPP_VER_MAJ ||
3902 (hw->pkg_ver.major == ICE_PKG_SUPP_VER_MAJ &&
3903 hw->pkg_ver.minor < ICE_PKG_SUPP_VER_MNR))
3904 dev_err(dev, "The DDP package file version is lower than the driver supports. The driver requires version %d.%d.x.x. Please use an updated DDP Package file. Entering Safe Mode.\n",
3905 ICE_PKG_SUPP_VER_MAJ, ICE_PKG_SUPP_VER_MNR);
3906 break;
3907 case ICE_ERR_AQ_ERROR:
3908 switch (hw->pkg_dwnld_status) {
3909 case ICE_AQ_RC_ENOSEC:
3910 case ICE_AQ_RC_EBADSIG:
3911 dev_err(dev, "The DDP package could not be loaded because its signature is not valid. Please use a valid DDP Package. Entering Safe Mode.\n");
3912 return;
3913 case ICE_AQ_RC_ESVN:
3914 dev_err(dev, "The DDP Package could not be loaded because its security revision is too low. Please use an updated DDP Package. Entering Safe Mode.\n");
3915 return;
3916 case ICE_AQ_RC_EBADMAN:
3917 case ICE_AQ_RC_EBADBUF:
3918 dev_err(dev, "An error occurred on the device while loading the DDP package. The device will be reset.\n");
3919
3920 if (ice_check_reset(hw))
3921 dev_err(dev, "Error resetting device. Please reload the driver\n");
3922 return;
3923 default:
3924 break;
3925 }
3926 fallthrough;
3927 default: