1
2
3
4#include "ice.h"
5#include "ice_base.h"
6#include "ice_flow.h"
7#include "ice_lib.h"
8#include "ice_fltr.h"
9#include "ice_dcb_lib.h"
10#include "ice_devlink.h"
11
12
13
14
15
16const char *ice_vsi_type_str(enum ice_vsi_type vsi_type)
17{
18 switch (vsi_type) {
19 case ICE_VSI_PF:
20 return "ICE_VSI_PF";
21 case ICE_VSI_VF:
22 return "ICE_VSI_VF";
23 case ICE_VSI_CTRL:
24 return "ICE_VSI_CTRL";
25 case ICE_VSI_LB:
26 return "ICE_VSI_LB";
27 default:
28 return "unknown";
29 }
30}
31
32
33
34
35
36
37
38
39
40
41
42static int ice_vsi_ctrl_all_rx_rings(struct ice_vsi *vsi, bool ena)
43{
44 int ret = 0;
45 u16 i;
46
47 for (i = 0; i < vsi->num_rxq; i++)
48 ice_vsi_ctrl_one_rx_ring(vsi, ena, i, false);
49
50 ice_flush(&vsi->back->hw);
51
52 for (i = 0; i < vsi->num_rxq; i++) {
53 ret = ice_vsi_wait_one_rx_ring(vsi, ena, i);
54 if (ret)
55 break;
56 }
57
58 return ret;
59}
60
61
62
63
64
65
66
67
68static int ice_vsi_alloc_arrays(struct ice_vsi *vsi)
69{
70 struct ice_pf *pf = vsi->back;
71 struct device *dev;
72
73 dev = ice_pf_to_dev(pf);
74
75
76 vsi->tx_rings = devm_kcalloc(dev, vsi->alloc_txq,
77 sizeof(*vsi->tx_rings), GFP_KERNEL);
78 if (!vsi->tx_rings)
79 return -ENOMEM;
80
81 vsi->rx_rings = devm_kcalloc(dev, vsi->alloc_rxq,
82 sizeof(*vsi->rx_rings), GFP_KERNEL);
83 if (!vsi->rx_rings)
84 goto err_rings;
85
86
87 vsi->txq_map = devm_kcalloc(dev, (2 * vsi->alloc_txq),
88 sizeof(*vsi->txq_map), GFP_KERNEL);
89
90 if (!vsi->txq_map)
91 goto err_txq_map;
92
93 vsi->rxq_map = devm_kcalloc(dev, vsi->alloc_rxq,
94 sizeof(*vsi->rxq_map), GFP_KERNEL);
95 if (!vsi->rxq_map)
96 goto err_rxq_map;
97
98
99 if (vsi->type == ICE_VSI_LB)
100 return 0;
101
102
103 vsi->q_vectors = devm_kcalloc(dev, vsi->num_q_vectors,
104 sizeof(*vsi->q_vectors), GFP_KERNEL);
105 if (!vsi->q_vectors)
106 goto err_vectors;
107
108 vsi->af_xdp_zc_qps = bitmap_zalloc(max_t(int, vsi->alloc_txq, vsi->alloc_rxq), GFP_KERNEL);
109 if (!vsi->af_xdp_zc_qps)
110 goto err_zc_qps;
111
112 return 0;
113
114err_zc_qps:
115 devm_kfree(dev, vsi->q_vectors);
116err_vectors:
117 devm_kfree(dev, vsi->rxq_map);
118err_rxq_map:
119 devm_kfree(dev, vsi->txq_map);
120err_txq_map:
121 devm_kfree(dev, vsi->rx_rings);
122err_rings:
123 devm_kfree(dev, vsi->tx_rings);
124 return -ENOMEM;
125}
126
127
128
129
130
131static void ice_vsi_set_num_desc(struct ice_vsi *vsi)
132{
133 switch (vsi->type) {
134 case ICE_VSI_PF:
135 case ICE_VSI_CTRL:
136 case ICE_VSI_LB:
137
138
139
140
141 if (!vsi->num_rx_desc)
142 vsi->num_rx_desc = ICE_DFLT_NUM_RX_DESC;
143 if (!vsi->num_tx_desc)
144 vsi->num_tx_desc = ICE_DFLT_NUM_TX_DESC;
145 break;
146 default:
147 dev_dbg(ice_pf_to_dev(vsi->back), "Not setting number of Tx/Rx descriptors for VSI type %d\n",
148 vsi->type);
149 break;
150 }
151}
152
153
154
155
156
157
158
159
160static void ice_vsi_set_num_qs(struct ice_vsi *vsi, u16 vf_id)
161{
162 struct ice_pf *pf = vsi->back;
163 struct ice_vf *vf = NULL;
164
165 if (vsi->type == ICE_VSI_VF)
166 vsi->vf_id = vf_id;
167 else
168 vsi->vf_id = ICE_INVAL_VFID;
169
170 switch (vsi->type) {
171 case ICE_VSI_PF:
172 if (vsi->req_txq) {
173 vsi->alloc_txq = vsi->req_txq;
174 vsi->num_txq = vsi->req_txq;
175 } else {
176 vsi->alloc_txq = min3(pf->num_lan_msix,
177 ice_get_avail_txq_count(pf),
178 (u16)num_online_cpus());
179 }
180
181 pf->num_lan_tx = vsi->alloc_txq;
182
183
184 if (!test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
185 vsi->alloc_rxq = 1;
186 } else {
187 if (vsi->req_rxq) {
188 vsi->alloc_rxq = vsi->req_rxq;
189 vsi->num_rxq = vsi->req_rxq;
190 } else {
191 vsi->alloc_rxq = min3(pf->num_lan_msix,
192 ice_get_avail_rxq_count(pf),
193 (u16)num_online_cpus());
194 }
195 }
196
197 pf->num_lan_rx = vsi->alloc_rxq;
198
199 vsi->num_q_vectors = min_t(int, pf->num_lan_msix,
200 max_t(int, vsi->alloc_rxq,
201 vsi->alloc_txq));
202 break;
203 case ICE_VSI_VF:
204 vf = &pf->vf[vsi->vf_id];
205 if (vf->num_req_qs)
206 vf->num_vf_qs = vf->num_req_qs;
207 vsi->alloc_txq = vf->num_vf_qs;
208 vsi->alloc_rxq = vf->num_vf_qs;
209
210
211
212
213
214 vsi->num_q_vectors = pf->num_msix_per_vf - ICE_NONQ_VECS_VF;
215 break;
216 case ICE_VSI_CTRL:
217 vsi->alloc_txq = 1;
218 vsi->alloc_rxq = 1;
219 vsi->num_q_vectors = 1;
220 break;
221 case ICE_VSI_LB:
222 vsi->alloc_txq = 1;
223 vsi->alloc_rxq = 1;
224 break;
225 default:
226 dev_warn(ice_pf_to_dev(pf), "Unknown VSI type %d\n", vsi->type);
227 break;
228 }
229
230 ice_vsi_set_num_desc(vsi);
231}
232
233
234
235
236
237
238
239
240
241
242static int ice_get_free_slot(void *array, int size, int curr)
243{
244 int **tmp_array = (int **)array;
245 int next;
246
247 if (curr < (size - 1) && !tmp_array[curr + 1]) {
248 next = curr + 1;
249 } else {
250 int i = 0;
251
252 while ((i < size) && (tmp_array[i]))
253 i++;
254 if (i == size)
255 next = ICE_NO_VSI;
256 else
257 next = i;
258 }
259 return next;
260}
261
262
263
264
265
266static void ice_vsi_delete(struct ice_vsi *vsi)
267{
268 struct ice_pf *pf = vsi->back;
269 struct ice_vsi_ctx *ctxt;
270 enum ice_status status;
271
272 ctxt = kzalloc(sizeof(*ctxt), GFP_KERNEL);
273 if (!ctxt)
274 return;
275
276 if (vsi->type == ICE_VSI_VF)
277 ctxt->vf_num = vsi->vf_id;
278 ctxt->vsi_num = vsi->vsi_num;
279
280 memcpy(&ctxt->info, &vsi->info, sizeof(ctxt->info));
281
282 status = ice_free_vsi(&pf->hw, vsi->idx, ctxt, false, NULL);
283 if (status)
284 dev_err(ice_pf_to_dev(pf), "Failed to delete VSI %i in FW - error: %s\n",
285 vsi->vsi_num, ice_stat_str(status));
286
287 kfree(ctxt);
288}
289
290
291
292
293
294static void ice_vsi_free_arrays(struct ice_vsi *vsi)
295{
296 struct ice_pf *pf = vsi->back;
297 struct device *dev;
298
299 dev = ice_pf_to_dev(pf);
300
301 if (vsi->af_xdp_zc_qps) {
302 bitmap_free(vsi->af_xdp_zc_qps);
303 vsi->af_xdp_zc_qps = NULL;
304 }
305
306 if (vsi->q_vectors) {
307 devm_kfree(dev, vsi->q_vectors);
308 vsi->q_vectors = NULL;
309 }
310 if (vsi->tx_rings) {
311 devm_kfree(dev, vsi->tx_rings);
312 vsi->tx_rings = NULL;
313 }
314 if (vsi->rx_rings) {
315 devm_kfree(dev, vsi->rx_rings);
316 vsi->rx_rings = NULL;
317 }
318 if (vsi->txq_map) {
319 devm_kfree(dev, vsi->txq_map);
320 vsi->txq_map = NULL;
321 }
322 if (vsi->rxq_map) {
323 devm_kfree(dev, vsi->rxq_map);
324 vsi->rxq_map = NULL;
325 }
326}
327
328
329
330
331
332
333
334
335
336
337static int ice_vsi_clear(struct ice_vsi *vsi)
338{
339 struct ice_pf *pf = NULL;
340 struct device *dev;
341
342 if (!vsi)
343 return 0;
344
345 if (!vsi->back)
346 return -EINVAL;
347
348 pf = vsi->back;
349 dev = ice_pf_to_dev(pf);
350
351 if (!pf->vsi[vsi->idx] || pf->vsi[vsi->idx] != vsi) {
352 dev_dbg(dev, "vsi does not exist at pf->vsi[%d]\n", vsi->idx);
353 return -EINVAL;
354 }
355
356 mutex_lock(&pf->sw_mutex);
357
358
359 pf->vsi[vsi->idx] = NULL;
360 if (vsi->idx < pf->next_vsi && vsi->type != ICE_VSI_CTRL)
361 pf->next_vsi = vsi->idx;
362 if (vsi->idx < pf->next_vsi && vsi->type == ICE_VSI_CTRL &&
363 vsi->vf_id != ICE_INVAL_VFID)
364 pf->next_vsi = vsi->idx;
365
366 ice_vsi_free_arrays(vsi);
367 mutex_unlock(&pf->sw_mutex);
368 devm_kfree(dev, vsi);
369
370 return 0;
371}
372
373
374
375
376
377
378static irqreturn_t ice_msix_clean_ctrl_vsi(int __always_unused irq, void *data)
379{
380 struct ice_q_vector *q_vector = (struct ice_q_vector *)data;
381
382 if (!q_vector->tx.ring)
383 return IRQ_HANDLED;
384
385#define FDIR_RX_DESC_CLEAN_BUDGET 64
386 ice_clean_rx_irq(q_vector->rx.ring, FDIR_RX_DESC_CLEAN_BUDGET);
387 ice_clean_ctrl_tx_irq(q_vector->tx.ring);
388
389 return IRQ_HANDLED;
390}
391
392
393
394
395
396
397static irqreturn_t ice_msix_clean_rings(int __always_unused irq, void *data)
398{
399 struct ice_q_vector *q_vector = (struct ice_q_vector *)data;
400
401 if (!q_vector->tx.ring && !q_vector->rx.ring)
402 return IRQ_HANDLED;
403
404 q_vector->total_events++;
405
406 napi_schedule(&q_vector->napi);
407
408 return IRQ_HANDLED;
409}
410
411
412
413
414
415
416
417
418
419static struct ice_vsi *
420ice_vsi_alloc(struct ice_pf *pf, enum ice_vsi_type vsi_type, u16 vf_id)
421{
422 struct device *dev = ice_pf_to_dev(pf);
423 struct ice_vsi *vsi = NULL;
424
425
426 mutex_lock(&pf->sw_mutex);
427
428
429
430
431
432 if (pf->next_vsi == ICE_NO_VSI) {
433 dev_dbg(dev, "out of VSI slots!\n");
434 goto unlock_pf;
435 }
436
437 vsi = devm_kzalloc(dev, sizeof(*vsi), GFP_KERNEL);
438 if (!vsi)
439 goto unlock_pf;
440
441 vsi->type = vsi_type;
442 vsi->back = pf;
443 set_bit(ICE_VSI_DOWN, vsi->state);
444
445 if (vsi_type == ICE_VSI_VF)
446 ice_vsi_set_num_qs(vsi, vf_id);
447 else
448 ice_vsi_set_num_qs(vsi, ICE_INVAL_VFID);
449
450 switch (vsi->type) {
451 case ICE_VSI_PF:
452 if (ice_vsi_alloc_arrays(vsi))
453 goto err_rings;
454
455
456 vsi->irq_handler = ice_msix_clean_rings;
457 break;
458 case ICE_VSI_CTRL:
459 if (ice_vsi_alloc_arrays(vsi))
460 goto err_rings;
461
462
463 vsi->irq_handler = ice_msix_clean_ctrl_vsi;
464 break;
465 case ICE_VSI_VF:
466 if (ice_vsi_alloc_arrays(vsi))
467 goto err_rings;
468 break;
469 case ICE_VSI_LB:
470 if (ice_vsi_alloc_arrays(vsi))
471 goto err_rings;
472 break;
473 default:
474 dev_warn(dev, "Unknown VSI type %d\n", vsi->type);
475 goto unlock_pf;
476 }
477
478 if (vsi->type == ICE_VSI_CTRL && vf_id == ICE_INVAL_VFID) {
479
480 vsi->idx = pf->num_alloc_vsi - 1;
481 pf->ctrl_vsi_idx = vsi->idx;
482 pf->vsi[vsi->idx] = vsi;
483 } else {
484
485 vsi->idx = pf->next_vsi;
486 pf->vsi[pf->next_vsi] = vsi;
487
488
489 pf->next_vsi = ice_get_free_slot(pf->vsi, pf->num_alloc_vsi,
490 pf->next_vsi);
491 }
492
493 if (vsi->type == ICE_VSI_CTRL && vf_id != ICE_INVAL_VFID)
494 pf->vf[vf_id].ctrl_vsi_idx = vsi->idx;
495 goto unlock_pf;
496
497err_rings:
498 devm_kfree(dev, vsi);
499 vsi = NULL;
500unlock_pf:
501 mutex_unlock(&pf->sw_mutex);
502 return vsi;
503}
504
505
506
507
508
509
510
511
512
513static int ice_alloc_fd_res(struct ice_vsi *vsi)
514{
515 struct ice_pf *pf = vsi->back;
516 u32 g_val, b_val;
517
518
519
520
521
522
523
524 g_val = pf->hw.func_caps.fd_fltr_guar;
525 if (!g_val)
526 return -EPERM;
527
528
529 b_val = pf->hw.func_caps.fd_fltr_best_effort;
530 if (!b_val)
531 return -EPERM;
532
533 if (!(vsi->type == ICE_VSI_PF || vsi->type == ICE_VSI_VF))
534 return -EPERM;
535
536 if (!test_bit(ICE_FLAG_FD_ENA, pf->flags))
537 return -EPERM;
538
539 vsi->num_gfltr = g_val / pf->num_alloc_vsi;
540
541
542 vsi->num_bfltr = b_val;
543
544 if (vsi->type == ICE_VSI_VF) {
545 vsi->num_gfltr = 0;
546
547
548 vsi->num_bfltr = b_val;
549 }
550
551 return 0;
552}
553
554
555
556
557
558
559
560static int ice_vsi_get_qs(struct ice_vsi *vsi)
561{
562 struct ice_pf *pf = vsi->back;
563 struct ice_qs_cfg tx_qs_cfg = {
564 .qs_mutex = &pf->avail_q_mutex,
565 .pf_map = pf->avail_txqs,
566 .pf_map_size = pf->max_pf_txqs,
567 .q_count = vsi->alloc_txq,
568 .scatter_count = ICE_MAX_SCATTER_TXQS,
569 .vsi_map = vsi->txq_map,
570 .vsi_map_offset = 0,
571 .mapping_mode = ICE_VSI_MAP_CONTIG
572 };
573 struct ice_qs_cfg rx_qs_cfg = {
574 .qs_mutex = &pf->avail_q_mutex,
575 .pf_map = pf->avail_rxqs,
576 .pf_map_size = pf->max_pf_rxqs,
577 .q_count = vsi->alloc_rxq,
578 .scatter_count = ICE_MAX_SCATTER_RXQS,
579 .vsi_map = vsi->rxq_map,
580 .vsi_map_offset = 0,
581 .mapping_mode = ICE_VSI_MAP_CONTIG
582 };
583 int ret;
584
585 ret = __ice_vsi_get_qs(&tx_qs_cfg);
586 if (ret)
587 return ret;
588 vsi->tx_mapping_mode = tx_qs_cfg.mapping_mode;
589
590 ret = __ice_vsi_get_qs(&rx_qs_cfg);
591 if (ret)
592 return ret;
593 vsi->rx_mapping_mode = rx_qs_cfg.mapping_mode;
594
595 return 0;
596}
597
598
599
600
601
602static void ice_vsi_put_qs(struct ice_vsi *vsi)
603{
604 struct ice_pf *pf = vsi->back;
605 int i;
606
607 mutex_lock(&pf->avail_q_mutex);
608
609 for (i = 0; i < vsi->alloc_txq; i++) {
610 clear_bit(vsi->txq_map[i], pf->avail_txqs);
611 vsi->txq_map[i] = ICE_INVAL_Q_INDEX;
612 }
613
614 for (i = 0; i < vsi->alloc_rxq; i++) {
615 clear_bit(vsi->rxq_map[i], pf->avail_rxqs);
616 vsi->rxq_map[i] = ICE_INVAL_Q_INDEX;
617 }
618
619 mutex_unlock(&pf->avail_q_mutex);
620}
621
622
623
624
625
626
627
628bool ice_is_safe_mode(struct ice_pf *pf)
629{
630 return !test_bit(ICE_FLAG_ADV_FEATURES, pf->flags);
631}
632
633
634
635
636
637
638
639bool ice_is_aux_ena(struct ice_pf *pf)
640{
641 return test_bit(ICE_FLAG_AUX_ENA, pf->flags);
642}
643
644
645
646
647
648
649
650
651static void ice_vsi_clean_rss_flow_fld(struct ice_vsi *vsi)
652{
653 struct ice_pf *pf = vsi->back;
654 enum ice_status status;
655
656 if (ice_is_safe_mode(pf))
657 return;
658
659 status = ice_rem_vsi_rss_cfg(&pf->hw, vsi->idx);
660 if (status)
661 dev_dbg(ice_pf_to_dev(pf), "ice_rem_vsi_rss_cfg failed for vsi = %d, error = %s\n",
662 vsi->vsi_num, ice_stat_str(status));
663}
664
665
666
667
668
669static void ice_rss_clean(struct ice_vsi *vsi)
670{
671 struct ice_pf *pf = vsi->back;
672 struct device *dev;
673
674 dev = ice_pf_to_dev(pf);
675
676 if (vsi->rss_hkey_user)
677 devm_kfree(dev, vsi->rss_hkey_user);
678 if (vsi->rss_lut_user)
679 devm_kfree(dev, vsi->rss_lut_user);
680
681 ice_vsi_clean_rss_flow_fld(vsi);
682
683 if (!ice_is_safe_mode(pf))
684 ice_rem_vsi_rss_list(&pf->hw, vsi->idx);
685}
686
687
688
689
690
691static void ice_vsi_set_rss_params(struct ice_vsi *vsi)
692{
693 struct ice_hw_common_caps *cap;
694 struct ice_pf *pf = vsi->back;
695
696 if (!test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
697 vsi->rss_size = 1;
698 return;
699 }
700
701 cap = &pf->hw.func_caps.common_cap;
702 switch (vsi->type) {
703 case ICE_VSI_PF:
704
705 vsi->rss_table_size = (u16)cap->rss_table_size;
706 vsi->rss_size = min_t(u16, num_online_cpus(),
707 BIT(cap->rss_table_entry_width));
708 vsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
709 break;
710 case ICE_VSI_VF:
711
712
713
714 vsi->rss_table_size = ICE_VSIQF_HLUT_ARRAY_SIZE;
715 vsi->rss_size = ICE_MAX_RSS_QS_PER_VF;
716 vsi->rss_lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_VSI;
717 break;
718 case ICE_VSI_LB:
719 break;
720 default:
721 dev_dbg(ice_pf_to_dev(pf), "Unsupported VSI type %s\n",
722 ice_vsi_type_str(vsi->type));
723 break;
724 }
725}
726
727
728
729
730
731
732
733static void ice_set_dflt_vsi_ctx(struct ice_vsi_ctx *ctxt)
734{
735 u32 table = 0;
736
737 memset(&ctxt->info, 0, sizeof(ctxt->info));
738
739 ctxt->alloc_from_pool = true;
740
741 ctxt->info.sw_flags = ICE_AQ_VSI_SW_FLAG_SRC_PRUNE;
742
743 ctxt->info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
744
745
746
747
748 ctxt->info.vlan_flags = ((ICE_AQ_VSI_VLAN_MODE_ALL &
749 ICE_AQ_VSI_VLAN_MODE_M) >>
750 ICE_AQ_VSI_VLAN_MODE_S);
751
752 table |= ICE_UP_TABLE_TRANSLATE(0, 0);
753 table |= ICE_UP_TABLE_TRANSLATE(1, 1);
754 table |= ICE_UP_TABLE_TRANSLATE(2, 2);
755 table |= ICE_UP_TABLE_TRANSLATE(3, 3);
756 table |= ICE_UP_TABLE_TRANSLATE(4, 4);
757 table |= ICE_UP_TABLE_TRANSLATE(5, 5);
758 table |= ICE_UP_TABLE_TRANSLATE(6, 6);
759 table |= ICE_UP_TABLE_TRANSLATE(7, 7);
760 ctxt->info.ingress_table = cpu_to_le32(table);
761 ctxt->info.egress_table = cpu_to_le32(table);
762
763 ctxt->info.outer_up_table = cpu_to_le32(table);
764
765}
766
767
768
769
770
771
772static void ice_vsi_setup_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctxt)
773{
774 u16 offset = 0, qmap = 0, tx_count = 0, pow = 0;
775 u16 num_txq_per_tc, num_rxq_per_tc;
776 u16 qcount_tx = vsi->alloc_txq;
777 u16 qcount_rx = vsi->alloc_rxq;
778 bool ena_tc0 = false;
779 u8 netdev_tc = 0;
780 int i;
781
782
783 if (vsi->tc_cfg.numtc) {
784 if (!(vsi->tc_cfg.ena_tc & BIT(0)))
785 ena_tc0 = true;
786 } else {
787 ena_tc0 = true;
788 }
789
790 if (ena_tc0) {
791 vsi->tc_cfg.numtc++;
792 vsi->tc_cfg.ena_tc |= 1;
793 }
794
795 num_rxq_per_tc = min_t(u16, qcount_rx / vsi->tc_cfg.numtc, ICE_MAX_RXQS_PER_TC);
796 if (!num_rxq_per_tc)
797 num_rxq_per_tc = 1;
798 num_txq_per_tc = qcount_tx / vsi->tc_cfg.numtc;
799 if (!num_txq_per_tc)
800 num_txq_per_tc = 1;
801
802
803 pow = (u16)order_base_2(num_rxq_per_tc);
804
805
806
807
808
809
810
811
812
813
814
815
816 ice_for_each_traffic_class(i) {
817 if (!(vsi->tc_cfg.ena_tc & BIT(i))) {
818
819 vsi->tc_cfg.tc_info[i].qoffset = 0;
820 vsi->tc_cfg.tc_info[i].qcount_rx = 1;
821 vsi->tc_cfg.tc_info[i].qcount_tx = 1;
822 vsi->tc_cfg.tc_info[i].netdev_tc = 0;
823 ctxt->info.tc_mapping[i] = 0;
824 continue;
825 }
826
827
828 vsi->tc_cfg.tc_info[i].qoffset = offset;
829 vsi->tc_cfg.tc_info[i].qcount_rx = num_rxq_per_tc;
830 vsi->tc_cfg.tc_info[i].qcount_tx = num_txq_per_tc;
831 vsi->tc_cfg.tc_info[i].netdev_tc = netdev_tc++;
832
833 qmap = ((offset << ICE_AQ_VSI_TC_Q_OFFSET_S) &
834 ICE_AQ_VSI_TC_Q_OFFSET_M) |
835 ((pow << ICE_AQ_VSI_TC_Q_NUM_S) &
836 ICE_AQ_VSI_TC_Q_NUM_M);
837 offset += num_rxq_per_tc;
838 tx_count += num_txq_per_tc;
839 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
840 }
841
842
843
844
845
846
847
848 if (offset)
849 vsi->num_rxq = offset;
850 else
851 vsi->num_rxq = num_rxq_per_tc;
852
853 vsi->num_txq = tx_count;
854
855 if (vsi->type == ICE_VSI_VF && vsi->num_txq != vsi->num_rxq) {
856 dev_dbg(ice_pf_to_dev(vsi->back), "VF VSI should have same number of Tx and Rx queues. Hence making them equal\n");
857
858
859
860 vsi->num_txq = vsi->num_rxq;
861 }
862
863
864 ctxt->info.mapping_flags |= cpu_to_le16(ICE_AQ_VSI_Q_MAP_CONTIG);
865
866
867
868
869 ctxt->info.q_mapping[0] = cpu_to_le16(vsi->rxq_map[0]);
870 ctxt->info.q_mapping[1] = cpu_to_le16(vsi->num_rxq);
871}
872
873
874
875
876
877
878static void ice_set_fd_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)
879{
880 u8 dflt_q_group, dflt_q_prio;
881 u16 dflt_q, report_q, val;
882
883 if (vsi->type != ICE_VSI_PF && vsi->type != ICE_VSI_CTRL &&
884 vsi->type != ICE_VSI_VF)
885 return;
886
887 val = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
888 ctxt->info.valid_sections |= cpu_to_le16(val);
889 dflt_q = 0;
890 dflt_q_group = 0;
891 report_q = 0;
892 dflt_q_prio = 0;
893
894
895 val = ICE_AQ_VSI_FD_ENABLE | ICE_AQ_VSI_FD_PROG_ENABLE;
896 ctxt->info.fd_options = cpu_to_le16(val);
897
898 ctxt->info.max_fd_fltr_dedicated =
899 cpu_to_le16(vsi->num_gfltr);
900
901 ctxt->info.max_fd_fltr_shared =
902 cpu_to_le16(vsi->num_bfltr);
903
904 val = ((dflt_q << ICE_AQ_VSI_FD_DEF_Q_S) &
905 ICE_AQ_VSI_FD_DEF_Q_M);
906
907 val |= ((dflt_q_group << ICE_AQ_VSI_FD_DEF_GRP_S) &
908 ICE_AQ_VSI_FD_DEF_GRP_M);
909 ctxt->info.fd_def_q = cpu_to_le16(val);
910
911 val = ((report_q << ICE_AQ_VSI_FD_REPORT_Q_S) &
912 ICE_AQ_VSI_FD_REPORT_Q_M);
913
914 val |= ((dflt_q_prio << ICE_AQ_VSI_FD_DEF_PRIORITY_S) &
915 ICE_AQ_VSI_FD_DEF_PRIORITY_M);
916 ctxt->info.fd_report_opt = cpu_to_le16(val);
917}
918
919
920
921
922
923
924static void ice_set_rss_vsi_ctx(struct ice_vsi_ctx *ctxt, struct ice_vsi *vsi)
925{
926 u8 lut_type, hash_type;
927 struct device *dev;
928 struct ice_pf *pf;
929
930 pf = vsi->back;
931 dev = ice_pf_to_dev(pf);
932
933 switch (vsi->type) {
934 case ICE_VSI_PF:
935
936 lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF;
937 hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
938 break;
939 case ICE_VSI_VF:
940
941 lut_type = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI;
942 hash_type = ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
943 break;
944 default:
945 dev_dbg(dev, "Unsupported VSI type %s\n",
946 ice_vsi_type_str(vsi->type));
947 return;
948 }
949
950 ctxt->info.q_opt_rss = ((lut_type << ICE_AQ_VSI_Q_OPT_RSS_LUT_S) &
951 ICE_AQ_VSI_Q_OPT_RSS_LUT_M) |
952 ((hash_type << ICE_AQ_VSI_Q_OPT_RSS_HASH_S) &
953 ICE_AQ_VSI_Q_OPT_RSS_HASH_M);
954}
955
956
957
958
959
960
961
962
963
964static int ice_vsi_init(struct ice_vsi *vsi, bool init_vsi)
965{
966 struct ice_pf *pf = vsi->back;
967 struct ice_hw *hw = &pf->hw;
968 struct ice_vsi_ctx *ctxt;
969 struct device *dev;
970 int ret = 0;
971
972 dev = ice_pf_to_dev(pf);
973 ctxt = kzalloc(sizeof(*ctxt), GFP_KERNEL);
974 if (!ctxt)
975 return -ENOMEM;
976
977 switch (vsi->type) {
978 case ICE_VSI_CTRL:
979 case ICE_VSI_LB:
980 case ICE_VSI_PF:
981 ctxt->flags = ICE_AQ_VSI_TYPE_PF;
982 break;
983 case ICE_VSI_VF:
984 ctxt->flags = ICE_AQ_VSI_TYPE_VF;
985
986 ctxt->vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
987 break;
988 default:
989 ret = -ENODEV;
990 goto out;
991 }
992
993 ice_set_dflt_vsi_ctx(ctxt);
994 if (test_bit(ICE_FLAG_FD_ENA, pf->flags))
995 ice_set_fd_vsi_ctx(ctxt, vsi);
996
997 if (vsi->vsw->bridge_mode == BRIDGE_MODE_VEB)
998 ctxt->info.sw_flags |= ICE_AQ_VSI_SW_FLAG_ALLOW_LB;
999
1000
1001 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags) &&
1002 vsi->type != ICE_VSI_CTRL) {
1003 ice_set_rss_vsi_ctx(ctxt, vsi);
1004
1005
1006
1007 if (!init_vsi)
1008 ctxt->info.valid_sections |=
1009 cpu_to_le16(ICE_AQ_VSI_PROP_Q_OPT_VALID);
1010 }
1011
1012 ctxt->info.sw_id = vsi->port_info->sw_id;
1013 ice_vsi_setup_q_map(vsi, ctxt);
1014 if (!init_vsi)
1015
1016
1017
1018 ctxt->info.valid_sections |=
1019 cpu_to_le16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
1020
1021
1022
1023
1024 if (vsi->type == ICE_VSI_VF) {
1025 ctxt->info.valid_sections |=
1026 cpu_to_le16(ICE_AQ_VSI_PROP_SECURITY_VALID);
1027 if (pf->vf[vsi->vf_id].spoofchk) {
1028 ctxt->info.sec_flags |=
1029 ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF |
1030 (ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
1031 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S);
1032 } else {
1033 ctxt->info.sec_flags &=
1034 ~(ICE_AQ_VSI_SEC_FLAG_ENA_MAC_ANTI_SPOOF |
1035 (ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
1036 ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S));
1037 }
1038 }
1039
1040
1041 if (vsi->type == ICE_VSI_PF) {
1042 ctxt->info.sec_flags |= ICE_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD;
1043 ctxt->info.valid_sections |=
1044 cpu_to_le16(ICE_AQ_VSI_PROP_SECURITY_VALID);
1045 }
1046
1047 if (init_vsi) {
1048 ret = ice_add_vsi(hw, vsi->idx, ctxt, NULL);
1049 if (ret) {
1050 dev_err(dev, "Add VSI failed, err %d\n", ret);
1051 ret = -EIO;
1052 goto out;
1053 }
1054 } else {
1055 ret = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
1056 if (ret) {
1057 dev_err(dev, "Update VSI failed, err %d\n", ret);
1058 ret = -EIO;
1059 goto out;
1060 }
1061 }
1062
1063
1064 vsi->info = ctxt->info;
1065
1066
1067 vsi->vsi_num = ctxt->vsi_num;
1068
1069out:
1070 kfree(ctxt);
1071 return ret;
1072}
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082int ice_free_res(struct ice_res_tracker *res, u16 index, u16 id)
1083{
1084 int count = 0;
1085 int i;
1086
1087 if (!res || index >= res->end)
1088 return -EINVAL;
1089
1090 id |= ICE_RES_VALID_BIT;
1091 for (i = index; i < res->end && res->list[i] == id; i++) {
1092 res->list[i] = 0;
1093 count++;
1094 }
1095
1096 return count;
1097}
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107static int ice_search_res(struct ice_res_tracker *res, u16 needed, u16 id)
1108{
1109 u16 start = 0, end = 0;
1110
1111 if (needed > res->end)
1112 return -ENOMEM;
1113
1114 id |= ICE_RES_VALID_BIT;
1115
1116 do {
1117
1118 if (res->list[end++] & ICE_RES_VALID_BIT) {
1119 start = end;
1120 if ((start + needed) > res->end)
1121 break;
1122 }
1123
1124 if (end == (start + needed)) {
1125 int i = start;
1126
1127
1128 while (i != end)
1129 res->list[i++] = id;
1130
1131 return start;
1132 }
1133 } while (end < res->end);
1134
1135 return -ENOMEM;
1136}
1137
1138
1139
1140
1141
1142static u16 ice_get_free_res_count(struct ice_res_tracker *res)
1143{
1144 u16 i, count = 0;
1145
1146 for (i = 0; i < res->end; i++)
1147 if (!(res->list[i] & ICE_RES_VALID_BIT))
1148 count++;
1149
1150 return count;
1151}
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162int
1163ice_get_res(struct ice_pf *pf, struct ice_res_tracker *res, u16 needed, u16 id)
1164{
1165 if (!res || !pf)
1166 return -EINVAL;
1167
1168 if (!needed || needed > res->num_entries || id >= ICE_RES_VALID_BIT) {
1169 dev_err(ice_pf_to_dev(pf), "param err: needed=%d, num_entries = %d id=0x%04x\n",
1170 needed, res->num_entries, id);
1171 return -EINVAL;
1172 }
1173
1174 return ice_search_res(res, needed, id);
1175}
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187static int ice_vsi_setup_vector_base(struct ice_vsi *vsi)
1188{
1189 struct ice_pf *pf = vsi->back;
1190 struct device *dev;
1191 u16 num_q_vectors;
1192 int base;
1193
1194 dev = ice_pf_to_dev(pf);
1195
1196 if (vsi->type == ICE_VSI_VF)
1197 return 0;
1198
1199 if (vsi->base_vector) {
1200 dev_dbg(dev, "VSI %d has non-zero base vector %d\n",
1201 vsi->vsi_num, vsi->base_vector);
1202 return -EEXIST;
1203 }
1204
1205 num_q_vectors = vsi->num_q_vectors;
1206
1207 if (vsi->type == ICE_VSI_CTRL && vsi->vf_id != ICE_INVAL_VFID) {
1208 int i;
1209
1210 ice_for_each_vf(pf, i) {
1211 struct ice_vf *vf = &pf->vf[i];
1212
1213 if (i != vsi->vf_id && vf->ctrl_vsi_idx != ICE_NO_VSI) {
1214 base = pf->vsi[vf->ctrl_vsi_idx]->base_vector;
1215 break;
1216 }
1217 }
1218 if (i == pf->num_alloc_vfs)
1219 base = ice_get_res(pf, pf->irq_tracker, num_q_vectors,
1220 ICE_RES_VF_CTRL_VEC_ID);
1221 } else {
1222 base = ice_get_res(pf, pf->irq_tracker, num_q_vectors,
1223 vsi->idx);
1224 }
1225
1226 if (base < 0) {
1227 dev_err(dev, "%d MSI-X interrupts available. %s %d failed to get %d MSI-X vectors\n",
1228 ice_get_free_res_count(pf->irq_tracker),
1229 ice_vsi_type_str(vsi->type), vsi->idx, num_q_vectors);
1230 return -ENOENT;
1231 }
1232 vsi->base_vector = (u16)base;
1233 pf->num_avail_sw_msix -= num_q_vectors;
1234
1235 return 0;
1236}
1237
1238
1239
1240
1241
1242static void ice_vsi_clear_rings(struct ice_vsi *vsi)
1243{
1244 int i;
1245
1246
1247 if (vsi->q_vectors) {
1248 ice_for_each_q_vector(vsi, i) {
1249 struct ice_q_vector *q_vector = vsi->q_vectors[i];
1250
1251 if (q_vector) {
1252 q_vector->tx.ring = NULL;
1253 q_vector->rx.ring = NULL;
1254 }
1255 }
1256 }
1257
1258 if (vsi->tx_rings) {
1259 for (i = 0; i < vsi->alloc_txq; i++) {
1260 if (vsi->tx_rings[i]) {
1261 kfree_rcu(vsi->tx_rings[i], rcu);
1262 WRITE_ONCE(vsi->tx_rings[i], NULL);
1263 }
1264 }
1265 }
1266 if (vsi->rx_rings) {
1267 for (i = 0; i < vsi->alloc_rxq; i++) {
1268 if (vsi->rx_rings[i]) {
1269 kfree_rcu(vsi->rx_rings[i], rcu);
1270 WRITE_ONCE(vsi->rx_rings[i], NULL);
1271 }
1272 }
1273 }
1274}
1275
1276
1277
1278
1279
1280static int ice_vsi_alloc_rings(struct ice_vsi *vsi)
1281{
1282 struct ice_pf *pf = vsi->back;
1283 struct device *dev;
1284 u16 i;
1285
1286 dev = ice_pf_to_dev(pf);
1287
1288 for (i = 0; i < vsi->alloc_txq; i++) {
1289 struct ice_ring *ring;
1290
1291
1292 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1293
1294 if (!ring)
1295 goto err_out;
1296
1297 ring->q_index = i;
1298 ring->reg_idx = vsi->txq_map[i];
1299 ring->ring_active = false;
1300 ring->vsi = vsi;
1301 ring->tx_tstamps = &pf->ptp.port.tx;
1302 ring->dev = dev;
1303 ring->count = vsi->num_tx_desc;
1304 WRITE_ONCE(vsi->tx_rings[i], ring);
1305 }
1306
1307
1308 for (i = 0; i < vsi->alloc_rxq; i++) {
1309 struct ice_ring *ring;
1310
1311
1312 ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1313 if (!ring)
1314 goto err_out;
1315
1316 ring->q_index = i;
1317 ring->reg_idx = vsi->rxq_map[i];
1318 ring->ring_active = false;
1319 ring->vsi = vsi;
1320 ring->netdev = vsi->netdev;
1321 ring->dev = dev;
1322 ring->count = vsi->num_rx_desc;
1323 WRITE_ONCE(vsi->rx_rings[i], ring);
1324 }
1325
1326 return 0;
1327
1328err_out:
1329 ice_vsi_clear_rings(vsi);
1330 return -ENOMEM;
1331}
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342void ice_vsi_manage_rss_lut(struct ice_vsi *vsi, bool ena)
1343{
1344 u8 *lut;
1345
1346 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
1347 if (!lut)
1348 return;
1349
1350 if (ena) {
1351 if (vsi->rss_lut_user)
1352 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1353 else
1354 ice_fill_rss_lut(lut, vsi->rss_table_size,
1355 vsi->rss_size);
1356 }
1357
1358 ice_set_rss_lut(vsi, lut, vsi->rss_table_size);
1359 kfree(lut);
1360}
1361
1362
1363
1364
1365
1366static int ice_vsi_cfg_rss_lut_key(struct ice_vsi *vsi)
1367{
1368 struct ice_pf *pf = vsi->back;
1369 struct device *dev;
1370 u8 *lut, *key;
1371 int err;
1372
1373 dev = ice_pf_to_dev(pf);
1374 vsi->rss_size = min_t(u16, vsi->rss_size, vsi->num_rxq);
1375
1376 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
1377 if (!lut)
1378 return -ENOMEM;
1379
1380 if (vsi->rss_lut_user)
1381 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1382 else
1383 ice_fill_rss_lut(lut, vsi->rss_table_size, vsi->rss_size);
1384
1385 err = ice_set_rss_lut(vsi, lut, vsi->rss_table_size);
1386 if (err) {
1387 dev_err(dev, "set_rss_lut failed, error %d\n", err);
1388 goto ice_vsi_cfg_rss_exit;
1389 }
1390
1391 key = kzalloc(ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE, GFP_KERNEL);
1392 if (!key) {
1393 err = -ENOMEM;
1394 goto ice_vsi_cfg_rss_exit;
1395 }
1396
1397 if (vsi->rss_hkey_user)
1398 memcpy(key, vsi->rss_hkey_user, ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE);
1399 else
1400 netdev_rss_key_fill((void *)key, ICE_GET_SET_RSS_KEY_EXTEND_KEY_SIZE);
1401
1402 err = ice_set_rss_key(vsi, key);
1403 if (err)
1404 dev_err(dev, "set_rss_key failed, error %d\n", err);
1405
1406 kfree(key);
1407ice_vsi_cfg_rss_exit:
1408 kfree(lut);
1409 return err;
1410}
1411
1412
1413
1414
1415
1416
1417
1418
1419
1420static void ice_vsi_set_vf_rss_flow_fld(struct ice_vsi *vsi)
1421{
1422 struct ice_pf *pf = vsi->back;
1423 enum ice_status status;
1424 struct device *dev;
1425
1426 dev = ice_pf_to_dev(pf);
1427 if (ice_is_safe_mode(pf)) {
1428 dev_dbg(dev, "Advanced RSS disabled. Package download failed, vsi num = %d\n",
1429 vsi->vsi_num);
1430 return;
1431 }
1432
1433 status = ice_add_avf_rss_cfg(&pf->hw, vsi->idx, ICE_DEFAULT_RSS_HENA);
1434 if (status)
1435 dev_dbg(dev, "ice_add_avf_rss_cfg failed for vsi = %d, error = %s\n",
1436 vsi->vsi_num, ice_stat_str(status));
1437}
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450static void ice_vsi_set_rss_flow_fld(struct ice_vsi *vsi)
1451{
1452 u16 vsi_handle = vsi->idx, vsi_num = vsi->vsi_num;
1453 struct ice_pf *pf = vsi->back;
1454 struct ice_hw *hw = &pf->hw;
1455 enum ice_status status;
1456 struct device *dev;
1457
1458 dev = ice_pf_to_dev(pf);
1459 if (ice_is_safe_mode(pf)) {
1460 dev_dbg(dev, "Advanced RSS disabled. Package download failed, vsi num = %d\n",
1461 vsi_num);
1462 return;
1463 }
1464
1465 status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV4,
1466 ICE_FLOW_SEG_HDR_IPV4);
1467 if (status)
1468 dev_dbg(dev, "ice_add_rss_cfg failed for ipv4 flow, vsi = %d, error = %s\n",
1469 vsi_num, ice_stat_str(status));
1470
1471
1472 status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV6,
1473 ICE_FLOW_SEG_HDR_IPV6);
1474 if (status)
1475 dev_dbg(dev, "ice_add_rss_cfg failed for ipv6 flow, vsi = %d, error = %s\n",
1476 vsi_num, ice_stat_str(status));
1477
1478
1479 status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_TCP_IPV4,
1480 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1481 if (status)
1482 dev_dbg(dev, "ice_add_rss_cfg failed for tcp4 flow, vsi = %d, error = %s\n",
1483 vsi_num, ice_stat_str(status));
1484
1485
1486 status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_UDP_IPV4,
1487 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1488 if (status)
1489 dev_dbg(dev, "ice_add_rss_cfg failed for udp4 flow, vsi = %d, error = %s\n",
1490 vsi_num, ice_stat_str(status));
1491
1492
1493 status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV4,
1494 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1495 if (status)
1496 dev_dbg(dev, "ice_add_rss_cfg failed for sctp4 flow, vsi = %d, error = %s\n",
1497 vsi_num, ice_stat_str(status));
1498
1499
1500 status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_TCP_IPV6,
1501 ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1502 if (status)
1503 dev_dbg(dev, "ice_add_rss_cfg failed for tcp6 flow, vsi = %d, error = %s\n",
1504 vsi_num, ice_stat_str(status));
1505
1506
1507 status = ice_add_rss_cfg(hw, vsi_handle, ICE_HASH_UDP_IPV6,
1508 ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1509 if (status)
1510 dev_dbg(dev, "ice_add_rss_cfg failed for udp6 flow, vsi = %d, error = %s\n",
1511 vsi_num, ice_stat_str(status));
1512
1513
1514 status = ice_add_rss_cfg(hw, vsi_handle, ICE_FLOW_HASH_IPV6,
1515 ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1516 if (status)
1517 dev_dbg(dev, "ice_add_rss_cfg failed for sctp6 flow, vsi = %d, error = %s\n",
1518 vsi_num, ice_stat_str(status));
1519}
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531bool ice_pf_state_is_nominal(struct ice_pf *pf)
1532{
1533 DECLARE_BITMAP(check_bits, ICE_STATE_NBITS) = { 0 };
1534
1535 if (!pf)
1536 return false;
1537
1538 bitmap_set(check_bits, 0, ICE_STATE_NOMINAL_CHECK_BITS);
1539 if (bitmap_intersects(pf->state, check_bits, ICE_STATE_NBITS))
1540 return false;
1541
1542 return true;
1543}
1544
1545
1546
1547
1548
1549void ice_update_eth_stats(struct ice_vsi *vsi)
1550{
1551 struct ice_eth_stats *prev_es, *cur_es;
1552 struct ice_hw *hw = &vsi->back->hw;
1553 u16 vsi_num = vsi->vsi_num;
1554
1555 prev_es = &vsi->eth_stats_prev;
1556 cur_es = &vsi->eth_stats;
1557
1558 ice_stat_update40(hw, GLV_GORCL(vsi_num), vsi->stat_offsets_loaded,
1559 &prev_es->rx_bytes, &cur_es->rx_bytes);
1560
1561 ice_stat_update40(hw, GLV_UPRCL(vsi_num), vsi->stat_offsets_loaded,
1562 &prev_es->rx_unicast, &cur_es->rx_unicast);
1563
1564 ice_stat_update40(hw, GLV_MPRCL(vsi_num), vsi->stat_offsets_loaded,
1565 &prev_es->rx_multicast, &cur_es->rx_multicast);
1566
1567 ice_stat_update40(hw, GLV_BPRCL(vsi_num), vsi->stat_offsets_loaded,
1568 &prev_es->rx_broadcast, &cur_es->rx_broadcast);
1569
1570 ice_stat_update32(hw, GLV_RDPC(vsi_num), vsi->stat_offsets_loaded,
1571 &prev_es->rx_discards, &cur_es->rx_discards);
1572
1573 ice_stat_update40(hw, GLV_GOTCL(vsi_num), vsi->stat_offsets_loaded,
1574 &prev_es->tx_bytes, &cur_es->tx_bytes);
1575
1576 ice_stat_update40(hw, GLV_UPTCL(vsi_num), vsi->stat_offsets_loaded,
1577 &prev_es->tx_unicast, &cur_es->tx_unicast);
1578
1579 ice_stat_update40(hw, GLV_MPTCL(vsi_num), vsi->stat_offsets_loaded,
1580 &prev_es->tx_multicast, &cur_es->tx_multicast);
1581
1582 ice_stat_update40(hw, GLV_BPTCL(vsi_num), vsi->stat_offsets_loaded,
1583 &prev_es->tx_broadcast, &cur_es->tx_broadcast);
1584
1585 ice_stat_update32(hw, GLV_TEPC(vsi_num), vsi->stat_offsets_loaded,
1586 &prev_es->tx_errors, &cur_es->tx_errors);
1587
1588 vsi->stat_offsets_loaded = true;
1589}
1590
1591
1592
1593
1594
1595
1596
1597int
1598ice_vsi_add_vlan(struct ice_vsi *vsi, u16 vid, enum ice_sw_fwd_act_type action)
1599{
1600 struct ice_pf *pf = vsi->back;
1601 struct device *dev;
1602 int err = 0;
1603
1604 dev = ice_pf_to_dev(pf);
1605
1606 if (!ice_fltr_add_vlan(vsi, vid, action)) {
1607 vsi->num_vlan++;
1608 } else {
1609 err = -ENODEV;
1610 dev_err(dev, "Failure Adding VLAN %d on VSI %i\n", vid,
1611 vsi->vsi_num);
1612 }
1613
1614 return err;
1615}
1616
1617
1618
1619
1620
1621
1622
1623
1624int ice_vsi_kill_vlan(struct ice_vsi *vsi, u16 vid)
1625{
1626 struct ice_pf *pf = vsi->back;
1627 enum ice_status status;
1628 struct device *dev;
1629 int err = 0;
1630
1631 dev = ice_pf_to_dev(pf);
1632
1633 status = ice_fltr_remove_vlan(vsi, vid, ICE_FWD_TO_VSI);
1634 if (!status) {
1635 vsi->num_vlan--;
1636 } else if (status == ICE_ERR_DOES_NOT_EXIST) {
1637 dev_dbg(dev, "Failed to remove VLAN %d on VSI %i, it does not exist, status: %s\n",
1638 vid, vsi->vsi_num, ice_stat_str(status));
1639 } else {
1640 dev_err(dev, "Error removing VLAN %d on vsi %i error: %s\n",
1641 vid, vsi->vsi_num, ice_stat_str(status));
1642 err = -EIO;
1643 }
1644
1645 return err;
1646}
1647
1648
1649
1650
1651
1652void ice_vsi_cfg_frame_size(struct ice_vsi *vsi)
1653{
1654 if (!vsi->netdev || test_bit(ICE_FLAG_LEGACY_RX, vsi->back->flags)) {
1655 vsi->max_frame = ICE_AQ_SET_MAC_FRAME_SIZE_MAX;
1656 vsi->rx_buf_len = ICE_RXBUF_2048;
1657#if (PAGE_SIZE < 8192)
1658 } else if (!ICE_2K_TOO_SMALL_WITH_PADDING &&
1659 (vsi->netdev->mtu <= ETH_DATA_LEN)) {
1660 vsi->max_frame = ICE_RXBUF_1536 - NET_IP_ALIGN;
1661 vsi->rx_buf_len = ICE_RXBUF_1536 - NET_IP_ALIGN;
1662#endif
1663 } else {
1664 vsi->max_frame = ICE_AQ_SET_MAC_FRAME_SIZE_MAX;
1665#if (PAGE_SIZE < 8192)
1666 vsi->rx_buf_len = ICE_RXBUF_3072;
1667#else
1668 vsi->rx_buf_len = ICE_RXBUF_2048;
1669#endif
1670 }
1671}
1672
1673
1674
1675
1676
1677
1678
1679
1680
1681void
1682ice_write_qrxflxp_cntxt(struct ice_hw *hw, u16 pf_q, u32 rxdid, u32 prio,
1683 bool ena_ts)
1684{
1685 int regval = rd32(hw, QRXFLXP_CNTXT(pf_q));
1686
1687
1688 regval &= ~(QRXFLXP_CNTXT_RXDID_IDX_M |
1689 QRXFLXP_CNTXT_RXDID_PRIO_M |
1690 QRXFLXP_CNTXT_TS_M);
1691
1692 regval |= (rxdid << QRXFLXP_CNTXT_RXDID_IDX_S) &
1693 QRXFLXP_CNTXT_RXDID_IDX_M;
1694
1695 regval |= (prio << QRXFLXP_CNTXT_RXDID_PRIO_S) &
1696 QRXFLXP_CNTXT_RXDID_PRIO_M;
1697
1698 if (ena_ts)
1699
1700 regval |= QRXFLXP_CNTXT_TS_M;
1701
1702 wr32(hw, QRXFLXP_CNTXT(pf_q), regval);
1703}
1704
1705int ice_vsi_cfg_single_rxq(struct ice_vsi *vsi, u16 q_idx)
1706{
1707 if (q_idx >= vsi->num_rxq)
1708 return -EINVAL;
1709
1710 return ice_vsi_cfg_rxq(vsi->rx_rings[q_idx]);
1711}
1712
1713int ice_vsi_cfg_single_txq(struct ice_vsi *vsi, struct ice_ring **tx_rings, u16 q_idx)
1714{
1715 struct ice_aqc_add_tx_qgrp *qg_buf;
1716 int err;
1717
1718 if (q_idx >= vsi->alloc_txq || !tx_rings || !tx_rings[q_idx])
1719 return -EINVAL;
1720
1721 qg_buf = kzalloc(struct_size(qg_buf, txqs, 1), GFP_KERNEL);
1722 if (!qg_buf)
1723 return -ENOMEM;
1724
1725 qg_buf->num_txqs = 1;
1726
1727 err = ice_vsi_cfg_txq(vsi, tx_rings[q_idx], qg_buf);
1728 kfree(qg_buf);
1729 return err;
1730}
1731
1732
1733
1734
1735
1736
1737
1738
1739int ice_vsi_cfg_rxqs(struct ice_vsi *vsi)
1740{
1741 u16 i;
1742
1743 if (vsi->type == ICE_VSI_VF)
1744 goto setup_rings;
1745
1746 ice_vsi_cfg_frame_size(vsi);
1747setup_rings:
1748
1749 ice_for_each_rxq(vsi, i) {
1750 int err = ice_vsi_cfg_rxq(vsi->rx_rings[i]);
1751
1752 if (err)
1753 return err;
1754 }
1755
1756 return 0;
1757}
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768static int
1769ice_vsi_cfg_txqs(struct ice_vsi *vsi, struct ice_ring **rings, u16 count)
1770{
1771 struct ice_aqc_add_tx_qgrp *qg_buf;
1772 u16 q_idx = 0;
1773 int err = 0;
1774
1775 qg_buf = kzalloc(struct_size(qg_buf, txqs, 1), GFP_KERNEL);
1776 if (!qg_buf)
1777 return -ENOMEM;
1778
1779 qg_buf->num_txqs = 1;
1780
1781 for (q_idx = 0; q_idx < count; q_idx++) {
1782 err = ice_vsi_cfg_txq(vsi, rings[q_idx], qg_buf);
1783 if (err)
1784 goto err_cfg_txqs;
1785 }
1786
1787err_cfg_txqs:
1788 kfree(qg_buf);
1789 return err;
1790}
1791
1792
1793
1794
1795
1796
1797
1798
1799int ice_vsi_cfg_lan_txqs(struct ice_vsi *vsi)
1800{
1801 return ice_vsi_cfg_txqs(vsi, vsi->tx_rings, vsi->num_txq);
1802}
1803
1804
1805
1806
1807
1808
1809
1810
1811int ice_vsi_cfg_xdp_txqs(struct ice_vsi *vsi)
1812{
1813 int ret;
1814 int i;
1815
1816 ret = ice_vsi_cfg_txqs(vsi, vsi->xdp_rings, vsi->num_xdp_txq);
1817 if (ret)
1818 return ret;
1819
1820 for (i = 0; i < vsi->num_xdp_txq; i++)
1821 vsi->xdp_rings[i]->xsk_pool = ice_xsk_pool(vsi->xdp_rings[i]);
1822
1823 return ret;
1824}
1825
1826
1827
1828
1829
1830
1831
1832
1833
1834static u32 ice_intrl_usec_to_reg(u8 intrl, u8 gran)
1835{
1836 u32 val = intrl / gran;
1837
1838 if (val)
1839 return val | GLINT_RATE_INTRL_ENA_M;
1840 return 0;
1841}
1842
1843
1844
1845
1846
1847
1848void ice_write_intrl(struct ice_q_vector *q_vector, u8 intrl)
1849{
1850 struct ice_hw *hw = &q_vector->vsi->back->hw;
1851
1852 wr32(hw, GLINT_RATE(q_vector->reg_idx),
1853 ice_intrl_usec_to_reg(intrl, ICE_INTRL_GRAN_ABOVE_25));
1854}
1855
1856
1857
1858
1859
1860
1861
1862static void __ice_write_itr(struct ice_q_vector *q_vector,
1863 struct ice_ring_container *rc, u16 itr)
1864{
1865 struct ice_hw *hw = &q_vector->vsi->back->hw;
1866
1867 wr32(hw, GLINT_ITR(rc->itr_idx, q_vector->reg_idx),
1868 ITR_REG_ALIGN(itr) >> ICE_ITR_GRAN_S);
1869}
1870
1871
1872
1873
1874
1875
1876void ice_write_itr(struct ice_ring_container *rc, u16 itr)
1877{
1878 struct ice_q_vector *q_vector;
1879
1880 if (!rc->ring)
1881 return;
1882
1883 q_vector = rc->ring->q_vector;
1884
1885 __ice_write_itr(q_vector, rc, itr);
1886}
1887
1888
1889
1890
1891
1892
1893
1894
1895void ice_vsi_cfg_msix(struct ice_vsi *vsi)
1896{
1897 struct ice_pf *pf = vsi->back;
1898 struct ice_hw *hw = &pf->hw;
1899 u16 txq = 0, rxq = 0;
1900 int i, q;
1901
1902 for (i = 0; i < vsi->num_q_vectors; i++) {
1903 struct ice_q_vector *q_vector = vsi->q_vectors[i];
1904 u16 reg_idx = q_vector->reg_idx;
1905
1906 ice_cfg_itr(hw, q_vector);
1907
1908
1909
1910
1911
1912
1913
1914
1915
1916
1917
1918
1919 for (q = 0; q < q_vector->num_ring_tx; q++) {
1920 ice_cfg_txq_interrupt(vsi, txq, reg_idx,
1921 q_vector->tx.itr_idx);
1922 txq++;
1923 }
1924
1925 for (q = 0; q < q_vector->num_ring_rx; q++) {
1926 ice_cfg_rxq_interrupt(vsi, rxq, reg_idx,
1927 q_vector->rx.itr_idx);
1928 rxq++;
1929 }
1930 }
1931}
1932
1933
1934
1935
1936
1937int ice_vsi_manage_vlan_insertion(struct ice_vsi *vsi)
1938{
1939 struct ice_hw *hw = &vsi->back->hw;
1940 struct ice_vsi_ctx *ctxt;
1941 enum ice_status status;
1942 int ret = 0;
1943
1944 ctxt = kzalloc(sizeof(*ctxt), GFP_KERNEL);
1945 if (!ctxt)
1946 return -ENOMEM;
1947
1948
1949
1950
1951
1952 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1953
1954
1955 ctxt->info.vlan_flags |= (vsi->info.vlan_flags &
1956 ICE_AQ_VSI_VLAN_EMOD_M);
1957
1958 ctxt->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);
1959
1960 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
1961 if (status) {
1962 dev_err(ice_pf_to_dev(vsi->back), "update VSI for VLAN insert failed, err %s aq_err %s\n",
1963 ice_stat_str(status),
1964 ice_aq_str(hw->adminq.sq_last_status));
1965 ret = -EIO;
1966 goto out;
1967 }
1968
1969 vsi->info.vlan_flags = ctxt->info.vlan_flags;
1970out:
1971 kfree(ctxt);
1972 return ret;
1973}
1974
1975
1976
1977
1978
1979
1980int ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
1981{
1982 struct ice_hw *hw = &vsi->back->hw;
1983 struct ice_vsi_ctx *ctxt;
1984 enum ice_status status;
1985 int ret = 0;
1986
1987
1988
1989
1990 if (vsi->info.pvid)
1991 return 0;
1992
1993 ctxt = kzalloc(sizeof(*ctxt), GFP_KERNEL);
1994 if (!ctxt)
1995 return -ENOMEM;
1996
1997
1998
1999
2000
2001 if (ena)
2002
2003 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2004 else
2005
2006 ctxt->info.vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2007
2008
2009 ctxt->info.vlan_flags |= ICE_AQ_VSI_VLAN_MODE_ALL;
2010
2011 ctxt->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_VLAN_VALID);
2012
2013 status = ice_update_vsi(hw, vsi->idx, ctxt, NULL);
2014 if (status) {
2015 dev_err(ice_pf_to_dev(vsi->back), "update VSI for VLAN strip failed, ena = %d err %s aq_err %s\n",
2016 ena, ice_stat_str(status),
2017 ice_aq_str(hw->adminq.sq_last_status));
2018 ret = -EIO;
2019 goto out;
2020 }
2021
2022 vsi->info.vlan_flags = ctxt->info.vlan_flags;
2023out:
2024 kfree(ctxt);
2025 return ret;
2026}
2027
2028
2029
2030
2031
2032
2033
2034int ice_vsi_start_all_rx_rings(struct ice_vsi *vsi)
2035{
2036 return ice_vsi_ctrl_all_rx_rings(vsi, true);
2037}
2038
2039
2040
2041
2042
2043
2044
2045int ice_vsi_stop_all_rx_rings(struct ice_vsi *vsi)
2046{
2047 return ice_vsi_ctrl_all_rx_rings(vsi, false);
2048}
2049
2050
2051
2052
2053
2054
2055
2056
2057
2058static int
2059ice_vsi_stop_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
2060 u16 rel_vmvf_num, struct ice_ring **rings, u16 count)
2061{
2062 u16 q_idx;
2063
2064 if (vsi->num_txq > ICE_LAN_TXQ_MAX_QDIS)
2065 return -EINVAL;
2066
2067 for (q_idx = 0; q_idx < count; q_idx++) {
2068 struct ice_txq_meta txq_meta = { };
2069 int status;
2070
2071 if (!rings || !rings[q_idx])
2072 return -EINVAL;
2073
2074 ice_fill_txq_meta(vsi, rings[q_idx], &txq_meta);
2075 status = ice_vsi_stop_tx_ring(vsi, rst_src, rel_vmvf_num,
2076 rings[q_idx], &txq_meta);
2077
2078 if (status)
2079 return status;
2080 }
2081
2082 return 0;
2083}
2084
2085
2086
2087
2088
2089
2090
2091int
2092ice_vsi_stop_lan_tx_rings(struct ice_vsi *vsi, enum ice_disq_rst_src rst_src,
2093 u16 rel_vmvf_num)
2094{
2095 return ice_vsi_stop_tx_rings(vsi, rst_src, rel_vmvf_num, vsi->tx_rings, vsi->num_txq);
2096}
2097
2098
2099
2100
2101
2102int ice_vsi_stop_xdp_tx_rings(struct ice_vsi *vsi)
2103{
2104 return ice_vsi_stop_tx_rings(vsi, ICE_NO_RESET, 0, vsi->xdp_rings, vsi->num_xdp_txq);
2105}
2106
2107
2108
2109
2110
2111
2112
2113bool ice_vsi_is_vlan_pruning_ena(struct ice_vsi *vsi)
2114{
2115 if (!vsi)
2116 return false;
2117
2118 return (vsi->info.sw_flags2 & ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA);
2119}
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129int ice_cfg_vlan_pruning(struct ice_vsi *vsi, bool ena, bool vlan_promisc)
2130{
2131 struct ice_vsi_ctx *ctxt;
2132 struct ice_pf *pf;
2133 int status;
2134
2135 if (!vsi)
2136 return -EINVAL;
2137
2138
2139
2140
2141
2142 if (vsi->netdev && vsi->netdev->flags & IFF_PROMISC && ena)
2143 return 0;
2144
2145 pf = vsi->back;
2146 ctxt = kzalloc(sizeof(*ctxt), GFP_KERNEL);
2147 if (!ctxt)
2148 return -ENOMEM;
2149
2150 ctxt->info = vsi->info;
2151
2152 if (ena)
2153 ctxt->info.sw_flags2 |= ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2154 else
2155 ctxt->info.sw_flags2 &= ~ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2156
2157 if (!vlan_promisc)
2158 ctxt->info.valid_sections =
2159 cpu_to_le16(ICE_AQ_VSI_PROP_SW_VALID);
2160
2161 status = ice_update_vsi(&pf->hw, vsi->idx, ctxt, NULL);
2162 if (status) {
2163 netdev_err(vsi->netdev, "%sabling VLAN pruning on VSI handle: %d, VSI HW ID: %d failed, err = %s, aq_err = %s\n",
2164 ena ? "En" : "Dis", vsi->idx, vsi->vsi_num,
2165 ice_stat_str(status),
2166 ice_aq_str(pf->hw.adminq.sq_last_status));
2167 goto err_out;
2168 }
2169
2170 vsi->info.sw_flags2 = ctxt->info.sw_flags2;
2171
2172 kfree(ctxt);
2173 return 0;
2174
2175err_out:
2176 kfree(ctxt);
2177 return -EIO;
2178}
2179
2180static void ice_vsi_set_tc_cfg(struct ice_vsi *vsi)
2181{
2182 struct ice_dcbx_cfg *cfg = &vsi->port_info->qos_cfg.local_dcbx_cfg;
2183
2184 vsi->tc_cfg.ena_tc = ice_dcb_get_ena_tc(cfg);
2185 vsi->tc_cfg.numtc = ice_dcb_get_num_tc(cfg);
2186}
2187
2188
2189
2190
2191
2192static int
2193ice_vsi_set_q_vectors_reg_idx(struct ice_vsi *vsi)
2194{
2195 u16 i;
2196
2197 if (!vsi || !vsi->q_vectors)
2198 return -EINVAL;
2199
2200 ice_for_each_q_vector(vsi, i) {
2201 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2202
2203 if (!q_vector) {
2204 dev_err(ice_pf_to_dev(vsi->back), "Failed to set reg_idx on q_vector %d VSI %d\n",
2205 i, vsi->vsi_num);
2206 goto clear_reg_idx;
2207 }
2208
2209 if (vsi->type == ICE_VSI_VF) {
2210 struct ice_vf *vf = &vsi->back->vf[vsi->vf_id];
2211
2212 q_vector->reg_idx = ice_calc_vf_reg_idx(vf, q_vector);
2213 } else {
2214 q_vector->reg_idx =
2215 q_vector->v_idx + vsi->base_vector;
2216 }
2217 }
2218
2219 return 0;
2220
2221clear_reg_idx:
2222 ice_for_each_q_vector(vsi, i) {
2223 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2224
2225 if (q_vector)
2226 q_vector->reg_idx = 0;
2227 }
2228
2229 return -EINVAL;
2230}
2231
2232
2233
2234
2235
2236
2237
2238void ice_cfg_sw_lldp(struct ice_vsi *vsi, bool tx, bool create)
2239{
2240 enum ice_status (*eth_fltr)(struct ice_vsi *v, u16 type, u16 flag,
2241 enum ice_sw_fwd_act_type act);
2242 struct ice_pf *pf = vsi->back;
2243 enum ice_status status;
2244 struct device *dev;
2245
2246 dev = ice_pf_to_dev(pf);
2247 eth_fltr = create ? ice_fltr_add_eth : ice_fltr_remove_eth;
2248
2249 if (tx) {
2250 status = eth_fltr(vsi, ETH_P_LLDP, ICE_FLTR_TX,
2251 ICE_DROP_PACKET);
2252 } else {
2253 if (ice_fw_supports_lldp_fltr_ctrl(&pf->hw)) {
2254 status = ice_lldp_fltr_add_remove(&pf->hw, vsi->vsi_num,
2255 create);
2256 } else {
2257 status = eth_fltr(vsi, ETH_P_LLDP, ICE_FLTR_RX,
2258 ICE_FWD_TO_VSI);
2259 }
2260 }
2261
2262 if (status)
2263 dev_dbg(dev, "Fail %s %s LLDP rule on VSI %i error: %s\n",
2264 create ? "adding" : "removing", tx ? "TX" : "RX",
2265 vsi->vsi_num, ice_stat_str(status));
2266}
2267
2268
2269
2270
2271
2272
2273
2274
2275static void ice_set_agg_vsi(struct ice_vsi *vsi)
2276{
2277 struct device *dev = ice_pf_to_dev(vsi->back);
2278 struct ice_agg_node *agg_node_iter = NULL;
2279 u32 agg_id = ICE_INVALID_AGG_NODE_ID;
2280 struct ice_agg_node *agg_node = NULL;
2281 int node_offset, max_agg_nodes = 0;
2282 struct ice_port_info *port_info;
2283 struct ice_pf *pf = vsi->back;
2284 u32 agg_node_id_start = 0;
2285 enum ice_status status;
2286
2287
2288
2289
2290
2291
2292 port_info = pf->hw.port_info;
2293 if (!port_info)
2294 return;
2295
2296 switch (vsi->type) {
2297 case ICE_VSI_CTRL:
2298 case ICE_VSI_LB:
2299 case ICE_VSI_PF:
2300 max_agg_nodes = ICE_MAX_PF_AGG_NODES;
2301 agg_node_id_start = ICE_PF_AGG_NODE_ID_START;
2302 agg_node_iter = &pf->pf_agg_node[0];
2303 break;
2304 case ICE_VSI_VF:
2305
2306
2307
2308
2309
2310
2311 max_agg_nodes = ICE_MAX_VF_AGG_NODES;
2312 agg_node_id_start = ICE_VF_AGG_NODE_ID_START;
2313 agg_node_iter = &pf->vf_agg_node[0];
2314 break;
2315 default:
2316
2317 dev_dbg(dev, "unexpected VSI type %s\n",
2318 ice_vsi_type_str(vsi->type));
2319 return;
2320 }
2321
2322
2323 for (node_offset = 0; node_offset < max_agg_nodes; node_offset++) {
2324
2325
2326
2327 if (agg_node_iter->num_vsis &&
2328 agg_node_iter->num_vsis == ICE_MAX_VSIS_IN_AGG_NODE) {
2329 agg_node_iter++;
2330 continue;
2331 }
2332
2333 if (agg_node_iter->valid &&
2334 agg_node_iter->agg_id != ICE_INVALID_AGG_NODE_ID) {
2335 agg_id = agg_node_iter->agg_id;
2336 agg_node = agg_node_iter;
2337 break;
2338 }
2339
2340
2341 if (agg_node_iter->agg_id == ICE_INVALID_AGG_NODE_ID) {
2342 agg_id = node_offset + agg_node_id_start;
2343 agg_node = agg_node_iter;
2344 break;
2345 }
2346
2347 agg_node_iter++;
2348 }
2349
2350 if (!agg_node)
2351 return;
2352
2353
2354 if (!agg_node->valid) {
2355 status = ice_cfg_agg(port_info, agg_id, ICE_AGG_TYPE_AGG,
2356 (u8)vsi->tc_cfg.ena_tc);
2357 if (status) {
2358 dev_err(dev, "unable to create aggregator node with agg_id %u\n",
2359 agg_id);
2360 return;
2361 }
2362
2363 agg_node->valid = true;
2364 agg_node->agg_id = agg_id;
2365 }
2366
2367
2368 status = ice_move_vsi_to_agg(port_info, agg_id, vsi->idx,
2369 (u8)vsi->tc_cfg.ena_tc);
2370 if (status) {
2371 dev_err(dev, "unable to move VSI idx %u into aggregator %u node",
2372 vsi->idx, agg_id);
2373 return;
2374 }
2375
2376
2377 agg_node->num_vsis++;
2378
2379
2380
2381
2382 vsi->agg_node = agg_node;
2383 dev_dbg(dev, "successfully moved VSI idx %u tc_bitmap 0x%x) into aggregator node %d which has num_vsis %u\n",
2384 vsi->idx, vsi->tc_cfg.ena_tc, vsi->agg_node->agg_id,
2385 vsi->agg_node->num_vsis);
2386}
2387
2388
2389
2390
2391
2392
2393
2394
2395
2396
2397
2398
2399
2400
2401
2402struct ice_vsi *
2403ice_vsi_setup(struct ice_pf *pf, struct ice_port_info *pi,
2404 enum ice_vsi_type vsi_type, u16 vf_id)
2405{
2406 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
2407 struct device *dev = ice_pf_to_dev(pf);
2408 enum ice_status status;
2409 struct ice_vsi *vsi;
2410 int ret, i;
2411
2412 if (vsi_type == ICE_VSI_VF || vsi_type == ICE_VSI_CTRL)
2413 vsi = ice_vsi_alloc(pf, vsi_type, vf_id);
2414 else
2415 vsi = ice_vsi_alloc(pf, vsi_type, ICE_INVAL_VFID);
2416
2417 if (!vsi) {
2418 dev_err(dev, "could not allocate VSI\n");
2419 return NULL;
2420 }
2421
2422 vsi->port_info = pi;
2423 vsi->vsw = pf->first_sw;
2424 if (vsi->type == ICE_VSI_PF)
2425 vsi->ethtype = ETH_P_PAUSE;
2426
2427 if (vsi->type == ICE_VSI_VF || vsi->type == ICE_VSI_CTRL)
2428 vsi->vf_id = vf_id;
2429
2430 ice_alloc_fd_res(vsi);
2431
2432 if (ice_vsi_get_qs(vsi)) {
2433 dev_err(dev, "Failed to allocate queues. vsi->idx = %d\n",
2434 vsi->idx);
2435 goto unroll_vsi_alloc;
2436 }
2437
2438
2439 ice_vsi_set_rss_params(vsi);
2440
2441
2442 ice_vsi_set_tc_cfg(vsi);
2443
2444
2445 ret = ice_vsi_init(vsi, true);
2446 if (ret)
2447 goto unroll_get_qs;
2448
2449 switch (vsi->type) {
2450 case ICE_VSI_CTRL:
2451 case ICE_VSI_PF:
2452 ret = ice_vsi_alloc_q_vectors(vsi);
2453 if (ret)
2454 goto unroll_vsi_init;
2455
2456 ret = ice_vsi_setup_vector_base(vsi);
2457 if (ret)
2458 goto unroll_alloc_q_vector;
2459
2460 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
2461 if (ret)
2462 goto unroll_vector_base;
2463
2464 ret = ice_vsi_alloc_rings(vsi);
2465 if (ret)
2466 goto unroll_vector_base;
2467
2468
2469
2470
2471
2472
2473
2474
2475 ret = ice_vsi_add_vlan(vsi, 0, ICE_FWD_TO_VSI);
2476 if (ret)
2477 goto unroll_clear_rings;
2478
2479 ice_vsi_map_rings_to_vectors(vsi);
2480
2481
2482 if (vsi->type != ICE_VSI_CTRL)
2483
2484
2485
2486
2487 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
2488 ice_vsi_cfg_rss_lut_key(vsi);
2489 ice_vsi_set_rss_flow_fld(vsi);
2490 }
2491 ice_init_arfs(vsi);
2492 break;
2493 case ICE_VSI_VF:
2494
2495
2496
2497
2498
2499 ret = ice_vsi_alloc_q_vectors(vsi);
2500 if (ret)
2501 goto unroll_vsi_init;
2502
2503 ret = ice_vsi_alloc_rings(vsi);
2504 if (ret)
2505 goto unroll_alloc_q_vector;
2506
2507 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
2508 if (ret)
2509 goto unroll_vector_base;
2510
2511
2512
2513
2514
2515 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags)) {
2516 ice_vsi_cfg_rss_lut_key(vsi);
2517 ice_vsi_set_vf_rss_flow_fld(vsi);
2518 }
2519 break;
2520 case ICE_VSI_LB:
2521 ret = ice_vsi_alloc_rings(vsi);
2522 if (ret)
2523 goto unroll_vsi_init;
2524 break;
2525 default:
2526
2527 goto unroll_vsi_init;
2528 }
2529
2530
2531 for (i = 0; i < vsi->tc_cfg.numtc; i++)
2532 max_txqs[i] = vsi->alloc_txq;
2533
2534 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
2535 max_txqs);
2536 if (status) {
2537 dev_err(dev, "VSI %d failed lan queue config, error %s\n",
2538 vsi->vsi_num, ice_stat_str(status));
2539 goto unroll_clear_rings;
2540 }
2541
2542
2543
2544
2545
2546
2547
2548
2549
2550
2551 if (!ice_is_safe_mode(pf))
2552 if (vsi->type == ICE_VSI_PF) {
2553 ice_fltr_add_eth(vsi, ETH_P_PAUSE, ICE_FLTR_TX,
2554 ICE_DROP_PACKET);
2555 ice_cfg_sw_lldp(vsi, true, true);
2556 }
2557
2558 if (!vsi->agg_node)
2559 ice_set_agg_vsi(vsi);
2560 return vsi;
2561
2562unroll_clear_rings:
2563 ice_vsi_clear_rings(vsi);
2564unroll_vector_base:
2565
2566 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
2567 pf->num_avail_sw_msix += vsi->num_q_vectors;
2568unroll_alloc_q_vector:
2569 ice_vsi_free_q_vectors(vsi);
2570unroll_vsi_init:
2571 ice_vsi_delete(vsi);
2572unroll_get_qs:
2573 ice_vsi_put_qs(vsi);
2574unroll_vsi_alloc:
2575 if (vsi_type == ICE_VSI_VF)
2576 ice_enable_lag(pf->lag);
2577 ice_vsi_clear(vsi);
2578
2579 return NULL;
2580}
2581
2582
2583
2584
2585
2586static void ice_vsi_release_msix(struct ice_vsi *vsi)
2587{
2588 struct ice_pf *pf = vsi->back;
2589 struct ice_hw *hw = &pf->hw;
2590 u32 txq = 0;
2591 u32 rxq = 0;
2592 int i, q;
2593
2594 for (i = 0; i < vsi->num_q_vectors; i++) {
2595 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2596
2597 ice_write_intrl(q_vector, 0);
2598 for (q = 0; q < q_vector->num_ring_tx; q++) {
2599 ice_write_itr(&q_vector->tx, 0);
2600 wr32(hw, QINT_TQCTL(vsi->txq_map[txq]), 0);
2601 if (ice_is_xdp_ena_vsi(vsi)) {
2602 u32 xdp_txq = txq + vsi->num_xdp_txq;
2603
2604 wr32(hw, QINT_TQCTL(vsi->txq_map[xdp_txq]), 0);
2605 }
2606 txq++;
2607 }
2608
2609 for (q = 0; q < q_vector->num_ring_rx; q++) {
2610 ice_write_itr(&q_vector->rx, 0);
2611 wr32(hw, QINT_RQCTL(vsi->rxq_map[rxq]), 0);
2612 rxq++;
2613 }
2614 }
2615
2616 ice_flush(hw);
2617}
2618
2619
2620
2621
2622
2623void ice_vsi_free_irq(struct ice_vsi *vsi)
2624{
2625 struct ice_pf *pf = vsi->back;
2626 int base = vsi->base_vector;
2627 int i;
2628
2629 if (!vsi->q_vectors || !vsi->irqs_ready)
2630 return;
2631
2632 ice_vsi_release_msix(vsi);
2633 if (vsi->type == ICE_VSI_VF)
2634 return;
2635
2636 vsi->irqs_ready = false;
2637 ice_for_each_q_vector(vsi, i) {
2638 u16 vector = i + base;
2639 int irq_num;
2640
2641 irq_num = pf->msix_entries[vector].vector;
2642
2643
2644 if (!vsi->q_vectors[i] ||
2645 !(vsi->q_vectors[i]->num_ring_tx ||
2646 vsi->q_vectors[i]->num_ring_rx))
2647 continue;
2648
2649
2650 irq_set_affinity_notifier(irq_num, NULL);
2651
2652
2653 irq_set_affinity_hint(irq_num, NULL);
2654 synchronize_irq(irq_num);
2655 devm_free_irq(ice_pf_to_dev(pf), irq_num, vsi->q_vectors[i]);
2656 }
2657}
2658
2659
2660
2661
2662
2663void ice_vsi_free_tx_rings(struct ice_vsi *vsi)
2664{
2665 int i;
2666
2667 if (!vsi->tx_rings)
2668 return;
2669
2670 ice_for_each_txq(vsi, i)
2671 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
2672 ice_free_tx_ring(vsi->tx_rings[i]);
2673}
2674
2675
2676
2677
2678
2679void ice_vsi_free_rx_rings(struct ice_vsi *vsi)
2680{
2681 int i;
2682
2683 if (!vsi->rx_rings)
2684 return;
2685
2686 ice_for_each_rxq(vsi, i)
2687 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
2688 ice_free_rx_ring(vsi->rx_rings[i]);
2689}
2690
2691
2692
2693
2694
2695void ice_vsi_close(struct ice_vsi *vsi)
2696{
2697 if (!test_and_set_bit(ICE_VSI_DOWN, vsi->state))
2698 ice_down(vsi);
2699
2700 ice_vsi_free_irq(vsi);
2701 ice_vsi_free_tx_rings(vsi);
2702 ice_vsi_free_rx_rings(vsi);
2703}
2704
2705
2706
2707
2708
2709
2710int ice_ena_vsi(struct ice_vsi *vsi, bool locked)
2711{
2712 int err = 0;
2713
2714 if (!test_bit(ICE_VSI_NEEDS_RESTART, vsi->state))
2715 return 0;
2716
2717 clear_bit(ICE_VSI_NEEDS_RESTART, vsi->state);
2718
2719 if (vsi->netdev && vsi->type == ICE_VSI_PF) {
2720 if (netif_running(vsi->netdev)) {
2721 if (!locked)
2722 rtnl_lock();
2723
2724 err = ice_open_internal(vsi->netdev);
2725
2726 if (!locked)
2727 rtnl_unlock();
2728 }
2729 } else if (vsi->type == ICE_VSI_CTRL) {
2730 err = ice_vsi_open_ctrl(vsi);
2731 }
2732
2733 return err;
2734}
2735
2736
2737
2738
2739
2740
2741void ice_dis_vsi(struct ice_vsi *vsi, bool locked)
2742{
2743 if (test_bit(ICE_VSI_DOWN, vsi->state))
2744 return;
2745
2746 set_bit(ICE_VSI_NEEDS_RESTART, vsi->state);
2747
2748 if (vsi->type == ICE_VSI_PF && vsi->netdev) {
2749 if (netif_running(vsi->netdev)) {
2750 if (!locked)
2751 rtnl_lock();
2752
2753 ice_vsi_close(vsi);
2754
2755 if (!locked)
2756 rtnl_unlock();
2757 } else {
2758 ice_vsi_close(vsi);
2759 }
2760 } else if (vsi->type == ICE_VSI_CTRL) {
2761 ice_vsi_close(vsi);
2762 }
2763}
2764
2765
2766
2767
2768
2769void ice_vsi_dis_irq(struct ice_vsi *vsi)
2770{
2771 int base = vsi->base_vector;
2772 struct ice_pf *pf = vsi->back;
2773 struct ice_hw *hw = &pf->hw;
2774 u32 val;
2775 int i;
2776
2777
2778 if (vsi->tx_rings) {
2779 ice_for_each_txq(vsi, i) {
2780 if (vsi->tx_rings[i]) {
2781 u16 reg;
2782
2783 reg = vsi->tx_rings[i]->reg_idx;
2784 val = rd32(hw, QINT_TQCTL(reg));
2785 val &= ~QINT_TQCTL_CAUSE_ENA_M;
2786 wr32(hw, QINT_TQCTL(reg), val);
2787 }
2788 }
2789 }
2790
2791 if (vsi->rx_rings) {
2792 ice_for_each_rxq(vsi, i) {
2793 if (vsi->rx_rings[i]) {
2794 u16 reg;
2795
2796 reg = vsi->rx_rings[i]->reg_idx;
2797 val = rd32(hw, QINT_RQCTL(reg));
2798 val &= ~QINT_RQCTL_CAUSE_ENA_M;
2799 wr32(hw, QINT_RQCTL(reg), val);
2800 }
2801 }
2802 }
2803
2804
2805 ice_for_each_q_vector(vsi, i) {
2806 if (!vsi->q_vectors[i])
2807 continue;
2808 wr32(hw, GLINT_DYN_CTL(vsi->q_vectors[i]->reg_idx), 0);
2809 }
2810
2811 ice_flush(hw);
2812
2813
2814 if (vsi->type == ICE_VSI_VF)
2815 return;
2816
2817 ice_for_each_q_vector(vsi, i)
2818 synchronize_irq(pf->msix_entries[i + base].vector);
2819}
2820
2821
2822
2823
2824
2825void ice_napi_del(struct ice_vsi *vsi)
2826{
2827 int v_idx;
2828
2829 if (!vsi->netdev)
2830 return;
2831
2832 ice_for_each_q_vector(vsi, v_idx)
2833 netif_napi_del(&vsi->q_vectors[v_idx]->napi);
2834}
2835
2836
2837
2838
2839
2840
2841
2842int ice_vsi_release(struct ice_vsi *vsi)
2843{
2844 struct ice_pf *pf;
2845
2846 if (!vsi->back)
2847 return -ENODEV;
2848 pf = vsi->back;
2849
2850
2851
2852
2853
2854
2855
2856 if (vsi->netdev && !ice_is_reset_in_progress(pf->state) &&
2857 (test_bit(ICE_VSI_NETDEV_REGISTERED, vsi->state))) {
2858 unregister_netdev(vsi->netdev);
2859 clear_bit(ICE_VSI_NETDEV_REGISTERED, vsi->state);
2860 }
2861
2862 ice_devlink_destroy_port(vsi);
2863
2864 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
2865 ice_rss_clean(vsi);
2866
2867
2868 if (vsi->type != ICE_VSI_LB)
2869 ice_vsi_dis_irq(vsi);
2870 ice_vsi_close(vsi);
2871
2872
2873
2874
2875
2876
2877 if (vsi->type == ICE_VSI_CTRL && vsi->vf_id != ICE_INVAL_VFID) {
2878 int i;
2879
2880 ice_for_each_vf(pf, i) {
2881 struct ice_vf *vf = &pf->vf[i];
2882
2883 if (i != vsi->vf_id && vf->ctrl_vsi_idx != ICE_NO_VSI)
2884 break;
2885 }
2886 if (i == pf->num_alloc_vfs) {
2887
2888
2889
2890 ice_free_res(pf->irq_tracker, vsi->base_vector,
2891 ICE_RES_VF_CTRL_VEC_ID);
2892 pf->num_avail_sw_msix += vsi->num_q_vectors;
2893 }
2894 } else if (vsi->type != ICE_VSI_VF) {
2895
2896 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
2897 pf->num_avail_sw_msix += vsi->num_q_vectors;
2898 }
2899
2900 if (!ice_is_safe_mode(pf)) {
2901 if (vsi->type == ICE_VSI_PF) {
2902 ice_fltr_remove_eth(vsi, ETH_P_PAUSE, ICE_FLTR_TX,
2903 ICE_DROP_PACKET);
2904 ice_cfg_sw_lldp(vsi, true, false);
2905
2906
2907
2908 if (!test_bit(ICE_FLAG_FW_LLDP_AGENT, pf->flags))
2909 ice_cfg_sw_lldp(vsi, false, false);
2910 }
2911 }
2912
2913 ice_fltr_remove_all(vsi);
2914 ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
2915 ice_vsi_delete(vsi);
2916 ice_vsi_free_q_vectors(vsi);
2917
2918 if (vsi->netdev) {
2919 if (test_bit(ICE_VSI_NETDEV_REGISTERED, vsi->state)) {
2920 unregister_netdev(vsi->netdev);
2921 clear_bit(ICE_VSI_NETDEV_REGISTERED, vsi->state);
2922 }
2923 if (test_bit(ICE_VSI_NETDEV_ALLOCD, vsi->state)) {
2924 free_netdev(vsi->netdev);
2925 vsi->netdev = NULL;
2926 clear_bit(ICE_VSI_NETDEV_ALLOCD, vsi->state);
2927 }
2928 }
2929
2930 if (vsi->type == ICE_VSI_VF &&
2931 vsi->agg_node && vsi->agg_node->valid)
2932 vsi->agg_node->num_vsis--;
2933 ice_vsi_clear_rings(vsi);
2934
2935 ice_vsi_put_qs(vsi);
2936
2937
2938
2939
2940
2941 if (!ice_is_reset_in_progress(pf->state))
2942 ice_vsi_clear(vsi);
2943
2944 return 0;
2945}
2946
2947
2948
2949
2950
2951
2952
2953
2954static int
2955ice_vsi_rebuild_get_coalesce(struct ice_vsi *vsi,
2956 struct ice_coalesce_stored *coalesce)
2957{
2958 int i;
2959
2960 ice_for_each_q_vector(vsi, i) {
2961 struct ice_q_vector *q_vector = vsi->q_vectors[i];
2962
2963 coalesce[i].itr_tx = q_vector->tx.itr_setting;
2964 coalesce[i].itr_rx = q_vector->rx.itr_setting;
2965 coalesce[i].intrl = q_vector->intrl;
2966
2967 if (i < vsi->num_txq)
2968 coalesce[i].tx_valid = true;
2969 if (i < vsi->num_rxq)
2970 coalesce[i].rx_valid = true;
2971 }
2972
2973 return vsi->num_q_vectors;
2974}
2975
2976
2977
2978
2979
2980
2981
2982
2983
2984
2985
2986static void
2987ice_vsi_rebuild_set_coalesce(struct ice_vsi *vsi,
2988 struct ice_coalesce_stored *coalesce, int size)
2989{
2990 struct ice_ring_container *rc;
2991 int i;
2992
2993 if ((size && !coalesce) || !vsi)
2994 return;
2995
2996
2997
2998
2999
3000
3001
3002 for (i = 0; i < size && i < vsi->num_q_vectors; i++) {
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018 if (i < vsi->alloc_rxq && coalesce[i].rx_valid) {
3019 rc = &vsi->q_vectors[i]->rx;
3020 rc->itr_setting = coalesce[i].itr_rx;
3021 ice_write_itr(rc, rc->itr_setting);
3022 } else if (i < vsi->alloc_rxq) {
3023 rc = &vsi->q_vectors[i]->rx;
3024 rc->itr_setting = coalesce[0].itr_rx;
3025 ice_write_itr(rc, rc->itr_setting);
3026 }
3027
3028 if (i < vsi->alloc_txq && coalesce[i].tx_valid) {
3029 rc = &vsi->q_vectors[i]->tx;
3030 rc->itr_setting = coalesce[i].itr_tx;
3031 ice_write_itr(rc, rc->itr_setting);
3032 } else if (i < vsi->alloc_txq) {
3033 rc = &vsi->q_vectors[i]->tx;
3034 rc->itr_setting = coalesce[0].itr_tx;
3035 ice_write_itr(rc, rc->itr_setting);
3036 }
3037
3038 vsi->q_vectors[i]->intrl = coalesce[i].intrl;
3039 ice_write_intrl(vsi->q_vectors[i], coalesce[i].intrl);
3040 }
3041
3042
3043
3044
3045 for (; i < vsi->num_q_vectors; i++) {
3046
3047 rc = &vsi->q_vectors[i]->tx;
3048 rc->itr_setting = coalesce[0].itr_tx;
3049 ice_write_itr(rc, rc->itr_setting);
3050
3051
3052 rc = &vsi->q_vectors[i]->rx;
3053 rc->itr_setting = coalesce[0].itr_rx;
3054 ice_write_itr(rc, rc->itr_setting);
3055
3056 vsi->q_vectors[i]->intrl = coalesce[0].intrl;
3057 ice_write_intrl(vsi->q_vectors[i], coalesce[0].intrl);
3058 }
3059}
3060
3061
3062
3063
3064
3065
3066
3067
3068int ice_vsi_rebuild(struct ice_vsi *vsi, bool init_vsi)
3069{
3070 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
3071 struct ice_coalesce_stored *coalesce;
3072 int prev_num_q_vectors = 0;
3073 struct ice_vf *vf = NULL;
3074 enum ice_vsi_type vtype;
3075 enum ice_status status;
3076 struct ice_pf *pf;
3077 int ret, i;
3078
3079 if (!vsi)
3080 return -EINVAL;
3081
3082 pf = vsi->back;
3083 vtype = vsi->type;
3084 if (vtype == ICE_VSI_VF)
3085 vf = &pf->vf[vsi->vf_id];
3086
3087 coalesce = kcalloc(vsi->num_q_vectors,
3088 sizeof(struct ice_coalesce_stored), GFP_KERNEL);
3089 if (!coalesce)
3090 return -ENOMEM;
3091
3092 prev_num_q_vectors = ice_vsi_rebuild_get_coalesce(vsi, coalesce);
3093
3094 ice_rm_vsi_lan_cfg(vsi->port_info, vsi->idx);
3095 ice_vsi_free_q_vectors(vsi);
3096
3097
3098
3099
3100
3101
3102 if (vtype != ICE_VSI_VF) {
3103
3104 ice_free_res(pf->irq_tracker, vsi->base_vector, vsi->idx);
3105 pf->num_avail_sw_msix += vsi->num_q_vectors;
3106 vsi->base_vector = 0;
3107 }
3108
3109 if (ice_is_xdp_ena_vsi(vsi))
3110
3111
3112
3113 ice_destroy_xdp_rings(vsi);
3114 ice_vsi_put_qs(vsi);
3115 ice_vsi_clear_rings(vsi);
3116 ice_vsi_free_arrays(vsi);
3117 if (vtype == ICE_VSI_VF)
3118 ice_vsi_set_num_qs(vsi, vf->vf_id);
3119 else
3120 ice_vsi_set_num_qs(vsi, ICE_INVAL_VFID);
3121
3122 ret = ice_vsi_alloc_arrays(vsi);
3123 if (ret < 0)
3124 goto err_vsi;
3125
3126 ice_vsi_get_qs(vsi);
3127
3128 ice_alloc_fd_res(vsi);
3129 ice_vsi_set_tc_cfg(vsi);
3130
3131
3132 ret = ice_vsi_init(vsi, init_vsi);
3133 if (ret < 0)
3134 goto err_vsi;
3135
3136 switch (vtype) {
3137 case ICE_VSI_CTRL:
3138 case ICE_VSI_PF:
3139 ret = ice_vsi_alloc_q_vectors(vsi);
3140 if (ret)
3141 goto err_rings;
3142
3143 ret = ice_vsi_setup_vector_base(vsi);
3144 if (ret)
3145 goto err_vectors;
3146
3147 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
3148 if (ret)
3149 goto err_vectors;
3150
3151 ret = ice_vsi_alloc_rings(vsi);
3152 if (ret)
3153 goto err_vectors;
3154
3155 ice_vsi_map_rings_to_vectors(vsi);
3156 if (ice_is_xdp_ena_vsi(vsi)) {
3157 vsi->num_xdp_txq = vsi->alloc_rxq;
3158 ret = ice_prepare_xdp_rings(vsi, vsi->xdp_prog);
3159 if (ret)
3160 goto err_vectors;
3161 }
3162
3163 if (vtype != ICE_VSI_CTRL)
3164
3165
3166
3167
3168 if (test_bit(ICE_FLAG_RSS_ENA, pf->flags))
3169 ice_vsi_cfg_rss_lut_key(vsi);
3170 break;
3171 case ICE_VSI_VF:
3172 ret = ice_vsi_alloc_q_vectors(vsi);
3173 if (ret)
3174 goto err_rings;
3175
3176 ret = ice_vsi_set_q_vectors_reg_idx(vsi);
3177 if (ret)
3178 goto err_vectors;
3179
3180 ret = ice_vsi_alloc_rings(vsi);
3181 if (ret)
3182 goto err_vectors;
3183
3184 break;
3185 default:
3186 break;
3187 }
3188
3189
3190 for (i = 0; i < vsi->tc_cfg.numtc; i++) {
3191 max_txqs[i] = vsi->alloc_txq;
3192
3193 if (ice_is_xdp_ena_vsi(vsi))
3194 max_txqs[i] += vsi->num_xdp_txq;
3195 }
3196
3197 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
3198 max_txqs);
3199 if (status) {
3200 dev_err(ice_pf_to_dev(pf), "VSI %d failed lan queue config, error %s\n",
3201 vsi->vsi_num, ice_stat_str(status));
3202 if (init_vsi) {
3203 ret = -EIO;
3204 goto err_vectors;
3205 } else {
3206 return ice_schedule_reset(pf, ICE_RESET_PFR);
3207 }
3208 }
3209 ice_vsi_rebuild_set_coalesce(vsi, coalesce, prev_num_q_vectors);
3210 kfree(coalesce);
3211
3212 return 0;
3213
3214err_vectors:
3215 ice_vsi_free_q_vectors(vsi);
3216err_rings:
3217 if (vsi->netdev) {
3218 vsi->current_netdev_flags = 0;
3219 unregister_netdev(vsi->netdev);
3220 free_netdev(vsi->netdev);
3221 vsi->netdev = NULL;
3222 }
3223err_vsi:
3224 ice_vsi_clear(vsi);
3225 set_bit(ICE_RESET_FAILED, pf->state);
3226 kfree(coalesce);
3227 return ret;
3228}
3229
3230
3231
3232
3233
3234bool ice_is_reset_in_progress(unsigned long *state)
3235{
3236 return test_bit(ICE_RESET_OICR_RECV, state) ||
3237 test_bit(ICE_PFR_REQ, state) ||
3238 test_bit(ICE_CORER_REQ, state) ||
3239 test_bit(ICE_GLOBR_REQ, state);
3240}
3241
3242
3243
3244
3245
3246
3247
3248
3249
3250
3251
3252
3253
3254
3255int ice_wait_for_reset(struct ice_pf *pf, unsigned long timeout)
3256{
3257 long ret;
3258
3259 ret = wait_event_interruptible_timeout(pf->reset_wait_queue,
3260 !ice_is_reset_in_progress(pf->state),
3261 timeout);
3262 if (ret < 0)
3263 return ret;
3264 else if (!ret)
3265 return -EBUSY;
3266 else
3267 return 0;
3268}
3269
3270#ifdef CONFIG_DCB
3271
3272
3273
3274
3275
3276static void ice_vsi_update_q_map(struct ice_vsi *vsi, struct ice_vsi_ctx *ctx)
3277{
3278 vsi->info.mapping_flags = ctx->info.mapping_flags;
3279 memcpy(&vsi->info.q_mapping, &ctx->info.q_mapping,
3280 sizeof(vsi->info.q_mapping));
3281 memcpy(&vsi->info.tc_mapping, ctx->info.tc_mapping,
3282 sizeof(vsi->info.tc_mapping));
3283}
3284
3285
3286
3287
3288
3289
3290
3291
3292int ice_vsi_cfg_tc(struct ice_vsi *vsi, u8 ena_tc)
3293{
3294 u16 max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
3295 struct ice_pf *pf = vsi->back;
3296 struct ice_vsi_ctx *ctx;
3297 enum ice_status status;
3298 struct device *dev;
3299 int i, ret = 0;
3300 u8 num_tc = 0;
3301
3302 dev = ice_pf_to_dev(pf);
3303
3304 ice_for_each_traffic_class(i) {
3305
3306 if (ena_tc & BIT(i))
3307 num_tc++;
3308
3309 max_txqs[i] = vsi->alloc_txq;
3310 }
3311
3312 vsi->tc_cfg.ena_tc = ena_tc;
3313 vsi->tc_cfg.numtc = num_tc;
3314
3315 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
3316 if (!ctx)
3317 return -ENOMEM;
3318
3319 ctx->vf_num = 0;
3320 ctx->info = vsi->info;
3321
3322 ice_vsi_setup_q_map(vsi, ctx);
3323
3324
3325 ctx->info.valid_sections = cpu_to_le16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
3326 status = ice_update_vsi(&pf->hw, vsi->idx, ctx, NULL);
3327 if (status) {
3328 dev_info(dev, "Failed VSI Update\n");
3329 ret = -EIO;
3330 goto out;
3331 }
3332
3333 status = ice_cfg_vsi_lan(vsi->port_info, vsi->idx, vsi->tc_cfg.ena_tc,
3334 max_txqs);
3335
3336 if (status) {
3337 dev_err(dev, "VSI %d failed TC config, error %s\n",
3338 vsi->vsi_num, ice_stat_str(status));
3339 ret = -EIO;
3340 goto out;
3341 }
3342 ice_vsi_update_q_map(vsi, ctx);
3343 vsi->info.valid_sections = 0;
3344
3345 ice_vsi_cfg_netdev_tc(vsi, ena_tc);
3346out:
3347 kfree(ctx);
3348 return ret;
3349}
3350#endif
3351
3352
3353
3354
3355
3356
3357
3358
3359
3360static void ice_update_ring_stats(struct ice_ring *ring, u64 pkts, u64 bytes)
3361{
3362 ring->stats.bytes += bytes;
3363 ring->stats.pkts += pkts;
3364}
3365
3366
3367
3368
3369
3370
3371
3372void ice_update_tx_ring_stats(struct ice_ring *tx_ring, u64 pkts, u64 bytes)
3373{
3374 u64_stats_update_begin(&tx_ring->syncp);
3375 ice_update_ring_stats(tx_ring, pkts, bytes);
3376 u64_stats_update_end(&tx_ring->syncp);
3377}
3378
3379
3380
3381
3382
3383
3384
3385void ice_update_rx_ring_stats(struct ice_ring *rx_ring, u64 pkts, u64 bytes)
3386{
3387 u64_stats_update_begin(&rx_ring->syncp);
3388 ice_update_ring_stats(rx_ring, pkts, bytes);
3389 u64_stats_update_end(&rx_ring->syncp);
3390}
3391
3392
3393
3394
3395
3396int ice_status_to_errno(enum ice_status err)
3397{
3398 switch (err) {
3399 case ICE_SUCCESS:
3400 return 0;
3401 case ICE_ERR_DOES_NOT_EXIST:
3402 return -ENOENT;
3403 case ICE_ERR_OUT_OF_RANGE:
3404 case ICE_ERR_AQ_ERROR:
3405 case ICE_ERR_AQ_TIMEOUT:
3406 case ICE_ERR_AQ_EMPTY:
3407 case ICE_ERR_AQ_FW_CRITICAL:
3408 return -EIO;
3409 case ICE_ERR_PARAM:
3410 case ICE_ERR_INVAL_SIZE:
3411 return -EINVAL;
3412 case ICE_ERR_NO_MEMORY:
3413 return -ENOMEM;
3414 case ICE_ERR_MAX_LIMIT:
3415 return -EAGAIN;
3416 case ICE_ERR_RESET_ONGOING:
3417 return -EBUSY;
3418 case ICE_ERR_AQ_FULL:
3419 return -ENOSPC;
3420 default:
3421 return -EINVAL;
3422 }
3423}
3424
3425
3426
3427
3428
3429
3430
3431
3432bool ice_is_dflt_vsi_in_use(struct ice_sw *sw)
3433{
3434 return (sw->dflt_vsi && sw->dflt_vsi_ena);
3435}
3436
3437
3438
3439
3440
3441
3442
3443
3444
3445bool ice_is_vsi_dflt_vsi(struct ice_sw *sw, struct ice_vsi *vsi)
3446{
3447 return (sw->dflt_vsi == vsi && sw->dflt_vsi_ena);
3448}
3449
3450
3451
3452
3453
3454
3455
3456
3457
3458
3459
3460
3461
3462
3463
3464int ice_set_dflt_vsi(struct ice_sw *sw, struct ice_vsi *vsi)
3465{
3466 enum ice_status status;
3467 struct device *dev;
3468
3469 if (!sw || !vsi)
3470 return -EINVAL;
3471
3472 dev = ice_pf_to_dev(vsi->back);
3473
3474
3475 if (ice_is_vsi_dflt_vsi(sw, vsi)) {
3476 dev_dbg(dev, "VSI %d passed in is already the default forwarding VSI, nothing to do\n",
3477 vsi->vsi_num);
3478 return 0;
3479 }
3480
3481
3482 if (ice_is_dflt_vsi_in_use(sw)) {
3483 dev_err(dev, "Default forwarding VSI %d already in use, disable it and try again\n",
3484 sw->dflt_vsi->vsi_num);
3485 return -EEXIST;
3486 }
3487
3488 status = ice_cfg_dflt_vsi(&vsi->back->hw, vsi->idx, true, ICE_FLTR_RX);
3489 if (status) {
3490 dev_err(dev, "Failed to set VSI %d as the default forwarding VSI, error %s\n",
3491 vsi->vsi_num, ice_stat_str(status));
3492 return -EIO;
3493 }
3494
3495 sw->dflt_vsi = vsi;
3496 sw->dflt_vsi_ena = true;
3497
3498 return 0;
3499}
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509int ice_clear_dflt_vsi(struct ice_sw *sw)
3510{
3511 struct ice_vsi *dflt_vsi;
3512 enum ice_status status;
3513 struct device *dev;
3514
3515 if (!sw)
3516 return -EINVAL;
3517
3518 dev = ice_pf_to_dev(sw->pf);
3519
3520 dflt_vsi = sw->dflt_vsi;
3521
3522
3523 if (!ice_is_dflt_vsi_in_use(sw))
3524 return -ENODEV;
3525
3526 status = ice_cfg_dflt_vsi(&dflt_vsi->back->hw, dflt_vsi->idx, false,
3527 ICE_FLTR_RX);
3528 if (status) {
3529 dev_err(dev, "Failed to clear the default forwarding VSI %d, error %s\n",
3530 dflt_vsi->vsi_num, ice_stat_str(status));
3531 return -EIO;
3532 }
3533
3534 sw->dflt_vsi = NULL;
3535 sw->dflt_vsi_ena = false;
3536
3537 return 0;
3538}
3539
3540
3541
3542
3543
3544
3545int ice_set_link(struct ice_vsi *vsi, bool ena)
3546{
3547 struct device *dev = ice_pf_to_dev(vsi->back);
3548 struct ice_port_info *pi = vsi->port_info;
3549 struct ice_hw *hw = pi->hw;
3550 enum ice_status status;
3551
3552 if (vsi->type != ICE_VSI_PF)
3553 return -EINVAL;
3554
3555 status = ice_aq_set_link_restart_an(pi, ena, NULL);
3556
3557
3558
3559
3560
3561
3562 if (status == ICE_ERR_AQ_ERROR) {
3563 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE)
3564 dev_warn(dev, "can't set link to %s, err %s aq_err %s. not fatal, continuing\n",
3565 (ena ? "ON" : "OFF"), ice_stat_str(status),
3566 ice_aq_str(hw->adminq.sq_last_status));
3567 } else if (status) {
3568 dev_err(dev, "can't set link to %s, err %s aq_err %s\n",
3569 (ena ? "ON" : "OFF"), ice_stat_str(status),
3570 ice_aq_str(hw->adminq.sq_last_status));
3571 return -EIO;
3572 }
3573
3574 return 0;
3575}
3576