1
2
3
4#include "i40e.h"
5#include "i40e_type.h"
6#include "i40e_adminq.h"
7#include "i40e_prototype.h"
8#include <linux/avf/virtchnl.h>
9
10
11
12
13
14
15
16
17i40e_status i40e_set_mac_type(struct i40e_hw *hw)
18{
19 i40e_status status = 0;
20
21 if (hw->vendor_id == PCI_VENDOR_ID_INTEL) {
22 switch (hw->device_id) {
23 case I40E_DEV_ID_SFP_XL710:
24 case I40E_DEV_ID_QEMU:
25 case I40E_DEV_ID_KX_B:
26 case I40E_DEV_ID_KX_C:
27 case I40E_DEV_ID_QSFP_A:
28 case I40E_DEV_ID_QSFP_B:
29 case I40E_DEV_ID_QSFP_C:
30 case I40E_DEV_ID_5G_BASE_T_BC:
31 case I40E_DEV_ID_10G_BASE_T:
32 case I40E_DEV_ID_10G_BASE_T4:
33 case I40E_DEV_ID_10G_BASE_T_BC:
34 case I40E_DEV_ID_10G_B:
35 case I40E_DEV_ID_10G_SFP:
36 case I40E_DEV_ID_20G_KR2:
37 case I40E_DEV_ID_20G_KR2_A:
38 case I40E_DEV_ID_25G_B:
39 case I40E_DEV_ID_25G_SFP28:
40 case I40E_DEV_ID_X710_N3000:
41 case I40E_DEV_ID_XXV710_N3000:
42 hw->mac.type = I40E_MAC_XL710;
43 break;
44 case I40E_DEV_ID_KX_X722:
45 case I40E_DEV_ID_QSFP_X722:
46 case I40E_DEV_ID_SFP_X722:
47 case I40E_DEV_ID_1G_BASE_T_X722:
48 case I40E_DEV_ID_10G_BASE_T_X722:
49 case I40E_DEV_ID_SFP_I_X722:
50 hw->mac.type = I40E_MAC_X722;
51 break;
52 default:
53 hw->mac.type = I40E_MAC_GENERIC;
54 break;
55 }
56 } else {
57 status = I40E_ERR_DEVICE_NOT_SUPPORTED;
58 }
59
60 hw_dbg(hw, "i40e_set_mac_type found mac: %d, returns: %d\n",
61 hw->mac.type, status);
62 return status;
63}
64
65
66
67
68
69
70const char *i40e_aq_str(struct i40e_hw *hw, enum i40e_admin_queue_err aq_err)
71{
72 switch (aq_err) {
73 case I40E_AQ_RC_OK:
74 return "OK";
75 case I40E_AQ_RC_EPERM:
76 return "I40E_AQ_RC_EPERM";
77 case I40E_AQ_RC_ENOENT:
78 return "I40E_AQ_RC_ENOENT";
79 case I40E_AQ_RC_ESRCH:
80 return "I40E_AQ_RC_ESRCH";
81 case I40E_AQ_RC_EINTR:
82 return "I40E_AQ_RC_EINTR";
83 case I40E_AQ_RC_EIO:
84 return "I40E_AQ_RC_EIO";
85 case I40E_AQ_RC_ENXIO:
86 return "I40E_AQ_RC_ENXIO";
87 case I40E_AQ_RC_E2BIG:
88 return "I40E_AQ_RC_E2BIG";
89 case I40E_AQ_RC_EAGAIN:
90 return "I40E_AQ_RC_EAGAIN";
91 case I40E_AQ_RC_ENOMEM:
92 return "I40E_AQ_RC_ENOMEM";
93 case I40E_AQ_RC_EACCES:
94 return "I40E_AQ_RC_EACCES";
95 case I40E_AQ_RC_EFAULT:
96 return "I40E_AQ_RC_EFAULT";
97 case I40E_AQ_RC_EBUSY:
98 return "I40E_AQ_RC_EBUSY";
99 case I40E_AQ_RC_EEXIST:
100 return "I40E_AQ_RC_EEXIST";
101 case I40E_AQ_RC_EINVAL:
102 return "I40E_AQ_RC_EINVAL";
103 case I40E_AQ_RC_ENOTTY:
104 return "I40E_AQ_RC_ENOTTY";
105 case I40E_AQ_RC_ENOSPC:
106 return "I40E_AQ_RC_ENOSPC";
107 case I40E_AQ_RC_ENOSYS:
108 return "I40E_AQ_RC_ENOSYS";
109 case I40E_AQ_RC_ERANGE:
110 return "I40E_AQ_RC_ERANGE";
111 case I40E_AQ_RC_EFLUSHED:
112 return "I40E_AQ_RC_EFLUSHED";
113 case I40E_AQ_RC_BAD_ADDR:
114 return "I40E_AQ_RC_BAD_ADDR";
115 case I40E_AQ_RC_EMODE:
116 return "I40E_AQ_RC_EMODE";
117 case I40E_AQ_RC_EFBIG:
118 return "I40E_AQ_RC_EFBIG";
119 }
120
121 snprintf(hw->err_str, sizeof(hw->err_str), "%d", aq_err);
122 return hw->err_str;
123}
124
125
126
127
128
129
130const char *i40e_stat_str(struct i40e_hw *hw, i40e_status stat_err)
131{
132 switch (stat_err) {
133 case 0:
134 return "OK";
135 case I40E_ERR_NVM:
136 return "I40E_ERR_NVM";
137 case I40E_ERR_NVM_CHECKSUM:
138 return "I40E_ERR_NVM_CHECKSUM";
139 case I40E_ERR_PHY:
140 return "I40E_ERR_PHY";
141 case I40E_ERR_CONFIG:
142 return "I40E_ERR_CONFIG";
143 case I40E_ERR_PARAM:
144 return "I40E_ERR_PARAM";
145 case I40E_ERR_MAC_TYPE:
146 return "I40E_ERR_MAC_TYPE";
147 case I40E_ERR_UNKNOWN_PHY:
148 return "I40E_ERR_UNKNOWN_PHY";
149 case I40E_ERR_LINK_SETUP:
150 return "I40E_ERR_LINK_SETUP";
151 case I40E_ERR_ADAPTER_STOPPED:
152 return "I40E_ERR_ADAPTER_STOPPED";
153 case I40E_ERR_INVALID_MAC_ADDR:
154 return "I40E_ERR_INVALID_MAC_ADDR";
155 case I40E_ERR_DEVICE_NOT_SUPPORTED:
156 return "I40E_ERR_DEVICE_NOT_SUPPORTED";
157 case I40E_ERR_MASTER_REQUESTS_PENDING:
158 return "I40E_ERR_MASTER_REQUESTS_PENDING";
159 case I40E_ERR_INVALID_LINK_SETTINGS:
160 return "I40E_ERR_INVALID_LINK_SETTINGS";
161 case I40E_ERR_AUTONEG_NOT_COMPLETE:
162 return "I40E_ERR_AUTONEG_NOT_COMPLETE";
163 case I40E_ERR_RESET_FAILED:
164 return "I40E_ERR_RESET_FAILED";
165 case I40E_ERR_SWFW_SYNC:
166 return "I40E_ERR_SWFW_SYNC";
167 case I40E_ERR_NO_AVAILABLE_VSI:
168 return "I40E_ERR_NO_AVAILABLE_VSI";
169 case I40E_ERR_NO_MEMORY:
170 return "I40E_ERR_NO_MEMORY";
171 case I40E_ERR_BAD_PTR:
172 return "I40E_ERR_BAD_PTR";
173 case I40E_ERR_RING_FULL:
174 return "I40E_ERR_RING_FULL";
175 case I40E_ERR_INVALID_PD_ID:
176 return "I40E_ERR_INVALID_PD_ID";
177 case I40E_ERR_INVALID_QP_ID:
178 return "I40E_ERR_INVALID_QP_ID";
179 case I40E_ERR_INVALID_CQ_ID:
180 return "I40E_ERR_INVALID_CQ_ID";
181 case I40E_ERR_INVALID_CEQ_ID:
182 return "I40E_ERR_INVALID_CEQ_ID";
183 case I40E_ERR_INVALID_AEQ_ID:
184 return "I40E_ERR_INVALID_AEQ_ID";
185 case I40E_ERR_INVALID_SIZE:
186 return "I40E_ERR_INVALID_SIZE";
187 case I40E_ERR_INVALID_ARP_INDEX:
188 return "I40E_ERR_INVALID_ARP_INDEX";
189 case I40E_ERR_INVALID_FPM_FUNC_ID:
190 return "I40E_ERR_INVALID_FPM_FUNC_ID";
191 case I40E_ERR_QP_INVALID_MSG_SIZE:
192 return "I40E_ERR_QP_INVALID_MSG_SIZE";
193 case I40E_ERR_QP_TOOMANY_WRS_POSTED:
194 return "I40E_ERR_QP_TOOMANY_WRS_POSTED";
195 case I40E_ERR_INVALID_FRAG_COUNT:
196 return "I40E_ERR_INVALID_FRAG_COUNT";
197 case I40E_ERR_QUEUE_EMPTY:
198 return "I40E_ERR_QUEUE_EMPTY";
199 case I40E_ERR_INVALID_ALIGNMENT:
200 return "I40E_ERR_INVALID_ALIGNMENT";
201 case I40E_ERR_FLUSHED_QUEUE:
202 return "I40E_ERR_FLUSHED_QUEUE";
203 case I40E_ERR_INVALID_PUSH_PAGE_INDEX:
204 return "I40E_ERR_INVALID_PUSH_PAGE_INDEX";
205 case I40E_ERR_INVALID_IMM_DATA_SIZE:
206 return "I40E_ERR_INVALID_IMM_DATA_SIZE";
207 case I40E_ERR_TIMEOUT:
208 return "I40E_ERR_TIMEOUT";
209 case I40E_ERR_OPCODE_MISMATCH:
210 return "I40E_ERR_OPCODE_MISMATCH";
211 case I40E_ERR_CQP_COMPL_ERROR:
212 return "I40E_ERR_CQP_COMPL_ERROR";
213 case I40E_ERR_INVALID_VF_ID:
214 return "I40E_ERR_INVALID_VF_ID";
215 case I40E_ERR_INVALID_HMCFN_ID:
216 return "I40E_ERR_INVALID_HMCFN_ID";
217 case I40E_ERR_BACKING_PAGE_ERROR:
218 return "I40E_ERR_BACKING_PAGE_ERROR";
219 case I40E_ERR_NO_PBLCHUNKS_AVAILABLE:
220 return "I40E_ERR_NO_PBLCHUNKS_AVAILABLE";
221 case I40E_ERR_INVALID_PBLE_INDEX:
222 return "I40E_ERR_INVALID_PBLE_INDEX";
223 case I40E_ERR_INVALID_SD_INDEX:
224 return "I40E_ERR_INVALID_SD_INDEX";
225 case I40E_ERR_INVALID_PAGE_DESC_INDEX:
226 return "I40E_ERR_INVALID_PAGE_DESC_INDEX";
227 case I40E_ERR_INVALID_SD_TYPE:
228 return "I40E_ERR_INVALID_SD_TYPE";
229 case I40E_ERR_MEMCPY_FAILED:
230 return "I40E_ERR_MEMCPY_FAILED";
231 case I40E_ERR_INVALID_HMC_OBJ_INDEX:
232 return "I40E_ERR_INVALID_HMC_OBJ_INDEX";
233 case I40E_ERR_INVALID_HMC_OBJ_COUNT:
234 return "I40E_ERR_INVALID_HMC_OBJ_COUNT";
235 case I40E_ERR_INVALID_SRQ_ARM_LIMIT:
236 return "I40E_ERR_INVALID_SRQ_ARM_LIMIT";
237 case I40E_ERR_SRQ_ENABLED:
238 return "I40E_ERR_SRQ_ENABLED";
239 case I40E_ERR_ADMIN_QUEUE_ERROR:
240 return "I40E_ERR_ADMIN_QUEUE_ERROR";
241 case I40E_ERR_ADMIN_QUEUE_TIMEOUT:
242 return "I40E_ERR_ADMIN_QUEUE_TIMEOUT";
243 case I40E_ERR_BUF_TOO_SHORT:
244 return "I40E_ERR_BUF_TOO_SHORT";
245 case I40E_ERR_ADMIN_QUEUE_FULL:
246 return "I40E_ERR_ADMIN_QUEUE_FULL";
247 case I40E_ERR_ADMIN_QUEUE_NO_WORK:
248 return "I40E_ERR_ADMIN_QUEUE_NO_WORK";
249 case I40E_ERR_BAD_IWARP_CQE:
250 return "I40E_ERR_BAD_IWARP_CQE";
251 case I40E_ERR_NVM_BLANK_MODE:
252 return "I40E_ERR_NVM_BLANK_MODE";
253 case I40E_ERR_NOT_IMPLEMENTED:
254 return "I40E_ERR_NOT_IMPLEMENTED";
255 case I40E_ERR_PE_DOORBELL_NOT_ENABLED:
256 return "I40E_ERR_PE_DOORBELL_NOT_ENABLED";
257 case I40E_ERR_DIAG_TEST_FAILED:
258 return "I40E_ERR_DIAG_TEST_FAILED";
259 case I40E_ERR_NOT_READY:
260 return "I40E_ERR_NOT_READY";
261 case I40E_NOT_SUPPORTED:
262 return "I40E_NOT_SUPPORTED";
263 case I40E_ERR_FIRMWARE_API_VERSION:
264 return "I40E_ERR_FIRMWARE_API_VERSION";
265 case I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR:
266 return "I40E_ERR_ADMIN_QUEUE_CRITICAL_ERROR";
267 }
268
269 snprintf(hw->err_str, sizeof(hw->err_str), "%d", stat_err);
270 return hw->err_str;
271}
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281
282
283void i40e_debug_aq(struct i40e_hw *hw, enum i40e_debug_mask mask, void *desc,
284 void *buffer, u16 buf_len)
285{
286 struct i40e_aq_desc *aq_desc = (struct i40e_aq_desc *)desc;
287 u32 effective_mask = hw->debug_mask & mask;
288 char prefix[27];
289 u16 len;
290 u8 *buf = (u8 *)buffer;
291
292 if (!effective_mask || !desc)
293 return;
294
295 len = le16_to_cpu(aq_desc->datalen);
296
297 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
298 "AQ CMD: opcode 0x%04X, flags 0x%04X, datalen 0x%04X, retval 0x%04X\n",
299 le16_to_cpu(aq_desc->opcode),
300 le16_to_cpu(aq_desc->flags),
301 le16_to_cpu(aq_desc->datalen),
302 le16_to_cpu(aq_desc->retval));
303 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
304 "\tcookie (h,l) 0x%08X 0x%08X\n",
305 le32_to_cpu(aq_desc->cookie_high),
306 le32_to_cpu(aq_desc->cookie_low));
307 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
308 "\tparam (0,1) 0x%08X 0x%08X\n",
309 le32_to_cpu(aq_desc->params.internal.param0),
310 le32_to_cpu(aq_desc->params.internal.param1));
311 i40e_debug(hw, mask & I40E_DEBUG_AQ_DESCRIPTOR,
312 "\taddr (h,l) 0x%08X 0x%08X\n",
313 le32_to_cpu(aq_desc->params.external.addr_high),
314 le32_to_cpu(aq_desc->params.external.addr_low));
315
316 if (buffer && buf_len != 0 && len != 0 &&
317 (effective_mask & I40E_DEBUG_AQ_DESC_BUFFER)) {
318 i40e_debug(hw, mask, "AQ CMD Buffer:\n");
319 if (buf_len < len)
320 len = buf_len;
321
322 snprintf(prefix, sizeof(prefix),
323 "i40e %02x:%02x.%x: \t0x",
324 hw->bus.bus_id,
325 hw->bus.device,
326 hw->bus.func);
327
328 print_hex_dump(KERN_INFO, prefix, DUMP_PREFIX_OFFSET,
329 16, 1, buf, len, false);
330 }
331}
332
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338
339bool i40e_check_asq_alive(struct i40e_hw *hw)
340{
341 if (hw->aq.asq.len)
342 return !!(rd32(hw, hw->aq.asq.len) &
343 I40E_PF_ATQLEN_ATQENABLE_MASK);
344 else
345 return false;
346}
347
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355
356i40e_status i40e_aq_queue_shutdown(struct i40e_hw *hw,
357 bool unloading)
358{
359 struct i40e_aq_desc desc;
360 struct i40e_aqc_queue_shutdown *cmd =
361 (struct i40e_aqc_queue_shutdown *)&desc.params.raw;
362 i40e_status status;
363
364 i40e_fill_default_direct_cmd_desc(&desc,
365 i40e_aqc_opc_queue_shutdown);
366
367 if (unloading)
368 cmd->driver_unloading = cpu_to_le32(I40E_AQ_DRIVER_UNLOADING);
369 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
370
371 return status;
372}
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385static i40e_status i40e_aq_get_set_rss_lut(struct i40e_hw *hw,
386 u16 vsi_id, bool pf_lut,
387 u8 *lut, u16 lut_size,
388 bool set)
389{
390 i40e_status status;
391 struct i40e_aq_desc desc;
392 struct i40e_aqc_get_set_rss_lut *cmd_resp =
393 (struct i40e_aqc_get_set_rss_lut *)&desc.params.raw;
394
395 if (set)
396 i40e_fill_default_direct_cmd_desc(&desc,
397 i40e_aqc_opc_set_rss_lut);
398 else
399 i40e_fill_default_direct_cmd_desc(&desc,
400 i40e_aqc_opc_get_rss_lut);
401
402
403 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
404 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
405
406 cmd_resp->vsi_id =
407 cpu_to_le16((u16)((vsi_id <<
408 I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) &
409 I40E_AQC_SET_RSS_LUT_VSI_ID_MASK));
410 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_LUT_VSI_VALID);
411
412 if (pf_lut)
413 cmd_resp->flags |= cpu_to_le16((u16)
414 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF <<
415 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
416 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
417 else
418 cmd_resp->flags |= cpu_to_le16((u16)
419 ((I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI <<
420 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) &
421 I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK));
422
423 status = i40e_asq_send_command(hw, &desc, lut, lut_size, NULL);
424
425 return status;
426}
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437
438i40e_status i40e_aq_get_rss_lut(struct i40e_hw *hw, u16 vsi_id,
439 bool pf_lut, u8 *lut, u16 lut_size)
440{
441 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size,
442 false);
443}
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455i40e_status i40e_aq_set_rss_lut(struct i40e_hw *hw, u16 vsi_id,
456 bool pf_lut, u8 *lut, u16 lut_size)
457{
458 return i40e_aq_get_set_rss_lut(hw, vsi_id, pf_lut, lut, lut_size, true);
459}
460
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469
470static i40e_status i40e_aq_get_set_rss_key(struct i40e_hw *hw,
471 u16 vsi_id,
472 struct i40e_aqc_get_set_rss_key_data *key,
473 bool set)
474{
475 i40e_status status;
476 struct i40e_aq_desc desc;
477 struct i40e_aqc_get_set_rss_key *cmd_resp =
478 (struct i40e_aqc_get_set_rss_key *)&desc.params.raw;
479 u16 key_size = sizeof(struct i40e_aqc_get_set_rss_key_data);
480
481 if (set)
482 i40e_fill_default_direct_cmd_desc(&desc,
483 i40e_aqc_opc_set_rss_key);
484 else
485 i40e_fill_default_direct_cmd_desc(&desc,
486 i40e_aqc_opc_get_rss_key);
487
488
489 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
490 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
491
492 cmd_resp->vsi_id =
493 cpu_to_le16((u16)((vsi_id <<
494 I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) &
495 I40E_AQC_SET_RSS_KEY_VSI_ID_MASK));
496 cmd_resp->vsi_id |= cpu_to_le16((u16)I40E_AQC_SET_RSS_KEY_VSI_VALID);
497
498 status = i40e_asq_send_command(hw, &desc, key, key_size, NULL);
499
500 return status;
501}
502
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509
510i40e_status i40e_aq_get_rss_key(struct i40e_hw *hw,
511 u16 vsi_id,
512 struct i40e_aqc_get_set_rss_key_data *key)
513{
514 return i40e_aq_get_set_rss_key(hw, vsi_id, key, false);
515}
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525i40e_status i40e_aq_set_rss_key(struct i40e_hw *hw,
526 u16 vsi_id,
527 struct i40e_aqc_get_set_rss_key_data *key)
528{
529 return i40e_aq_get_set_rss_key(hw, vsi_id, key, true);
530}
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555
556#define I40E_PTT(PTYPE, OUTER_IP, OUTER_IP_VER, OUTER_FRAG, T, TE, TEF, I, PL)\
557 [PTYPE] = { \
558 1, \
559 I40E_RX_PTYPE_OUTER_##OUTER_IP, \
560 I40E_RX_PTYPE_OUTER_##OUTER_IP_VER, \
561 I40E_RX_PTYPE_##OUTER_FRAG, \
562 I40E_RX_PTYPE_TUNNEL_##T, \
563 I40E_RX_PTYPE_TUNNEL_END_##TE, \
564 I40E_RX_PTYPE_##TEF, \
565 I40E_RX_PTYPE_INNER_PROT_##I, \
566 I40E_RX_PTYPE_PAYLOAD_LAYER_##PL }
567
568#define I40E_PTT_UNUSED_ENTRY(PTYPE) [PTYPE] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
569
570
571#define I40E_RX_PTYPE_NOF I40E_RX_PTYPE_NOT_FRAG
572#define I40E_RX_PTYPE_FRG I40E_RX_PTYPE_FRAG
573#define I40E_RX_PTYPE_INNER_PROT_TS I40E_RX_PTYPE_INNER_PROT_TIMESYNC
574
575
576struct i40e_rx_ptype_decoded i40e_ptype_lookup[BIT(8)] = {
577
578 I40E_PTT_UNUSED_ENTRY(0),
579 I40E_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
580 I40E_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
581 I40E_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
582 I40E_PTT_UNUSED_ENTRY(4),
583 I40E_PTT_UNUSED_ENTRY(5),
584 I40E_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
585 I40E_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
586 I40E_PTT_UNUSED_ENTRY(8),
587 I40E_PTT_UNUSED_ENTRY(9),
588 I40E_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
589 I40E_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
590 I40E_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
591 I40E_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
592 I40E_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
593 I40E_PTT(15, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
594 I40E_PTT(16, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
595 I40E_PTT(17, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
596 I40E_PTT(18, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
597 I40E_PTT(19, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
598 I40E_PTT(20, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
599 I40E_PTT(21, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
600
601
602 I40E_PTT(22, IP, IPV4, FRG, NONE, NONE, NOF, NONE, PAY3),
603 I40E_PTT(23, IP, IPV4, NOF, NONE, NONE, NOF, NONE, PAY3),
604 I40E_PTT(24, IP, IPV4, NOF, NONE, NONE, NOF, UDP, PAY4),
605 I40E_PTT_UNUSED_ENTRY(25),
606 I40E_PTT(26, IP, IPV4, NOF, NONE, NONE, NOF, TCP, PAY4),
607 I40E_PTT(27, IP, IPV4, NOF, NONE, NONE, NOF, SCTP, PAY4),
608 I40E_PTT(28, IP, IPV4, NOF, NONE, NONE, NOF, ICMP, PAY4),
609
610
611 I40E_PTT(29, IP, IPV4, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
612 I40E_PTT(30, IP, IPV4, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
613 I40E_PTT(31, IP, IPV4, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
614 I40E_PTT_UNUSED_ENTRY(32),
615 I40E_PTT(33, IP, IPV4, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
616 I40E_PTT(34, IP, IPV4, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
617 I40E_PTT(35, IP, IPV4, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
618
619
620 I40E_PTT(36, IP, IPV4, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
621 I40E_PTT(37, IP, IPV4, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
622 I40E_PTT(38, IP, IPV4, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
623 I40E_PTT_UNUSED_ENTRY(39),
624 I40E_PTT(40, IP, IPV4, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
625 I40E_PTT(41, IP, IPV4, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
626 I40E_PTT(42, IP, IPV4, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
627
628
629 I40E_PTT(43, IP, IPV4, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
630
631
632 I40E_PTT(44, IP, IPV4, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
633 I40E_PTT(45, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
634 I40E_PTT(46, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
635 I40E_PTT_UNUSED_ENTRY(47),
636 I40E_PTT(48, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
637 I40E_PTT(49, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
638 I40E_PTT(50, IP, IPV4, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
639
640
641 I40E_PTT(51, IP, IPV4, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
642 I40E_PTT(52, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
643 I40E_PTT(53, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
644 I40E_PTT_UNUSED_ENTRY(54),
645 I40E_PTT(55, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
646 I40E_PTT(56, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
647 I40E_PTT(57, IP, IPV4, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
648
649
650 I40E_PTT(58, IP, IPV4, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
651
652
653 I40E_PTT(59, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
654 I40E_PTT(60, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
655 I40E_PTT(61, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
656 I40E_PTT_UNUSED_ENTRY(62),
657 I40E_PTT(63, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
658 I40E_PTT(64, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
659 I40E_PTT(65, IP, IPV4, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
660
661
662 I40E_PTT(66, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
663 I40E_PTT(67, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
664 I40E_PTT(68, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
665 I40E_PTT_UNUSED_ENTRY(69),
666 I40E_PTT(70, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
667 I40E_PTT(71, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
668 I40E_PTT(72, IP, IPV4, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
669
670
671 I40E_PTT(73, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
672
673
674 I40E_PTT(74, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
675 I40E_PTT(75, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
676 I40E_PTT(76, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
677 I40E_PTT_UNUSED_ENTRY(77),
678 I40E_PTT(78, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
679 I40E_PTT(79, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
680 I40E_PTT(80, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
681
682
683 I40E_PTT(81, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
684 I40E_PTT(82, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
685 I40E_PTT(83, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
686 I40E_PTT_UNUSED_ENTRY(84),
687 I40E_PTT(85, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
688 I40E_PTT(86, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
689 I40E_PTT(87, IP, IPV4, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
690
691
692 I40E_PTT(88, IP, IPV6, FRG, NONE, NONE, NOF, NONE, PAY3),
693 I40E_PTT(89, IP, IPV6, NOF, NONE, NONE, NOF, NONE, PAY3),
694 I40E_PTT(90, IP, IPV6, NOF, NONE, NONE, NOF, UDP, PAY4),
695 I40E_PTT_UNUSED_ENTRY(91),
696 I40E_PTT(92, IP, IPV6, NOF, NONE, NONE, NOF, TCP, PAY4),
697 I40E_PTT(93, IP, IPV6, NOF, NONE, NONE, NOF, SCTP, PAY4),
698 I40E_PTT(94, IP, IPV6, NOF, NONE, NONE, NOF, ICMP, PAY4),
699
700
701 I40E_PTT(95, IP, IPV6, NOF, IP_IP, IPV4, FRG, NONE, PAY3),
702 I40E_PTT(96, IP, IPV6, NOF, IP_IP, IPV4, NOF, NONE, PAY3),
703 I40E_PTT(97, IP, IPV6, NOF, IP_IP, IPV4, NOF, UDP, PAY4),
704 I40E_PTT_UNUSED_ENTRY(98),
705 I40E_PTT(99, IP, IPV6, NOF, IP_IP, IPV4, NOF, TCP, PAY4),
706 I40E_PTT(100, IP, IPV6, NOF, IP_IP, IPV4, NOF, SCTP, PAY4),
707 I40E_PTT(101, IP, IPV6, NOF, IP_IP, IPV4, NOF, ICMP, PAY4),
708
709
710 I40E_PTT(102, IP, IPV6, NOF, IP_IP, IPV6, FRG, NONE, PAY3),
711 I40E_PTT(103, IP, IPV6, NOF, IP_IP, IPV6, NOF, NONE, PAY3),
712 I40E_PTT(104, IP, IPV6, NOF, IP_IP, IPV6, NOF, UDP, PAY4),
713 I40E_PTT_UNUSED_ENTRY(105),
714 I40E_PTT(106, IP, IPV6, NOF, IP_IP, IPV6, NOF, TCP, PAY4),
715 I40E_PTT(107, IP, IPV6, NOF, IP_IP, IPV6, NOF, SCTP, PAY4),
716 I40E_PTT(108, IP, IPV6, NOF, IP_IP, IPV6, NOF, ICMP, PAY4),
717
718
719 I40E_PTT(109, IP, IPV6, NOF, IP_GRENAT, NONE, NOF, NONE, PAY3),
720
721
722 I40E_PTT(110, IP, IPV6, NOF, IP_GRENAT, IPV4, FRG, NONE, PAY3),
723 I40E_PTT(111, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, NONE, PAY3),
724 I40E_PTT(112, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, UDP, PAY4),
725 I40E_PTT_UNUSED_ENTRY(113),
726 I40E_PTT(114, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, TCP, PAY4),
727 I40E_PTT(115, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, SCTP, PAY4),
728 I40E_PTT(116, IP, IPV6, NOF, IP_GRENAT, IPV4, NOF, ICMP, PAY4),
729
730
731 I40E_PTT(117, IP, IPV6, NOF, IP_GRENAT, IPV6, FRG, NONE, PAY3),
732 I40E_PTT(118, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, NONE, PAY3),
733 I40E_PTT(119, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, UDP, PAY4),
734 I40E_PTT_UNUSED_ENTRY(120),
735 I40E_PTT(121, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, TCP, PAY4),
736 I40E_PTT(122, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, SCTP, PAY4),
737 I40E_PTT(123, IP, IPV6, NOF, IP_GRENAT, IPV6, NOF, ICMP, PAY4),
738
739
740 I40E_PTT(124, IP, IPV6, NOF, IP_GRENAT_MAC, NONE, NOF, NONE, PAY3),
741
742
743 I40E_PTT(125, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, FRG, NONE, PAY3),
744 I40E_PTT(126, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, NONE, PAY3),
745 I40E_PTT(127, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, UDP, PAY4),
746 I40E_PTT_UNUSED_ENTRY(128),
747 I40E_PTT(129, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, TCP, PAY4),
748 I40E_PTT(130, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, SCTP, PAY4),
749 I40E_PTT(131, IP, IPV6, NOF, IP_GRENAT_MAC, IPV4, NOF, ICMP, PAY4),
750
751
752 I40E_PTT(132, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, FRG, NONE, PAY3),
753 I40E_PTT(133, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, NONE, PAY3),
754 I40E_PTT(134, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, UDP, PAY4),
755 I40E_PTT_UNUSED_ENTRY(135),
756 I40E_PTT(136, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, TCP, PAY4),
757 I40E_PTT(137, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, SCTP, PAY4),
758 I40E_PTT(138, IP, IPV6, NOF, IP_GRENAT_MAC, IPV6, NOF, ICMP, PAY4),
759
760
761 I40E_PTT(139, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, NONE, NOF, NONE, PAY3),
762
763
764 I40E_PTT(140, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, FRG, NONE, PAY3),
765 I40E_PTT(141, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, NONE, PAY3),
766 I40E_PTT(142, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, UDP, PAY4),
767 I40E_PTT_UNUSED_ENTRY(143),
768 I40E_PTT(144, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, TCP, PAY4),
769 I40E_PTT(145, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, SCTP, PAY4),
770 I40E_PTT(146, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV4, NOF, ICMP, PAY4),
771
772
773 I40E_PTT(147, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, FRG, NONE, PAY3),
774 I40E_PTT(148, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, NONE, PAY3),
775 I40E_PTT(149, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, UDP, PAY4),
776 I40E_PTT_UNUSED_ENTRY(150),
777 I40E_PTT(151, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, TCP, PAY4),
778 I40E_PTT(152, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, SCTP, PAY4),
779 I40E_PTT(153, IP, IPV6, NOF, IP_GRENAT_MAC_VLAN, IPV6, NOF, ICMP, PAY4),
780
781
782 [154 ... 255] = { 0, 0, 0, 0, 0, 0, 0, 0, 0 }
783};
784
785
786
787
788
789
790
791
792
793
794
795
796
797i40e_status i40e_init_shared_code(struct i40e_hw *hw)
798{
799 i40e_status status = 0;
800 u32 port, ari, func_rid;
801
802 i40e_set_mac_type(hw);
803
804 switch (hw->mac.type) {
805 case I40E_MAC_XL710:
806 case I40E_MAC_X722:
807 break;
808 default:
809 return I40E_ERR_DEVICE_NOT_SUPPORTED;
810 }
811
812 hw->phy.get_link_info = true;
813
814
815 port = (rd32(hw, I40E_PFGEN_PORTNUM) & I40E_PFGEN_PORTNUM_PORT_NUM_MASK)
816 >> I40E_PFGEN_PORTNUM_PORT_NUM_SHIFT;
817 hw->port = (u8)port;
818 ari = (rd32(hw, I40E_GLPCI_CAPSUP) & I40E_GLPCI_CAPSUP_ARI_EN_MASK) >>
819 I40E_GLPCI_CAPSUP_ARI_EN_SHIFT;
820 func_rid = rd32(hw, I40E_PF_FUNC_RID);
821 if (ari)
822 hw->pf_id = (u8)(func_rid & 0xff);
823 else
824 hw->pf_id = (u8)(func_rid & 0x7);
825
826 status = i40e_init_nvm(hw);
827 return status;
828}
829
830
831
832
833
834
835
836
837static i40e_status i40e_aq_mac_address_read(struct i40e_hw *hw,
838 u16 *flags,
839 struct i40e_aqc_mac_address_read_data *addrs,
840 struct i40e_asq_cmd_details *cmd_details)
841{
842 struct i40e_aq_desc desc;
843 struct i40e_aqc_mac_address_read *cmd_data =
844 (struct i40e_aqc_mac_address_read *)&desc.params.raw;
845 i40e_status status;
846
847 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_mac_address_read);
848 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF);
849
850 status = i40e_asq_send_command(hw, &desc, addrs,
851 sizeof(*addrs), cmd_details);
852 *flags = le16_to_cpu(cmd_data->command_flags);
853
854 return status;
855}
856
857
858
859
860
861
862
863
864i40e_status i40e_aq_mac_address_write(struct i40e_hw *hw,
865 u16 flags, u8 *mac_addr,
866 struct i40e_asq_cmd_details *cmd_details)
867{
868 struct i40e_aq_desc desc;
869 struct i40e_aqc_mac_address_write *cmd_data =
870 (struct i40e_aqc_mac_address_write *)&desc.params.raw;
871 i40e_status status;
872
873 i40e_fill_default_direct_cmd_desc(&desc,
874 i40e_aqc_opc_mac_address_write);
875 cmd_data->command_flags = cpu_to_le16(flags);
876 cmd_data->mac_sah = cpu_to_le16((u16)mac_addr[0] << 8 | mac_addr[1]);
877 cmd_data->mac_sal = cpu_to_le32(((u32)mac_addr[2] << 24) |
878 ((u32)mac_addr[3] << 16) |
879 ((u32)mac_addr[4] << 8) |
880 mac_addr[5]);
881
882 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
883
884 return status;
885}
886
887
888
889
890
891
892
893
894i40e_status i40e_get_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
895{
896 struct i40e_aqc_mac_address_read_data addrs;
897 i40e_status status;
898 u16 flags = 0;
899
900 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
901
902 if (flags & I40E_AQC_LAN_ADDR_VALID)
903 ether_addr_copy(mac_addr, addrs.pf_lan_mac);
904
905 return status;
906}
907
908
909
910
911
912
913
914
915i40e_status i40e_get_port_mac_addr(struct i40e_hw *hw, u8 *mac_addr)
916{
917 struct i40e_aqc_mac_address_read_data addrs;
918 i40e_status status;
919 u16 flags = 0;
920
921 status = i40e_aq_mac_address_read(hw, &flags, &addrs, NULL);
922 if (status)
923 return status;
924
925 if (flags & I40E_AQC_PORT_ADDR_VALID)
926 ether_addr_copy(mac_addr, addrs.port_mac);
927 else
928 status = I40E_ERR_INVALID_MAC_ADDR;
929
930 return status;
931}
932
933
934
935
936
937
938
939
940
941
942void i40e_pre_tx_queue_cfg(struct i40e_hw *hw, u32 queue, bool enable)
943{
944 u32 abs_queue_idx = hw->func_caps.base_queue + queue;
945 u32 reg_block = 0;
946 u32 reg_val;
947
948 if (abs_queue_idx >= 128) {
949 reg_block = abs_queue_idx / 128;
950 abs_queue_idx %= 128;
951 }
952
953 reg_val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
954 reg_val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
955 reg_val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
956
957 if (enable)
958 reg_val |= I40E_GLLAN_TXPRE_QDIS_CLEAR_QDIS_MASK;
959 else
960 reg_val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
961
962 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), reg_val);
963}
964
965
966
967
968
969
970
971
972
973i40e_status i40e_read_pba_string(struct i40e_hw *hw, u8 *pba_num,
974 u32 pba_num_size)
975{
976 i40e_status status = 0;
977 u16 pba_word = 0;
978 u16 pba_size = 0;
979 u16 pba_ptr = 0;
980 u16 i = 0;
981
982 status = i40e_read_nvm_word(hw, I40E_SR_PBA_FLAGS, &pba_word);
983 if (status || (pba_word != 0xFAFA)) {
984 hw_dbg(hw, "Failed to read PBA flags or flag is invalid.\n");
985 return status;
986 }
987
988 status = i40e_read_nvm_word(hw, I40E_SR_PBA_BLOCK_PTR, &pba_ptr);
989 if (status) {
990 hw_dbg(hw, "Failed to read PBA Block pointer.\n");
991 return status;
992 }
993
994 status = i40e_read_nvm_word(hw, pba_ptr, &pba_size);
995 if (status) {
996 hw_dbg(hw, "Failed to read PBA Block size.\n");
997 return status;
998 }
999
1000
1001
1002
1003 pba_size--;
1004 if (pba_num_size < (((u32)pba_size * 2) + 1)) {
1005 hw_dbg(hw, "Buffer too small for PBA data.\n");
1006 return I40E_ERR_PARAM;
1007 }
1008
1009 for (i = 0; i < pba_size; i++) {
1010 status = i40e_read_nvm_word(hw, (pba_ptr + 1) + i, &pba_word);
1011 if (status) {
1012 hw_dbg(hw, "Failed to read PBA Block word %d.\n", i);
1013 return status;
1014 }
1015
1016 pba_num[(i * 2)] = (pba_word >> 8) & 0xFF;
1017 pba_num[(i * 2) + 1] = pba_word & 0xFF;
1018 }
1019 pba_num[(pba_size * 2)] = '\0';
1020
1021 return status;
1022}
1023
1024
1025
1026
1027
1028static enum i40e_media_type i40e_get_media_type(struct i40e_hw *hw)
1029{
1030 enum i40e_media_type media;
1031
1032 switch (hw->phy.link_info.phy_type) {
1033 case I40E_PHY_TYPE_10GBASE_SR:
1034 case I40E_PHY_TYPE_10GBASE_LR:
1035 case I40E_PHY_TYPE_1000BASE_SX:
1036 case I40E_PHY_TYPE_1000BASE_LX:
1037 case I40E_PHY_TYPE_40GBASE_SR4:
1038 case I40E_PHY_TYPE_40GBASE_LR4:
1039 case I40E_PHY_TYPE_25GBASE_LR:
1040 case I40E_PHY_TYPE_25GBASE_SR:
1041 media = I40E_MEDIA_TYPE_FIBER;
1042 break;
1043 case I40E_PHY_TYPE_100BASE_TX:
1044 case I40E_PHY_TYPE_1000BASE_T:
1045 case I40E_PHY_TYPE_2_5GBASE_T_LINK_STATUS:
1046 case I40E_PHY_TYPE_5GBASE_T_LINK_STATUS:
1047 case I40E_PHY_TYPE_10GBASE_T:
1048 media = I40E_MEDIA_TYPE_BASET;
1049 break;
1050 case I40E_PHY_TYPE_10GBASE_CR1_CU:
1051 case I40E_PHY_TYPE_40GBASE_CR4_CU:
1052 case I40E_PHY_TYPE_10GBASE_CR1:
1053 case I40E_PHY_TYPE_40GBASE_CR4:
1054 case I40E_PHY_TYPE_10GBASE_SFPP_CU:
1055 case I40E_PHY_TYPE_40GBASE_AOC:
1056 case I40E_PHY_TYPE_10GBASE_AOC:
1057 case I40E_PHY_TYPE_25GBASE_CR:
1058 case I40E_PHY_TYPE_25GBASE_AOC:
1059 case I40E_PHY_TYPE_25GBASE_ACC:
1060 media = I40E_MEDIA_TYPE_DA;
1061 break;
1062 case I40E_PHY_TYPE_1000BASE_KX:
1063 case I40E_PHY_TYPE_10GBASE_KX4:
1064 case I40E_PHY_TYPE_10GBASE_KR:
1065 case I40E_PHY_TYPE_40GBASE_KR4:
1066 case I40E_PHY_TYPE_20GBASE_KR2:
1067 case I40E_PHY_TYPE_25GBASE_KR:
1068 media = I40E_MEDIA_TYPE_BACKPLANE;
1069 break;
1070 case I40E_PHY_TYPE_SGMII:
1071 case I40E_PHY_TYPE_XAUI:
1072 case I40E_PHY_TYPE_XFI:
1073 case I40E_PHY_TYPE_XLAUI:
1074 case I40E_PHY_TYPE_XLPPI:
1075 default:
1076 media = I40E_MEDIA_TYPE_UNKNOWN;
1077 break;
1078 }
1079
1080 return media;
1081}
1082
1083
1084
1085
1086
1087
1088static i40e_status i40e_poll_globr(struct i40e_hw *hw,
1089 u32 retry_limit)
1090{
1091 u32 cnt, reg = 0;
1092
1093 for (cnt = 0; cnt < retry_limit; cnt++) {
1094 reg = rd32(hw, I40E_GLGEN_RSTAT);
1095 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1096 return 0;
1097 msleep(100);
1098 }
1099
1100 hw_dbg(hw, "Global reset failed.\n");
1101 hw_dbg(hw, "I40E_GLGEN_RSTAT = 0x%x\n", reg);
1102
1103 return I40E_ERR_RESET_FAILED;
1104}
1105
1106#define I40E_PF_RESET_WAIT_COUNT_A0 200
1107#define I40E_PF_RESET_WAIT_COUNT 200
1108
1109
1110
1111
1112
1113
1114
1115i40e_status i40e_pf_reset(struct i40e_hw *hw)
1116{
1117 u32 cnt = 0;
1118 u32 cnt1 = 0;
1119 u32 reg = 0;
1120 u32 grst_del;
1121
1122
1123
1124
1125
1126 grst_del = (rd32(hw, I40E_GLGEN_RSTCTL) &
1127 I40E_GLGEN_RSTCTL_GRSTDEL_MASK) >>
1128 I40E_GLGEN_RSTCTL_GRSTDEL_SHIFT;
1129
1130
1131
1132
1133 grst_del = grst_del * 20;
1134
1135 for (cnt = 0; cnt < grst_del; cnt++) {
1136 reg = rd32(hw, I40E_GLGEN_RSTAT);
1137 if (!(reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK))
1138 break;
1139 msleep(100);
1140 }
1141 if (reg & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1142 hw_dbg(hw, "Global reset polling failed to complete.\n");
1143 return I40E_ERR_RESET_FAILED;
1144 }
1145
1146
1147 for (cnt1 = 0; cnt1 < I40E_PF_RESET_WAIT_COUNT; cnt1++) {
1148 reg = rd32(hw, I40E_GLNVM_ULD);
1149 reg &= (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1150 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK);
1151 if (reg == (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1152 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK)) {
1153 hw_dbg(hw, "Core and Global modules ready %d\n", cnt1);
1154 break;
1155 }
1156 usleep_range(10000, 20000);
1157 }
1158 if (!(reg & (I40E_GLNVM_ULD_CONF_CORE_DONE_MASK |
1159 I40E_GLNVM_ULD_CONF_GLOBAL_DONE_MASK))) {
1160 hw_dbg(hw, "wait for FW Reset complete timedout\n");
1161 hw_dbg(hw, "I40E_GLNVM_ULD = 0x%x\n", reg);
1162 return I40E_ERR_RESET_FAILED;
1163 }
1164
1165
1166
1167
1168 if (!cnt) {
1169 u32 reg2 = 0;
1170 if (hw->revision_id == 0)
1171 cnt = I40E_PF_RESET_WAIT_COUNT_A0;
1172 else
1173 cnt = I40E_PF_RESET_WAIT_COUNT;
1174 reg = rd32(hw, I40E_PFGEN_CTRL);
1175 wr32(hw, I40E_PFGEN_CTRL,
1176 (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1177 for (; cnt; cnt--) {
1178 reg = rd32(hw, I40E_PFGEN_CTRL);
1179 if (!(reg & I40E_PFGEN_CTRL_PFSWR_MASK))
1180 break;
1181 reg2 = rd32(hw, I40E_GLGEN_RSTAT);
1182 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK)
1183 break;
1184 usleep_range(1000, 2000);
1185 }
1186 if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) {
1187 if (i40e_poll_globr(hw, grst_del))
1188 return I40E_ERR_RESET_FAILED;
1189 } else if (reg & I40E_PFGEN_CTRL_PFSWR_MASK) {
1190 hw_dbg(hw, "PF reset polling failed to complete.\n");
1191 return I40E_ERR_RESET_FAILED;
1192 }
1193 }
1194
1195 i40e_clear_pxe_mode(hw);
1196
1197 return 0;
1198}
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208void i40e_clear_hw(struct i40e_hw *hw)
1209{
1210 u32 num_queues, base_queue;
1211 u32 num_pf_int;
1212 u32 num_vf_int;
1213 u32 num_vfs;
1214 u32 i, j;
1215 u32 val;
1216 u32 eol = 0x7ff;
1217
1218
1219 val = rd32(hw, I40E_GLPCI_CNF2);
1220 num_pf_int = (val & I40E_GLPCI_CNF2_MSI_X_PF_N_MASK) >>
1221 I40E_GLPCI_CNF2_MSI_X_PF_N_SHIFT;
1222 num_vf_int = (val & I40E_GLPCI_CNF2_MSI_X_VF_N_MASK) >>
1223 I40E_GLPCI_CNF2_MSI_X_VF_N_SHIFT;
1224
1225 val = rd32(hw, I40E_PFLAN_QALLOC);
1226 base_queue = (val & I40E_PFLAN_QALLOC_FIRSTQ_MASK) >>
1227 I40E_PFLAN_QALLOC_FIRSTQ_SHIFT;
1228 j = (val & I40E_PFLAN_QALLOC_LASTQ_MASK) >>
1229 I40E_PFLAN_QALLOC_LASTQ_SHIFT;
1230 if (val & I40E_PFLAN_QALLOC_VALID_MASK)
1231 num_queues = (j - base_queue) + 1;
1232 else
1233 num_queues = 0;
1234
1235 val = rd32(hw, I40E_PF_VT_PFALLOC);
1236 i = (val & I40E_PF_VT_PFALLOC_FIRSTVF_MASK) >>
1237 I40E_PF_VT_PFALLOC_FIRSTVF_SHIFT;
1238 j = (val & I40E_PF_VT_PFALLOC_LASTVF_MASK) >>
1239 I40E_PF_VT_PFALLOC_LASTVF_SHIFT;
1240 if (val & I40E_PF_VT_PFALLOC_VALID_MASK)
1241 num_vfs = (j - i) + 1;
1242 else
1243 num_vfs = 0;
1244
1245
1246 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
1247 val = 0x3 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT;
1248 for (i = 0; i < num_pf_int - 2; i++)
1249 wr32(hw, I40E_PFINT_DYN_CTLN(i), val);
1250
1251
1252 val = eol << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1253 wr32(hw, I40E_PFINT_LNKLST0, val);
1254 for (i = 0; i < num_pf_int - 2; i++)
1255 wr32(hw, I40E_PFINT_LNKLSTN(i), val);
1256 val = eol << I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT;
1257 for (i = 0; i < num_vfs; i++)
1258 wr32(hw, I40E_VPINT_LNKLST0(i), val);
1259 for (i = 0; i < num_vf_int - 2; i++)
1260 wr32(hw, I40E_VPINT_LNKLSTN(i), val);
1261
1262
1263 for (i = 0; i < num_queues; i++) {
1264 u32 abs_queue_idx = base_queue + i;
1265 u32 reg_block = 0;
1266
1267 if (abs_queue_idx >= 128) {
1268 reg_block = abs_queue_idx / 128;
1269 abs_queue_idx %= 128;
1270 }
1271
1272 val = rd32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block));
1273 val &= ~I40E_GLLAN_TXPRE_QDIS_QINDX_MASK;
1274 val |= (abs_queue_idx << I40E_GLLAN_TXPRE_QDIS_QINDX_SHIFT);
1275 val |= I40E_GLLAN_TXPRE_QDIS_SET_QDIS_MASK;
1276
1277 wr32(hw, I40E_GLLAN_TXPRE_QDIS(reg_block), val);
1278 }
1279 udelay(400);
1280
1281
1282 for (i = 0; i < num_queues; i++) {
1283 wr32(hw, I40E_QINT_TQCTL(i), 0);
1284 wr32(hw, I40E_QTX_ENA(i), 0);
1285 wr32(hw, I40E_QINT_RQCTL(i), 0);
1286 wr32(hw, I40E_QRX_ENA(i), 0);
1287 }
1288
1289
1290 udelay(50);
1291}
1292
1293
1294
1295
1296
1297
1298
1299
1300void i40e_clear_pxe_mode(struct i40e_hw *hw)
1301{
1302 u32 reg;
1303
1304 if (i40e_check_asq_alive(hw))
1305 i40e_aq_clear_pxe_mode(hw, NULL);
1306
1307
1308 reg = rd32(hw, I40E_GLLAN_RCTL_0);
1309
1310 if (hw->revision_id == 0) {
1311
1312 wr32(hw, I40E_GLLAN_RCTL_0, (reg & (~I40E_GLLAN_RCTL_0_PXE_MODE_MASK)));
1313 } else {
1314 wr32(hw, I40E_GLLAN_RCTL_0, (reg | I40E_GLLAN_RCTL_0_PXE_MODE_MASK));
1315 }
1316}
1317
1318
1319
1320
1321
1322
1323
1324
1325static u32 i40e_led_is_mine(struct i40e_hw *hw, int idx)
1326{
1327 u32 gpio_val = 0;
1328 u32 port;
1329
1330 if (!I40E_IS_X710TL_DEVICE(hw->device_id) &&
1331 !hw->func_caps.led[idx])
1332 return 0;
1333 gpio_val = rd32(hw, I40E_GLGEN_GPIO_CTL(idx));
1334 port = (gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_MASK) >>
1335 I40E_GLGEN_GPIO_CTL_PRT_NUM_SHIFT;
1336
1337
1338
1339
1340 if ((gpio_val & I40E_GLGEN_GPIO_CTL_PRT_NUM_NA_MASK) ||
1341 (port != hw->port))
1342 return 0;
1343
1344 return gpio_val;
1345}
1346
1347#define I40E_FW_LED BIT(4)
1348#define I40E_LED_MODE_VALID (I40E_GLGEN_GPIO_CTL_LED_MODE_MASK >> \
1349 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT)
1350
1351#define I40E_LED0 22
1352
1353#define I40E_PIN_FUNC_SDP 0x0
1354#define I40E_PIN_FUNC_LED 0x1
1355
1356
1357
1358
1359
1360
1361
1362
1363
1364
1365u32 i40e_led_get(struct i40e_hw *hw)
1366{
1367 u32 mode = 0;
1368 int i;
1369
1370
1371
1372
1373 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1374 u32 gpio_val = i40e_led_is_mine(hw, i);
1375
1376 if (!gpio_val)
1377 continue;
1378
1379 mode = (gpio_val & I40E_GLGEN_GPIO_CTL_LED_MODE_MASK) >>
1380 I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT;
1381 break;
1382 }
1383
1384 return mode;
1385}
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396void i40e_led_set(struct i40e_hw *hw, u32 mode, bool blink)
1397{
1398 int i;
1399
1400 if (mode & ~I40E_LED_MODE_VALID) {
1401 hw_dbg(hw, "invalid mode passed in %X\n", mode);
1402 return;
1403 }
1404
1405
1406
1407
1408 for (i = I40E_LED0; i <= I40E_GLGEN_GPIO_CTL_MAX_INDEX; i++) {
1409 u32 gpio_val = i40e_led_is_mine(hw, i);
1410
1411 if (!gpio_val)
1412 continue;
1413
1414 if (I40E_IS_X710TL_DEVICE(hw->device_id)) {
1415 u32 pin_func = 0;
1416
1417 if (mode & I40E_FW_LED)
1418 pin_func = I40E_PIN_FUNC_SDP;
1419 else
1420 pin_func = I40E_PIN_FUNC_LED;
1421
1422 gpio_val &= ~I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK;
1423 gpio_val |= ((pin_func <<
1424 I40E_GLGEN_GPIO_CTL_PIN_FUNC_SHIFT) &
1425 I40E_GLGEN_GPIO_CTL_PIN_FUNC_MASK);
1426 }
1427 gpio_val &= ~I40E_GLGEN_GPIO_CTL_LED_MODE_MASK;
1428
1429 gpio_val |= ((mode << I40E_GLGEN_GPIO_CTL_LED_MODE_SHIFT) &
1430 I40E_GLGEN_GPIO_CTL_LED_MODE_MASK);
1431
1432 if (blink)
1433 gpio_val |= BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1434 else
1435 gpio_val &= ~BIT(I40E_GLGEN_GPIO_CTL_LED_BLINK_SHIFT);
1436
1437 wr32(hw, I40E_GLGEN_GPIO_CTL(i), gpio_val);
1438 break;
1439 }
1440}
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450
1451
1452
1453
1454i40e_status i40e_aq_get_phy_capabilities(struct i40e_hw *hw,
1455 bool qualified_modules, bool report_init,
1456 struct i40e_aq_get_phy_abilities_resp *abilities,
1457 struct i40e_asq_cmd_details *cmd_details)
1458{
1459 struct i40e_aq_desc desc;
1460 i40e_status status;
1461 u16 abilities_size = sizeof(struct i40e_aq_get_phy_abilities_resp);
1462 u16 max_delay = I40E_MAX_PHY_TIMEOUT, total_delay = 0;
1463
1464 if (!abilities)
1465 return I40E_ERR_PARAM;
1466
1467 do {
1468 i40e_fill_default_direct_cmd_desc(&desc,
1469 i40e_aqc_opc_get_phy_abilities);
1470
1471 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
1472 if (abilities_size > I40E_AQ_LARGE_BUF)
1473 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
1474
1475 if (qualified_modules)
1476 desc.params.external.param0 |=
1477 cpu_to_le32(I40E_AQ_PHY_REPORT_QUALIFIED_MODULES);
1478
1479 if (report_init)
1480 desc.params.external.param0 |=
1481 cpu_to_le32(I40E_AQ_PHY_REPORT_INITIAL_VALUES);
1482
1483 status = i40e_asq_send_command(hw, &desc, abilities,
1484 abilities_size, cmd_details);
1485
1486 switch (hw->aq.asq_last_status) {
1487 case I40E_AQ_RC_EIO:
1488 status = I40E_ERR_UNKNOWN_PHY;
1489 break;
1490 case I40E_AQ_RC_EAGAIN:
1491 usleep_range(1000, 2000);
1492 total_delay++;
1493 status = I40E_ERR_TIMEOUT;
1494 break;
1495
1496 default:
1497 break;
1498 }
1499
1500 } while ((hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN) &&
1501 (total_delay < max_delay));
1502
1503 if (status)
1504 return status;
1505
1506 if (report_init) {
1507 if (hw->mac.type == I40E_MAC_XL710 &&
1508 hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
1509 hw->aq.api_min_ver >= I40E_MINOR_VER_GET_LINK_INFO_XL710) {
1510 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
1511 } else {
1512 hw->phy.phy_types = le32_to_cpu(abilities->phy_type);
1513 hw->phy.phy_types |=
1514 ((u64)abilities->phy_type_ext << 32);
1515 }
1516 }
1517
1518 return status;
1519}
1520
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533enum i40e_status_code i40e_aq_set_phy_config(struct i40e_hw *hw,
1534 struct i40e_aq_set_phy_config *config,
1535 struct i40e_asq_cmd_details *cmd_details)
1536{
1537 struct i40e_aq_desc desc;
1538 struct i40e_aq_set_phy_config *cmd =
1539 (struct i40e_aq_set_phy_config *)&desc.params.raw;
1540 enum i40e_status_code status;
1541
1542 if (!config)
1543 return I40E_ERR_PARAM;
1544
1545 i40e_fill_default_direct_cmd_desc(&desc,
1546 i40e_aqc_opc_set_phy_config);
1547
1548 *cmd = *config;
1549
1550 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1551
1552 return status;
1553}
1554
1555static noinline_for_stack enum i40e_status_code
1556i40e_set_fc_status(struct i40e_hw *hw,
1557 struct i40e_aq_get_phy_abilities_resp *abilities,
1558 bool atomic_restart)
1559{
1560 struct i40e_aq_set_phy_config config;
1561 enum i40e_fc_mode fc_mode = hw->fc.requested_mode;
1562 u8 pause_mask = 0x0;
1563
1564 switch (fc_mode) {
1565 case I40E_FC_FULL:
1566 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1567 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1568 break;
1569 case I40E_FC_RX_PAUSE:
1570 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_RX;
1571 break;
1572 case I40E_FC_TX_PAUSE:
1573 pause_mask |= I40E_AQ_PHY_FLAG_PAUSE_TX;
1574 break;
1575 default:
1576 break;
1577 }
1578
1579 memset(&config, 0, sizeof(struct i40e_aq_set_phy_config));
1580
1581 config.abilities = abilities->abilities & ~(I40E_AQ_PHY_FLAG_PAUSE_TX) &
1582 ~(I40E_AQ_PHY_FLAG_PAUSE_RX);
1583
1584 config.abilities |= pause_mask;
1585
1586 if (config.abilities == abilities->abilities)
1587 return 0;
1588
1589
1590 if (atomic_restart)
1591 config.abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1592
1593 config.phy_type = abilities->phy_type;
1594 config.phy_type_ext = abilities->phy_type_ext;
1595 config.link_speed = abilities->link_speed;
1596 config.eee_capability = abilities->eee_capability;
1597 config.eeer = abilities->eeer_val;
1598 config.low_power_ctrl = abilities->d3_lpan;
1599 config.fec_config = abilities->fec_cfg_curr_mod_ext_info &
1600 I40E_AQ_PHY_FEC_CONFIG_MASK;
1601
1602 return i40e_aq_set_phy_config(hw, &config, NULL);
1603}
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613enum i40e_status_code i40e_set_fc(struct i40e_hw *hw, u8 *aq_failures,
1614 bool atomic_restart)
1615{
1616 struct i40e_aq_get_phy_abilities_resp abilities;
1617 enum i40e_status_code status;
1618
1619 *aq_failures = 0x0;
1620
1621
1622 status = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
1623 NULL);
1624 if (status) {
1625 *aq_failures |= I40E_SET_FC_AQ_FAIL_GET;
1626 return status;
1627 }
1628
1629 status = i40e_set_fc_status(hw, &abilities, atomic_restart);
1630 if (status)
1631 *aq_failures |= I40E_SET_FC_AQ_FAIL_SET;
1632
1633
1634 status = i40e_update_link_info(hw);
1635 if (status) {
1636
1637
1638
1639
1640 msleep(1000);
1641 status = i40e_update_link_info(hw);
1642 }
1643 if (status)
1644 *aq_failures |= I40E_SET_FC_AQ_FAIL_UPDATE;
1645
1646 return status;
1647}
1648
1649
1650
1651
1652
1653
1654
1655
1656i40e_status i40e_aq_clear_pxe_mode(struct i40e_hw *hw,
1657 struct i40e_asq_cmd_details *cmd_details)
1658{
1659 i40e_status status;
1660 struct i40e_aq_desc desc;
1661 struct i40e_aqc_clear_pxe *cmd =
1662 (struct i40e_aqc_clear_pxe *)&desc.params.raw;
1663
1664 i40e_fill_default_direct_cmd_desc(&desc,
1665 i40e_aqc_opc_clear_pxe_mode);
1666
1667 cmd->rx_cnt = 0x2;
1668
1669 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1670
1671 wr32(hw, I40E_GLLAN_RCTL_0, 0x1);
1672
1673 return status;
1674}
1675
1676
1677
1678
1679
1680
1681
1682
1683
1684i40e_status i40e_aq_set_link_restart_an(struct i40e_hw *hw,
1685 bool enable_link,
1686 struct i40e_asq_cmd_details *cmd_details)
1687{
1688 struct i40e_aq_desc desc;
1689 struct i40e_aqc_set_link_restart_an *cmd =
1690 (struct i40e_aqc_set_link_restart_an *)&desc.params.raw;
1691 i40e_status status;
1692
1693 i40e_fill_default_direct_cmd_desc(&desc,
1694 i40e_aqc_opc_set_link_restart_an);
1695
1696 cmd->command = I40E_AQ_PHY_RESTART_AN;
1697 if (enable_link)
1698 cmd->command |= I40E_AQ_PHY_LINK_ENABLE;
1699 else
1700 cmd->command &= ~I40E_AQ_PHY_LINK_ENABLE;
1701
1702 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1703
1704 return status;
1705}
1706
1707
1708
1709
1710
1711
1712
1713
1714
1715
1716i40e_status i40e_aq_get_link_info(struct i40e_hw *hw,
1717 bool enable_lse, struct i40e_link_status *link,
1718 struct i40e_asq_cmd_details *cmd_details)
1719{
1720 struct i40e_aq_desc desc;
1721 struct i40e_aqc_get_link_status *resp =
1722 (struct i40e_aqc_get_link_status *)&desc.params.raw;
1723 struct i40e_link_status *hw_link_info = &hw->phy.link_info;
1724 i40e_status status;
1725 bool tx_pause, rx_pause;
1726 u16 command_flags;
1727
1728 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_link_status);
1729
1730 if (enable_lse)
1731 command_flags = I40E_AQ_LSE_ENABLE;
1732 else
1733 command_flags = I40E_AQ_LSE_DISABLE;
1734 resp->command_flags = cpu_to_le16(command_flags);
1735
1736 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1737
1738 if (status)
1739 goto aq_get_link_info_exit;
1740
1741
1742 hw->phy.link_info_old = *hw_link_info;
1743
1744
1745 hw_link_info->phy_type = (enum i40e_aq_phy_type)resp->phy_type;
1746 hw->phy.media_type = i40e_get_media_type(hw);
1747 hw_link_info->link_speed = (enum i40e_aq_link_speed)resp->link_speed;
1748 hw_link_info->link_info = resp->link_info;
1749 hw_link_info->an_info = resp->an_info;
1750 hw_link_info->fec_info = resp->config & (I40E_AQ_CONFIG_FEC_KR_ENA |
1751 I40E_AQ_CONFIG_FEC_RS_ENA);
1752 hw_link_info->ext_info = resp->ext_info;
1753 hw_link_info->loopback = resp->loopback & I40E_AQ_LOOPBACK_MASK;
1754 hw_link_info->max_frame_size = le16_to_cpu(resp->max_frame_size);
1755 hw_link_info->pacing = resp->config & I40E_AQ_CONFIG_PACING_MASK;
1756
1757
1758 tx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_TX);
1759 rx_pause = !!(resp->an_info & I40E_AQ_LINK_PAUSE_RX);
1760 if (tx_pause & rx_pause)
1761 hw->fc.current_mode = I40E_FC_FULL;
1762 else if (tx_pause)
1763 hw->fc.current_mode = I40E_FC_TX_PAUSE;
1764 else if (rx_pause)
1765 hw->fc.current_mode = I40E_FC_RX_PAUSE;
1766 else
1767 hw->fc.current_mode = I40E_FC_NONE;
1768
1769 if (resp->config & I40E_AQ_CONFIG_CRC_ENA)
1770 hw_link_info->crc_enable = true;
1771 else
1772 hw_link_info->crc_enable = false;
1773
1774 if (resp->command_flags & cpu_to_le16(I40E_AQ_LSE_IS_ENABLED))
1775 hw_link_info->lse_enable = true;
1776 else
1777 hw_link_info->lse_enable = false;
1778
1779 if ((hw->mac.type == I40E_MAC_XL710) &&
1780 (hw->aq.fw_maj_ver < 4 || (hw->aq.fw_maj_ver == 4 &&
1781 hw->aq.fw_min_ver < 40)) && hw_link_info->phy_type == 0xE)
1782 hw_link_info->phy_type = I40E_PHY_TYPE_10GBASE_SFPP_CU;
1783
1784 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE &&
1785 hw->mac.type != I40E_MAC_X722) {
1786 __le32 tmp;
1787
1788 memcpy(&tmp, resp->link_type, sizeof(tmp));
1789 hw->phy.phy_types = le32_to_cpu(tmp);
1790 hw->phy.phy_types |= ((u64)resp->link_type_ext << 32);
1791 }
1792
1793
1794 if (link)
1795 *link = *hw_link_info;
1796
1797
1798 hw->phy.get_link_info = false;
1799
1800aq_get_link_info_exit:
1801 return status;
1802}
1803
1804
1805
1806
1807
1808
1809
1810
1811
1812i40e_status i40e_aq_set_phy_int_mask(struct i40e_hw *hw,
1813 u16 mask,
1814 struct i40e_asq_cmd_details *cmd_details)
1815{
1816 struct i40e_aq_desc desc;
1817 struct i40e_aqc_set_phy_int_mask *cmd =
1818 (struct i40e_aqc_set_phy_int_mask *)&desc.params.raw;
1819 i40e_status status;
1820
1821 i40e_fill_default_direct_cmd_desc(&desc,
1822 i40e_aqc_opc_set_phy_int_mask);
1823
1824 cmd->event_mask = cpu_to_le16(mask);
1825
1826 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1827
1828 return status;
1829}
1830
1831
1832
1833
1834
1835
1836
1837
1838
1839i40e_status i40e_aq_set_phy_debug(struct i40e_hw *hw, u8 cmd_flags,
1840 struct i40e_asq_cmd_details *cmd_details)
1841{
1842 struct i40e_aq_desc desc;
1843 struct i40e_aqc_set_phy_debug *cmd =
1844 (struct i40e_aqc_set_phy_debug *)&desc.params.raw;
1845 i40e_status status;
1846
1847 i40e_fill_default_direct_cmd_desc(&desc,
1848 i40e_aqc_opc_set_phy_debug);
1849
1850 cmd->command_flags = cmd_flags;
1851
1852 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1853
1854 return status;
1855}
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865static bool i40e_is_aq_api_ver_ge(struct i40e_adminq_info *aq, u16 maj,
1866 u16 min)
1867{
1868 return (aq->api_maj_ver > maj ||
1869 (aq->api_maj_ver == maj && aq->api_min_ver >= min));
1870}
1871
1872
1873
1874
1875
1876
1877
1878
1879
1880i40e_status i40e_aq_add_vsi(struct i40e_hw *hw,
1881 struct i40e_vsi_context *vsi_ctx,
1882 struct i40e_asq_cmd_details *cmd_details)
1883{
1884 struct i40e_aq_desc desc;
1885 struct i40e_aqc_add_get_update_vsi *cmd =
1886 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
1887 struct i40e_aqc_add_get_update_vsi_completion *resp =
1888 (struct i40e_aqc_add_get_update_vsi_completion *)
1889 &desc.params.raw;
1890 i40e_status status;
1891
1892 i40e_fill_default_direct_cmd_desc(&desc,
1893 i40e_aqc_opc_add_vsi);
1894
1895 cmd->uplink_seid = cpu_to_le16(vsi_ctx->uplink_seid);
1896 cmd->connection_type = vsi_ctx->connection_type;
1897 cmd->vf_id = vsi_ctx->vf_num;
1898 cmd->vsi_flags = cpu_to_le16(vsi_ctx->flags);
1899
1900 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
1901
1902 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
1903 sizeof(vsi_ctx->info), cmd_details);
1904
1905 if (status)
1906 goto aq_add_vsi_exit;
1907
1908 vsi_ctx->seid = le16_to_cpu(resp->seid);
1909 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
1910 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
1911 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
1912
1913aq_add_vsi_exit:
1914 return status;
1915}
1916
1917
1918
1919
1920
1921
1922
1923i40e_status i40e_aq_set_default_vsi(struct i40e_hw *hw,
1924 u16 seid,
1925 struct i40e_asq_cmd_details *cmd_details)
1926{
1927 struct i40e_aq_desc desc;
1928 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1929 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1930 &desc.params.raw;
1931 i40e_status status;
1932
1933 i40e_fill_default_direct_cmd_desc(&desc,
1934 i40e_aqc_opc_set_vsi_promiscuous_modes);
1935
1936 cmd->promiscuous_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1937 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1938 cmd->seid = cpu_to_le16(seid);
1939
1940 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1941
1942 return status;
1943}
1944
1945
1946
1947
1948
1949
1950
1951i40e_status i40e_aq_clear_default_vsi(struct i40e_hw *hw,
1952 u16 seid,
1953 struct i40e_asq_cmd_details *cmd_details)
1954{
1955 struct i40e_aq_desc desc;
1956 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1957 (struct i40e_aqc_set_vsi_promiscuous_modes *)
1958 &desc.params.raw;
1959 i40e_status status;
1960
1961 i40e_fill_default_direct_cmd_desc(&desc,
1962 i40e_aqc_opc_set_vsi_promiscuous_modes);
1963
1964 cmd->promiscuous_flags = cpu_to_le16(0);
1965 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_DEFAULT);
1966 cmd->seid = cpu_to_le16(seid);
1967
1968 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
1969
1970 return status;
1971}
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981i40e_status i40e_aq_set_vsi_unicast_promiscuous(struct i40e_hw *hw,
1982 u16 seid, bool set,
1983 struct i40e_asq_cmd_details *cmd_details,
1984 bool rx_only_promisc)
1985{
1986 struct i40e_aq_desc desc;
1987 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
1988 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
1989 i40e_status status;
1990 u16 flags = 0;
1991
1992 i40e_fill_default_direct_cmd_desc(&desc,
1993 i40e_aqc_opc_set_vsi_promiscuous_modes);
1994
1995 if (set) {
1996 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
1997 if (rx_only_promisc && i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
1998 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
1999 }
2000
2001 cmd->promiscuous_flags = cpu_to_le16(flags);
2002
2003 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2004 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2005 cmd->valid_flags |=
2006 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2007
2008 cmd->seid = cpu_to_le16(seid);
2009 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2010
2011 return status;
2012}
2013
2014
2015
2016
2017
2018
2019
2020
2021i40e_status i40e_aq_set_vsi_multicast_promiscuous(struct i40e_hw *hw,
2022 u16 seid, bool set, struct i40e_asq_cmd_details *cmd_details)
2023{
2024 struct i40e_aq_desc desc;
2025 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2026 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2027 i40e_status status;
2028 u16 flags = 0;
2029
2030 i40e_fill_default_direct_cmd_desc(&desc,
2031 i40e_aqc_opc_set_vsi_promiscuous_modes);
2032
2033 if (set)
2034 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2035
2036 cmd->promiscuous_flags = cpu_to_le16(flags);
2037
2038 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2039
2040 cmd->seid = cpu_to_le16(seid);
2041 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2042
2043 return status;
2044}
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054enum i40e_status_code i40e_aq_set_vsi_mc_promisc_on_vlan(struct i40e_hw *hw,
2055 u16 seid, bool enable,
2056 u16 vid,
2057 struct i40e_asq_cmd_details *cmd_details)
2058{
2059 struct i40e_aq_desc desc;
2060 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2061 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2062 enum i40e_status_code status;
2063 u16 flags = 0;
2064
2065 i40e_fill_default_direct_cmd_desc(&desc,
2066 i40e_aqc_opc_set_vsi_promiscuous_modes);
2067
2068 if (enable)
2069 flags |= I40E_AQC_SET_VSI_PROMISC_MULTICAST;
2070
2071 cmd->promiscuous_flags = cpu_to_le16(flags);
2072 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_MULTICAST);
2073 cmd->seid = cpu_to_le16(seid);
2074 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2075
2076 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2077
2078 return status;
2079}
2080
2081
2082
2083
2084
2085
2086
2087
2088
2089enum i40e_status_code i40e_aq_set_vsi_uc_promisc_on_vlan(struct i40e_hw *hw,
2090 u16 seid, bool enable,
2091 u16 vid,
2092 struct i40e_asq_cmd_details *cmd_details)
2093{
2094 struct i40e_aq_desc desc;
2095 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2096 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2097 enum i40e_status_code status;
2098 u16 flags = 0;
2099
2100 i40e_fill_default_direct_cmd_desc(&desc,
2101 i40e_aqc_opc_set_vsi_promiscuous_modes);
2102
2103 if (enable) {
2104 flags |= I40E_AQC_SET_VSI_PROMISC_UNICAST;
2105 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2106 flags |= I40E_AQC_SET_VSI_PROMISC_RX_ONLY;
2107 }
2108
2109 cmd->promiscuous_flags = cpu_to_le16(flags);
2110 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_UNICAST);
2111 if (i40e_is_aq_api_ver_ge(&hw->aq, 1, 5))
2112 cmd->valid_flags |=
2113 cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_RX_ONLY);
2114 cmd->seid = cpu_to_le16(seid);
2115 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2116
2117 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2118
2119 return status;
2120}
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130i40e_status i40e_aq_set_vsi_bc_promisc_on_vlan(struct i40e_hw *hw,
2131 u16 seid, bool enable, u16 vid,
2132 struct i40e_asq_cmd_details *cmd_details)
2133{
2134 struct i40e_aq_desc desc;
2135 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2136 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2137 i40e_status status;
2138 u16 flags = 0;
2139
2140 i40e_fill_default_direct_cmd_desc(&desc,
2141 i40e_aqc_opc_set_vsi_promiscuous_modes);
2142
2143 if (enable)
2144 flags |= I40E_AQC_SET_VSI_PROMISC_BROADCAST;
2145
2146 cmd->promiscuous_flags = cpu_to_le16(flags);
2147 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2148 cmd->seid = cpu_to_le16(seid);
2149 cmd->vlan_tag = cpu_to_le16(vid | I40E_AQC_SET_VSI_VLAN_VALID);
2150
2151 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2152
2153 return status;
2154}
2155
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165i40e_status i40e_aq_set_vsi_broadcast(struct i40e_hw *hw,
2166 u16 seid, bool set_filter,
2167 struct i40e_asq_cmd_details *cmd_details)
2168{
2169 struct i40e_aq_desc desc;
2170 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2171 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2172 i40e_status status;
2173
2174 i40e_fill_default_direct_cmd_desc(&desc,
2175 i40e_aqc_opc_set_vsi_promiscuous_modes);
2176
2177 if (set_filter)
2178 cmd->promiscuous_flags
2179 |= cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2180 else
2181 cmd->promiscuous_flags
2182 &= cpu_to_le16(~I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2183
2184 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_BROADCAST);
2185 cmd->seid = cpu_to_le16(seid);
2186 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2187
2188 return status;
2189}
2190
2191
2192
2193
2194
2195
2196
2197
2198i40e_status i40e_aq_set_vsi_vlan_promisc(struct i40e_hw *hw,
2199 u16 seid, bool enable,
2200 struct i40e_asq_cmd_details *cmd_details)
2201{
2202 struct i40e_aq_desc desc;
2203 struct i40e_aqc_set_vsi_promiscuous_modes *cmd =
2204 (struct i40e_aqc_set_vsi_promiscuous_modes *)&desc.params.raw;
2205 i40e_status status;
2206 u16 flags = 0;
2207
2208 i40e_fill_default_direct_cmd_desc(&desc,
2209 i40e_aqc_opc_set_vsi_promiscuous_modes);
2210 if (enable)
2211 flags |= I40E_AQC_SET_VSI_PROMISC_VLAN;
2212
2213 cmd->promiscuous_flags = cpu_to_le16(flags);
2214 cmd->valid_flags = cpu_to_le16(I40E_AQC_SET_VSI_PROMISC_VLAN);
2215 cmd->seid = cpu_to_le16(seid);
2216
2217 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2218
2219 return status;
2220}
2221
2222
2223
2224
2225
2226
2227
2228i40e_status i40e_aq_get_vsi_params(struct i40e_hw *hw,
2229 struct i40e_vsi_context *vsi_ctx,
2230 struct i40e_asq_cmd_details *cmd_details)
2231{
2232 struct i40e_aq_desc desc;
2233 struct i40e_aqc_add_get_update_vsi *cmd =
2234 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2235 struct i40e_aqc_add_get_update_vsi_completion *resp =
2236 (struct i40e_aqc_add_get_update_vsi_completion *)
2237 &desc.params.raw;
2238 i40e_status status;
2239
2240 i40e_fill_default_direct_cmd_desc(&desc,
2241 i40e_aqc_opc_get_vsi_parameters);
2242
2243 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2244
2245 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2246
2247 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2248 sizeof(vsi_ctx->info), NULL);
2249
2250 if (status)
2251 goto aq_get_vsi_params_exit;
2252
2253 vsi_ctx->seid = le16_to_cpu(resp->seid);
2254 vsi_ctx->vsi_number = le16_to_cpu(resp->vsi_number);
2255 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2256 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2257
2258aq_get_vsi_params_exit:
2259 return status;
2260}
2261
2262
2263
2264
2265
2266
2267
2268
2269
2270i40e_status i40e_aq_update_vsi_params(struct i40e_hw *hw,
2271 struct i40e_vsi_context *vsi_ctx,
2272 struct i40e_asq_cmd_details *cmd_details)
2273{
2274 struct i40e_aq_desc desc;
2275 struct i40e_aqc_add_get_update_vsi *cmd =
2276 (struct i40e_aqc_add_get_update_vsi *)&desc.params.raw;
2277 struct i40e_aqc_add_get_update_vsi_completion *resp =
2278 (struct i40e_aqc_add_get_update_vsi_completion *)
2279 &desc.params.raw;
2280 i40e_status status;
2281
2282 i40e_fill_default_direct_cmd_desc(&desc,
2283 i40e_aqc_opc_update_vsi_parameters);
2284 cmd->uplink_seid = cpu_to_le16(vsi_ctx->seid);
2285
2286 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2287
2288 status = i40e_asq_send_command(hw, &desc, &vsi_ctx->info,
2289 sizeof(vsi_ctx->info), cmd_details);
2290
2291 vsi_ctx->vsis_allocated = le16_to_cpu(resp->vsi_used);
2292 vsi_ctx->vsis_unallocated = le16_to_cpu(resp->vsi_free);
2293
2294 return status;
2295}
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307i40e_status i40e_aq_get_switch_config(struct i40e_hw *hw,
2308 struct i40e_aqc_get_switch_config_resp *buf,
2309 u16 buf_size, u16 *start_seid,
2310 struct i40e_asq_cmd_details *cmd_details)
2311{
2312 struct i40e_aq_desc desc;
2313 struct i40e_aqc_switch_seid *scfg =
2314 (struct i40e_aqc_switch_seid *)&desc.params.raw;
2315 i40e_status status;
2316
2317 i40e_fill_default_direct_cmd_desc(&desc,
2318 i40e_aqc_opc_get_switch_config);
2319 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
2320 if (buf_size > I40E_AQ_LARGE_BUF)
2321 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2322 scfg->seid = cpu_to_le16(*start_seid);
2323
2324 status = i40e_asq_send_command(hw, &desc, buf, buf_size, cmd_details);
2325 *start_seid = le16_to_cpu(scfg->seid);
2326
2327 return status;
2328}
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341enum i40e_status_code i40e_aq_set_switch_config(struct i40e_hw *hw,
2342 u16 flags,
2343 u16 valid_flags, u8 mode,
2344 struct i40e_asq_cmd_details *cmd_details)
2345{
2346 struct i40e_aq_desc desc;
2347 struct i40e_aqc_set_switch_config *scfg =
2348 (struct i40e_aqc_set_switch_config *)&desc.params.raw;
2349 enum i40e_status_code status;
2350
2351 i40e_fill_default_direct_cmd_desc(&desc,
2352 i40e_aqc_opc_set_switch_config);
2353 scfg->flags = cpu_to_le16(flags);
2354 scfg->valid_flags = cpu_to_le16(valid_flags);
2355 scfg->mode = mode;
2356 if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
2357 scfg->switch_tag = cpu_to_le16(hw->switch_tag);
2358 scfg->first_tag = cpu_to_le16(hw->first_tag);
2359 scfg->second_tag = cpu_to_le16(hw->second_tag);
2360 }
2361 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2362
2363 return status;
2364}
2365
2366
2367
2368
2369
2370
2371
2372
2373
2374
2375
2376
2377
2378i40e_status i40e_aq_get_firmware_version(struct i40e_hw *hw,
2379 u16 *fw_major_version, u16 *fw_minor_version,
2380 u32 *fw_build,
2381 u16 *api_major_version, u16 *api_minor_version,
2382 struct i40e_asq_cmd_details *cmd_details)
2383{
2384 struct i40e_aq_desc desc;
2385 struct i40e_aqc_get_version *resp =
2386 (struct i40e_aqc_get_version *)&desc.params.raw;
2387 i40e_status status;
2388
2389 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_version);
2390
2391 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2392
2393 if (!status) {
2394 if (fw_major_version)
2395 *fw_major_version = le16_to_cpu(resp->fw_major);
2396 if (fw_minor_version)
2397 *fw_minor_version = le16_to_cpu(resp->fw_minor);
2398 if (fw_build)
2399 *fw_build = le32_to_cpu(resp->fw_build);
2400 if (api_major_version)
2401 *api_major_version = le16_to_cpu(resp->api_major);
2402 if (api_minor_version)
2403 *api_minor_version = le16_to_cpu(resp->api_minor);
2404 }
2405
2406 return status;
2407}
2408
2409
2410
2411
2412
2413
2414
2415
2416
2417i40e_status i40e_aq_send_driver_version(struct i40e_hw *hw,
2418 struct i40e_driver_version *dv,
2419 struct i40e_asq_cmd_details *cmd_details)
2420{
2421 struct i40e_aq_desc desc;
2422 struct i40e_aqc_driver_version *cmd =
2423 (struct i40e_aqc_driver_version *)&desc.params.raw;
2424 i40e_status status;
2425 u16 len;
2426
2427 if (dv == NULL)
2428 return I40E_ERR_PARAM;
2429
2430 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_driver_version);
2431
2432 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
2433 cmd->driver_major_ver = dv->major_version;
2434 cmd->driver_minor_ver = dv->minor_version;
2435 cmd->driver_build_ver = dv->build_version;
2436 cmd->driver_subbuild_ver = dv->subbuild_version;
2437
2438 len = 0;
2439 while (len < sizeof(dv->driver_string) &&
2440 (dv->driver_string[len] < 0x80) &&
2441 dv->driver_string[len])
2442 len++;
2443 status = i40e_asq_send_command(hw, &desc, dv->driver_string,
2444 len, cmd_details);
2445
2446 return status;
2447}
2448
2449
2450
2451
2452
2453
2454
2455
2456
2457
2458
2459i40e_status i40e_get_link_status(struct i40e_hw *hw, bool *link_up)
2460{
2461 i40e_status status = 0;
2462
2463 if (hw->phy.get_link_info) {
2464 status = i40e_update_link_info(hw);
2465
2466 if (status)
2467 i40e_debug(hw, I40E_DEBUG_LINK, "get link failed: status %d\n",
2468 status);
2469 }
2470
2471 *link_up = hw->phy.link_info.link_info & I40E_AQ_LINK_UP;
2472
2473 return status;
2474}
2475
2476
2477
2478
2479
2480noinline_for_stack i40e_status i40e_update_link_info(struct i40e_hw *hw)
2481{
2482 struct i40e_aq_get_phy_abilities_resp abilities;
2483 i40e_status status = 0;
2484
2485 status = i40e_aq_get_link_info(hw, true, NULL, NULL);
2486 if (status)
2487 return status;
2488
2489
2490 if ((hw->phy.link_info.link_info & I40E_AQ_MEDIA_AVAILABLE) &&
2491 ((hw->phy.link_info.link_info & I40E_AQ_LINK_UP) ||
2492 !(hw->phy.link_info_old.link_info & I40E_AQ_LINK_UP))) {
2493 status = i40e_aq_get_phy_capabilities(hw, false, false,
2494 &abilities, NULL);
2495 if (status)
2496 return status;
2497
2498 if (abilities.fec_cfg_curr_mod_ext_info &
2499 I40E_AQ_ENABLE_FEC_AUTO)
2500 hw->phy.link_info.req_fec_info =
2501 (I40E_AQ_REQUEST_FEC_KR |
2502 I40E_AQ_REQUEST_FEC_RS);
2503 else
2504 hw->phy.link_info.req_fec_info =
2505 abilities.fec_cfg_curr_mod_ext_info &
2506 (I40E_AQ_REQUEST_FEC_KR |
2507 I40E_AQ_REQUEST_FEC_RS);
2508
2509 memcpy(hw->phy.link_info.module_type, &abilities.module_type,
2510 sizeof(hw->phy.link_info.module_type));
2511 }
2512
2513 return status;
2514}
2515
2516
2517
2518
2519
2520
2521
2522
2523
2524
2525
2526
2527
2528
2529
2530i40e_status i40e_aq_add_veb(struct i40e_hw *hw, u16 uplink_seid,
2531 u16 downlink_seid, u8 enabled_tc,
2532 bool default_port, u16 *veb_seid,
2533 bool enable_stats,
2534 struct i40e_asq_cmd_details *cmd_details)
2535{
2536 struct i40e_aq_desc desc;
2537 struct i40e_aqc_add_veb *cmd =
2538 (struct i40e_aqc_add_veb *)&desc.params.raw;
2539 struct i40e_aqc_add_veb_completion *resp =
2540 (struct i40e_aqc_add_veb_completion *)&desc.params.raw;
2541 i40e_status status;
2542 u16 veb_flags = 0;
2543
2544
2545 if (!!uplink_seid != !!downlink_seid)
2546 return I40E_ERR_PARAM;
2547
2548 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_veb);
2549
2550 cmd->uplink_seid = cpu_to_le16(uplink_seid);
2551 cmd->downlink_seid = cpu_to_le16(downlink_seid);
2552 cmd->enable_tcs = enabled_tc;
2553 if (!uplink_seid)
2554 veb_flags |= I40E_AQC_ADD_VEB_FLOATING;
2555 if (default_port)
2556 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT;
2557 else
2558 veb_flags |= I40E_AQC_ADD_VEB_PORT_TYPE_DATA;
2559
2560
2561 if (!enable_stats)
2562 veb_flags |= I40E_AQC_ADD_VEB_ENABLE_DISABLE_STATS;
2563
2564 cmd->veb_flags = cpu_to_le16(veb_flags);
2565
2566 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2567
2568 if (!status && veb_seid)
2569 *veb_seid = le16_to_cpu(resp->veb_seid);
2570
2571 return status;
2572}
2573
2574
2575
2576
2577
2578
2579
2580
2581
2582
2583
2584
2585
2586
2587
2588i40e_status i40e_aq_get_veb_parameters(struct i40e_hw *hw,
2589 u16 veb_seid, u16 *switch_id,
2590 bool *floating, u16 *statistic_index,
2591 u16 *vebs_used, u16 *vebs_free,
2592 struct i40e_asq_cmd_details *cmd_details)
2593{
2594 struct i40e_aq_desc desc;
2595 struct i40e_aqc_get_veb_parameters_completion *cmd_resp =
2596 (struct i40e_aqc_get_veb_parameters_completion *)
2597 &desc.params.raw;
2598 i40e_status status;
2599
2600 if (veb_seid == 0)
2601 return I40E_ERR_PARAM;
2602
2603 i40e_fill_default_direct_cmd_desc(&desc,
2604 i40e_aqc_opc_get_veb_parameters);
2605 cmd_resp->seid = cpu_to_le16(veb_seid);
2606
2607 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2608 if (status)
2609 goto get_veb_exit;
2610
2611 if (switch_id)
2612 *switch_id = le16_to_cpu(cmd_resp->switch_id);
2613 if (statistic_index)
2614 *statistic_index = le16_to_cpu(cmd_resp->statistic_index);
2615 if (vebs_used)
2616 *vebs_used = le16_to_cpu(cmd_resp->vebs_used);
2617 if (vebs_free)
2618 *vebs_free = le16_to_cpu(cmd_resp->vebs_free);
2619 if (floating) {
2620 u16 flags = le16_to_cpu(cmd_resp->veb_flags);
2621
2622 if (flags & I40E_AQC_ADD_VEB_FLOATING)
2623 *floating = true;
2624 else
2625 *floating = false;
2626 }
2627
2628get_veb_exit:
2629 return status;
2630}
2631
2632
2633
2634
2635
2636
2637
2638
2639
2640
2641
2642i40e_status i40e_aq_add_macvlan(struct i40e_hw *hw, u16 seid,
2643 struct i40e_aqc_add_macvlan_element_data *mv_list,
2644 u16 count, struct i40e_asq_cmd_details *cmd_details)
2645{
2646 struct i40e_aq_desc desc;
2647 struct i40e_aqc_macvlan *cmd =
2648 (struct i40e_aqc_macvlan *)&desc.params.raw;
2649 i40e_status status;
2650 u16 buf_size;
2651 int i;
2652
2653 if (count == 0 || !mv_list || !hw)
2654 return I40E_ERR_PARAM;
2655
2656 buf_size = count * sizeof(*mv_list);
2657
2658
2659 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_macvlan);
2660 cmd->num_addresses = cpu_to_le16(count);
2661 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2662 cmd->seid[1] = 0;
2663 cmd->seid[2] = 0;
2664
2665 for (i = 0; i < count; i++)
2666 if (is_multicast_ether_addr(mv_list[i].mac_addr))
2667 mv_list[i].flags |=
2668 cpu_to_le16(I40E_AQC_MACVLAN_ADD_USE_SHARED_MAC);
2669
2670 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2671 if (buf_size > I40E_AQ_LARGE_BUF)
2672 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2673
2674 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2675 cmd_details);
2676
2677 return status;
2678}
2679
2680
2681
2682
2683
2684
2685
2686
2687
2688
2689
2690i40e_status i40e_aq_remove_macvlan(struct i40e_hw *hw, u16 seid,
2691 struct i40e_aqc_remove_macvlan_element_data *mv_list,
2692 u16 count, struct i40e_asq_cmd_details *cmd_details)
2693{
2694 struct i40e_aq_desc desc;
2695 struct i40e_aqc_macvlan *cmd =
2696 (struct i40e_aqc_macvlan *)&desc.params.raw;
2697 i40e_status status;
2698 u16 buf_size;
2699
2700 if (count == 0 || !mv_list || !hw)
2701 return I40E_ERR_PARAM;
2702
2703 buf_size = count * sizeof(*mv_list);
2704
2705
2706 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_remove_macvlan);
2707 cmd->num_addresses = cpu_to_le16(count);
2708 cmd->seid[0] = cpu_to_le16(I40E_AQC_MACVLAN_CMD_SEID_VALID | seid);
2709 cmd->seid[1] = 0;
2710 cmd->seid[2] = 0;
2711
2712 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
2713 if (buf_size > I40E_AQ_LARGE_BUF)
2714 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2715
2716 status = i40e_asq_send_command(hw, &desc, mv_list, buf_size,
2717 cmd_details);
2718
2719 return status;
2720}
2721
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739static i40e_status i40e_mirrorrule_op(struct i40e_hw *hw,
2740 u16 opcode, u16 sw_seid, u16 rule_type, u16 id,
2741 u16 count, __le16 *mr_list,
2742 struct i40e_asq_cmd_details *cmd_details,
2743 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2744{
2745 struct i40e_aq_desc desc;
2746 struct i40e_aqc_add_delete_mirror_rule *cmd =
2747 (struct i40e_aqc_add_delete_mirror_rule *)&desc.params.raw;
2748 struct i40e_aqc_add_delete_mirror_rule_completion *resp =
2749 (struct i40e_aqc_add_delete_mirror_rule_completion *)&desc.params.raw;
2750 i40e_status status;
2751 u16 buf_size;
2752
2753 buf_size = count * sizeof(*mr_list);
2754
2755
2756 i40e_fill_default_direct_cmd_desc(&desc, opcode);
2757 cmd->seid = cpu_to_le16(sw_seid);
2758 cmd->rule_type = cpu_to_le16(rule_type &
2759 I40E_AQC_MIRROR_RULE_TYPE_MASK);
2760 cmd->num_entries = cpu_to_le16(count);
2761
2762 cmd->destination = cpu_to_le16(id);
2763 if (mr_list) {
2764 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2765 I40E_AQ_FLAG_RD));
2766 if (buf_size > I40E_AQ_LARGE_BUF)
2767 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2768 }
2769
2770 status = i40e_asq_send_command(hw, &desc, mr_list, buf_size,
2771 cmd_details);
2772 if (!status ||
2773 hw->aq.asq_last_status == I40E_AQ_RC_ENOSPC) {
2774 if (rule_id)
2775 *rule_id = le16_to_cpu(resp->rule_id);
2776 if (rules_used)
2777 *rules_used = le16_to_cpu(resp->mirror_rules_used);
2778 if (rules_free)
2779 *rules_free = le16_to_cpu(resp->mirror_rules_free);
2780 }
2781 return status;
2782}
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796
2797
2798
2799i40e_status i40e_aq_add_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2800 u16 rule_type, u16 dest_vsi, u16 count, __le16 *mr_list,
2801 struct i40e_asq_cmd_details *cmd_details,
2802 u16 *rule_id, u16 *rules_used, u16 *rules_free)
2803{
2804 if (!(rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS ||
2805 rule_type == I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS)) {
2806 if (count == 0 || !mr_list)
2807 return I40E_ERR_PARAM;
2808 }
2809
2810 return i40e_mirrorrule_op(hw, i40e_aqc_opc_add_mirror_rule, sw_seid,
2811 rule_type, dest_vsi, count, mr_list,
2812 cmd_details, rule_id, rules_used, rules_free);
2813}
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823
2824
2825
2826
2827
2828
2829
2830i40e_status i40e_aq_delete_mirrorrule(struct i40e_hw *hw, u16 sw_seid,
2831 u16 rule_type, u16 rule_id, u16 count, __le16 *mr_list,
2832 struct i40e_asq_cmd_details *cmd_details,
2833 u16 *rules_used, u16 *rules_free)
2834{
2835
2836 if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
2837
2838
2839
2840
2841 if (count == 0 || !mr_list)
2842 return I40E_ERR_PARAM;
2843 }
2844
2845 return i40e_mirrorrule_op(hw, i40e_aqc_opc_delete_mirror_rule, sw_seid,
2846 rule_type, rule_id, count, mr_list,
2847 cmd_details, NULL, rules_used, rules_free);
2848}
2849
2850
2851
2852
2853
2854
2855
2856
2857
2858
2859
2860
2861
2862i40e_status i40e_aq_send_msg_to_vf(struct i40e_hw *hw, u16 vfid,
2863 u32 v_opcode, u32 v_retval, u8 *msg, u16 msglen,
2864 struct i40e_asq_cmd_details *cmd_details)
2865{
2866 struct i40e_aq_desc desc;
2867 struct i40e_aqc_pf_vf_message *cmd =
2868 (struct i40e_aqc_pf_vf_message *)&desc.params.raw;
2869 i40e_status status;
2870
2871 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_send_msg_to_vf);
2872 cmd->id = cpu_to_le32(vfid);
2873 desc.cookie_high = cpu_to_le32(v_opcode);
2874 desc.cookie_low = cpu_to_le32(v_retval);
2875 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_SI);
2876 if (msglen) {
2877 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
2878 I40E_AQ_FLAG_RD));
2879 if (msglen > I40E_AQ_LARGE_BUF)
2880 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
2881 desc.datalen = cpu_to_le16(msglen);
2882 }
2883 status = i40e_asq_send_command(hw, &desc, msg, msglen, cmd_details);
2884
2885 return status;
2886}
2887
2888
2889
2890
2891
2892
2893
2894
2895
2896
2897i40e_status i40e_aq_debug_read_register(struct i40e_hw *hw,
2898 u32 reg_addr, u64 *reg_val,
2899 struct i40e_asq_cmd_details *cmd_details)
2900{
2901 struct i40e_aq_desc desc;
2902 struct i40e_aqc_debug_reg_read_write *cmd_resp =
2903 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2904 i40e_status status;
2905
2906 if (reg_val == NULL)
2907 return I40E_ERR_PARAM;
2908
2909 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_read_reg);
2910
2911 cmd_resp->address = cpu_to_le32(reg_addr);
2912
2913 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2914
2915 if (!status) {
2916 *reg_val = ((u64)le32_to_cpu(cmd_resp->value_high) << 32) |
2917 (u64)le32_to_cpu(cmd_resp->value_low);
2918 }
2919
2920 return status;
2921}
2922
2923
2924
2925
2926
2927
2928
2929
2930
2931
2932i40e_status i40e_aq_debug_write_register(struct i40e_hw *hw,
2933 u32 reg_addr, u64 reg_val,
2934 struct i40e_asq_cmd_details *cmd_details)
2935{
2936 struct i40e_aq_desc desc;
2937 struct i40e_aqc_debug_reg_read_write *cmd =
2938 (struct i40e_aqc_debug_reg_read_write *)&desc.params.raw;
2939 i40e_status status;
2940
2941 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_debug_write_reg);
2942
2943 cmd->address = cpu_to_le32(reg_addr);
2944 cmd->value_high = cpu_to_le32((u32)(reg_val >> 32));
2945 cmd->value_low = cpu_to_le32((u32)(reg_val & 0xFFFFFFFF));
2946
2947 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2948
2949 return status;
2950}
2951
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963i40e_status i40e_aq_request_resource(struct i40e_hw *hw,
2964 enum i40e_aq_resources_ids resource,
2965 enum i40e_aq_resource_access_type access,
2966 u8 sdp_number, u64 *timeout,
2967 struct i40e_asq_cmd_details *cmd_details)
2968{
2969 struct i40e_aq_desc desc;
2970 struct i40e_aqc_request_resource *cmd_resp =
2971 (struct i40e_aqc_request_resource *)&desc.params.raw;
2972 i40e_status status;
2973
2974 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_request_resource);
2975
2976 cmd_resp->resource_id = cpu_to_le16(resource);
2977 cmd_resp->access_type = cpu_to_le16(access);
2978 cmd_resp->resource_number = cpu_to_le32(sdp_number);
2979
2980 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
2981
2982
2983
2984
2985
2986
2987 if (!status || hw->aq.asq_last_status == I40E_AQ_RC_EBUSY)
2988 *timeout = le32_to_cpu(cmd_resp->timeout);
2989
2990 return status;
2991}
2992
2993
2994
2995
2996
2997
2998
2999
3000
3001
3002i40e_status i40e_aq_release_resource(struct i40e_hw *hw,
3003 enum i40e_aq_resources_ids resource,
3004 u8 sdp_number,
3005 struct i40e_asq_cmd_details *cmd_details)
3006{
3007 struct i40e_aq_desc desc;
3008 struct i40e_aqc_request_resource *cmd =
3009 (struct i40e_aqc_request_resource *)&desc.params.raw;
3010 i40e_status status;
3011
3012 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_release_resource);
3013
3014 cmd->resource_id = cpu_to_le16(resource);
3015 cmd->resource_number = cpu_to_le32(sdp_number);
3016
3017 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3018
3019 return status;
3020}
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034i40e_status i40e_aq_read_nvm(struct i40e_hw *hw, u8 module_pointer,
3035 u32 offset, u16 length, void *data,
3036 bool last_command,
3037 struct i40e_asq_cmd_details *cmd_details)
3038{
3039 struct i40e_aq_desc desc;
3040 struct i40e_aqc_nvm_update *cmd =
3041 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3042 i40e_status status;
3043
3044
3045 if (offset & 0xFF000000) {
3046 status = I40E_ERR_PARAM;
3047 goto i40e_aq_read_nvm_exit;
3048 }
3049
3050 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_read);
3051
3052
3053 if (last_command)
3054 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3055 cmd->module_pointer = module_pointer;
3056 cmd->offset = cpu_to_le32(offset);
3057 cmd->length = cpu_to_le16(length);
3058
3059 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3060 if (length > I40E_AQ_LARGE_BUF)
3061 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3062
3063 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3064
3065i40e_aq_read_nvm_exit:
3066 return status;
3067}
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080i40e_status i40e_aq_erase_nvm(struct i40e_hw *hw, u8 module_pointer,
3081 u32 offset, u16 length, bool last_command,
3082 struct i40e_asq_cmd_details *cmd_details)
3083{
3084 struct i40e_aq_desc desc;
3085 struct i40e_aqc_nvm_update *cmd =
3086 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3087 i40e_status status;
3088
3089
3090 if (offset & 0xFF000000) {
3091 status = I40E_ERR_PARAM;
3092 goto i40e_aq_erase_nvm_exit;
3093 }
3094
3095 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_erase);
3096
3097
3098 if (last_command)
3099 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3100 cmd->module_pointer = module_pointer;
3101 cmd->offset = cpu_to_le32(offset);
3102 cmd->length = cpu_to_le16(length);
3103
3104 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3105
3106i40e_aq_erase_nvm_exit:
3107 return status;
3108}
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119static void i40e_parse_discover_capabilities(struct i40e_hw *hw, void *buff,
3120 u32 cap_count,
3121 enum i40e_admin_queue_opc list_type_opc)
3122{
3123 struct i40e_aqc_list_capabilities_element_resp *cap;
3124 u32 valid_functions, num_functions;
3125 u32 number, logical_id, phys_id;
3126 struct i40e_hw_capabilities *p;
3127 u16 id, ocp_cfg_word0;
3128 i40e_status status;
3129 u8 major_rev;
3130 u32 i = 0;
3131
3132 cap = (struct i40e_aqc_list_capabilities_element_resp *) buff;
3133
3134 if (list_type_opc == i40e_aqc_opc_list_dev_capabilities)
3135 p = &hw->dev_caps;
3136 else if (list_type_opc == i40e_aqc_opc_list_func_capabilities)
3137 p = &hw->func_caps;
3138 else
3139 return;
3140
3141 for (i = 0; i < cap_count; i++, cap++) {
3142 id = le16_to_cpu(cap->id);
3143 number = le32_to_cpu(cap->number);
3144 logical_id = le32_to_cpu(cap->logical_id);
3145 phys_id = le32_to_cpu(cap->phys_id);
3146 major_rev = cap->major_rev;
3147
3148 switch (id) {
3149 case I40E_AQ_CAP_ID_SWITCH_MODE:
3150 p->switch_mode = number;
3151 break;
3152 case I40E_AQ_CAP_ID_MNG_MODE:
3153 p->management_mode = number;
3154 if (major_rev > 1) {
3155 p->mng_protocols_over_mctp = logical_id;
3156 i40e_debug(hw, I40E_DEBUG_INIT,
3157 "HW Capability: Protocols over MCTP = %d\n",
3158 p->mng_protocols_over_mctp);
3159 } else {
3160 p->mng_protocols_over_mctp = 0;
3161 }
3162 break;
3163 case I40E_AQ_CAP_ID_NPAR_ACTIVE:
3164 p->npar_enable = number;
3165 break;
3166 case I40E_AQ_CAP_ID_OS2BMC_CAP:
3167 p->os2bmc = number;
3168 break;
3169 case I40E_AQ_CAP_ID_FUNCTIONS_VALID:
3170 p->valid_functions = number;
3171 break;
3172 case I40E_AQ_CAP_ID_SRIOV:
3173 if (number == 1)
3174 p->sr_iov_1_1 = true;
3175 break;
3176 case I40E_AQ_CAP_ID_VF:
3177 p->num_vfs = number;
3178 p->vf_base_id = logical_id;
3179 break;
3180 case I40E_AQ_CAP_ID_VMDQ:
3181 if (number == 1)
3182 p->vmdq = true;
3183 break;
3184 case I40E_AQ_CAP_ID_8021QBG:
3185 if (number == 1)
3186 p->evb_802_1_qbg = true;
3187 break;
3188 case I40E_AQ_CAP_ID_8021QBR:
3189 if (number == 1)
3190 p->evb_802_1_qbh = true;
3191 break;
3192 case I40E_AQ_CAP_ID_VSI:
3193 p->num_vsis = number;
3194 break;
3195 case I40E_AQ_CAP_ID_DCB:
3196 if (number == 1) {
3197 p->dcb = true;
3198 p->enabled_tcmap = logical_id;
3199 p->maxtc = phys_id;
3200 }
3201 break;
3202 case I40E_AQ_CAP_ID_FCOE:
3203 if (number == 1)
3204 p->fcoe = true;
3205 break;
3206 case I40E_AQ_CAP_ID_ISCSI:
3207 if (number == 1)
3208 p->iscsi = true;
3209 break;
3210 case I40E_AQ_CAP_ID_RSS:
3211 p->rss = true;
3212 p->rss_table_size = number;
3213 p->rss_table_entry_width = logical_id;
3214 break;
3215 case I40E_AQ_CAP_ID_RXQ:
3216 p->num_rx_qp = number;
3217 p->base_queue = phys_id;
3218 break;
3219 case I40E_AQ_CAP_ID_TXQ:
3220 p->num_tx_qp = number;
3221 p->base_queue = phys_id;
3222 break;
3223 case I40E_AQ_CAP_ID_MSIX:
3224 p->num_msix_vectors = number;
3225 i40e_debug(hw, I40E_DEBUG_INIT,
3226 "HW Capability: MSIX vector count = %d\n",
3227 p->num_msix_vectors);
3228 break;
3229 case I40E_AQ_CAP_ID_VF_MSIX:
3230 p->num_msix_vectors_vf = number;
3231 break;
3232 case I40E_AQ_CAP_ID_FLEX10:
3233 if (major_rev == 1) {
3234 if (number == 1) {
3235 p->flex10_enable = true;
3236 p->flex10_capable = true;
3237 }
3238 } else {
3239
3240 if (number & 1)
3241 p->flex10_enable = true;
3242 if (number & 2)
3243 p->flex10_capable = true;
3244 }
3245 p->flex10_mode = logical_id;
3246 p->flex10_status = phys_id;
3247 break;
3248 case I40E_AQ_CAP_ID_CEM:
3249 if (number == 1)
3250 p->mgmt_cem = true;
3251 break;
3252 case I40E_AQ_CAP_ID_IWARP:
3253 if (number == 1)
3254 p->iwarp = true;
3255 break;
3256 case I40E_AQ_CAP_ID_LED:
3257 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3258 p->led[phys_id] = true;
3259 break;
3260 case I40E_AQ_CAP_ID_SDP:
3261 if (phys_id < I40E_HW_CAP_MAX_GPIO)
3262 p->sdp[phys_id] = true;
3263 break;
3264 case I40E_AQ_CAP_ID_MDIO:
3265 if (number == 1) {
3266 p->mdio_port_num = phys_id;
3267 p->mdio_port_mode = logical_id;
3268 }
3269 break;
3270 case I40E_AQ_CAP_ID_1588:
3271 if (number == 1)
3272 p->ieee_1588 = true;
3273 break;
3274 case I40E_AQ_CAP_ID_FLOW_DIRECTOR:
3275 p->fd = true;
3276 p->fd_filters_guaranteed = number;
3277 p->fd_filters_best_effort = logical_id;
3278 break;
3279 case I40E_AQ_CAP_ID_WSR_PROT:
3280 p->wr_csr_prot = (u64)number;
3281 p->wr_csr_prot |= (u64)logical_id << 32;
3282 break;
3283 case I40E_AQ_CAP_ID_NVM_MGMT:
3284 if (number & I40E_NVM_MGMT_SEC_REV_DISABLED)
3285 p->sec_rev_disabled = true;
3286 if (number & I40E_NVM_MGMT_UPDATE_DISABLED)
3287 p->update_disabled = true;
3288 break;
3289 default:
3290 break;
3291 }
3292 }
3293
3294 if (p->fcoe)
3295 i40e_debug(hw, I40E_DEBUG_ALL, "device is FCoE capable\n");
3296
3297
3298
3299
3300 if (p->npar_enable || p->flex10_enable)
3301 p->fcoe = false;
3302
3303
3304 hw->num_ports = 0;
3305 for (i = 0; i < 4; i++) {
3306 u32 port_cfg_reg = I40E_PRTGEN_CNF + (4 * i);
3307 u64 port_cfg = 0;
3308
3309
3310
3311
3312 i40e_aq_debug_read_register(hw, port_cfg_reg, &port_cfg, NULL);
3313 if (!(port_cfg & I40E_PRTGEN_CNF_PORT_DIS_MASK))
3314 hw->num_ports++;
3315 }
3316
3317
3318
3319
3320
3321
3322
3323
3324 if (hw->mac.type == I40E_MAC_X722) {
3325 if (!i40e_acquire_nvm(hw, I40E_RESOURCE_READ)) {
3326 status = i40e_aq_read_nvm(hw, I40E_SR_EMP_MODULE_PTR,
3327 2 * I40E_SR_OCP_CFG_WORD0,
3328 sizeof(ocp_cfg_word0),
3329 &ocp_cfg_word0, true, NULL);
3330 if (!status &&
3331 (ocp_cfg_word0 & I40E_SR_OCP_ENABLED))
3332 hw->num_ports = 4;
3333 i40e_release_nvm(hw);
3334 }
3335 }
3336
3337 valid_functions = p->valid_functions;
3338 num_functions = 0;
3339 while (valid_functions) {
3340 if (valid_functions & 1)
3341 num_functions++;
3342 valid_functions >>= 1;
3343 }
3344
3345
3346
3347
3348 if (hw->num_ports != 0) {
3349 hw->partition_id = (hw->pf_id / hw->num_ports) + 1;
3350 hw->num_partitions = num_functions / hw->num_ports;
3351 }
3352
3353
3354
3355
3356 p->rx_buf_chain_len = I40E_MAX_CHAINED_RX_BUFFERS;
3357}
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370i40e_status i40e_aq_discover_capabilities(struct i40e_hw *hw,
3371 void *buff, u16 buff_size, u16 *data_size,
3372 enum i40e_admin_queue_opc list_type_opc,
3373 struct i40e_asq_cmd_details *cmd_details)
3374{
3375 struct i40e_aqc_list_capabilites *cmd;
3376 struct i40e_aq_desc desc;
3377 i40e_status status = 0;
3378
3379 cmd = (struct i40e_aqc_list_capabilites *)&desc.params.raw;
3380
3381 if (list_type_opc != i40e_aqc_opc_list_func_capabilities &&
3382 list_type_opc != i40e_aqc_opc_list_dev_capabilities) {
3383 status = I40E_ERR_PARAM;
3384 goto exit;
3385 }
3386
3387 i40e_fill_default_direct_cmd_desc(&desc, list_type_opc);
3388
3389 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3390 if (buff_size > I40E_AQ_LARGE_BUF)
3391 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3392
3393 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3394 *data_size = le16_to_cpu(desc.datalen);
3395
3396 if (status)
3397 goto exit;
3398
3399 i40e_parse_discover_capabilities(hw, buff, le32_to_cpu(cmd->count),
3400 list_type_opc);
3401
3402exit:
3403 return status;
3404}
3405
3406
3407
3408
3409
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419i40e_status i40e_aq_update_nvm(struct i40e_hw *hw, u8 module_pointer,
3420 u32 offset, u16 length, void *data,
3421 bool last_command, u8 preservation_flags,
3422 struct i40e_asq_cmd_details *cmd_details)
3423{
3424 struct i40e_aq_desc desc;
3425 struct i40e_aqc_nvm_update *cmd =
3426 (struct i40e_aqc_nvm_update *)&desc.params.raw;
3427 i40e_status status;
3428
3429
3430 if (offset & 0xFF000000) {
3431 status = I40E_ERR_PARAM;
3432 goto i40e_aq_update_nvm_exit;
3433 }
3434
3435 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3436
3437
3438 if (last_command)
3439 cmd->command_flags |= I40E_AQ_NVM_LAST_CMD;
3440 if (hw->mac.type == I40E_MAC_X722) {
3441 if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_SELECTED)
3442 cmd->command_flags |=
3443 (I40E_AQ_NVM_PRESERVATION_FLAGS_SELECTED <<
3444 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3445 else if (preservation_flags == I40E_NVM_PRESERVATION_FLAGS_ALL)
3446 cmd->command_flags |=
3447 (I40E_AQ_NVM_PRESERVATION_FLAGS_ALL <<
3448 I40E_AQ_NVM_PRESERVATION_FLAGS_SHIFT);
3449 }
3450 cmd->module_pointer = module_pointer;
3451 cmd->offset = cpu_to_le32(offset);
3452 cmd->length = cpu_to_le16(length);
3453
3454 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3455 if (length > I40E_AQ_LARGE_BUF)
3456 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3457
3458 status = i40e_asq_send_command(hw, &desc, data, length, cmd_details);
3459
3460i40e_aq_update_nvm_exit:
3461 return status;
3462}
3463
3464
3465
3466
3467
3468
3469
3470
3471
3472i40e_status i40e_aq_rearrange_nvm(struct i40e_hw *hw,
3473 u8 rearrange_nvm,
3474 struct i40e_asq_cmd_details *cmd_details)
3475{
3476 struct i40e_aqc_nvm_update *cmd;
3477 i40e_status status;
3478 struct i40e_aq_desc desc;
3479
3480 cmd = (struct i40e_aqc_nvm_update *)&desc.params.raw;
3481
3482 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_nvm_update);
3483
3484 rearrange_nvm &= (I40E_AQ_NVM_REARRANGE_TO_FLAT |
3485 I40E_AQ_NVM_REARRANGE_TO_STRUCT);
3486
3487 if (!rearrange_nvm) {
3488 status = I40E_ERR_PARAM;
3489 goto i40e_aq_rearrange_nvm_exit;
3490 }
3491
3492 cmd->command_flags |= rearrange_nvm;
3493 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3494
3495i40e_aq_rearrange_nvm_exit:
3496 return status;
3497}
3498
3499
3500
3501
3502
3503
3504
3505
3506
3507
3508
3509
3510
3511
3512i40e_status i40e_aq_get_lldp_mib(struct i40e_hw *hw, u8 bridge_type,
3513 u8 mib_type, void *buff, u16 buff_size,
3514 u16 *local_len, u16 *remote_len,
3515 struct i40e_asq_cmd_details *cmd_details)
3516{
3517 struct i40e_aq_desc desc;
3518 struct i40e_aqc_lldp_get_mib *cmd =
3519 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3520 struct i40e_aqc_lldp_get_mib *resp =
3521 (struct i40e_aqc_lldp_get_mib *)&desc.params.raw;
3522 i40e_status status;
3523
3524 if (buff_size == 0 || !buff)
3525 return I40E_ERR_PARAM;
3526
3527 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_get_mib);
3528
3529 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3530
3531 cmd->type = mib_type & I40E_AQ_LLDP_MIB_TYPE_MASK;
3532 cmd->type |= ((bridge_type << I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT) &
3533 I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
3534
3535 desc.datalen = cpu_to_le16(buff_size);
3536
3537 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3538 if (buff_size > I40E_AQ_LARGE_BUF)
3539 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3540
3541 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3542 if (!status) {
3543 if (local_len != NULL)
3544 *local_len = le16_to_cpu(resp->local_len);
3545 if (remote_len != NULL)
3546 *remote_len = le16_to_cpu(resp->remote_len);
3547 }
3548
3549 return status;
3550}
3551
3552
3553
3554
3555
3556
3557
3558
3559
3560
3561
3562enum i40e_status_code
3563i40e_aq_set_lldp_mib(struct i40e_hw *hw,
3564 u8 mib_type, void *buff, u16 buff_size,
3565 struct i40e_asq_cmd_details *cmd_details)
3566{
3567 struct i40e_aqc_lldp_set_local_mib *cmd;
3568 enum i40e_status_code status;
3569 struct i40e_aq_desc desc;
3570
3571 cmd = (struct i40e_aqc_lldp_set_local_mib *)&desc.params.raw;
3572 if (buff_size == 0 || !buff)
3573 return I40E_ERR_PARAM;
3574
3575 i40e_fill_default_direct_cmd_desc(&desc,
3576 i40e_aqc_opc_lldp_set_local_mib);
3577
3578 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
3579 if (buff_size > I40E_AQ_LARGE_BUF)
3580 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3581 desc.datalen = cpu_to_le16(buff_size);
3582
3583 cmd->type = mib_type;
3584 cmd->length = cpu_to_le16(buff_size);
3585 cmd->address_high = cpu_to_le32(upper_32_bits((uintptr_t)buff));
3586 cmd->address_low = cpu_to_le32(lower_32_bits((uintptr_t)buff));
3587
3588 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3589 return status;
3590}
3591
3592
3593
3594
3595
3596
3597
3598
3599
3600
3601i40e_status i40e_aq_cfg_lldp_mib_change_event(struct i40e_hw *hw,
3602 bool enable_update,
3603 struct i40e_asq_cmd_details *cmd_details)
3604{
3605 struct i40e_aq_desc desc;
3606 struct i40e_aqc_lldp_update_mib *cmd =
3607 (struct i40e_aqc_lldp_update_mib *)&desc.params.raw;
3608 i40e_status status;
3609
3610 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_update_mib);
3611
3612 if (!enable_update)
3613 cmd->command |= I40E_AQ_LLDP_MIB_UPDATE_DISABLE;
3614
3615 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3616
3617 return status;
3618}
3619
3620
3621
3622
3623
3624
3625
3626
3627
3628
3629
3630enum i40e_status_code
3631i40e_aq_restore_lldp(struct i40e_hw *hw, u8 *setting, bool restore,
3632 struct i40e_asq_cmd_details *cmd_details)
3633{
3634 struct i40e_aq_desc desc;
3635 struct i40e_aqc_lldp_restore *cmd =
3636 (struct i40e_aqc_lldp_restore *)&desc.params.raw;
3637 i40e_status status;
3638
3639 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)) {
3640 i40e_debug(hw, I40E_DEBUG_ALL,
3641 "Restore LLDP not supported by current FW version.\n");
3642 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3643 }
3644
3645 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_restore);
3646
3647 if (restore)
3648 cmd->command |= I40E_AQ_LLDP_AGENT_RESTORE;
3649
3650 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3651
3652 if (setting)
3653 *setting = cmd->command & 1;
3654
3655 return status;
3656}
3657
3658
3659
3660
3661
3662
3663
3664
3665
3666
3667i40e_status i40e_aq_stop_lldp(struct i40e_hw *hw, bool shutdown_agent,
3668 bool persist,
3669 struct i40e_asq_cmd_details *cmd_details)
3670{
3671 struct i40e_aq_desc desc;
3672 struct i40e_aqc_lldp_stop *cmd =
3673 (struct i40e_aqc_lldp_stop *)&desc.params.raw;
3674 i40e_status status;
3675
3676 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_stop);
3677
3678 if (shutdown_agent)
3679 cmd->command |= I40E_AQ_LLDP_AGENT_SHUTDOWN;
3680
3681 if (persist) {
3682 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3683 cmd->command |= I40E_AQ_LLDP_AGENT_STOP_PERSIST;
3684 else
3685 i40e_debug(hw, I40E_DEBUG_ALL,
3686 "Persistent Stop LLDP not supported by current FW version.\n");
3687 }
3688
3689 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3690
3691 return status;
3692}
3693
3694
3695
3696
3697
3698
3699
3700
3701
3702i40e_status i40e_aq_start_lldp(struct i40e_hw *hw, bool persist,
3703 struct i40e_asq_cmd_details *cmd_details)
3704{
3705 struct i40e_aq_desc desc;
3706 struct i40e_aqc_lldp_start *cmd =
3707 (struct i40e_aqc_lldp_start *)&desc.params.raw;
3708 i40e_status status;
3709
3710 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_lldp_start);
3711
3712 cmd->command = I40E_AQ_LLDP_AGENT_START;
3713
3714 if (persist) {
3715 if (hw->flags & I40E_HW_FLAG_FW_LLDP_PERSISTENT)
3716 cmd->command |= I40E_AQ_LLDP_AGENT_START_PERSIST;
3717 else
3718 i40e_debug(hw, I40E_DEBUG_ALL,
3719 "Persistent Start LLDP not supported by current FW version.\n");
3720 }
3721
3722 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3723
3724 return status;
3725}
3726
3727
3728
3729
3730
3731
3732
3733
3734enum i40e_status_code
3735i40e_aq_set_dcb_parameters(struct i40e_hw *hw, bool dcb_enable,
3736 struct i40e_asq_cmd_details *cmd_details)
3737{
3738 struct i40e_aq_desc desc;
3739 struct i40e_aqc_set_dcb_parameters *cmd =
3740 (struct i40e_aqc_set_dcb_parameters *)&desc.params.raw;
3741 i40e_status status;
3742
3743 if (!(hw->flags & I40E_HW_FLAG_FW_LLDP_STOPPABLE))
3744 return I40E_ERR_DEVICE_NOT_SUPPORTED;
3745
3746 i40e_fill_default_direct_cmd_desc(&desc,
3747 i40e_aqc_opc_set_dcb_parameters);
3748
3749 if (dcb_enable) {
3750 cmd->valid_flags = I40E_DCB_VALID;
3751 cmd->command = I40E_AQ_DCB_SET_AGENT;
3752 }
3753 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3754
3755 return status;
3756}
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767i40e_status i40e_aq_get_cee_dcb_config(struct i40e_hw *hw,
3768 void *buff, u16 buff_size,
3769 struct i40e_asq_cmd_details *cmd_details)
3770{
3771 struct i40e_aq_desc desc;
3772 i40e_status status;
3773
3774 if (buff_size == 0 || !buff)
3775 return I40E_ERR_PARAM;
3776
3777 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_get_cee_dcb_cfg);
3778
3779 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3780 status = i40e_asq_send_command(hw, &desc, (void *)buff, buff_size,
3781 cmd_details);
3782
3783 return status;
3784}
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795
3796
3797
3798i40e_status i40e_aq_add_udp_tunnel(struct i40e_hw *hw,
3799 u16 udp_port, u8 protocol_index,
3800 u8 *filter_index,
3801 struct i40e_asq_cmd_details *cmd_details)
3802{
3803 struct i40e_aq_desc desc;
3804 struct i40e_aqc_add_udp_tunnel *cmd =
3805 (struct i40e_aqc_add_udp_tunnel *)&desc.params.raw;
3806 struct i40e_aqc_del_udp_tunnel_completion *resp =
3807 (struct i40e_aqc_del_udp_tunnel_completion *)&desc.params.raw;
3808 i40e_status status;
3809
3810 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_add_udp_tunnel);
3811
3812 cmd->udp_port = cpu_to_le16(udp_port);
3813 cmd->protocol_type = protocol_index;
3814
3815 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3816
3817 if (!status && filter_index)
3818 *filter_index = resp->index;
3819
3820 return status;
3821}
3822
3823
3824
3825
3826
3827
3828
3829i40e_status i40e_aq_del_udp_tunnel(struct i40e_hw *hw, u8 index,
3830 struct i40e_asq_cmd_details *cmd_details)
3831{
3832 struct i40e_aq_desc desc;
3833 struct i40e_aqc_remove_udp_tunnel *cmd =
3834 (struct i40e_aqc_remove_udp_tunnel *)&desc.params.raw;
3835 i40e_status status;
3836
3837 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_del_udp_tunnel);
3838
3839 cmd->index = index;
3840
3841 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3842
3843 return status;
3844}
3845
3846
3847
3848
3849
3850
3851
3852
3853
3854i40e_status i40e_aq_delete_element(struct i40e_hw *hw, u16 seid,
3855 struct i40e_asq_cmd_details *cmd_details)
3856{
3857 struct i40e_aq_desc desc;
3858 struct i40e_aqc_switch_seid *cmd =
3859 (struct i40e_aqc_switch_seid *)&desc.params.raw;
3860 i40e_status status;
3861
3862 if (seid == 0)
3863 return I40E_ERR_PARAM;
3864
3865 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_delete_element);
3866
3867 cmd->seid = cpu_to_le16(seid);
3868
3869 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3870
3871 return status;
3872}
3873
3874
3875
3876
3877
3878
3879
3880
3881
3882
3883i40e_status i40e_aq_dcb_updated(struct i40e_hw *hw,
3884 struct i40e_asq_cmd_details *cmd_details)
3885{
3886 struct i40e_aq_desc desc;
3887 i40e_status status;
3888
3889 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_dcb_updated);
3890
3891 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3892
3893 return status;
3894}
3895
3896
3897
3898
3899
3900
3901
3902
3903
3904
3905
3906
3907static i40e_status i40e_aq_tx_sched_cmd(struct i40e_hw *hw, u16 seid,
3908 void *buff, u16 buff_size,
3909 enum i40e_admin_queue_opc opcode,
3910 struct i40e_asq_cmd_details *cmd_details)
3911{
3912 struct i40e_aq_desc desc;
3913 struct i40e_aqc_tx_sched_ind *cmd =
3914 (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
3915 i40e_status status;
3916 bool cmd_param_flag = false;
3917
3918 switch (opcode) {
3919 case i40e_aqc_opc_configure_vsi_ets_sla_bw_limit:
3920 case i40e_aqc_opc_configure_vsi_tc_bw:
3921 case i40e_aqc_opc_enable_switching_comp_ets:
3922 case i40e_aqc_opc_modify_switching_comp_ets:
3923 case i40e_aqc_opc_disable_switching_comp_ets:
3924 case i40e_aqc_opc_configure_switching_comp_ets_bw_limit:
3925 case i40e_aqc_opc_configure_switching_comp_bw_config:
3926 cmd_param_flag = true;
3927 break;
3928 case i40e_aqc_opc_query_vsi_bw_config:
3929 case i40e_aqc_opc_query_vsi_ets_sla_config:
3930 case i40e_aqc_opc_query_switching_comp_ets_config:
3931 case i40e_aqc_opc_query_port_ets_config:
3932 case i40e_aqc_opc_query_switching_comp_bw_config:
3933 cmd_param_flag = false;
3934 break;
3935 default:
3936 return I40E_ERR_PARAM;
3937 }
3938
3939 i40e_fill_default_direct_cmd_desc(&desc, opcode);
3940
3941
3942 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
3943 if (cmd_param_flag)
3944 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
3945 if (buff_size > I40E_AQ_LARGE_BUF)
3946 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
3947
3948 desc.datalen = cpu_to_le16(buff_size);
3949
3950 cmd->vsi_seid = cpu_to_le16(seid);
3951
3952 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
3953
3954 return status;
3955}
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965i40e_status i40e_aq_config_vsi_bw_limit(struct i40e_hw *hw,
3966 u16 seid, u16 credit, u8 max_credit,
3967 struct i40e_asq_cmd_details *cmd_details)
3968{
3969 struct i40e_aq_desc desc;
3970 struct i40e_aqc_configure_vsi_bw_limit *cmd =
3971 (struct i40e_aqc_configure_vsi_bw_limit *)&desc.params.raw;
3972 i40e_status status;
3973
3974 i40e_fill_default_direct_cmd_desc(&desc,
3975 i40e_aqc_opc_configure_vsi_bw_limit);
3976
3977 cmd->vsi_seid = cpu_to_le16(seid);
3978 cmd->credit = cpu_to_le16(credit);
3979 cmd->max_credit = max_credit;
3980
3981 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
3982
3983 return status;
3984}
3985
3986
3987
3988
3989
3990
3991
3992
3993i40e_status i40e_aq_config_vsi_tc_bw(struct i40e_hw *hw,
3994 u16 seid,
3995 struct i40e_aqc_configure_vsi_tc_bw_data *bw_data,
3996 struct i40e_asq_cmd_details *cmd_details)
3997{
3998 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
3999 i40e_aqc_opc_configure_vsi_tc_bw,
4000 cmd_details);
4001}
4002
4003
4004
4005
4006
4007
4008
4009
4010
4011i40e_status i40e_aq_config_switch_comp_ets(struct i40e_hw *hw,
4012 u16 seid,
4013 struct i40e_aqc_configure_switching_comp_ets_data *ets_data,
4014 enum i40e_admin_queue_opc opcode,
4015 struct i40e_asq_cmd_details *cmd_details)
4016{
4017 return i40e_aq_tx_sched_cmd(hw, seid, (void *)ets_data,
4018 sizeof(*ets_data), opcode, cmd_details);
4019}
4020
4021
4022
4023
4024
4025
4026
4027
4028i40e_status i40e_aq_config_switch_comp_bw_config(struct i40e_hw *hw,
4029 u16 seid,
4030 struct i40e_aqc_configure_switching_comp_bw_config_data *bw_data,
4031 struct i40e_asq_cmd_details *cmd_details)
4032{
4033 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4034 i40e_aqc_opc_configure_switching_comp_bw_config,
4035 cmd_details);
4036}
4037
4038
4039
4040
4041
4042
4043
4044
4045i40e_status i40e_aq_query_vsi_bw_config(struct i40e_hw *hw,
4046 u16 seid,
4047 struct i40e_aqc_query_vsi_bw_config_resp *bw_data,
4048 struct i40e_asq_cmd_details *cmd_details)
4049{
4050 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4051 i40e_aqc_opc_query_vsi_bw_config,
4052 cmd_details);
4053}
4054
4055
4056
4057
4058
4059
4060
4061
4062i40e_status i40e_aq_query_vsi_ets_sla_config(struct i40e_hw *hw,
4063 u16 seid,
4064 struct i40e_aqc_query_vsi_ets_sla_config_resp *bw_data,
4065 struct i40e_asq_cmd_details *cmd_details)
4066{
4067 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4068 i40e_aqc_opc_query_vsi_ets_sla_config,
4069 cmd_details);
4070}
4071
4072
4073
4074
4075
4076
4077
4078
4079i40e_status i40e_aq_query_switch_comp_ets_config(struct i40e_hw *hw,
4080 u16 seid,
4081 struct i40e_aqc_query_switching_comp_ets_config_resp *bw_data,
4082 struct i40e_asq_cmd_details *cmd_details)
4083{
4084 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4085 i40e_aqc_opc_query_switching_comp_ets_config,
4086 cmd_details);
4087}
4088
4089
4090
4091
4092
4093
4094
4095
4096i40e_status i40e_aq_query_port_ets_config(struct i40e_hw *hw,
4097 u16 seid,
4098 struct i40e_aqc_query_port_ets_config_resp *bw_data,
4099 struct i40e_asq_cmd_details *cmd_details)
4100{
4101 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4102 i40e_aqc_opc_query_port_ets_config,
4103 cmd_details);
4104}
4105
4106
4107
4108
4109
4110
4111
4112
4113i40e_status i40e_aq_query_switch_comp_bw_config(struct i40e_hw *hw,
4114 u16 seid,
4115 struct i40e_aqc_query_switching_comp_bw_config_resp *bw_data,
4116 struct i40e_asq_cmd_details *cmd_details)
4117{
4118 return i40e_aq_tx_sched_cmd(hw, seid, (void *)bw_data, sizeof(*bw_data),
4119 i40e_aqc_opc_query_switching_comp_bw_config,
4120 cmd_details);
4121}
4122
4123
4124
4125
4126
4127
4128
4129
4130
4131
4132
4133
4134
4135static i40e_status i40e_validate_filter_settings(struct i40e_hw *hw,
4136 struct i40e_filter_control_settings *settings)
4137{
4138 u32 fcoe_cntx_size, fcoe_filt_size;
4139 u32 pe_cntx_size, pe_filt_size;
4140 u32 fcoe_fmax;
4141 u32 val;
4142
4143
4144 switch (settings->fcoe_filt_num) {
4145 case I40E_HASH_FILTER_SIZE_1K:
4146 case I40E_HASH_FILTER_SIZE_2K:
4147 case I40E_HASH_FILTER_SIZE_4K:
4148 case I40E_HASH_FILTER_SIZE_8K:
4149 case I40E_HASH_FILTER_SIZE_16K:
4150 case I40E_HASH_FILTER_SIZE_32K:
4151 fcoe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4152 fcoe_filt_size <<= (u32)settings->fcoe_filt_num;
4153 break;
4154 default:
4155 return I40E_ERR_PARAM;
4156 }
4157
4158 switch (settings->fcoe_cntx_num) {
4159 case I40E_DMA_CNTX_SIZE_512:
4160 case I40E_DMA_CNTX_SIZE_1K:
4161 case I40E_DMA_CNTX_SIZE_2K:
4162 case I40E_DMA_CNTX_SIZE_4K:
4163 fcoe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4164 fcoe_cntx_size <<= (u32)settings->fcoe_cntx_num;
4165 break;
4166 default:
4167 return I40E_ERR_PARAM;
4168 }
4169
4170
4171 switch (settings->pe_filt_num) {
4172 case I40E_HASH_FILTER_SIZE_1K:
4173 case I40E_HASH_FILTER_SIZE_2K:
4174 case I40E_HASH_FILTER_SIZE_4K:
4175 case I40E_HASH_FILTER_SIZE_8K:
4176 case I40E_HASH_FILTER_SIZE_16K:
4177 case I40E_HASH_FILTER_SIZE_32K:
4178 case I40E_HASH_FILTER_SIZE_64K:
4179 case I40E_HASH_FILTER_SIZE_128K:
4180 case I40E_HASH_FILTER_SIZE_256K:
4181 case I40E_HASH_FILTER_SIZE_512K:
4182 case I40E_HASH_FILTER_SIZE_1M:
4183 pe_filt_size = I40E_HASH_FILTER_BASE_SIZE;
4184 pe_filt_size <<= (u32)settings->pe_filt_num;
4185 break;
4186 default:
4187 return I40E_ERR_PARAM;
4188 }
4189
4190 switch (settings->pe_cntx_num) {
4191 case I40E_DMA_CNTX_SIZE_512:
4192 case I40E_DMA_CNTX_SIZE_1K:
4193 case I40E_DMA_CNTX_SIZE_2K:
4194 case I40E_DMA_CNTX_SIZE_4K:
4195 case I40E_DMA_CNTX_SIZE_8K:
4196 case I40E_DMA_CNTX_SIZE_16K:
4197 case I40E_DMA_CNTX_SIZE_32K:
4198 case I40E_DMA_CNTX_SIZE_64K:
4199 case I40E_DMA_CNTX_SIZE_128K:
4200 case I40E_DMA_CNTX_SIZE_256K:
4201 pe_cntx_size = I40E_DMA_CNTX_BASE_SIZE;
4202 pe_cntx_size <<= (u32)settings->pe_cntx_num;
4203 break;
4204 default:
4205 return I40E_ERR_PARAM;
4206 }
4207
4208
4209 val = rd32(hw, I40E_GLHMC_FCOEFMAX);
4210 fcoe_fmax = (val & I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_MASK)
4211 >> I40E_GLHMC_FCOEFMAX_PMFCOEFMAX_SHIFT;
4212 if (fcoe_filt_size + fcoe_cntx_size > fcoe_fmax)
4213 return I40E_ERR_INVALID_SIZE;
4214
4215 return 0;
4216}
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227i40e_status i40e_set_filter_control(struct i40e_hw *hw,
4228 struct i40e_filter_control_settings *settings)
4229{
4230 i40e_status ret = 0;
4231 u32 hash_lut_size = 0;
4232 u32 val;
4233
4234 if (!settings)
4235 return I40E_ERR_PARAM;
4236
4237
4238 ret = i40e_validate_filter_settings(hw, settings);
4239 if (ret)
4240 return ret;
4241
4242
4243 val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
4244
4245
4246 val &= ~I40E_PFQF_CTL_0_PEHSIZE_MASK;
4247 val |= ((u32)settings->pe_filt_num << I40E_PFQF_CTL_0_PEHSIZE_SHIFT) &
4248 I40E_PFQF_CTL_0_PEHSIZE_MASK;
4249
4250 val &= ~I40E_PFQF_CTL_0_PEDSIZE_MASK;
4251 val |= ((u32)settings->pe_cntx_num << I40E_PFQF_CTL_0_PEDSIZE_SHIFT) &
4252 I40E_PFQF_CTL_0_PEDSIZE_MASK;
4253
4254
4255 val &= ~I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4256 val |= ((u32)settings->fcoe_filt_num <<
4257 I40E_PFQF_CTL_0_PFFCHSIZE_SHIFT) &
4258 I40E_PFQF_CTL_0_PFFCHSIZE_MASK;
4259
4260 val &= ~I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4261 val |= ((u32)settings->fcoe_cntx_num <<
4262 I40E_PFQF_CTL_0_PFFCDSIZE_SHIFT) &
4263 I40E_PFQF_CTL_0_PFFCDSIZE_MASK;
4264
4265
4266 val &= ~I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4267 if (settings->hash_lut_size == I40E_HASH_LUT_SIZE_512)
4268 hash_lut_size = 1;
4269 val |= (hash_lut_size << I40E_PFQF_CTL_0_HASHLUTSIZE_SHIFT) &
4270 I40E_PFQF_CTL_0_HASHLUTSIZE_MASK;
4271
4272
4273 if (settings->enable_fdir)
4274 val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
4275 if (settings->enable_ethtype)
4276 val |= I40E_PFQF_CTL_0_ETYPE_ENA_MASK;
4277 if (settings->enable_macvlan)
4278 val |= I40E_PFQF_CTL_0_MACVLAN_ENA_MASK;
4279
4280 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
4281
4282 return 0;
4283}
4284
4285
4286
4287
4288
4289
4290
4291
4292
4293
4294
4295
4296
4297
4298
4299
4300
4301i40e_status i40e_aq_add_rem_control_packet_filter(struct i40e_hw *hw,
4302 u8 *mac_addr, u16 ethtype, u16 flags,
4303 u16 vsi_seid, u16 queue, bool is_add,
4304 struct i40e_control_filter_stats *stats,
4305 struct i40e_asq_cmd_details *cmd_details)
4306{
4307 struct i40e_aq_desc desc;
4308 struct i40e_aqc_add_remove_control_packet_filter *cmd =
4309 (struct i40e_aqc_add_remove_control_packet_filter *)
4310 &desc.params.raw;
4311 struct i40e_aqc_add_remove_control_packet_filter_completion *resp =
4312 (struct i40e_aqc_add_remove_control_packet_filter_completion *)
4313 &desc.params.raw;
4314 i40e_status status;
4315
4316 if (vsi_seid == 0)
4317 return I40E_ERR_PARAM;
4318
4319 if (is_add) {
4320 i40e_fill_default_direct_cmd_desc(&desc,
4321 i40e_aqc_opc_add_control_packet_filter);
4322 cmd->queue = cpu_to_le16(queue);
4323 } else {
4324 i40e_fill_default_direct_cmd_desc(&desc,
4325 i40e_aqc_opc_remove_control_packet_filter);
4326 }
4327
4328 if (mac_addr)
4329 ether_addr_copy(cmd->mac, mac_addr);
4330
4331 cmd->etype = cpu_to_le16(ethtype);
4332 cmd->flags = cpu_to_le16(flags);
4333 cmd->seid = cpu_to_le16(vsi_seid);
4334
4335 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4336
4337 if (!status && stats) {
4338 stats->mac_etype_used = le16_to_cpu(resp->mac_etype_used);
4339 stats->etype_used = le16_to_cpu(resp->etype_used);
4340 stats->mac_etype_free = le16_to_cpu(resp->mac_etype_free);
4341 stats->etype_free = le16_to_cpu(resp->etype_free);
4342 }
4343
4344 return status;
4345}
4346
4347
4348
4349
4350
4351
4352void i40e_add_filter_to_drop_tx_flow_control_frames(struct i40e_hw *hw,
4353 u16 seid)
4354{
4355#define I40E_FLOW_CONTROL_ETHTYPE 0x8808
4356 u16 flag = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
4357 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
4358 I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
4359 u16 ethtype = I40E_FLOW_CONTROL_ETHTYPE;
4360 i40e_status status;
4361
4362 status = i40e_aq_add_rem_control_packet_filter(hw, NULL, ethtype, flag,
4363 seid, 0, true, NULL,
4364 NULL);
4365 if (status)
4366 hw_dbg(hw, "Ethtype Filter Add failed: Error pruning Tx flow control frames\n");
4367}
4368
4369
4370
4371
4372
4373
4374
4375
4376
4377
4378
4379
4380
4381
4382static i40e_status i40e_aq_alternate_read(struct i40e_hw *hw,
4383 u32 reg_addr0, u32 *reg_val0,
4384 u32 reg_addr1, u32 *reg_val1)
4385{
4386 struct i40e_aq_desc desc;
4387 struct i40e_aqc_alternate_write *cmd_resp =
4388 (struct i40e_aqc_alternate_write *)&desc.params.raw;
4389 i40e_status status;
4390
4391 if (!reg_val0)
4392 return I40E_ERR_PARAM;
4393
4394 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_alternate_read);
4395 cmd_resp->address0 = cpu_to_le32(reg_addr0);
4396 cmd_resp->address1 = cpu_to_le32(reg_addr1);
4397
4398 status = i40e_asq_send_command(hw, &desc, NULL, 0, NULL);
4399
4400 if (!status) {
4401 *reg_val0 = le32_to_cpu(cmd_resp->data0);
4402
4403 if (reg_val1)
4404 *reg_val1 = le32_to_cpu(cmd_resp->data1);
4405 }
4406
4407 return status;
4408}
4409
4410
4411
4412
4413
4414
4415
4416
4417
4418i40e_status i40e_aq_suspend_port_tx(struct i40e_hw *hw, u16 seid,
4419 struct i40e_asq_cmd_details *cmd_details)
4420{
4421 struct i40e_aqc_tx_sched_ind *cmd;
4422 struct i40e_aq_desc desc;
4423 i40e_status status;
4424
4425 cmd = (struct i40e_aqc_tx_sched_ind *)&desc.params.raw;
4426 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_suspend_port_tx);
4427 cmd->vsi_seid = cpu_to_le16(seid);
4428 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4429
4430 return status;
4431}
4432
4433
4434
4435
4436
4437
4438
4439
4440i40e_status i40e_aq_resume_port_tx(struct i40e_hw *hw,
4441 struct i40e_asq_cmd_details *cmd_details)
4442{
4443 struct i40e_aq_desc desc;
4444 i40e_status status;
4445
4446 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_resume_port_tx);
4447
4448 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
4449
4450 return status;
4451}
4452
4453
4454
4455
4456
4457
4458
4459
4460void i40e_set_pci_config_data(struct i40e_hw *hw, u16 link_status)
4461{
4462 hw->bus.type = i40e_bus_type_pci_express;
4463
4464 switch (link_status & PCI_EXP_LNKSTA_NLW) {
4465 case PCI_EXP_LNKSTA_NLW_X1:
4466 hw->bus.width = i40e_bus_width_pcie_x1;
4467 break;
4468 case PCI_EXP_LNKSTA_NLW_X2:
4469 hw->bus.width = i40e_bus_width_pcie_x2;
4470 break;
4471 case PCI_EXP_LNKSTA_NLW_X4:
4472 hw->bus.width = i40e_bus_width_pcie_x4;
4473 break;
4474 case PCI_EXP_LNKSTA_NLW_X8:
4475 hw->bus.width = i40e_bus_width_pcie_x8;
4476 break;
4477 default:
4478 hw->bus.width = i40e_bus_width_unknown;
4479 break;
4480 }
4481
4482 switch (link_status & PCI_EXP_LNKSTA_CLS) {
4483 case PCI_EXP_LNKSTA_CLS_2_5GB:
4484 hw->bus.speed = i40e_bus_speed_2500;
4485 break;
4486 case PCI_EXP_LNKSTA_CLS_5_0GB:
4487 hw->bus.speed = i40e_bus_speed_5000;
4488 break;
4489 case PCI_EXP_LNKSTA_CLS_8_0GB:
4490 hw->bus.speed = i40e_bus_speed_8000;
4491 break;
4492 default:
4493 hw->bus.speed = i40e_bus_speed_unknown;
4494 break;
4495 }
4496}
4497
4498
4499
4500
4501
4502
4503
4504
4505
4506
4507
4508
4509
4510
4511
4512
4513
4514i40e_status i40e_aq_debug_dump(struct i40e_hw *hw, u8 cluster_id,
4515 u8 table_id, u32 start_index, u16 buff_size,
4516 void *buff, u16 *ret_buff_size,
4517 u8 *ret_next_table, u32 *ret_next_index,
4518 struct i40e_asq_cmd_details *cmd_details)
4519{
4520 struct i40e_aq_desc desc;
4521 struct i40e_aqc_debug_dump_internals *cmd =
4522 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4523 struct i40e_aqc_debug_dump_internals *resp =
4524 (struct i40e_aqc_debug_dump_internals *)&desc.params.raw;
4525 i40e_status status;
4526
4527 if (buff_size == 0 || !buff)
4528 return I40E_ERR_PARAM;
4529
4530 i40e_fill_default_direct_cmd_desc(&desc,
4531 i40e_aqc_opc_debug_dump_internals);
4532
4533 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4534 if (buff_size > I40E_AQ_LARGE_BUF)
4535 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4536
4537 cmd->cluster_id = cluster_id;
4538 cmd->table_id = table_id;
4539 cmd->idx = cpu_to_le32(start_index);
4540
4541 desc.datalen = cpu_to_le16(buff_size);
4542
4543 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
4544 if (!status) {
4545 if (ret_buff_size)
4546 *ret_buff_size = le16_to_cpu(desc.datalen);
4547 if (ret_next_table)
4548 *ret_next_table = resp->table_id;
4549 if (ret_next_index)
4550 *ret_next_index = le32_to_cpu(resp->idx);
4551 }
4552
4553 return status;
4554}
4555
4556
4557
4558
4559
4560
4561
4562
4563
4564
4565
4566i40e_status i40e_read_bw_from_alt_ram(struct i40e_hw *hw,
4567 u32 *max_bw, u32 *min_bw,
4568 bool *min_valid, bool *max_valid)
4569{
4570 i40e_status status;
4571 u32 max_bw_addr, min_bw_addr;
4572
4573
4574 max_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4575 I40E_ALT_STRUCT_MAX_BW_OFFSET +
4576 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4577 min_bw_addr = I40E_ALT_STRUCT_FIRST_PF_OFFSET +
4578 I40E_ALT_STRUCT_MIN_BW_OFFSET +
4579 (I40E_ALT_STRUCT_DWORDS_PER_PF * hw->pf_id);
4580
4581
4582 status = i40e_aq_alternate_read(hw, max_bw_addr, max_bw,
4583 min_bw_addr, min_bw);
4584
4585 if (*min_bw & I40E_ALT_BW_VALID_MASK)
4586 *min_valid = true;
4587 else
4588 *min_valid = false;
4589
4590 if (*max_bw & I40E_ALT_BW_VALID_MASK)
4591 *max_valid = true;
4592 else
4593 *max_valid = false;
4594
4595 return status;
4596}
4597
4598
4599
4600
4601
4602
4603
4604
4605
4606i40e_status i40e_aq_configure_partition_bw(struct i40e_hw *hw,
4607 struct i40e_aqc_configure_partition_bw_data *bw_data,
4608 struct i40e_asq_cmd_details *cmd_details)
4609{
4610 i40e_status status;
4611 struct i40e_aq_desc desc;
4612 u16 bwd_size = sizeof(*bw_data);
4613
4614 i40e_fill_default_direct_cmd_desc(&desc,
4615 i40e_aqc_opc_configure_partition_bw);
4616
4617
4618 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
4619 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_RD);
4620
4621 if (bwd_size > I40E_AQ_LARGE_BUF)
4622 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
4623
4624 desc.datalen = cpu_to_le16(bwd_size);
4625
4626 status = i40e_asq_send_command(hw, &desc, bw_data, bwd_size,
4627 cmd_details);
4628
4629 return status;
4630}
4631
4632
4633
4634
4635
4636
4637
4638
4639
4640
4641i40e_status i40e_read_phy_register_clause22(struct i40e_hw *hw,
4642 u16 reg, u8 phy_addr, u16 *value)
4643{
4644 i40e_status status = I40E_ERR_TIMEOUT;
4645 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4646 u32 command = 0;
4647 u16 retry = 1000;
4648
4649 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4650 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4651 (I40E_MDIO_CLAUSE22_OPCODE_READ_MASK) |
4652 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4653 (I40E_GLGEN_MSCA_MDICMD_MASK);
4654 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4655 do {
4656 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4657 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4658 status = 0;
4659 break;
4660 }
4661 udelay(10);
4662 retry--;
4663 } while (retry);
4664
4665 if (status) {
4666 i40e_debug(hw, I40E_DEBUG_PHY,
4667 "PHY: Can't write command to external PHY.\n");
4668 } else {
4669 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4670 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4671 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4672 }
4673
4674 return status;
4675}
4676
4677
4678
4679
4680
4681
4682
4683
4684
4685
4686i40e_status i40e_write_phy_register_clause22(struct i40e_hw *hw,
4687 u16 reg, u8 phy_addr, u16 value)
4688{
4689 i40e_status status = I40E_ERR_TIMEOUT;
4690 u8 port_num = (u8)hw->func_caps.mdio_port_num;
4691 u32 command = 0;
4692 u16 retry = 1000;
4693
4694 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4695 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4696
4697 command = (reg << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4698 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4699 (I40E_MDIO_CLAUSE22_OPCODE_WRITE_MASK) |
4700 (I40E_MDIO_CLAUSE22_STCODE_MASK) |
4701 (I40E_GLGEN_MSCA_MDICMD_MASK);
4702
4703 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4704 do {
4705 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4706 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4707 status = 0;
4708 break;
4709 }
4710 udelay(10);
4711 retry--;
4712 } while (retry);
4713
4714 return status;
4715}
4716
4717
4718
4719
4720
4721
4722
4723
4724
4725
4726
4727i40e_status i40e_read_phy_register_clause45(struct i40e_hw *hw,
4728 u8 page, u16 reg, u8 phy_addr, u16 *value)
4729{
4730 i40e_status status = I40E_ERR_TIMEOUT;
4731 u32 command = 0;
4732 u16 retry = 1000;
4733 u8 port_num = hw->func_caps.mdio_port_num;
4734
4735 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4736 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4737 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4738 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4739 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4740 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4741 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4742 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4743 do {
4744 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4745 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4746 status = 0;
4747 break;
4748 }
4749 usleep_range(10, 20);
4750 retry--;
4751 } while (retry);
4752
4753 if (status) {
4754 i40e_debug(hw, I40E_DEBUG_PHY,
4755 "PHY: Can't write command to external PHY.\n");
4756 goto phy_read_end;
4757 }
4758
4759 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4760 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4761 (I40E_MDIO_CLAUSE45_OPCODE_READ_MASK) |
4762 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4763 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4764 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4765 status = I40E_ERR_TIMEOUT;
4766 retry = 1000;
4767 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4768 do {
4769 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4770 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4771 status = 0;
4772 break;
4773 }
4774 usleep_range(10, 20);
4775 retry--;
4776 } while (retry);
4777
4778 if (!status) {
4779 command = rd32(hw, I40E_GLGEN_MSRWD(port_num));
4780 *value = (command & I40E_GLGEN_MSRWD_MDIRDDATA_MASK) >>
4781 I40E_GLGEN_MSRWD_MDIRDDATA_SHIFT;
4782 } else {
4783 i40e_debug(hw, I40E_DEBUG_PHY,
4784 "PHY: Can't read register value from external PHY.\n");
4785 }
4786
4787phy_read_end:
4788 return status;
4789}
4790
4791
4792
4793
4794
4795
4796
4797
4798
4799
4800
4801i40e_status i40e_write_phy_register_clause45(struct i40e_hw *hw,
4802 u8 page, u16 reg, u8 phy_addr, u16 value)
4803{
4804 i40e_status status = I40E_ERR_TIMEOUT;
4805 u32 command = 0;
4806 u16 retry = 1000;
4807 u8 port_num = hw->func_caps.mdio_port_num;
4808
4809 command = (reg << I40E_GLGEN_MSCA_MDIADD_SHIFT) |
4810 (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4811 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4812 (I40E_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK) |
4813 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4814 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4815 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4816 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4817 do {
4818 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4819 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4820 status = 0;
4821 break;
4822 }
4823 usleep_range(10, 20);
4824 retry--;
4825 } while (retry);
4826 if (status) {
4827 i40e_debug(hw, I40E_DEBUG_PHY,
4828 "PHY: Can't write command to external PHY.\n");
4829 goto phy_write_end;
4830 }
4831
4832 command = value << I40E_GLGEN_MSRWD_MDIWRDATA_SHIFT;
4833 wr32(hw, I40E_GLGEN_MSRWD(port_num), command);
4834
4835 command = (page << I40E_GLGEN_MSCA_DEVADD_SHIFT) |
4836 (phy_addr << I40E_GLGEN_MSCA_PHYADD_SHIFT) |
4837 (I40E_MDIO_CLAUSE45_OPCODE_WRITE_MASK) |
4838 (I40E_MDIO_CLAUSE45_STCODE_MASK) |
4839 (I40E_GLGEN_MSCA_MDICMD_MASK) |
4840 (I40E_GLGEN_MSCA_MDIINPROGEN_MASK);
4841 status = I40E_ERR_TIMEOUT;
4842 retry = 1000;
4843 wr32(hw, I40E_GLGEN_MSCA(port_num), command);
4844 do {
4845 command = rd32(hw, I40E_GLGEN_MSCA(port_num));
4846 if (!(command & I40E_GLGEN_MSCA_MDICMD_MASK)) {
4847 status = 0;
4848 break;
4849 }
4850 usleep_range(10, 20);
4851 retry--;
4852 } while (retry);
4853
4854phy_write_end:
4855 return status;
4856}
4857
4858
4859
4860
4861
4862
4863
4864
4865
4866
4867
4868i40e_status i40e_write_phy_register(struct i40e_hw *hw,
4869 u8 page, u16 reg, u8 phy_addr, u16 value)
4870{
4871 i40e_status status;
4872
4873 switch (hw->device_id) {
4874 case I40E_DEV_ID_1G_BASE_T_X722:
4875 status = i40e_write_phy_register_clause22(hw, reg, phy_addr,
4876 value);
4877 break;
4878 case I40E_DEV_ID_5G_BASE_T_BC:
4879 case I40E_DEV_ID_10G_BASE_T:
4880 case I40E_DEV_ID_10G_BASE_T4:
4881 case I40E_DEV_ID_10G_BASE_T_BC:
4882 case I40E_DEV_ID_10G_BASE_T_X722:
4883 case I40E_DEV_ID_25G_B:
4884 case I40E_DEV_ID_25G_SFP28:
4885 status = i40e_write_phy_register_clause45(hw, page, reg,
4886 phy_addr, value);
4887 break;
4888 default:
4889 status = I40E_ERR_UNKNOWN_PHY;
4890 break;
4891 }
4892
4893 return status;
4894}
4895
4896
4897
4898
4899
4900
4901
4902
4903
4904
4905
4906i40e_status i40e_read_phy_register(struct i40e_hw *hw,
4907 u8 page, u16 reg, u8 phy_addr, u16 *value)
4908{
4909 i40e_status status;
4910
4911 switch (hw->device_id) {
4912 case I40E_DEV_ID_1G_BASE_T_X722:
4913 status = i40e_read_phy_register_clause22(hw, reg, phy_addr,
4914 value);
4915 break;
4916 case I40E_DEV_ID_5G_BASE_T_BC:
4917 case I40E_DEV_ID_10G_BASE_T:
4918 case I40E_DEV_ID_10G_BASE_T4:
4919 case I40E_DEV_ID_10G_BASE_T_BC:
4920 case I40E_DEV_ID_10G_BASE_T_X722:
4921 case I40E_DEV_ID_25G_B:
4922 case I40E_DEV_ID_25G_SFP28:
4923 status = i40e_read_phy_register_clause45(hw, page, reg,
4924 phy_addr, value);
4925 break;
4926 default:
4927 status = I40E_ERR_UNKNOWN_PHY;
4928 break;
4929 }
4930
4931 return status;
4932}
4933
4934
4935
4936
4937
4938
4939
4940
4941u8 i40e_get_phy_address(struct i40e_hw *hw, u8 dev_num)
4942{
4943 u8 port_num = hw->func_caps.mdio_port_num;
4944 u32 reg_val = rd32(hw, I40E_GLGEN_MDIO_I2C_SEL(port_num));
4945
4946 return (u8)(reg_val >> ((dev_num + 1) * 5)) & 0x1f;
4947}
4948
4949
4950
4951
4952
4953
4954
4955
4956
4957i40e_status i40e_blink_phy_link_led(struct i40e_hw *hw,
4958 u32 time, u32 interval)
4959{
4960 i40e_status status = 0;
4961 u32 i;
4962 u16 led_ctl;
4963 u16 gpio_led_port;
4964 u16 led_reg;
4965 u16 led_addr = I40E_PHY_LED_PROV_REG_1;
4966 u8 phy_addr = 0;
4967 u8 port_num;
4968
4969 i = rd32(hw, I40E_PFGEN_PORTNUM);
4970 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
4971 phy_addr = i40e_get_phy_address(hw, port_num);
4972
4973 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
4974 led_addr++) {
4975 status = i40e_read_phy_register_clause45(hw,
4976 I40E_PHY_COM_REG_PAGE,
4977 led_addr, phy_addr,
4978 &led_reg);
4979 if (status)
4980 goto phy_blinking_end;
4981 led_ctl = led_reg;
4982 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
4983 led_reg = 0;
4984 status = i40e_write_phy_register_clause45(hw,
4985 I40E_PHY_COM_REG_PAGE,
4986 led_addr, phy_addr,
4987 led_reg);
4988 if (status)
4989 goto phy_blinking_end;
4990 break;
4991 }
4992 }
4993
4994 if (time > 0 && interval > 0) {
4995 for (i = 0; i < time * 1000; i += interval) {
4996 status = i40e_read_phy_register_clause45(hw,
4997 I40E_PHY_COM_REG_PAGE,
4998 led_addr, phy_addr, &led_reg);
4999 if (status)
5000 goto restore_config;
5001 if (led_reg & I40E_PHY_LED_MANUAL_ON)
5002 led_reg = 0;
5003 else
5004 led_reg = I40E_PHY_LED_MANUAL_ON;
5005 status = i40e_write_phy_register_clause45(hw,
5006 I40E_PHY_COM_REG_PAGE,
5007 led_addr, phy_addr, led_reg);
5008 if (status)
5009 goto restore_config;
5010 msleep(interval);
5011 }
5012 }
5013
5014restore_config:
5015 status = i40e_write_phy_register_clause45(hw,
5016 I40E_PHY_COM_REG_PAGE,
5017 led_addr, phy_addr, led_ctl);
5018
5019phy_blinking_end:
5020 return status;
5021}
5022
5023
5024
5025
5026
5027
5028
5029static enum i40e_status_code i40e_led_get_reg(struct i40e_hw *hw, u16 led_addr,
5030 u32 *reg_val)
5031{
5032 enum i40e_status_code status;
5033 u8 phy_addr = 0;
5034 u8 port_num;
5035 u32 i;
5036
5037 *reg_val = 0;
5038 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5039 status =
5040 i40e_aq_get_phy_register(hw,
5041 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5042 I40E_PHY_COM_REG_PAGE, true,
5043 I40E_PHY_LED_PROV_REG_1,
5044 reg_val, NULL);
5045 } else {
5046 i = rd32(hw, I40E_PFGEN_PORTNUM);
5047 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5048 phy_addr = i40e_get_phy_address(hw, port_num);
5049 status = i40e_read_phy_register_clause45(hw,
5050 I40E_PHY_COM_REG_PAGE,
5051 led_addr, phy_addr,
5052 (u16 *)reg_val);
5053 }
5054 return status;
5055}
5056
5057
5058
5059
5060
5061
5062
5063static enum i40e_status_code i40e_led_set_reg(struct i40e_hw *hw, u16 led_addr,
5064 u32 reg_val)
5065{
5066 enum i40e_status_code status;
5067 u8 phy_addr = 0;
5068 u8 port_num;
5069 u32 i;
5070
5071 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5072 status =
5073 i40e_aq_set_phy_register(hw,
5074 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5075 I40E_PHY_COM_REG_PAGE, true,
5076 I40E_PHY_LED_PROV_REG_1,
5077 reg_val, NULL);
5078 } else {
5079 i = rd32(hw, I40E_PFGEN_PORTNUM);
5080 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5081 phy_addr = i40e_get_phy_address(hw, port_num);
5082 status = i40e_write_phy_register_clause45(hw,
5083 I40E_PHY_COM_REG_PAGE,
5084 led_addr, phy_addr,
5085 (u16)reg_val);
5086 }
5087
5088 return status;
5089}
5090
5091
5092
5093
5094
5095
5096
5097
5098i40e_status i40e_led_get_phy(struct i40e_hw *hw, u16 *led_addr,
5099 u16 *val)
5100{
5101 i40e_status status = 0;
5102 u16 gpio_led_port;
5103 u8 phy_addr = 0;
5104 u16 reg_val;
5105 u16 temp_addr;
5106 u8 port_num;
5107 u32 i;
5108 u32 reg_val_aq;
5109
5110 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE) {
5111 status =
5112 i40e_aq_get_phy_register(hw,
5113 I40E_AQ_PHY_REG_ACCESS_EXTERNAL,
5114 I40E_PHY_COM_REG_PAGE, true,
5115 I40E_PHY_LED_PROV_REG_1,
5116 ®_val_aq, NULL);
5117 if (status == I40E_SUCCESS)
5118 *val = (u16)reg_val_aq;
5119 return status;
5120 }
5121 temp_addr = I40E_PHY_LED_PROV_REG_1;
5122 i = rd32(hw, I40E_PFGEN_PORTNUM);
5123 port_num = (u8)(i & I40E_PFGEN_PORTNUM_PORT_NUM_MASK);
5124 phy_addr = i40e_get_phy_address(hw, port_num);
5125
5126 for (gpio_led_port = 0; gpio_led_port < 3; gpio_led_port++,
5127 temp_addr++) {
5128 status = i40e_read_phy_register_clause45(hw,
5129 I40E_PHY_COM_REG_PAGE,
5130 temp_addr, phy_addr,
5131 ®_val);
5132 if (status)
5133 return status;
5134 *val = reg_val;
5135 if (reg_val & I40E_PHY_LED_LINK_MODE_MASK) {
5136 *led_addr = temp_addr;
5137 break;
5138 }
5139 }
5140 return status;
5141}
5142
5143
5144
5145
5146
5147
5148
5149
5150
5151
5152
5153i40e_status i40e_led_set_phy(struct i40e_hw *hw, bool on,
5154 u16 led_addr, u32 mode)
5155{
5156 i40e_status status = 0;
5157 u32 led_ctl = 0;
5158 u32 led_reg = 0;
5159
5160 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5161 if (status)
5162 return status;
5163 led_ctl = led_reg;
5164 if (led_reg & I40E_PHY_LED_LINK_MODE_MASK) {
5165 led_reg = 0;
5166 status = i40e_led_set_reg(hw, led_addr, led_reg);
5167 if (status)
5168 return status;
5169 }
5170 status = i40e_led_get_reg(hw, led_addr, &led_reg);
5171 if (status)
5172 goto restore_config;
5173 if (on)
5174 led_reg = I40E_PHY_LED_MANUAL_ON;
5175 else
5176 led_reg = 0;
5177
5178 status = i40e_led_set_reg(hw, led_addr, led_reg);
5179 if (status)
5180 goto restore_config;
5181 if (mode & I40E_PHY_LED_MODE_ORIG) {
5182 led_ctl = (mode & I40E_PHY_LED_MODE_MASK);
5183 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5184 }
5185 return status;
5186
5187restore_config:
5188 status = i40e_led_set_reg(hw, led_addr, led_ctl);
5189 return status;
5190}
5191
5192
5193
5194
5195
5196
5197
5198
5199
5200
5201
5202i40e_status i40e_aq_rx_ctl_read_register(struct i40e_hw *hw,
5203 u32 reg_addr, u32 *reg_val,
5204 struct i40e_asq_cmd_details *cmd_details)
5205{
5206 struct i40e_aq_desc desc;
5207 struct i40e_aqc_rx_ctl_reg_read_write *cmd_resp =
5208 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5209 i40e_status status;
5210
5211 if (!reg_val)
5212 return I40E_ERR_PARAM;
5213
5214 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_read);
5215
5216 cmd_resp->address = cpu_to_le32(reg_addr);
5217
5218 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5219
5220 if (status == 0)
5221 *reg_val = le32_to_cpu(cmd_resp->value);
5222
5223 return status;
5224}
5225
5226
5227
5228
5229
5230
5231u32 i40e_read_rx_ctl(struct i40e_hw *hw, u32 reg_addr)
5232{
5233 i40e_status status = 0;
5234 bool use_register;
5235 int retry = 5;
5236 u32 val = 0;
5237
5238 use_register = (((hw->aq.api_maj_ver == 1) &&
5239 (hw->aq.api_min_ver < 5)) ||
5240 (hw->mac.type == I40E_MAC_X722));
5241 if (!use_register) {
5242do_retry:
5243 status = i40e_aq_rx_ctl_read_register(hw, reg_addr, &val, NULL);
5244 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5245 usleep_range(1000, 2000);
5246 retry--;
5247 goto do_retry;
5248 }
5249 }
5250
5251
5252 if (status || use_register)
5253 val = rd32(hw, reg_addr);
5254
5255 return val;
5256}
5257
5258
5259
5260
5261
5262
5263
5264
5265
5266
5267
5268i40e_status i40e_aq_rx_ctl_write_register(struct i40e_hw *hw,
5269 u32 reg_addr, u32 reg_val,
5270 struct i40e_asq_cmd_details *cmd_details)
5271{
5272 struct i40e_aq_desc desc;
5273 struct i40e_aqc_rx_ctl_reg_read_write *cmd =
5274 (struct i40e_aqc_rx_ctl_reg_read_write *)&desc.params.raw;
5275 i40e_status status;
5276
5277 i40e_fill_default_direct_cmd_desc(&desc, i40e_aqc_opc_rx_ctl_reg_write);
5278
5279 cmd->address = cpu_to_le32(reg_addr);
5280 cmd->value = cpu_to_le32(reg_val);
5281
5282 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5283
5284 return status;
5285}
5286
5287
5288
5289
5290
5291
5292
5293void i40e_write_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
5294{
5295 i40e_status status = 0;
5296 bool use_register;
5297 int retry = 5;
5298
5299 use_register = (((hw->aq.api_maj_ver == 1) &&
5300 (hw->aq.api_min_ver < 5)) ||
5301 (hw->mac.type == I40E_MAC_X722));
5302 if (!use_register) {
5303do_retry:
5304 status = i40e_aq_rx_ctl_write_register(hw, reg_addr,
5305 reg_val, NULL);
5306 if (hw->aq.asq_last_status == I40E_AQ_RC_EAGAIN && retry) {
5307 usleep_range(1000, 2000);
5308 retry--;
5309 goto do_retry;
5310 }
5311 }
5312
5313
5314 if (status || use_register)
5315 wr32(hw, reg_addr, reg_val);
5316}
5317
5318
5319
5320
5321
5322
5323
5324
5325static void i40e_mdio_if_number_selection(struct i40e_hw *hw, bool set_mdio,
5326 u8 mdio_num,
5327 struct i40e_aqc_phy_register_access *cmd)
5328{
5329 if (set_mdio && cmd->phy_interface == I40E_AQ_PHY_REG_ACCESS_EXTERNAL) {
5330 if (hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED)
5331 cmd->cmd_flags |=
5332 I40E_AQ_PHY_REG_ACCESS_SET_MDIO_IF_NUMBER |
5333 ((mdio_num <<
5334 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_SHIFT) &
5335 I40E_AQ_PHY_REG_ACCESS_MDIO_IF_NUMBER_MASK);
5336 else
5337 i40e_debug(hw, I40E_DEBUG_PHY,
5338 "MDIO I/F number selection not supported by current FW version.\n");
5339 }
5340}
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350
5351
5352
5353
5354
5355
5356
5357
5358enum i40e_status_code i40e_aq_set_phy_register_ext(struct i40e_hw *hw,
5359 u8 phy_select, u8 dev_addr, bool page_change,
5360 bool set_mdio, u8 mdio_num,
5361 u32 reg_addr, u32 reg_val,
5362 struct i40e_asq_cmd_details *cmd_details)
5363{
5364 struct i40e_aq_desc desc;
5365 struct i40e_aqc_phy_register_access *cmd =
5366 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5367 i40e_status status;
5368
5369 i40e_fill_default_direct_cmd_desc(&desc,
5370 i40e_aqc_opc_set_phy_register);
5371
5372 cmd->phy_interface = phy_select;
5373 cmd->dev_address = dev_addr;
5374 cmd->reg_address = cpu_to_le32(reg_addr);
5375 cmd->reg_value = cpu_to_le32(reg_val);
5376
5377 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5378
5379 if (!page_change)
5380 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5381
5382 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5383
5384 return status;
5385}
5386
5387
5388
5389
5390
5391
5392
5393
5394
5395
5396
5397
5398
5399
5400
5401
5402
5403enum i40e_status_code i40e_aq_get_phy_register_ext(struct i40e_hw *hw,
5404 u8 phy_select, u8 dev_addr, bool page_change,
5405 bool set_mdio, u8 mdio_num,
5406 u32 reg_addr, u32 *reg_val,
5407 struct i40e_asq_cmd_details *cmd_details)
5408{
5409 struct i40e_aq_desc desc;
5410 struct i40e_aqc_phy_register_access *cmd =
5411 (struct i40e_aqc_phy_register_access *)&desc.params.raw;
5412 i40e_status status;
5413
5414 i40e_fill_default_direct_cmd_desc(&desc,
5415 i40e_aqc_opc_get_phy_register);
5416
5417 cmd->phy_interface = phy_select;
5418 cmd->dev_address = dev_addr;
5419 cmd->reg_address = cpu_to_le32(reg_addr);
5420
5421 i40e_mdio_if_number_selection(hw, set_mdio, mdio_num, cmd);
5422
5423 if (!page_change)
5424 cmd->cmd_flags = I40E_AQ_PHY_REG_ACCESS_DONT_CHANGE_QSFP_PAGE;
5425
5426 status = i40e_asq_send_command(hw, &desc, NULL, 0, cmd_details);
5427 if (!status)
5428 *reg_val = le32_to_cpu(cmd->reg_value);
5429
5430 return status;
5431}
5432
5433
5434
5435
5436
5437
5438
5439
5440
5441
5442
5443enum
5444i40e_status_code i40e_aq_write_ddp(struct i40e_hw *hw, void *buff,
5445 u16 buff_size, u32 track_id,
5446 u32 *error_offset, u32 *error_info,
5447 struct i40e_asq_cmd_details *cmd_details)
5448{
5449 struct i40e_aq_desc desc;
5450 struct i40e_aqc_write_personalization_profile *cmd =
5451 (struct i40e_aqc_write_personalization_profile *)
5452 &desc.params.raw;
5453 struct i40e_aqc_write_ddp_resp *resp;
5454 i40e_status status;
5455
5456 i40e_fill_default_direct_cmd_desc(&desc,
5457 i40e_aqc_opc_write_personalization_profile);
5458
5459 desc.flags |= cpu_to_le16(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD);
5460 if (buff_size > I40E_AQ_LARGE_BUF)
5461 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5462
5463 desc.datalen = cpu_to_le16(buff_size);
5464
5465 cmd->profile_track_id = cpu_to_le32(track_id);
5466
5467 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5468 if (!status) {
5469 resp = (struct i40e_aqc_write_ddp_resp *)&desc.params.raw;
5470 if (error_offset)
5471 *error_offset = le32_to_cpu(resp->error_offset);
5472 if (error_info)
5473 *error_info = le32_to_cpu(resp->error_info);
5474 }
5475
5476 return status;
5477}
5478
5479
5480
5481
5482
5483
5484
5485
5486
5487enum
5488i40e_status_code i40e_aq_get_ddp_list(struct i40e_hw *hw, void *buff,
5489 u16 buff_size, u8 flags,
5490 struct i40e_asq_cmd_details *cmd_details)
5491{
5492 struct i40e_aq_desc desc;
5493 struct i40e_aqc_get_applied_profiles *cmd =
5494 (struct i40e_aqc_get_applied_profiles *)&desc.params.raw;
5495 i40e_status status;
5496
5497 i40e_fill_default_direct_cmd_desc(&desc,
5498 i40e_aqc_opc_get_personalization_profile_list);
5499
5500 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_BUF);
5501 if (buff_size > I40E_AQ_LARGE_BUF)
5502 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5503 desc.datalen = cpu_to_le16(buff_size);
5504
5505 cmd->flags = flags;
5506
5507 status = i40e_asq_send_command(hw, &desc, buff, buff_size, cmd_details);
5508
5509 return status;
5510}
5511
5512
5513
5514
5515
5516
5517
5518
5519
5520
5521struct i40e_generic_seg_header *
5522i40e_find_segment_in_package(u32 segment_type,
5523 struct i40e_package_header *pkg_hdr)
5524{
5525 struct i40e_generic_seg_header *segment;
5526 u32 i;
5527
5528
5529 for (i = 0; i < pkg_hdr->segment_count; i++) {
5530 segment =
5531 (struct i40e_generic_seg_header *)((u8 *)pkg_hdr +
5532 pkg_hdr->segment_offset[i]);
5533
5534 if (segment->type == segment_type)
5535 return segment;
5536 }
5537
5538 return NULL;
5539}
5540
5541
5542#define I40E_SECTION_TABLE(profile, sec_tbl) \
5543 do { \
5544 struct i40e_profile_segment *p = (profile); \
5545 u32 count; \
5546 u32 *nvm; \
5547 count = p->device_table_count; \
5548 nvm = (u32 *)&p->device_table[count]; \
5549 sec_tbl = (struct i40e_section_table *)&nvm[nvm[0] + 1]; \
5550 } while (0)
5551
5552
5553#define I40E_SECTION_HEADER(profile, offset) \
5554 (struct i40e_profile_section_header *)((u8 *)(profile) + (offset))
5555
5556
5557
5558
5559
5560
5561
5562
5563
5564
5565struct i40e_profile_section_header *
5566i40e_find_section_in_profile(u32 section_type,
5567 struct i40e_profile_segment *profile)
5568{
5569 struct i40e_profile_section_header *sec;
5570 struct i40e_section_table *sec_tbl;
5571 u32 sec_off;
5572 u32 i;
5573
5574 if (profile->header.type != SEGMENT_TYPE_I40E)
5575 return NULL;
5576
5577 I40E_SECTION_TABLE(profile, sec_tbl);
5578
5579 for (i = 0; i < sec_tbl->section_count; i++) {
5580 sec_off = sec_tbl->section_offset[i];
5581 sec = I40E_SECTION_HEADER(profile, sec_off);
5582 if (sec->section.type == section_type)
5583 return sec;
5584 }
5585
5586 return NULL;
5587}
5588
5589
5590
5591
5592
5593
5594static enum
5595i40e_status_code i40e_ddp_exec_aq_section(struct i40e_hw *hw,
5596 struct i40e_profile_aq_section *aq)
5597{
5598 i40e_status status;
5599 struct i40e_aq_desc desc;
5600 u8 *msg = NULL;
5601 u16 msglen;
5602
5603 i40e_fill_default_direct_cmd_desc(&desc, aq->opcode);
5604 desc.flags |= cpu_to_le16(aq->flags);
5605 memcpy(desc.params.raw, aq->param, sizeof(desc.params.raw));
5606
5607 msglen = aq->datalen;
5608 if (msglen) {
5609 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF |
5610 I40E_AQ_FLAG_RD));
5611 if (msglen > I40E_AQ_LARGE_BUF)
5612 desc.flags |= cpu_to_le16((u16)I40E_AQ_FLAG_LB);
5613 desc.datalen = cpu_to_le16(msglen);
5614 msg = &aq->data[0];
5615 }
5616
5617 status = i40e_asq_send_command(hw, &desc, msg, msglen, NULL);
5618
5619 if (status) {
5620 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5621 "unable to exec DDP AQ opcode %u, error %d\n",
5622 aq->opcode, status);
5623 return status;
5624 }
5625
5626
5627 memcpy(aq->param, desc.params.raw, sizeof(desc.params.raw));
5628
5629 return 0;
5630}
5631
5632
5633
5634
5635
5636
5637
5638
5639
5640
5641static enum i40e_status_code
5642i40e_validate_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5643 u32 track_id, bool rollback)
5644{
5645 struct i40e_profile_section_header *sec = NULL;
5646 i40e_status status = 0;
5647 struct i40e_section_table *sec_tbl;
5648 u32 vendor_dev_id;
5649 u32 dev_cnt;
5650 u32 sec_off;
5651 u32 i;
5652
5653 if (track_id == I40E_DDP_TRACKID_INVALID) {
5654 i40e_debug(hw, I40E_DEBUG_PACKAGE, "Invalid track_id\n");
5655 return I40E_NOT_SUPPORTED;
5656 }
5657
5658 dev_cnt = profile->device_table_count;
5659 for (i = 0; i < dev_cnt; i++) {
5660 vendor_dev_id = profile->device_table[i].vendor_dev_id;
5661 if ((vendor_dev_id >> 16) == PCI_VENDOR_ID_INTEL &&
5662 hw->device_id == (vendor_dev_id & 0xFFFF))
5663 break;
5664 }
5665 if (dev_cnt && i == dev_cnt) {
5666 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5667 "Device doesn't support DDP\n");
5668 return I40E_ERR_DEVICE_NOT_SUPPORTED;
5669 }
5670
5671 I40E_SECTION_TABLE(profile, sec_tbl);
5672
5673
5674 for (i = 0; i < sec_tbl->section_count; i++) {
5675 sec_off = sec_tbl->section_offset[i];
5676 sec = I40E_SECTION_HEADER(profile, sec_off);
5677 if (rollback) {
5678 if (sec->section.type == SECTION_TYPE_MMIO ||
5679 sec->section.type == SECTION_TYPE_AQ ||
5680 sec->section.type == SECTION_TYPE_RB_AQ) {
5681 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5682 "Not a roll-back package\n");
5683 return I40E_NOT_SUPPORTED;
5684 }
5685 } else {
5686 if (sec->section.type == SECTION_TYPE_RB_AQ ||
5687 sec->section.type == SECTION_TYPE_RB_MMIO) {
5688 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5689 "Not an original package\n");
5690 return I40E_NOT_SUPPORTED;
5691 }
5692 }
5693 }
5694
5695 return status;
5696}
5697
5698
5699
5700
5701
5702
5703
5704
5705
5706enum i40e_status_code
5707i40e_write_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5708 u32 track_id)
5709{
5710 i40e_status status = 0;
5711 struct i40e_section_table *sec_tbl;
5712 struct i40e_profile_section_header *sec = NULL;
5713 struct i40e_profile_aq_section *ddp_aq;
5714 u32 section_size = 0;
5715 u32 offset = 0, info = 0;
5716 u32 sec_off;
5717 u32 i;
5718
5719 status = i40e_validate_profile(hw, profile, track_id, false);
5720 if (status)
5721 return status;
5722
5723 I40E_SECTION_TABLE(profile, sec_tbl);
5724
5725 for (i = 0; i < sec_tbl->section_count; i++) {
5726 sec_off = sec_tbl->section_offset[i];
5727 sec = I40E_SECTION_HEADER(profile, sec_off);
5728
5729 if (sec->section.type == SECTION_TYPE_AQ) {
5730 ddp_aq = (struct i40e_profile_aq_section *)&sec[1];
5731 status = i40e_ddp_exec_aq_section(hw, ddp_aq);
5732 if (status) {
5733 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5734 "Failed to execute aq: section %d, opcode %u\n",
5735 i, ddp_aq->opcode);
5736 break;
5737 }
5738 sec->section.type = SECTION_TYPE_RB_AQ;
5739 }
5740
5741
5742 if (sec->section.type != SECTION_TYPE_MMIO)
5743 continue;
5744
5745 section_size = sec->section.size +
5746 sizeof(struct i40e_profile_section_header);
5747
5748
5749 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5750 track_id, &offset, &info, NULL);
5751 if (status) {
5752 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5753 "Failed to write profile: section %d, offset %d, info %d\n",
5754 i, offset, info);
5755 break;
5756 }
5757 }
5758 return status;
5759}
5760
5761
5762
5763
5764
5765
5766
5767
5768
5769enum i40e_status_code
5770i40e_rollback_profile(struct i40e_hw *hw, struct i40e_profile_segment *profile,
5771 u32 track_id)
5772{
5773 struct i40e_profile_section_header *sec = NULL;
5774 i40e_status status = 0;
5775 struct i40e_section_table *sec_tbl;
5776 u32 offset = 0, info = 0;
5777 u32 section_size = 0;
5778 u32 sec_off;
5779 int i;
5780
5781 status = i40e_validate_profile(hw, profile, track_id, true);
5782 if (status)
5783 return status;
5784
5785 I40E_SECTION_TABLE(profile, sec_tbl);
5786
5787
5788 for (i = sec_tbl->section_count - 1; i >= 0; i--) {
5789 sec_off = sec_tbl->section_offset[i];
5790 sec = I40E_SECTION_HEADER(profile, sec_off);
5791
5792
5793 if (sec->section.type != SECTION_TYPE_RB_MMIO)
5794 continue;
5795
5796 section_size = sec->section.size +
5797 sizeof(struct i40e_profile_section_header);
5798
5799
5800 status = i40e_aq_write_ddp(hw, (void *)sec, (u16)section_size,
5801 track_id, &offset, &info, NULL);
5802 if (status) {
5803 i40e_debug(hw, I40E_DEBUG_PACKAGE,
5804 "Failed to write profile: section %d, offset %d, info %d\n",
5805 i, offset, info);
5806 break;
5807 }
5808 }
5809 return status;
5810}
5811
5812
5813
5814
5815
5816
5817
5818
5819
5820
5821enum i40e_status_code
5822i40e_add_pinfo_to_list(struct i40e_hw *hw,
5823 struct i40e_profile_segment *profile,
5824 u8 *profile_info_sec, u32 track_id)
5825{
5826 i40e_status status = 0;
5827 struct i40e_profile_section_header *sec = NULL;
5828 struct i40e_profile_info *pinfo;
5829 u32 offset = 0, info = 0;
5830
5831 sec = (struct i40e_profile_section_header *)profile_info_sec;
5832 sec->tbl_size = 1;
5833 sec->data_end = sizeof(struct i40e_profile_section_header) +
5834 sizeof(struct i40e_profile_info);
5835 sec->section.type = SECTION_TYPE_INFO;
5836 sec->section.offset = sizeof(struct i40e_profile_section_header);
5837 sec->section.size = sizeof(struct i40e_profile_info);
5838 pinfo = (struct i40e_profile_info *)(profile_info_sec +
5839 sec->section.offset);
5840 pinfo->track_id = track_id;
5841 pinfo->version = profile->version;
5842 pinfo->op = I40E_DDP_ADD_TRACKID;
5843 memcpy(pinfo->name, profile->name, I40E_DDP_NAME_SIZE);
5844
5845 status = i40e_aq_write_ddp(hw, (void *)sec, sec->data_end,
5846 track_id, &offset, &info, NULL);
5847
5848 return status;
5849}
5850
5851
5852
5853
5854
5855
5856
5857
5858
5859
5860
5861
5862
5863enum i40e_status_code
5864i40e_aq_add_cloud_filters(struct i40e_hw *hw, u16 seid,
5865 struct i40e_aqc_cloud_filters_element_data *filters,
5866 u8 filter_count)
5867{
5868 struct i40e_aq_desc desc;
5869 struct i40e_aqc_add_remove_cloud_filters *cmd =
5870 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5871 enum i40e_status_code status;
5872 u16 buff_len;
5873
5874 i40e_fill_default_direct_cmd_desc(&desc,
5875 i40e_aqc_opc_add_cloud_filters);
5876
5877 buff_len = filter_count * sizeof(*filters);
5878 desc.datalen = cpu_to_le16(buff_len);
5879 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5880 cmd->num_filters = filter_count;
5881 cmd->seid = cpu_to_le16(seid);
5882
5883 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5884
5885 return status;
5886}
5887
5888
5889
5890
5891
5892
5893
5894
5895
5896
5897
5898
5899
5900enum i40e_status_code
5901i40e_aq_add_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5902 struct i40e_aqc_cloud_filters_element_bb *filters,
5903 u8 filter_count)
5904{
5905 struct i40e_aq_desc desc;
5906 struct i40e_aqc_add_remove_cloud_filters *cmd =
5907 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5908 i40e_status status;
5909 u16 buff_len;
5910 int i;
5911
5912 i40e_fill_default_direct_cmd_desc(&desc,
5913 i40e_aqc_opc_add_cloud_filters);
5914
5915 buff_len = filter_count * sizeof(*filters);
5916 desc.datalen = cpu_to_le16(buff_len);
5917 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5918 cmd->num_filters = filter_count;
5919 cmd->seid = cpu_to_le16(seid);
5920 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
5921
5922 for (i = 0; i < filter_count; i++) {
5923 u16 tnl_type;
5924 u32 ti;
5925
5926 tnl_type = (le16_to_cpu(filters[i].element.flags) &
5927 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
5928 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
5929
5930
5931
5932
5933
5934 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
5935 ti = le32_to_cpu(filters[i].element.tenant_id);
5936 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
5937 }
5938 }
5939
5940 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5941
5942 return status;
5943}
5944
5945
5946
5947
5948
5949
5950
5951
5952
5953
5954
5955
5956
5957enum i40e_status_code
5958i40e_aq_rem_cloud_filters(struct i40e_hw *hw, u16 seid,
5959 struct i40e_aqc_cloud_filters_element_data *filters,
5960 u8 filter_count)
5961{
5962 struct i40e_aq_desc desc;
5963 struct i40e_aqc_add_remove_cloud_filters *cmd =
5964 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
5965 enum i40e_status_code status;
5966 u16 buff_len;
5967
5968 i40e_fill_default_direct_cmd_desc(&desc,
5969 i40e_aqc_opc_remove_cloud_filters);
5970
5971 buff_len = filter_count * sizeof(*filters);
5972 desc.datalen = cpu_to_le16(buff_len);
5973 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
5974 cmd->num_filters = filter_count;
5975 cmd->seid = cpu_to_le16(seid);
5976
5977 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
5978
5979 return status;
5980}
5981
5982
5983
5984
5985
5986
5987
5988
5989
5990
5991
5992
5993
5994enum i40e_status_code
5995i40e_aq_rem_cloud_filters_bb(struct i40e_hw *hw, u16 seid,
5996 struct i40e_aqc_cloud_filters_element_bb *filters,
5997 u8 filter_count)
5998{
5999 struct i40e_aq_desc desc;
6000 struct i40e_aqc_add_remove_cloud_filters *cmd =
6001 (struct i40e_aqc_add_remove_cloud_filters *)&desc.params.raw;
6002 i40e_status status;
6003 u16 buff_len;
6004 int i;
6005
6006 i40e_fill_default_direct_cmd_desc(&desc,
6007 i40e_aqc_opc_remove_cloud_filters);
6008
6009 buff_len = filter_count * sizeof(*filters);
6010 desc.datalen = cpu_to_le16(buff_len);
6011 desc.flags |= cpu_to_le16((u16)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6012 cmd->num_filters = filter_count;
6013 cmd->seid = cpu_to_le16(seid);
6014 cmd->big_buffer_flag = I40E_AQC_ADD_CLOUD_CMD_BB;
6015
6016 for (i = 0; i < filter_count; i++) {
6017 u16 tnl_type;
6018 u32 ti;
6019
6020 tnl_type = (le16_to_cpu(filters[i].element.flags) &
6021 I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK) >>
6022 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT;
6023
6024
6025
6026
6027
6028 if (tnl_type == I40E_AQC_ADD_CLOUD_TNL_TYPE_GENEVE) {
6029 ti = le32_to_cpu(filters[i].element.tenant_id);
6030 filters[i].element.tenant_id = cpu_to_le32(ti << 8);
6031 }
6032 }
6033
6034 status = i40e_asq_send_command(hw, &desc, filters, buff_len, NULL);
6035
6036 return status;
6037}
6038
