linux/drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
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   1/* SPDX-License-Identifier: GPL-2.0+ */
   2// Copyright (c) 2016-2017 Hisilicon Limited.
   3
   4#ifndef __HCLGE_CMD_H
   5#define __HCLGE_CMD_H
   6#include <linux/types.h>
   7#include <linux/io.h>
   8#include <linux/etherdevice.h>
   9#include "hnae3.h"
  10
  11#define HCLGE_CMDQ_TX_TIMEOUT           30000
  12#define HCLGE_CMDQ_CLEAR_WAIT_TIME      200
  13#define HCLGE_DESC_DATA_LEN             6
  14
  15struct hclge_dev;
  16struct hclge_desc {
  17        __le16 opcode;
  18
  19#define HCLGE_CMDQ_RX_INVLD_B           0
  20#define HCLGE_CMDQ_RX_OUTVLD_B          1
  21
  22        __le16 flag;
  23        __le16 retval;
  24        __le16 rsv;
  25        __le32 data[HCLGE_DESC_DATA_LEN];
  26};
  27
  28struct hclge_cmq_ring {
  29        dma_addr_t desc_dma_addr;
  30        struct hclge_desc *desc;
  31        struct hclge_dev *dev;
  32        u32 head;
  33        u32 tail;
  34
  35        u16 buf_size;
  36        u16 desc_num;
  37        int next_to_use;
  38        int next_to_clean;
  39        u8 ring_type; /* cmq ring type */
  40        spinlock_t lock; /* Command queue lock */
  41};
  42
  43enum hclge_cmd_return_status {
  44        HCLGE_CMD_EXEC_SUCCESS  = 0,
  45        HCLGE_CMD_NO_AUTH       = 1,
  46        HCLGE_CMD_NOT_SUPPORTED = 2,
  47        HCLGE_CMD_QUEUE_FULL    = 3,
  48        HCLGE_CMD_NEXT_ERR      = 4,
  49        HCLGE_CMD_UNEXE_ERR     = 5,
  50        HCLGE_CMD_PARA_ERR      = 6,
  51        HCLGE_CMD_RESULT_ERR    = 7,
  52        HCLGE_CMD_TIMEOUT       = 8,
  53        HCLGE_CMD_HILINK_ERR    = 9,
  54        HCLGE_CMD_QUEUE_ILLEGAL = 10,
  55        HCLGE_CMD_INVALID       = 11,
  56};
  57
  58enum hclge_cmd_status {
  59        HCLGE_STATUS_SUCCESS    = 0,
  60        HCLGE_ERR_CSQ_FULL      = -1,
  61        HCLGE_ERR_CSQ_TIMEOUT   = -2,
  62        HCLGE_ERR_CSQ_ERROR     = -3,
  63};
  64
  65struct hclge_misc_vector {
  66        u8 __iomem *addr;
  67        int vector_irq;
  68        char name[HNAE3_INT_NAME_LEN];
  69};
  70
  71struct hclge_cmq {
  72        struct hclge_cmq_ring csq;
  73        struct hclge_cmq_ring crq;
  74        u16 tx_timeout;
  75        enum hclge_cmd_status last_status;
  76};
  77
  78#define HCLGE_CMD_FLAG_IN       BIT(0)
  79#define HCLGE_CMD_FLAG_OUT      BIT(1)
  80#define HCLGE_CMD_FLAG_NEXT     BIT(2)
  81#define HCLGE_CMD_FLAG_WR       BIT(3)
  82#define HCLGE_CMD_FLAG_NO_INTR  BIT(4)
  83#define HCLGE_CMD_FLAG_ERR_INTR BIT(5)
  84
  85enum hclge_opcode_type {
  86        /* Generic commands */
  87        HCLGE_OPC_QUERY_FW_VER          = 0x0001,
  88        HCLGE_OPC_CFG_RST_TRIGGER       = 0x0020,
  89        HCLGE_OPC_GBL_RST_STATUS        = 0x0021,
  90        HCLGE_OPC_QUERY_FUNC_STATUS     = 0x0022,
  91        HCLGE_OPC_QUERY_PF_RSRC         = 0x0023,
  92        HCLGE_OPC_QUERY_VF_RSRC         = 0x0024,
  93        HCLGE_OPC_GET_CFG_PARAM         = 0x0025,
  94        HCLGE_OPC_PF_RST_DONE           = 0x0026,
  95        HCLGE_OPC_QUERY_VF_RST_RDY      = 0x0027,
  96
  97        HCLGE_OPC_STATS_64_BIT          = 0x0030,
  98        HCLGE_OPC_STATS_32_BIT          = 0x0031,
  99        HCLGE_OPC_STATS_MAC             = 0x0032,
 100        HCLGE_OPC_QUERY_MAC_REG_NUM     = 0x0033,
 101        HCLGE_OPC_STATS_MAC_ALL         = 0x0034,
 102
 103        HCLGE_OPC_QUERY_REG_NUM         = 0x0040,
 104        HCLGE_OPC_QUERY_32_BIT_REG      = 0x0041,
 105        HCLGE_OPC_QUERY_64_BIT_REG      = 0x0042,
 106        HCLGE_OPC_DFX_BD_NUM            = 0x0043,
 107        HCLGE_OPC_DFX_BIOS_COMMON_REG   = 0x0044,
 108        HCLGE_OPC_DFX_SSU_REG_0         = 0x0045,
 109        HCLGE_OPC_DFX_SSU_REG_1         = 0x0046,
 110        HCLGE_OPC_DFX_IGU_EGU_REG       = 0x0047,
 111        HCLGE_OPC_DFX_RPU_REG_0         = 0x0048,
 112        HCLGE_OPC_DFX_RPU_REG_1         = 0x0049,
 113        HCLGE_OPC_DFX_NCSI_REG          = 0x004A,
 114        HCLGE_OPC_DFX_RTC_REG           = 0x004B,
 115        HCLGE_OPC_DFX_PPP_REG           = 0x004C,
 116        HCLGE_OPC_DFX_RCB_REG           = 0x004D,
 117        HCLGE_OPC_DFX_TQP_REG           = 0x004E,
 118        HCLGE_OPC_DFX_SSU_REG_2         = 0x004F,
 119
 120        HCLGE_OPC_QUERY_DEV_SPECS       = 0x0050,
 121
 122        /* MAC command */
 123        HCLGE_OPC_CONFIG_MAC_MODE       = 0x0301,
 124        HCLGE_OPC_CONFIG_AN_MODE        = 0x0304,
 125        HCLGE_OPC_QUERY_LINK_STATUS     = 0x0307,
 126        HCLGE_OPC_CONFIG_MAX_FRM_SIZE   = 0x0308,
 127        HCLGE_OPC_CONFIG_SPEED_DUP      = 0x0309,
 128        HCLGE_OPC_QUERY_MAC_TNL_INT     = 0x0310,
 129        HCLGE_OPC_MAC_TNL_INT_EN        = 0x0311,
 130        HCLGE_OPC_CLEAR_MAC_TNL_INT     = 0x0312,
 131        HCLGE_OPC_COMMON_LOOPBACK       = 0x0315,
 132        HCLGE_OPC_CONFIG_FEC_MODE       = 0x031A,
 133
 134        /* PTP commands */
 135        HCLGE_OPC_PTP_INT_EN            = 0x0501,
 136        HCLGE_OPC_PTP_MODE_CFG          = 0x0507,
 137
 138        /* PFC/Pause commands */
 139        HCLGE_OPC_CFG_MAC_PAUSE_EN      = 0x0701,
 140        HCLGE_OPC_CFG_PFC_PAUSE_EN      = 0x0702,
 141        HCLGE_OPC_CFG_MAC_PARA          = 0x0703,
 142        HCLGE_OPC_CFG_PFC_PARA          = 0x0704,
 143        HCLGE_OPC_QUERY_MAC_TX_PKT_CNT  = 0x0705,
 144        HCLGE_OPC_QUERY_MAC_RX_PKT_CNT  = 0x0706,
 145        HCLGE_OPC_QUERY_PFC_TX_PKT_CNT  = 0x0707,
 146        HCLGE_OPC_QUERY_PFC_RX_PKT_CNT  = 0x0708,
 147        HCLGE_OPC_PRI_TO_TC_MAPPING     = 0x0709,
 148        HCLGE_OPC_QOS_MAP               = 0x070A,
 149
 150        /* ETS/scheduler commands */
 151        HCLGE_OPC_TM_PG_TO_PRI_LINK     = 0x0804,
 152        HCLGE_OPC_TM_QS_TO_PRI_LINK     = 0x0805,
 153        HCLGE_OPC_TM_NQ_TO_QS_LINK      = 0x0806,
 154        HCLGE_OPC_TM_RQ_TO_QS_LINK      = 0x0807,
 155        HCLGE_OPC_TM_PORT_WEIGHT        = 0x0808,
 156        HCLGE_OPC_TM_PG_WEIGHT          = 0x0809,
 157        HCLGE_OPC_TM_QS_WEIGHT          = 0x080A,
 158        HCLGE_OPC_TM_PRI_WEIGHT         = 0x080B,
 159        HCLGE_OPC_TM_PRI_C_SHAPPING     = 0x080C,
 160        HCLGE_OPC_TM_PRI_P_SHAPPING     = 0x080D,
 161        HCLGE_OPC_TM_PG_C_SHAPPING      = 0x080E,
 162        HCLGE_OPC_TM_PG_P_SHAPPING      = 0x080F,
 163        HCLGE_OPC_TM_PORT_SHAPPING      = 0x0810,
 164        HCLGE_OPC_TM_PG_SCH_MODE_CFG    = 0x0812,
 165        HCLGE_OPC_TM_PRI_SCH_MODE_CFG   = 0x0813,
 166        HCLGE_OPC_TM_QS_SCH_MODE_CFG    = 0x0814,
 167        HCLGE_OPC_TM_BP_TO_QSET_MAPPING = 0x0815,
 168        HCLGE_OPC_TM_NODES              = 0x0816,
 169        HCLGE_OPC_ETS_TC_WEIGHT         = 0x0843,
 170        HCLGE_OPC_QSET_DFX_STS          = 0x0844,
 171        HCLGE_OPC_PRI_DFX_STS           = 0x0845,
 172        HCLGE_OPC_PG_DFX_STS            = 0x0846,
 173        HCLGE_OPC_PORT_DFX_STS          = 0x0847,
 174        HCLGE_OPC_SCH_NQ_CNT            = 0x0848,
 175        HCLGE_OPC_SCH_RQ_CNT            = 0x0849,
 176        HCLGE_OPC_TM_INTERNAL_STS       = 0x0850,
 177        HCLGE_OPC_TM_INTERNAL_CNT       = 0x0851,
 178        HCLGE_OPC_TM_INTERNAL_STS_1     = 0x0852,
 179
 180        /* Packet buffer allocate commands */
 181        HCLGE_OPC_TX_BUFF_ALLOC         = 0x0901,
 182        HCLGE_OPC_RX_PRIV_BUFF_ALLOC    = 0x0902,
 183        HCLGE_OPC_RX_PRIV_WL_ALLOC      = 0x0903,
 184        HCLGE_OPC_RX_COM_THRD_ALLOC     = 0x0904,
 185        HCLGE_OPC_RX_COM_WL_ALLOC       = 0x0905,
 186        HCLGE_OPC_RX_GBL_PKT_CNT        = 0x0906,
 187
 188        /* TQP management command */
 189        HCLGE_OPC_SET_TQP_MAP           = 0x0A01,
 190
 191        /* TQP commands */
 192        HCLGE_OPC_CFG_TX_QUEUE          = 0x0B01,
 193        HCLGE_OPC_QUERY_TX_POINTER      = 0x0B02,
 194        HCLGE_OPC_QUERY_TX_STATS        = 0x0B03,
 195        HCLGE_OPC_TQP_TX_QUEUE_TC       = 0x0B04,
 196        HCLGE_OPC_CFG_RX_QUEUE          = 0x0B11,
 197        HCLGE_OPC_QUERY_RX_POINTER      = 0x0B12,
 198        HCLGE_OPC_QUERY_RX_STATS        = 0x0B13,
 199        HCLGE_OPC_STASH_RX_QUEUE_LRO    = 0x0B16,
 200        HCLGE_OPC_CFG_RX_QUEUE_LRO      = 0x0B17,
 201        HCLGE_OPC_CFG_COM_TQP_QUEUE     = 0x0B20,
 202        HCLGE_OPC_RESET_TQP_QUEUE       = 0x0B22,
 203
 204        /* PPU commands */
 205        HCLGE_OPC_PPU_PF_OTHER_INT_DFX  = 0x0B4A,
 206
 207        /* TSO command */
 208        HCLGE_OPC_TSO_GENERIC_CONFIG    = 0x0C01,
 209        HCLGE_OPC_GRO_GENERIC_CONFIG    = 0x0C10,
 210
 211        /* RSS commands */
 212        HCLGE_OPC_RSS_GENERIC_CONFIG    = 0x0D01,
 213        HCLGE_OPC_RSS_INDIR_TABLE       = 0x0D07,
 214        HCLGE_OPC_RSS_TC_MODE           = 0x0D08,
 215        HCLGE_OPC_RSS_INPUT_TUPLE       = 0x0D02,
 216
 217        /* Promisuous mode command */
 218        HCLGE_OPC_CFG_PROMISC_MODE      = 0x0E01,
 219
 220        /* Vlan offload commands */
 221        HCLGE_OPC_VLAN_PORT_TX_CFG      = 0x0F01,
 222        HCLGE_OPC_VLAN_PORT_RX_CFG      = 0x0F02,
 223
 224        /* Interrupts commands */
 225        HCLGE_OPC_ADD_RING_TO_VECTOR    = 0x1503,
 226        HCLGE_OPC_DEL_RING_TO_VECTOR    = 0x1504,
 227
 228        /* MAC commands */
 229        HCLGE_OPC_MAC_VLAN_ADD              = 0x1000,
 230        HCLGE_OPC_MAC_VLAN_REMOVE           = 0x1001,
 231        HCLGE_OPC_MAC_VLAN_TYPE_ID          = 0x1002,
 232        HCLGE_OPC_MAC_VLAN_INSERT           = 0x1003,
 233        HCLGE_OPC_MAC_VLAN_ALLOCATE         = 0x1004,
 234        HCLGE_OPC_MAC_ETHTYPE_ADD           = 0x1010,
 235        HCLGE_OPC_MAC_ETHTYPE_REMOVE    = 0x1011,
 236
 237        /* MAC VLAN commands */
 238        HCLGE_OPC_MAC_VLAN_SWITCH_PARAM = 0x1033,
 239
 240        /* VLAN commands */
 241        HCLGE_OPC_VLAN_FILTER_CTRL          = 0x1100,
 242        HCLGE_OPC_VLAN_FILTER_PF_CFG    = 0x1101,
 243        HCLGE_OPC_VLAN_FILTER_VF_CFG    = 0x1102,
 244        HCLGE_OPC_PORT_VLAN_BYPASS      = 0x1103,
 245
 246        /* Flow Director commands */
 247        HCLGE_OPC_FD_MODE_CTRL          = 0x1200,
 248        HCLGE_OPC_FD_GET_ALLOCATION     = 0x1201,
 249        HCLGE_OPC_FD_KEY_CONFIG         = 0x1202,
 250        HCLGE_OPC_FD_TCAM_OP            = 0x1203,
 251        HCLGE_OPC_FD_AD_OP              = 0x1204,
 252        HCLGE_OPC_FD_CNT_OP             = 0x1205,
 253        HCLGE_OPC_FD_USER_DEF_OP        = 0x1207,
 254
 255        /* MDIO command */
 256        HCLGE_OPC_MDIO_CONFIG           = 0x1900,
 257
 258        /* QCN commands */
 259        HCLGE_OPC_QCN_MOD_CFG           = 0x1A01,
 260        HCLGE_OPC_QCN_GRP_TMPLT_CFG     = 0x1A02,
 261        HCLGE_OPC_QCN_SHAPPING_CFG      = 0x1A03,
 262        HCLGE_OPC_QCN_SHAPPING_BS_CFG   = 0x1A04,
 263        HCLGE_OPC_QCN_QSET_LINK_CFG     = 0x1A05,
 264        HCLGE_OPC_QCN_RP_STATUS_GET     = 0x1A06,
 265        HCLGE_OPC_QCN_AJUST_INIT        = 0x1A07,
 266        HCLGE_OPC_QCN_DFX_CNT_STATUS    = 0x1A08,
 267
 268        /* Mailbox command */
 269        HCLGEVF_OPC_MBX_PF_TO_VF        = 0x2000,
 270
 271        /* Led command */
 272        HCLGE_OPC_LED_STATUS_CFG        = 0xB000,
 273
 274        /* clear hardware resource command */
 275        HCLGE_OPC_CLEAR_HW_RESOURCE     = 0x700B,
 276
 277        /* NCL config command */
 278        HCLGE_OPC_QUERY_NCL_CONFIG      = 0x7011,
 279
 280        /* IMP stats command */
 281        HCLGE_OPC_IMP_STATS_BD          = 0x7012,
 282        HCLGE_OPC_IMP_STATS_INFO                = 0x7013,
 283        HCLGE_OPC_IMP_COMPAT_CFG                = 0x701A,
 284
 285        /* SFP command */
 286        HCLGE_OPC_GET_SFP_EEPROM        = 0x7100,
 287        HCLGE_OPC_GET_SFP_EXIST         = 0x7101,
 288        HCLGE_OPC_GET_SFP_INFO          = 0x7104,
 289
 290        /* Error INT commands */
 291        HCLGE_MAC_COMMON_INT_EN         = 0x030E,
 292        HCLGE_TM_SCH_ECC_INT_EN         = 0x0829,
 293        HCLGE_SSU_ECC_INT_CMD           = 0x0989,
 294        HCLGE_SSU_COMMON_INT_CMD        = 0x098C,
 295        HCLGE_PPU_MPF_ECC_INT_CMD       = 0x0B40,
 296        HCLGE_PPU_MPF_OTHER_INT_CMD     = 0x0B41,
 297        HCLGE_PPU_PF_OTHER_INT_CMD      = 0x0B42,
 298        HCLGE_COMMON_ECC_INT_CFG        = 0x1505,
 299        HCLGE_QUERY_RAS_INT_STS_BD_NUM  = 0x1510,
 300        HCLGE_QUERY_CLEAR_MPF_RAS_INT   = 0x1511,
 301        HCLGE_QUERY_CLEAR_PF_RAS_INT    = 0x1512,
 302        HCLGE_QUERY_MSIX_INT_STS_BD_NUM = 0x1513,
 303        HCLGE_QUERY_CLEAR_ALL_MPF_MSIX_INT      = 0x1514,
 304        HCLGE_QUERY_CLEAR_ALL_PF_MSIX_INT       = 0x1515,
 305        HCLGE_QUERY_ALL_ERR_BD_NUM              = 0x1516,
 306        HCLGE_QUERY_ALL_ERR_INFO                = 0x1517,
 307        HCLGE_CONFIG_ROCEE_RAS_INT_EN   = 0x1580,
 308        HCLGE_QUERY_CLEAR_ROCEE_RAS_INT = 0x1581,
 309        HCLGE_ROCEE_PF_RAS_INT_CMD      = 0x1584,
 310        HCLGE_QUERY_ROCEE_ECC_RAS_INFO_CMD      = 0x1585,
 311        HCLGE_QUERY_ROCEE_AXI_RAS_INFO_CMD      = 0x1586,
 312        HCLGE_IGU_EGU_TNL_INT_EN        = 0x1803,
 313        HCLGE_IGU_COMMON_INT_EN         = 0x1806,
 314        HCLGE_TM_QCN_MEM_INT_CFG        = 0x1A14,
 315        HCLGE_PPP_CMD0_INT_CMD          = 0x2100,
 316        HCLGE_PPP_CMD1_INT_CMD          = 0x2101,
 317        HCLGE_MAC_ETHERTYPE_IDX_RD      = 0x2105,
 318        HCLGE_NCSI_INT_EN               = 0x2401,
 319
 320        /* PHY command */
 321        HCLGE_OPC_PHY_LINK_KSETTING     = 0x7025,
 322        HCLGE_OPC_PHY_REG               = 0x7026,
 323};
 324
 325#define HCLGE_TQP_REG_OFFSET            0x80000
 326#define HCLGE_TQP_REG_SIZE              0x200
 327
 328#define HCLGE_TQP_MAX_SIZE_DEV_V2       1024
 329#define HCLGE_TQP_EXT_REG_OFFSET        0x100
 330
 331#define HCLGE_RCB_INIT_QUERY_TIMEOUT    10
 332#define HCLGE_RCB_INIT_FLAG_EN_B        0
 333#define HCLGE_RCB_INIT_FLAG_FINI_B      8
 334struct hclge_config_rcb_init_cmd {
 335        __le16 rcb_init_flag;
 336        u8 rsv[22];
 337};
 338
 339struct hclge_tqp_map_cmd {
 340        __le16 tqp_id;  /* Absolute tqp id for in this pf */
 341        u8 tqp_vf;      /* VF id */
 342#define HCLGE_TQP_MAP_TYPE_PF           0
 343#define HCLGE_TQP_MAP_TYPE_VF           1
 344#define HCLGE_TQP_MAP_TYPE_B            0
 345#define HCLGE_TQP_MAP_EN_B              1
 346        u8 tqp_flag;    /* Indicate it's pf or vf tqp */
 347        __le16 tqp_vid; /* Virtual id in this pf/vf */
 348        u8 rsv[18];
 349};
 350
 351#define HCLGE_VECTOR_ELEMENTS_PER_CMD   10
 352
 353enum hclge_int_type {
 354        HCLGE_INT_TX,
 355        HCLGE_INT_RX,
 356        HCLGE_INT_EVENT,
 357};
 358
 359struct hclge_ctrl_vector_chain_cmd {
 360#define HCLGE_VECTOR_ID_L_S     0
 361#define HCLGE_VECTOR_ID_L_M     GENMASK(7, 0)
 362        u8 int_vector_id_l;
 363        u8 int_cause_num;
 364#define HCLGE_INT_TYPE_S        0
 365#define HCLGE_INT_TYPE_M        GENMASK(1, 0)
 366#define HCLGE_TQP_ID_S          2
 367#define HCLGE_TQP_ID_M          GENMASK(12, 2)
 368#define HCLGE_INT_GL_IDX_S      13
 369#define HCLGE_INT_GL_IDX_M      GENMASK(14, 13)
 370        __le16 tqp_type_and_id[HCLGE_VECTOR_ELEMENTS_PER_CMD];
 371        u8 vfid;
 372#define HCLGE_VECTOR_ID_H_S     8
 373#define HCLGE_VECTOR_ID_H_M     GENMASK(15, 8)
 374        u8 int_vector_id_h;
 375};
 376
 377#define HCLGE_MAX_TC_NUM                8
 378#define HCLGE_TC0_PRI_BUF_EN_B  15 /* Bit 15 indicate enable or not */
 379#define HCLGE_BUF_UNIT_S        7  /* Buf size is united by 128 bytes */
 380struct hclge_tx_buff_alloc_cmd {
 381        __le16 tx_pkt_buff[HCLGE_MAX_TC_NUM];
 382        u8 tx_buff_rsv[8];
 383};
 384
 385struct hclge_rx_priv_buff_cmd {
 386        __le16 buf_num[HCLGE_MAX_TC_NUM];
 387        __le16 shared_buf;
 388        u8 rsv[6];
 389};
 390
 391enum HCLGE_CAP_BITS {
 392        HCLGE_CAP_UDP_GSO_B,
 393        HCLGE_CAP_QB_B,
 394        HCLGE_CAP_FD_FORWARD_TC_B,
 395        HCLGE_CAP_PTP_B,
 396        HCLGE_CAP_INT_QL_B,
 397        HCLGE_CAP_HW_TX_CSUM_B,
 398        HCLGE_CAP_TX_PUSH_B,
 399        HCLGE_CAP_PHY_IMP_B,
 400        HCLGE_CAP_TQP_TXRX_INDEP_B,
 401        HCLGE_CAP_HW_PAD_B,
 402        HCLGE_CAP_STASH_B,
 403        HCLGE_CAP_UDP_TUNNEL_CSUM_B,
 404        HCLGE_CAP_RAS_IMP_B = 12,
 405        HCLGE_CAP_FEC_B = 13,
 406        HCLGE_CAP_PAUSE_B = 14,
 407        HCLGE_CAP_RXD_ADV_LAYOUT_B = 15,
 408        HCLGE_CAP_PORT_VLAN_BYPASS_B = 17,
 409};
 410
 411enum HCLGE_API_CAP_BITS {
 412        HCLGE_API_CAP_FLEX_RSS_TBL_B,
 413};
 414
 415#define HCLGE_QUERY_CAP_LENGTH          3
 416struct hclge_query_version_cmd {
 417        __le32 firmware;
 418        __le32 hardware;
 419        __le32 api_caps;
 420        __le32 caps[HCLGE_QUERY_CAP_LENGTH]; /* capabilities of device */
 421};
 422
 423#define HCLGE_RX_PRIV_EN_B      15
 424#define HCLGE_TC_NUM_ONE_DESC   4
 425struct hclge_priv_wl {
 426        __le16 high;
 427        __le16 low;
 428};
 429
 430struct hclge_rx_priv_wl_buf {
 431        struct hclge_priv_wl tc_wl[HCLGE_TC_NUM_ONE_DESC];
 432};
 433
 434struct hclge_rx_com_thrd {
 435        struct hclge_priv_wl com_thrd[HCLGE_TC_NUM_ONE_DESC];
 436};
 437
 438struct hclge_rx_com_wl {
 439        struct hclge_priv_wl com_wl;
 440};
 441
 442struct hclge_waterline {
 443        u32 low;
 444        u32 high;
 445};
 446
 447struct hclge_tc_thrd {
 448        u32 low;
 449        u32 high;
 450};
 451
 452struct hclge_priv_buf {
 453        struct hclge_waterline wl;      /* Waterline for low and high*/
 454        u32 buf_size;   /* TC private buffer size */
 455        u32 tx_buf_size;
 456        u32 enable;     /* Enable TC private buffer or not */
 457};
 458
 459struct hclge_shared_buf {
 460        struct hclge_waterline self;
 461        struct hclge_tc_thrd tc_thrd[HCLGE_MAX_TC_NUM];
 462        u32 buf_size;
 463};
 464
 465struct hclge_pkt_buf_alloc {
 466        struct hclge_priv_buf priv_buf[HCLGE_MAX_TC_NUM];
 467        struct hclge_shared_buf s_buf;
 468};
 469
 470#define HCLGE_RX_COM_WL_EN_B    15
 471struct hclge_rx_com_wl_buf_cmd {
 472        __le16 high_wl;
 473        __le16 low_wl;
 474        u8 rsv[20];
 475};
 476
 477#define HCLGE_RX_PKT_EN_B       15
 478struct hclge_rx_pkt_buf_cmd {
 479        __le16 high_pkt;
 480        __le16 low_pkt;
 481        u8 rsv[20];
 482};
 483
 484#define HCLGE_PF_STATE_DONE_B   0
 485#define HCLGE_PF_STATE_MAIN_B   1
 486#define HCLGE_PF_STATE_BOND_B   2
 487#define HCLGE_PF_STATE_MAC_N_B  6
 488#define HCLGE_PF_MAC_NUM_MASK   0x3
 489#define HCLGE_PF_STATE_MAIN     BIT(HCLGE_PF_STATE_MAIN_B)
 490#define HCLGE_PF_STATE_DONE     BIT(HCLGE_PF_STATE_DONE_B)
 491#define HCLGE_VF_RST_STATUS_CMD 4
 492
 493struct hclge_func_status_cmd {
 494        __le32  vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
 495        u8 pf_state;
 496        u8 mac_id;
 497        u8 rsv1;
 498        u8 pf_cnt_in_mac;
 499        u8 pf_num;
 500        u8 vf_num;
 501        u8 rsv[2];
 502};
 503
 504struct hclge_pf_res_cmd {
 505        __le16 tqp_num;
 506        __le16 buf_size;
 507        __le16 msixcap_localid_ba_nic;
 508        __le16 msixcap_localid_number_nic;
 509        __le16 pf_intr_vector_number_roce;
 510        __le16 pf_own_fun_number;
 511        __le16 tx_buf_size;
 512        __le16 dv_buf_size;
 513        __le16 ext_tqp_num;
 514        u8 rsv[6];
 515};
 516
 517#define HCLGE_CFG_OFFSET_S      0
 518#define HCLGE_CFG_OFFSET_M      GENMASK(19, 0)
 519#define HCLGE_CFG_RD_LEN_S      24
 520#define HCLGE_CFG_RD_LEN_M      GENMASK(27, 24)
 521#define HCLGE_CFG_RD_LEN_BYTES  16
 522#define HCLGE_CFG_RD_LEN_UNIT   4
 523
 524#define HCLGE_CFG_TC_NUM_S      8
 525#define HCLGE_CFG_TC_NUM_M      GENMASK(15, 8)
 526#define HCLGE_CFG_TQP_DESC_N_S  16
 527#define HCLGE_CFG_TQP_DESC_N_M  GENMASK(31, 16)
 528#define HCLGE_CFG_PHY_ADDR_S    0
 529#define HCLGE_CFG_PHY_ADDR_M    GENMASK(7, 0)
 530#define HCLGE_CFG_MEDIA_TP_S    8
 531#define HCLGE_CFG_MEDIA_TP_M    GENMASK(15, 8)
 532#define HCLGE_CFG_RX_BUF_LEN_S  16
 533#define HCLGE_CFG_RX_BUF_LEN_M  GENMASK(31, 16)
 534#define HCLGE_CFG_MAC_ADDR_H_S  0
 535#define HCLGE_CFG_MAC_ADDR_H_M  GENMASK(15, 0)
 536#define HCLGE_CFG_DEFAULT_SPEED_S       16
 537#define HCLGE_CFG_DEFAULT_SPEED_M       GENMASK(23, 16)
 538#define HCLGE_CFG_RSS_SIZE_S    24
 539#define HCLGE_CFG_RSS_SIZE_M    GENMASK(31, 24)
 540#define HCLGE_CFG_SPEED_ABILITY_S       0
 541#define HCLGE_CFG_SPEED_ABILITY_M       GENMASK(7, 0)
 542#define HCLGE_CFG_SPEED_ABILITY_EXT_S   10
 543#define HCLGE_CFG_SPEED_ABILITY_EXT_M   GENMASK(15, 10)
 544#define HCLGE_CFG_VLAN_FLTR_CAP_S       8
 545#define HCLGE_CFG_VLAN_FLTR_CAP_M       GENMASK(9, 8)
 546#define HCLGE_CFG_UMV_TBL_SPACE_S       16
 547#define HCLGE_CFG_UMV_TBL_SPACE_M       GENMASK(31, 16)
 548#define HCLGE_CFG_PF_RSS_SIZE_S         0
 549#define HCLGE_CFG_PF_RSS_SIZE_M         GENMASK(3, 0)
 550#define HCLGE_CFG_TX_SPARE_BUF_SIZE_S   4
 551#define HCLGE_CFG_TX_SPARE_BUF_SIZE_M   GENMASK(15, 4)
 552
 553#define HCLGE_CFG_CMD_CNT               4
 554
 555struct hclge_cfg_param_cmd {
 556        __le32 offset;
 557        __le32 rsv;
 558        __le32 param[HCLGE_CFG_CMD_CNT];
 559};
 560
 561#define HCLGE_MAC_MODE          0x0
 562#define HCLGE_DESC_NUM          0x40
 563
 564#define HCLGE_ALLOC_VALID_B     0
 565struct hclge_vf_num_cmd {
 566        u8 alloc_valid;
 567        u8 rsv[23];
 568};
 569
 570#define HCLGE_RSS_DEFAULT_OUTPORT_B     4
 571#define HCLGE_RSS_HASH_KEY_OFFSET_B     4
 572#define HCLGE_RSS_HASH_KEY_NUM          16
 573struct hclge_rss_config_cmd {
 574        u8 hash_config;
 575        u8 rsv[7];
 576        u8 hash_key[HCLGE_RSS_HASH_KEY_NUM];
 577};
 578
 579struct hclge_rss_input_tuple_cmd {
 580        u8 ipv4_tcp_en;
 581        u8 ipv4_udp_en;
 582        u8 ipv4_sctp_en;
 583        u8 ipv4_fragment_en;
 584        u8 ipv6_tcp_en;
 585        u8 ipv6_udp_en;
 586        u8 ipv6_sctp_en;
 587        u8 ipv6_fragment_en;
 588        u8 rsv[16];
 589};
 590
 591#define HCLGE_RSS_CFG_TBL_SIZE  16
 592#define HCLGE_RSS_CFG_TBL_SIZE_H        4
 593#define HCLGE_RSS_CFG_TBL_BW_H          2U
 594#define HCLGE_RSS_CFG_TBL_BW_L          8U
 595
 596struct hclge_rss_indirection_table_cmd {
 597        __le16 start_table_index;
 598        __le16 rss_set_bitmap;
 599        u8 rss_qid_h[HCLGE_RSS_CFG_TBL_SIZE_H];
 600        u8 rss_qid_l[HCLGE_RSS_CFG_TBL_SIZE];
 601};
 602
 603#define HCLGE_RSS_TC_OFFSET_S           0
 604#define HCLGE_RSS_TC_OFFSET_M           GENMASK(10, 0)
 605#define HCLGE_RSS_TC_SIZE_MSB_B         11
 606#define HCLGE_RSS_TC_SIZE_S             12
 607#define HCLGE_RSS_TC_SIZE_M             GENMASK(14, 12)
 608#define HCLGE_RSS_TC_SIZE_MSB_OFFSET    3
 609#define HCLGE_RSS_TC_VALID_B            15
 610struct hclge_rss_tc_mode_cmd {
 611        __le16 rss_tc_mode[HCLGE_MAX_TC_NUM];
 612        u8 rsv[8];
 613};
 614
 615#define HCLGE_LINK_STATUS_UP_B  0
 616#define HCLGE_LINK_STATUS_UP_M  BIT(HCLGE_LINK_STATUS_UP_B)
 617struct hclge_link_status_cmd {
 618        u8 status;
 619        u8 rsv[23];
 620};
 621
 622/* for DEVICE_VERSION_V1/2, reference to promisc cmd byte8 */
 623#define HCLGE_PROMISC_EN_UC     1
 624#define HCLGE_PROMISC_EN_MC     2
 625#define HCLGE_PROMISC_EN_BC     3
 626#define HCLGE_PROMISC_TX_EN     4
 627#define HCLGE_PROMISC_RX_EN     5
 628
 629/* for DEVICE_VERSION_V3, reference to promisc cmd byte10 */
 630#define HCLGE_PROMISC_UC_RX_EN  2
 631#define HCLGE_PROMISC_MC_RX_EN  3
 632#define HCLGE_PROMISC_BC_RX_EN  4
 633#define HCLGE_PROMISC_UC_TX_EN  5
 634#define HCLGE_PROMISC_MC_TX_EN  6
 635#define HCLGE_PROMISC_BC_TX_EN  7
 636
 637struct hclge_promisc_cfg_cmd {
 638        u8 promisc;
 639        u8 vf_id;
 640        u8 extend_promisc;
 641        u8 rsv0[21];
 642};
 643
 644enum hclge_promisc_type {
 645        HCLGE_UNICAST   = 1,
 646        HCLGE_MULTICAST = 2,
 647        HCLGE_BROADCAST = 3,
 648};
 649
 650#define HCLGE_MAC_TX_EN_B       6
 651#define HCLGE_MAC_RX_EN_B       7
 652#define HCLGE_MAC_PAD_TX_B      11
 653#define HCLGE_MAC_PAD_RX_B      12
 654#define HCLGE_MAC_1588_TX_B     13
 655#define HCLGE_MAC_1588_RX_B     14
 656#define HCLGE_MAC_APP_LP_B      15
 657#define HCLGE_MAC_LINE_LP_B     16
 658#define HCLGE_MAC_FCS_TX_B      17
 659#define HCLGE_MAC_RX_OVERSIZE_TRUNCATE_B        18
 660#define HCLGE_MAC_RX_FCS_STRIP_B        19
 661#define HCLGE_MAC_RX_FCS_B      20
 662#define HCLGE_MAC_TX_UNDER_MIN_ERR_B            21
 663#define HCLGE_MAC_TX_OVERSIZE_TRUNCATE_B        22
 664
 665struct hclge_config_mac_mode_cmd {
 666        __le32 txrx_pad_fcs_loop_en;
 667        u8 rsv[20];
 668};
 669
 670struct hclge_pf_rst_sync_cmd {
 671#define HCLGE_PF_RST_ALL_VF_RDY_B       0
 672        u8 all_vf_ready;
 673        u8 rsv[23];
 674};
 675
 676#define HCLGE_CFG_SPEED_S               0
 677#define HCLGE_CFG_SPEED_M               GENMASK(5, 0)
 678
 679#define HCLGE_CFG_DUPLEX_B              7
 680#define HCLGE_CFG_DUPLEX_M              BIT(HCLGE_CFG_DUPLEX_B)
 681
 682struct hclge_config_mac_speed_dup_cmd {
 683        u8 speed_dup;
 684
 685#define HCLGE_CFG_MAC_SPEED_CHANGE_EN_B 0
 686        u8 mac_change_fec_en;
 687        u8 rsv[22];
 688};
 689
 690#define HCLGE_TQP_ENABLE_B              0
 691
 692#define HCLGE_MAC_CFG_AN_EN_B           0
 693#define HCLGE_MAC_CFG_AN_INT_EN_B       1
 694#define HCLGE_MAC_CFG_AN_INT_MSK_B      2
 695#define HCLGE_MAC_CFG_AN_INT_CLR_B      3
 696#define HCLGE_MAC_CFG_AN_RST_B          4
 697
 698#define HCLGE_MAC_CFG_AN_EN     BIT(HCLGE_MAC_CFG_AN_EN_B)
 699
 700struct hclge_config_auto_neg_cmd {
 701        __le32  cfg_an_cmd_flag;
 702        u8      rsv[20];
 703};
 704
 705struct hclge_sfp_info_cmd {
 706        __le32 speed;
 707        u8 query_type; /* 0: sfp speed, 1: active speed */
 708        u8 active_fec;
 709        u8 autoneg; /* autoneg state */
 710        u8 autoneg_ability; /* whether support autoneg */
 711        __le32 speed_ability; /* speed ability for current media */
 712        __le32 module_type;
 713        u8 rsv[8];
 714};
 715
 716#define HCLGE_MAC_CFG_FEC_AUTO_EN_B     0
 717#define HCLGE_MAC_CFG_FEC_MODE_S        1
 718#define HCLGE_MAC_CFG_FEC_MODE_M        GENMASK(3, 1)
 719#define HCLGE_MAC_CFG_FEC_SET_DEF_B     0
 720#define HCLGE_MAC_CFG_FEC_CLR_DEF_B     1
 721
 722#define HCLGE_MAC_FEC_OFF               0
 723#define HCLGE_MAC_FEC_BASER             1
 724#define HCLGE_MAC_FEC_RS                2
 725struct hclge_config_fec_cmd {
 726        u8 fec_mode;
 727        u8 default_config;
 728        u8 rsv[22];
 729};
 730
 731#define HCLGE_MAC_UPLINK_PORT           0x100
 732
 733struct hclge_config_max_frm_size_cmd {
 734        __le16  max_frm_size;
 735        u8      min_frm_size;
 736        u8      rsv[21];
 737};
 738
 739enum hclge_mac_vlan_tbl_opcode {
 740        HCLGE_MAC_VLAN_ADD,     /* Add new or modify mac_vlan */
 741        HCLGE_MAC_VLAN_UPDATE,  /* Modify other fields of this table */
 742        HCLGE_MAC_VLAN_REMOVE,  /* Remove a entry through mac_vlan key */
 743        HCLGE_MAC_VLAN_LKUP,    /* Lookup a entry through mac_vlan key */
 744};
 745
 746enum hclge_mac_vlan_add_resp_code {
 747        HCLGE_ADD_UC_OVERFLOW = 2,      /* ADD failed for UC overflow */
 748        HCLGE_ADD_MC_OVERFLOW,          /* ADD failed for MC overflow */
 749};
 750
 751#define HCLGE_MAC_VLAN_BIT0_EN_B        0
 752#define HCLGE_MAC_VLAN_BIT1_EN_B        1
 753#define HCLGE_MAC_EPORT_SW_EN_B         12
 754#define HCLGE_MAC_EPORT_TYPE_B          11
 755#define HCLGE_MAC_EPORT_VFID_S          3
 756#define HCLGE_MAC_EPORT_VFID_M          GENMASK(10, 3)
 757#define HCLGE_MAC_EPORT_PFID_S          0
 758#define HCLGE_MAC_EPORT_PFID_M          GENMASK(2, 0)
 759struct hclge_mac_vlan_tbl_entry_cmd {
 760        u8      flags;
 761        u8      resp_code;
 762        __le16  vlan_tag;
 763        __le32  mac_addr_hi32;
 764        __le16  mac_addr_lo16;
 765        __le16  rsv1;
 766        u8      entry_type;
 767        u8      mc_mac_en;
 768        __le16  egress_port;
 769        __le16  egress_queue;
 770        u8      rsv2[6];
 771};
 772
 773#define HCLGE_UMV_SPC_ALC_B     0
 774struct hclge_umv_spc_alc_cmd {
 775        u8 allocate;
 776        u8 rsv1[3];
 777        __le32 space_size;
 778        u8 rsv2[16];
 779};
 780
 781#define HCLGE_MAC_MGR_MASK_VLAN_B               BIT(0)
 782#define HCLGE_MAC_MGR_MASK_MAC_B                BIT(1)
 783#define HCLGE_MAC_MGR_MASK_ETHERTYPE_B          BIT(2)
 784
 785struct hclge_mac_mgr_tbl_entry_cmd {
 786        u8      flags;
 787        u8      resp_code;
 788        __le16  vlan_tag;
 789        u8      mac_addr[ETH_ALEN];
 790        __le16  rsv1;
 791        __le16  ethter_type;
 792        __le16  egress_port;
 793        __le16  egress_queue;
 794        u8      sw_port_id_aware;
 795        u8      rsv2;
 796        u8      i_port_bitmap;
 797        u8      i_port_direction;
 798        u8      rsv3[2];
 799};
 800
 801struct hclge_vlan_filter_ctrl_cmd {
 802        u8 vlan_type;
 803        u8 vlan_fe;
 804        u8 rsv1[2];
 805        u8 vf_id;
 806        u8 rsv2[19];
 807};
 808
 809#define HCLGE_VLAN_ID_OFFSET_STEP       160
 810#define HCLGE_VLAN_BYTE_SIZE            8
 811#define HCLGE_VLAN_OFFSET_BITMAP \
 812        (HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
 813
 814struct hclge_vlan_filter_pf_cfg_cmd {
 815        u8 vlan_offset;
 816        u8 vlan_cfg;
 817        u8 rsv[2];
 818        u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
 819};
 820
 821#define HCLGE_MAX_VF_BYTES  16
 822
 823struct hclge_vlan_filter_vf_cfg_cmd {
 824        __le16 vlan_id;
 825        u8  resp_code;
 826        u8  rsv;
 827        u8  vlan_cfg;
 828        u8  rsv1[3];
 829        u8  vf_bitmap[HCLGE_MAX_VF_BYTES];
 830};
 831
 832#define HCLGE_INGRESS_BYPASS_B          0
 833struct hclge_port_vlan_filter_bypass_cmd {
 834        u8 bypass_state;
 835        u8 rsv1[3];
 836        u8 vf_id;
 837        u8 rsv2[19];
 838};
 839
 840#define HCLGE_SWITCH_ANTI_SPOOF_B       0U
 841#define HCLGE_SWITCH_ALW_LPBK_B         1U
 842#define HCLGE_SWITCH_ALW_LCL_LPBK_B     2U
 843#define HCLGE_SWITCH_ALW_DST_OVRD_B     3U
 844#define HCLGE_SWITCH_NO_MASK            0x0
 845#define HCLGE_SWITCH_ANTI_SPOOF_MASK    0xFE
 846#define HCLGE_SWITCH_ALW_LPBK_MASK      0xFD
 847#define HCLGE_SWITCH_ALW_LCL_LPBK_MASK  0xFB
 848#define HCLGE_SWITCH_LW_DST_OVRD_MASK   0xF7
 849
 850struct hclge_mac_vlan_switch_cmd {
 851        u8 roce_sel;
 852        u8 rsv1[3];
 853        __le32 func_id;
 854        u8 switch_param;
 855        u8 rsv2[3];
 856        u8 param_mask;
 857        u8 rsv3[11];
 858};
 859
 860enum hclge_mac_vlan_cfg_sel {
 861        HCLGE_MAC_VLAN_NIC_SEL = 0,
 862        HCLGE_MAC_VLAN_ROCE_SEL,
 863};
 864
 865#define HCLGE_ACCEPT_TAG1_B             0
 866#define HCLGE_ACCEPT_UNTAG1_B           1
 867#define HCLGE_PORT_INS_TAG1_EN_B        2
 868#define HCLGE_PORT_INS_TAG2_EN_B        3
 869#define HCLGE_CFG_NIC_ROCE_SEL_B        4
 870#define HCLGE_ACCEPT_TAG2_B             5
 871#define HCLGE_ACCEPT_UNTAG2_B           6
 872#define HCLGE_TAG_SHIFT_MODE_EN_B       7
 873#define HCLGE_VF_NUM_PER_BYTE           8
 874
 875struct hclge_vport_vtag_tx_cfg_cmd {
 876        u8 vport_vlan_cfg;
 877        u8 vf_offset;
 878        u8 rsv1[2];
 879        __le16 def_vlan_tag1;
 880        __le16 def_vlan_tag2;
 881        u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 882        u8 rsv2[8];
 883};
 884
 885#define HCLGE_REM_TAG1_EN_B             0
 886#define HCLGE_REM_TAG2_EN_B             1
 887#define HCLGE_SHOW_TAG1_EN_B            2
 888#define HCLGE_SHOW_TAG2_EN_B            3
 889#define HCLGE_DISCARD_TAG1_EN_B         5
 890#define HCLGE_DISCARD_TAG2_EN_B         6
 891struct hclge_vport_vtag_rx_cfg_cmd {
 892        u8 vport_vlan_cfg;
 893        u8 vf_offset;
 894        u8 rsv1[6];
 895        u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
 896        u8 rsv2[8];
 897};
 898
 899struct hclge_tx_vlan_type_cfg_cmd {
 900        __le16 ot_vlan_type;
 901        __le16 in_vlan_type;
 902        u8 rsv[20];
 903};
 904
 905struct hclge_rx_vlan_type_cfg_cmd {
 906        __le16 ot_fst_vlan_type;
 907        __le16 ot_sec_vlan_type;
 908        __le16 in_fst_vlan_type;
 909        __le16 in_sec_vlan_type;
 910        u8 rsv[16];
 911};
 912
 913struct hclge_cfg_com_tqp_queue_cmd {
 914        __le16 tqp_id;
 915        __le16 stream_id;
 916        u8 enable;
 917        u8 rsv[19];
 918};
 919
 920struct hclge_cfg_tx_queue_pointer_cmd {
 921        __le16 tqp_id;
 922        __le16 tx_tail;
 923        __le16 tx_head;
 924        __le16 fbd_num;
 925        __le16 ring_offset;
 926        u8 rsv[14];
 927};
 928
 929#pragma pack(1)
 930struct hclge_mac_ethertype_idx_rd_cmd {
 931        u8      flags;
 932        u8      resp_code;
 933        __le16  vlan_tag;
 934        u8      mac_addr[ETH_ALEN];
 935        __le16  index;
 936        __le16  ethter_type;
 937        __le16  egress_port;
 938        __le16  egress_queue;
 939        __le16  rev0;
 940        u8      i_port_bitmap;
 941        u8      i_port_direction;
 942        u8      rev1[2];
 943};
 944
 945#pragma pack()
 946
 947#define HCLGE_TSO_MSS_MIN_S     0
 948#define HCLGE_TSO_MSS_MIN_M     GENMASK(13, 0)
 949
 950#define HCLGE_TSO_MSS_MAX_S     16
 951#define HCLGE_TSO_MSS_MAX_M     GENMASK(29, 16)
 952
 953struct hclge_cfg_tso_status_cmd {
 954        __le16 tso_mss_min;
 955        __le16 tso_mss_max;
 956        u8 rsv[20];
 957};
 958
 959#define HCLGE_GRO_EN_B          0
 960struct hclge_cfg_gro_status_cmd {
 961        u8 gro_en;
 962        u8 rsv[23];
 963};
 964
 965#define HCLGE_TSO_MSS_MIN       256
 966#define HCLGE_TSO_MSS_MAX       9668
 967
 968#define HCLGE_TQP_RESET_B       0
 969struct hclge_reset_tqp_queue_cmd {
 970        __le16 tqp_id;
 971        u8 reset_req;
 972        u8 ready_to_reset;
 973        u8 rsv[20];
 974};
 975
 976#define HCLGE_CFG_RESET_MAC_B           3
 977#define HCLGE_CFG_RESET_FUNC_B          7
 978#define HCLGE_CFG_RESET_RCB_B           1
 979struct hclge_reset_cmd {
 980        u8 mac_func_reset;
 981        u8 fun_reset_vfid;
 982        u8 fun_reset_rcb;
 983        u8 rsv;
 984        __le16 fun_reset_rcb_vqid_start;
 985        __le16 fun_reset_rcb_vqid_num;
 986        u8 fun_reset_rcb_return_status;
 987        u8 rsv1[15];
 988};
 989
 990#define HCLGE_PF_RESET_DONE_BIT         BIT(0)
 991
 992struct hclge_pf_rst_done_cmd {
 993        u8 pf_rst_done;
 994        u8 rsv[23];
 995};
 996
 997#define HCLGE_CMD_SERDES_SERIAL_INNER_LOOP_B    BIT(0)
 998#define HCLGE_CMD_SERDES_PARALLEL_INNER_LOOP_B  BIT(2)
 999#define HCLGE_CMD_GE_PHY_INNER_LOOP_B           BIT(3)
1000#define HCLGE_CMD_COMMON_LB_DONE_B              BIT(0)
1001#define HCLGE_CMD_COMMON_LB_SUCCESS_B           BIT(1)
1002struct hclge_common_lb_cmd {
1003        u8 mask;
1004        u8 enable;
1005        u8 result;
1006        u8 rsv[21];
1007};
1008
1009#define HCLGE_DEFAULT_TX_BUF            0x4000   /* 16k  bytes */
1010#define HCLGE_TOTAL_PKT_BUF             0x108000 /* 1.03125M bytes */
1011#define HCLGE_DEFAULT_DV                0xA000   /* 40k byte */
1012#define HCLGE_DEFAULT_NON_DCB_DV        0x7800  /* 30K byte */
1013#define HCLGE_NON_DCB_ADDITIONAL_BUF    0x1400  /* 5120 byte */
1014
1015#define HCLGE_TYPE_CRQ                  0
1016#define HCLGE_TYPE_CSQ                  1
1017#define HCLGE_NIC_CSQ_BASEADDR_L_REG    0x27000
1018#define HCLGE_NIC_CSQ_BASEADDR_H_REG    0x27004
1019#define HCLGE_NIC_CSQ_DEPTH_REG         0x27008
1020#define HCLGE_NIC_CSQ_TAIL_REG          0x27010
1021#define HCLGE_NIC_CSQ_HEAD_REG          0x27014
1022#define HCLGE_NIC_CRQ_BASEADDR_L_REG    0x27018
1023#define HCLGE_NIC_CRQ_BASEADDR_H_REG    0x2701c
1024#define HCLGE_NIC_CRQ_DEPTH_REG         0x27020
1025#define HCLGE_NIC_CRQ_TAIL_REG          0x27024
1026#define HCLGE_NIC_CRQ_HEAD_REG          0x27028
1027
1028/* this bit indicates that the driver is ready for hardware reset */
1029#define HCLGE_NIC_SW_RST_RDY_B          16
1030#define HCLGE_NIC_SW_RST_RDY            BIT(HCLGE_NIC_SW_RST_RDY_B)
1031
1032#define HCLGE_NIC_CMQ_DESC_NUM          1024
1033#define HCLGE_NIC_CMQ_DESC_NUM_S        3
1034
1035#define HCLGE_LED_LOCATE_STATE_S        0
1036#define HCLGE_LED_LOCATE_STATE_M        GENMASK(1, 0)
1037
1038struct hclge_set_led_state_cmd {
1039        u8 rsv1[3];
1040        u8 locate_led_config;
1041        u8 rsv2[20];
1042};
1043
1044struct hclge_get_fd_mode_cmd {
1045        u8 mode;
1046        u8 enable;
1047        u8 rsv[22];
1048};
1049
1050struct hclge_get_fd_allocation_cmd {
1051        __le32 stage1_entry_num;
1052        __le32 stage2_entry_num;
1053        __le16 stage1_counter_num;
1054        __le16 stage2_counter_num;
1055        u8 rsv[12];
1056};
1057
1058struct hclge_set_fd_key_config_cmd {
1059        u8 stage;
1060        u8 key_select;
1061        u8 inner_sipv6_word_en;
1062        u8 inner_dipv6_word_en;
1063        u8 outer_sipv6_word_en;
1064        u8 outer_dipv6_word_en;
1065        u8 rsv1[2];
1066        __le32 tuple_mask;
1067        __le32 meta_data_mask;
1068        u8 rsv2[8];
1069};
1070
1071#define HCLGE_FD_EPORT_SW_EN_B          0
1072struct hclge_fd_tcam_config_1_cmd {
1073        u8 stage;
1074        u8 xy_sel;
1075        u8 port_info;
1076        u8 rsv1[1];
1077        __le32 index;
1078        u8 entry_vld;
1079        u8 rsv2[7];
1080        u8 tcam_data[8];
1081};
1082
1083struct hclge_fd_tcam_config_2_cmd {
1084        u8 tcam_data[24];
1085};
1086
1087struct hclge_fd_tcam_config_3_cmd {
1088        u8 tcam_data[20];
1089        u8 rsv[4];
1090};
1091
1092#define HCLGE_FD_AD_DROP_B              0
1093#define HCLGE_FD_AD_DIRECT_QID_B        1
1094#define HCLGE_FD_AD_QID_S               2
1095#define HCLGE_FD_AD_QID_M               GENMASK(11, 2)
1096#define HCLGE_FD_AD_USE_COUNTER_B       12
1097#define HCLGE_FD_AD_COUNTER_NUM_S       13
1098#define HCLGE_FD_AD_COUNTER_NUM_M       GENMASK(20, 13)
1099#define HCLGE_FD_AD_NXT_STEP_B          20
1100#define HCLGE_FD_AD_NXT_KEY_S           21
1101#define HCLGE_FD_AD_NXT_KEY_M           GENMASK(25, 21)
1102#define HCLGE_FD_AD_WR_RULE_ID_B        0
1103#define HCLGE_FD_AD_RULE_ID_S           1
1104#define HCLGE_FD_AD_RULE_ID_M           GENMASK(12, 1)
1105#define HCLGE_FD_AD_TC_OVRD_B           16
1106#define HCLGE_FD_AD_TC_SIZE_S           17
1107#define HCLGE_FD_AD_TC_SIZE_M           GENMASK(20, 17)
1108
1109struct hclge_fd_ad_config_cmd {
1110        u8 stage;
1111        u8 rsv1[3];
1112        __le32 index;
1113        __le64 ad_data;
1114        u8 rsv2[8];
1115};
1116
1117struct hclge_fd_ad_cnt_read_cmd {
1118        u8 rsv0[4];
1119        __le16 index;
1120        u8 rsv1[2];
1121        __le64 cnt;
1122        u8 rsv2[8];
1123};
1124
1125#define HCLGE_FD_USER_DEF_OFT_S         0
1126#define HCLGE_FD_USER_DEF_OFT_M         GENMASK(14, 0)
1127#define HCLGE_FD_USER_DEF_EN_B          15
1128struct hclge_fd_user_def_cfg_cmd {
1129        __le16 ol2_cfg;
1130        __le16 l2_cfg;
1131        __le16 ol3_cfg;
1132        __le16 l3_cfg;
1133        __le16 ol4_cfg;
1134        __le16 l4_cfg;
1135        u8 rsv[12];
1136};
1137
1138struct hclge_get_imp_bd_cmd {
1139        __le32 bd_num;
1140        u8 rsv[20];
1141};
1142
1143struct hclge_query_ppu_pf_other_int_dfx_cmd {
1144        __le16 over_8bd_no_fe_qid;
1145        __le16 over_8bd_no_fe_vf_id;
1146        __le16 tso_mss_cmp_min_err_qid;
1147        __le16 tso_mss_cmp_min_err_vf_id;
1148        __le16 tso_mss_cmp_max_err_qid;
1149        __le16 tso_mss_cmp_max_err_vf_id;
1150        __le16 tx_rd_fbd_poison_qid;
1151        __le16 tx_rd_fbd_poison_vf_id;
1152        __le16 rx_rd_fbd_poison_qid;
1153        __le16 rx_rd_fbd_poison_vf_id;
1154        u8 rsv[4];
1155};
1156
1157#define HCLGE_LINK_EVENT_REPORT_EN_B    0
1158#define HCLGE_NCSI_ERROR_REPORT_EN_B    1
1159#define HCLGE_PHY_IMP_EN_B              2
1160struct hclge_firmware_compat_cmd {
1161        __le32 compat;
1162        u8 rsv[20];
1163};
1164
1165#define HCLGE_SFP_INFO_CMD_NUM  6
1166#define HCLGE_SFP_INFO_BD0_LEN  20
1167#define HCLGE_SFP_INFO_BDX_LEN  24
1168#define HCLGE_SFP_INFO_MAX_LEN \
1169        (HCLGE_SFP_INFO_BD0_LEN + \
1170        (HCLGE_SFP_INFO_CMD_NUM - 1) * HCLGE_SFP_INFO_BDX_LEN)
1171
1172struct hclge_sfp_info_bd0_cmd {
1173        __le16 offset;
1174        __le16 read_len;
1175        u8 data[HCLGE_SFP_INFO_BD0_LEN];
1176};
1177
1178#define HCLGE_QUERY_DEV_SPECS_BD_NUM            4
1179
1180struct hclge_dev_specs_0_cmd {
1181        __le32 rsv0;
1182        __le32 mac_entry_num;
1183        __le32 mng_entry_num;
1184        __le16 rss_ind_tbl_size;
1185        __le16 rss_key_size;
1186        __le16 int_ql_max;
1187        u8 max_non_tso_bd_num;
1188        u8 rsv1;
1189        __le32 max_tm_rate;
1190};
1191
1192#define HCLGE_DEF_MAX_INT_GL            0x1FE0U
1193
1194struct hclge_dev_specs_1_cmd {
1195        __le16 max_frm_size;
1196        __le16 max_qset_num;
1197        __le16 max_int_gl;
1198        u8 rsv1[18];
1199};
1200
1201#define HCLGE_PHY_LINK_SETTING_BD_NUM           2
1202
1203struct hclge_phy_link_ksetting_0_cmd {
1204        __le32 speed;
1205        u8 duplex;
1206        u8 autoneg;
1207        u8 eth_tp_mdix;
1208        u8 eth_tp_mdix_ctrl;
1209        u8 port;
1210        u8 transceiver;
1211        u8 phy_address;
1212        u8 rsv;
1213        __le32 supported;
1214        __le32 advertising;
1215        __le32 lp_advertising;
1216};
1217
1218struct hclge_phy_link_ksetting_1_cmd {
1219        u8 master_slave_cfg;
1220        u8 master_slave_state;
1221        u8 rsv[22];
1222};
1223
1224struct hclge_phy_reg_cmd {
1225        __le16 reg_addr;
1226        u8 rsv0[2];
1227        __le16 reg_val;
1228        u8 rsv1[18];
1229};
1230
1231int hclge_cmd_init(struct hclge_dev *hdev);
1232static inline void hclge_write_reg(void __iomem *base, u32 reg, u32 value)
1233{
1234        writel(value, base + reg);
1235}
1236
1237#define hclge_write_dev(a, reg, value) \
1238        hclge_write_reg((a)->io_base, reg, value)
1239#define hclge_read_dev(a, reg) \
1240        hclge_read_reg((a)->io_base, reg)
1241
1242static inline u32 hclge_read_reg(u8 __iomem *base, u32 reg)
1243{
1244        u8 __iomem *reg_addr = READ_ONCE(base);
1245
1246        return readl(reg_addr + reg);
1247}
1248
1249#define HCLGE_SEND_SYNC(flag) \
1250        ((flag) & HCLGE_CMD_FLAG_NO_INTR)
1251
1252struct hclge_hw;
1253int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num);
1254void hclge_cmd_setup_basic_desc(struct hclge_desc *desc,
1255                                enum hclge_opcode_type opcode, bool is_read);
1256void hclge_cmd_reuse_desc(struct hclge_desc *desc, bool is_read);
1257
1258enum hclge_cmd_status hclge_cmd_mdio_write(struct hclge_hw *hw,
1259                                           struct hclge_desc *desc);
1260enum hclge_cmd_status hclge_cmd_mdio_read(struct hclge_hw *hw,
1261                                          struct hclge_desc *desc);
1262
1263void hclge_cmd_uninit(struct hclge_dev *hdev);
1264int hclge_cmd_queue_init(struct hclge_dev *hdev);
1265#endif
1266