1
2
3
4
5
6#ifndef __DPAA2_ETH_H
7#define __DPAA2_ETH_H
8
9#include <linux/dcbnl.h>
10#include <linux/netdevice.h>
11#include <linux/if_vlan.h>
12#include <linux/fsl/mc.h>
13#include <linux/net_tstamp.h>
14#include <net/devlink.h>
15
16#include <soc/fsl/dpaa2-io.h>
17#include <soc/fsl/dpaa2-fd.h>
18#include "dpni.h"
19#include "dpni-cmd.h"
20
21#include "dpaa2-eth-trace.h"
22#include "dpaa2-eth-debugfs.h"
23#include "dpaa2-mac.h"
24
25#define DPAA2_WRIOP_VERSION(x, y, z) ((x) << 10 | (y) << 5 | (z) << 0)
26
27#define DPAA2_ETH_STORE_SIZE 16
28
29
30
31
32#define DPAA2_ETH_MAX_SG_ENTRIES ((64 * 1024) / DPAA2_ETH_RX_BUF_SIZE)
33
34
35
36
37#define DPAA2_ETH_MFL (10 * 1024)
38#define DPAA2_ETH_MAX_MTU (DPAA2_ETH_MFL - VLAN_ETH_HLEN)
39
40#define DPAA2_ETH_L2_MAX_FRM(mtu) ((mtu) + VLAN_ETH_HLEN)
41
42
43
44
45
46#define DPAA2_ETH_FQ_TAILDROP_THRESH (1024 * 1024)
47
48
49#define DPAA2_ETH_MAX_BURST_SIZE 0xF7FF
50
51
52
53
54#define DPAA2_ETH_TXCONF_PER_NAPI 256
55
56
57
58
59
60
61
62#define DPAA2_ETH_NUM_BUFS 1280
63#define DPAA2_ETH_REFILL_THRESH \
64 (DPAA2_ETH_NUM_BUFS - DPAA2_ETH_BUFS_PER_CMD)
65
66
67
68
69
70
71#define DPAA2_ETH_CG_TAILDROP_THRESH(priv) \
72 (1024 * dpaa2_eth_queue_count(priv) / dpaa2_eth_tc_count(priv))
73
74
75
76
77
78
79
80#define DPAA2_ETH_CN_THRESH_ENTRY(priv) \
81 (DPAA2_ETH_CG_TAILDROP_THRESH(priv) / 2)
82#define DPAA2_ETH_CN_THRESH_EXIT(priv) \
83 (DPAA2_ETH_CN_THRESH_ENTRY(priv) * 3 / 4)
84
85
86
87
88#define DPAA2_ETH_BUFS_PER_CMD 7
89
90
91#define DPAA2_ETH_TX_BUF_ALIGN 64
92
93#define DPAA2_ETH_RX_BUF_RAW_SIZE PAGE_SIZE
94#define DPAA2_ETH_RX_BUF_TAILROOM \
95 SKB_DATA_ALIGN(sizeof(struct skb_shared_info))
96#define DPAA2_ETH_RX_BUF_SIZE \
97 (DPAA2_ETH_RX_BUF_RAW_SIZE - DPAA2_ETH_RX_BUF_TAILROOM)
98
99
100#define DPAA2_ETH_RX_HWA_SIZE 64
101#define DPAA2_ETH_TX_HWA_SIZE 128
102
103
104#define DPAA2_PTP_CLK_PERIOD_NS 1
105
106
107
108
109#define DPAA2_ETH_RX_BUF_ALIGN_REV1 256
110#define DPAA2_ETH_RX_BUF_ALIGN 64
111
112
113
114
115
116#define DPAA2_ETH_SWA_SIZE 64
117
118
119
120
121enum dpaa2_eth_swa_type {
122 DPAA2_ETH_SWA_SINGLE,
123 DPAA2_ETH_SWA_SG,
124 DPAA2_ETH_SWA_XDP,
125};
126
127
128struct dpaa2_eth_swa {
129 enum dpaa2_eth_swa_type type;
130 union {
131 struct {
132 struct sk_buff *skb;
133 int sgt_size;
134 } single;
135 struct {
136 struct sk_buff *skb;
137 struct scatterlist *scl;
138 int num_sg;
139 int sgt_size;
140 } sg;
141 struct {
142 int dma_size;
143 struct xdp_frame *xdpf;
144 } xdp;
145 };
146};
147
148
149#define DPAA2_FD_FRC_FASV 0x8000
150#define DPAA2_FD_FRC_FAEADV 0x4000
151#define DPAA2_FD_FRC_FAPRV 0x2000
152#define DPAA2_FD_FRC_FAIADV 0x1000
153#define DPAA2_FD_FRC_FASWOV 0x0800
154#define DPAA2_FD_FRC_FAICFDV 0x0400
155
156
157#define DPAA2_FD_RX_ERR_MASK (FD_CTRL_SBE | FD_CTRL_FAERR)
158#define DPAA2_FD_TX_ERR_MASK (FD_CTRL_UFD | \
159 FD_CTRL_SBE | \
160 FD_CTRL_FSE | \
161 FD_CTRL_FAERR)
162
163
164#define DPAA2_FD_CTRL_ASAL 0x00020000
165
166
167struct dpaa2_fas {
168 u8 reserved;
169 u8 ppid;
170 __le16 ifpid;
171 __le32 status;
172};
173
174
175
176
177#define DPAA2_FAS_OFFSET 0
178#define DPAA2_FAS_SIZE (sizeof(struct dpaa2_fas))
179
180
181
182
183#define DPAA2_TS_OFFSET 0x8
184
185
186struct dpaa2_fapr {
187
188 __le32 faf_lo;
189 __le16 faf_ext;
190 __le16 nxt_hdr;
191
192 __le64 faf_hi;
193
194 u8 last_ethertype_offset;
195 u8 vlan_tci_offset_n;
196 u8 vlan_tci_offset_1;
197 u8 llc_snap_offset;
198 u8 eth_offset;
199 u8 ip1_pid_offset;
200 u8 shim_offset_2;
201 u8 shim_offset_1;
202
203 u8 l5_offset;
204 u8 l4_offset;
205 u8 gre_offset;
206 u8 l3_offset_n;
207 u8 l3_offset_1;
208 u8 mpls_offset_n;
209 u8 mpls_offset_1;
210 u8 pppoe_offset;
211
212 __le16 running_sum;
213 __le16 gross_running_sum;
214 u8 ipv6_frag_offset;
215 u8 nxt_hdr_offset;
216 u8 routing_hdr_offset_2;
217 u8 routing_hdr_offset_1;
218
219 u8 reserved[5];
220 u8 ip_proto_offset_n;
221 u8 nxt_hdr_frag_offset;
222 u8 parse_error_code;
223};
224
225#define DPAA2_FAPR_OFFSET 0x10
226#define DPAA2_FAPR_SIZE sizeof((struct dpaa2_fapr))
227
228
229#define DPAA2_FAEAD_OFFSET 0x58
230
231struct dpaa2_faead {
232 __le32 conf_fqid;
233 __le32 ctrl;
234};
235
236#define DPAA2_FAEAD_A2V 0x20000000
237#define DPAA2_FAEAD_A4V 0x08000000
238#define DPAA2_FAEAD_UPDV 0x00001000
239#define DPAA2_FAEAD_EBDDV 0x00002000
240#define DPAA2_FAEAD_UPD 0x00000010
241
242struct ptp_tstamp {
243 u16 sec_msb;
244 u32 sec_lsb;
245 u32 nsec;
246};
247
248static inline void ns_to_ptp_tstamp(struct ptp_tstamp *tstamp, u64 ns)
249{
250 u64 sec, nsec;
251
252 sec = ns;
253 nsec = do_div(sec, 1000000000);
254
255 tstamp->sec_lsb = sec & 0xFFFFFFFF;
256 tstamp->sec_msb = (sec >> 32) & 0xFFFF;
257 tstamp->nsec = nsec;
258}
259
260
261static inline void *dpaa2_get_hwa(void *buf_addr, bool swa)
262{
263 return buf_addr + (swa ? DPAA2_ETH_SWA_SIZE : 0);
264}
265
266static inline struct dpaa2_fas *dpaa2_get_fas(void *buf_addr, bool swa)
267{
268 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAS_OFFSET;
269}
270
271static inline __le64 *dpaa2_get_ts(void *buf_addr, bool swa)
272{
273 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_TS_OFFSET;
274}
275
276static inline struct dpaa2_fapr *dpaa2_get_fapr(void *buf_addr, bool swa)
277{
278 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAPR_OFFSET;
279}
280
281static inline struct dpaa2_faead *dpaa2_get_faead(void *buf_addr, bool swa)
282{
283 return dpaa2_get_hwa(buf_addr, swa) + DPAA2_FAEAD_OFFSET;
284}
285
286
287
288#define DPAA2_FAS_DISC 0x80000000
289
290#define DPAA2_FAS_MS 0x40000000
291#define DPAA2_FAS_PTP 0x08000000
292
293#define DPAA2_FAS_MC 0x04000000
294
295#define DPAA2_FAS_BC 0x02000000
296#define DPAA2_FAS_KSE 0x00040000
297#define DPAA2_FAS_EOFHE 0x00020000
298#define DPAA2_FAS_MNLE 0x00010000
299#define DPAA2_FAS_TIDE 0x00008000
300#define DPAA2_FAS_PIEE 0x00004000
301
302#define DPAA2_FAS_FLE 0x00002000
303
304#define DPAA2_FAS_FPE 0x00001000
305#define DPAA2_FAS_PTE 0x00000080
306#define DPAA2_FAS_ISP 0x00000040
307#define DPAA2_FAS_PHE 0x00000020
308#define DPAA2_FAS_BLE 0x00000010
309
310#define DPAA2_FAS_L3CV 0x00000008
311
312#define DPAA2_FAS_L3CE 0x00000004
313
314#define DPAA2_FAS_L4CV 0x00000002
315
316#define DPAA2_FAS_L4CE 0x00000001
317
318#define DPAA2_FAS_RX_ERR_MASK (DPAA2_FAS_KSE | \
319 DPAA2_FAS_EOFHE | \
320 DPAA2_FAS_MNLE | \
321 DPAA2_FAS_TIDE | \
322 DPAA2_FAS_PIEE | \
323 DPAA2_FAS_FLE | \
324 DPAA2_FAS_FPE | \
325 DPAA2_FAS_PTE | \
326 DPAA2_FAS_ISP | \
327 DPAA2_FAS_PHE | \
328 DPAA2_FAS_BLE | \
329 DPAA2_FAS_L3CE | \
330 DPAA2_FAS_L4CE)
331
332
333#define DPAA2_ETH_LINK_STATE_REFRESH 1000
334
335
336
337
338
339#define DPAA2_ETH_ENQUEUE_RETRIES 10
340
341
342
343
344
345
346
347#define DPAA2_ETH_SWP_BUSY_RETRIES 1000
348
349
350
351
352struct dpaa2_eth_drv_stats {
353 __u64 tx_conf_frames;
354 __u64 tx_conf_bytes;
355 __u64 tx_sg_frames;
356 __u64 tx_sg_bytes;
357 __u64 rx_sg_frames;
358 __u64 rx_sg_bytes;
359
360 __u64 tx_converted_sg_frames;
361 __u64 tx_converted_sg_bytes;
362
363 __u64 tx_portal_busy;
364};
365
366
367struct dpaa2_eth_fq_stats {
368
369 __u64 frames;
370};
371
372
373struct dpaa2_eth_ch_stats {
374
375 __u64 dequeue_portal_busy;
376
377 __u64 pull_err;
378
379 __u64 cdan;
380
381 __u64 xdp_drop;
382 __u64 xdp_tx;
383 __u64 xdp_tx_err;
384 __u64 xdp_redirect;
385
386 __u64 frames;
387};
388
389
390#define DPAA2_ETH_MAX_TCS 8
391#define DPAA2_ETH_MAX_RX_QUEUES_PER_TC 16
392#define DPAA2_ETH_MAX_RX_QUEUES \
393 (DPAA2_ETH_MAX_RX_QUEUES_PER_TC * DPAA2_ETH_MAX_TCS)
394#define DPAA2_ETH_MAX_TX_QUEUES 16
395#define DPAA2_ETH_MAX_RX_ERR_QUEUES 1
396#define DPAA2_ETH_MAX_QUEUES (DPAA2_ETH_MAX_RX_QUEUES + \
397 DPAA2_ETH_MAX_TX_QUEUES + \
398 DPAA2_ETH_MAX_RX_ERR_QUEUES)
399#define DPAA2_ETH_MAX_NETDEV_QUEUES \
400 (DPAA2_ETH_MAX_TX_QUEUES * DPAA2_ETH_MAX_TCS)
401
402#define DPAA2_ETH_MAX_DPCONS 16
403
404enum dpaa2_eth_fq_type {
405 DPAA2_RX_FQ = 0,
406 DPAA2_TX_CONF_FQ,
407 DPAA2_RX_ERR_FQ
408};
409
410struct dpaa2_eth_priv;
411
412struct dpaa2_eth_xdp_fds {
413 struct dpaa2_fd fds[DEV_MAP_BULK_SIZE];
414 ssize_t num;
415};
416
417struct dpaa2_eth_fq {
418 u32 fqid;
419 u32 tx_qdbin;
420 u32 tx_fqid[DPAA2_ETH_MAX_TCS];
421 u16 flowid;
422 u8 tc;
423 int target_cpu;
424 u32 dq_frames;
425 u32 dq_bytes;
426 struct dpaa2_eth_channel *channel;
427 enum dpaa2_eth_fq_type type;
428
429 void (*consume)(struct dpaa2_eth_priv *priv,
430 struct dpaa2_eth_channel *ch,
431 const struct dpaa2_fd *fd,
432 struct dpaa2_eth_fq *fq);
433 struct dpaa2_eth_fq_stats stats;
434
435 struct dpaa2_eth_xdp_fds xdp_redirect_fds;
436 struct dpaa2_eth_xdp_fds xdp_tx_fds;
437};
438
439struct dpaa2_eth_ch_xdp {
440 struct bpf_prog *prog;
441 unsigned int res;
442};
443
444struct dpaa2_eth_channel {
445 struct dpaa2_io_notification_ctx nctx;
446 struct fsl_mc_device *dpcon;
447 int dpcon_id;
448 int ch_id;
449 struct napi_struct napi;
450 struct dpaa2_io *dpio;
451 struct dpaa2_io_store *store;
452 struct dpaa2_eth_priv *priv;
453 int buf_count;
454 struct dpaa2_eth_ch_stats stats;
455 struct dpaa2_eth_ch_xdp xdp;
456 struct xdp_rxq_info xdp_rxq;
457 struct list_head *rx_list;
458
459
460 u64 recycled_bufs[DPAA2_ETH_BUFS_PER_CMD];
461 int recycled_bufs_cnt;
462};
463
464struct dpaa2_eth_dist_fields {
465 u64 rxnfc_field;
466 enum net_prot cls_prot;
467 int cls_field;
468 int size;
469 u64 id;
470};
471
472struct dpaa2_eth_cls_rule {
473 struct ethtool_rx_flow_spec fs;
474 u8 in_use;
475};
476
477#define DPAA2_ETH_SGT_CACHE_SIZE 256
478struct dpaa2_eth_sgt_cache {
479 void *buf[DPAA2_ETH_SGT_CACHE_SIZE];
480 u16 count;
481};
482
483struct dpaa2_eth_trap_item {
484 void *trap_ctx;
485};
486
487struct dpaa2_eth_trap_data {
488 struct dpaa2_eth_trap_item *trap_items_arr;
489 struct dpaa2_eth_priv *priv;
490};
491
492#define DPAA2_ETH_DEFAULT_COPYBREAK 512
493
494
495struct dpaa2_eth_priv {
496 struct net_device *net_dev;
497
498 u8 num_fqs;
499 struct dpaa2_eth_fq fq[DPAA2_ETH_MAX_QUEUES];
500 int (*enqueue)(struct dpaa2_eth_priv *priv,
501 struct dpaa2_eth_fq *fq,
502 struct dpaa2_fd *fd, u8 prio,
503 u32 num_frames,
504 int *frames_enqueued);
505
506 u8 num_channels;
507 struct dpaa2_eth_channel *channel[DPAA2_ETH_MAX_DPCONS];
508 struct dpaa2_eth_sgt_cache __percpu *sgt_cache;
509
510 struct dpni_attr dpni_attrs;
511 u16 dpni_ver_major;
512 u16 dpni_ver_minor;
513 u16 tx_data_offset;
514
515 struct fsl_mc_device *dpbp_dev;
516 u16 rx_buf_size;
517 u16 bpid;
518 struct iommu_domain *iommu_domain;
519
520 enum hwtstamp_tx_types tx_tstamp_type;
521 bool rx_tstamp;
522
523 u16 tx_qdid;
524 struct fsl_mc_io *mc_io;
525
526
527
528 struct cpumask dpio_cpumask;
529
530
531 struct rtnl_link_stats64 __percpu *percpu_stats;
532
533 struct dpaa2_eth_drv_stats __percpu *percpu_extras;
534
535 u16 mc_token;
536 u8 rx_fqtd_enabled;
537 u8 rx_cgtd_enabled;
538
539 struct dpni_link_state link_state;
540 bool do_link_poll;
541 struct task_struct *poll_thread;
542
543
544 u64 rx_hash_fields;
545 u64 rx_cls_fields;
546 struct dpaa2_eth_cls_rule *cls_rules;
547 u8 rx_cls_enabled;
548 u8 vlan_cls_enabled;
549 u8 pfc_enabled;
550#ifdef CONFIG_FSL_DPAA2_ETH_DCB
551 u8 dcbx_mode;
552 struct ieee_pfc pfc;
553#endif
554 struct bpf_prog *xdp_prog;
555#ifdef CONFIG_DEBUG_FS
556 struct dpaa2_debugfs dbg;
557#endif
558
559 struct dpaa2_mac *mac;
560 struct workqueue_struct *dpaa2_ptp_wq;
561 struct work_struct tx_onestep_tstamp;
562 struct sk_buff_head tx_skbs;
563
564
565
566
567
568
569
570 struct mutex onestep_tstamp_lock;
571 struct devlink *devlink;
572 struct dpaa2_eth_trap_data *trap_data;
573 struct devlink_port devlink_port;
574
575 u32 rx_copybreak;
576};
577
578struct dpaa2_eth_devlink_priv {
579 struct dpaa2_eth_priv *dpaa2_priv;
580};
581
582#define TX_TSTAMP 0x1
583#define TX_TSTAMP_ONESTEP_SYNC 0x2
584
585#define DPAA2_RXH_SUPPORTED (RXH_L2DA | RXH_VLAN | RXH_L3_PROTO \
586 | RXH_IP_SRC | RXH_IP_DST | RXH_L4_B_0_1 \
587 | RXH_L4_B_2_3)
588
589
590#define DPAA2_RXH_DEFAULT (RXH_L3_PROTO | RXH_IP_SRC | RXH_IP_DST | \
591 RXH_L4_B_0_1 | RXH_L4_B_2_3)
592
593#define dpaa2_eth_hash_enabled(priv) \
594 ((priv)->dpni_attrs.num_queues > 1)
595
596
597#define DPAA2_CLASSIFIER_DMA_SIZE 256
598
599extern const struct ethtool_ops dpaa2_ethtool_ops;
600extern int dpaa2_phc_index;
601extern struct ptp_qoriq *dpaa2_ptp;
602
603static inline int dpaa2_eth_cmp_dpni_ver(struct dpaa2_eth_priv *priv,
604 u16 ver_major, u16 ver_minor)
605{
606 if (priv->dpni_ver_major == ver_major)
607 return priv->dpni_ver_minor - ver_minor;
608 return priv->dpni_ver_major - ver_major;
609}
610
611
612
613
614#define DPNI_RX_DIST_KEY_VER_MAJOR 7
615#define DPNI_RX_DIST_KEY_VER_MINOR 5
616
617#define dpaa2_eth_has_legacy_dist(priv) \
618 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_RX_DIST_KEY_VER_MAJOR, \
619 DPNI_RX_DIST_KEY_VER_MINOR) < 0)
620
621#define dpaa2_eth_fs_enabled(priv) \
622 (!((priv)->dpni_attrs.options & DPNI_OPT_NO_FS))
623
624#define dpaa2_eth_fs_mask_enabled(priv) \
625 ((priv)->dpni_attrs.options & DPNI_OPT_HAS_KEY_MASKING)
626
627#define dpaa2_eth_fs_count(priv) \
628 ((priv)->dpni_attrs.fs_entries)
629
630#define dpaa2_eth_tc_count(priv) \
631 ((priv)->dpni_attrs.num_tcs)
632
633
634#define dpaa2_eth_queue_count(priv) \
635 ((priv)->num_channels)
636
637enum dpaa2_eth_rx_dist {
638 DPAA2_ETH_RX_DIST_HASH,
639 DPAA2_ETH_RX_DIST_CLS
640};
641
642
643#define DPAA2_ETH_DIST_ETHDST BIT(0)
644#define DPAA2_ETH_DIST_ETHSRC BIT(1)
645#define DPAA2_ETH_DIST_ETHTYPE BIT(2)
646#define DPAA2_ETH_DIST_VLAN BIT(3)
647#define DPAA2_ETH_DIST_IPSRC BIT(4)
648#define DPAA2_ETH_DIST_IPDST BIT(5)
649#define DPAA2_ETH_DIST_IPPROTO BIT(6)
650#define DPAA2_ETH_DIST_L4SRC BIT(7)
651#define DPAA2_ETH_DIST_L4DST BIT(8)
652#define DPAA2_ETH_DIST_ALL (~0ULL)
653
654#define DPNI_PAUSE_VER_MAJOR 7
655#define DPNI_PAUSE_VER_MINOR 13
656#define dpaa2_eth_has_pause_support(priv) \
657 (dpaa2_eth_cmp_dpni_ver((priv), DPNI_PAUSE_VER_MAJOR, \
658 DPNI_PAUSE_VER_MINOR) >= 0)
659
660static inline bool dpaa2_eth_tx_pause_enabled(u64 link_options)
661{
662 return !!(link_options & DPNI_LINK_OPT_PAUSE) ^
663 !!(link_options & DPNI_LINK_OPT_ASYM_PAUSE);
664}
665
666static inline bool dpaa2_eth_rx_pause_enabled(u64 link_options)
667{
668 return !!(link_options & DPNI_LINK_OPT_PAUSE);
669}
670
671static inline unsigned int dpaa2_eth_needed_headroom(struct sk_buff *skb)
672{
673 unsigned int headroom = DPAA2_ETH_SWA_SIZE;
674
675
676
677
678 if (!skb)
679 return headroom;
680
681
682
683
684 if (skb_is_nonlinear(skb))
685 return 0;
686
687
688 if (skb->cb[0])
689 headroom += DPAA2_ETH_TX_HWA_SIZE;
690
691 return headroom;
692}
693
694
695
696
697static inline unsigned int dpaa2_eth_rx_head_room(struct dpaa2_eth_priv *priv)
698{
699 return priv->tx_data_offset - DPAA2_ETH_RX_HWA_SIZE;
700}
701
702static inline bool dpaa2_eth_is_type_phy(struct dpaa2_eth_priv *priv)
703{
704 if (priv->mac &&
705 (priv->mac->attr.link_type == DPMAC_LINK_TYPE_PHY ||
706 priv->mac->attr.link_type == DPMAC_LINK_TYPE_BACKPLANE))
707 return true;
708
709 return false;
710}
711
712static inline bool dpaa2_eth_has_mac(struct dpaa2_eth_priv *priv)
713{
714 return priv->mac ? true : false;
715}
716
717int dpaa2_eth_set_hash(struct net_device *net_dev, u64 flags);
718int dpaa2_eth_set_cls(struct net_device *net_dev, u64 key);
719int dpaa2_eth_cls_key_size(u64 key);
720int dpaa2_eth_cls_fld_off(int prot, int field);
721void dpaa2_eth_cls_trim_rule(void *key_mem, u64 fields);
722
723void dpaa2_eth_set_rx_taildrop(struct dpaa2_eth_priv *priv,
724 bool tx_pause, bool pfc);
725
726extern const struct dcbnl_rtnl_ops dpaa2_eth_dcbnl_ops;
727
728int dpaa2_eth_dl_register(struct dpaa2_eth_priv *priv);
729void dpaa2_eth_dl_unregister(struct dpaa2_eth_priv *priv);
730
731int dpaa2_eth_dl_port_add(struct dpaa2_eth_priv *priv);
732void dpaa2_eth_dl_port_del(struct dpaa2_eth_priv *priv);
733
734int dpaa2_eth_dl_traps_register(struct dpaa2_eth_priv *priv);
735void dpaa2_eth_dl_traps_unregister(struct dpaa2_eth_priv *priv);
736
737struct dpaa2_eth_trap_item *dpaa2_eth_dl_get_trap(struct dpaa2_eth_priv *priv,
738 struct dpaa2_fapr *fapr);
739#endif
740