linux/drivers/net/ethernet/chelsio/cxgb4/t4_hw.c
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   1/*
   2 * This file is part of the Chelsio T4 Ethernet driver for Linux.
   3 *
   4 * Copyright (c) 2003-2016 Chelsio Communications, Inc. All rights reserved.
   5 *
   6 * This software is available to you under a choice of one of two
   7 * licenses.  You may choose to be licensed under the terms of the GNU
   8 * General Public License (GPL) Version 2, available from the file
   9 * COPYING in the main directory of this source tree, or the
  10 * OpenIB.org BSD license below:
  11 *
  12 *     Redistribution and use in source and binary forms, with or
  13 *     without modification, are permitted provided that the following
  14 *     conditions are met:
  15 *
  16 *      - Redistributions of source code must retain the above
  17 *        copyright notice, this list of conditions and the following
  18 *        disclaimer.
  19 *
  20 *      - Redistributions in binary form must reproduce the above
  21 *        copyright notice, this list of conditions and the following
  22 *        disclaimer in the documentation and/or other materials
  23 *        provided with the distribution.
  24 *
  25 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  26 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  27 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  28 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  29 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  30 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  31 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  32 * SOFTWARE.
  33 */
  34
  35#include <linux/delay.h>
  36#include "cxgb4.h"
  37#include "t4_regs.h"
  38#include "t4_values.h"
  39#include "t4fw_api.h"
  40#include "t4fw_version.h"
  41
  42/**
  43 *      t4_wait_op_done_val - wait until an operation is completed
  44 *      @adapter: the adapter performing the operation
  45 *      @reg: the register to check for completion
  46 *      @mask: a single-bit field within @reg that indicates completion
  47 *      @polarity: the value of the field when the operation is completed
  48 *      @attempts: number of check iterations
  49 *      @delay: delay in usecs between iterations
  50 *      @valp: where to store the value of the register at completion time
  51 *
  52 *      Wait until an operation is completed by checking a bit in a register
  53 *      up to @attempts times.  If @valp is not NULL the value of the register
  54 *      at the time it indicated completion is stored there.  Returns 0 if the
  55 *      operation completes and -EAGAIN otherwise.
  56 */
  57static int t4_wait_op_done_val(struct adapter *adapter, int reg, u32 mask,
  58                               int polarity, int attempts, int delay, u32 *valp)
  59{
  60        while (1) {
  61                u32 val = t4_read_reg(adapter, reg);
  62
  63                if (!!(val & mask) == polarity) {
  64                        if (valp)
  65                                *valp = val;
  66                        return 0;
  67                }
  68                if (--attempts == 0)
  69                        return -EAGAIN;
  70                if (delay)
  71                        udelay(delay);
  72        }
  73}
  74
  75static inline int t4_wait_op_done(struct adapter *adapter, int reg, u32 mask,
  76                                  int polarity, int attempts, int delay)
  77{
  78        return t4_wait_op_done_val(adapter, reg, mask, polarity, attempts,
  79                                   delay, NULL);
  80}
  81
  82/**
  83 *      t4_set_reg_field - set a register field to a value
  84 *      @adapter: the adapter to program
  85 *      @addr: the register address
  86 *      @mask: specifies the portion of the register to modify
  87 *      @val: the new value for the register field
  88 *
  89 *      Sets a register field specified by the supplied mask to the
  90 *      given value.
  91 */
  92void t4_set_reg_field(struct adapter *adapter, unsigned int addr, u32 mask,
  93                      u32 val)
  94{
  95        u32 v = t4_read_reg(adapter, addr) & ~mask;
  96
  97        t4_write_reg(adapter, addr, v | val);
  98        (void) t4_read_reg(adapter, addr);      /* flush */
  99}
 100
 101/**
 102 *      t4_read_indirect - read indirectly addressed registers
 103 *      @adap: the adapter
 104 *      @addr_reg: register holding the indirect address
 105 *      @data_reg: register holding the value of the indirect register
 106 *      @vals: where the read register values are stored
 107 *      @nregs: how many indirect registers to read
 108 *      @start_idx: index of first indirect register to read
 109 *
 110 *      Reads registers that are accessed indirectly through an address/data
 111 *      register pair.
 112 */
 113void t4_read_indirect(struct adapter *adap, unsigned int addr_reg,
 114                             unsigned int data_reg, u32 *vals,
 115                             unsigned int nregs, unsigned int start_idx)
 116{
 117        while (nregs--) {
 118                t4_write_reg(adap, addr_reg, start_idx);
 119                *vals++ = t4_read_reg(adap, data_reg);
 120                start_idx++;
 121        }
 122}
 123
 124/**
 125 *      t4_write_indirect - write indirectly addressed registers
 126 *      @adap: the adapter
 127 *      @addr_reg: register holding the indirect addresses
 128 *      @data_reg: register holding the value for the indirect registers
 129 *      @vals: values to write
 130 *      @nregs: how many indirect registers to write
 131 *      @start_idx: address of first indirect register to write
 132 *
 133 *      Writes a sequential block of registers that are accessed indirectly
 134 *      through an address/data register pair.
 135 */
 136void t4_write_indirect(struct adapter *adap, unsigned int addr_reg,
 137                       unsigned int data_reg, const u32 *vals,
 138                       unsigned int nregs, unsigned int start_idx)
 139{
 140        while (nregs--) {
 141                t4_write_reg(adap, addr_reg, start_idx++);
 142                t4_write_reg(adap, data_reg, *vals++);
 143        }
 144}
 145
 146/*
 147 * Read a 32-bit PCI Configuration Space register via the PCI-E backdoor
 148 * mechanism.  This guarantees that we get the real value even if we're
 149 * operating within a Virtual Machine and the Hypervisor is trapping our
 150 * Configuration Space accesses.
 151 */
 152void t4_hw_pci_read_cfg4(struct adapter *adap, int reg, u32 *val)
 153{
 154        u32 req = FUNCTION_V(adap->pf) | REGISTER_V(reg);
 155
 156        if (CHELSIO_CHIP_VERSION(adap->params.chip) <= CHELSIO_T5)
 157                req |= ENABLE_F;
 158        else
 159                req |= T6_ENABLE_F;
 160
 161        if (is_t4(adap->params.chip))
 162                req |= LOCALCFG_F;
 163
 164        t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, req);
 165        *val = t4_read_reg(adap, PCIE_CFG_SPACE_DATA_A);
 166
 167        /* Reset ENABLE to 0 so reads of PCIE_CFG_SPACE_DATA won't cause a
 168         * Configuration Space read.  (None of the other fields matter when
 169         * ENABLE is 0 so a simple register write is easier than a
 170         * read-modify-write via t4_set_reg_field().)
 171         */
 172        t4_write_reg(adap, PCIE_CFG_SPACE_REQ_A, 0);
 173}
 174
 175/*
 176 * t4_report_fw_error - report firmware error
 177 * @adap: the adapter
 178 *
 179 * The adapter firmware can indicate error conditions to the host.
 180 * If the firmware has indicated an error, print out the reason for
 181 * the firmware error.
 182 */
 183static void t4_report_fw_error(struct adapter *adap)
 184{
 185        static const char *const reason[] = {
 186                "Crash",                        /* PCIE_FW_EVAL_CRASH */
 187                "During Device Preparation",    /* PCIE_FW_EVAL_PREP */
 188                "During Device Configuration",  /* PCIE_FW_EVAL_CONF */
 189                "During Device Initialization", /* PCIE_FW_EVAL_INIT */
 190                "Unexpected Event",             /* PCIE_FW_EVAL_UNEXPECTEDEVENT */
 191                "Insufficient Airflow",         /* PCIE_FW_EVAL_OVERHEAT */
 192                "Device Shutdown",              /* PCIE_FW_EVAL_DEVICESHUTDOWN */
 193                "Reserved",                     /* reserved */
 194        };
 195        u32 pcie_fw;
 196
 197        pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 198        if (pcie_fw & PCIE_FW_ERR_F) {
 199                dev_err(adap->pdev_dev, "Firmware reports adapter error: %s\n",
 200                        reason[PCIE_FW_EVAL_G(pcie_fw)]);
 201                adap->flags &= ~CXGB4_FW_OK;
 202        }
 203}
 204
 205/*
 206 * Get the reply to a mailbox command and store it in @rpl in big-endian order.
 207 */
 208static void get_mbox_rpl(struct adapter *adap, __be64 *rpl, int nflit,
 209                         u32 mbox_addr)
 210{
 211        for ( ; nflit; nflit--, mbox_addr += 8)
 212                *rpl++ = cpu_to_be64(t4_read_reg64(adap, mbox_addr));
 213}
 214
 215/*
 216 * Handle a FW assertion reported in a mailbox.
 217 */
 218static void fw_asrt(struct adapter *adap, u32 mbox_addr)
 219{
 220        struct fw_debug_cmd asrt;
 221
 222        get_mbox_rpl(adap, (__be64 *)&asrt, sizeof(asrt) / 8, mbox_addr);
 223        dev_alert(adap->pdev_dev,
 224                  "FW assertion at %.16s:%u, val0 %#x, val1 %#x\n",
 225                  asrt.u.assert.filename_0_7, be32_to_cpu(asrt.u.assert.line),
 226                  be32_to_cpu(asrt.u.assert.x), be32_to_cpu(asrt.u.assert.y));
 227}
 228
 229/**
 230 *      t4_record_mbox - record a Firmware Mailbox Command/Reply in the log
 231 *      @adapter: the adapter
 232 *      @cmd: the Firmware Mailbox Command or Reply
 233 *      @size: command length in bytes
 234 *      @access: the time (ms) needed to access the Firmware Mailbox
 235 *      @execute: the time (ms) the command spent being executed
 236 */
 237static void t4_record_mbox(struct adapter *adapter,
 238                           const __be64 *cmd, unsigned int size,
 239                           int access, int execute)
 240{
 241        struct mbox_cmd_log *log = adapter->mbox_log;
 242        struct mbox_cmd *entry;
 243        int i;
 244
 245        entry = mbox_cmd_log_entry(log, log->cursor++);
 246        if (log->cursor == log->size)
 247                log->cursor = 0;
 248
 249        for (i = 0; i < size / 8; i++)
 250                entry->cmd[i] = be64_to_cpu(cmd[i]);
 251        while (i < MBOX_LEN / 8)
 252                entry->cmd[i++] = 0;
 253        entry->timestamp = jiffies;
 254        entry->seqno = log->seqno++;
 255        entry->access = access;
 256        entry->execute = execute;
 257}
 258
 259/**
 260 *      t4_wr_mbox_meat_timeout - send a command to FW through the given mailbox
 261 *      @adap: the adapter
 262 *      @mbox: index of the mailbox to use
 263 *      @cmd: the command to write
 264 *      @size: command length in bytes
 265 *      @rpl: where to optionally store the reply
 266 *      @sleep_ok: if true we may sleep while awaiting command completion
 267 *      @timeout: time to wait for command to finish before timing out
 268 *
 269 *      Sends the given command to FW through the selected mailbox and waits
 270 *      for the FW to execute the command.  If @rpl is not %NULL it is used to
 271 *      store the FW's reply to the command.  The command and its optional
 272 *      reply are of the same length.  FW can take up to %FW_CMD_MAX_TIMEOUT ms
 273 *      to respond.  @sleep_ok determines whether we may sleep while awaiting
 274 *      the response.  If sleeping is allowed we use progressive backoff
 275 *      otherwise we spin.
 276 *
 277 *      The return value is 0 on success or a negative errno on failure.  A
 278 *      failure can happen either because we are not able to execute the
 279 *      command or FW executes it but signals an error.  In the latter case
 280 *      the return value is the error code indicated by FW (negated).
 281 */
 282int t4_wr_mbox_meat_timeout(struct adapter *adap, int mbox, const void *cmd,
 283                            int size, void *rpl, bool sleep_ok, int timeout)
 284{
 285        static const int delay[] = {
 286                1, 1, 3, 5, 10, 10, 20, 50, 100, 200
 287        };
 288
 289        struct mbox_list entry;
 290        u16 access = 0;
 291        u16 execute = 0;
 292        u32 v;
 293        u64 res;
 294        int i, ms, delay_idx, ret;
 295        const __be64 *p = cmd;
 296        u32 data_reg = PF_REG(mbox, CIM_PF_MAILBOX_DATA_A);
 297        u32 ctl_reg = PF_REG(mbox, CIM_PF_MAILBOX_CTRL_A);
 298        __be64 cmd_rpl[MBOX_LEN / 8];
 299        u32 pcie_fw;
 300
 301        if ((size & 15) || size > MBOX_LEN)
 302                return -EINVAL;
 303
 304        /*
 305         * If the device is off-line, as in EEH, commands will time out.
 306         * Fail them early so we don't waste time waiting.
 307         */
 308        if (adap->pdev->error_state != pci_channel_io_normal)
 309                return -EIO;
 310
 311        /* If we have a negative timeout, that implies that we can't sleep. */
 312        if (timeout < 0) {
 313                sleep_ok = false;
 314                timeout = -timeout;
 315        }
 316
 317        /* Queue ourselves onto the mailbox access list.  When our entry is at
 318         * the front of the list, we have rights to access the mailbox.  So we
 319         * wait [for a while] till we're at the front [or bail out with an
 320         * EBUSY] ...
 321         */
 322        spin_lock_bh(&adap->mbox_lock);
 323        list_add_tail(&entry.list, &adap->mlist.list);
 324        spin_unlock_bh(&adap->mbox_lock);
 325
 326        delay_idx = 0;
 327        ms = delay[0];
 328
 329        for (i = 0; ; i += ms) {
 330                /* If we've waited too long, return a busy indication.  This
 331                 * really ought to be based on our initial position in the
 332                 * mailbox access list but this is a start.  We very rarely
 333                 * contend on access to the mailbox ...
 334                 */
 335                pcie_fw = t4_read_reg(adap, PCIE_FW_A);
 336                if (i > FW_CMD_MAX_TIMEOUT || (pcie_fw & PCIE_FW_ERR_F)) {
 337                        spin_lock_bh(&adap->mbox_lock);
 338                        list_del(&entry.list);
 339                        spin_unlock_bh(&adap->mbox_lock);
 340                        ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -EBUSY;
 341                        t4_record_mbox(adap, cmd, size, access, ret);
 342                        return ret;
 343                }
 344
 345                /* If we're at the head, break out and start the mailbox
 346                 * protocol.
 347                 */
 348                if (list_first_entry(&adap->mlist.list, struct mbox_list,
 349                                     list) == &entry)
 350                        break;
 351
 352                /* Delay for a bit before checking again ... */
 353                if (sleep_ok) {
 354                        ms = delay[delay_idx];  /* last element may repeat */
 355                        if (delay_idx < ARRAY_SIZE(delay) - 1)
 356                                delay_idx++;
 357                        msleep(ms);
 358                } else {
 359                        mdelay(ms);
 360                }
 361        }
 362
 363        /* Loop trying to get ownership of the mailbox.  Return an error
 364         * if we can't gain ownership.
 365         */
 366        v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 367        for (i = 0; v == MBOX_OWNER_NONE && i < 3; i++)
 368                v = MBOWNER_G(t4_read_reg(adap, ctl_reg));
 369        if (v != MBOX_OWNER_DRV) {
 370                spin_lock_bh(&adap->mbox_lock);
 371                list_del(&entry.list);
 372                spin_unlock_bh(&adap->mbox_lock);
 373                ret = (v == MBOX_OWNER_FW) ? -EBUSY : -ETIMEDOUT;
 374                t4_record_mbox(adap, cmd, size, access, ret);
 375                return ret;
 376        }
 377
 378        /* Copy in the new mailbox command and send it on its way ... */
 379        t4_record_mbox(adap, cmd, size, access, 0);
 380        for (i = 0; i < size; i += 8)
 381                t4_write_reg64(adap, data_reg + i, be64_to_cpu(*p++));
 382
 383        t4_write_reg(adap, ctl_reg, MBMSGVALID_F | MBOWNER_V(MBOX_OWNER_FW));
 384        t4_read_reg(adap, ctl_reg);          /* flush write */
 385
 386        delay_idx = 0;
 387        ms = delay[0];
 388
 389        for (i = 0;
 390             !((pcie_fw = t4_read_reg(adap, PCIE_FW_A)) & PCIE_FW_ERR_F) &&
 391             i < timeout;
 392             i += ms) {
 393                if (sleep_ok) {
 394                        ms = delay[delay_idx];  /* last element may repeat */
 395                        if (delay_idx < ARRAY_SIZE(delay) - 1)
 396                                delay_idx++;
 397                        msleep(ms);
 398                } else
 399                        mdelay(ms);
 400
 401                v = t4_read_reg(adap, ctl_reg);
 402                if (MBOWNER_G(v) == MBOX_OWNER_DRV) {
 403                        if (!(v & MBMSGVALID_F)) {
 404                                t4_write_reg(adap, ctl_reg, 0);
 405                                continue;
 406                        }
 407
 408                        get_mbox_rpl(adap, cmd_rpl, MBOX_LEN / 8, data_reg);
 409                        res = be64_to_cpu(cmd_rpl[0]);
 410
 411                        if (FW_CMD_OP_G(res >> 32) == FW_DEBUG_CMD) {
 412                                fw_asrt(adap, data_reg);
 413                                res = FW_CMD_RETVAL_V(EIO);
 414                        } else if (rpl) {
 415                                memcpy(rpl, cmd_rpl, size);
 416                        }
 417
 418                        t4_write_reg(adap, ctl_reg, 0);
 419
 420                        execute = i + ms;
 421                        t4_record_mbox(adap, cmd_rpl,
 422                                       MBOX_LEN, access, execute);
 423                        spin_lock_bh(&adap->mbox_lock);
 424                        list_del(&entry.list);
 425                        spin_unlock_bh(&adap->mbox_lock);
 426                        return -FW_CMD_RETVAL_G((int)res);
 427                }
 428        }
 429
 430        ret = (pcie_fw & PCIE_FW_ERR_F) ? -ENXIO : -ETIMEDOUT;
 431        t4_record_mbox(adap, cmd, size, access, ret);
 432        dev_err(adap->pdev_dev, "command %#x in mailbox %d timed out\n",
 433                *(const u8 *)cmd, mbox);
 434        t4_report_fw_error(adap);
 435        spin_lock_bh(&adap->mbox_lock);
 436        list_del(&entry.list);
 437        spin_unlock_bh(&adap->mbox_lock);
 438        t4_fatal_err(adap);
 439        return ret;
 440}
 441
 442int t4_wr_mbox_meat(struct adapter *adap, int mbox, const void *cmd, int size,
 443                    void *rpl, bool sleep_ok)
 444{
 445        return t4_wr_mbox_meat_timeout(adap, mbox, cmd, size, rpl, sleep_ok,
 446                                       FW_CMD_MAX_TIMEOUT);
 447}
 448
 449static int t4_edc_err_read(struct adapter *adap, int idx)
 450{
 451        u32 edc_ecc_err_addr_reg;
 452        u32 rdata_reg;
 453
 454        if (is_t4(adap->params.chip)) {
 455                CH_WARN(adap, "%s: T4 NOT supported.\n", __func__);
 456                return 0;
 457        }
 458        if (idx != 0 && idx != 1) {
 459                CH_WARN(adap, "%s: idx %d NOT supported.\n", __func__, idx);
 460                return 0;
 461        }
 462
 463        edc_ecc_err_addr_reg = EDC_T5_REG(EDC_H_ECC_ERR_ADDR_A, idx);
 464        rdata_reg = EDC_T5_REG(EDC_H_BIST_STATUS_RDATA_A, idx);
 465
 466        CH_WARN(adap,
 467                "edc%d err addr 0x%x: 0x%x.\n",
 468                idx, edc_ecc_err_addr_reg,
 469                t4_read_reg(adap, edc_ecc_err_addr_reg));
 470        CH_WARN(adap,
 471                "bist: 0x%x, status %llx %llx %llx %llx %llx %llx %llx %llx %llx.\n",
 472                rdata_reg,
 473                (unsigned long long)t4_read_reg64(adap, rdata_reg),
 474                (unsigned long long)t4_read_reg64(adap, rdata_reg + 8),
 475                (unsigned long long)t4_read_reg64(adap, rdata_reg + 16),
 476                (unsigned long long)t4_read_reg64(adap, rdata_reg + 24),
 477                (unsigned long long)t4_read_reg64(adap, rdata_reg + 32),
 478                (unsigned long long)t4_read_reg64(adap, rdata_reg + 40),
 479                (unsigned long long)t4_read_reg64(adap, rdata_reg + 48),
 480                (unsigned long long)t4_read_reg64(adap, rdata_reg + 56),
 481                (unsigned long long)t4_read_reg64(adap, rdata_reg + 64));
 482
 483        return 0;
 484}
 485
 486/**
 487 * t4_memory_rw_init - Get memory window relative offset, base, and size.
 488 * @adap: the adapter
 489 * @win: PCI-E Memory Window to use
 490 * @mtype: memory type: MEM_EDC0, MEM_EDC1, MEM_HMA or MEM_MC
 491 * @mem_off: memory relative offset with respect to @mtype.
 492 * @mem_base: configured memory base address.
 493 * @mem_aperture: configured memory window aperture.
 494 *
 495 * Get the configured memory window's relative offset, base, and size.
 496 */
 497int t4_memory_rw_init(struct adapter *adap, int win, int mtype, u32 *mem_off,
 498                      u32 *mem_base, u32 *mem_aperture)
 499{
 500        u32 edc_size, mc_size, mem_reg;
 501
 502        /* Offset into the region of memory which is being accessed
 503         * MEM_EDC0 = 0
 504         * MEM_EDC1 = 1
 505         * MEM_MC   = 2 -- MEM_MC for chips with only 1 memory controller
 506         * MEM_MC1  = 3 -- for chips with 2 memory controllers (e.g. T5)
 507         * MEM_HMA  = 4
 508         */
 509        edc_size  = EDRAM0_SIZE_G(t4_read_reg(adap, MA_EDRAM0_BAR_A));
 510        if (mtype == MEM_HMA) {
 511                *mem_off = 2 * (edc_size * 1024 * 1024);
 512        } else if (mtype != MEM_MC1) {
 513                *mem_off = (mtype * (edc_size * 1024 * 1024));
 514        } else {
 515                mc_size = EXT_MEM0_SIZE_G(t4_read_reg(adap,
 516                                                      MA_EXT_MEMORY0_BAR_A));
 517                *mem_off = (MEM_MC0 * edc_size + mc_size) * 1024 * 1024;
 518        }
 519
 520        /* Each PCI-E Memory Window is programmed with a window size -- or
 521         * "aperture" -- which controls the granularity of its mapping onto
 522         * adapter memory.  We need to grab that aperture in order to know
 523         * how to use the specified window.  The window is also programmed
 524         * with the base address of the Memory Window in BAR0's address
 525         * space.  For T4 this is an absolute PCI-E Bus Address.  For T5
 526         * the address is relative to BAR0.
 527         */
 528        mem_reg = t4_read_reg(adap,
 529                              PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A,
 530                                                  win));
 531        /* a dead adapter will return 0xffffffff for PIO reads */
 532        if (mem_reg == 0xffffffff)
 533                return -ENXIO;
 534
 535        *mem_aperture = 1 << (WINDOW_G(mem_reg) + WINDOW_SHIFT_X);
 536        *mem_base = PCIEOFST_G(mem_reg) << PCIEOFST_SHIFT_X;
 537        if (is_t4(adap->params.chip))
 538                *mem_base -= adap->t4_bar0;
 539
 540        return 0;
 541}
 542
 543/**
 544 * t4_memory_update_win - Move memory window to specified address.
 545 * @adap: the adapter
 546 * @win: PCI-E Memory Window to use
 547 * @addr: location to move.
 548 *
 549 * Move memory window to specified address.
 550 */
 551void t4_memory_update_win(struct adapter *adap, int win, u32 addr)
 552{
 553        t4_write_reg(adap,
 554                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win),
 555                     addr);
 556        /* Read it back to ensure that changes propagate before we
 557         * attempt to use the new value.
 558         */
 559        t4_read_reg(adap,
 560                    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_OFFSET_A, win));
 561}
 562
 563/**
 564 * t4_memory_rw_residual - Read/Write residual data.
 565 * @adap: the adapter
 566 * @off: relative offset within residual to start read/write.
 567 * @addr: address within indicated memory type.
 568 * @buf: host memory buffer
 569 * @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 570 *
 571 * Read/Write residual data less than 32-bits.
 572 */
 573void t4_memory_rw_residual(struct adapter *adap, u32 off, u32 addr, u8 *buf,
 574                           int dir)
 575{
 576        union {
 577                u32 word;
 578                char byte[4];
 579        } last;
 580        unsigned char *bp;
 581        int i;
 582
 583        if (dir == T4_MEMORY_READ) {
 584                last.word = le32_to_cpu((__force __le32)
 585                                        t4_read_reg(adap, addr));
 586                for (bp = (unsigned char *)buf, i = off; i < 4; i++)
 587                        bp[i] = last.byte[i];
 588        } else {
 589                last.word = *buf;
 590                for (i = off; i < 4; i++)
 591                        last.byte[i] = 0;
 592                t4_write_reg(adap, addr,
 593                             (__force u32)cpu_to_le32(last.word));
 594        }
 595}
 596
 597/**
 598 *      t4_memory_rw - read/write EDC 0, EDC 1 or MC via PCIE memory window
 599 *      @adap: the adapter
 600 *      @win: PCI-E Memory Window to use
 601 *      @mtype: memory type: MEM_EDC0, MEM_EDC1 or MEM_MC
 602 *      @addr: address within indicated memory type
 603 *      @len: amount of memory to transfer
 604 *      @hbuf: host memory buffer
 605 *      @dir: direction of transfer T4_MEMORY_READ (1) or T4_MEMORY_WRITE (0)
 606 *
 607 *      Reads/writes an [almost] arbitrary memory region in the firmware: the
 608 *      firmware memory address and host buffer must be aligned on 32-bit
 609 *      boundaries; the length may be arbitrary.  The memory is transferred as
 610 *      a raw byte sequence from/to the firmware's memory.  If this memory
 611 *      contains data structures which contain multi-byte integers, it's the
 612 *      caller's responsibility to perform appropriate byte order conversions.
 613 */
 614int t4_memory_rw(struct adapter *adap, int win, int mtype, u32 addr,
 615                 u32 len, void *hbuf, int dir)
 616{
 617        u32 pos, offset, resid, memoffset;
 618        u32 win_pf, mem_aperture, mem_base;
 619        u32 *buf;
 620        int ret;
 621
 622        /* Argument sanity checks ...
 623         */
 624        if (addr & 0x3 || (uintptr_t)hbuf & 0x3)
 625                return -EINVAL;
 626        buf = (u32 *)hbuf;
 627
 628        /* It's convenient to be able to handle lengths which aren't a
 629         * multiple of 32-bits because we often end up transferring files to
 630         * the firmware.  So we'll handle that by normalizing the length here
 631         * and then handling any residual transfer at the end.
 632         */
 633        resid = len & 0x3;
 634        len -= resid;
 635
 636        ret = t4_memory_rw_init(adap, win, mtype, &memoffset, &mem_base,
 637                                &mem_aperture);
 638        if (ret)
 639                return ret;
 640
 641        /* Determine the PCIE_MEM_ACCESS_OFFSET */
 642        addr = addr + memoffset;
 643
 644        win_pf = is_t4(adap->params.chip) ? 0 : PFNUM_V(adap->pf);
 645
 646        /* Calculate our initial PCI-E Memory Window Position and Offset into
 647         * that Window.
 648         */
 649        pos = addr & ~(mem_aperture - 1);
 650        offset = addr - pos;
 651
 652        /* Set up initial PCI-E Memory Window to cover the start of our
 653         * transfer.
 654         */
 655        t4_memory_update_win(adap, win, pos | win_pf);
 656
 657        /* Transfer data to/from the adapter as long as there's an integral
 658         * number of 32-bit transfers to complete.
 659         *
 660         * A note on Endianness issues:
 661         *
 662         * The "register" reads and writes below from/to the PCI-E Memory
 663         * Window invoke the standard adapter Big-Endian to PCI-E Link
 664         * Little-Endian "swizzel."  As a result, if we have the following
 665         * data in adapter memory:
 666         *
 667         *     Memory:  ... | b0 | b1 | b2 | b3 | ...
 668         *     Address:      i+0  i+1  i+2  i+3
 669         *
 670         * Then a read of the adapter memory via the PCI-E Memory Window
 671         * will yield:
 672         *
 673         *     x = readl(i)
 674         *         31                  0
 675         *         [ b3 | b2 | b1 | b0 ]
 676         *
 677         * If this value is stored into local memory on a Little-Endian system
 678         * it will show up correctly in local memory as:
 679         *
 680         *     ( ..., b0, b1, b2, b3, ... )
 681         *
 682         * But on a Big-Endian system, the store will show up in memory
 683         * incorrectly swizzled as:
 684         *
 685         *     ( ..., b3, b2, b1, b0, ... )
 686         *
 687         * So we need to account for this in the reads and writes to the
 688         * PCI-E Memory Window below by undoing the register read/write
 689         * swizzels.
 690         */
 691        while (len > 0) {
 692                if (dir == T4_MEMORY_READ)
 693                        *buf++ = le32_to_cpu((__force __le32)t4_read_reg(adap,
 694                                                mem_base + offset));
 695                else
 696                        t4_write_reg(adap, mem_base + offset,
 697                                     (__force u32)cpu_to_le32(*buf++));
 698                offset += sizeof(__be32);
 699                len -= sizeof(__be32);
 700
 701                /* If we've reached the end of our current window aperture,
 702                 * move the PCI-E Memory Window on to the next.  Note that
 703                 * doing this here after "len" may be 0 allows us to set up
 704                 * the PCI-E Memory Window for a possible final residual
 705                 * transfer below ...
 706                 */
 707                if (offset == mem_aperture) {
 708                        pos += mem_aperture;
 709                        offset = 0;
 710                        t4_memory_update_win(adap, win, pos | win_pf);
 711                }
 712        }
 713
 714        /* If the original transfer had a length which wasn't a multiple of
 715         * 32-bits, now's where we need to finish off the transfer of the
 716         * residual amount.  The PCI-E Memory Window has already been moved
 717         * above (if necessary) to cover this final transfer.
 718         */
 719        if (resid)
 720                t4_memory_rw_residual(adap, resid, mem_base + offset,
 721                                      (u8 *)buf, dir);
 722
 723        return 0;
 724}
 725
 726/* Return the specified PCI-E Configuration Space register from our Physical
 727 * Function.  We try first via a Firmware LDST Command since we prefer to let
 728 * the firmware own all of these registers, but if that fails we go for it
 729 * directly ourselves.
 730 */
 731u32 t4_read_pcie_cfg4(struct adapter *adap, int reg)
 732{
 733        u32 val, ldst_addrspace;
 734
 735        /* If fw_attach != 0, construct and send the Firmware LDST Command to
 736         * retrieve the specified PCI-E Configuration Space register.
 737         */
 738        struct fw_ldst_cmd ldst_cmd;
 739        int ret;
 740
 741        memset(&ldst_cmd, 0, sizeof(ldst_cmd));
 742        ldst_addrspace = FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_FUNC_PCIE);
 743        ldst_cmd.op_to_addrspace = cpu_to_be32(FW_CMD_OP_V(FW_LDST_CMD) |
 744                                               FW_CMD_REQUEST_F |
 745                                               FW_CMD_READ_F |
 746                                               ldst_addrspace);
 747        ldst_cmd.cycles_to_len16 = cpu_to_be32(FW_LEN16(ldst_cmd));
 748        ldst_cmd.u.pcie.select_naccess = FW_LDST_CMD_NACCESS_V(1);
 749        ldst_cmd.u.pcie.ctrl_to_fn =
 750                (FW_LDST_CMD_LC_F | FW_LDST_CMD_FN_V(adap->pf));
 751        ldst_cmd.u.pcie.r = reg;
 752
 753        /* If the LDST Command succeeds, return the result, otherwise
 754         * fall through to reading it directly ourselves ...
 755         */
 756        ret = t4_wr_mbox(adap, adap->mbox, &ldst_cmd, sizeof(ldst_cmd),
 757                         &ldst_cmd);
 758        if (ret == 0)
 759                val = be32_to_cpu(ldst_cmd.u.pcie.data[0]);
 760        else
 761                /* Read the desired Configuration Space register via the PCI-E
 762                 * Backdoor mechanism.
 763                 */
 764                t4_hw_pci_read_cfg4(adap, reg, &val);
 765        return val;
 766}
 767
 768/* Get the window based on base passed to it.
 769 * Window aperture is currently unhandled, but there is no use case for it
 770 * right now
 771 */
 772static u32 t4_get_window(struct adapter *adap, u32 pci_base, u64 pci_mask,
 773                         u32 memwin_base)
 774{
 775        u32 ret;
 776
 777        if (is_t4(adap->params.chip)) {
 778                u32 bar0;
 779
 780                /* Truncation intentional: we only read the bottom 32-bits of
 781                 * the 64-bit BAR0/BAR1 ...  We use the hardware backdoor
 782                 * mechanism to read BAR0 instead of using
 783                 * pci_resource_start() because we could be operating from
 784                 * within a Virtual Machine which is trapping our accesses to
 785                 * our Configuration Space and we need to set up the PCI-E
 786                 * Memory Window decoders with the actual addresses which will
 787                 * be coming across the PCI-E link.
 788                 */
 789                bar0 = t4_read_pcie_cfg4(adap, pci_base);
 790                bar0 &= pci_mask;
 791                adap->t4_bar0 = bar0;
 792
 793                ret = bar0 + memwin_base;
 794        } else {
 795                /* For T5, only relative offset inside the PCIe BAR is passed */
 796                ret = memwin_base;
 797        }
 798        return ret;
 799}
 800
 801/* Get the default utility window (win0) used by everyone */
 802u32 t4_get_util_window(struct adapter *adap)
 803{
 804        return t4_get_window(adap, PCI_BASE_ADDRESS_0,
 805                             PCI_BASE_ADDRESS_MEM_MASK, MEMWIN0_BASE);
 806}
 807
 808/* Set up memory window for accessing adapter memory ranges.  (Read
 809 * back MA register to ensure that changes propagate before we attempt
 810 * to use the new values.)
 811 */
 812void t4_setup_memwin(struct adapter *adap, u32 memwin_base, u32 window)
 813{
 814        t4_write_reg(adap,
 815                     PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window),
 816                     memwin_base | BIR_V(0) |
 817                     WINDOW_V(ilog2(MEMWIN0_APERTURE) - WINDOW_SHIFT_X));
 818        t4_read_reg(adap,
 819                    PCIE_MEM_ACCESS_REG(PCIE_MEM_ACCESS_BASE_WIN_A, window));
 820}
 821
 822/**
 823 *      t4_get_regs_len - return the size of the chips register set
 824 *      @adapter: the adapter
 825 *
 826 *      Returns the size of the chip's BAR0 register space.
 827 */
 828unsigned int t4_get_regs_len(struct adapter *adapter)
 829{
 830        unsigned int chip_version = CHELSIO_CHIP_VERSION(adapter->params.chip);
 831
 832        switch (chip_version) {
 833        case CHELSIO_T4:
 834                return T4_REGMAP_SIZE;
 835
 836        case CHELSIO_T5:
 837        case CHELSIO_T6:
 838                return T5_REGMAP_SIZE;
 839        }
 840
 841        dev_err(adapter->pdev_dev,
 842                "Unsupported chip version %d\n", chip_version);
 843        return 0;
 844}
 845
 846/**
 847 *      t4_get_regs - read chip registers into provided buffer
 848 *      @adap: the adapter
 849 *      @buf: register buffer
 850 *      @buf_size: size (in bytes) of register buffer
 851 *
 852 *      If the provided register buffer isn't large enough for the chip's
 853 *      full register range, the register dump will be truncated to the
 854 *      register buffer's size.
 855 */
 856void t4_get_regs(struct adapter *adap, void *buf, size_t buf_size)
 857{
 858        static const unsigned int t4_reg_ranges[] = {
 859                0x1008, 0x1108,
 860                0x1180, 0x1184,
 861                0x1190, 0x1194,
 862                0x11a0, 0x11a4,
 863                0x11b0, 0x11b4,
 864                0x11fc, 0x123c,
 865                0x1300, 0x173c,
 866                0x1800, 0x18fc,
 867                0x3000, 0x30d8,
 868                0x30e0, 0x30e4,
 869                0x30ec, 0x5910,
 870                0x5920, 0x5924,
 871                0x5960, 0x5960,
 872                0x5968, 0x5968,
 873                0x5970, 0x5970,
 874                0x5978, 0x5978,
 875                0x5980, 0x5980,
 876                0x5988, 0x5988,
 877                0x5990, 0x5990,
 878                0x5998, 0x5998,
 879                0x59a0, 0x59d4,
 880                0x5a00, 0x5ae0,
 881                0x5ae8, 0x5ae8,
 882                0x5af0, 0x5af0,
 883                0x5af8, 0x5af8,
 884                0x6000, 0x6098,
 885                0x6100, 0x6150,
 886                0x6200, 0x6208,
 887                0x6240, 0x6248,
 888                0x6280, 0x62b0,
 889                0x62c0, 0x6338,
 890                0x6370, 0x638c,
 891                0x6400, 0x643c,
 892                0x6500, 0x6524,
 893                0x6a00, 0x6a04,
 894                0x6a14, 0x6a38,
 895                0x6a60, 0x6a70,
 896                0x6a78, 0x6a78,
 897                0x6b00, 0x6b0c,
 898                0x6b1c, 0x6b84,
 899                0x6bf0, 0x6bf8,
 900                0x6c00, 0x6c0c,
 901                0x6c1c, 0x6c84,
 902                0x6cf0, 0x6cf8,
 903                0x6d00, 0x6d0c,
 904                0x6d1c, 0x6d84,
 905                0x6df0, 0x6df8,
 906                0x6e00, 0x6e0c,
 907                0x6e1c, 0x6e84,
 908                0x6ef0, 0x6ef8,
 909                0x6f00, 0x6f0c,
 910                0x6f1c, 0x6f84,
 911                0x6ff0, 0x6ff8,
 912                0x7000, 0x700c,
 913                0x701c, 0x7084,
 914                0x70f0, 0x70f8,
 915                0x7100, 0x710c,
 916                0x711c, 0x7184,
 917                0x71f0, 0x71f8,
 918                0x7200, 0x720c,
 919                0x721c, 0x7284,
 920                0x72f0, 0x72f8,
 921                0x7300, 0x730c,
 922                0x731c, 0x7384,
 923                0x73f0, 0x73f8,
 924                0x7400, 0x7450,
 925                0x7500, 0x7530,
 926                0x7600, 0x760c,
 927                0x7614, 0x761c,
 928                0x7680, 0x76cc,
 929                0x7700, 0x7798,
 930                0x77c0, 0x77fc,
 931                0x7900, 0x79fc,
 932                0x7b00, 0x7b58,
 933                0x7b60, 0x7b84,
 934                0x7b8c, 0x7c38,
 935                0x7d00, 0x7d38,
 936                0x7d40, 0x7d80,
 937                0x7d8c, 0x7ddc,
 938                0x7de4, 0x7e04,
 939                0x7e10, 0x7e1c,
 940                0x7e24, 0x7e38,
 941                0x7e40, 0x7e44,
 942                0x7e4c, 0x7e78,
 943                0x7e80, 0x7ea4,
 944                0x7eac, 0x7edc,
 945                0x7ee8, 0x7efc,
 946                0x8dc0, 0x8e04,
 947                0x8e10, 0x8e1c,
 948                0x8e30, 0x8e78,
 949                0x8ea0, 0x8eb8,
 950                0x8ec0, 0x8f6c,
 951                0x8fc0, 0x9008,
 952                0x9010, 0x9058,
 953                0x9060, 0x9060,
 954                0x9068, 0x9074,
 955                0x90fc, 0x90fc,
 956                0x9400, 0x9408,
 957                0x9410, 0x9458,
 958                0x9600, 0x9600,
 959                0x9608, 0x9638,
 960                0x9640, 0x96bc,
 961                0x9800, 0x9808,
 962                0x9820, 0x983c,
 963                0x9850, 0x9864,
 964                0x9c00, 0x9c6c,
 965                0x9c80, 0x9cec,
 966                0x9d00, 0x9d6c,
 967                0x9d80, 0x9dec,
 968                0x9e00, 0x9e6c,
 969                0x9e80, 0x9eec,
 970                0x9f00, 0x9f6c,
 971                0x9f80, 0x9fec,
 972                0xd004, 0xd004,
 973                0xd010, 0xd03c,
 974                0xdfc0, 0xdfe0,
 975                0xe000, 0xea7c,
 976                0xf000, 0x11110,
 977                0x11118, 0x11190,
 978                0x19040, 0x1906c,
 979                0x19078, 0x19080,
 980                0x1908c, 0x190e4,
 981                0x190f0, 0x190f8,
 982                0x19100, 0x19110,
 983                0x19120, 0x19124,
 984                0x19150, 0x19194,
 985                0x1919c, 0x191b0,
 986                0x191d0, 0x191e8,
 987                0x19238, 0x1924c,
 988                0x193f8, 0x1943c,
 989                0x1944c, 0x19474,
 990                0x19490, 0x194e0,
 991                0x194f0, 0x194f8,
 992                0x19800, 0x19c08,
 993                0x19c10, 0x19c90,
 994                0x19ca0, 0x19ce4,
 995                0x19cf0, 0x19d40,
 996                0x19d50, 0x19d94,
 997                0x19da0, 0x19de8,
 998                0x19df0, 0x19e40,
 999                0x19e50, 0x19e90,
1000                0x19ea0, 0x19f4c,
1001                0x1a000, 0x1a004,
1002                0x1a010, 0x1a06c,
1003                0x1a0b0, 0x1a0e4,
1004                0x1a0ec, 0x1a0f4,
1005                0x1a100, 0x1a108,
1006                0x1a114, 0x1a120,
1007                0x1a128, 0x1a130,
1008                0x1a138, 0x1a138,
1009                0x1a190, 0x1a1c4,
1010                0x1a1fc, 0x1a1fc,
1011                0x1e040, 0x1e04c,
1012                0x1e284, 0x1e28c,
1013                0x1e2c0, 0x1e2c0,
1014                0x1e2e0, 0x1e2e0,
1015                0x1e300, 0x1e384,
1016                0x1e3c0, 0x1e3c8,
1017                0x1e440, 0x1e44c,
1018                0x1e684, 0x1e68c,
1019                0x1e6c0, 0x1e6c0,
1020                0x1e6e0, 0x1e6e0,
1021                0x1e700, 0x1e784,
1022                0x1e7c0, 0x1e7c8,
1023                0x1e840, 0x1e84c,
1024                0x1ea84, 0x1ea8c,
1025                0x1eac0, 0x1eac0,
1026                0x1eae0, 0x1eae0,
1027                0x1eb00, 0x1eb84,
1028                0x1ebc0, 0x1ebc8,
1029                0x1ec40, 0x1ec4c,
1030                0x1ee84, 0x1ee8c,
1031                0x1eec0, 0x1eec0,
1032                0x1eee0, 0x1eee0,
1033                0x1ef00, 0x1ef84,
1034                0x1efc0, 0x1efc8,
1035                0x1f040, 0x1f04c,
1036                0x1f284, 0x1f28c,
1037                0x1f2c0, 0x1f2c0,
1038                0x1f2e0, 0x1f2e0,
1039                0x1f300, 0x1f384,
1040                0x1f3c0, 0x1f3c8,
1041                0x1f440, 0x1f44c,
1042                0x1f684, 0x1f68c,
1043                0x1f6c0, 0x1f6c0,
1044                0x1f6e0, 0x1f6e0,
1045                0x1f700, 0x1f784,
1046                0x1f7c0, 0x1f7c8,
1047                0x1f840, 0x1f84c,
1048                0x1fa84, 0x1fa8c,
1049                0x1fac0, 0x1fac0,
1050                0x1fae0, 0x1fae0,
1051                0x1fb00, 0x1fb84,
1052                0x1fbc0, 0x1fbc8,
1053                0x1fc40, 0x1fc4c,
1054                0x1fe84, 0x1fe8c,
1055                0x1fec0, 0x1fec0,
1056                0x1fee0, 0x1fee0,
1057                0x1ff00, 0x1ff84,
1058                0x1ffc0, 0x1ffc8,
1059                0x20000, 0x2002c,
1060                0x20100, 0x2013c,
1061                0x20190, 0x201a0,
1062                0x201a8, 0x201b8,
1063                0x201c4, 0x201c8,
1064                0x20200, 0x20318,
1065                0x20400, 0x204b4,
1066                0x204c0, 0x20528,
1067                0x20540, 0x20614,
1068                0x21000, 0x21040,
1069                0x2104c, 0x21060,
1070                0x210c0, 0x210ec,
1071                0x21200, 0x21268,
1072                0x21270, 0x21284,
1073                0x212fc, 0x21388,
1074                0x21400, 0x21404,
1075                0x21500, 0x21500,
1076                0x21510, 0x21518,
1077                0x2152c, 0x21530,
1078                0x2153c, 0x2153c,
1079                0x21550, 0x21554,
1080                0x21600, 0x21600,
1081                0x21608, 0x2161c,
1082                0x21624, 0x21628,
1083                0x21630, 0x21634,
1084                0x2163c, 0x2163c,
1085                0x21700, 0x2171c,
1086                0x21780, 0x2178c,
1087                0x21800, 0x21818,
1088                0x21820, 0x21828,
1089                0x21830, 0x21848,
1090                0x21850, 0x21854,
1091                0x21860, 0x21868,
1092                0x21870, 0x21870,
1093                0x21878, 0x21898,
1094                0x218a0, 0x218a8,
1095                0x218b0, 0x218c8,
1096                0x218d0, 0x218d4,
1097                0x218e0, 0x218e8,
1098                0x218f0, 0x218f0,
1099                0x218f8, 0x21a18,
1100                0x21a20, 0x21a28,
1101                0x21a30, 0x21a48,
1102                0x21a50, 0x21a54,
1103                0x21a60, 0x21a68,
1104                0x21a70, 0x21a70,
1105                0x21a78, 0x21a98,
1106                0x21aa0, 0x21aa8,
1107                0x21ab0, 0x21ac8,
1108                0x21ad0, 0x21ad4,
1109                0x21ae0, 0x21ae8,
1110                0x21af0, 0x21af0,
1111                0x21af8, 0x21c18,
1112                0x21c20, 0x21c20,
1113                0x21c28, 0x21c30,
1114                0x21c38, 0x21c38,
1115                0x21c80, 0x21c98,
1116                0x21ca0, 0x21ca8,
1117                0x21cb0, 0x21cc8,
1118                0x21cd0, 0x21cd4,
1119                0x21ce0, 0x21ce8,
1120                0x21cf0, 0x21cf0,
1121                0x21cf8, 0x21d7c,
1122                0x21e00, 0x21e04,
1123                0x22000, 0x2202c,
1124                0x22100, 0x2213c,
1125                0x22190, 0x221a0,
1126                0x221a8, 0x221b8,
1127                0x221c4, 0x221c8,
1128                0x22200, 0x22318,
1129                0x22400, 0x224b4,
1130                0x224c0, 0x22528,
1131                0x22540, 0x22614,
1132                0x23000, 0x23040,
1133                0x2304c, 0x23060,
1134                0x230c0, 0x230ec,
1135                0x23200, 0x23268,
1136                0x23270, 0x23284,
1137                0x232fc, 0x23388,
1138                0x23400, 0x23404,
1139                0x23500, 0x23500,
1140                0x23510, 0x23518,
1141                0x2352c, 0x23530,
1142                0x2353c, 0x2353c,
1143                0x23550, 0x23554,
1144                0x23600, 0x23600,
1145                0x23608, 0x2361c,
1146                0x23624, 0x23628,
1147                0x23630, 0x23634,
1148                0x2363c, 0x2363c,
1149                0x23700, 0x2371c,
1150                0x23780, 0x2378c,
1151                0x23800, 0x23818,
1152                0x23820, 0x23828,
1153                0x23830, 0x23848,
1154                0x23850, 0x23854,
1155                0x23860, 0x23868,
1156                0x23870, 0x23870,
1157                0x23878, 0x23898,
1158                0x238a0, 0x238a8,
1159                0x238b0, 0x238c8,
1160                0x238d0, 0x238d4,
1161                0x238e0, 0x238e8,
1162                0x238f0, 0x238f0,
1163                0x238f8, 0x23a18,
1164                0x23a20, 0x23a28,
1165                0x23a30, 0x23a48,
1166                0x23a50, 0x23a54,
1167                0x23a60, 0x23a68,
1168                0x23a70, 0x23a70,
1169                0x23a78, 0x23a98,
1170                0x23aa0, 0x23aa8,
1171                0x23ab0, 0x23ac8,
1172                0x23ad0, 0x23ad4,
1173                0x23ae0, 0x23ae8,
1174                0x23af0, 0x23af0,
1175                0x23af8, 0x23c18,
1176                0x23c20, 0x23c20,
1177                0x23c28, 0x23c30,
1178                0x23c38, 0x23c38,
1179                0x23c80, 0x23c98,
1180                0x23ca0, 0x23ca8,
1181                0x23cb0, 0x23cc8,
1182                0x23cd0, 0x23cd4,
1183                0x23ce0, 0x23ce8,
1184                0x23cf0, 0x23cf0,
1185                0x23cf8, 0x23d7c,
1186                0x23e00, 0x23e04,
1187                0x24000, 0x2402c,
1188                0x24100, 0x2413c,
1189                0x24190, 0x241a0,
1190                0x241a8, 0x241b8,
1191                0x241c4, 0x241c8,
1192                0x24200, 0x24318,
1193                0x24400, 0x244b4,
1194                0x244c0, 0x24528,
1195                0x24540, 0x24614,
1196                0x25000, 0x25040,
1197                0x2504c, 0x25060,
1198                0x250c0, 0x250ec,
1199                0x25200, 0x25268,
1200                0x25270, 0x25284,
1201                0x252fc, 0x25388,
1202                0x25400, 0x25404,
1203                0x25500, 0x25500,
1204                0x25510, 0x25518,
1205                0x2552c, 0x25530,
1206                0x2553c, 0x2553c,
1207                0x25550, 0x25554,
1208                0x25600, 0x25600,
1209                0x25608, 0x2561c,
1210                0x25624, 0x25628,
1211                0x25630, 0x25634,
1212                0x2563c, 0x2563c,
1213                0x25700, 0x2571c,
1214                0x25780, 0x2578c,
1215                0x25800, 0x25818,
1216                0x25820, 0x25828,
1217                0x25830, 0x25848,
1218                0x25850, 0x25854,
1219                0x25860, 0x25868,
1220                0x25870, 0x25870,
1221                0x25878, 0x25898,
1222                0x258a0, 0x258a8,
1223                0x258b0, 0x258c8,
1224                0x258d0, 0x258d4,
1225                0x258e0, 0x258e8,
1226                0x258f0, 0x258f0,
1227                0x258f8, 0x25a18,
1228                0x25a20, 0x25a28,
1229                0x25a30, 0x25a48,
1230                0x25a50, 0x25a54,
1231                0x25a60, 0x25a68,
1232                0x25a70, 0x25a70,
1233                0x25a78, 0x25a98,
1234                0x25aa0, 0x25aa8,
1235                0x25ab0, 0x25ac8,
1236                0x25ad0, 0x25ad4,
1237                0x25ae0, 0x25ae8,
1238                0x25af0, 0x25af0,
1239                0x25af8, 0x25c18,
1240                0x25c20, 0x25c20,
1241                0x25c28, 0x25c30,
1242                0x25c38, 0x25c38,
1243                0x25c80, 0x25c98,
1244                0x25ca0, 0x25ca8,
1245                0x25cb0, 0x25cc8,
1246                0x25cd0, 0x25cd4,
1247                0x25ce0, 0x25ce8,
1248                0x25cf0, 0x25cf0,
1249                0x25cf8, 0x25d7c,
1250                0x25e00, 0x25e04,
1251                0x26000, 0x2602c,
1252                0x26100, 0x2613c,
1253                0x26190, 0x261a0,
1254                0x261a8, 0x261b8,
1255                0x261c4, 0x261c8,
1256                0x26200, 0x26318,
1257                0x26400, 0x264b4,
1258                0x264c0, 0x26528,
1259                0x26540, 0x26614,
1260                0x27000, 0x27040,
1261                0x2704c, 0x27060,
1262                0x270c0, 0x270ec,
1263                0x27200, 0x27268,
1264                0x27270, 0x27284,
1265                0x272fc, 0x27388,
1266                0x27400, 0x27404,
1267                0x27500, 0x27500,
1268                0x27510, 0x27518,
1269                0x2752c, 0x27530,
1270                0x2753c, 0x2753c,
1271                0x27550, 0x27554,
1272                0x27600, 0x27600,
1273                0x27608, 0x2761c,
1274                0x27624, 0x27628,
1275                0x27630, 0x27634,
1276                0x2763c, 0x2763c,
1277                0x27700, 0x2771c,
1278                0x27780, 0x2778c,
1279                0x27800, 0x27818,
1280                0x27820, 0x27828,
1281                0x27830, 0x27848,
1282                0x27850, 0x27854,
1283                0x27860, 0x27868,
1284                0x27870, 0x27870,
1285                0x27878, 0x27898,
1286                0x278a0, 0x278a8,
1287                0x278b0, 0x278c8,
1288                0x278d0, 0x278d4,
1289                0x278e0, 0x278e8,
1290                0x278f0, 0x278f0,
1291                0x278f8, 0x27a18,
1292                0x27a20, 0x27a28,
1293                0x27a30, 0x27a48,
1294                0x27a50, 0x27a54,
1295                0x27a60, 0x27a68,
1296                0x27a70, 0x27a70,
1297                0x27a78, 0x27a98,
1298                0x27aa0, 0x27aa8,
1299                0x27ab0, 0x27ac8,
1300                0x27ad0, 0x27ad4,
1301                0x27ae0, 0x27ae8,
1302                0x27af0, 0x27af0,
1303                0x27af8, 0x27c18,
1304                0x27c20, 0x27c20,
1305                0x27c28, 0x27c30,
1306                0x27c38, 0x27c38,
1307                0x27c80, 0x27c98,
1308                0x27ca0, 0x27ca8,
1309                0x27cb0, 0x27cc8,
1310                0x27cd0, 0x27cd4,
1311                0x27ce0, 0x27ce8,
1312                0x27cf0, 0x27cf0,
1313                0x27cf8, 0x27d7c,
1314                0x27e00, 0x27e04,
1315        };
1316
1317        static const unsigned int t5_reg_ranges[] = {
1318                0x1008, 0x10c0,
1319                0x10cc, 0x10f8,
1320                0x1100, 0x1100,
1321                0x110c, 0x1148,
1322                0x1180, 0x1184,
1323                0x1190, 0x1194,
1324                0x11a0, 0x11a4,
1325                0x11b0, 0x11b4,
1326                0x11fc, 0x123c,
1327                0x1280, 0x173c,
1328                0x1800, 0x18fc,
1329                0x3000, 0x3028,
1330                0x3060, 0x30b0,
1331                0x30b8, 0x30d8,
1332                0x30e0, 0x30fc,
1333                0x3140, 0x357c,
1334                0x35a8, 0x35cc,
1335                0x35ec, 0x35ec,
1336                0x3600, 0x5624,
1337                0x56cc, 0x56ec,
1338                0x56f4, 0x5720,
1339                0x5728, 0x575c,
1340                0x580c, 0x5814,
1341                0x5890, 0x589c,
1342                0x58a4, 0x58ac,
1343                0x58b8, 0x58bc,
1344                0x5940, 0x59c8,
1345                0x59d0, 0x59dc,
1346                0x59fc, 0x5a18,
1347                0x5a60, 0x5a70,
1348                0x5a80, 0x5a9c,
1349                0x5b94, 0x5bfc,
1350                0x6000, 0x6020,
1351                0x6028, 0x6040,
1352                0x6058, 0x609c,
1353                0x60a8, 0x614c,
1354                0x7700, 0x7798,
1355                0x77c0, 0x78fc,
1356                0x7b00, 0x7b58,
1357                0x7b60, 0x7b84,
1358                0x7b8c, 0x7c54,
1359                0x7d00, 0x7d38,
1360                0x7d40, 0x7d80,
1361                0x7d8c, 0x7ddc,
1362                0x7de4, 0x7e04,
1363                0x7e10, 0x7e1c,
1364                0x7e24, 0x7e38,
1365                0x7e40, 0x7e44,
1366                0x7e4c, 0x7e78,
1367                0x7e80, 0x7edc,
1368                0x7ee8, 0x7efc,
1369                0x8dc0, 0x8de0,
1370                0x8df8, 0x8e04,
1371                0x8e10, 0x8e84,
1372                0x8ea0, 0x8f84,
1373                0x8fc0, 0x9058,
1374                0x9060, 0x9060,
1375                0x9068, 0x90f8,
1376                0x9400, 0x9408,
1377                0x9410, 0x9470,
1378                0x9600, 0x9600,
1379                0x9608, 0x9638,
1380                0x9640, 0x96f4,
1381                0x9800, 0x9808,
1382                0x9810, 0x9864,
1383                0x9c00, 0x9c6c,
1384                0x9c80, 0x9cec,
1385                0x9d00, 0x9d6c,
1386                0x9d80, 0x9dec,
1387                0x9e00, 0x9e6c,
1388                0x9e80, 0x9eec,
1389                0x9f00, 0x9f6c,
1390                0x9f80, 0xa020,
1391                0xd000, 0xd004,
1392                0xd010, 0xd03c,
1393                0xdfc0, 0xdfe0,
1394                0xe000, 0x1106c,
1395                0x11074, 0x11088,
1396                0x1109c, 0x1117c,
1397                0x11190, 0x11204,
1398                0x19040, 0x1906c,
1399                0x19078, 0x19080,
1400                0x1908c, 0x190e8,
1401                0x190f0, 0x190f8,
1402                0x19100, 0x19110,
1403                0x19120, 0x19124,
1404                0x19150, 0x19194,
1405                0x1919c, 0x191b0,
1406                0x191d0, 0x191e8,
1407                0x19238, 0x19290,
1408                0x193f8, 0x19428,
1409                0x19430, 0x19444,
1410                0x1944c, 0x1946c,
1411                0x19474, 0x19474,
1412                0x19490, 0x194cc,
1413                0x194f0, 0x194f8,
1414                0x19c00, 0x19c08,
1415                0x19c10, 0x19c60,
1416                0x19c94, 0x19ce4,
1417                0x19cf0, 0x19d40,
1418                0x19d50, 0x19d94,
1419                0x19da0, 0x19de8,
1420                0x19df0, 0x19e10,
1421                0x19e50, 0x19e90,
1422                0x19ea0, 0x19f24,
1423                0x19f34, 0x19f34,
1424                0x19f40, 0x19f50,
1425                0x19f90, 0x19fb4,
1426                0x19fc4, 0x19fe4,
1427                0x1a000, 0x1a004,
1428                0x1a010, 0x1a06c,
1429                0x1a0b0, 0x1a0e4,
1430                0x1a0ec, 0x1a0f8,
1431                0x1a100, 0x1a108,
1432                0x1a114, 0x1a130,
1433                0x1a138, 0x1a1c4,
1434                0x1a1fc, 0x1a1fc,
1435                0x1e008, 0x1e00c,
1436                0x1e040, 0x1e044,
1437                0x1e04c, 0x1e04c,
1438                0x1e284, 0x1e290,
1439                0x1e2c0, 0x1e2c0,
1440                0x1e2e0, 0x1e2e0,
1441                0x1e300, 0x1e384,
1442                0x1e3c0, 0x1e3c8,
1443                0x1e408, 0x1e40c,
1444                0x1e440, 0x1e444,
1445                0x1e44c, 0x1e44c,
1446                0x1e684, 0x1e690,
1447                0x1e6c0, 0x1e6c0,
1448                0x1e6e0, 0x1e6e0,
1449                0x1e700, 0x1e784,
1450                0x1e7c0, 0x1e7c8,
1451                0x1e808, 0x1e80c,
1452                0x1e840, 0x1e844,
1453                0x1e84c, 0x1e84c,
1454                0x1ea84, 0x1ea90,
1455                0x1eac0, 0x1eac0,
1456                0x1eae0, 0x1eae0,
1457                0x1eb00, 0x1eb84,
1458                0x1ebc0, 0x1ebc8,
1459                0x1ec08, 0x1ec0c,
1460                0x1ec40, 0x1ec44,
1461                0x1ec4c, 0x1ec4c,
1462                0x1ee84, 0x1ee90,
1463                0x1eec0, 0x1eec0,
1464                0x1eee0, 0x1eee0,
1465                0x1ef00, 0x1ef84,
1466                0x1efc0, 0x1efc8,
1467                0x1f008, 0x1f00c,
1468                0x1f040, 0x1f044,
1469                0x1f04c, 0x1f04c,
1470                0x1f284, 0x1f290,
1471                0x1f2c0, 0x1f2c0,
1472                0x1f2e0, 0x1f2e0,
1473                0x1f300, 0x1f384,
1474                0x1f3c0, 0x1f3c8,
1475                0x1f408, 0x1f40c,
1476                0x1f440, 0x1f444,
1477                0x1f44c, 0x1f44c,
1478                0x1f684, 0x1f690,
1479                0x1f6c0, 0x1f6c0,
1480                0x1f6e0, 0x1f6e0,
1481                0x1f700, 0x1f784,
1482                0x1f7c0, 0x1f7c8,
1483                0x1f808, 0x1f80c,
1484                0x1f840, 0x1f844,
1485                0x1f84c, 0x1f84c,
1486                0x1fa84, 0x1fa90,
1487                0x1fac0, 0x1fac0,
1488                0x1fae0, 0x1fae0,
1489                0x1fb00, 0x1fb84,
1490                0x1fbc0, 0x1fbc8,
1491                0x1fc08, 0x1fc0c,
1492                0x1fc40, 0x1fc44,
1493                0x1fc4c, 0x1fc4c,
1494                0x1fe84, 0x1fe90,
1495                0x1fec0, 0x1fec0,
1496                0x1fee0, 0x1fee0,
1497                0x1ff00, 0x1ff84,
1498                0x1ffc0, 0x1ffc8,
1499                0x30000, 0x30030,
1500                0x30100, 0x30144,
1501                0x30190, 0x301a0,
1502                0x301a8, 0x301b8,
1503                0x301c4, 0x301c8,
1504                0x301d0, 0x301d0,
1505                0x30200, 0x30318,
1506                0x30400, 0x304b4,
1507                0x304c0, 0x3052c,
1508                0x30540, 0x3061c,
1509                0x30800, 0x30828,
1510                0x30834, 0x30834,
1511                0x308c0, 0x30908,
1512                0x30910, 0x309ac,
1513                0x30a00, 0x30a14,
1514                0x30a1c, 0x30a2c,
1515                0x30a44, 0x30a50,
1516                0x30a74, 0x30a74,
1517                0x30a7c, 0x30afc,
1518                0x30b08, 0x30c24,
1519                0x30d00, 0x30d00,
1520                0x30d08, 0x30d14,
1521                0x30d1c, 0x30d20,
1522                0x30d3c, 0x30d3c,
1523                0x30d48, 0x30d50,
1524                0x31200, 0x3120c,
1525                0x31220, 0x31220,
1526                0x31240, 0x31240,
1527                0x31600, 0x3160c,
1528                0x31a00, 0x31a1c,
1529                0x31e00, 0x31e20,
1530                0x31e38, 0x31e3c,
1531                0x31e80, 0x31e80,
1532                0x31e88, 0x31ea8,
1533                0x31eb0, 0x31eb4,
1534                0x31ec8, 0x31ed4,
1535                0x31fb8, 0x32004,
1536                0x32200, 0x32200,
1537                0x32208, 0x32240,
1538                0x32248, 0x32280,
1539                0x32288, 0x322c0,
1540                0x322c8, 0x322fc,
1541                0x32600, 0x32630,
1542                0x32a00, 0x32abc,
1543                0x32b00, 0x32b10,
1544                0x32b20, 0x32b30,
1545                0x32b40, 0x32b50,
1546                0x32b60, 0x32b70,
1547                0x33000, 0x33028,
1548                0x33030, 0x33048,
1549                0x33060, 0x33068,
1550                0x33070, 0x3309c,
1551                0x330f0, 0x33128,
1552                0x33130, 0x33148,
1553                0x33160, 0x33168,
1554                0x33170, 0x3319c,
1555                0x331f0, 0x33238,
1556                0x33240, 0x33240,
1557                0x33248, 0x33250,
1558                0x3325c, 0x33264,
1559                0x33270, 0x332b8,
1560                0x332c0, 0x332e4,
1561                0x332f8, 0x33338,
1562                0x33340, 0x33340,
1563                0x33348, 0x33350,
1564                0x3335c, 0x33364,
1565                0x33370, 0x333b8,
1566                0x333c0, 0x333e4,
1567                0x333f8, 0x33428,
1568                0x33430, 0x33448,
1569                0x33460, 0x33468,
1570                0x33470, 0x3349c,
1571                0x334f0, 0x33528,
1572                0x33530, 0x33548,
1573                0x33560, 0x33568,
1574                0x33570, 0x3359c,
1575                0x335f0, 0x33638,
1576                0x33640, 0x33640,
1577                0x33648, 0x33650,
1578                0x3365c, 0x33664,
1579                0x33670, 0x336b8,
1580                0x336c0, 0x336e4,
1581                0x336f8, 0x33738,
1582                0x33740, 0x33740,
1583                0x33748, 0x33750,
1584                0x3375c, 0x33764,
1585                0x33770, 0x337b8,
1586                0x337c0, 0x337e4,
1587                0x337f8, 0x337fc,
1588                0x33814, 0x33814,
1589                0x3382c, 0x3382c,
1590                0x33880, 0x3388c,
1591                0x338e8, 0x338ec,
1592                0x33900, 0x33928,
1593                0x33930, 0x33948,
1594                0x33960, 0x33968,
1595                0x33970, 0x3399c,
1596                0x339f0, 0x33a38,
1597                0x33a40, 0x33a40,
1598                0x33a48, 0x33a50,
1599                0x33a5c, 0x33a64,
1600                0x33a70, 0x33ab8,
1601                0x33ac0, 0x33ae4,
1602                0x33af8, 0x33b10,
1603                0x33b28, 0x33b28,
1604                0x33b3c, 0x33b50,
1605                0x33bf0, 0x33c10,
1606                0x33c28, 0x33c28,
1607                0x33c3c, 0x33c50,
1608                0x33cf0, 0x33cfc,
1609                0x34000, 0x34030,
1610                0x34100, 0x34144,
1611                0x34190, 0x341a0,
1612                0x341a8, 0x341b8,
1613                0x341c4, 0x341c8,
1614                0x341d0, 0x341d0,
1615                0x34200, 0x34318,
1616                0x34400, 0x344b4,
1617                0x344c0, 0x3452c,
1618                0x34540, 0x3461c,
1619                0x34800, 0x34828,
1620                0x34834, 0x34834,
1621                0x348c0, 0x34908,
1622                0x34910, 0x349ac,
1623                0x34a00, 0x34a14,
1624                0x34a1c, 0x34a2c,
1625                0x34a44, 0x34a50,
1626                0x34a74, 0x34a74,
1627                0x34a7c, 0x34afc,
1628                0x34b08, 0x34c24,
1629                0x34d00, 0x34d00,
1630                0x34d08, 0x34d14,
1631                0x34d1c, 0x34d20,
1632                0x34d3c, 0x34d3c,
1633                0x34d48, 0x34d50,
1634                0x35200, 0x3520c,
1635                0x35220, 0x35220,
1636                0x35240, 0x35240,
1637                0x35600, 0x3560c,
1638                0x35a00, 0x35a1c,
1639                0x35e00, 0x35e20,
1640                0x35e38, 0x35e3c,
1641                0x35e80, 0x35e80,
1642                0x35e88, 0x35ea8,
1643                0x35eb0, 0x35eb4,
1644                0x35ec8, 0x35ed4,
1645                0x35fb8, 0x36004,
1646                0x36200, 0x36200,
1647                0x36208, 0x36240,
1648                0x36248, 0x36280,
1649                0x36288, 0x362c0,
1650                0x362c8, 0x362fc,
1651                0x36600, 0x36630,
1652                0x36a00, 0x36abc,
1653                0x36b00, 0x36b10,
1654                0x36b20, 0x36b30,
1655                0x36b40, 0x36b50,
1656                0x36b60, 0x36b70,
1657                0x37000, 0x37028,
1658                0x37030, 0x37048,
1659                0x37060, 0x37068,
1660                0x37070, 0x3709c,
1661                0x370f0, 0x37128,
1662                0x37130, 0x37148,
1663                0x37160, 0x37168,
1664                0x37170, 0x3719c,
1665                0x371f0, 0x37238,
1666                0x37240, 0x37240,
1667                0x37248, 0x37250,
1668                0x3725c, 0x37264,
1669                0x37270, 0x372b8,
1670                0x372c0, 0x372e4,
1671                0x372f8, 0x37338,
1672                0x37340, 0x37340,
1673                0x37348, 0x37350,
1674                0x3735c, 0x37364,
1675                0x37370, 0x373b8,
1676                0x373c0, 0x373e4,
1677                0x373f8, 0x37428,
1678                0x37430, 0x37448,
1679                0x37460, 0x37468,
1680                0x37470, 0x3749c,
1681                0x374f0, 0x37528,
1682                0x37530, 0x37548,
1683                0x37560, 0x37568,
1684                0x37570, 0x3759c,
1685                0x375f0, 0x37638,
1686                0x37640, 0x37640,
1687                0x37648, 0x37650,
1688                0x3765c, 0x37664,
1689                0x37670, 0x376b8,
1690                0x376c0, 0x376e4,
1691                0x376f8, 0x37738,
1692                0x37740, 0x37740,
1693                0x37748, 0x37750,
1694                0x3775c, 0x37764,
1695                0x37770, 0x377b8,
1696                0x377c0, 0x377e4,
1697                0x377f8, 0x377fc,
1698                0x37814, 0x37814,
1699                0x3782c, 0x3782c,
1700                0x37880, 0x3788c,
1701                0x378e8, 0x378ec,
1702                0x37900, 0x37928,
1703                0x37930, 0x37948,
1704                0x37960, 0x37968,
1705                0x37970, 0x3799c,
1706                0x379f0, 0x37a38,
1707                0x37a40, 0x37a40,
1708                0x37a48, 0x37a50,
1709                0x37a5c, 0x37a64,
1710                0x37a70, 0x37ab8,
1711                0x37ac0, 0x37ae4,
1712                0x37af8, 0x37b10,
1713                0x37b28, 0x37b28,
1714                0x37b3c, 0x37b50,
1715                0x37bf0, 0x37c10,
1716                0x37c28, 0x37c28,
1717                0x37c3c, 0x37c50,
1718                0x37cf0, 0x37cfc,
1719                0x38000, 0x38030,
1720                0x38100, 0x38144,
1721                0x38190, 0x381a0,
1722                0x381a8, 0x381b8,
1723                0x381c4, 0x381c8,
1724                0x381d0, 0x381d0,
1725                0x38200, 0x38318,
1726                0x38400, 0x384b4,
1727                0x384c0, 0x3852c,
1728                0x38540, 0x3861c,
1729                0x38800, 0x38828,
1730                0x38834, 0x38834,
1731                0x388c0, 0x38908,
1732                0x38910, 0x389ac,
1733                0x38a00, 0x38a14,
1734                0x38a1c, 0x38a2c,
1735                0x38a44, 0x38a50,
1736                0x38a74, 0x38a74,
1737                0x38a7c, 0x38afc,
1738                0x38b08, 0x38c24,
1739                0x38d00, 0x38d00,
1740                0x38d08, 0x38d14,
1741                0x38d1c, 0x38d20,
1742                0x38d3c, 0x38d3c,
1743                0x38d48, 0x38d50,
1744                0x39200, 0x3920c,
1745                0x39220, 0x39220,
1746                0x39240, 0x39240,
1747                0x39600, 0x3960c,
1748                0x39a00, 0x39a1c,
1749                0x39e00, 0x39e20,
1750                0x39e38, 0x39e3c,
1751                0x39e80, 0x39e80,
1752                0x39e88, 0x39ea8,
1753                0x39eb0, 0x39eb4,
1754                0x39ec8, 0x39ed4,
1755                0x39fb8, 0x3a004,
1756                0x3a200, 0x3a200,
1757                0x3a208, 0x3a240,
1758                0x3a248, 0x3a280,
1759                0x3a288, 0x3a2c0,
1760                0x3a2c8, 0x3a2fc,
1761                0x3a600, 0x3a630,
1762                0x3aa00, 0x3aabc,
1763                0x3ab00, 0x3ab10,
1764                0x3ab20, 0x3ab30,
1765                0x3ab40, 0x3ab50,
1766                0x3ab60, 0x3ab70,
1767                0x3b000, 0x3b028,
1768                0x3b030, 0x3b048,
1769                0x3b060, 0x3b068,
1770                0x3b070, 0x3b09c,
1771                0x3b0f0, 0x3b128,
1772                0x3b130, 0x3b148,
1773                0x3b160, 0x3b168,
1774                0x3b170, 0x3b19c,
1775                0x3b1f0, 0x3b238,
1776                0x3b240, 0x3b240,
1777                0x3b248, 0x3b250,
1778                0x3b25c, 0x3b264,
1779                0x3b270, 0x3b2b8,
1780                0x3b2c0, 0x3b2e4,
1781                0x3b2f8, 0x3b338,
1782                0x3b340, 0x3b340,
1783                0x3b348, 0x3b350,
1784                0x3b35c, 0x3b364,
1785                0x3b370, 0x3b3b8,
1786                0x3b3c0, 0x3b3e4,
1787                0x3b3f8, 0x3b428,
1788                0x3b430, 0x3b448,
1789                0x3b460, 0x3b468,
1790                0x3b470, 0x3b49c,
1791                0x3b4f0, 0x3b528,
1792                0x3b530, 0x3b548,
1793                0x3b560, 0x3b568,
1794                0x3b570, 0x3b59c,
1795                0x3b5f0, 0x3b638,
1796                0x3b640, 0x3b640,
1797                0x3b648, 0x3b650,
1798                0x3b65c, 0x3b664,
1799                0x3b670, 0x3b6b8,
1800                0x3b6c0, 0x3b6e4,
1801                0x3b6f8, 0x3b738,
1802                0x3b740, 0x3b740,
1803                0x3b748, 0x3b750,
1804                0x3b75c, 0x3b764,
1805                0x3b770, 0x3b7b8,
1806                0x3b7c0, 0x3b7e4,
1807                0x3b7f8, 0x3b7fc,
1808                0x3b814, 0x3b814,
1809                0x3b82c, 0x3b82c,
1810                0x3b880, 0x3b88c,
1811                0x3b8e8, 0x3b8ec,
1812                0x3b900, 0x3b928,
1813                0x3b930, 0x3b948,
1814                0x3b960, 0x3b968,
1815                0x3b970, 0x3b99c,
1816                0x3b9f0, 0x3ba38,
1817                0x3ba40, 0x3ba40,
1818                0x3ba48, 0x3ba50,
1819                0x3ba5c, 0x3ba64,
1820                0x3ba70, 0x3bab8,
1821                0x3bac0, 0x3bae4,
1822                0x3baf8, 0x3bb10,
1823                0x3bb28, 0x3bb28,
1824                0x3bb3c, 0x3bb50,
1825                0x3bbf0, 0x3bc10,
1826                0x3bc28, 0x3bc28,
1827                0x3bc3c, 0x3bc50,
1828                0x3bcf0, 0x3bcfc,
1829                0x3c000, 0x3c030,
1830                0x3c100, 0x3c144,
1831                0x3c190, 0x3c1a0,
1832                0x3c1a8, 0x3c1b8,
1833                0x3c1c4, 0x3c1c8,
1834                0x3c1d0, 0x3c1d0,
1835                0x3c200, 0x3c318,
1836                0x3c400, 0x3c4b4,
1837                0x3c4c0, 0x3c52c,
1838                0x3c540, 0x3c61c,
1839                0x3c800, 0x3c828,
1840                0x3c834, 0x3c834,
1841                0x3c8c0, 0x3c908,
1842                0x3c910, 0x3c9ac,
1843                0x3ca00, 0x3ca14,
1844                0x3ca1c, 0x3ca2c,
1845                0x3ca44, 0x3ca50,
1846                0x3ca74, 0x3ca74,
1847                0x3ca7c, 0x3cafc,
1848                0x3cb08, 0x3cc24,
1849                0x3cd00, 0x3cd00,
1850                0x3cd08, 0x3cd14,
1851                0x3cd1c, 0x3cd20,
1852                0x3cd3c, 0x3cd3c,
1853                0x3cd48, 0x3cd50,
1854                0x3d200, 0x3d20c,
1855                0x3d220, 0x3d220,
1856                0x3d240, 0x3d240,
1857                0x3d600, 0x3d60c,
1858                0x3da00, 0x3da1c,
1859                0x3de00, 0x3de20,
1860                0x3de38, 0x3de3c,
1861                0x3de80, 0x3de80,
1862                0x3de88, 0x3dea8,
1863                0x3deb0, 0x3deb4,
1864                0x3dec8, 0x3ded4,
1865                0x3dfb8, 0x3e004,
1866                0x3e200, 0x3e200,
1867                0x3e208, 0x3e240,
1868                0x3e248, 0x3e280,
1869                0x3e288, 0x3e2c0,
1870                0x3e2c8, 0x3e2fc,
1871                0x3e600, 0x3e630,
1872                0x3ea00, 0x3eabc,
1873                0x3eb00, 0x3eb10,
1874                0x3eb20, 0x3eb30,
1875                0x3eb40, 0x3eb50,
1876                0x3eb60, 0x3eb70,
1877                0x3f000, 0x3f028,
1878                0x3f030, 0x3f048,
1879                0x3f060, 0x3f068,
1880                0x3f070, 0x3f09c,
1881                0x3f0f0, 0x3f128,
1882                0x3f130, 0x3f148,
1883                0x3f160, 0x3f168,
1884                0x3f170, 0x3f19c,
1885                0x3f1f0, 0x3f238,
1886                0x3f240, 0x3f240,
1887                0x3f248, 0x3f250,
1888                0x3f25c, 0x3f264,
1889                0x3f270, 0x3f2b8,
1890                0x3f2c0, 0x3f2e4,
1891                0x3f2f8, 0x3f338,
1892                0x3f340, 0x3f340,
1893                0x3f348, 0x3f350,
1894                0x3f35c, 0x3f364,
1895                0x3f370, 0x3f3b8,
1896                0x3f3c0, 0x3f3e4,
1897                0x3f3f8, 0x3f428,
1898                0x3f430, 0x3f448,
1899                0x3f460, 0x3f468,
1900                0x3f470, 0x3f49c,
1901                0x3f4f0, 0x3f528,
1902                0x3f530, 0x3f548,
1903                0x3f560, 0x3f568,
1904                0x3f570, 0x3f59c,
1905                0x3f5f0, 0x3f638,
1906                0x3f640, 0x3f640,
1907                0x3f648, 0x3f650,
1908                0x3f65c, 0x3f664,
1909                0x3f670, 0x3f6b8,
1910                0x3f6c0, 0x3f6e4,
1911                0x3f6f8, 0x3f738,
1912                0x3f740, 0x3f740,
1913                0x3f748, 0x3f750,
1914                0x3f75c, 0x3f764,
1915                0x3f770, 0x3f7b8,
1916                0x3f7c0, 0x3f7e4,
1917                0x3f7f8, 0x3f7fc,
1918                0x3f814, 0x3f814,
1919                0x3f82c, 0x3f82c,
1920                0x3f880, 0x3f88c,
1921                0x3f8e8, 0x3f8ec,
1922                0x3f900, 0x3f928,
1923                0x3f930, 0x3f948,
1924                0x3f960, 0x3f968,
1925                0x3f970, 0x3f99c,
1926                0x3f9f0, 0x3fa38,
1927                0x3fa40, 0x3fa40,
1928                0x3fa48, 0x3fa50,
1929                0x3fa5c, 0x3fa64,
1930                0x3fa70, 0x3fab8,
1931                0x3fac0, 0x3fae4,
1932                0x3faf8, 0x3fb10,
1933                0x3fb28, 0x3fb28,
1934                0x3fb3c, 0x3fb50,
1935                0x3fbf0, 0x3fc10,
1936                0x3fc28, 0x3fc28,
1937                0x3fc3c, 0x3fc50,
1938                0x3fcf0, 0x3fcfc,
1939                0x40000, 0x4000c,
1940                0x40040, 0x40050,
1941                0x40060, 0x40068,
1942                0x4007c, 0x4008c,
1943                0x40094, 0x400b0,
1944                0x400c0, 0x40144,
1945                0x40180, 0x4018c,
1946                0x40200, 0x40254,
1947                0x40260, 0x40264,
1948                0x40270, 0x40288,
1949                0x40290, 0x40298,
1950                0x402ac, 0x402c8,
1951                0x402d0, 0x402e0,
1952                0x402f0, 0x402f0,
1953                0x40300, 0x4033c,
1954                0x403f8, 0x403fc,
1955                0x41304, 0x413c4,
1956                0x41400, 0x4140c,
1957                0x41414, 0x4141c,
1958                0x41480, 0x414d0,
1959                0x44000, 0x44054,
1960                0x4405c, 0x44078,
1961                0x440c0, 0x44174,
1962                0x44180, 0x441ac,
1963                0x441b4, 0x441b8,
1964                0x441c0, 0x44254,
1965                0x4425c, 0x44278,
1966                0x442c0, 0x44374,
1967                0x44380, 0x443ac,
1968                0x443b4, 0x443b8,
1969                0x443c0, 0x44454,
1970                0x4445c, 0x44478,
1971                0x444c0, 0x44574,
1972                0x44580, 0x445ac,
1973                0x445b4, 0x445b8,
1974                0x445c0, 0x44654,
1975                0x4465c, 0x44678,
1976                0x446c0, 0x44774,
1977                0x44780, 0x447ac,
1978                0x447b4, 0x447b8,
1979                0x447c0, 0x44854,
1980                0x4485c, 0x44878,
1981                0x448c0, 0x44974,
1982                0x44980, 0x449ac,
1983                0x449b4, 0x449b8,
1984                0x449c0, 0x449fc,
1985                0x45000, 0x45004,
1986                0x45010, 0x45030,
1987                0x45040, 0x45060,
1988                0x45068, 0x45068,
1989                0x45080, 0x45084,
1990                0x450a0, 0x450b0,
1991                0x45200, 0x45204,
1992                0x45210, 0x45230,
1993                0x45240, 0x45260,
1994                0x45268, 0x45268,
1995                0x45280, 0x45284,
1996                0x452a0, 0x452b0,
1997                0x460c0, 0x460e4,
1998                0x47000, 0x4703c,
1999                0x47044, 0x4708c,
2000                0x47200, 0x47250,
2001                0x47400, 0x47408,
2002                0x47414, 0x47420,
2003                0x47600, 0x47618,
2004                0x47800, 0x47814,
2005                0x48000, 0x4800c,
2006                0x48040, 0x48050,
2007                0x48060, 0x48068,
2008                0x4807c, 0x4808c,
2009                0x48094, 0x480b0,
2010                0x480c0, 0x48144,
2011                0x48180, 0x4818c,
2012                0x48200, 0x48254,
2013                0x48260, 0x48264,
2014                0x48270, 0x48288,
2015                0x48290, 0x48298,
2016                0x482ac, 0x482c8,
2017                0x482d0, 0x482e0,
2018                0x482f0, 0x482f0,
2019                0x48300, 0x4833c,
2020                0x483f8, 0x483fc,
2021                0x49304, 0x493c4,
2022                0x49400, 0x4940c,
2023                0x49414, 0x4941c,
2024                0x49480, 0x494d0,
2025                0x4c000, 0x4c054,
2026                0x4c05c, 0x4c078,
2027                0x4c0c0, 0x4c174,
2028                0x4c180, 0x4c1ac,
2029                0x4c1b4, 0x4c1b8,
2030                0x4c1c0, 0x4c254,
2031                0x4c25c, 0x4c278,
2032                0x4c2c0, 0x4c374,
2033                0x4c380, 0x4c3ac,
2034                0x4c3b4, 0x4c3b8,
2035                0x4c3c0, 0x4c454,
2036                0x4c45c, 0x4c478,
2037                0x4c4c0, 0x4c574,
2038                0x4c580, 0x4c5ac,
2039                0x4c5b4, 0x4c5b8,
2040                0x4c5c0, 0x4c654,
2041                0x4c65c, 0x4c678,
2042                0x4c6c0, 0x4c774,
2043                0x4c780, 0x4c7ac,
2044                0x4c7b4, 0x4c7b8,
2045                0x4c7c0, 0x4c854,
2046                0x4c85c, 0x4c878,
2047                0x4c8c0, 0x4c974,
2048                0x4c980, 0x4c9ac,
2049                0x4c9b4, 0x4c9b8,
2050                0x4c9c0, 0x4c9fc,
2051                0x4d000, 0x4d004,
2052                0x4d010, 0x4d030,
2053                0x4d040, 0x4d060,
2054                0x4d068, 0x4d068,
2055                0x4d080, 0x4d084,
2056                0x4d0a0, 0x4d0b0,
2057                0x4d200, 0x4d204,
2058                0x4d210, 0x4d230,
2059                0x4d240, 0x4d260,
2060                0x4d268, 0x4d268,
2061                0x4d280, 0x4d284,
2062                0x4d2a0, 0x4d2b0,
2063                0x4e0c0, 0x4e0e4,
2064                0x4f000, 0x4f03c,
2065                0x4f044, 0x4f08c,
2066                0x4f200, 0x4f250,
2067                0x4f400, 0x4f408,
2068                0x4f414, 0x4f420,
2069                0x4f600, 0x4f618,
2070                0x4f800, 0x4f814,
2071                0x50000, 0x50084,
2072                0x50090, 0x500cc,
2073                0x50400, 0x50400,
2074                0x50800, 0x50884,
2075                0x50890, 0x508cc,
2076                0x50c00, 0x50c00,
2077                0x51000, 0x5101c,
2078                0x51300, 0x51308,
2079        };
2080
2081        static const unsigned int t6_reg_ranges[] = {
2082                0x1008, 0x101c,
2083                0x1024, 0x10a8,
2084                0x10b4, 0x10f8,
2085                0x1100, 0x1114,
2086                0x111c, 0x112c,
2087                0x1138, 0x113c,
2088                0x1144, 0x114c,
2089                0x1180, 0x1184,
2090                0x1190, 0x1194,
2091                0x11a0, 0x11a4,
2092                0x11b0, 0x11b4,
2093                0x11fc, 0x123c,
2094                0x1254, 0x1274,
2095                0x1280, 0x133c,
2096                0x1800, 0x18fc,
2097                0x3000, 0x302c,
2098                0x3060, 0x30b0,
2099                0x30b8, 0x30d8,
2100                0x30e0, 0x30fc,
2101                0x3140, 0x357c,
2102                0x35a8, 0x35cc,
2103                0x35ec, 0x35ec,
2104                0x3600, 0x5624,
2105                0x56cc, 0x56ec,
2106                0x56f4, 0x5720,
2107                0x5728, 0x575c,
2108                0x580c, 0x5814,
2109                0x5890, 0x589c,
2110                0x58a4, 0x58ac,
2111                0x58b8, 0x58bc,
2112                0x5940, 0x595c,
2113                0x5980, 0x598c,
2114                0x59b0, 0x59c8,
2115                0x59d0, 0x59dc,
2116                0x59fc, 0x5a18,
2117                0x5a60, 0x5a6c,
2118                0x5a80, 0x5a8c,
2119                0x5a94, 0x5a9c,
2120                0x5b94, 0x5bfc,
2121                0x5c10, 0x5e48,
2122                0x5e50, 0x5e94,
2123                0x5ea0, 0x5eb0,
2124                0x5ec0, 0x5ec0,
2125                0x5ec8, 0x5ed0,
2126                0x5ee0, 0x5ee0,
2127                0x5ef0, 0x5ef0,
2128                0x5f00, 0x5f00,
2129                0x6000, 0x6020,
2130                0x6028, 0x6040,
2131                0x6058, 0x609c,
2132                0x60a8, 0x619c,
2133                0x7700, 0x7798,
2134                0x77c0, 0x7880,
2135                0x78cc, 0x78fc,
2136                0x7b00, 0x7b58,
2137                0x7b60, 0x7b84,
2138                0x7b8c, 0x7c54,
2139                0x7d00, 0x7d38,
2140                0x7d40, 0x7d84,
2141                0x7d8c, 0x7ddc,
2142                0x7de4, 0x7e04,
2143                0x7e10, 0x7e1c,
2144                0x7e24, 0x7e38,
2145                0x7e40, 0x7e44,
2146                0x7e4c, 0x7e78,
2147                0x7e80, 0x7edc,
2148                0x7ee8, 0x7efc,
2149                0x8dc0, 0x8de4,
2150                0x8df8, 0x8e04,
2151                0x8e10, 0x8e84,
2152                0x8ea0, 0x8f88,
2153                0x8fb8, 0x9058,
2154                0x9060, 0x9060,
2155                0x9068, 0x90f8,
2156                0x9100, 0x9124,
2157                0x9400, 0x9470,
2158                0x9600, 0x9600,
2159                0x9608, 0x9638,
2160                0x9640, 0x9704,
2161                0x9710, 0x971c,
2162                0x9800, 0x9808,
2163                0x9810, 0x9864,
2164                0x9c00, 0x9c6c,
2165                0x9c80, 0x9cec,
2166                0x9d00, 0x9d6c,
2167                0x9d80, 0x9dec,
2168                0x9e00, 0x9e6c,
2169                0x9e80, 0x9eec,
2170                0x9f00, 0x9f6c,
2171                0x9f80, 0xa020,
2172                0xd000, 0xd03c,
2173                0xd100, 0xd118,
2174                0xd200, 0xd214,
2175                0xd220, 0xd234,
2176                0xd240, 0xd254,
2177                0xd260, 0xd274,
2178                0xd280, 0xd294,
2179                0xd2a0, 0xd2b4,
2180                0xd2c0, 0xd2d4,
2181                0xd2e0, 0xd2f4,
2182                0xd300, 0xd31c,
2183                0xdfc0, 0xdfe0,
2184                0xe000, 0xf008,
2185                0xf010, 0xf018,
2186                0xf020, 0xf028,
2187                0x11000, 0x11014,
2188                0x11048, 0x1106c,
2189                0x11074, 0x11088,
2190                0x11098, 0x11120,
2191                0x1112c, 0x1117c,
2192                0x11190, 0x112e0,
2193                0x11300, 0x1130c,
2194                0x12000, 0x1206c,
2195                0x19040, 0x1906c,
2196                0x19078, 0x19080,
2197                0x1908c, 0x190e8,
2198                0x190f0, 0x190f8,
2199                0x19100, 0x19110,
2200                0x19120, 0x19124,
2201                0x19150, 0x19194,
2202                0x1919c, 0x191b0,
2203                0x191d0, 0x191e8,
2204                0x19238, 0x19290,
2205                0x192a4, 0x192b0,
2206                0x192bc, 0x192bc,
2207                0x19348, 0x1934c,
2208                0x193f8, 0x19418,
2209                0x19420, 0x19428,
2210                0x19430, 0x19444,
2211                0x1944c, 0x1946c,
2212                0x19474, 0x19474,
2213                0x19490, 0x194cc,
2214                0x194f0, 0x194f8,
2215                0x19c00, 0x19c48,
2216                0x19c50, 0x19c80,
2217                0x19c94, 0x19c98,
2218                0x19ca0, 0x19cbc,
2219                0x19ce4, 0x19ce4,
2220                0x19cf0, 0x19cf8,
2221                0x19d00, 0x19d28,
2222                0x19d50, 0x19d78,
2223                0x19d94, 0x19d98,
2224                0x19da0, 0x19dc8,
2225                0x19df0, 0x19e10,
2226                0x19e50, 0x19e6c,
2227                0x19ea0, 0x19ebc,
2228                0x19ec4, 0x19ef4,
2229                0x19f04, 0x19f2c,
2230                0x19f34, 0x19f34,
2231                0x19f40, 0x19f50,
2232                0x19f90, 0x19fac,
2233                0x19fc4, 0x19fc8,
2234                0x19fd0, 0x19fe4,
2235                0x1a000, 0x1a004,
2236                0x1a010, 0x1a06c,
2237                0x1a0b0, 0x1a0e4,
2238                0x1a0ec, 0x1a0f8,
2239                0x1a100, 0x1a108,
2240                0x1a114, 0x1a130,
2241                0x1a138, 0x1a1c4,
2242                0x1a1fc, 0x1a1fc,
2243                0x1e008, 0x1e00c,
2244                0x1e040, 0x1e044,
2245                0x1e04c, 0x1e04c,
2246                0x1e284, 0x1e290,
2247                0x1e2c0, 0x1e2c0,
2248                0x1e2e0, 0x1e2e0,
2249                0x1e300, 0x1e384,
2250                0x1e3c0, 0x1e3c8,
2251                0x1e408, 0x1e40c,
2252                0x1e440, 0x1e444,
2253                0x1e44c, 0x1e44c,
2254                0x1e684, 0x1e690,
2255                0x1e6c0, 0x1e6c0,
2256                0x1e6e0, 0x1e6e0,
2257                0x1e700, 0x1e784,
2258                0x1e7c0, 0x1e7c8,
2259                0x1e808, 0x1e80c,
2260                0x1e840, 0x1e844,
2261                0x1e84c, 0x1e84c,
2262                0x1ea84, 0x1ea90,
2263                0x1eac0, 0x1eac0,
2264                0x1eae0, 0x1eae0,
2265                0x1eb00, 0x1eb84,
2266                0x1ebc0, 0x1ebc8,
2267                0x1ec08, 0x1ec0c,
2268                0x1ec40, 0x1ec44,
2269                0x1ec4c, 0x1ec4c,
2270                0x1ee84, 0x1ee90,
2271                0x1eec0, 0x1eec0,
2272                0x1eee0, 0x1eee0,
2273                0x1ef00, 0x1ef84,
2274                0x1efc0, 0x1efc8,
2275                0x1f008, 0x1f00c,
2276                0x1f040, 0x1f044,
2277                0x1f04c, 0x1f04c,
2278                0x1f284, 0x1f290,
2279                0x1f2c0, 0x1f2c0,
2280                0x1f2e0, 0x1f2e0,
2281                0x1f300, 0x1f384,
2282                0x1f3c0, 0x1f3c8,
2283                0x1f408, 0x1f40c,
2284                0x1f440, 0x1f444,
2285                0x1f44c, 0x1f44c,
2286                0x1f684, 0x1f690,
2287                0x1f6c0, 0x1f6c0,
2288                0x1f6e0, 0x1f6e0,
2289                0x1f700, 0x1f784,
2290                0x1f7c0, 0x1f7c8,
2291                0x1f808, 0x1f80c,
2292                0x1f840, 0x1f844,
2293                0x1f84c, 0x1f84c,
2294                0x1fa84, 0x1fa90,
2295                0x1fac0, 0x1fac0,
2296                0x1fae0, 0x1fae0,
2297                0x1fb00, 0x1fb84,
2298                0x1fbc0, 0x1fbc8,
2299                0x1fc08, 0x1fc0c,
2300                0x1fc40, 0x1fc44,
2301                0x1fc4c, 0x1fc4c,
2302                0x1fe84, 0x1fe90,
2303                0x1fec0, 0x1fec0,
2304                0x1fee0, 0x1fee0,
2305                0x1ff00, 0x1ff84,
2306                0x1ffc0, 0x1ffc8,
2307                0x30000, 0x30030,
2308                0x30100, 0x30168,
2309                0x30190, 0x301a0,
2310                0x301a8, 0x301b8,
2311                0x301c4, 0x301c8,
2312                0x301d0, 0x301d0,
2313                0x30200, 0x30320,
2314                0x30400, 0x304b4,
2315                0x304c0, 0x3052c,
2316                0x30540, 0x3061c,
2317                0x30800, 0x308a0,
2318                0x308c0, 0x30908,
2319                0x30910, 0x309b8,
2320                0x30a00, 0x30a04,
2321                0x30a0c, 0x30a14,
2322                0x30a1c, 0x30a2c,
2323                0x30a44, 0x30a50,
2324                0x30a74, 0x30a74,
2325                0x30a7c, 0x30afc,
2326                0x30b08, 0x30c24,
2327                0x30d00, 0x30d14,
2328                0x30d1c, 0x30d3c,
2329                0x30d44, 0x30d4c,
2330                0x30d54, 0x30d74,
2331                0x30d7c, 0x30d7c,
2332                0x30de0, 0x30de0,
2333                0x30e00, 0x30ed4,
2334                0x30f00, 0x30fa4,
2335                0x30fc0, 0x30fc4,
2336                0x31000, 0x31004,
2337                0x31080, 0x310fc,
2338                0x31208, 0x31220,
2339                0x3123c, 0x31254,
2340                0x31300, 0x31300,
2341                0x31308, 0x3131c,
2342                0x31338, 0x3133c,
2343                0x31380, 0x31380,
2344                0x31388, 0x313a8,
2345                0x313b4, 0x313b4,
2346                0x31400, 0x31420,
2347                0x31438, 0x3143c,
2348                0x31480, 0x31480,
2349                0x314a8, 0x314a8,
2350                0x314b0, 0x314b4,
2351                0x314c8, 0x314d4,
2352                0x31a40, 0x31a4c,
2353                0x31af0, 0x31b20,
2354                0x31b38, 0x31b3c,
2355                0x31b80, 0x31b80,
2356                0x31ba8, 0x31ba8,
2357                0x31bb0, 0x31bb4,
2358                0x31bc8, 0x31bd4,
2359                0x32140, 0x3218c,
2360                0x321f0, 0x321f4,
2361                0x32200, 0x32200,
2362                0x32218, 0x32218,
2363                0x32400, 0x32400,
2364                0x32408, 0x3241c,
2365                0x32618, 0x32620,
2366                0x32664, 0x32664,
2367                0x326a8, 0x326a8,
2368                0x326ec, 0x326ec,
2369                0x32a00, 0x32abc,
2370                0x32b00, 0x32b18,
2371                0x32b20, 0x32b38,
2372                0x32b40, 0x32b58,
2373                0x32b60, 0x32b78,
2374                0x32c00, 0x32c00,
2375                0x32c08, 0x32c3c,
2376                0x33000, 0x3302c,
2377                0x33034, 0x33050,
2378                0x33058, 0x33058,
2379                0x33060, 0x3308c,
2380                0x3309c, 0x330ac,
2381                0x330c0, 0x330c0,
2382                0x330c8, 0x330d0,
2383                0x330d8, 0x330e0,
2384                0x330ec, 0x3312c,
2385                0x33134, 0x33150,
2386                0x33158, 0x33158,
2387                0x33160, 0x3318c,
2388                0x3319c, 0x331ac,
2389                0x331c0, 0x331c0,
2390                0x331c8, 0x331d0,
2391                0x331d8, 0x331e0,
2392                0x331ec, 0x33290,
2393                0x33298, 0x332c4,
2394                0x332e4, 0x33390,
2395                0x33398, 0x333c4,
2396                0x333e4, 0x3342c,
2397                0x33434, 0x33450,
2398                0x33458, 0x33458,
2399                0x33460, 0x3348c,
2400                0x3349c, 0x334ac,
2401                0x334c0, 0x334c0,
2402                0x334c8, 0x334d0,
2403                0x334d8, 0x334e0,
2404                0x334ec, 0x3352c,
2405                0x33534, 0x33550,
2406                0x33558, 0x33558,
2407                0x33560, 0x3358c,
2408                0x3359c, 0x335ac,
2409                0x335c0, 0x335c0,
2410                0x335c8, 0x335d0,
2411                0x335d8, 0x335e0,
2412                0x335ec, 0x33690,
2413                0x33698, 0x336c4,
2414                0x336e4, 0x33790,
2415                0x33798, 0x337c4,
2416                0x337e4, 0x337fc,
2417                0x33814, 0x33814,
2418                0x33854, 0x33868,
2419                0x33880, 0x3388c,
2420                0x338c0, 0x338d0,
2421                0x338e8, 0x338ec,
2422                0x33900, 0x3392c,
2423                0x33934, 0x33950,
2424                0x33958, 0x33958,
2425                0x33960, 0x3398c,
2426                0x3399c, 0x339ac,
2427                0x339c0, 0x339c0,
2428                0x339c8, 0x339d0,
2429                0x339d8, 0x339e0,
2430                0x339ec, 0x33a90,
2431                0x33a98, 0x33ac4,
2432                0x33ae4, 0x33b10,
2433                0x33b24, 0x33b28,
2434                0x33b38, 0x33b50,
2435                0x33bf0, 0x33c10,
2436                0x33c24, 0x33c28,
2437                0x33c38, 0x33c50,
2438                0x33cf0, 0x33cfc,
2439                0x34000, 0x34030,
2440                0x34100, 0x34168,
2441                0x34190, 0x341a0,
2442                0x341a8, 0x341b8,
2443                0x341c4, 0x341c8,
2444                0x341d0, 0x341d0,
2445                0x34200, 0x34320,
2446                0x34400, 0x344b4,
2447                0x344c0, 0x3452c,
2448                0x34540, 0x3461c,
2449                0x34800, 0x348a0,
2450                0x348c0, 0x34908,
2451                0x34910, 0x349b8,
2452                0x34a00, 0x34a04,
2453                0x34a0c, 0x34a14,
2454                0x34a1c, 0x34a2c,
2455                0x34a44, 0x34a50,
2456                0x34a74, 0x34a74,
2457                0x34a7c, 0x34afc,
2458                0x34b08, 0x34c24,
2459                0x34d00, 0x34d14,
2460                0x34d1c, 0x34d3c,
2461                0x34d44, 0x34d4c,
2462                0x34d54, 0x34d74,
2463                0x34d7c, 0x34d7c,
2464                0x34de0, 0x34de0,
2465                0x34e00, 0x34ed4,
2466                0x34f00, 0x34fa4,
2467                0x34fc0, 0x34fc4,
2468                0x35000, 0x35004,
2469                0x35080, 0x350fc,
2470                0x35208, 0x35220,
2471                0x3523c, 0x35254,
2472                0x35300, 0x35300,
2473                0x35308, 0x3531c,
2474                0x35338, 0x3533c,
2475                0x35380, 0x35380,
2476                0x35388, 0x353a8,
2477                0x353b4, 0x353b4,
2478                0x35400, 0x35420,
2479                0x35438, 0x3543c,
2480                0x35480, 0x35480,
2481                0x354a8, 0x354a8,
2482                0x354b0, 0x354b4,
2483                0x354c8, 0x354d4,
2484                0x35a40, 0x35a4c,
2485                0x35af0, 0x35b20,
2486                0x35b38, 0x35b3c,
2487                0x35b80, 0x35b80,
2488                0x35ba8, 0x35ba8,
2489                0x35bb0, 0x35bb4,
2490                0x35bc8, 0x35bd4,
2491                0x36140, 0x3618c,
2492                0x361f0, 0x361f4,
2493                0x36200, 0x36200,
2494                0x36218, 0x36218,
2495                0x36400, 0x36400,
2496                0x36408, 0x3641c,
2497                0x36618, 0x36620,
2498                0x36664, 0x36664,
2499                0x366a8, 0x366a8,
2500                0x366ec, 0x366ec,
2501                0x36a00, 0x36abc,
2502                0x36b00, 0x36b18,
2503                0x36b20, 0x36b38,
2504                0x36b40, 0x36b58,
2505                0x36b60, 0x36b78,
2506                0x36c00, 0x36c00,
2507                0x36c08, 0x36c3c,
2508                0x37000, 0x3702c,
2509                0x37034, 0x37050,
2510                0x37058, 0x37058,
2511                0x37060, 0x3708c,
2512                0x3709c, 0x370ac,
2513                0x370c0, 0x370c0,
2514                0x370c8, 0x370d0,
2515                0x370d8, 0x370e0,
2516                0x370ec, 0x3712c,
2517                0x37134, 0x37150,
2518                0x37158, 0x37158,
2519                0x37160, 0x3718c,
2520                0x3719c, 0x371ac,
2521                0x371c0, 0x371c0,
2522                0x371c8, 0x371d0,
2523                0x371d8, 0x371e0,
2524                0x371ec, 0x37290,
2525                0x37298, 0x372c4,
2526                0x372e4, 0x37390,
2527                0x37398, 0x373c4,
2528                0x373e4, 0x3742c,
2529                0x37434, 0x37450,
2530                0x37458, 0x37458,
2531                0x37460, 0x3748c,
2532                0x3749c, 0x374ac,
2533                0x374c0, 0x374c0,
2534                0x374c8, 0x374d0,
2535                0x374d8, 0x374e0,
2536                0x374ec, 0x3752c,
2537                0x37534, 0x37550,
2538                0x37558, 0x37558,
2539                0x37560, 0x3758c,
2540                0x3759c, 0x375ac,
2541                0x375c0, 0x375c0,
2542                0x375c8, 0x375d0,
2543                0x375d8, 0x375e0,
2544                0x375ec, 0x37690,
2545                0x37698, 0x376c4,
2546                0x376e4, 0x37790,
2547                0x37798, 0x377c4,
2548                0x377e4, 0x377fc,
2549                0x37814, 0x37814,
2550                0x37854, 0x37868,
2551                0x37880, 0x3788c,
2552                0x378c0, 0x378d0,
2553                0x378e8, 0x378ec,
2554                0x37900, 0x3792c,
2555                0x37934, 0x37950,
2556                0x37958, 0x37958,
2557                0x37960, 0x3798c,
2558                0x3799c, 0x379ac,
2559                0x379c0, 0x379c0,
2560                0x379c8, 0x379d0,
2561                0x379d8, 0x379e0,
2562                0x379ec, 0x37a90,
2563                0x37a98, 0x37ac4,
2564                0x37ae4, 0x37b10,
2565                0x37b24, 0x37b28,
2566                0x37b38, 0x37b50,
2567                0x37bf0, 0x37c10,
2568                0x37c24, 0x37c28,
2569                0x37c38, 0x37c50,
2570                0x37cf0, 0x37cfc,
2571                0x40040, 0x40040,
2572                0x40080, 0x40084,
2573                0x40100, 0x40100,
2574                0x40140, 0x401bc,
2575                0x40200, 0x40214,
2576                0x40228, 0x40228,
2577                0x40240, 0x40258,
2578                0x40280, 0x40280,
2579                0x40304, 0x40304,
2580                0x40330, 0x4033c,
2581                0x41304, 0x413c8,
2582                0x413d0, 0x413dc,
2583                0x413f0, 0x413f0,
2584                0x41400, 0x4140c,
2585                0x41414, 0x4141c,
2586                0x41480, 0x414d0,
2587                0x44000, 0x4407c,
2588                0x440c0, 0x441ac,
2589                0x441b4, 0x4427c,
2590                0x442c0, 0x443ac,
2591                0x443b4, 0x4447c,
2592                0x444c0, 0x445ac,
2593                0x445b4, 0x4467c,
2594                0x446c0, 0x447ac,
2595                0x447b4, 0x4487c,
2596                0x448c0, 0x449ac,
2597                0x449b4, 0x44a7c,
2598                0x44ac0, 0x44bac,
2599                0x44bb4, 0x44c7c,
2600                0x44cc0, 0x44dac,
2601                0x44db4, 0x44e7c,
2602                0x44ec0, 0x44fac,
2603                0x44fb4, 0x4507c,
2604                0x450c0, 0x451ac,
2605                0x451b4, 0x451fc,
2606                0x45800, 0x45804,
2607                0x45810, 0x45830,
2608                0x45840, 0x45860,
2609                0x45868, 0x45868,
2610                0x45880, 0x45884,
2611                0x458a0, 0x458b0,
2612                0x45a00, 0x45a04,
2613                0x45a10, 0x45a30,
2614                0x45a40, 0x45a60,
2615                0x45a68, 0x45a68,
2616                0x45a80, 0x45a84,
2617                0x45aa0, 0x45ab0,
2618                0x460c0, 0x460e4,
2619                0x47000, 0x4703c,
2620                0x47044, 0x4708c,
2621                0x47200, 0x47250,
2622                0x47400, 0x47408,
2623                0x47414, 0x47420,
2624                0x47600, 0x47618,
2625                0x47800, 0x47814,
2626                0x47820, 0x4782c,
2627                0x50000, 0x50084,
2628                0x50090, 0x500cc,
2629                0x50300, 0x50384,
2630                0x50400, 0x50400,
2631                0x50800, 0x50884,
2632                0x50890, 0x508cc,
2633                0x50b00, 0x50b84,
2634                0x50c00, 0x50c00,
2635                0x51000, 0x51020,
2636                0x51028, 0x510b0,
2637                0x51300, 0x51324,
2638        };
2639
2640        u32 *buf_end = (u32 *)((char *)buf + buf_size);
2641        const unsigned int *reg_ranges;
2642        int reg_ranges_size, range;
2643        unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
2644
2645        /* Select the right set of register ranges to dump depending on the
2646         * adapter chip type.
2647         */
2648        switch (chip_version) {
2649        case CHELSIO_T4:
2650                reg_ranges = t4_reg_ranges;
2651                reg_ranges_size = ARRAY_SIZE(t4_reg_ranges);
2652                break;
2653
2654        case CHELSIO_T5:
2655                reg_ranges = t5_reg_ranges;
2656                reg_ranges_size = ARRAY_SIZE(t5_reg_ranges);
2657                break;
2658
2659        case CHELSIO_T6:
2660                reg_ranges = t6_reg_ranges;
2661                reg_ranges_size = ARRAY_SIZE(t6_reg_ranges);
2662                break;
2663
2664        default:
2665                dev_err(adap->pdev_dev,
2666                        "Unsupported chip version %d\n", chip_version);
2667                return;
2668        }
2669
2670        /* Clear the register buffer and insert the appropriate register
2671         * values selected by the above register ranges.
2672         */
2673        memset(buf, 0, buf_size);
2674        for (range = 0; range < reg_ranges_size; range += 2) {
2675                unsigned int reg = reg_ranges[range];
2676                unsigned int last_reg = reg_ranges[range + 1];
2677                u32 *bufp = (u32 *)((char *)buf + reg);
2678
2679                /* Iterate across the register range filling in the register
2680                 * buffer but don't write past the end of the register buffer.
2681                 */
2682                while (reg <= last_reg && bufp < buf_end) {
2683                        *bufp++ = t4_read_reg(adap, reg);
2684                        reg += sizeof(u32);
2685                }
2686        }
2687}
2688
2689#define EEPROM_STAT_ADDR   0x7bfc
2690#define VPD_BASE           0x400
2691#define VPD_BASE_OLD       0
2692#define VPD_LEN            1024
2693
2694/**
2695 * t4_eeprom_ptov - translate a physical EEPROM address to virtual
2696 * @phys_addr: the physical EEPROM address
2697 * @fn: the PCI function number
2698 * @sz: size of function-specific area
2699 *
2700 * Translate a physical EEPROM address to virtual.  The first 1K is
2701 * accessed through virtual addresses starting at 31K, the rest is
2702 * accessed through virtual addresses starting at 0.
2703 *
2704 * The mapping is as follows:
2705 * [0..1K) -> [31K..32K)
2706 * [1K..1K+A) -> [31K-A..31K)
2707 * [1K+A..ES) -> [0..ES-A-1K)
2708 *
2709 * where A = @fn * @sz, and ES = EEPROM size.
2710 */
2711int t4_eeprom_ptov(unsigned int phys_addr, unsigned int fn, unsigned int sz)
2712{
2713        fn *= sz;
2714        if (phys_addr < 1024)
2715                return phys_addr + (31 << 10);
2716        if (phys_addr < 1024 + fn)
2717                return 31744 - fn + phys_addr - 1024;
2718        if (phys_addr < EEPROMSIZE)
2719                return phys_addr - 1024 - fn;
2720        return -EINVAL;
2721}
2722
2723/**
2724 *      t4_seeprom_wp - enable/disable EEPROM write protection
2725 *      @adapter: the adapter
2726 *      @enable: whether to enable or disable write protection
2727 *
2728 *      Enables or disables write protection on the serial EEPROM.
2729 */
2730int t4_seeprom_wp(struct adapter *adapter, bool enable)
2731{
2732        unsigned int v = enable ? 0xc : 0;
2733        int ret = pci_write_vpd(adapter->pdev, EEPROM_STAT_ADDR, 4, &v);
2734        return ret < 0 ? ret : 0;
2735}
2736
2737/**
2738 *      t4_get_raw_vpd_params - read VPD parameters from VPD EEPROM
2739 *      @adapter: adapter to read
2740 *      @p: where to store the parameters
2741 *
2742 *      Reads card parameters stored in VPD EEPROM.
2743 */
2744int t4_get_raw_vpd_params(struct adapter *adapter, struct vpd_params *p)
2745{
2746        int i, ret = 0, addr;
2747        int ec, sn, pn, na;
2748        u8 *vpd, csum, base_val = 0;
2749        unsigned int vpdr_len, kw_offset, id_len;
2750
2751        vpd = vmalloc(VPD_LEN);
2752        if (!vpd)
2753                return -ENOMEM;
2754
2755        /* Card information normally starts at VPD_BASE but early cards had
2756         * it at 0.
2757         */
2758        ret = pci_read_vpd(adapter->pdev, VPD_BASE, 1, &base_val);
2759        if (ret < 0)
2760                goto out;
2761
2762        addr = base_val == PCI_VPD_LRDT_ID_STRING ? VPD_BASE : VPD_BASE_OLD;
2763
2764        ret = pci_read_vpd(adapter->pdev, addr, VPD_LEN, vpd);
2765        if (ret < 0)
2766                goto out;
2767
2768        if (vpd[0] != PCI_VPD_LRDT_ID_STRING) {
2769                dev_err(adapter->pdev_dev, "missing VPD ID string\n");
2770                ret = -EINVAL;
2771                goto out;
2772        }
2773
2774        id_len = pci_vpd_lrdt_size(vpd);
2775        if (id_len > ID_LEN)
2776                id_len = ID_LEN;
2777
2778        i = pci_vpd_find_tag(vpd, VPD_LEN, PCI_VPD_LRDT_RO_DATA);
2779        if (i < 0) {
2780                dev_err(adapter->pdev_dev, "missing VPD-R section\n");
2781                ret = -EINVAL;
2782                goto out;
2783        }
2784
2785        vpdr_len = pci_vpd_lrdt_size(&vpd[i]);
2786        kw_offset = i + PCI_VPD_LRDT_TAG_SIZE;
2787        if (vpdr_len + kw_offset > VPD_LEN) {
2788                dev_err(adapter->pdev_dev, "bad VPD-R length %u\n", vpdr_len);
2789                ret = -EINVAL;
2790                goto out;
2791        }
2792
2793#define FIND_VPD_KW(var, name) do { \
2794        var = pci_vpd_find_info_keyword(vpd, kw_offset, vpdr_len, name); \
2795        if (var < 0) { \
2796                dev_err(adapter->pdev_dev, "missing VPD keyword " name "\n"); \
2797                ret = -EINVAL; \
2798                goto out; \
2799        } \
2800        var += PCI_VPD_INFO_FLD_HDR_SIZE; \
2801} while (0)
2802
2803        FIND_VPD_KW(i, "RV");
2804        for (csum = 0; i >= 0; i--)
2805                csum += vpd[i];
2806
2807        if (csum) {
2808                dev_err(adapter->pdev_dev,
2809                        "corrupted VPD EEPROM, actual csum %u\n", csum);
2810                ret = -EINVAL;
2811                goto out;
2812        }
2813
2814        FIND_VPD_KW(ec, "EC");
2815        FIND_VPD_KW(sn, "SN");
2816        FIND_VPD_KW(pn, "PN");
2817        FIND_VPD_KW(na, "NA");
2818#undef FIND_VPD_KW
2819
2820        memcpy(p->id, vpd + PCI_VPD_LRDT_TAG_SIZE, id_len);
2821        strim(p->id);
2822        memcpy(p->ec, vpd + ec, EC_LEN);
2823        strim(p->ec);
2824        i = pci_vpd_info_field_size(vpd + sn - PCI_VPD_INFO_FLD_HDR_SIZE);
2825        memcpy(p->sn, vpd + sn, min(i, SERNUM_LEN));
2826        strim(p->sn);
2827        i = pci_vpd_info_field_size(vpd + pn - PCI_VPD_INFO_FLD_HDR_SIZE);
2828        memcpy(p->pn, vpd + pn, min(i, PN_LEN));
2829        strim(p->pn);
2830        memcpy(p->na, vpd + na, min(i, MACADDR_LEN));
2831        strim((char *)p->na);
2832
2833out:
2834        vfree(vpd);
2835        return ret < 0 ? ret : 0;
2836}
2837
2838/**
2839 *      t4_get_vpd_params - read VPD parameters & retrieve Core Clock
2840 *      @adapter: adapter to read
2841 *      @p: where to store the parameters
2842 *
2843 *      Reads card parameters stored in VPD EEPROM and retrieves the Core
2844 *      Clock.  This can only be called after a connection to the firmware
2845 *      is established.
2846 */
2847int t4_get_vpd_params(struct adapter *adapter, struct vpd_params *p)
2848{
2849        u32 cclk_param, cclk_val;
2850        int ret;
2851
2852        /* Grab the raw VPD parameters.
2853         */
2854        ret = t4_get_raw_vpd_params(adapter, p);
2855        if (ret)
2856                return ret;
2857
2858        /* Ask firmware for the Core Clock since it knows how to translate the
2859         * Reference Clock ('V2') VPD field into a Core Clock value ...
2860         */
2861        cclk_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
2862                      FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_CCLK));
2863        ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
2864                              1, &cclk_param, &cclk_val);
2865
2866        if (ret)
2867                return ret;
2868        p->cclk = cclk_val;
2869
2870        return 0;
2871}
2872
2873/**
2874 *      t4_get_pfres - retrieve VF resource limits
2875 *      @adapter: the adapter
2876 *
2877 *      Retrieves configured resource limits and capabilities for a physical
2878 *      function.  The results are stored in @adapter->pfres.
2879 */
2880int t4_get_pfres(struct adapter *adapter)
2881{
2882        struct pf_resources *pfres = &adapter->params.pfres;
2883        struct fw_pfvf_cmd cmd, rpl;
2884        int v;
2885        u32 word;
2886
2887        /* Execute PFVF Read command to get VF resource limits; bail out early
2888         * with error on command failure.
2889         */
2890        memset(&cmd, 0, sizeof(cmd));
2891        cmd.op_to_vfn = cpu_to_be32(FW_CMD_OP_V(FW_PFVF_CMD) |
2892                                    FW_CMD_REQUEST_F |
2893                                    FW_CMD_READ_F |
2894                                    FW_PFVF_CMD_PFN_V(adapter->pf) |
2895                                    FW_PFVF_CMD_VFN_V(0));
2896        cmd.retval_len16 = cpu_to_be32(FW_LEN16(cmd));
2897        v = t4_wr_mbox(adapter, adapter->mbox, &cmd, sizeof(cmd), &rpl);
2898        if (v != FW_SUCCESS)
2899                return v;
2900
2901        /* Extract PF resource limits and return success.
2902         */
2903        word = be32_to_cpu(rpl.niqflint_niq);
2904        pfres->niqflint = FW_PFVF_CMD_NIQFLINT_G(word);
2905        pfres->niq = FW_PFVF_CMD_NIQ_G(word);
2906
2907        word = be32_to_cpu(rpl.type_to_neq);
2908        pfres->neq = FW_PFVF_CMD_NEQ_G(word);
2909        pfres->pmask = FW_PFVF_CMD_PMASK_G(word);
2910
2911        word = be32_to_cpu(rpl.tc_to_nexactf);
2912        pfres->tc = FW_PFVF_CMD_TC_G(word);
2913        pfres->nvi = FW_PFVF_CMD_NVI_G(word);
2914        pfres->nexactf = FW_PFVF_CMD_NEXACTF_G(word);
2915
2916        word = be32_to_cpu(rpl.r_caps_to_nethctrl);
2917        pfres->r_caps = FW_PFVF_CMD_R_CAPS_G(word);
2918        pfres->wx_caps = FW_PFVF_CMD_WX_CAPS_G(word);
2919        pfres->nethctrl = FW_PFVF_CMD_NETHCTRL_G(word);
2920
2921        return 0;
2922}
2923
2924/* serial flash and firmware constants */
2925enum {
2926        SF_ATTEMPTS = 10,             /* max retries for SF operations */
2927
2928        /* flash command opcodes */
2929        SF_PROG_PAGE    = 2,          /* program page */
2930        SF_WR_DISABLE   = 4,          /* disable writes */
2931        SF_RD_STATUS    = 5,          /* read status register */
2932        SF_WR_ENABLE    = 6,          /* enable writes */
2933        SF_RD_DATA_FAST = 0xb,        /* read flash */
2934        SF_RD_ID        = 0x9f,       /* read ID */
2935        SF_ERASE_SECTOR = 0xd8,       /* erase sector */
2936};
2937
2938/**
2939 *      sf1_read - read data from the serial flash
2940 *      @adapter: the adapter
2941 *      @byte_cnt: number of bytes to read
2942 *      @cont: whether another operation will be chained
2943 *      @lock: whether to lock SF for PL access only
2944 *      @valp: where to store the read data
2945 *
2946 *      Reads up to 4 bytes of data from the serial flash.  The location of
2947 *      the read needs to be specified prior to calling this by issuing the
2948 *      appropriate commands to the serial flash.
2949 */
2950static int sf1_read(struct adapter *adapter, unsigned int byte_cnt, int cont,
2951                    int lock, u32 *valp)
2952{
2953        int ret;
2954
2955        if (!byte_cnt || byte_cnt > 4)
2956                return -EINVAL;
2957        if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2958                return -EBUSY;
2959        t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2960                     SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1));
2961        ret = t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2962        if (!ret)
2963                *valp = t4_read_reg(adapter, SF_DATA_A);
2964        return ret;
2965}
2966
2967/**
2968 *      sf1_write - write data to the serial flash
2969 *      @adapter: the adapter
2970 *      @byte_cnt: number of bytes to write
2971 *      @cont: whether another operation will be chained
2972 *      @lock: whether to lock SF for PL access only
2973 *      @val: value to write
2974 *
2975 *      Writes up to 4 bytes of data to the serial flash.  The location of
2976 *      the write needs to be specified prior to calling this by issuing the
2977 *      appropriate commands to the serial flash.
2978 */
2979static int sf1_write(struct adapter *adapter, unsigned int byte_cnt, int cont,
2980                     int lock, u32 val)
2981{
2982        if (!byte_cnt || byte_cnt > 4)
2983                return -EINVAL;
2984        if (t4_read_reg(adapter, SF_OP_A) & SF_BUSY_F)
2985                return -EBUSY;
2986        t4_write_reg(adapter, SF_DATA_A, val);
2987        t4_write_reg(adapter, SF_OP_A, SF_LOCK_V(lock) |
2988                     SF_CONT_V(cont) | BYTECNT_V(byte_cnt - 1) | OP_V(1));
2989        return t4_wait_op_done(adapter, SF_OP_A, SF_BUSY_F, 0, SF_ATTEMPTS, 5);
2990}
2991
2992/**
2993 *      flash_wait_op - wait for a flash operation to complete
2994 *      @adapter: the adapter
2995 *      @attempts: max number of polls of the status register
2996 *      @delay: delay between polls in ms
2997 *
2998 *      Wait for a flash operation to complete by polling the status register.
2999 */
3000static int flash_wait_op(struct adapter *adapter, int attempts, int delay)
3001{
3002        int ret;
3003        u32 status;
3004
3005        while (1) {
3006                if ((ret = sf1_write(adapter, 1, 1, 1, SF_RD_STATUS)) != 0 ||
3007                    (ret = sf1_read(adapter, 1, 0, 1, &status)) != 0)
3008                        return ret;
3009                if (!(status & 1))
3010                        return 0;
3011                if (--attempts == 0)
3012                        return -EAGAIN;
3013                if (delay)
3014                        msleep(delay);
3015        }
3016}
3017
3018/**
3019 *      t4_read_flash - read words from serial flash
3020 *      @adapter: the adapter
3021 *      @addr: the start address for the read
3022 *      @nwords: how many 32-bit words to read
3023 *      @data: where to store the read data
3024 *      @byte_oriented: whether to store data as bytes or as words
3025 *
3026 *      Read the specified number of 32-bit words from the serial flash.
3027 *      If @byte_oriented is set the read data is stored as a byte array
3028 *      (i.e., big-endian), otherwise as 32-bit words in the platform's
3029 *      natural endianness.
3030 */
3031int t4_read_flash(struct adapter *adapter, unsigned int addr,
3032                  unsigned int nwords, u32 *data, int byte_oriented)
3033{
3034        int ret;
3035
3036        if (addr + nwords * sizeof(u32) > adapter->params.sf_size || (addr & 3))
3037                return -EINVAL;
3038
3039        addr = swab32(addr) | SF_RD_DATA_FAST;
3040
3041        if ((ret = sf1_write(adapter, 4, 1, 0, addr)) != 0 ||
3042            (ret = sf1_read(adapter, 1, 1, 0, data)) != 0)
3043                return ret;
3044
3045        for ( ; nwords; nwords--, data++) {
3046                ret = sf1_read(adapter, 4, nwords > 1, nwords == 1, data);
3047                if (nwords == 1)
3048                        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3049                if (ret)
3050                        return ret;
3051                if (byte_oriented)
3052                        *data = (__force __u32)(cpu_to_be32(*data));
3053        }
3054        return 0;
3055}
3056
3057/**
3058 *      t4_write_flash - write up to a page of data to the serial flash
3059 *      @adapter: the adapter
3060 *      @addr: the start address to write
3061 *      @n: length of data to write in bytes
3062 *      @data: the data to write
3063 *      @byte_oriented: whether to store data as bytes or as words
3064 *
3065 *      Writes up to a page of data (256 bytes) to the serial flash starting
3066 *      at the given address.  All the data must be written to the same page.
3067 *      If @byte_oriented is set the write data is stored as byte stream
3068 *      (i.e. matches what on disk), otherwise in big-endian.
3069 */
3070static int t4_write_flash(struct adapter *adapter, unsigned int addr,
3071                          unsigned int n, const u8 *data, bool byte_oriented)
3072{
3073        unsigned int i, c, left, val, offset = addr & 0xff;
3074        u32 buf[64];
3075        int ret;
3076
3077        if (addr >= adapter->params.sf_size || offset + n > SF_PAGE_SIZE)
3078                return -EINVAL;
3079
3080        val = swab32(addr) | SF_PROG_PAGE;
3081
3082        if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3083            (ret = sf1_write(adapter, 4, 1, 1, val)) != 0)
3084                goto unlock;
3085
3086        for (left = n; left; left -= c, data += c) {
3087                c = min(left, 4U);
3088                for (val = 0, i = 0; i < c; ++i) {
3089                        if (byte_oriented)
3090                                val = (val << 8) + data[i];
3091                        else
3092                                val = (val << 8) + data[c - i - 1];
3093                }
3094
3095                ret = sf1_write(adapter, c, c != left, 1, val);
3096                if (ret)
3097                        goto unlock;
3098        }
3099        ret = flash_wait_op(adapter, 8, 1);
3100        if (ret)
3101                goto unlock;
3102
3103        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3104
3105        /* Read the page to verify the write succeeded */
3106        ret = t4_read_flash(adapter, addr & ~0xff, ARRAY_SIZE(buf), buf,
3107                            byte_oriented);
3108        if (ret)
3109                return ret;
3110
3111        if (memcmp(data - n, (u8 *)buf + offset, n)) {
3112                dev_err(adapter->pdev_dev,
3113                        "failed to correctly write the flash page at %#x\n",
3114                        addr);
3115                return -EIO;
3116        }
3117        return 0;
3118
3119unlock:
3120        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3121        return ret;
3122}
3123
3124/**
3125 *      t4_get_fw_version - read the firmware version
3126 *      @adapter: the adapter
3127 *      @vers: where to place the version
3128 *
3129 *      Reads the FW version from flash.
3130 */
3131int t4_get_fw_version(struct adapter *adapter, u32 *vers)
3132{
3133        return t4_read_flash(adapter, FLASH_FW_START +
3134                             offsetof(struct fw_hdr, fw_ver), 1,
3135                             vers, 0);
3136}
3137
3138/**
3139 *      t4_get_bs_version - read the firmware bootstrap version
3140 *      @adapter: the adapter
3141 *      @vers: where to place the version
3142 *
3143 *      Reads the FW Bootstrap version from flash.
3144 */
3145int t4_get_bs_version(struct adapter *adapter, u32 *vers)
3146{
3147        return t4_read_flash(adapter, FLASH_FWBOOTSTRAP_START +
3148                             offsetof(struct fw_hdr, fw_ver), 1,
3149                             vers, 0);
3150}
3151
3152/**
3153 *      t4_get_tp_version - read the TP microcode version
3154 *      @adapter: the adapter
3155 *      @vers: where to place the version
3156 *
3157 *      Reads the TP microcode version from flash.
3158 */
3159int t4_get_tp_version(struct adapter *adapter, u32 *vers)
3160{
3161        return t4_read_flash(adapter, FLASH_FW_START +
3162                             offsetof(struct fw_hdr, tp_microcode_ver),
3163                             1, vers, 0);
3164}
3165
3166/**
3167 *      t4_get_exprom_version - return the Expansion ROM version (if any)
3168 *      @adap: the adapter
3169 *      @vers: where to place the version
3170 *
3171 *      Reads the Expansion ROM header from FLASH and returns the version
3172 *      number (if present) through the @vers return value pointer.  We return
3173 *      this in the Firmware Version Format since it's convenient.  Return
3174 *      0 on success, -ENOENT if no Expansion ROM is present.
3175 */
3176int t4_get_exprom_version(struct adapter *adap, u32 *vers)
3177{
3178        struct exprom_header {
3179                unsigned char hdr_arr[16];      /* must start with 0x55aa */
3180                unsigned char hdr_ver[4];       /* Expansion ROM version */
3181        } *hdr;
3182        u32 exprom_header_buf[DIV_ROUND_UP(sizeof(struct exprom_header),
3183                                           sizeof(u32))];
3184        int ret;
3185
3186        ret = t4_read_flash(adap, FLASH_EXP_ROM_START,
3187                            ARRAY_SIZE(exprom_header_buf), exprom_header_buf,
3188                            0);
3189        if (ret)
3190                return ret;
3191
3192        hdr = (struct exprom_header *)exprom_header_buf;
3193        if (hdr->hdr_arr[0] != 0x55 || hdr->hdr_arr[1] != 0xaa)
3194                return -ENOENT;
3195
3196        *vers = (FW_HDR_FW_VER_MAJOR_V(hdr->hdr_ver[0]) |
3197                 FW_HDR_FW_VER_MINOR_V(hdr->hdr_ver[1]) |
3198                 FW_HDR_FW_VER_MICRO_V(hdr->hdr_ver[2]) |
3199                 FW_HDR_FW_VER_BUILD_V(hdr->hdr_ver[3]));
3200        return 0;
3201}
3202
3203/**
3204 *      t4_get_vpd_version - return the VPD version
3205 *      @adapter: the adapter
3206 *      @vers: where to place the version
3207 *
3208 *      Reads the VPD via the Firmware interface (thus this can only be called
3209 *      once we're ready to issue Firmware commands).  The format of the
3210 *      VPD version is adapter specific.  Returns 0 on success, an error on
3211 *      failure.
3212 *
3213 *      Note that early versions of the Firmware didn't include the ability
3214 *      to retrieve the VPD version, so we zero-out the return-value parameter
3215 *      in that case to avoid leaving it with garbage in it.
3216 *
3217 *      Also note that the Firmware will return its cached copy of the VPD
3218 *      Revision ID, not the actual Revision ID as written in the Serial
3219 *      EEPROM.  This is only an issue if a new VPD has been written and the
3220 *      Firmware/Chip haven't yet gone through a RESET sequence.  So it's best
3221 *      to defer calling this routine till after a FW_RESET_CMD has been issued
3222 *      if the Host Driver will be performing a full adapter initialization.
3223 */
3224int t4_get_vpd_version(struct adapter *adapter, u32 *vers)
3225{
3226        u32 vpdrev_param;
3227        int ret;
3228
3229        vpdrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3230                        FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_VPDREV));
3231        ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3232                              1, &vpdrev_param, vers);
3233        if (ret)
3234                *vers = 0;
3235        return ret;
3236}
3237
3238/**
3239 *      t4_get_scfg_version - return the Serial Configuration version
3240 *      @adapter: the adapter
3241 *      @vers: where to place the version
3242 *
3243 *      Reads the Serial Configuration Version via the Firmware interface
3244 *      (thus this can only be called once we're ready to issue Firmware
3245 *      commands).  The format of the Serial Configuration version is
3246 *      adapter specific.  Returns 0 on success, an error on failure.
3247 *
3248 *      Note that early versions of the Firmware didn't include the ability
3249 *      to retrieve the Serial Configuration version, so we zero-out the
3250 *      return-value parameter in that case to avoid leaving it with
3251 *      garbage in it.
3252 *
3253 *      Also note that the Firmware will return its cached copy of the Serial
3254 *      Initialization Revision ID, not the actual Revision ID as written in
3255 *      the Serial EEPROM.  This is only an issue if a new VPD has been written
3256 *      and the Firmware/Chip haven't yet gone through a RESET sequence.  So
3257 *      it's best to defer calling this routine till after a FW_RESET_CMD has
3258 *      been issued if the Host Driver will be performing a full adapter
3259 *      initialization.
3260 */
3261int t4_get_scfg_version(struct adapter *adapter, u32 *vers)
3262{
3263        u32 scfgrev_param;
3264        int ret;
3265
3266        scfgrev_param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3267                         FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_SCFGREV));
3268        ret = t4_query_params(adapter, adapter->mbox, adapter->pf, 0,
3269                              1, &scfgrev_param, vers);
3270        if (ret)
3271                *vers = 0;
3272        return ret;
3273}
3274
3275/**
3276 *      t4_get_version_info - extract various chip/firmware version information
3277 *      @adapter: the adapter
3278 *
3279 *      Reads various chip/firmware version numbers and stores them into the
3280 *      adapter Adapter Parameters structure.  If any of the efforts fails
3281 *      the first failure will be returned, but all of the version numbers
3282 *      will be read.
3283 */
3284int t4_get_version_info(struct adapter *adapter)
3285{
3286        int ret = 0;
3287
3288        #define FIRST_RET(__getvinfo) \
3289        do { \
3290                int __ret = __getvinfo; \
3291                if (__ret && !ret) \
3292                        ret = __ret; \
3293        } while (0)
3294
3295        FIRST_RET(t4_get_fw_version(adapter, &adapter->params.fw_vers));
3296        FIRST_RET(t4_get_bs_version(adapter, &adapter->params.bs_vers));
3297        FIRST_RET(t4_get_tp_version(adapter, &adapter->params.tp_vers));
3298        FIRST_RET(t4_get_exprom_version(adapter, &adapter->params.er_vers));
3299        FIRST_RET(t4_get_scfg_version(adapter, &adapter->params.scfg_vers));
3300        FIRST_RET(t4_get_vpd_version(adapter, &adapter->params.vpd_vers));
3301
3302        #undef FIRST_RET
3303        return ret;
3304}
3305
3306/**
3307 *      t4_dump_version_info - dump all of the adapter configuration IDs
3308 *      @adapter: the adapter
3309 *
3310 *      Dumps all of the various bits of adapter configuration version/revision
3311 *      IDs information.  This is typically called at some point after
3312 *      t4_get_version_info() has been called.
3313 */
3314void t4_dump_version_info(struct adapter *adapter)
3315{
3316        /* Device information */
3317        dev_info(adapter->pdev_dev, "Chelsio %s rev %d\n",
3318                 adapter->params.vpd.id,
3319                 CHELSIO_CHIP_RELEASE(adapter->params.chip));
3320        dev_info(adapter->pdev_dev, "S/N: %s, P/N: %s\n",
3321                 adapter->params.vpd.sn, adapter->params.vpd.pn);
3322
3323        /* Firmware Version */
3324        if (!adapter->params.fw_vers)
3325                dev_warn(adapter->pdev_dev, "No firmware loaded\n");
3326        else
3327                dev_info(adapter->pdev_dev, "Firmware version: %u.%u.%u.%u\n",
3328                         FW_HDR_FW_VER_MAJOR_G(adapter->params.fw_vers),
3329                         FW_HDR_FW_VER_MINOR_G(adapter->params.fw_vers),
3330                         FW_HDR_FW_VER_MICRO_G(adapter->params.fw_vers),
3331                         FW_HDR_FW_VER_BUILD_G(adapter->params.fw_vers));
3332
3333        /* Bootstrap Firmware Version. (Some adapters don't have Bootstrap
3334         * Firmware, so dev_info() is more appropriate here.)
3335         */
3336        if (!adapter->params.bs_vers)
3337                dev_info(adapter->pdev_dev, "No bootstrap loaded\n");
3338        else
3339                dev_info(adapter->pdev_dev, "Bootstrap version: %u.%u.%u.%u\n",
3340                         FW_HDR_FW_VER_MAJOR_G(adapter->params.bs_vers),
3341                         FW_HDR_FW_VER_MINOR_G(adapter->params.bs_vers),
3342                         FW_HDR_FW_VER_MICRO_G(adapter->params.bs_vers),
3343                         FW_HDR_FW_VER_BUILD_G(adapter->params.bs_vers));
3344
3345        /* TP Microcode Version */
3346        if (!adapter->params.tp_vers)
3347                dev_warn(adapter->pdev_dev, "No TP Microcode loaded\n");
3348        else
3349                dev_info(adapter->pdev_dev,
3350                         "TP Microcode version: %u.%u.%u.%u\n",
3351                         FW_HDR_FW_VER_MAJOR_G(adapter->params.tp_vers),
3352                         FW_HDR_FW_VER_MINOR_G(adapter->params.tp_vers),
3353                         FW_HDR_FW_VER_MICRO_G(adapter->params.tp_vers),
3354                         FW_HDR_FW_VER_BUILD_G(adapter->params.tp_vers));
3355
3356        /* Expansion ROM version */
3357        if (!adapter->params.er_vers)
3358                dev_info(adapter->pdev_dev, "No Expansion ROM loaded\n");
3359        else
3360                dev_info(adapter->pdev_dev,
3361                         "Expansion ROM version: %u.%u.%u.%u\n",
3362                         FW_HDR_FW_VER_MAJOR_G(adapter->params.er_vers),
3363                         FW_HDR_FW_VER_MINOR_G(adapter->params.er_vers),
3364                         FW_HDR_FW_VER_MICRO_G(adapter->params.er_vers),
3365                         FW_HDR_FW_VER_BUILD_G(adapter->params.er_vers));
3366
3367        /* Serial Configuration version */
3368        dev_info(adapter->pdev_dev, "Serial Configuration version: %#x\n",
3369                 adapter->params.scfg_vers);
3370
3371        /* VPD Version */
3372        dev_info(adapter->pdev_dev, "VPD version: %#x\n",
3373                 adapter->params.vpd_vers);
3374}
3375
3376/**
3377 *      t4_check_fw_version - check if the FW is supported with this driver
3378 *      @adap: the adapter
3379 *
3380 *      Checks if an adapter's FW is compatible with the driver.  Returns 0
3381 *      if there's exact match, a negative error if the version could not be
3382 *      read or there's a major version mismatch
3383 */
3384int t4_check_fw_version(struct adapter *adap)
3385{
3386        int i, ret, major, minor, micro;
3387        int exp_major, exp_minor, exp_micro;
3388        unsigned int chip_version = CHELSIO_CHIP_VERSION(adap->params.chip);
3389
3390        ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3391        /* Try multiple times before returning error */
3392        for (i = 0; (ret == -EBUSY || ret == -EAGAIN) && i < 3; i++)
3393                ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3394
3395        if (ret)
3396                return ret;
3397
3398        major = FW_HDR_FW_VER_MAJOR_G(adap->params.fw_vers);
3399        minor = FW_HDR_FW_VER_MINOR_G(adap->params.fw_vers);
3400        micro = FW_HDR_FW_VER_MICRO_G(adap->params.fw_vers);
3401
3402        switch (chip_version) {
3403        case CHELSIO_T4:
3404                exp_major = T4FW_MIN_VERSION_MAJOR;
3405                exp_minor = T4FW_MIN_VERSION_MINOR;
3406                exp_micro = T4FW_MIN_VERSION_MICRO;
3407                break;
3408        case CHELSIO_T5:
3409                exp_major = T5FW_MIN_VERSION_MAJOR;
3410                exp_minor = T5FW_MIN_VERSION_MINOR;
3411                exp_micro = T5FW_MIN_VERSION_MICRO;
3412                break;
3413        case CHELSIO_T6:
3414                exp_major = T6FW_MIN_VERSION_MAJOR;
3415                exp_minor = T6FW_MIN_VERSION_MINOR;
3416                exp_micro = T6FW_MIN_VERSION_MICRO;
3417                break;
3418        default:
3419                dev_err(adap->pdev_dev, "Unsupported chip type, %x\n",
3420                        adap->chip);
3421                return -EINVAL;
3422        }
3423
3424        if (major < exp_major || (major == exp_major && minor < exp_minor) ||
3425            (major == exp_major && minor == exp_minor && micro < exp_micro)) {
3426                dev_err(adap->pdev_dev,
3427                        "Card has firmware version %u.%u.%u, minimum "
3428                        "supported firmware is %u.%u.%u.\n", major, minor,
3429                        micro, exp_major, exp_minor, exp_micro);
3430                return -EFAULT;
3431        }
3432        return 0;
3433}
3434
3435/* Is the given firmware API compatible with the one the driver was compiled
3436 * with?
3437 */
3438static int fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
3439{
3440
3441        /* short circuit if it's the exact same firmware version */
3442        if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
3443                return 1;
3444
3445#define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
3446        if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
3447            SAME_INTF(ri) && SAME_INTF(iscsi) && SAME_INTF(fcoe))
3448                return 1;
3449#undef SAME_INTF
3450
3451        return 0;
3452}
3453
3454/* The firmware in the filesystem is usable, but should it be installed?
3455 * This routine explains itself in detail if it indicates the filesystem
3456 * firmware should be installed.
3457 */
3458static int should_install_fs_fw(struct adapter *adap, int card_fw_usable,
3459                                int k, int c)
3460{
3461        const char *reason;
3462
3463        if (!card_fw_usable) {
3464                reason = "incompatible or unusable";
3465                goto install;
3466        }
3467
3468        if (k > c) {
3469                reason = "older than the version supported with this driver";
3470                goto install;
3471        }
3472
3473        return 0;
3474
3475install:
3476        dev_err(adap->pdev_dev, "firmware on card (%u.%u.%u.%u) is %s, "
3477                "installing firmware %u.%u.%u.%u on card.\n",
3478                FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3479                FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c), reason,
3480                FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3481                FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3482
3483        return 1;
3484}
3485
3486int t4_prep_fw(struct adapter *adap, struct fw_info *fw_info,
3487               const u8 *fw_data, unsigned int fw_size,
3488               struct fw_hdr *card_fw, enum dev_state state,
3489               int *reset)
3490{
3491        int ret, card_fw_usable, fs_fw_usable;
3492        const struct fw_hdr *fs_fw;
3493        const struct fw_hdr *drv_fw;
3494
3495        drv_fw = &fw_info->fw_hdr;
3496
3497        /* Read the header of the firmware on the card */
3498        ret = t4_read_flash(adap, FLASH_FW_START,
3499                            sizeof(*card_fw) / sizeof(uint32_t),
3500                            (uint32_t *)card_fw, 1);
3501        if (ret == 0) {
3502                card_fw_usable = fw_compatible(drv_fw, (const void *)card_fw);
3503        } else {
3504                dev_err(adap->pdev_dev,
3505                        "Unable to read card's firmware header: %d\n", ret);
3506                card_fw_usable = 0;
3507        }
3508
3509        if (fw_data != NULL) {
3510                fs_fw = (const void *)fw_data;
3511                fs_fw_usable = fw_compatible(drv_fw, fs_fw);
3512        } else {
3513                fs_fw = NULL;
3514                fs_fw_usable = 0;
3515        }
3516
3517        if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3518            (!fs_fw_usable || fs_fw->fw_ver == drv_fw->fw_ver)) {
3519                /* Common case: the firmware on the card is an exact match and
3520                 * the filesystem one is an exact match too, or the filesystem
3521                 * one is absent/incompatible.
3522                 */
3523        } else if (fs_fw_usable && state == DEV_STATE_UNINIT &&
3524                   should_install_fs_fw(adap, card_fw_usable,
3525                                        be32_to_cpu(fs_fw->fw_ver),
3526                                        be32_to_cpu(card_fw->fw_ver))) {
3527                ret = t4_fw_upgrade(adap, adap->mbox, fw_data,
3528                                    fw_size, 0);
3529                if (ret != 0) {
3530                        dev_err(adap->pdev_dev,
3531                                "failed to install firmware: %d\n", ret);
3532                        goto bye;
3533                }
3534
3535                /* Installed successfully, update the cached header too. */
3536                *card_fw = *fs_fw;
3537                card_fw_usable = 1;
3538                *reset = 0;     /* already reset as part of load_fw */
3539        }
3540
3541        if (!card_fw_usable) {
3542                uint32_t d, c, k;
3543
3544                d = be32_to_cpu(drv_fw->fw_ver);
3545                c = be32_to_cpu(card_fw->fw_ver);
3546                k = fs_fw ? be32_to_cpu(fs_fw->fw_ver) : 0;
3547
3548                dev_err(adap->pdev_dev, "Cannot find a usable firmware: "
3549                        "chip state %d, "
3550                        "driver compiled with %d.%d.%d.%d, "
3551                        "card has %d.%d.%d.%d, filesystem has %d.%d.%d.%d\n",
3552                        state,
3553                        FW_HDR_FW_VER_MAJOR_G(d), FW_HDR_FW_VER_MINOR_G(d),
3554                        FW_HDR_FW_VER_MICRO_G(d), FW_HDR_FW_VER_BUILD_G(d),
3555                        FW_HDR_FW_VER_MAJOR_G(c), FW_HDR_FW_VER_MINOR_G(c),
3556                        FW_HDR_FW_VER_MICRO_G(c), FW_HDR_FW_VER_BUILD_G(c),
3557                        FW_HDR_FW_VER_MAJOR_G(k), FW_HDR_FW_VER_MINOR_G(k),
3558                        FW_HDR_FW_VER_MICRO_G(k), FW_HDR_FW_VER_BUILD_G(k));
3559                ret = -EINVAL;
3560                goto bye;
3561        }
3562
3563        /* We're using whatever's on the card and it's known to be good. */
3564        adap->params.fw_vers = be32_to_cpu(card_fw->fw_ver);
3565        adap->params.tp_vers = be32_to_cpu(card_fw->tp_microcode_ver);
3566
3567bye:
3568        return ret;
3569}
3570
3571/**
3572 *      t4_flash_erase_sectors - erase a range of flash sectors
3573 *      @adapter: the adapter
3574 *      @start: the first sector to erase
3575 *      @end: the last sector to erase
3576 *
3577 *      Erases the sectors in the given inclusive range.
3578 */
3579static int t4_flash_erase_sectors(struct adapter *adapter, int start, int end)
3580{
3581        int ret = 0;
3582
3583        if (end >= adapter->params.sf_nsec)
3584                return -EINVAL;
3585
3586        while (start <= end) {
3587                if ((ret = sf1_write(adapter, 1, 0, 1, SF_WR_ENABLE)) != 0 ||
3588                    (ret = sf1_write(adapter, 4, 0, 1,
3589                                     SF_ERASE_SECTOR | (start << 8))) != 0 ||
3590                    (ret = flash_wait_op(adapter, 14, 500)) != 0) {
3591                        dev_err(adapter->pdev_dev,
3592                                "erase of flash sector %d failed, error %d\n",
3593                                start, ret);
3594                        break;
3595                }
3596                start++;
3597        }
3598        t4_write_reg(adapter, SF_OP_A, 0);    /* unlock SF */
3599        return ret;
3600}
3601
3602/**
3603 *      t4_flash_cfg_addr - return the address of the flash configuration file
3604 *      @adapter: the adapter
3605 *
3606 *      Return the address within the flash where the Firmware Configuration
3607 *      File is stored.
3608 */
3609unsigned int t4_flash_cfg_addr(struct adapter *adapter)
3610{
3611        if (adapter->params.sf_size == 0x100000)
3612                return FLASH_FPGA_CFG_START;
3613        else
3614                return FLASH_CFG_START;
3615}
3616
3617/* Return TRUE if the specified firmware matches the adapter.  I.e. T4
3618 * firmware for T4 adapters, T5 firmware for T5 adapters, etc.  We go ahead
3619 * and emit an error message for mismatched firmware to save our caller the
3620 * effort ...
3621 */
3622static bool t4_fw_matches_chip(const struct adapter *adap,
3623                               const struct fw_hdr *hdr)
3624{
3625        /* The expression below will return FALSE for any unsupported adapter
3626         * which will keep us "honest" in the future ...
3627         */
3628        if ((is_t4(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T4) ||
3629            (is_t5(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T5) ||
3630            (is_t6(adap->params.chip) && hdr->chip == FW_HDR_CHIP_T6))
3631                return true;
3632
3633        dev_err(adap->pdev_dev,
3634                "FW image (%d) is not suitable for this adapter (%d)\n",
3635                hdr->chip, CHELSIO_CHIP_VERSION(adap->params.chip));
3636        return false;
3637}
3638
3639/**
3640 *      t4_load_fw - download firmware
3641 *      @adap: the adapter
3642 *      @fw_data: the firmware image to write
3643 *      @size: image size
3644 *
3645 *      Write the supplied firmware image to the card's serial flash.
3646 */
3647int t4_load_fw(struct adapter *adap, const u8 *fw_data, unsigned int size)
3648{
3649        u32 csum;
3650        int ret, addr;
3651        unsigned int i;
3652        u8 first_page[SF_PAGE_SIZE];
3653        const __be32 *p = (const __be32 *)fw_data;
3654        const struct fw_hdr *hdr = (const struct fw_hdr *)fw_data;
3655        unsigned int sf_sec_size = adap->params.sf_size / adap->params.sf_nsec;
3656        unsigned int fw_start_sec = FLASH_FW_START_SEC;
3657        unsigned int fw_size = FLASH_FW_MAX_SIZE;
3658        unsigned int fw_start = FLASH_FW_START;
3659
3660        if (!size) {
3661                dev_err(adap->pdev_dev, "FW image has no data\n");
3662                return -EINVAL;
3663        }
3664        if (size & 511) {
3665                dev_err(adap->pdev_dev,
3666                        "FW image size not multiple of 512 bytes\n");
3667                return -EINVAL;
3668        }
3669        if ((unsigned int)be16_to_cpu(hdr->len512) * 512 != size) {
3670                dev_err(adap->pdev_dev,
3671                        "FW image size differs from size in FW header\n");
3672                return -EINVAL;
3673        }
3674        if (size > fw_size) {
3675                dev_err(adap->pdev_dev, "FW image too large, max is %u bytes\n",
3676                        fw_size);
3677                return -EFBIG;
3678        }
3679        if (!t4_fw_matches_chip(adap, hdr))
3680                return -EINVAL;
3681
3682        for (csum = 0, i = 0; i < size / sizeof(csum); i++)
3683                csum += be32_to_cpu(p[i]);
3684
3685        if (csum != 0xffffffff) {
3686                dev_err(adap->pdev_dev,
3687                        "corrupted firmware image, checksum %#x\n", csum);
3688                return -EINVAL;
3689        }
3690
3691        i = DIV_ROUND_UP(size, sf_sec_size);        /* # of sectors spanned */
3692        ret = t4_flash_erase_sectors(adap, fw_start_sec, fw_start_sec + i - 1);
3693        if (ret)
3694                goto out;
3695
3696        /*
3697         * We write the correct version at the end so the driver can see a bad
3698         * version if the FW write fails.  Start by writing a copy of the
3699         * first page with a bad version.
3700         */
3701        memcpy(first_page, fw_data, SF_PAGE_SIZE);
3702        ((struct fw_hdr *)first_page)->fw_ver = cpu_to_be32(0xffffffff);
3703        ret = t4_write_flash(adap, fw_start, SF_PAGE_SIZE, first_page, true);
3704        if (ret)
3705                goto out;
3706
3707        addr = fw_start;
3708        for (size -= SF_PAGE_SIZE; size; size -= SF_PAGE_SIZE) {
3709                addr += SF_PAGE_SIZE;
3710                fw_data += SF_PAGE_SIZE;
3711                ret = t4_write_flash(adap, addr, SF_PAGE_SIZE, fw_data, true);
3712                if (ret)
3713                        goto out;
3714        }
3715
3716        ret = t4_write_flash(adap, fw_start + offsetof(struct fw_hdr, fw_ver),
3717                             sizeof(hdr->fw_ver), (const u8 *)&hdr->fw_ver,
3718                             true);
3719out:
3720        if (ret)
3721                dev_err(adap->pdev_dev, "firmware download failed, error %d\n",
3722                        ret);
3723        else
3724                ret = t4_get_fw_version(adap, &adap->params.fw_vers);
3725        return ret;
3726}
3727
3728/**
3729 *      t4_phy_fw_ver - return current PHY firmware version
3730 *      @adap: the adapter
3731 *      @phy_fw_ver: return value buffer for PHY firmware version
3732 *
3733 *      Returns the current version of external PHY firmware on the
3734 *      adapter.
3735 */
3736int t4_phy_fw_ver(struct adapter *adap, int *phy_fw_ver)
3737{
3738        u32 param, val;
3739        int ret;
3740
3741        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3742                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3743                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3744                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_VERSION));
3745        ret = t4_query_params(adap, adap->mbox, adap->pf, 0, 1,
3746                              &param, &val);
3747        if (ret)
3748                return ret;
3749        *phy_fw_ver = val;
3750        return 0;
3751}
3752
3753/**
3754 *      t4_load_phy_fw - download port PHY firmware
3755 *      @adap: the adapter
3756 *      @win: the PCI-E Memory Window index to use for t4_memory_rw()
3757 *      @phy_fw_version: function to check PHY firmware versions
3758 *      @phy_fw_data: the PHY firmware image to write
3759 *      @phy_fw_size: image size
3760 *
3761 *      Transfer the specified PHY firmware to the adapter.  If a non-NULL
3762 *      @phy_fw_version is supplied, then it will be used to determine if
3763 *      it's necessary to perform the transfer by comparing the version
3764 *      of any existing adapter PHY firmware with that of the passed in
3765 *      PHY firmware image.
3766 *
3767 *      A negative error number will be returned if an error occurs.  If
3768 *      version number support is available and there's no need to upgrade
3769 *      the firmware, 0 will be returned.  If firmware is successfully
3770 *      transferred to the adapter, 1 will be returned.
3771 *
3772 *      NOTE: some adapters only have local RAM to store the PHY firmware.  As
3773 *      a result, a RESET of the adapter would cause that RAM to lose its
3774 *      contents.  Thus, loading PHY firmware on such adapters must happen
3775 *      after any FW_RESET_CMDs ...
3776 */
3777int t4_load_phy_fw(struct adapter *adap, int win,
3778                   int (*phy_fw_version)(const u8 *, size_t),
3779                   const u8 *phy_fw_data, size_t phy_fw_size)
3780{
3781        int cur_phy_fw_ver = 0, new_phy_fw_vers = 0;
3782        unsigned long mtype = 0, maddr = 0;
3783        u32 param, val;
3784        int ret;
3785
3786        /* If we have version number support, then check to see if the adapter
3787         * already has up-to-date PHY firmware loaded.
3788         */
3789        if (phy_fw_version) {
3790                new_phy_fw_vers = phy_fw_version(phy_fw_data, phy_fw_size);
3791                ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3792                if (ret < 0)
3793                        return ret;
3794
3795                if (cur_phy_fw_ver >= new_phy_fw_vers) {
3796                        CH_WARN(adap, "PHY Firmware already up-to-date, "
3797                                "version %#x\n", cur_phy_fw_ver);
3798                        return 0;
3799                }
3800        }
3801
3802        /* Ask the firmware where it wants us to copy the PHY firmware image.
3803         * The size of the file requires a special version of the READ command
3804         * which will pass the file size via the values field in PARAMS_CMD and
3805         * retrieve the return value from firmware and place it in the same
3806         * buffer values
3807         */
3808        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3809                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3810                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3811                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3812        val = phy_fw_size;
3813        ret = t4_query_params_rw(adap, adap->mbox, adap->pf, 0, 1,
3814                                 &param, &val, 1, true);
3815        if (ret < 0)
3816                return ret;
3817        mtype = val >> 8;
3818        maddr = (val & 0xff) << 16;
3819
3820        /* Copy the supplied PHY Firmware image to the adapter memory location
3821         * allocated by the adapter firmware.
3822         */
3823        spin_lock_bh(&adap->win0_lock);
3824        ret = t4_memory_rw(adap, win, mtype, maddr,
3825                           phy_fw_size, (__be32 *)phy_fw_data,
3826                           T4_MEMORY_WRITE);
3827        spin_unlock_bh(&adap->win0_lock);
3828        if (ret)
3829                return ret;
3830
3831        /* Tell the firmware that the PHY firmware image has been written to
3832         * RAM and it can now start copying it over to the PHYs.  The chip
3833         * firmware will RESET the affected PHYs as part of this operation
3834         * leaving them running the new PHY firmware image.
3835         */
3836        param = (FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3837                 FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_PHYFW) |
3838                 FW_PARAMS_PARAM_Y_V(adap->params.portvec) |
3839                 FW_PARAMS_PARAM_Z_V(FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD));
3840        ret = t4_set_params_timeout(adap, adap->mbox, adap->pf, 0, 1,
3841                                    &param, &val, 30000);
3842
3843        /* If we have version number support, then check to see that the new
3844         * firmware got loaded properly.
3845         */
3846        if (phy_fw_version) {
3847                ret = t4_phy_fw_ver(adap, &cur_phy_fw_ver);
3848                if (ret < 0)
3849                        return ret;
3850
3851                if (cur_phy_fw_ver != new_phy_fw_vers) {
3852                        CH_WARN(adap, "PHY Firmware did not update: "
3853                                "version on adapter %#x, "
3854                                "version flashed %#x\n",
3855                                cur_phy_fw_ver, new_phy_fw_vers);
3856                        return -ENXIO;
3857                }
3858        }
3859
3860        return 1;
3861}
3862
3863/**
3864 *      t4_fwcache - firmware cache operation
3865 *      @adap: the adapter
3866 *      @op  : the operation (flush or flush and invalidate)
3867 */
3868int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op)
3869{
3870        struct fw_params_cmd c;
3871
3872        memset(&c, 0, sizeof(c));
3873        c.op_to_vfn =
3874                cpu_to_be32(FW_CMD_OP_V(FW_PARAMS_CMD) |
3875                            FW_CMD_REQUEST_F | FW_CMD_WRITE_F |
3876                            FW_PARAMS_CMD_PFN_V(adap->pf) |
3877                            FW_PARAMS_CMD_VFN_V(0));
3878        c.retval_len16 = cpu_to_be32(FW_LEN16(c));
3879        c.param[0].mnem =
3880                cpu_to_be32(FW_PARAMS_MNEM_V(FW_PARAMS_MNEM_DEV) |
3881                            FW_PARAMS_PARAM_X_V(FW_PARAMS_PARAM_DEV_FWCACHE));
3882        c.param[0].val = cpu_to_be32(op);
3883
3884        return t4_wr_mbox(adap, adap->mbox, &c, sizeof(c), NULL);
3885}
3886
3887void t4_cim_read_pif_la(struct adapter *adap, u32 *pif_req, u32 *pif_rsp,
3888                        unsigned int *pif_req_wrptr,
3889                        unsigned int *pif_rsp_wrptr)
3890{
3891        int i, j;
3892        u32 cfg, val, req, rsp;
3893
3894        cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3895        if (cfg & LADBGEN_F)
3896                t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3897
3898        val = t4_read_reg(adap, CIM_DEBUGSTS_A);
3899        req = POLADBGWRPTR_G(val);
3900        rsp = PILADBGWRPTR_G(val);
3901        if (pif_req_wrptr)
3902                *pif_req_wrptr = req;
3903        if (pif_rsp_wrptr)
3904                *pif_rsp_wrptr = rsp;
3905
3906        for (i = 0; i < CIM_PIFLA_SIZE; i++) {
3907                for (j = 0; j < 6; j++) {
3908                        t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(req) |
3909                                     PILADBGRDPTR_V(rsp));
3910                        *pif_req++ = t4_read_reg(adap, CIM_PO_LA_DEBUGDATA_A);
3911                        *pif_rsp++ = t4_read_reg(adap, CIM_PI_LA_DEBUGDATA_A);
3912                        req++;
3913                        rsp++;
3914                }
3915                req = (req + 2) & POLADBGRDPTR_M;
3916                rsp = (rsp + 2) & PILADBGRDPTR_M;
3917        }
3918        t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3919}
3920
3921void t4_cim_read_ma_la(struct adapter *adap, u32 *ma_req, u32 *ma_rsp)
3922{
3923        u32 cfg;
3924        int i, j, idx;
3925
3926        cfg = t4_read_reg(adap, CIM_DEBUGCFG_A);
3927        if (cfg & LADBGEN_F)
3928                t4_write_reg(adap, CIM_DEBUGCFG_A, cfg ^ LADBGEN_F);
3929
3930        for (i = 0; i < CIM_MALA_SIZE; i++) {
3931                for (j = 0; j < 5; j++) {
3932                        idx = 8 * i + j;
3933                        t4_write_reg(adap, CIM_DEBUGCFG_A, POLADBGRDPTR_V(idx) |
3934                                     PILADBGRDPTR_V(idx));
3935                        *ma_req++ = t4_read_reg(adap, CIM_PO_LA_MADEBUGDATA_A);
3936                        *ma_rsp++ = t4_read_reg(adap, CIM_PI_LA_MADEBUGDATA_A);
3937                }
3938        }
3939        t4_write_reg(adap, CIM_DEBUGCFG_A, cfg);
3940}
3941
3942void t4_ulprx_read_la(struct adapter *adap, u32 *la_buf)
3943{
3944        unsigned int i, j;
3945
3946        for (i = 0; i < 8; i++) {
3947                u32 *p = la_buf + i;
3948
3949                t4_write_reg(adap, ULP_RX_LA_CTL_A, i);
3950                j = t4_read_reg(adap, ULP_RX_LA_WRPTR_A);
3951                t4_write_reg(adap, ULP_RX_LA_RDPTR_A, j);
3952                for (j = 0; j < ULPRX_LA_SIZE; j++, p += 8)
3953                        *p = t4_read_reg(adap, ULP_RX_LA_RDDATA_A);
3954        }
3955}
3956
3957/* The ADVERT_MASK is used to mask out all of the Advertised Firmware Port
3958 * Capabilities which we control with separate controls -- see, for instance,
3959 * Pause Frames and Forward Error Correction.  In order to determine what the
3960 * full set of Advertised Port Capabilities are, the base Advertised Port
3961 * Capabilities (masked by ADVERT_MASK) must be combined with the Advertised
3962 * Port Capabilities associated with those other controls.  See
3963 * t4_link_acaps() for how this is done.
3964 */
3965#define ADVERT_MASK (FW_PORT_CAP32_SPEED_V(FW_PORT_CAP32_SPEED_M) | \
3966                     FW_PORT_CAP32_ANEG)
3967
3968/**
3969 *      fwcaps16_to_caps32 - convert 16-bit Port Capabilities to 32-bits
3970 *      @caps16: a 16-bit Port Capabilities value
3971 *
3972 *      Returns the equivalent 32-bit Port Capabilities value.
3973 */
3974static fw_port_cap32_t fwcaps16_to_caps32(fw_port_cap16_t caps16)
3975{
3976        fw_port_cap32_t caps32 = 0;
3977
3978        #define CAP16_TO_CAP32(__cap) \
3979                do { \
3980                        if (caps16 & FW_PORT_CAP_##__cap) \
3981                                caps32 |= FW_PORT_CAP32_##__cap; \
3982                } while (0)
3983
3984        CAP16_TO_CAP32(SPEED_100M);
3985        CAP16_TO_CAP32(SPEED_1G);
3986        CAP16_TO_CAP32(SPEED_25G);
3987        CAP16_TO_CAP32(SPEED_10G);
3988        CAP16_TO_CAP32(SPEED_40G);
3989        CAP16_TO_CAP32(SPEED_100G);
3990        CAP16_TO_CAP32(FC_RX);
3991        CAP16_TO_CAP32(FC_TX);
3992        CAP16_TO_CAP32(ANEG);
3993        CAP16_TO_CAP32(FORCE_PAUSE);
3994        CAP16_TO_CAP32(MDIAUTO);
3995        CAP16_TO_CAP32(MDISTRAIGHT);
3996        CAP16_TO_CAP32(FEC_RS);
3997        CAP16_TO_CAP32(FEC_BASER_RS);
3998        CAP16_TO_CAP32(802_3_PAUSE);
3999        CAP16_TO_CAP32(802_3_ASM_DIR);
4000
4001        #undef CAP16_TO_CAP32
4002
4003        return caps32;
4004}
4005
4006/**
4007 *      fwcaps32_to_caps16 - convert 32-bit Port Capabilities to 16-bits
4008 *      @caps32: a 32-bit Port Capabilities value
4009 *
4010 *      Returns the equivalent 16-bit Port Capabilities value.  Note that
4011 *      not all 32-bit Port Capabilities can be represented in the 16-bit
4012 *      Port Capabilities and some fields/values may not make it.
4013 */
4014static fw_port_cap16_t fwcaps32_to_caps16(fw_port_cap32_t caps32)
4015{
4016        fw_port_cap16_t caps16 = 0;
4017
4018        #define CAP32_TO_CAP16(__cap) \
4019                do { \
4020                        if (caps32 & FW_PORT_CAP32_##__cap) \
4021                                caps16 |= FW_PORT_CAP_##__cap; \
4022                } while (0)
4023
4024        CAP32_TO_CAP16(SPEED_100M);
4025        CAP32_TO_CAP16(SPEED_1G);
4026        CAP32_TO_CAP16(SPEED_10G);
4027        CAP32_TO_CAP16(SPEED_25G);
4028        CAP32_TO_CAP16(SPEED_40G);
4029        CAP32_TO_CAP16(SPEED_100G);
4030        CAP32_TO_CAP16(FC_RX);
4031        CAP32_TO_CAP16(FC_TX);
4032        CAP32_TO_CAP16(802_3_PAUSE);
4033        CAP32_TO_CAP16(802_3_ASM_DIR);
4034        CAP32_TO_CAP16(ANEG);
4035        CAP32_TO_CAP16(FORCE_PAUSE);
4036        CAP32_TO_CAP16(MDIAUTO);
4037        CAP32_TO_CAP16(MDISTRAIGHT);
4038        CAP32_TO_CAP16(FEC_RS);
4039        CAP32_TO_CAP16(FEC_BASER_RS);
4040
4041        #undef CAP32_TO_CAP16
4042
4043        return caps16;
4044}
4045
4046/* Translate Firmware Port Capabilities Pause specification to Common Code */
4047static inline enum cc_pause fwcap_to_cc_pause(fw_port_cap32_t fw_pause)
4048{
4049        enum cc_pause cc_pause = 0;
4050
4051        if (fw_pause & FW_PORT_CAP32_FC_RX)
4052                cc_pause |= PAUSE_RX;
4053        if (fw_pause & FW_PORT_CAP32_FC_TX)
4054                cc_pause |= PAUSE_TX;
4055
4056        return cc_pause;
4057}
4058
4059/* Translate Common Code Pause specification into Firmware Port Capabilities */
4060static inline fw_port_cap32_t cc_to_fwcap_pause(enum cc_pause cc_pause)
4061{
4062        /* Translate orthogonal RX/TX Pause Controls for L1 Configure
4063         * commands, etc.
4064         */
4065        fw_port_cap32_t fw_pause = 0;
4066
4067        if (cc_pause & PAUSE_RX)
4068                fw_pause |= FW_PORT_CAP32_FC_RX;
4069        if (cc_pause & PAUSE_TX)
4070                fw_pause |= FW_PORT_CAP32_FC_TX;
4071        if (!(cc_pause & PAUSE_AUTONEG))
4072                fw_pause |= FW_PORT_CAP32_FORCE_PAUSE;
4073
4074        /* Translate orthogonal Pause controls into IEEE 802.3 Pause,
4075         * Asymmetrical Pause for use in reporting to upper layer OS code, etc.
4076         * Note that these bits are ignored in L1 Configure commands.
4077         */
4078        if (cc_pause & PAUSE_RX) {
4079                if (cc_pause & PAUSE_TX)
4080                        fw_pause |= FW_PORT_CAP32_802_3_PAUSE;
4081                else
4082                        fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR |
4083                                    FW_PORT_CAP32_802_3_PAUSE;
4084        } else if (cc_pause & PAUSE_TX) {
4085                fw_pause |= FW_PORT_CAP32_802_3_ASM_DIR;
4086        }
4087
4088        return fw_pause;
4089}
4090
4091/* Translate Firmware Forward Error Correction specification to Common Code */
4092static inline enum cc_fec fwcap_to_cc_fec(fw_port_cap32_t fw_fec)
4093{
4094        enum cc_fec cc_fec = 0;
4095
4096        if (fw_fec & FW_PORT_CAP32_FEC_RS)
4097                cc_fec |= FEC_RS;
4098        if (fw_fec & FW_PORT_CAP32_FEC_BASER_RS)
4099                cc_fec |= FEC_BASER_RS;
4100
4101        return cc_fec;
4102}
4103
4104/* Translate Common Code Forward Error Correction specification to Firmware */
4105static inline fw_port_cap32_t cc_to_fwcap_fec(enum cc_fec cc_fec)
4106{
4107        fw_port_cap32_t fw_fec = 0;
4108
4109        if (cc_fec & FEC_RS)
4110                fw_fec |= FW_PORT_CAP32_FEC_RS;
4111        if (cc_fec & FEC_BASER_RS)
4112                fw_fec |= FW_PORT_CAP32_FEC_BASER_RS;
4113
4114        return fw_fec;
4115}
4116
4117/**
4118 *      t4_link_acaps - compute Link Advertised Port Capabilities
4119 *      @adapter: the adapter
4120 *      @port: the Port ID
4121 *      @lc: the Port's Link Configuration
4122 *
4123 *      Synthesize the Advertised Port Capabilities we'll be using based on
4124 *      the base Advertised Port Capabilities (which have been filtered by
4125 *      ADVERT_MASK) plus the individual controls for things like Pause
4126 *      Frames, Forward Error Correction, MDI, etc.
4127 */
4128fw_port_cap32_t t4_link_acaps(struct adapter *adapter, unsigned int port,
4129                              struct link_config *lc)
4130{
4131        fw_port_cap32_t fw_fc, fw_fec, acaps;
4132        unsigned int fw_mdi;
4133        char cc_fec;
4134
4135        fw_mdi = (FW_PORT_CAP32_MDI_V(FW_PORT_CAP32_MDI_AUTO) & lc->pcaps);
4136
4137        /* Convert driver coding of Pause Frame Flow Control settings into the
4138         * Firmware's API.
4139         */
4140        fw_fc = cc_to_fwcap_pause(lc->requested_fc);
4141
4142        /* Convert Common Code Forward Error Control settings into the
4143         * Firmware's API.  If the current Requested FEC has "Automatic"
4144         * (IEEE 802.3) specified, then we use whatever the Firmware
4145         * sent us as part of its IEEE 802.3-based interpretation of
4146         * the Transceiver Module EPROM FEC parameters.  Otherwise we
4147         * use whatever is in the current Requested FEC settings.
4148         */
4149        if (lc->requested_fec & FEC_AUTO)
4150                cc_fec = fwcap_to_cc_fec(lc->def_acaps);
4151        else
4152                cc_fec = lc->requested_fec;
4153        fw_fec = cc_to_fwcap_fec(cc_fec);
4154
4155        /* Figure out what our Requested Port Capabilities are going to be.
4156         * Note parallel structure in t4_handle_get_port_info() and
4157         * init_link_config().
4158         */
4159        if (!(lc->pcaps & FW_PORT_CAP32_ANEG)) {
4160                acaps = lc->acaps | fw_fc | fw_fec;
4161                lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4162                lc->fec = cc_fec;
4163        } else if (lc->autoneg == AUTONEG_DISABLE) {
4164                acaps = lc->speed_caps | fw_fc | fw_fec | fw_mdi;
4165                lc->fc = lc->requested_fc & ~PAUSE_AUTONEG;
4166                lc->fec = cc_fec;
4167        } else {
4168                acaps = lc->acaps | fw_fc | fw_fec | fw_mdi;
4169        }
4170
4171        /* Some Requested Port Capabilities are trivially wrong if they exceed
4172         * the Physical Port Capabilities.  We can check that here and provide
4173         * moderately useful feedback in the system log.
4174         *
4175         * Note that older Firmware doesn't have FW_PORT_CAP32_FORCE_PAUSE, so
4176         * we need to exclude this from this check in order to maintain
4177         * compatibility ...
4178         */
4179        if ((acaps & ~lc->pcaps) & ~FW_PORT_CAP32_FORCE_PAUSE) {
4180                dev_err(adapter->pdev_dev, "Requested Port Capabilities %#x exceed Physical Port Capabilities %#x\n",
4181                        acaps, lc->pcaps);
4182                return -EINVAL;
4183        }
4184
4185        return acaps;
4186}
4187
4188/**
4189 *      t4_link_l1cfg_core - apply link configuration to MAC/PHY
4190 *      @adapter: the adapter
4191 *      @mbox: the Firmware Mailbox to use
4192 *      @port: the Port ID
4193 *      @lc: the Port's Link Configuration
4194 *      @sleep_ok: if true we may sleep while awaiting command completion
4195 *      @timeout: time to wait for command to finish before timing out
4196 *              (negative implies @sleep_ok=false)
4197 *
4198 *      Set up a port's MAC and PHY according to a desired link configuration.
4199 *      - If the PHY can auto-negotiate first decide what to advertise, then
4200 *        enable/disable auto-negotiation as desired, and reset.
4201 *      - If the PHY does not auto-negotiate just reset it.
4202 *      - If auto-negotiation is off set the MAC to the proper speed/duplex/FC,
4203 *        otherwise do it later based on the outcome of auto-negotiation.
4204 */
4205int t4_link_l1cfg_core(struct adapter *adapter, unsigned int mbox,
4206                       unsigned int port, struct link_config *lc,
4207                       u8 sleep_ok, int timeout)
4208{
4209        unsigned int fw_caps = adapter->params.fw_caps_support;
4210        struct fw_port_cmd cmd;
4211        fw_port_cap32_t rcap;
4212        int ret;
4213
4214        if (!(lc->pcaps & FW_PORT_CAP32_ANEG) &&
4215            lc->autoneg == AUTONEG_ENABLE) {
4216                return -EINVAL;
4217        }
4218
4219        /* Compute our Requested Port Capabilities and send that on to the
4220         * Firmware.
4221         */
4222        rcap = t4_link_acaps(adapter, port, lc);
4223        memset(&cmd, 0, sizeof(cmd));
4224        cmd.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4225                                       FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4226                                       FW_PORT_CMD_PORTID_V(port));
4227        cmd.action_to_len16 =
4228                cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4229                                                 ? FW_PORT_ACTION_L1_CFG
4230                                                 : FW_PORT_ACTION_L1_CFG32) |
4231                                                 FW_LEN16(cmd));
4232        if (fw_caps == FW_CAPS16)
4233                cmd.u.l1cfg.rcap = cpu_to_be32(fwcaps32_to_caps16(rcap));
4234        else
4235                cmd.u.l1cfg32.rcap32 = cpu_to_be32(rcap);
4236
4237        ret = t4_wr_mbox_meat_timeout(adapter, mbox, &cmd, sizeof(cmd), NULL,
4238                                      sleep_ok, timeout);
4239
4240        /* Unfortunately, even if the Requested Port Capabilities "fit" within
4241         * the Physical Port Capabilities, some combinations of features may
4242         * still not be legal.  For example, 40Gb/s and Reed-Solomon Forward
4243         * Error Correction.  So if the Firmware rejects the L1 Configure
4244         * request, flag that here.
4245         */
4246        if (ret) {
4247                dev_err(adapter->pdev_dev,
4248                        "Requested Port Capabilities %#x rejected, error %d\n",
4249                        rcap, -ret);
4250                return ret;
4251        }
4252        return 0;
4253}
4254
4255/**
4256 *      t4_restart_aneg - restart autonegotiation
4257 *      @adap: the adapter
4258 *      @mbox: mbox to use for the FW command
4259 *      @port: the port id
4260 *
4261 *      Restarts autonegotiation for the selected port.
4262 */
4263int t4_restart_aneg(struct adapter *adap, unsigned int mbox, unsigned int port)
4264{
4265        unsigned int fw_caps = adap->params.fw_caps_support;
4266        struct fw_port_cmd c;
4267
4268        memset(&c, 0, sizeof(c));
4269        c.op_to_portid = cpu_to_be32(FW_CMD_OP_V(FW_PORT_CMD) |
4270                                     FW_CMD_REQUEST_F | FW_CMD_EXEC_F |
4271                                     FW_PORT_CMD_PORTID_V(port));
4272        c.action_to_len16 =
4273                cpu_to_be32(FW_PORT_CMD_ACTION_V(fw_caps == FW_CAPS16
4274                                                 ? FW_PORT_ACTION_L1_CFG
4275                                                 : FW_PORT_ACTION_L1_CFG32) |
4276                            FW_LEN16(c));
4277        if (fw_caps == FW_CAPS16)
4278                c.u.l1cfg.rcap = cpu_to_be32(FW_PORT_CAP_ANEG);
4279        else
4280                c.u.l1cfg32.rcap32 = cpu_to_be32(FW_PORT_CAP32_ANEG);
4281        return t4_wr_mbox(adap, mbox, &c, sizeof(c), NULL);
4282}
4283
4284typedef void (*int_handler_t)(struct adapter *adap);
4285
4286struct intr_info {
4287        unsigned int mask;       /* bits to check in interrupt status */
4288        const char *msg;         /* message to print or NULL */
4289        short stat_idx;          /* stat counter to increment or -1 */
4290        unsigned short fatal;    /* whether the condition reported is fatal */
4291        int_handler_t int_handler; /* platform-specific int handler */
4292};
4293
4294/**
4295 *      t4_handle_intr_status - table driven interrupt handler
4296 *      @adapter: the adapter that generated the interrupt
4297 *      @reg: the interrupt status register to process
4298 *      @acts: table of interrupt actions
4299 *
4300 *      A table driven interrupt handler that applies a set of masks to an
4301 *      interrupt status word and performs the corresponding actions if the
4302 *      interrupts described by the mask have occurred.  The actions include
4303 *      optionally emitting a warning or alert message.  The table is terminated
4304 *      by an entry specifying mask 0.  Returns the number of fatal interrupt
4305 *      conditions.
4306 */
4307static int t4_handle_intr_status(struct adapter *adapter, unsigned int reg,
4308                                 const struct intr_info *acts)
4309{
4310        int fatal = 0;
4311        unsigned int mask = 0;
4312        unsigned int status = t4_read_reg(adapter, reg);
4313
4314        for ( ; acts->mask; ++acts) {
4315                if (!(status & acts->mask))
4316                        continue;
4317                if (acts->fatal) {
4318                        fatal++;
4319                        dev_alert(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4320                                  status & acts->mask);
4321                } else if (acts->msg && printk_ratelimit())
4322                        dev_warn(adapter->pdev_dev, "%s (0x%x)\n", acts->msg,
4323                                 status & acts->mask);
4324                if (acts->int_handler)
4325                        acts->int_handler(adapter);
4326                mask |= acts->mask;
4327        }
4328        status &= mask;
4329        if (status)                           /* clear processed interrupts */
4330                t4_write_reg(adapter, reg, status);
4331        return fatal;
4332}
4333
4334/*
4335 * Interrupt handler for the PCIE module.
4336 */
4337static void pcie_intr_handler(struct adapter *adapter)
4338{
4339        static const struct intr_info sysbus_intr_info[] = {
4340                { RNPP_F, "RXNP array parity error", -1, 1 },
4341                { RPCP_F, "RXPC array parity error", -1, 1 },
4342                { RCIP_F, "RXCIF array parity error", -1, 1 },
4343                { RCCP_F, "Rx completions control array parity error", -1, 1 },
4344                { RFTP_F, "RXFT array parity error", -1, 1 },
4345                { 0 }
4346        };
4347        static const struct intr_info pcie_port_intr_info[] = {
4348                { TPCP_F, "TXPC array parity error", -1, 1 },
4349                { TNPP_F, "TXNP array parity error", -1, 1 },
4350                { TFTP_F, "TXFT array parity error", -1, 1 },
4351                { TCAP_F, "TXCA array parity error", -1, 1 },
4352                { TCIP_F, "TXCIF array parity error", -1, 1 },
4353                { RCAP_F, "RXCA array parity error", -1, 1 },
4354                { OTDD_F, "outbound request TLP discarded", -1, 1 },
4355                { RDPE_F, "Rx data parity error", -1, 1 },
4356                { TDUE_F, "Tx uncorrectable data error", -1, 1 },
4357                { 0 }
4358        };
4359        static const struct intr_info pcie_intr_info[] = {
4360                { MSIADDRLPERR_F, "MSI AddrL parity error", -1, 1 },
4361                { MSIADDRHPERR_F, "MSI AddrH parity error", -1, 1 },
4362                { MSIDATAPERR_F, "MSI data parity error", -1, 1 },
4363                { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4364                { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4365                { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4366                { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4367                { PIOCPLPERR_F, "PCI PIO completion FIFO parity error", -1, 1 },
4368                { PIOREQPERR_F, "PCI PIO request FIFO parity error", -1, 1 },
4369                { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4370                { CCNTPERR_F, "PCI CMD channel count parity error", -1, 1 },
4371                { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4372                { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4373                { DCNTPERR_F, "PCI DMA channel count parity error", -1, 1 },
4374                { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4375                { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4376                { HCNTPERR_F, "PCI HMA channel count parity error", -1, 1 },
4377                { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4378                { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4379                { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4380                { FIDPERR_F, "PCI FID parity error", -1, 1 },
4381                { INTXCLRPERR_F, "PCI INTx clear parity error", -1, 1 },
4382                { MATAGPERR_F, "PCI MA tag parity error", -1, 1 },
4383                { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4384                { RXCPLPERR_F, "PCI Rx completion parity error", -1, 1 },
4385                { RXWRPERR_F, "PCI Rx write parity error", -1, 1 },
4386                { RPLPERR_F, "PCI replay buffer parity error", -1, 1 },
4387                { PCIESINT_F, "PCI core secondary fault", -1, 1 },
4388                { PCIEPINT_F, "PCI core primary fault", -1, 1 },
4389                { UNXSPLCPLERR_F, "PCI unexpected split completion error",
4390                  -1, 0 },
4391                { 0 }
4392        };
4393
4394        static struct intr_info t5_pcie_intr_info[] = {
4395                { MSTGRPPERR_F, "Master Response Read Queue parity error",
4396                  -1, 1 },
4397                { MSTTIMEOUTPERR_F, "Master Timeout FIFO parity error", -1, 1 },
4398                { MSIXSTIPERR_F, "MSI-X STI SRAM parity error", -1, 1 },
4399                { MSIXADDRLPERR_F, "MSI-X AddrL parity error", -1, 1 },
4400                { MSIXADDRHPERR_F, "MSI-X AddrH parity error", -1, 1 },
4401                { MSIXDATAPERR_F, "MSI-X data parity error", -1, 1 },
4402                { MSIXDIPERR_F, "MSI-X DI parity error", -1, 1 },
4403                { PIOCPLGRPPERR_F, "PCI PIO completion Group FIFO parity error",
4404                  -1, 1 },
4405                { PIOREQGRPPERR_F, "PCI PIO request Group FIFO parity error",
4406                  -1, 1 },
4407                { TARTAGPERR_F, "PCI PCI target tag FIFO parity error", -1, 1 },
4408                { MSTTAGQPERR_F, "PCI master tag queue parity error", -1, 1 },
4409                { CREQPERR_F, "PCI CMD channel request parity error", -1, 1 },
4410                { CRSPPERR_F, "PCI CMD channel response parity error", -1, 1 },
4411                { DREQWRPERR_F, "PCI DMA channel write request parity error",
4412                  -1, 1 },
4413                { DREQPERR_F, "PCI DMA channel request parity error", -1, 1 },
4414                { DRSPPERR_F, "PCI DMA channel response parity error", -1, 1 },
4415                { HREQWRPERR_F, "PCI HMA channel count parity error", -1, 1 },
4416                { HREQPERR_F, "PCI HMA channel request parity error", -1, 1 },
4417                { HRSPPERR_F, "PCI HMA channel response parity error", -1, 1 },
4418                { CFGSNPPERR_F, "PCI config snoop FIFO parity error", -1, 1 },
4419                { FIDPERR_F, "PCI FID parity error", -1, 1 },
4420                { VFIDPERR_F, "PCI INTx clear parity error", -1, 1 },
4421                { MAGRPPERR_F, "PCI MA group FIFO parity error", -1, 1 },
4422                { PIOTAGPERR_F, "PCI PIO tag parity error", -1, 1 },
4423                { IPRXHDRGRPPERR_F, "PCI IP Rx header group parity error",
4424                  -1, 1 },
4425                { IPRXDATAGRPPERR_F, "PCI IP Rx data group parity error",
4426                  -1, 1 },
4427                { RPLPERR_F, "PCI IP replay buffer parity error", -1, 1 },
4428                { IPSOTPERR_F, "PCI IP SOT buffer parity error", -1, 1 },
4429                { TRGT1GRPPERR_F, "PCI TRGT1 group FIFOs parity error", -1, 1 },
4430                { READRSPERR_F, "Outbound read error", -1, 0 },
4431                { 0 }
4432        };
4433
4434        int fat;
4435
4436        if (is_t4(adapter->params.chip))
4437                fat = t4_handle_intr_status(adapter,
4438                                PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS_A,
4439                                sysbus_intr_info) +
4440                        t4_handle_intr_status(adapter,
4441                                        PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS_A,
4442                                        pcie_port_intr_info) +
4443                        t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4444                                              pcie_intr_info);
4445        else
4446                fat = t4_handle_intr_status(adapter, PCIE_INT_CAUSE_A,
4447                                            t5_pcie_intr_info);
4448
4449        if (fat)
4450                t4_fatal_err(adapter);
4451}
4452
4453/*
4454 * TP interrupt handler.
4455 */
4456static void tp_intr_handler(struct adapter *adapter)
4457{
4458        static const struct intr_info tp_intr_info[] = {
4459                { 0x3fffffff, "TP parity error", -1, 1 },
4460                { FLMTXFLSTEMPTY_F, "TP out of Tx pages", -1, 1 },
4461                { 0 }
4462        };
4463
4464        if (t4_handle_intr_status(adapter, TP_INT_CAUSE_A, tp_intr_info))
4465                t4_fatal_err(adapter);
4466}
4467
4468/*
4469 * SGE interrupt handler.
4470 */
4471static void sge_intr_handler(struct adapter *adapter)
4472{
4473        u32 v = 0, perr;
4474        u32 err;
4475
4476        static const struct intr_info sge_intr_info[] = {
4477                { ERR_CPL_EXCEED_IQE_SIZE_F,
4478                  "SGE received CPL exceeding IQE size", -1, 1 },
4479                { ERR_INVALID_CIDX_INC_F,
4480                  "SGE GTS CIDX increment too large", -1, 0 },
4481                { ERR_CPL_OPCODE_0_F, "SGE received 0-length CPL", -1, 0 },
4482                { DBFIFO_LP_INT_F, NULL, -1, 0, t4_db_full },
4483                { ERR_DATA_CPL_ON_HIGH_QID1_F | ERR_DATA_CPL_ON_HIGH_QID0_F,
4484                  "SGE IQID > 1023 received CPL for FL", -1, 0 },
4485                { ERR_BAD_DB_PIDX3_F, "SGE DBP 3 pidx increment too large", -1,
4486                  0 },
4487                { ERR_BAD_DB_PIDX2_F, "SGE DBP 2 pidx increment too large", -1,
4488                  0 },
4489                { ERR_BAD_DB_PIDX1_F, "SGE DBP 1 pidx increment too large", -1,
4490                  0 },
4491                { ERR_BAD_DB_PIDX0_F, "SGE DBP 0 pidx increment too large", -1,
4492                  0 },
4493                { ERR_ING_CTXT_PRIO_F,
4494                  "SGE too many priority ingress contexts", -1, 0 },
4495                { INGRESS_SIZE_ERR_F, "SGE illegal ingress QID", -1, 0 },
4496                { EGRESS_SIZE_ERR_F, "SGE illegal egress QID", -1, 0 },
4497                { 0 }
4498        };
4499
4500        static struct intr_info t4t5_sge_intr_info[] = {
4501                { ERR_DROPPED_DB_F, NULL, -1, 0, t4_db_dropped },
4502                { DBFIFO_HP_INT_F, NULL, -1, 0, t4_db_full },
4503                { ERR_EGR_CTXT_PRIO_F,
4504                  "SGE too many priority egress contexts", -1, 0 },
4505                { 0 }
4506        };
4507
4508        perr = t4_read_reg(adapter, SGE_INT_CAUSE1_A);
4509        if (perr) {
4510                v |= perr;
4511                dev_alert(adapter->pdev_dev, "SGE Cause1 Parity Error %#x\n",
4512                          perr);
4513        }
4514
4515        perr = t4_read_reg(adapter, SGE_INT_CAUSE2_A);
4516        if (perr) {
4517                v |= perr;
4518                dev_alert(adapter->pdev_dev, "SGE Cause2 Parity Error %#x\n",
4519                          perr);
4520        }
4521
4522        if (CHELSIO_CHIP_VERSION(adapter->params.chip) >= CHELSIO_T5) {
4523                perr = t4_read_reg(adapter, SGE_INT_CAUSE5_A);
4524                /* Parity error (CRC) for err_T_RxCRC is trivial, ignore it */
4525                perr &= ~ERR_T_RXCRC_F;
4526                if (perr) {
4527                        v |= perr;
4528                        dev_alert(adapter->pdev_dev,
4529                                  "SGE Cause5 Parity Error %#x\n", perr);
4530                }
4531        }
4532
4533        v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A, sge_intr_info);
4534        if (CHELSIO_CHIP_VERSION(adapter->params.chip) <= CHELSIO_T5)
4535                v |= t4_handle_intr_status(adapter, SGE_INT_CAUSE3_A,
4536                                           t4t5_sge_intr_info);
4537
4538        err = t4_read_reg(adapter, SGE_ERROR_STATS_A);
4539        if (err & ERROR_QID_VALID_F) {
4540                dev_err(adapter->pdev_dev, "SGE error for queue %u\n",
4541                        ERROR_QID_G(err));
4542                if (err & UNCAPTURED_ERROR_F)
4543                        dev_err(adapter->pdev_dev,
4544                                "SGE UNCAPTURED_ERROR set (clearing)\n");
4545                t4_write_reg(adapter, SGE_ERROR_STATS_A, ERROR_QID_VALID_F |
4546                             UNCAPTURED_ERROR_F);
4547        }
4548
4549        if (v != 0)
4550                t4_fatal_err(adapter);
4551}
4552
4553#define CIM_OBQ_INTR (OBQULP0PARERR_F | OBQULP1PARERR_F | OBQULP2PARERR_F |\
4554                      OBQULP3PARERR_F | OBQSGEPARERR_F | OBQNCSIPARERR_F)
4555#define CIM_IBQ_INTR (IBQTP0PARERR_F | IBQTP1PARERR_F | IBQULPPARERR_F |\
4556                      IBQSGEHIPARERR_F | IBQSGELOPARERR_F | IBQNCSIPARERR_F)
4557
4558/*
4559 * CIM interrupt handler.
4560 */
4561static void cim_intr_handler(struct adapter *adapter)
4562{
4563        static const struct intr_info cim_intr_info[] = {
4564                { PREFDROPINT_F, "CIM control register prefetch drop", -1, 1 },
4565                { CIM_OBQ_INTR, "CIM OBQ parity error", -1, 1 },
4566                { CIM_IBQ_INTR, "CIM IBQ parity error", -1, 1 },
4567                { MBUPPARERR_F, "CIM mailbox uP parity error", -1, 1 },
4568                { MBHOSTPARERR_F, "CIM mailbox host parity error", -1, 1 },
4569                { TIEQINPARERRINT_F, "CIM TIEQ outgoing parity error", -1, 1 },
4570                { TIEQOUTPARERRINT_F, "CIM TIEQ incoming parity error", -1, 1 },
4571                { TIMER0INT_F, "CIM TIMER0 interrupt", -1, 1 },
4572                { 0 }
4573        };
4574        static const struct intr_info cim_upintr_info[] = {
4575                { RSVDSPACEINT_F, "CIM reserved space access", -1, 1 },
4576                { ILLTRANSINT_F, "CIM illegal transaction", -1, 1 },
4577                { ILLWRINT_F, "CIM illegal write", -1, 1 },
4578                { ILLRDINT_F, "CIM illegal read", -1, 1 },
4579                { ILLRDBEINT_F, "CIM illegal read BE", -1, 1 },
4580                { ILLWRBEINT_F, "CIM illegal write BE", -1, 1 },
4581                { SGLRDBOOTINT_F, "CIM single read from boot space", -1, 1 },
4582                { SGLWRBOOTINT_F, "CIM single write to boot space", -1, 1 },
4583                { BLKWRBOOTINT_F, "CIM block write to boot space", -1, 1 },
4584                { SGLRDFLASHINT_F, "CIM single read from flash space", -1, 1 },
4585                { SGLWRFLASHINT_F, "CIM single write to flash space", -1, 1 },
4586                { BLKWRFLASHINT_F, "CIM block write to flash space", -1, 1 },
4587                { SGLRDEEPROMINT_F, "CIM single EEPROM read", -1, 1 },
4588                { SGLWREEPROMINT_F, "CIM single EEPROM write", -1, 1 },
4589                { BLKRDEEPROMINT_F, "CIM block EEPROM read", -1, 1 },
4590                { BLKWREEPROMINT_F, "CIM block EEPROM write", -1, 1 },
4591                { SGLRDCTLINT_F, "CIM single read from CTL space", -1, 1 },
4592                { SGLWRCTLINT_F, "CIM single write to CTL space", -1, 1 },
4593                { BLKRDCTLINT_F, "CIM block read from CTL space", -1, 1 },
4594                { BLKWRCTLINT_F, "CIM block write to CTL space", -1, 1 },
4595                { SGLRDPLINT_F, "CIM single read from PL space", -1, 1 },
4596                { SGLWRPLINT_F, "CIM single write to PL space", -1, 1 },
4597                { BLKRDPLINT_F, "CIM block read from PL space", -1, 1 },
4598                { BLKWRPLINT_F, "CIM block write to PL space", -1, 1 },
4599                { REQOVRLOOKUPINT_F, "CIM request FIFO overwrite", -1, 1 },
4600                { RSPOVRLOOKUPINT_F, "CIM response FIFO overwrite", -1, 1 },
4601                { TIMEOUTINT_F, "CIM PIF timeout", -1, 1 },
4602                { TIMEOUTMAINT_F, "CIM PIF MA timeout", -1, 1 },
4603                { 0 }
4604        };
4605
4606        u32 val, fw_err;
4607        int fat;
4608
4609        fw_err = t4_read_reg(adapter, PCIE_FW_A);
4610        if (fw_err & PCIE_FW_ERR_F)
4611                t4_report_fw_error(adapter);
4612
4613        /* When the Firmware detects an internal error which normally
4614         * wouldn't raise a Host Interrupt, it forces a CIM Timer0 interrupt
4615         * in order to make sure the Host sees the Firmware Crash.  So
4616         * if we have a Timer0 interrupt and don't see a Firmware Crash,
4617         * ignore the Timer0 interrupt.
4618         */
4619
4620        val = t4_read_reg(adapter, CIM_HOST_INT_CAUSE_A);
4621        if (val & TIMER0INT_F)
4622                if (!(fw_err & PCIE_FW_ERR_F) ||
4623                    (PCIE_FW_EVAL_G(fw_err) != PCIE_FW_EVAL_CRASH))
4624                        t4_write_reg(adapter, CIM_HOST_INT_CAUSE_A,
4625                                     TIMER0INT_F);
4626
4627        fat = t4_handle_intr_status(adapter, CIM_HOST_INT_CAUSE_A,
4628                                    cim_intr_info) +
4629              t4_handle_intr_status(adapter, CIM_HOST_UPACC_INT_CAUSE_A,
4630                                    cim_upintr_info);
4631        if (fat)
4632                t4_fatal_err(adapter);
4633}
4634
4635/*
4636 * ULP RX interrupt handler.
4637 */
4638static void ulprx_intr_handler(struct adapter *adapter)
4639{
4640        static const struct intr_info ulprx_intr_info[] = {
4641                { 0x1800000, "ULPRX context error", -1, 1 },
4642                { 0x7fffff, "ULPRX parity error", -1, 1 },
4643                { 0 }
4644        };
4645
4646        if (t4_handle_intr_status(adapter, ULP_RX_INT_CAUSE_A, ulprx_intr_info))
4647                t4_fatal_err(adapter);
4648}
4649
4650/*
4651 * ULP TX interrupt handler.
4652 */
4653static void ulptx_intr_handler(struct adapter *adapter)
4654{
4655        static const struct intr_info ulptx_intr_info[] = {
4656                { PBL_BOUND_ERR_CH3_F, "ULPTX channel 3 PBL out of bounds", -1,
4657                  0 },
4658                { PBL_BOUND_ERR_CH2_F, "ULPTX channel 2 PBL out of bounds", -1,
4659                  0 },
4660                { PBL_BOUND_ERR_CH1_F, "ULPTX channel 1 PBL out of bounds", -1,
4661                  0 },
4662                { PBL_BOUND_ERR_CH0_F, "ULPTX channel 0 PBL out of bounds", -1,
4663                  0 },
4664                { 0xfffffff, "ULPTX parity error", -1, 1 },
4665                { 0 }
4666        };
4667
4668        if (t4_handle_intr_status(adapter, ULP_TX_INT_CAUSE_A, ulptx_intr_info))
4669                t4_fatal_err(adapter);
4670}
4671
4672/*