linux/drivers/net/ethernet/cavium/octeon/octeon_mgmt.c
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   1/*
   2 * This file is subject to the terms and conditions of the GNU General Public
   3 * License.  See the file "COPYING" in the main directory of this archive
   4 * for more details.
   5 *
   6 * Copyright (C) 2009-2012 Cavium, Inc
   7 */
   8
   9#include <linux/platform_device.h>
  10#include <linux/dma-mapping.h>
  11#include <linux/etherdevice.h>
  12#include <linux/capability.h>
  13#include <linux/net_tstamp.h>
  14#include <linux/interrupt.h>
  15#include <linux/netdevice.h>
  16#include <linux/spinlock.h>
  17#include <linux/if_vlan.h>
  18#include <linux/of_mdio.h>
  19#include <linux/module.h>
  20#include <linux/of_net.h>
  21#include <linux/init.h>
  22#include <linux/slab.h>
  23#include <linux/phy.h>
  24#include <linux/io.h>
  25
  26#include <asm/octeon/octeon.h>
  27#include <asm/octeon/cvmx-mixx-defs.h>
  28#include <asm/octeon/cvmx-agl-defs.h>
  29
  30#define DRV_NAME "octeon_mgmt"
  31#define DRV_DESCRIPTION \
  32        "Cavium Networks Octeon MII (management) port Network Driver"
  33
  34#define OCTEON_MGMT_NAPI_WEIGHT 16
  35
  36/* Ring sizes that are powers of two allow for more efficient modulo
  37 * opertions.
  38 */
  39#define OCTEON_MGMT_RX_RING_SIZE 512
  40#define OCTEON_MGMT_TX_RING_SIZE 128
  41
  42/* Allow 8 bytes for vlan and FCS. */
  43#define OCTEON_MGMT_RX_HEADROOM (ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN)
  44
  45union mgmt_port_ring_entry {
  46        u64 d64;
  47        struct {
  48#define RING_ENTRY_CODE_DONE 0xf
  49#define RING_ENTRY_CODE_MORE 0x10
  50#ifdef __BIG_ENDIAN_BITFIELD
  51                u64 reserved_62_63:2;
  52                /* Length of the buffer/packet in bytes */
  53                u64 len:14;
  54                /* For TX, signals that the packet should be timestamped */
  55                u64 tstamp:1;
  56                /* The RX error code */
  57                u64 code:7;
  58                /* Physical address of the buffer */
  59                u64 addr:40;
  60#else
  61                u64 addr:40;
  62                u64 code:7;
  63                u64 tstamp:1;
  64                u64 len:14;
  65                u64 reserved_62_63:2;
  66#endif
  67        } s;
  68};
  69
  70#define MIX_ORING1      0x0
  71#define MIX_ORING2      0x8
  72#define MIX_IRING1      0x10
  73#define MIX_IRING2      0x18
  74#define MIX_CTL         0x20
  75#define MIX_IRHWM       0x28
  76#define MIX_IRCNT       0x30
  77#define MIX_ORHWM       0x38
  78#define MIX_ORCNT       0x40
  79#define MIX_ISR         0x48
  80#define MIX_INTENA      0x50
  81#define MIX_REMCNT      0x58
  82#define MIX_BIST        0x78
  83
  84#define AGL_GMX_PRT_CFG                 0x10
  85#define AGL_GMX_RX_FRM_CTL              0x18
  86#define AGL_GMX_RX_FRM_MAX              0x30
  87#define AGL_GMX_RX_JABBER               0x38
  88#define AGL_GMX_RX_STATS_CTL            0x50
  89
  90#define AGL_GMX_RX_STATS_PKTS_DRP       0xb0
  91#define AGL_GMX_RX_STATS_OCTS_DRP       0xb8
  92#define AGL_GMX_RX_STATS_PKTS_BAD       0xc0
  93
  94#define AGL_GMX_RX_ADR_CTL              0x100
  95#define AGL_GMX_RX_ADR_CAM_EN           0x108
  96#define AGL_GMX_RX_ADR_CAM0             0x180
  97#define AGL_GMX_RX_ADR_CAM1             0x188
  98#define AGL_GMX_RX_ADR_CAM2             0x190
  99#define AGL_GMX_RX_ADR_CAM3             0x198
 100#define AGL_GMX_RX_ADR_CAM4             0x1a0
 101#define AGL_GMX_RX_ADR_CAM5             0x1a8
 102
 103#define AGL_GMX_TX_CLK                  0x208
 104#define AGL_GMX_TX_STATS_CTL            0x268
 105#define AGL_GMX_TX_CTL                  0x270
 106#define AGL_GMX_TX_STAT0                0x280
 107#define AGL_GMX_TX_STAT1                0x288
 108#define AGL_GMX_TX_STAT2                0x290
 109#define AGL_GMX_TX_STAT3                0x298
 110#define AGL_GMX_TX_STAT4                0x2a0
 111#define AGL_GMX_TX_STAT5                0x2a8
 112#define AGL_GMX_TX_STAT6                0x2b0
 113#define AGL_GMX_TX_STAT7                0x2b8
 114#define AGL_GMX_TX_STAT8                0x2c0
 115#define AGL_GMX_TX_STAT9                0x2c8
 116
 117struct octeon_mgmt {
 118        struct net_device *netdev;
 119        u64 mix;
 120        u64 agl;
 121        u64 agl_prt_ctl;
 122        int port;
 123        int irq;
 124        bool has_rx_tstamp;
 125        u64 *tx_ring;
 126        dma_addr_t tx_ring_handle;
 127        unsigned int tx_next;
 128        unsigned int tx_next_clean;
 129        unsigned int tx_current_fill;
 130        /* The tx_list lock also protects the ring related variables */
 131        struct sk_buff_head tx_list;
 132
 133        /* RX variables only touched in napi_poll.  No locking necessary. */
 134        u64 *rx_ring;
 135        dma_addr_t rx_ring_handle;
 136        unsigned int rx_next;
 137        unsigned int rx_next_fill;
 138        unsigned int rx_current_fill;
 139        struct sk_buff_head rx_list;
 140
 141        spinlock_t lock;
 142        unsigned int last_duplex;
 143        unsigned int last_link;
 144        unsigned int last_speed;
 145        struct device *dev;
 146        struct napi_struct napi;
 147        struct tasklet_struct tx_clean_tasklet;
 148        struct device_node *phy_np;
 149        resource_size_t mix_phys;
 150        resource_size_t mix_size;
 151        resource_size_t agl_phys;
 152        resource_size_t agl_size;
 153        resource_size_t agl_prt_ctl_phys;
 154        resource_size_t agl_prt_ctl_size;
 155};
 156
 157static void octeon_mgmt_set_rx_irq(struct octeon_mgmt *p, int enable)
 158{
 159        union cvmx_mixx_intena mix_intena;
 160        unsigned long flags;
 161
 162        spin_lock_irqsave(&p->lock, flags);
 163        mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);
 164        mix_intena.s.ithena = enable ? 1 : 0;
 165        cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
 166        spin_unlock_irqrestore(&p->lock, flags);
 167}
 168
 169static void octeon_mgmt_set_tx_irq(struct octeon_mgmt *p, int enable)
 170{
 171        union cvmx_mixx_intena mix_intena;
 172        unsigned long flags;
 173
 174        spin_lock_irqsave(&p->lock, flags);
 175        mix_intena.u64 = cvmx_read_csr(p->mix + MIX_INTENA);
 176        mix_intena.s.othena = enable ? 1 : 0;
 177        cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
 178        spin_unlock_irqrestore(&p->lock, flags);
 179}
 180
 181static void octeon_mgmt_enable_rx_irq(struct octeon_mgmt *p)
 182{
 183        octeon_mgmt_set_rx_irq(p, 1);
 184}
 185
 186static void octeon_mgmt_disable_rx_irq(struct octeon_mgmt *p)
 187{
 188        octeon_mgmt_set_rx_irq(p, 0);
 189}
 190
 191static void octeon_mgmt_enable_tx_irq(struct octeon_mgmt *p)
 192{
 193        octeon_mgmt_set_tx_irq(p, 1);
 194}
 195
 196static void octeon_mgmt_disable_tx_irq(struct octeon_mgmt *p)
 197{
 198        octeon_mgmt_set_tx_irq(p, 0);
 199}
 200
 201static unsigned int ring_max_fill(unsigned int ring_size)
 202{
 203        return ring_size - 8;
 204}
 205
 206static unsigned int ring_size_to_bytes(unsigned int ring_size)
 207{
 208        return ring_size * sizeof(union mgmt_port_ring_entry);
 209}
 210
 211static void octeon_mgmt_rx_fill_ring(struct net_device *netdev)
 212{
 213        struct octeon_mgmt *p = netdev_priv(netdev);
 214
 215        while (p->rx_current_fill < ring_max_fill(OCTEON_MGMT_RX_RING_SIZE)) {
 216                unsigned int size;
 217                union mgmt_port_ring_entry re;
 218                struct sk_buff *skb;
 219
 220                /* CN56XX pass 1 needs 8 bytes of padding.  */
 221                size = netdev->mtu + OCTEON_MGMT_RX_HEADROOM + 8 + NET_IP_ALIGN;
 222
 223                skb = netdev_alloc_skb(netdev, size);
 224                if (!skb)
 225                        break;
 226                skb_reserve(skb, NET_IP_ALIGN);
 227                __skb_queue_tail(&p->rx_list, skb);
 228
 229                re.d64 = 0;
 230                re.s.len = size;
 231                re.s.addr = dma_map_single(p->dev, skb->data,
 232                                           size,
 233                                           DMA_FROM_DEVICE);
 234
 235                /* Put it in the ring.  */
 236                p->rx_ring[p->rx_next_fill] = re.d64;
 237                /* Make sure there is no reorder of filling the ring and ringing
 238                 * the bell
 239                 */
 240                wmb();
 241
 242                dma_sync_single_for_device(p->dev, p->rx_ring_handle,
 243                                           ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
 244                                           DMA_BIDIRECTIONAL);
 245                p->rx_next_fill =
 246                        (p->rx_next_fill + 1) % OCTEON_MGMT_RX_RING_SIZE;
 247                p->rx_current_fill++;
 248                /* Ring the bell.  */
 249                cvmx_write_csr(p->mix + MIX_IRING2, 1);
 250        }
 251}
 252
 253static void octeon_mgmt_clean_tx_buffers(struct octeon_mgmt *p)
 254{
 255        union cvmx_mixx_orcnt mix_orcnt;
 256        union mgmt_port_ring_entry re;
 257        struct sk_buff *skb;
 258        int cleaned = 0;
 259        unsigned long flags;
 260
 261        mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
 262        while (mix_orcnt.s.orcnt) {
 263                spin_lock_irqsave(&p->tx_list.lock, flags);
 264
 265                mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
 266
 267                if (mix_orcnt.s.orcnt == 0) {
 268                        spin_unlock_irqrestore(&p->tx_list.lock, flags);
 269                        break;
 270                }
 271
 272                dma_sync_single_for_cpu(p->dev, p->tx_ring_handle,
 273                                        ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
 274                                        DMA_BIDIRECTIONAL);
 275
 276                re.d64 = p->tx_ring[p->tx_next_clean];
 277                p->tx_next_clean =
 278                        (p->tx_next_clean + 1) % OCTEON_MGMT_TX_RING_SIZE;
 279                skb = __skb_dequeue(&p->tx_list);
 280
 281                mix_orcnt.u64 = 0;
 282                mix_orcnt.s.orcnt = 1;
 283
 284                /* Acknowledge to hardware that we have the buffer.  */
 285                cvmx_write_csr(p->mix + MIX_ORCNT, mix_orcnt.u64);
 286                p->tx_current_fill--;
 287
 288                spin_unlock_irqrestore(&p->tx_list.lock, flags);
 289
 290                dma_unmap_single(p->dev, re.s.addr, re.s.len,
 291                                 DMA_TO_DEVICE);
 292
 293                /* Read the hardware TX timestamp if one was recorded */
 294                if (unlikely(re.s.tstamp)) {
 295                        struct skb_shared_hwtstamps ts;
 296                        u64 ns;
 297
 298                        memset(&ts, 0, sizeof(ts));
 299                        /* Read the timestamp */
 300                        ns = cvmx_read_csr(CVMX_MIXX_TSTAMP(p->port));
 301                        /* Remove the timestamp from the FIFO */
 302                        cvmx_write_csr(CVMX_MIXX_TSCTL(p->port), 0);
 303                        /* Tell the kernel about the timestamp */
 304                        ts.hwtstamp = ns_to_ktime(ns);
 305                        skb_tstamp_tx(skb, &ts);
 306                }
 307
 308                dev_kfree_skb_any(skb);
 309                cleaned++;
 310
 311                mix_orcnt.u64 = cvmx_read_csr(p->mix + MIX_ORCNT);
 312        }
 313
 314        if (cleaned && netif_queue_stopped(p->netdev))
 315                netif_wake_queue(p->netdev);
 316}
 317
 318static void octeon_mgmt_clean_tx_tasklet(struct tasklet_struct *t)
 319{
 320        struct octeon_mgmt *p = from_tasklet(p, t, tx_clean_tasklet);
 321        octeon_mgmt_clean_tx_buffers(p);
 322        octeon_mgmt_enable_tx_irq(p);
 323}
 324
 325static void octeon_mgmt_update_rx_stats(struct net_device *netdev)
 326{
 327        struct octeon_mgmt *p = netdev_priv(netdev);
 328        unsigned long flags;
 329        u64 drop, bad;
 330
 331        /* These reads also clear the count registers.  */
 332        drop = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP);
 333        bad = cvmx_read_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD);
 334
 335        if (drop || bad) {
 336                /* Do an atomic update. */
 337                spin_lock_irqsave(&p->lock, flags);
 338                netdev->stats.rx_errors += bad;
 339                netdev->stats.rx_dropped += drop;
 340                spin_unlock_irqrestore(&p->lock, flags);
 341        }
 342}
 343
 344static void octeon_mgmt_update_tx_stats(struct net_device *netdev)
 345{
 346        struct octeon_mgmt *p = netdev_priv(netdev);
 347        unsigned long flags;
 348
 349        union cvmx_agl_gmx_txx_stat0 s0;
 350        union cvmx_agl_gmx_txx_stat1 s1;
 351
 352        /* These reads also clear the count registers.  */
 353        s0.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT0);
 354        s1.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_STAT1);
 355
 356        if (s0.s.xsdef || s0.s.xscol || s1.s.scol || s1.s.mcol) {
 357                /* Do an atomic update. */
 358                spin_lock_irqsave(&p->lock, flags);
 359                netdev->stats.tx_errors += s0.s.xsdef + s0.s.xscol;
 360                netdev->stats.collisions += s1.s.scol + s1.s.mcol;
 361                spin_unlock_irqrestore(&p->lock, flags);
 362        }
 363}
 364
 365/*
 366 * Dequeue a receive skb and its corresponding ring entry.  The ring
 367 * entry is returned, *pskb is updated to point to the skb.
 368 */
 369static u64 octeon_mgmt_dequeue_rx_buffer(struct octeon_mgmt *p,
 370                                         struct sk_buff **pskb)
 371{
 372        union mgmt_port_ring_entry re;
 373
 374        dma_sync_single_for_cpu(p->dev, p->rx_ring_handle,
 375                                ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
 376                                DMA_BIDIRECTIONAL);
 377
 378        re.d64 = p->rx_ring[p->rx_next];
 379        p->rx_next = (p->rx_next + 1) % OCTEON_MGMT_RX_RING_SIZE;
 380        p->rx_current_fill--;
 381        *pskb = __skb_dequeue(&p->rx_list);
 382
 383        dma_unmap_single(p->dev, re.s.addr,
 384                         ETH_FRAME_LEN + OCTEON_MGMT_RX_HEADROOM,
 385                         DMA_FROM_DEVICE);
 386
 387        return re.d64;
 388}
 389
 390
 391static int octeon_mgmt_receive_one(struct octeon_mgmt *p)
 392{
 393        struct net_device *netdev = p->netdev;
 394        union cvmx_mixx_ircnt mix_ircnt;
 395        union mgmt_port_ring_entry re;
 396        struct sk_buff *skb;
 397        struct sk_buff *skb2;
 398        struct sk_buff *skb_new;
 399        union mgmt_port_ring_entry re2;
 400        int rc = 1;
 401
 402
 403        re.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb);
 404        if (likely(re.s.code == RING_ENTRY_CODE_DONE)) {
 405                /* A good packet, send it up. */
 406                skb_put(skb, re.s.len);
 407good:
 408                /* Process the RX timestamp if it was recorded */
 409                if (p->has_rx_tstamp) {
 410                        /* The first 8 bytes are the timestamp */
 411                        u64 ns = *(u64 *)skb->data;
 412                        struct skb_shared_hwtstamps *ts;
 413                        ts = skb_hwtstamps(skb);
 414                        ts->hwtstamp = ns_to_ktime(ns);
 415                        __skb_pull(skb, 8);
 416                }
 417                skb->protocol = eth_type_trans(skb, netdev);
 418                netdev->stats.rx_packets++;
 419                netdev->stats.rx_bytes += skb->len;
 420                netif_receive_skb(skb);
 421                rc = 0;
 422        } else if (re.s.code == RING_ENTRY_CODE_MORE) {
 423                /* Packet split across skbs.  This can happen if we
 424                 * increase the MTU.  Buffers that are already in the
 425                 * rx ring can then end up being too small.  As the rx
 426                 * ring is refilled, buffers sized for the new MTU
 427                 * will be used and we should go back to the normal
 428                 * non-split case.
 429                 */
 430                skb_put(skb, re.s.len);
 431                do {
 432                        re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
 433                        if (re2.s.code != RING_ENTRY_CODE_MORE
 434                                && re2.s.code != RING_ENTRY_CODE_DONE)
 435                                goto split_error;
 436                        skb_put(skb2,  re2.s.len);
 437                        skb_new = skb_copy_expand(skb, 0, skb2->len,
 438                                                  GFP_ATOMIC);
 439                        if (!skb_new)
 440                                goto split_error;
 441                        if (skb_copy_bits(skb2, 0, skb_tail_pointer(skb_new),
 442                                          skb2->len))
 443                                goto split_error;
 444                        skb_put(skb_new, skb2->len);
 445                        dev_kfree_skb_any(skb);
 446                        dev_kfree_skb_any(skb2);
 447                        skb = skb_new;
 448                } while (re2.s.code == RING_ENTRY_CODE_MORE);
 449                goto good;
 450        } else {
 451                /* Some other error, discard it. */
 452                dev_kfree_skb_any(skb);
 453                /* Error statistics are accumulated in
 454                 * octeon_mgmt_update_rx_stats.
 455                 */
 456        }
 457        goto done;
 458split_error:
 459        /* Discard the whole mess. */
 460        dev_kfree_skb_any(skb);
 461        dev_kfree_skb_any(skb2);
 462        while (re2.s.code == RING_ENTRY_CODE_MORE) {
 463                re2.d64 = octeon_mgmt_dequeue_rx_buffer(p, &skb2);
 464                dev_kfree_skb_any(skb2);
 465        }
 466        netdev->stats.rx_errors++;
 467
 468done:
 469        /* Tell the hardware we processed a packet.  */
 470        mix_ircnt.u64 = 0;
 471        mix_ircnt.s.ircnt = 1;
 472        cvmx_write_csr(p->mix + MIX_IRCNT, mix_ircnt.u64);
 473        return rc;
 474}
 475
 476static int octeon_mgmt_receive_packets(struct octeon_mgmt *p, int budget)
 477{
 478        unsigned int work_done = 0;
 479        union cvmx_mixx_ircnt mix_ircnt;
 480        int rc;
 481
 482        mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);
 483        while (work_done < budget && mix_ircnt.s.ircnt) {
 484
 485                rc = octeon_mgmt_receive_one(p);
 486                if (!rc)
 487                        work_done++;
 488
 489                /* Check for more packets. */
 490                mix_ircnt.u64 = cvmx_read_csr(p->mix + MIX_IRCNT);
 491        }
 492
 493        octeon_mgmt_rx_fill_ring(p->netdev);
 494
 495        return work_done;
 496}
 497
 498static int octeon_mgmt_napi_poll(struct napi_struct *napi, int budget)
 499{
 500        struct octeon_mgmt *p = container_of(napi, struct octeon_mgmt, napi);
 501        struct net_device *netdev = p->netdev;
 502        unsigned int work_done = 0;
 503
 504        work_done = octeon_mgmt_receive_packets(p, budget);
 505
 506        if (work_done < budget) {
 507                /* We stopped because no more packets were available. */
 508                napi_complete_done(napi, work_done);
 509                octeon_mgmt_enable_rx_irq(p);
 510        }
 511        octeon_mgmt_update_rx_stats(netdev);
 512
 513        return work_done;
 514}
 515
 516/* Reset the hardware to clean state.  */
 517static void octeon_mgmt_reset_hw(struct octeon_mgmt *p)
 518{
 519        union cvmx_mixx_ctl mix_ctl;
 520        union cvmx_mixx_bist mix_bist;
 521        union cvmx_agl_gmx_bist agl_gmx_bist;
 522
 523        mix_ctl.u64 = 0;
 524        cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
 525        do {
 526                mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
 527        } while (mix_ctl.s.busy);
 528        mix_ctl.s.reset = 1;
 529        cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
 530        cvmx_read_csr(p->mix + MIX_CTL);
 531        octeon_io_clk_delay(64);
 532
 533        mix_bist.u64 = cvmx_read_csr(p->mix + MIX_BIST);
 534        if (mix_bist.u64)
 535                dev_warn(p->dev, "MIX failed BIST (0x%016llx)\n",
 536                        (unsigned long long)mix_bist.u64);
 537
 538        agl_gmx_bist.u64 = cvmx_read_csr(CVMX_AGL_GMX_BIST);
 539        if (agl_gmx_bist.u64)
 540                dev_warn(p->dev, "AGL failed BIST (0x%016llx)\n",
 541                         (unsigned long long)agl_gmx_bist.u64);
 542}
 543
 544struct octeon_mgmt_cam_state {
 545        u64 cam[6];
 546        u64 cam_mask;
 547        int cam_index;
 548};
 549
 550static void octeon_mgmt_cam_state_add(struct octeon_mgmt_cam_state *cs,
 551                                      unsigned char *addr)
 552{
 553        int i;
 554
 555        for (i = 0; i < 6; i++)
 556                cs->cam[i] |= (u64)addr[i] << (8 * (cs->cam_index));
 557        cs->cam_mask |= (1ULL << cs->cam_index);
 558        cs->cam_index++;
 559}
 560
 561static void octeon_mgmt_set_rx_filtering(struct net_device *netdev)
 562{
 563        struct octeon_mgmt *p = netdev_priv(netdev);
 564        union cvmx_agl_gmx_rxx_adr_ctl adr_ctl;
 565        union cvmx_agl_gmx_prtx_cfg agl_gmx_prtx;
 566        unsigned long flags;
 567        unsigned int prev_packet_enable;
 568        unsigned int cam_mode = 1; /* 1 - Accept on CAM match */
 569        unsigned int multicast_mode = 1; /* 1 - Reject all multicast.  */
 570        struct octeon_mgmt_cam_state cam_state;
 571        struct netdev_hw_addr *ha;
 572        int available_cam_entries;
 573
 574        memset(&cam_state, 0, sizeof(cam_state));
 575
 576        if ((netdev->flags & IFF_PROMISC) || netdev->uc.count > 7) {
 577                cam_mode = 0;
 578                available_cam_entries = 8;
 579        } else {
 580                /* One CAM entry for the primary address, leaves seven
 581                 * for the secondary addresses.
 582                 */
 583                available_cam_entries = 7 - netdev->uc.count;
 584        }
 585
 586        if (netdev->flags & IFF_MULTICAST) {
 587                if (cam_mode == 0 || (netdev->flags & IFF_ALLMULTI) ||
 588                    netdev_mc_count(netdev) > available_cam_entries)
 589                        multicast_mode = 2; /* 2 - Accept all multicast.  */
 590                else
 591                        multicast_mode = 0; /* 0 - Use CAM.  */
 592        }
 593
 594        if (cam_mode == 1) {
 595                /* Add primary address. */
 596                octeon_mgmt_cam_state_add(&cam_state, netdev->dev_addr);
 597                netdev_for_each_uc_addr(ha, netdev)
 598                        octeon_mgmt_cam_state_add(&cam_state, ha->addr);
 599        }
 600        if (multicast_mode == 0) {
 601                netdev_for_each_mc_addr(ha, netdev)
 602                        octeon_mgmt_cam_state_add(&cam_state, ha->addr);
 603        }
 604
 605        spin_lock_irqsave(&p->lock, flags);
 606
 607        /* Disable packet I/O. */
 608        agl_gmx_prtx.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
 609        prev_packet_enable = agl_gmx_prtx.s.en;
 610        agl_gmx_prtx.s.en = 0;
 611        cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);
 612
 613        adr_ctl.u64 = 0;
 614        adr_ctl.s.cam_mode = cam_mode;
 615        adr_ctl.s.mcst = multicast_mode;
 616        adr_ctl.s.bcst = 1;     /* Allow broadcast */
 617
 618        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CTL, adr_ctl.u64);
 619
 620        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM0, cam_state.cam[0]);
 621        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM1, cam_state.cam[1]);
 622        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM2, cam_state.cam[2]);
 623        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM3, cam_state.cam[3]);
 624        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM4, cam_state.cam[4]);
 625        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM5, cam_state.cam[5]);
 626        cvmx_write_csr(p->agl + AGL_GMX_RX_ADR_CAM_EN, cam_state.cam_mask);
 627
 628        /* Restore packet I/O. */
 629        agl_gmx_prtx.s.en = prev_packet_enable;
 630        cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, agl_gmx_prtx.u64);
 631
 632        spin_unlock_irqrestore(&p->lock, flags);
 633}
 634
 635static int octeon_mgmt_set_mac_address(struct net_device *netdev, void *addr)
 636{
 637        int r = eth_mac_addr(netdev, addr);
 638
 639        if (r)
 640                return r;
 641
 642        octeon_mgmt_set_rx_filtering(netdev);
 643
 644        return 0;
 645}
 646
 647static int octeon_mgmt_change_mtu(struct net_device *netdev, int new_mtu)
 648{
 649        struct octeon_mgmt *p = netdev_priv(netdev);
 650        int max_packet = new_mtu + ETH_HLEN + ETH_FCS_LEN;
 651
 652        netdev->mtu = new_mtu;
 653
 654        /* HW lifts the limit if the frame is VLAN tagged
 655         * (+4 bytes per each tag, up to two tags)
 656         */
 657        cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_MAX, max_packet);
 658        /* Set the hardware to truncate packets larger than the MTU. The jabber
 659         * register must be set to a multiple of 8 bytes, so round up. JABBER is
 660         * an unconditional limit, so we need to account for two possible VLAN
 661         * tags.
 662         */
 663        cvmx_write_csr(p->agl + AGL_GMX_RX_JABBER,
 664                       (max_packet + 7 + VLAN_HLEN * 2) & 0xfff8);
 665
 666        return 0;
 667}
 668
 669static irqreturn_t octeon_mgmt_interrupt(int cpl, void *dev_id)
 670{
 671        struct net_device *netdev = dev_id;
 672        struct octeon_mgmt *p = netdev_priv(netdev);
 673        union cvmx_mixx_isr mixx_isr;
 674
 675        mixx_isr.u64 = cvmx_read_csr(p->mix + MIX_ISR);
 676
 677        /* Clear any pending interrupts */
 678        cvmx_write_csr(p->mix + MIX_ISR, mixx_isr.u64);
 679        cvmx_read_csr(p->mix + MIX_ISR);
 680
 681        if (mixx_isr.s.irthresh) {
 682                octeon_mgmt_disable_rx_irq(p);
 683                napi_schedule(&p->napi);
 684        }
 685        if (mixx_isr.s.orthresh) {
 686                octeon_mgmt_disable_tx_irq(p);
 687                tasklet_schedule(&p->tx_clean_tasklet);
 688        }
 689
 690        return IRQ_HANDLED;
 691}
 692
 693static int octeon_mgmt_ioctl_hwtstamp(struct net_device *netdev,
 694                                      struct ifreq *rq, int cmd)
 695{
 696        struct octeon_mgmt *p = netdev_priv(netdev);
 697        struct hwtstamp_config config;
 698        union cvmx_mio_ptp_clock_cfg ptp;
 699        union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
 700        bool have_hw_timestamps = false;
 701
 702        if (copy_from_user(&config, rq->ifr_data, sizeof(config)))
 703                return -EFAULT;
 704
 705        if (config.flags) /* reserved for future extensions */
 706                return -EINVAL;
 707
 708        /* Check the status of hardware for tiemstamps */
 709        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
 710                /* Get the current state of the PTP clock */
 711                ptp.u64 = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_CFG);
 712                if (!ptp.s.ext_clk_en) {
 713                        /* The clock has not been configured to use an
 714                         * external source.  Program it to use the main clock
 715                         * reference.
 716                         */
 717                        u64 clock_comp = (NSEC_PER_SEC << 32) / octeon_get_io_clock_rate();
 718                        if (!ptp.s.ptp_en)
 719                                cvmx_write_csr(CVMX_MIO_PTP_CLOCK_COMP, clock_comp);
 720                        netdev_info(netdev,
 721                                    "PTP Clock using sclk reference @ %lldHz\n",
 722                                    (NSEC_PER_SEC << 32) / clock_comp);
 723                } else {
 724                        /* The clock is already programmed to use a GPIO */
 725                        u64 clock_comp = cvmx_read_csr(CVMX_MIO_PTP_CLOCK_COMP);
 726                        netdev_info(netdev,
 727                                    "PTP Clock using GPIO%d @ %lld Hz\n",
 728                                    ptp.s.ext_clk_in, (NSEC_PER_SEC << 32) / clock_comp);
 729                }
 730
 731                /* Enable the clock if it wasn't done already */
 732                if (!ptp.s.ptp_en) {
 733                        ptp.s.ptp_en = 1;
 734                        cvmx_write_csr(CVMX_MIO_PTP_CLOCK_CFG, ptp.u64);
 735                }
 736                have_hw_timestamps = true;
 737        }
 738
 739        if (!have_hw_timestamps)
 740                return -EINVAL;
 741
 742        switch (config.tx_type) {
 743        case HWTSTAMP_TX_OFF:
 744        case HWTSTAMP_TX_ON:
 745                break;
 746        default:
 747                return -ERANGE;
 748        }
 749
 750        switch (config.rx_filter) {
 751        case HWTSTAMP_FILTER_NONE:
 752                p->has_rx_tstamp = false;
 753                rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);
 754                rxx_frm_ctl.s.ptp_mode = 0;
 755                cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
 756                break;
 757        case HWTSTAMP_FILTER_ALL:
 758        case HWTSTAMP_FILTER_SOME:
 759        case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
 760        case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
 761        case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
 762        case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
 763        case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
 764        case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
 765        case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
 766        case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
 767        case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
 768        case HWTSTAMP_FILTER_PTP_V2_EVENT:
 769        case HWTSTAMP_FILTER_PTP_V2_SYNC:
 770        case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
 771        case HWTSTAMP_FILTER_NTP_ALL:
 772                p->has_rx_tstamp = have_hw_timestamps;
 773                config.rx_filter = HWTSTAMP_FILTER_ALL;
 774                if (p->has_rx_tstamp) {
 775                        rxx_frm_ctl.u64 = cvmx_read_csr(p->agl + AGL_GMX_RX_FRM_CTL);
 776                        rxx_frm_ctl.s.ptp_mode = 1;
 777                        cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
 778                }
 779                break;
 780        default:
 781                return -ERANGE;
 782        }
 783
 784        if (copy_to_user(rq->ifr_data, &config, sizeof(config)))
 785                return -EFAULT;
 786
 787        return 0;
 788}
 789
 790static int octeon_mgmt_ioctl(struct net_device *netdev,
 791                             struct ifreq *rq, int cmd)
 792{
 793        switch (cmd) {
 794        case SIOCSHWTSTAMP:
 795                return octeon_mgmt_ioctl_hwtstamp(netdev, rq, cmd);
 796        default:
 797                return phy_do_ioctl(netdev, rq, cmd);
 798        }
 799}
 800
 801static void octeon_mgmt_disable_link(struct octeon_mgmt *p)
 802{
 803        union cvmx_agl_gmx_prtx_cfg prtx_cfg;
 804
 805        /* Disable GMX before we make any changes. */
 806        prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
 807        prtx_cfg.s.en = 0;
 808        prtx_cfg.s.tx_en = 0;
 809        prtx_cfg.s.rx_en = 0;
 810        cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
 811
 812        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
 813                int i;
 814                for (i = 0; i < 10; i++) {
 815                        prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
 816                        if (prtx_cfg.s.tx_idle == 1 || prtx_cfg.s.rx_idle == 1)
 817                                break;
 818                        mdelay(1);
 819                        i++;
 820                }
 821        }
 822}
 823
 824static void octeon_mgmt_enable_link(struct octeon_mgmt *p)
 825{
 826        union cvmx_agl_gmx_prtx_cfg prtx_cfg;
 827
 828        /* Restore the GMX enable state only if link is set */
 829        prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
 830        prtx_cfg.s.tx_en = 1;
 831        prtx_cfg.s.rx_en = 1;
 832        prtx_cfg.s.en = 1;
 833        cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
 834}
 835
 836static void octeon_mgmt_update_link(struct octeon_mgmt *p)
 837{
 838        struct net_device *ndev = p->netdev;
 839        struct phy_device *phydev = ndev->phydev;
 840        union cvmx_agl_gmx_prtx_cfg prtx_cfg;
 841
 842        prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
 843
 844        if (!phydev->link)
 845                prtx_cfg.s.duplex = 1;
 846        else
 847                prtx_cfg.s.duplex = phydev->duplex;
 848
 849        switch (phydev->speed) {
 850        case 10:
 851                prtx_cfg.s.speed = 0;
 852                prtx_cfg.s.slottime = 0;
 853
 854                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
 855                        prtx_cfg.s.burst = 1;
 856                        prtx_cfg.s.speed_msb = 1;
 857                }
 858                break;
 859        case 100:
 860                prtx_cfg.s.speed = 0;
 861                prtx_cfg.s.slottime = 0;
 862
 863                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
 864                        prtx_cfg.s.burst = 1;
 865                        prtx_cfg.s.speed_msb = 0;
 866                }
 867                break;
 868        case 1000:
 869                /* 1000 MBits is only supported on 6XXX chips */
 870                if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
 871                        prtx_cfg.s.speed = 1;
 872                        prtx_cfg.s.speed_msb = 0;
 873                        /* Only matters for half-duplex */
 874                        prtx_cfg.s.slottime = 1;
 875                        prtx_cfg.s.burst = phydev->duplex;
 876                }
 877                break;
 878        case 0:  /* No link */
 879        default:
 880                break;
 881        }
 882
 883        /* Write the new GMX setting with the port still disabled. */
 884        cvmx_write_csr(p->agl + AGL_GMX_PRT_CFG, prtx_cfg.u64);
 885
 886        /* Read GMX CFG again to make sure the config is completed. */
 887        prtx_cfg.u64 = cvmx_read_csr(p->agl + AGL_GMX_PRT_CFG);
 888
 889        if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) {
 890                union cvmx_agl_gmx_txx_clk agl_clk;
 891                union cvmx_agl_prtx_ctl prtx_ctl;
 892
 893                prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
 894                agl_clk.u64 = cvmx_read_csr(p->agl + AGL_GMX_TX_CLK);
 895                /* MII (both speeds) and RGMII 1000 speed. */
 896                agl_clk.s.clk_cnt = 1;
 897                if (prtx_ctl.s.mode == 0) { /* RGMII mode */
 898                        if (phydev->speed == 10)
 899                                agl_clk.s.clk_cnt = 50;
 900                        else if (phydev->speed == 100)
 901                                agl_clk.s.clk_cnt = 5;
 902                }
 903                cvmx_write_csr(p->agl + AGL_GMX_TX_CLK, agl_clk.u64);
 904        }
 905}
 906
 907static void octeon_mgmt_adjust_link(struct net_device *netdev)
 908{
 909        struct octeon_mgmt *p = netdev_priv(netdev);
 910        struct phy_device *phydev = netdev->phydev;
 911        unsigned long flags;
 912        int link_changed = 0;
 913
 914        if (!phydev)
 915                return;
 916
 917        spin_lock_irqsave(&p->lock, flags);
 918
 919
 920        if (!phydev->link && p->last_link)
 921                link_changed = -1;
 922
 923        if (phydev->link &&
 924            (p->last_duplex != phydev->duplex ||
 925             p->last_link != phydev->link ||
 926             p->last_speed != phydev->speed)) {
 927                octeon_mgmt_disable_link(p);
 928                link_changed = 1;
 929                octeon_mgmt_update_link(p);
 930                octeon_mgmt_enable_link(p);
 931        }
 932
 933        p->last_link = phydev->link;
 934        p->last_speed = phydev->speed;
 935        p->last_duplex = phydev->duplex;
 936
 937        spin_unlock_irqrestore(&p->lock, flags);
 938
 939        if (link_changed != 0) {
 940                if (link_changed > 0)
 941                        netdev_info(netdev, "Link is up - %d/%s\n",
 942                                    phydev->speed, phydev->duplex == DUPLEX_FULL ? "Full" : "Half");
 943                else
 944                        netdev_info(netdev, "Link is down\n");
 945        }
 946}
 947
 948static int octeon_mgmt_init_phy(struct net_device *netdev)
 949{
 950        struct octeon_mgmt *p = netdev_priv(netdev);
 951        struct phy_device *phydev = NULL;
 952
 953        if (octeon_is_simulation() || p->phy_np == NULL) {
 954                /* No PHYs in the simulator. */
 955                netif_carrier_on(netdev);
 956                return 0;
 957        }
 958
 959        phydev = of_phy_connect(netdev, p->phy_np,
 960                                octeon_mgmt_adjust_link, 0,
 961                                PHY_INTERFACE_MODE_MII);
 962
 963        if (!phydev)
 964                return -EPROBE_DEFER;
 965
 966        return 0;
 967}
 968
 969static int octeon_mgmt_open(struct net_device *netdev)
 970{
 971        struct octeon_mgmt *p = netdev_priv(netdev);
 972        union cvmx_mixx_ctl mix_ctl;
 973        union cvmx_agl_gmx_inf_mode agl_gmx_inf_mode;
 974        union cvmx_mixx_oring1 oring1;
 975        union cvmx_mixx_iring1 iring1;
 976        union cvmx_agl_gmx_rxx_frm_ctl rxx_frm_ctl;
 977        union cvmx_mixx_irhwm mix_irhwm;
 978        union cvmx_mixx_orhwm mix_orhwm;
 979        union cvmx_mixx_intena mix_intena;
 980        struct sockaddr sa;
 981
 982        /* Allocate ring buffers.  */
 983        p->tx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
 984                             GFP_KERNEL);
 985        if (!p->tx_ring)
 986                return -ENOMEM;
 987        p->tx_ring_handle =
 988                dma_map_single(p->dev, p->tx_ring,
 989                               ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
 990                               DMA_BIDIRECTIONAL);
 991        p->tx_next = 0;
 992        p->tx_next_clean = 0;
 993        p->tx_current_fill = 0;
 994
 995
 996        p->rx_ring = kzalloc(ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
 997                             GFP_KERNEL);
 998        if (!p->rx_ring)
 999                goto err_nomem;
1000        p->rx_ring_handle =
1001                dma_map_single(p->dev, p->rx_ring,
1002                               ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
1003                               DMA_BIDIRECTIONAL);
1004
1005        p->rx_next = 0;
1006        p->rx_next_fill = 0;
1007        p->rx_current_fill = 0;
1008
1009        octeon_mgmt_reset_hw(p);
1010
1011        mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
1012
1013        /* Bring it out of reset if needed. */
1014        if (mix_ctl.s.reset) {
1015                mix_ctl.s.reset = 0;
1016                cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
1017                do {
1018                        mix_ctl.u64 = cvmx_read_csr(p->mix + MIX_CTL);
1019                } while (mix_ctl.s.reset);
1020        }
1021
1022        if (OCTEON_IS_MODEL(OCTEON_CN5XXX)) {
1023                agl_gmx_inf_mode.u64 = 0;
1024                agl_gmx_inf_mode.s.en = 1;
1025                cvmx_write_csr(CVMX_AGL_GMX_INF_MODE, agl_gmx_inf_mode.u64);
1026        }
1027        if (OCTEON_IS_MODEL(OCTEON_CN56XX_PASS1_X)
1028                || OCTEON_IS_MODEL(OCTEON_CN52XX_PASS1_X)) {
1029                /* Force compensation values, as they are not
1030                 * determined properly by HW
1031                 */
1032                union cvmx_agl_gmx_drv_ctl drv_ctl;
1033
1034                drv_ctl.u64 = cvmx_read_csr(CVMX_AGL_GMX_DRV_CTL);
1035                if (p->port) {
1036                        drv_ctl.s.byp_en1 = 1;
1037                        drv_ctl.s.nctl1 = 6;
1038                        drv_ctl.s.pctl1 = 6;
1039                } else {
1040                        drv_ctl.s.byp_en = 1;
1041                        drv_ctl.s.nctl = 6;
1042                        drv_ctl.s.pctl = 6;
1043                }
1044                cvmx_write_csr(CVMX_AGL_GMX_DRV_CTL, drv_ctl.u64);
1045        }
1046
1047        oring1.u64 = 0;
1048        oring1.s.obase = p->tx_ring_handle >> 3;
1049        oring1.s.osize = OCTEON_MGMT_TX_RING_SIZE;
1050        cvmx_write_csr(p->mix + MIX_ORING1, oring1.u64);
1051
1052        iring1.u64 = 0;
1053        iring1.s.ibase = p->rx_ring_handle >> 3;
1054        iring1.s.isize = OCTEON_MGMT_RX_RING_SIZE;
1055        cvmx_write_csr(p->mix + MIX_IRING1, iring1.u64);
1056
1057        memcpy(sa.sa_data, netdev->dev_addr, ETH_ALEN);
1058        octeon_mgmt_set_mac_address(netdev, &sa);
1059
1060        octeon_mgmt_change_mtu(netdev, netdev->mtu);
1061
1062        /* Enable the port HW. Packets are not allowed until
1063         * cvmx_mgmt_port_enable() is called.
1064         */
1065        mix_ctl.u64 = 0;
1066        mix_ctl.s.crc_strip = 1;    /* Strip the ending CRC */
1067        mix_ctl.s.en = 1;           /* Enable the port */
1068        mix_ctl.s.nbtarb = 0;       /* Arbitration mode */
1069        /* MII CB-request FIFO programmable high watermark */
1070        mix_ctl.s.mrq_hwm = 1;
1071#ifdef __LITTLE_ENDIAN
1072        mix_ctl.s.lendian = 1;
1073#endif
1074        cvmx_write_csr(p->mix + MIX_CTL, mix_ctl.u64);
1075
1076        /* Read the PHY to find the mode of the interface. */
1077        if (octeon_mgmt_init_phy(netdev)) {
1078                dev_err(p->dev, "Cannot initialize PHY on MIX%d.\n", p->port);
1079                goto err_noirq;
1080        }
1081
1082        /* Set the mode of the interface, RGMII/MII. */
1083        if (OCTEON_IS_MODEL(OCTEON_CN6XXX) && netdev->phydev) {
1084                union cvmx_agl_prtx_ctl agl_prtx_ctl;
1085                int rgmii_mode =
1086                        (linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT,
1087                                           netdev->phydev->supported) |
1088                         linkmode_test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT,
1089                                           netdev->phydev->supported)) != 0;
1090
1091                agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1092                agl_prtx_ctl.s.mode = rgmii_mode ? 0 : 1;
1093                cvmx_write_csr(p->agl_prt_ctl,  agl_prtx_ctl.u64);
1094
1095                /* MII clocks counts are based on the 125Mhz
1096                 * reference, which has an 8nS period. So our delays
1097                 * need to be multiplied by this factor.
1098                 */
1099#define NS_PER_PHY_CLK 8
1100
1101                /* Take the DLL and clock tree out of reset */
1102                agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1103                agl_prtx_ctl.s.clkrst = 0;
1104                if (rgmii_mode) {
1105                        agl_prtx_ctl.s.dllrst = 0;
1106                        agl_prtx_ctl.s.clktx_byp = 0;
1107                }
1108                cvmx_write_csr(p->agl_prt_ctl,  agl_prtx_ctl.u64);
1109                cvmx_read_csr(p->agl_prt_ctl); /* Force write out before wait */
1110
1111                /* Wait for the DLL to lock. External 125 MHz
1112                 * reference clock must be stable at this point.
1113                 */
1114                ndelay(256 * NS_PER_PHY_CLK);
1115
1116                /* Enable the interface */
1117                agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1118                agl_prtx_ctl.s.enable = 1;
1119                cvmx_write_csr(p->agl_prt_ctl, agl_prtx_ctl.u64);
1120
1121                /* Read the value back to force the previous write */
1122                agl_prtx_ctl.u64 = cvmx_read_csr(p->agl_prt_ctl);
1123
1124                /* Enable the compensation controller */
1125                agl_prtx_ctl.s.comp = 1;
1126                agl_prtx_ctl.s.drv_byp = 0;
1127                cvmx_write_csr(p->agl_prt_ctl,  agl_prtx_ctl.u64);
1128                /* Force write out before wait. */
1129                cvmx_read_csr(p->agl_prt_ctl);
1130
1131                /* For compensation state to lock. */
1132                ndelay(1040 * NS_PER_PHY_CLK);
1133
1134                /* Default Interframe Gaps are too small.  Recommended
1135                 * workaround is.
1136                 *
1137                 * AGL_GMX_TX_IFG[IFG1]=14
1138                 * AGL_GMX_TX_IFG[IFG2]=10
1139                 */
1140                cvmx_write_csr(CVMX_AGL_GMX_TX_IFG, 0xae);
1141        }
1142
1143        octeon_mgmt_rx_fill_ring(netdev);
1144
1145        /* Clear statistics. */
1146        /* Clear on read. */
1147        cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_CTL, 1);
1148        cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_DRP, 0);
1149        cvmx_write_csr(p->agl + AGL_GMX_RX_STATS_PKTS_BAD, 0);
1150
1151        cvmx_write_csr(p->agl + AGL_GMX_TX_STATS_CTL, 1);
1152        cvmx_write_csr(p->agl + AGL_GMX_TX_STAT0, 0);
1153        cvmx_write_csr(p->agl + AGL_GMX_TX_STAT1, 0);
1154
1155        /* Clear any pending interrupts */
1156        cvmx_write_csr(p->mix + MIX_ISR, cvmx_read_csr(p->mix + MIX_ISR));
1157
1158        if (request_irq(p->irq, octeon_mgmt_interrupt, 0, netdev->name,
1159                        netdev)) {
1160                dev_err(p->dev, "request_irq(%d) failed.\n", p->irq);
1161                goto err_noirq;
1162        }
1163
1164        /* Interrupt every single RX packet */
1165        mix_irhwm.u64 = 0;
1166        mix_irhwm.s.irhwm = 0;
1167        cvmx_write_csr(p->mix + MIX_IRHWM, mix_irhwm.u64);
1168
1169        /* Interrupt when we have 1 or more packets to clean.  */
1170        mix_orhwm.u64 = 0;
1171        mix_orhwm.s.orhwm = 0;
1172        cvmx_write_csr(p->mix + MIX_ORHWM, mix_orhwm.u64);
1173
1174        /* Enable receive and transmit interrupts */
1175        mix_intena.u64 = 0;
1176        mix_intena.s.ithena = 1;
1177        mix_intena.s.othena = 1;
1178        cvmx_write_csr(p->mix + MIX_INTENA, mix_intena.u64);
1179
1180        /* Enable packet I/O. */
1181
1182        rxx_frm_ctl.u64 = 0;
1183        rxx_frm_ctl.s.ptp_mode = p->has_rx_tstamp ? 1 : 0;
1184        rxx_frm_ctl.s.pre_align = 1;
1185        /* When set, disables the length check for non-min sized pkts
1186         * with padding in the client data.
1187         */
1188        rxx_frm_ctl.s.pad_len = 1;
1189        /* When set, disables the length check for VLAN pkts */
1190        rxx_frm_ctl.s.vlan_len = 1;
1191        /* When set, PREAMBLE checking is  less strict */
1192        rxx_frm_ctl.s.pre_free = 1;
1193        /* Control Pause Frames can match station SMAC */
1194        rxx_frm_ctl.s.ctl_smac = 0;
1195        /* Control Pause Frames can match globally assign Multicast address */
1196        rxx_frm_ctl.s.ctl_mcst = 1;
1197        /* Forward pause information to TX block */
1198        rxx_frm_ctl.s.ctl_bck = 1;
1199        /* Drop Control Pause Frames */
1200        rxx_frm_ctl.s.ctl_drp = 1;
1201        /* Strip off the preamble */
1202        rxx_frm_ctl.s.pre_strp = 1;
1203        /* This port is configured to send PREAMBLE+SFD to begin every
1204         * frame.  GMX checks that the PREAMBLE is sent correctly.
1205         */
1206        rxx_frm_ctl.s.pre_chk = 1;
1207        cvmx_write_csr(p->agl + AGL_GMX_RX_FRM_CTL, rxx_frm_ctl.u64);
1208
1209        /* Configure the port duplex, speed and enables */
1210        octeon_mgmt_disable_link(p);
1211        if (netdev->phydev)
1212                octeon_mgmt_update_link(p);
1213        octeon_mgmt_enable_link(p);
1214
1215        p->last_link = 0;
1216        p->last_speed = 0;
1217        /* PHY is not present in simulator. The carrier is enabled
1218         * while initializing the phy for simulator, leave it enabled.
1219         */
1220        if (netdev->phydev) {
1221                netif_carrier_off(netdev);
1222                phy_start(netdev->phydev);
1223        }
1224
1225        netif_wake_queue(netdev);
1226        napi_enable(&p->napi);
1227
1228        return 0;
1229err_noirq:
1230        octeon_mgmt_reset_hw(p);
1231        dma_unmap_single(p->dev, p->rx_ring_handle,
1232                         ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
1233                         DMA_BIDIRECTIONAL);
1234        kfree(p->rx_ring);
1235err_nomem:
1236        dma_unmap_single(p->dev, p->tx_ring_handle,
1237                         ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
1238                         DMA_BIDIRECTIONAL);
1239        kfree(p->tx_ring);
1240        return -ENOMEM;
1241}
1242
1243static int octeon_mgmt_stop(struct net_device *netdev)
1244{
1245        struct octeon_mgmt *p = netdev_priv(netdev);
1246
1247        napi_disable(&p->napi);
1248        netif_stop_queue(netdev);
1249
1250        if (netdev->phydev) {
1251                phy_stop(netdev->phydev);
1252                phy_disconnect(netdev->phydev);
1253        }
1254
1255        netif_carrier_off(netdev);
1256
1257        octeon_mgmt_reset_hw(p);
1258
1259        free_irq(p->irq, netdev);
1260
1261        /* dma_unmap is a nop on Octeon, so just free everything.  */
1262        skb_queue_purge(&p->tx_list);
1263        skb_queue_purge(&p->rx_list);
1264
1265        dma_unmap_single(p->dev, p->rx_ring_handle,
1266                         ring_size_to_bytes(OCTEON_MGMT_RX_RING_SIZE),
1267                         DMA_BIDIRECTIONAL);
1268        kfree(p->rx_ring);
1269
1270        dma_unmap_single(p->dev, p->tx_ring_handle,
1271                         ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
1272                         DMA_BIDIRECTIONAL);
1273        kfree(p->tx_ring);
1274
1275        return 0;
1276}
1277
1278static netdev_tx_t
1279octeon_mgmt_xmit(struct sk_buff *skb, struct net_device *netdev)
1280{
1281        struct octeon_mgmt *p = netdev_priv(netdev);
1282        union mgmt_port_ring_entry re;
1283        unsigned long flags;
1284        netdev_tx_t rv = NETDEV_TX_BUSY;
1285
1286        re.d64 = 0;
1287        re.s.tstamp = ((skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) != 0);
1288        re.s.len = skb->len;
1289        re.s.addr = dma_map_single(p->dev, skb->data,
1290                                   skb->len,
1291                                   DMA_TO_DEVICE);
1292
1293        spin_lock_irqsave(&p->tx_list.lock, flags);
1294
1295        if (unlikely(p->tx_current_fill >= ring_max_fill(OCTEON_MGMT_TX_RING_SIZE) - 1)) {
1296                spin_unlock_irqrestore(&p->tx_list.lock, flags);
1297                netif_stop_queue(netdev);
1298                spin_lock_irqsave(&p->tx_list.lock, flags);
1299        }
1300
1301        if (unlikely(p->tx_current_fill >=
1302                     ring_max_fill(OCTEON_MGMT_TX_RING_SIZE))) {
1303                spin_unlock_irqrestore(&p->tx_list.lock, flags);
1304                dma_unmap_single(p->dev, re.s.addr, re.s.len,
1305                                 DMA_TO_DEVICE);
1306                goto out;
1307        }
1308
1309        __skb_queue_tail(&p->tx_list, skb);
1310
1311        /* Put it in the ring.  */
1312        p->tx_ring[p->tx_next] = re.d64;
1313        p->tx_next = (p->tx_next + 1) % OCTEON_MGMT_TX_RING_SIZE;
1314        p->tx_current_fill++;
1315
1316        spin_unlock_irqrestore(&p->tx_list.lock, flags);
1317
1318        dma_sync_single_for_device(p->dev, p->tx_ring_handle,
1319                                   ring_size_to_bytes(OCTEON_MGMT_TX_RING_SIZE),
1320                                   DMA_BIDIRECTIONAL);
1321
1322        netdev->stats.tx_packets++;
1323        netdev->stats.tx_bytes += skb->len;
1324
1325        /* Ring the bell.  */
1326        cvmx_write_csr(p->mix + MIX_ORING2, 1);
1327
1328        netif_trans_update(netdev);
1329        rv = NETDEV_TX_OK;
1330out:
1331        octeon_mgmt_update_tx_stats(netdev);
1332        return rv;
1333}
1334
1335#ifdef CONFIG_NET_POLL_CONTROLLER
1336static void octeon_mgmt_poll_controller(struct net_device *netdev)
1337{
1338        struct octeon_mgmt *p = netdev_priv(netdev);
1339
1340        octeon_mgmt_receive_packets(p, 16);
1341        octeon_mgmt_update_rx_stats(netdev);
1342}
1343#endif
1344
1345static void octeon_mgmt_get_drvinfo(struct net_device *netdev,
1346                                    struct ethtool_drvinfo *info)
1347{
1348        strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
1349}
1350
1351static int octeon_mgmt_nway_reset(struct net_device *dev)
1352{
1353        if (!capable(CAP_NET_ADMIN))
1354                return -EPERM;
1355
1356        if (dev->phydev)
1357                return phy_start_aneg(dev->phydev);
1358
1359        return -EOPNOTSUPP;
1360}
1361
1362static const struct ethtool_ops octeon_mgmt_ethtool_ops = {
1363        .get_drvinfo = octeon_mgmt_get_drvinfo,
1364        .nway_reset = octeon_mgmt_nway_reset,
1365        .get_link = ethtool_op_get_link,
1366        .get_link_ksettings = phy_ethtool_get_link_ksettings,
1367        .set_link_ksettings = phy_ethtool_set_link_ksettings,
1368};
1369
1370static const struct net_device_ops octeon_mgmt_ops = {
1371        .ndo_open =                     octeon_mgmt_open,
1372        .ndo_stop =                     octeon_mgmt_stop,
1373        .ndo_start_xmit =               octeon_mgmt_xmit,
1374        .ndo_set_rx_mode =              octeon_mgmt_set_rx_filtering,
1375        .ndo_set_mac_address =          octeon_mgmt_set_mac_address,
1376        .ndo_do_ioctl =                 octeon_mgmt_ioctl,
1377        .ndo_change_mtu =               octeon_mgmt_change_mtu,
1378#ifdef CONFIG_NET_POLL_CONTROLLER
1379        .ndo_poll_controller =          octeon_mgmt_poll_controller,
1380#endif
1381};
1382
1383static int octeon_mgmt_probe(struct platform_device *pdev)
1384{
1385        struct net_device *netdev;
1386        struct octeon_mgmt *p;
1387        const __be32 *data;
1388        struct resource *res_mix;
1389        struct resource *res_agl;
1390        struct resource *res_agl_prt_ctl;
1391        int len;
1392        int result;
1393
1394        netdev = alloc_etherdev(sizeof(struct octeon_mgmt));
1395        if (netdev == NULL)
1396                return -ENOMEM;
1397
1398        SET_NETDEV_DEV(netdev, &pdev->dev);
1399
1400        platform_set_drvdata(pdev, netdev);
1401        p = netdev_priv(netdev);
1402        netif_napi_add(netdev, &p->napi, octeon_mgmt_napi_poll,
1403                       OCTEON_MGMT_NAPI_WEIGHT);
1404
1405        p->netdev = netdev;
1406        p->dev = &pdev->dev;
1407        p->has_rx_tstamp = false;
1408
1409        data = of_get_property(pdev->dev.of_node, "cell-index", &len);
1410        if (data && len == sizeof(*data)) {
1411                p->port = be32_to_cpup(data);
1412        } else {
1413                dev_err(&pdev->dev, "no 'cell-index' property\n");
1414                result = -ENXIO;
1415                goto err;
1416        }
1417
1418        snprintf(netdev->name, IFNAMSIZ, "mgmt%d", p->port);
1419
1420        result = platform_get_irq(pdev, 0);
1421        if (result < 0)
1422                goto err;
1423
1424        p->irq = result;
1425
1426        res_mix = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1427        if (res_mix == NULL) {
1428                dev_err(&pdev->dev, "no 'reg' resource\n");
1429                result = -ENXIO;
1430                goto err;
1431        }
1432
1433        res_agl = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1434        if (res_agl == NULL) {
1435                dev_err(&pdev->dev, "no 'reg' resource\n");
1436                result = -ENXIO;
1437                goto err;
1438        }
1439
1440        res_agl_prt_ctl = platform_get_resource(pdev, IORESOURCE_MEM, 3);
1441        if (res_agl_prt_ctl == NULL) {
1442                dev_err(&pdev->dev, "no 'reg' resource\n");
1443                result = -ENXIO;
1444                goto err;
1445        }
1446
1447        p->mix_phys = res_mix->start;
1448        p->mix_size = resource_size(res_mix);
1449        p->agl_phys = res_agl->start;
1450        p->agl_size = resource_size(res_agl);
1451        p->agl_prt_ctl_phys = res_agl_prt_ctl->start;
1452        p->agl_prt_ctl_size = resource_size(res_agl_prt_ctl);
1453
1454
1455        if (!devm_request_mem_region(&pdev->dev, p->mix_phys, p->mix_size,
1456                                     res_mix->name)) {
1457                dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1458                        res_mix->name);
1459                result = -ENXIO;
1460                goto err;
1461        }
1462
1463        if (!devm_request_mem_region(&pdev->dev, p->agl_phys, p->agl_size,
1464                                     res_agl->name)) {
1465                result = -ENXIO;
1466                dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1467                        res_agl->name);
1468                goto err;
1469        }
1470
1471        if (!devm_request_mem_region(&pdev->dev, p->agl_prt_ctl_phys,
1472                                     p->agl_prt_ctl_size, res_agl_prt_ctl->name)) {
1473                result = -ENXIO;
1474                dev_err(&pdev->dev, "request_mem_region (%s) failed\n",
1475                        res_agl_prt_ctl->name);
1476                goto err;
1477        }
1478
1479        p->mix = (u64)devm_ioremap(&pdev->dev, p->mix_phys, p->mix_size);
1480        p->agl = (u64)devm_ioremap(&pdev->dev, p->agl_phys, p->agl_size);
1481        p->agl_prt_ctl = (u64)devm_ioremap(&pdev->dev, p->agl_prt_ctl_phys,
1482                                           p->agl_prt_ctl_size);
1483        if (!p->mix || !p->agl || !p->agl_prt_ctl) {
1484                dev_err(&pdev->dev, "failed to map I/O memory\n");
1485                result = -ENOMEM;
1486                goto err;
1487        }
1488
1489        spin_lock_init(&p->lock);
1490
1491        skb_queue_head_init(&p->tx_list);
1492        skb_queue_head_init(&p->rx_list);
1493        tasklet_setup(&p->tx_clean_tasklet,
1494                      octeon_mgmt_clean_tx_tasklet);
1495
1496        netdev->priv_flags |= IFF_UNICAST_FLT;
1497
1498        netdev->netdev_ops = &octeon_mgmt_ops;
1499        netdev->ethtool_ops = &octeon_mgmt_ethtool_ops;
1500
1501        netdev->min_mtu = 64 - OCTEON_MGMT_RX_HEADROOM;
1502        netdev->max_mtu = 16383 - OCTEON_MGMT_RX_HEADROOM - VLAN_HLEN;
1503
1504        result = of_get_mac_address(pdev->dev.of_node, netdev->dev_addr);
1505        if (result)
1506                eth_hw_addr_random(netdev);
1507
1508        p->phy_np = of_parse_phandle(pdev->dev.of_node, "phy-handle", 0);
1509
1510        result = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
1511        if (result)
1512                goto err;
1513
1514        netif_carrier_off(netdev);
1515        result = register_netdev(netdev);
1516        if (result)
1517                goto err;
1518
1519        return 0;
1520
1521err:
1522        of_node_put(p->phy_np);
1523        free_netdev(netdev);
1524        return result;
1525}
1526
1527static int octeon_mgmt_remove(struct platform_device *pdev)
1528{
1529        struct net_device *netdev = platform_get_drvdata(pdev);
1530        struct octeon_mgmt *p = netdev_priv(netdev);
1531
1532        unregister_netdev(netdev);
1533        of_node_put(p->phy_np);
1534        free_netdev(netdev);
1535        return 0;
1536}
1537
1538static const struct of_device_id octeon_mgmt_match[] = {
1539        {
1540                .compatible = "cavium,octeon-5750-mix",
1541        },
1542        {},
1543};
1544MODULE_DEVICE_TABLE(of, octeon_mgmt_match);
1545
1546static struct platform_driver octeon_mgmt_driver = {
1547        .driver = {
1548                .name           = "octeon_mgmt",
1549                .of_match_table = octeon_mgmt_match,
1550        },
1551        .probe          = octeon_mgmt_probe,
1552        .remove         = octeon_mgmt_remove,
1553};
1554
1555module_platform_driver(octeon_mgmt_driver);
1556
1557MODULE_SOFTDEP("pre: mdio-cavium");
1558MODULE_DESCRIPTION(DRV_DESCRIPTION);
1559MODULE_AUTHOR("David Daney");
1560MODULE_LICENSE("GPL");
1561